dsi_pll_7nm.c 55 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "%s: " fmt, __func__
  6. #include <linux/kernel.h>
  7. #include <linux/err.h>
  8. #include <linux/iopoll.h>
  9. #include <linux/delay.h>
  10. #include "dsi_pll.h"
  11. #include "pll_drv.h"
  12. #include <dt-bindings/clock/mdss-10nm-pll-clk.h>
  13. #define VCO_DELAY_USEC 1
  14. #define MHZ_250 250000000UL
  15. #define MHZ_500 500000000UL
  16. #define MHZ_1000 1000000000UL
  17. #define MHZ_1100 1100000000UL
  18. #define MHZ_1900 1900000000UL
  19. #define MHZ_3000 3000000000UL
  20. /* Register Offsets from PLL base address */
  21. #define PLL_ANALOG_CONTROLS_ONE 0x0000
  22. #define PLL_ANALOG_CONTROLS_TWO 0x0004
  23. #define PLL_INT_LOOP_SETTINGS 0x0008
  24. #define PLL_INT_LOOP_SETTINGS_TWO 0x000C
  25. #define PLL_ANALOG_CONTROLS_THREE 0x0010
  26. #define PLL_ANALOG_CONTROLS_FOUR 0x0014
  27. #define PLL_ANALOG_CONTROLS_FIVE 0x0018
  28. #define PLL_INT_LOOP_CONTROLS 0x001C
  29. #define PLL_DSM_DIVIDER 0x0020
  30. #define PLL_FEEDBACK_DIVIDER 0x0024
  31. #define PLL_SYSTEM_MUXES 0x0028
  32. #define PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x002C
  33. #define PLL_CMODE 0x0030
  34. #define PLL_PSM_CTRL 0x0034
  35. #define PLL_RSM_CTRL 0x0038
  36. #define PLL_VCO_TUNE_MAP 0x003C
  37. #define PLL_PLL_CNTRL 0x0040
  38. #define PLL_CALIBRATION_SETTINGS 0x0044
  39. #define PLL_BAND_SEL_CAL_TIMER_LOW 0x0048
  40. #define PLL_BAND_SEL_CAL_TIMER_HIGH 0x004C
  41. #define PLL_BAND_SEL_CAL_SETTINGS 0x0050
  42. #define PLL_BAND_SEL_MIN 0x0054
  43. #define PLL_BAND_SEL_MAX 0x0058
  44. #define PLL_BAND_SEL_PFILT 0x005C
  45. #define PLL_BAND_SEL_IFILT 0x0060
  46. #define PLL_BAND_SEL_CAL_SETTINGS_TWO 0x0064
  47. #define PLL_BAND_SEL_CAL_SETTINGS_THREE 0x0068
  48. #define PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x006C
  49. #define PLL_BAND_SEL_ICODE_HIGH 0x0070
  50. #define PLL_BAND_SEL_ICODE_LOW 0x0074
  51. #define PLL_FREQ_DETECT_SETTINGS_ONE 0x0078
  52. #define PLL_FREQ_DETECT_THRESH 0x007C
  53. #define PLL_FREQ_DET_REFCLK_HIGH 0x0080
  54. #define PLL_FREQ_DET_REFCLK_LOW 0x0084
  55. #define PLL_FREQ_DET_PLLCLK_HIGH 0x0088
  56. #define PLL_FREQ_DET_PLLCLK_LOW 0x008C
  57. #define PLL_PFILT 0x0090
  58. #define PLL_IFILT 0x0094
  59. #define PLL_PLL_GAIN 0x0098
  60. #define PLL_ICODE_LOW 0x009C
  61. #define PLL_ICODE_HIGH 0x00A0
  62. #define PLL_LOCKDET 0x00A4
  63. #define PLL_OUTDIV 0x00A8
  64. #define PLL_FASTLOCK_CONTROL 0x00AC
  65. #define PLL_PASS_OUT_OVERRIDE_ONE 0x00B0
  66. #define PLL_PASS_OUT_OVERRIDE_TWO 0x00B4
  67. #define PLL_CORE_OVERRIDE 0x00B8
  68. #define PLL_CORE_INPUT_OVERRIDE 0x00BC
  69. #define PLL_RATE_CHANGE 0x00C0
  70. #define PLL_PLL_DIGITAL_TIMERS 0x00C4
  71. #define PLL_PLL_DIGITAL_TIMERS_TWO 0x00C8
  72. #define PLL_DECIMAL_DIV_START 0x00CC
  73. #define PLL_FRAC_DIV_START_LOW 0x00D0
  74. #define PLL_FRAC_DIV_START_MID 0x00D4
  75. #define PLL_FRAC_DIV_START_HIGH 0x00D8
  76. #define PLL_DEC_FRAC_MUXES 0x00DC
  77. #define PLL_DECIMAL_DIV_START_1 0x00E0
  78. #define PLL_FRAC_DIV_START_LOW_1 0x00E4
  79. #define PLL_FRAC_DIV_START_MID_1 0x00E8
  80. #define PLL_FRAC_DIV_START_HIGH_1 0x00EC
  81. #define PLL_DECIMAL_DIV_START_2 0x00F0
  82. #define PLL_FRAC_DIV_START_LOW_2 0x00F4
  83. #define PLL_FRAC_DIV_START_MID_2 0x00F8
  84. #define PLL_FRAC_DIV_START_HIGH_2 0x00FC
  85. #define PLL_MASH_CONTROL 0x0100
  86. #define PLL_SSC_STEPSIZE_LOW 0x0104
  87. #define PLL_SSC_STEPSIZE_HIGH 0x0108
  88. #define PLL_SSC_DIV_PER_LOW 0x010C
  89. #define PLL_SSC_DIV_PER_HIGH 0x0110
  90. #define PLL_SSC_ADJPER_LOW 0x0114
  91. #define PLL_SSC_ADJPER_HIGH 0x0118
  92. #define PLL_SSC_MUX_CONTROL 0x011C
  93. #define PLL_SSC_STEPSIZE_LOW_1 0x0120
  94. #define PLL_SSC_STEPSIZE_HIGH_1 0x0124
  95. #define PLL_SSC_DIV_PER_LOW_1 0x0128
  96. #define PLL_SSC_DIV_PER_HIGH_1 0x012C
  97. #define PLL_SSC_ADJPER_LOW_1 0x0130
  98. #define PLL_SSC_ADJPER_HIGH_1 0x0134
  99. #define PLL_SSC_STEPSIZE_LOW_2 0x0138
  100. #define PLL_SSC_STEPSIZE_HIGH_2 0x013C
  101. #define PLL_SSC_DIV_PER_LOW_2 0x0140
  102. #define PLL_SSC_DIV_PER_HIGH_2 0x0144
  103. #define PLL_SSC_ADJPER_LOW_2 0x0148
  104. #define PLL_SSC_ADJPER_HIGH_2 0x014C
  105. #define PLL_SSC_CONTROL 0x0150
  106. #define PLL_PLL_OUTDIV_RATE 0x0154
  107. #define PLL_PLL_LOCKDET_RATE_1 0x0158
  108. #define PLL_PLL_LOCKDET_RATE_2 0x015C
  109. #define PLL_PLL_PROP_GAIN_RATE_1 0x0160
  110. #define PLL_PLL_PROP_GAIN_RATE_2 0x0164
  111. #define PLL_PLL_BAND_SEL_RATE_1 0x0168
  112. #define PLL_PLL_BAND_SEL_RATE_2 0x016C
  113. #define PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0170
  114. #define PLL_PLL_INT_GAIN_IFILT_BAND_2 0x0174
  115. #define PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x0178
  116. #define PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x017C
  117. #define PLL_PLL_FASTLOCK_EN_BAND 0x0180
  118. #define PLL_FREQ_TUNE_ACCUM_INIT_MID 0x0184
  119. #define PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x0188
  120. #define PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x018C
  121. #define PLL_PLL_LOCK_OVERRIDE 0x0190
  122. #define PLL_PLL_LOCK_DELAY 0x0194
  123. #define PLL_PLL_LOCK_MIN_DELAY 0x0198
  124. #define PLL_CLOCK_INVERTERS 0x019C
  125. #define PLL_SPARE_AND_JPC_OVERRIDES 0x01A0
  126. #define PLL_BIAS_CONTROL_1 0x01A4
  127. #define PLL_BIAS_CONTROL_2 0x01A8
  128. #define PLL_ALOG_OBSV_BUS_CTRL_1 0x01AC
  129. #define PLL_COMMON_STATUS_ONE 0x01B0
  130. #define PLL_COMMON_STATUS_TWO 0x01B4
  131. #define PLL_BAND_SEL_CAL 0x01B8
  132. #define PLL_ICODE_ACCUM_STATUS_LOW 0x01BC
  133. #define PLL_ICODE_ACCUM_STATUS_HIGH 0x01C0
  134. #define PLL_FD_OUT_LOW 0x01C4
  135. #define PLL_FD_OUT_HIGH 0x01C8
  136. #define PLL_ALOG_OBSV_BUS_STATUS_1 0x01CC
  137. #define PLL_PLL_MISC_CONFIG 0x01D0
  138. #define PLL_FLL_CONFIG 0x01D4
  139. #define PLL_FLL_FREQ_ACQ_TIME 0x01D8
  140. #define PLL_FLL_CODE0 0x01DC
  141. #define PLL_FLL_CODE1 0x01E0
  142. #define PLL_FLL_GAIN0 0x01E4
  143. #define PLL_FLL_GAIN1 0x01E8
  144. #define PLL_SW_RESET 0x01EC
  145. #define PLL_FAST_PWRUP 0x01F0
  146. #define PLL_LOCKTIME0 0x01F4
  147. #define PLL_LOCKTIME1 0x01F8
  148. #define PLL_DEBUG_BUS_SEL 0x01FC
  149. #define PLL_DEBUG_BUS0 0x0200
  150. #define PLL_DEBUG_BUS1 0x0204
  151. #define PLL_DEBUG_BUS2 0x0208
  152. #define PLL_DEBUG_BUS3 0x020C
  153. #define PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x0210
  154. #define PLL_VCO_CONFIG 0x0214
  155. #define PLL_VCO_CAL_CODE1_MODE0_STATUS 0x0218
  156. #define PLL_VCO_CAL_CODE1_MODE1_STATUS 0x021C
  157. #define PLL_RESET_SM_STATUS 0x0220
  158. #define PLL_TDC_OFFSET 0x0224
  159. #define PLL_PS3_PWRDOWN_CONTROLS 0x0228
  160. #define PLL_PS4_PWRDOWN_CONTROLS 0x022C
  161. #define PLL_PLL_RST_CONTROLS 0x0230
  162. #define PLL_GEAR_BAND_SELECT_CONTROLS 0x0234
  163. #define PLL_PSM_CLK_CONTROLS 0x0238
  164. #define PLL_SYSTEM_MUXES_2 0x023C
  165. #define PLL_VCO_CONFIG_1 0x0240
  166. #define PLL_VCO_CONFIG_2 0x0244
  167. #define PLL_CLOCK_INVERTERS_1 0x0248
  168. #define PLL_CLOCK_INVERTERS_2 0x024C
  169. #define PLL_CMODE_1 0x0250
  170. #define PLL_CMODE_2 0x0254
  171. #define PLL_ANALOG_CONTROLS_FIVE_1 0x0258
  172. #define PLL_ANALOG_CONTROLS_FIVE_2 0x025C
  173. #define PLL_PERF_OPTIMIZE 0x0260
  174. /* Register Offsets from PHY base address */
  175. #define PHY_CMN_CLK_CFG0 0x010
  176. #define PHY_CMN_CLK_CFG1 0x014
  177. #define PHY_CMN_RBUF_CTRL 0x01C
  178. #define PHY_CMN_CTRL_0 0x024
  179. #define PHY_CMN_CTRL_3 0x030
  180. #define PHY_CMN_PLL_CNTRL 0x03C
  181. #define PHY_CMN_GLBL_DIGTOP_SPARE4 0x128
  182. /* Bit definition of SSC control registers */
  183. #define SSC_CENTER BIT(0)
  184. #define SSC_EN BIT(1)
  185. #define SSC_FREQ_UPDATE BIT(2)
  186. #define SSC_FREQ_UPDATE_MUX BIT(3)
  187. #define SSC_UPDATE_SSC BIT(4)
  188. #define SSC_UPDATE_SSC_MUX BIT(5)
  189. #define SSC_START BIT(6)
  190. #define SSC_START_MUX BIT(7)
  191. enum {
  192. DSI_PLL_0,
  193. DSI_PLL_1,
  194. DSI_PLL_MAX
  195. };
  196. struct dsi_pll_regs {
  197. u32 pll_prop_gain_rate;
  198. u32 pll_lockdet_rate;
  199. u32 decimal_div_start;
  200. u32 frac_div_start_low;
  201. u32 frac_div_start_mid;
  202. u32 frac_div_start_high;
  203. u32 pll_clock_inverters;
  204. u32 ssc_stepsize_low;
  205. u32 ssc_stepsize_high;
  206. u32 ssc_div_per_low;
  207. u32 ssc_div_per_high;
  208. u32 ssc_adjper_low;
  209. u32 ssc_adjper_high;
  210. u32 ssc_control;
  211. };
  212. struct dsi_pll_config {
  213. u32 ref_freq;
  214. bool div_override;
  215. u32 output_div;
  216. bool ignore_frac;
  217. bool disable_prescaler;
  218. bool enable_ssc;
  219. bool ssc_center;
  220. u32 dec_bits;
  221. u32 frac_bits;
  222. u32 lock_timer;
  223. u32 ssc_freq;
  224. u32 ssc_offset;
  225. u32 ssc_adj_per;
  226. u32 thresh_cycles;
  227. u32 refclk_cycles;
  228. };
  229. struct dsi_pll_7nm {
  230. struct mdss_pll_resources *rsc;
  231. struct dsi_pll_config pll_configuration;
  232. struct dsi_pll_regs reg_setup;
  233. };
  234. static inline bool dsi_pll_7nm_is_hw_revision_v1(
  235. struct mdss_pll_resources *rsc)
  236. {
  237. return (rsc->pll_interface_type == MDSS_DSI_PLL_7NM) ? true : false;
  238. }
  239. static inline bool dsi_pll_7nm_is_hw_revision_v2(
  240. struct mdss_pll_resources *rsc)
  241. {
  242. return (rsc->pll_interface_type == MDSS_DSI_PLL_7NM_V2) ? true : false;
  243. }
  244. static inline bool dsi_pll_7nm_is_hw_revision_v4_1(
  245. struct mdss_pll_resources *rsc)
  246. {
  247. return (rsc->pll_interface_type == MDSS_DSI_PLL_7NM_V4_1) ?
  248. true : false;
  249. }
  250. static inline int pll_reg_read(void *context, unsigned int reg,
  251. unsigned int *val)
  252. {
  253. int rc = 0;
  254. u32 data;
  255. struct mdss_pll_resources *rsc = context;
  256. rc = mdss_pll_resource_enable(rsc, true);
  257. if (rc) {
  258. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  259. return rc;
  260. }
  261. /*
  262. * DSI PHY/PLL should be both powered on when reading PLL
  263. * registers. Since PHY power has been enabled in DSI PHY
  264. * driver, only PLL power is needed to enable here.
  265. */
  266. data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0);
  267. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data | BIT(5));
  268. ndelay(250);
  269. *val = MDSS_PLL_REG_R(rsc->pll_base, reg);
  270. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data);
  271. (void)mdss_pll_resource_enable(rsc, false);
  272. return rc;
  273. }
  274. static inline int pll_reg_write(void *context, unsigned int reg,
  275. unsigned int val)
  276. {
  277. int rc = 0;
  278. struct mdss_pll_resources *rsc = context;
  279. rc = mdss_pll_resource_enable(rsc, true);
  280. if (rc) {
  281. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  282. return rc;
  283. }
  284. MDSS_PLL_REG_W(rsc->pll_base, reg, val);
  285. (void)mdss_pll_resource_enable(rsc, false);
  286. return rc;
  287. }
  288. static inline int phy_reg_read(void *context, unsigned int reg,
  289. unsigned int *val)
  290. {
  291. int rc = 0;
  292. struct mdss_pll_resources *rsc = context;
  293. rc = mdss_pll_resource_enable(rsc, true);
  294. if (rc) {
  295. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  296. return rc;
  297. }
  298. *val = MDSS_PLL_REG_R(rsc->phy_base, reg);
  299. (void)mdss_pll_resource_enable(rsc, false);
  300. return rc;
  301. }
  302. static inline int phy_reg_write(void *context, unsigned int reg,
  303. unsigned int val)
  304. {
  305. int rc = 0;
  306. struct mdss_pll_resources *rsc = context;
  307. rc = mdss_pll_resource_enable(rsc, true);
  308. if (rc) {
  309. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  310. return rc;
  311. }
  312. MDSS_PLL_REG_W(rsc->phy_base, reg, val);
  313. (void)mdss_pll_resource_enable(rsc, false);
  314. return rc;
  315. }
  316. static inline int phy_reg_update_bits_sub(struct mdss_pll_resources *rsc,
  317. unsigned int reg, unsigned int mask, unsigned int val)
  318. {
  319. u32 reg_val;
  320. reg_val = MDSS_PLL_REG_R(rsc->phy_base, reg);
  321. reg_val &= ~mask;
  322. reg_val |= (val & mask);
  323. MDSS_PLL_REG_W(rsc->phy_base, reg, reg_val);
  324. return 0;
  325. }
  326. static inline int phy_reg_update_bits(void *context, unsigned int reg,
  327. unsigned int mask, unsigned int val)
  328. {
  329. int rc = 0;
  330. struct mdss_pll_resources *rsc = context;
  331. rc = mdss_pll_resource_enable(rsc, true);
  332. if (rc) {
  333. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  334. return rc;
  335. }
  336. rc = phy_reg_update_bits_sub(rsc, reg, mask, val);
  337. if (!rc && rsc->slave)
  338. rc = phy_reg_update_bits_sub(rsc->slave, reg, mask, val);
  339. (void)mdss_pll_resource_enable(rsc, false);
  340. return rc;
  341. }
  342. static inline int pclk_mux_read_sel(void *context, unsigned int reg,
  343. unsigned int *val)
  344. {
  345. int rc = 0;
  346. struct mdss_pll_resources *rsc = context;
  347. rc = mdss_pll_resource_enable(rsc, true);
  348. if (rc)
  349. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  350. else
  351. *val = (MDSS_PLL_REG_R(rsc->phy_base, reg) & 0x3);
  352. (void)mdss_pll_resource_enable(rsc, false);
  353. return rc;
  354. }
  355. static inline int pclk_mux_write_sel_sub(struct mdss_pll_resources *rsc,
  356. unsigned int reg, unsigned int val)
  357. {
  358. u32 reg_val;
  359. reg_val = MDSS_PLL_REG_R(rsc->phy_base, reg);
  360. reg_val &= ~0x03;
  361. reg_val |= val;
  362. MDSS_PLL_REG_W(rsc->phy_base, reg, reg_val);
  363. return 0;
  364. }
  365. static inline int pclk_mux_write_sel(void *context, unsigned int reg,
  366. unsigned int val)
  367. {
  368. int rc = 0;
  369. struct mdss_pll_resources *rsc = context;
  370. rc = mdss_pll_resource_enable(rsc, true);
  371. if (rc) {
  372. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  373. return rc;
  374. }
  375. rc = pclk_mux_write_sel_sub(rsc, reg, val);
  376. if (!rc && rsc->slave)
  377. rc = pclk_mux_write_sel_sub(rsc->slave, reg, val);
  378. (void)mdss_pll_resource_enable(rsc, false);
  379. /*
  380. * cache the current parent index for cases where parent
  381. * is not changing but rate is changing. In that case
  382. * clock framework won't call parent_set and hence dsiclk_sel
  383. * bit won't be programmed. e.g. dfps update use case.
  384. */
  385. rsc->cached_cfg1 = val;
  386. return rc;
  387. }
  388. static struct mdss_pll_resources *pll_rsc_db[DSI_PLL_MAX];
  389. static struct dsi_pll_7nm plls[DSI_PLL_MAX];
  390. static void dsi_pll_config_slave(struct mdss_pll_resources *rsc)
  391. {
  392. u32 reg;
  393. struct mdss_pll_resources *orsc = pll_rsc_db[DSI_PLL_1];
  394. if (!rsc)
  395. return;
  396. /* Only DSI PLL0 can act as a master */
  397. if (rsc->index != DSI_PLL_0)
  398. return;
  399. /* default configuration: source is either internal or ref clock */
  400. rsc->slave = NULL;
  401. if (!orsc) {
  402. pr_warn("slave PLL unavilable, assuming standalone config\n");
  403. return;
  404. }
  405. /* check to see if the source of DSI1 PLL bitclk is set to external */
  406. reg = MDSS_PLL_REG_R(orsc->phy_base, PHY_CMN_CLK_CFG1);
  407. reg &= (BIT(2) | BIT(3));
  408. if (reg == 0x04)
  409. rsc->slave = pll_rsc_db[DSI_PLL_1]; /* external source */
  410. pr_debug("Slave PLL %s\n", rsc->slave ? "configured" : "absent");
  411. }
  412. static void dsi_pll_setup_config(struct dsi_pll_7nm *pll,
  413. struct mdss_pll_resources *rsc)
  414. {
  415. struct dsi_pll_config *config = &pll->pll_configuration;
  416. config->ref_freq = 19200000;
  417. config->output_div = 1;
  418. config->dec_bits = 8;
  419. config->frac_bits = 18;
  420. config->lock_timer = 64;
  421. config->ssc_freq = 31500;
  422. config->ssc_offset = 4800;
  423. config->ssc_adj_per = 2;
  424. config->thresh_cycles = 32;
  425. config->refclk_cycles = 256;
  426. config->div_override = false;
  427. config->ignore_frac = false;
  428. config->disable_prescaler = false;
  429. config->enable_ssc = rsc->ssc_en;
  430. config->ssc_center = rsc->ssc_center;
  431. if (config->enable_ssc) {
  432. if (rsc->ssc_freq)
  433. config->ssc_freq = rsc->ssc_freq;
  434. if (rsc->ssc_ppm)
  435. config->ssc_offset = rsc->ssc_ppm;
  436. }
  437. dsi_pll_config_slave(rsc);
  438. }
  439. static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll,
  440. struct mdss_pll_resources *rsc)
  441. {
  442. struct dsi_pll_config *config = &pll->pll_configuration;
  443. struct dsi_pll_regs *regs = &pll->reg_setup;
  444. u64 fref = rsc->vco_ref_clk_rate;
  445. u64 pll_freq;
  446. u64 divider;
  447. u64 dec, dec_multiple;
  448. u32 frac;
  449. u64 multiplier;
  450. pll_freq = rsc->vco_current_rate;
  451. if (config->disable_prescaler)
  452. divider = fref;
  453. else
  454. divider = fref * 2;
  455. multiplier = 1 << config->frac_bits;
  456. dec_multiple = div_u64(pll_freq * multiplier, divider);
  457. div_u64_rem(dec_multiple, multiplier, &frac);
  458. dec = div_u64(dec_multiple, multiplier);
  459. switch (rsc->pll_interface_type) {
  460. case MDSS_DSI_PLL_7NM:
  461. regs->pll_clock_inverters = 0x0;
  462. break;
  463. case MDSS_DSI_PLL_7NM_V2:
  464. regs->pll_clock_inverters = 0x28;
  465. break;
  466. case MDSS_DSI_PLL_7NM_V4_1:
  467. default:
  468. if (pll_freq <= 1000000000)
  469. regs->pll_clock_inverters = 0xA0;
  470. else if (pll_freq <= 2500000000)
  471. regs->pll_clock_inverters = 0x20;
  472. else if (pll_freq <= 3020000000)
  473. regs->pll_clock_inverters = 0x00;
  474. else
  475. regs->pll_clock_inverters = 0x40;
  476. break;
  477. }
  478. regs->pll_lockdet_rate = config->lock_timer;
  479. regs->decimal_div_start = dec;
  480. regs->frac_div_start_low = (frac & 0xff);
  481. regs->frac_div_start_mid = (frac & 0xff00) >> 8;
  482. regs->frac_div_start_high = (frac & 0x30000) >> 16;
  483. }
  484. static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll,
  485. struct mdss_pll_resources *rsc)
  486. {
  487. struct dsi_pll_config *config = &pll->pll_configuration;
  488. struct dsi_pll_regs *regs = &pll->reg_setup;
  489. u32 ssc_per;
  490. u32 ssc_mod;
  491. u64 ssc_step_size;
  492. u64 frac;
  493. if (!config->enable_ssc) {
  494. pr_debug("SSC not enabled\n");
  495. return;
  496. }
  497. ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1;
  498. ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
  499. ssc_per -= ssc_mod;
  500. frac = regs->frac_div_start_low |
  501. (regs->frac_div_start_mid << 8) |
  502. (regs->frac_div_start_high << 16);
  503. ssc_step_size = regs->decimal_div_start;
  504. ssc_step_size *= (1 << config->frac_bits);
  505. ssc_step_size += frac;
  506. ssc_step_size *= config->ssc_offset;
  507. ssc_step_size *= (config->ssc_adj_per + 1);
  508. ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
  509. ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
  510. regs->ssc_div_per_low = ssc_per & 0xFF;
  511. regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
  512. regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
  513. regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
  514. regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
  515. regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
  516. regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
  517. pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
  518. regs->decimal_div_start, frac, config->frac_bits);
  519. pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
  520. ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
  521. }
  522. static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll,
  523. struct mdss_pll_resources *rsc)
  524. {
  525. void __iomem *pll_base = rsc->pll_base;
  526. struct dsi_pll_regs *regs = &pll->reg_setup;
  527. if (pll->pll_configuration.enable_ssc) {
  528. pr_debug("SSC is enabled\n");
  529. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_LOW_1,
  530. regs->ssc_stepsize_low);
  531. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_HIGH_1,
  532. regs->ssc_stepsize_high);
  533. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_LOW_1,
  534. regs->ssc_div_per_low);
  535. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_HIGH_1,
  536. regs->ssc_div_per_high);
  537. MDSS_PLL_REG_W(pll_base, PLL_SSC_ADJPER_LOW_1,
  538. regs->ssc_adjper_low);
  539. MDSS_PLL_REG_W(pll_base, PLL_SSC_ADJPER_HIGH_1,
  540. regs->ssc_adjper_high);
  541. MDSS_PLL_REG_W(pll_base, PLL_SSC_CONTROL,
  542. SSC_EN | regs->ssc_control);
  543. }
  544. }
  545. static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll,
  546. struct mdss_pll_resources *rsc)
  547. {
  548. void __iomem *pll_base = rsc->pll_base;
  549. u64 vco_rate = rsc->vco_current_rate;
  550. switch (rsc->pll_interface_type) {
  551. case MDSS_DSI_PLL_7NM:
  552. case MDSS_DSI_PLL_7NM_V2:
  553. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_1, 0x01);
  554. MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);
  555. break;
  556. case MDSS_DSI_PLL_7NM_V4_1:
  557. default:
  558. if (vco_rate < 3100000000)
  559. MDSS_PLL_REG_W(pll_base,
  560. PLL_ANALOG_CONTROLS_FIVE_1, 0x01);
  561. else
  562. MDSS_PLL_REG_W(pll_base,
  563. PLL_ANALOG_CONTROLS_FIVE_1, 0x03);
  564. if (vco_rate < 1520000000)
  565. MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08);
  566. else if (vco_rate < 2990000000)
  567. MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01);
  568. else
  569. MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);
  570. break;
  571. }
  572. if (dsi_pll_7nm_is_hw_revision_v1(rsc))
  573. MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x21);
  574. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE, 0x01);
  575. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_TWO, 0x03);
  576. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_THREE, 0x00);
  577. MDSS_PLL_REG_W(pll_base, PLL_DSM_DIVIDER, 0x00);
  578. MDSS_PLL_REG_W(pll_base, PLL_FEEDBACK_DIVIDER, 0x4e);
  579. MDSS_PLL_REG_W(pll_base, PLL_CALIBRATION_SETTINGS, 0x40);
  580. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
  581. MDSS_PLL_REG_W(pll_base, PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
  582. MDSS_PLL_REG_W(pll_base, PLL_OUTDIV, 0x00);
  583. MDSS_PLL_REG_W(pll_base, PLL_CORE_OVERRIDE, 0x00);
  584. MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
  585. MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
  586. MDSS_PLL_REG_W(pll_base, PLL_PLL_BAND_SEL_RATE_1, 0xc0);
  587. MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
  588. MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
  589. MDSS_PLL_REG_W(pll_base, PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
  590. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_OVERRIDE, 0x80);
  591. MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x29);
  592. MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x2f);
  593. MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x2a);
  594. switch (rsc->pll_interface_type) {
  595. case MDSS_DSI_PLL_7NM:
  596. MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x30);
  597. break;
  598. case MDSS_DSI_PLL_7NM_V2:
  599. MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x22);
  600. break;
  601. case MDSS_DSI_PLL_7NM_V4_1:
  602. default:
  603. MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x3F);
  604. break;
  605. }
  606. if (dsi_pll_7nm_is_hw_revision_v4_1(rsc))
  607. MDSS_PLL_REG_W(pll_base, PLL_PERF_OPTIMIZE, 0x22);
  608. }
  609. static void dsi_pll_init_val(struct mdss_pll_resources *rsc)
  610. {
  611. void __iomem *pll_base = rsc->pll_base;
  612. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_ONE, 0x00000000);
  613. MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_SETTINGS, 0x0000003F);
  614. MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_SETTINGS_TWO, 0x00000000);
  615. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FOUR, 0x00000000);
  616. MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_CONTROLS, 0x00000080);
  617. MDSS_PLL_REG_W(pll_base, PLL_SYSTEM_MUXES, 0x00000000);
  618. MDSS_PLL_REG_W(pll_base, PLL_FREQ_UPDATE_CONTROL_OVERRIDES, 0x00000000);
  619. MDSS_PLL_REG_W(pll_base, PLL_CMODE, 0x00000010);
  620. MDSS_PLL_REG_W(pll_base, PLL_PSM_CTRL, 0x00000020);
  621. MDSS_PLL_REG_W(pll_base, PLL_RSM_CTRL, 0x00000010);
  622. MDSS_PLL_REG_W(pll_base, PLL_VCO_TUNE_MAP, 0x00000002);
  623. MDSS_PLL_REG_W(pll_base, PLL_PLL_CNTRL, 0x0000001C);
  624. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_TIMER_LOW, 0x00000000);
  625. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_TIMER_HIGH, 0x00000002);
  626. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS, 0x00000020);
  627. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_MIN, 0x00000000);
  628. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_MAX, 0x000000FF);
  629. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_PFILT, 0x00000000);
  630. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_IFILT, 0x0000000A);
  631. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_TWO, 0x00000025);
  632. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_THREE, 0x000000BA);
  633. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_FOUR, 0x0000004F);
  634. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_ICODE_HIGH, 0x0000000A);
  635. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_ICODE_LOW, 0x00000000);
  636. MDSS_PLL_REG_W(pll_base, PLL_FREQ_DETECT_SETTINGS_ONE, 0x0000000C);
  637. MDSS_PLL_REG_W(pll_base, PLL_FREQ_DETECT_THRESH, 0x00000020);
  638. MDSS_PLL_REG_W(pll_base, PLL_FREQ_DET_REFCLK_HIGH, 0x00000000);
  639. MDSS_PLL_REG_W(pll_base, PLL_FREQ_DET_REFCLK_LOW, 0x000000FF);
  640. MDSS_PLL_REG_W(pll_base, PLL_FREQ_DET_PLLCLK_HIGH, 0x00000010);
  641. MDSS_PLL_REG_W(pll_base, PLL_FREQ_DET_PLLCLK_LOW, 0x00000046);
  642. MDSS_PLL_REG_W(pll_base, PLL_PLL_GAIN, 0x00000054);
  643. MDSS_PLL_REG_W(pll_base, PLL_ICODE_LOW, 0x00000000);
  644. MDSS_PLL_REG_W(pll_base, PLL_ICODE_HIGH, 0x00000000);
  645. MDSS_PLL_REG_W(pll_base, PLL_LOCKDET, 0x00000040);
  646. MDSS_PLL_REG_W(pll_base, PLL_FASTLOCK_CONTROL, 0x00000004);
  647. MDSS_PLL_REG_W(pll_base, PLL_PASS_OUT_OVERRIDE_ONE, 0x00000000);
  648. MDSS_PLL_REG_W(pll_base, PLL_PASS_OUT_OVERRIDE_TWO, 0x00000000);
  649. MDSS_PLL_REG_W(pll_base, PLL_CORE_OVERRIDE, 0x00000000);
  650. MDSS_PLL_REG_W(pll_base, PLL_CORE_INPUT_OVERRIDE, 0x00000010);
  651. MDSS_PLL_REG_W(pll_base, PLL_RATE_CHANGE, 0x00000000);
  652. MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS, 0x00000008);
  653. MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS_TWO, 0x00000008);
  654. MDSS_PLL_REG_W(pll_base, PLL_DEC_FRAC_MUXES, 0x00000000);
  655. MDSS_PLL_REG_W(pll_base, PLL_MASH_CONTROL, 0x00000003);
  656. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_LOW, 0x00000000);
  657. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_HIGH, 0x00000000);
  658. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_LOW, 0x00000000);
  659. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_HIGH, 0x00000000);
  660. MDSS_PLL_REG_W(pll_base, PLL_SSC_ADJPER_LOW, 0x00000000);
  661. MDSS_PLL_REG_W(pll_base, PLL_SSC_ADJPER_HIGH, 0x00000000);
  662. MDSS_PLL_REG_W(pll_base, PLL_SSC_MUX_CONTROL, 0x00000000);
  663. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_LOW_1, 0x00000000);
  664. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_HIGH_1, 0x00000000);
  665. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_LOW_1, 0x00000000);
  666. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_HIGH_1, 0x00000000);
  667. MDSS_PLL_REG_W(pll_base, PLL_SSC_ADJPER_LOW_1, 0x00000000);
  668. MDSS_PLL_REG_W(pll_base, PLL_SSC_ADJPER_HIGH_1, 0x00000000);
  669. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_LOW_2, 0x00000000);
  670. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_HIGH_2, 0x00000000);
  671. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_LOW_2, 0x00000000);
  672. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_HIGH_2, 0x00000000);
  673. MDSS_PLL_REG_W(pll_base, PLL_SSC_ADJPER_LOW_2, 0x00000000);
  674. MDSS_PLL_REG_W(pll_base, PLL_SSC_ADJPER_HIGH_2, 0x00000000);
  675. MDSS_PLL_REG_W(pll_base, PLL_SSC_CONTROL, 0x00000000);
  676. MDSS_PLL_REG_W(pll_base, PLL_PLL_OUTDIV_RATE, 0x00000000);
  677. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCKDET_RATE_1, 0x00000040);
  678. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCKDET_RATE_2, 0x00000040);
  679. MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_1, 0x0000000C);
  680. MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_2, 0x0000000A);
  681. MDSS_PLL_REG_W(pll_base, PLL_PLL_BAND_SEL_RATE_1, 0x000000C0);
  682. MDSS_PLL_REG_W(pll_base, PLL_PLL_BAND_SEL_RATE_2, 0x00000000);
  683. MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x00000054);
  684. MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_2, 0x00000054);
  685. MDSS_PLL_REG_W(pll_base, PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x0000004C);
  686. MDSS_PLL_REG_W(pll_base, PLL_PLL_FL_INT_GAIN_PFILT_BAND_2, 0x0000004C);
  687. MDSS_PLL_REG_W(pll_base, PLL_PLL_FASTLOCK_EN_BAND, 0x00000003);
  688. MDSS_PLL_REG_W(pll_base, PLL_FREQ_TUNE_ACCUM_INIT_MID, 0x00000000);
  689. MDSS_PLL_REG_W(pll_base, PLL_FREQ_TUNE_ACCUM_INIT_HIGH, 0x00000000);
  690. MDSS_PLL_REG_W(pll_base, PLL_FREQ_TUNE_ACCUM_INIT_MUX, 0x00000000);
  691. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_OVERRIDE, 0x00000080);
  692. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_DELAY, 0x00000006);
  693. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_MIN_DELAY, 0x00000019);
  694. MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS, 0x00000000);
  695. MDSS_PLL_REG_W(pll_base, PLL_SPARE_AND_JPC_OVERRIDES, 0x00000000);
  696. if (dsi_pll_7nm_is_hw_revision_v1(rsc))
  697. MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x00000066);
  698. else
  699. MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x00000040);
  700. MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_2, 0x00000020);
  701. MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x00000000);
  702. MDSS_PLL_REG_W(pll_base, PLL_COMMON_STATUS_ONE, 0x00000000);
  703. MDSS_PLL_REG_W(pll_base, PLL_COMMON_STATUS_TWO, 0x00000000);
  704. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL, 0x00000000);
  705. MDSS_PLL_REG_W(pll_base, PLL_ICODE_ACCUM_STATUS_LOW, 0x00000000);
  706. MDSS_PLL_REG_W(pll_base, PLL_ICODE_ACCUM_STATUS_HIGH, 0x00000000);
  707. MDSS_PLL_REG_W(pll_base, PLL_FD_OUT_LOW, 0x00000000);
  708. MDSS_PLL_REG_W(pll_base, PLL_FD_OUT_HIGH, 0x00000000);
  709. MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_STATUS_1, 0x00000000);
  710. MDSS_PLL_REG_W(pll_base, PLL_PLL_MISC_CONFIG, 0x00000000);
  711. MDSS_PLL_REG_W(pll_base, PLL_FLL_CONFIG, 0x00000002);
  712. MDSS_PLL_REG_W(pll_base, PLL_FLL_FREQ_ACQ_TIME, 0x00000011);
  713. MDSS_PLL_REG_W(pll_base, PLL_FLL_CODE0, 0x00000000);
  714. MDSS_PLL_REG_W(pll_base, PLL_FLL_CODE1, 0x00000000);
  715. MDSS_PLL_REG_W(pll_base, PLL_FLL_GAIN0, 0x00000080);
  716. MDSS_PLL_REG_W(pll_base, PLL_FLL_GAIN1, 0x00000000);
  717. MDSS_PLL_REG_W(pll_base, PLL_SW_RESET, 0x00000000);
  718. MDSS_PLL_REG_W(pll_base, PLL_FAST_PWRUP, 0x00000000);
  719. MDSS_PLL_REG_W(pll_base, PLL_LOCKTIME0, 0x00000000);
  720. MDSS_PLL_REG_W(pll_base, PLL_LOCKTIME1, 0x00000000);
  721. MDSS_PLL_REG_W(pll_base, PLL_DEBUG_BUS_SEL, 0x00000000);
  722. MDSS_PLL_REG_W(pll_base, PLL_DEBUG_BUS0, 0x00000000);
  723. MDSS_PLL_REG_W(pll_base, PLL_DEBUG_BUS1, 0x00000000);
  724. MDSS_PLL_REG_W(pll_base, PLL_DEBUG_BUS2, 0x00000000);
  725. MDSS_PLL_REG_W(pll_base, PLL_DEBUG_BUS3, 0x00000000);
  726. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_FLL_CONTROL_OVERRIDES, 0x00000000);
  727. MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG, 0x00000000);
  728. MDSS_PLL_REG_W(pll_base, PLL_VCO_CAL_CODE1_MODE0_STATUS, 0x00000000);
  729. MDSS_PLL_REG_W(pll_base, PLL_VCO_CAL_CODE1_MODE1_STATUS, 0x00000000);
  730. MDSS_PLL_REG_W(pll_base, PLL_RESET_SM_STATUS, 0x00000000);
  731. MDSS_PLL_REG_W(pll_base, PLL_TDC_OFFSET, 0x00000000);
  732. MDSS_PLL_REG_W(pll_base, PLL_PS3_PWRDOWN_CONTROLS, 0x0000001D);
  733. MDSS_PLL_REG_W(pll_base, PLL_PS4_PWRDOWN_CONTROLS, 0x0000001C);
  734. MDSS_PLL_REG_W(pll_base, PLL_PLL_RST_CONTROLS, 0x000000FF);
  735. MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x00000022);
  736. MDSS_PLL_REG_W(pll_base, PLL_PSM_CLK_CONTROLS, 0x00000009);
  737. MDSS_PLL_REG_W(pll_base, PLL_SYSTEM_MUXES_2, 0x00000000);
  738. MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00000000);
  739. MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_2, 0x00000000);
  740. MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS_1, 0x00000040);
  741. MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS_2, 0x00000000);
  742. MDSS_PLL_REG_W(pll_base, PLL_CMODE_1, 0x00000010);
  743. MDSS_PLL_REG_W(pll_base, PLL_CMODE_2, 0x00000010);
  744. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_2, 0x00000003);
  745. }
  746. static void dsi_pll_commit(struct dsi_pll_7nm *pll,
  747. struct mdss_pll_resources *rsc)
  748. {
  749. void __iomem *pll_base = rsc->pll_base;
  750. struct dsi_pll_regs *reg = &pll->reg_setup;
  751. MDSS_PLL_REG_W(pll_base, PLL_CORE_INPUT_OVERRIDE, 0x12);
  752. MDSS_PLL_REG_W(pll_base, PLL_DECIMAL_DIV_START_1,
  753. reg->decimal_div_start);
  754. MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_LOW_1,
  755. reg->frac_div_start_low);
  756. MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_MID_1,
  757. reg->frac_div_start_mid);
  758. MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_HIGH_1,
  759. reg->frac_div_start_high);
  760. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCKDET_RATE_1, 0x40);
  761. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_DELAY, 0x06);
  762. MDSS_PLL_REG_W(pll_base, PLL_CMODE_1, 0x10);
  763. MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS_1,
  764. reg->pll_clock_inverters);
  765. }
  766. static int vco_7nm_set_rate(struct clk_hw *hw, unsigned long rate,
  767. unsigned long parent_rate)
  768. {
  769. int rc;
  770. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  771. struct mdss_pll_resources *rsc = vco->priv;
  772. struct dsi_pll_7nm *pll;
  773. if (!rsc) {
  774. pr_err("pll resource not found\n");
  775. return -EINVAL;
  776. }
  777. if (rsc->pll_on)
  778. return 0;
  779. pll = rsc->priv;
  780. if (!pll) {
  781. pr_err("pll configuration not found\n");
  782. return -EINVAL;
  783. }
  784. pr_debug("ndx=%d, rate=%lu\n", rsc->index, rate);
  785. rsc->vco_current_rate = rate;
  786. rsc->vco_ref_clk_rate = vco->ref_clk_rate;
  787. rc = mdss_pll_resource_enable(rsc, true);
  788. if (rc) {
  789. pr_err("failed to enable mdss dsi pll(%d), rc=%d\n",
  790. rsc->index, rc);
  791. return rc;
  792. }
  793. dsi_pll_init_val(rsc);
  794. dsi_pll_setup_config(pll, rsc);
  795. dsi_pll_calc_dec_frac(pll, rsc);
  796. dsi_pll_calc_ssc(pll, rsc);
  797. dsi_pll_commit(pll, rsc);
  798. dsi_pll_config_hzindep_reg(pll, rsc);
  799. dsi_pll_ssc_commit(pll, rsc);
  800. /* flush, ensure all register writes are done*/
  801. wmb();
  802. mdss_pll_resource_enable(rsc, false);
  803. return 0;
  804. }
  805. static int dsi_pll_7nm_lock_status(struct mdss_pll_resources *pll)
  806. {
  807. int rc;
  808. u32 status;
  809. u32 const delay_us = 100;
  810. u32 const timeout_us = 5000;
  811. rc = readl_poll_timeout_atomic(pll->pll_base + PLL_COMMON_STATUS_ONE,
  812. status,
  813. ((status & BIT(0)) > 0),
  814. delay_us,
  815. timeout_us);
  816. if (rc && !pll->handoff_resources)
  817. pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
  818. pll->index, status);
  819. return rc;
  820. }
  821. static void dsi_pll_disable_pll_bias(struct mdss_pll_resources *rsc)
  822. {
  823. u32 data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0);
  824. MDSS_PLL_REG_W(rsc->pll_base, PLL_SYSTEM_MUXES, 0);
  825. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data & ~BIT(5));
  826. ndelay(250);
  827. }
  828. static void dsi_pll_enable_pll_bias(struct mdss_pll_resources *rsc)
  829. {
  830. u32 data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0);
  831. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data | BIT(5));
  832. MDSS_PLL_REG_W(rsc->pll_base, PLL_SYSTEM_MUXES, 0xc0);
  833. ndelay(250);
  834. }
  835. static void dsi_pll_disable_global_clk(struct mdss_pll_resources *rsc)
  836. {
  837. u32 data;
  838. data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1);
  839. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data & ~BIT(5)));
  840. }
  841. static void dsi_pll_enable_global_clk(struct mdss_pll_resources *rsc)
  842. {
  843. u32 data;
  844. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_3, 0x04);
  845. data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1);
  846. /* Turn on clk_en_sel bit prior to resync toggle fifo */
  847. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data | BIT(5) |
  848. BIT(4)));
  849. }
  850. static void dsi_pll_phy_dig_reset(struct mdss_pll_resources *rsc)
  851. {
  852. /*
  853. * Reset the PHY digital domain. This would be needed when
  854. * coming out of a CX or analog rail power collapse while
  855. * ensuring that the pads maintain LP00 or LP11 state
  856. */
  857. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
  858. wmb(); /* Ensure that the reset is asserted */
  859. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
  860. wmb(); /* Ensure that the reset is deasserted */
  861. }
  862. static int dsi_pll_enable(struct dsi_pll_vco_clk *vco)
  863. {
  864. int rc;
  865. struct mdss_pll_resources *rsc = vco->priv;
  866. dsi_pll_enable_pll_bias(rsc);
  867. if (rsc->slave)
  868. dsi_pll_enable_pll_bias(rsc->slave);
  869. phy_reg_update_bits_sub(rsc, PHY_CMN_CLK_CFG1, 0x03, rsc->cached_cfg1);
  870. if (rsc->slave)
  871. phy_reg_update_bits_sub(rsc->slave, PHY_CMN_CLK_CFG1,
  872. 0x03, rsc->cached_cfg1);
  873. wmb(); /* ensure dsiclk_sel is always programmed before pll start */
  874. /* Start PLL */
  875. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0x01);
  876. /*
  877. * ensure all PLL configurations are written prior to checking
  878. * for PLL lock.
  879. */
  880. wmb();
  881. /* Check for PLL lock */
  882. rc = dsi_pll_7nm_lock_status(rsc);
  883. if (rc) {
  884. pr_err("PLL(%d) lock failed\n", rsc->index);
  885. goto error;
  886. }
  887. rsc->pll_on = true;
  888. /*
  889. * assert power on reset for PHY digital in case the PLL is
  890. * enabled after CX of analog domain power collapse. This needs
  891. * to be done before enabling the global clk.
  892. */
  893. dsi_pll_phy_dig_reset(rsc);
  894. if (rsc->slave)
  895. dsi_pll_phy_dig_reset(rsc->slave);
  896. dsi_pll_enable_global_clk(rsc);
  897. if (rsc->slave)
  898. dsi_pll_enable_global_clk(rsc->slave);
  899. error:
  900. return rc;
  901. }
  902. static void dsi_pll_disable_sub(struct mdss_pll_resources *rsc)
  903. {
  904. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0);
  905. dsi_pll_disable_pll_bias(rsc);
  906. }
  907. static void dsi_pll_disable(struct dsi_pll_vco_clk *vco)
  908. {
  909. struct mdss_pll_resources *rsc = vco->priv;
  910. if (!rsc->pll_on &&
  911. mdss_pll_resource_enable(rsc, true)) {
  912. pr_err("failed to enable pll (%d) resources\n", rsc->index);
  913. return;
  914. }
  915. rsc->handoff_resources = false;
  916. pr_debug("stop PLL (%d)\n", rsc->index);
  917. /*
  918. * To avoid any stray glitches while
  919. * abruptly powering down the PLL
  920. * make sure to gate the clock using
  921. * the clock enable bit before powering
  922. * down the PLL
  923. */
  924. dsi_pll_disable_global_clk(rsc);
  925. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0);
  926. dsi_pll_disable_sub(rsc);
  927. if (rsc->slave) {
  928. dsi_pll_disable_global_clk(rsc->slave);
  929. dsi_pll_disable_sub(rsc->slave);
  930. }
  931. /* flush, ensure all register writes are done*/
  932. wmb();
  933. rsc->pll_on = false;
  934. }
  935. long vco_7nm_round_rate(struct clk_hw *hw, unsigned long rate,
  936. unsigned long *parent_rate)
  937. {
  938. unsigned long rrate = rate;
  939. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  940. if (rate < vco->min_rate)
  941. rrate = vco->min_rate;
  942. if (rate > vco->max_rate)
  943. rrate = vco->max_rate;
  944. *parent_rate = rrate;
  945. return rrate;
  946. }
  947. static void vco_7nm_unprepare(struct clk_hw *hw)
  948. {
  949. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  950. struct mdss_pll_resources *pll = vco->priv;
  951. if (!pll) {
  952. pr_err("dsi pll resources not available\n");
  953. return;
  954. }
  955. /*
  956. * During unprepare in continuous splash use case we want driver
  957. * to pick all dividers instead of retaining bootloader configurations.
  958. */
  959. if (!pll->handoff_resources) {
  960. pll->cached_cfg0 = MDSS_PLL_REG_R(pll->phy_base,
  961. PHY_CMN_CLK_CFG0);
  962. pll->cached_outdiv = MDSS_PLL_REG_R(pll->pll_base,
  963. PLL_PLL_OUTDIV_RATE);
  964. pr_debug("cfg0=%d,cfg1=%d, outdiv=%d\n", pll->cached_cfg0,
  965. pll->cached_cfg1, pll->cached_outdiv);
  966. pll->vco_cached_rate = clk_hw_get_rate(hw);
  967. }
  968. /*
  969. * When continuous splash screen feature is enabled, we need to cache
  970. * the mux configuration for the pixel_clk_src mux clock. The clock
  971. * framework does not call back to re-configure the mux value if it is
  972. * does not change.For such usecases, we need to ensure that the cached
  973. * value is programmed prior to PLL being locked
  974. */
  975. if (pll->handoff_resources)
  976. pll->cached_cfg1 = MDSS_PLL_REG_R(pll->phy_base,
  977. PHY_CMN_CLK_CFG1);
  978. dsi_pll_disable(vco);
  979. mdss_pll_resource_enable(pll, false);
  980. }
  981. static int vco_7nm_prepare(struct clk_hw *hw)
  982. {
  983. int rc = 0;
  984. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  985. struct mdss_pll_resources *pll = vco->priv;
  986. if (!pll) {
  987. pr_err("dsi pll resources are not available\n");
  988. return -EINVAL;
  989. }
  990. /* Skip vco recalculation for continuous splash use case */
  991. if (pll->handoff_resources)
  992. return 0;
  993. rc = mdss_pll_resource_enable(pll, true);
  994. if (rc) {
  995. pr_err("failed to enable pll (%d) resource, rc=%d\n",
  996. pll->index, rc);
  997. return rc;
  998. }
  999. if ((pll->vco_cached_rate != 0) &&
  1000. (pll->vco_cached_rate == clk_hw_get_rate(hw))) {
  1001. rc = hw->init->ops->set_rate(hw, pll->vco_cached_rate,
  1002. pll->vco_cached_rate);
  1003. if (rc) {
  1004. pr_err("pll(%d) set_rate failed, rc=%d\n",
  1005. pll->index, rc);
  1006. mdss_pll_resource_enable(pll, false);
  1007. return rc;
  1008. }
  1009. pr_debug("cfg0=%d, cfg1=%d\n", pll->cached_cfg0,
  1010. pll->cached_cfg1);
  1011. MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0,
  1012. pll->cached_cfg0);
  1013. MDSS_PLL_REG_W(pll->pll_base, PLL_PLL_OUTDIV_RATE,
  1014. pll->cached_outdiv);
  1015. }
  1016. rc = dsi_pll_enable(vco);
  1017. if (rc) {
  1018. mdss_pll_resource_enable(pll, false);
  1019. pr_err("pll(%d) enable failed, rc=%d\n", pll->index, rc);
  1020. return rc;
  1021. }
  1022. return rc;
  1023. }
  1024. static unsigned long vco_7nm_recalc_rate(struct clk_hw *hw,
  1025. unsigned long parent_rate)
  1026. {
  1027. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  1028. struct mdss_pll_resources *pll = vco->priv;
  1029. int rc;
  1030. if (!vco->priv) {
  1031. pr_err("vco priv is null\n");
  1032. return 0;
  1033. }
  1034. /*
  1035. * In the case when vco arte is set, the recalculation function should
  1036. * return the current rate as to avoid trying to set the vco rate
  1037. * again. However durng handoff, recalculation should set the flag
  1038. * according to the status of PLL.
  1039. */
  1040. if (pll->vco_current_rate != 0) {
  1041. pr_debug("returning vco rate = %lld\n", pll->vco_current_rate);
  1042. return pll->vco_current_rate;
  1043. }
  1044. rc = mdss_pll_resource_enable(pll, true);
  1045. if (rc) {
  1046. pr_err("failed to enable pll(%d) resource, rc=%d\n",
  1047. pll->index, rc);
  1048. return 0;
  1049. }
  1050. pll->handoff_resources = true;
  1051. if (dsi_pll_7nm_lock_status(pll)) {
  1052. pr_debug("PLL not enabled\n");
  1053. pll->handoff_resources = false;
  1054. }
  1055. (void)mdss_pll_resource_enable(pll, false);
  1056. return rc;
  1057. }
  1058. static int pixel_clk_get_div(void *context, unsigned int reg, unsigned int *div)
  1059. {
  1060. int rc;
  1061. struct mdss_pll_resources *pll = context;
  1062. u32 reg_val;
  1063. rc = mdss_pll_resource_enable(pll, true);
  1064. if (rc) {
  1065. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  1066. return rc;
  1067. }
  1068. reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0);
  1069. *div = (reg_val & 0xF0) >> 4;
  1070. (void)mdss_pll_resource_enable(pll, false);
  1071. return rc;
  1072. }
  1073. static void pixel_clk_set_div_sub(struct mdss_pll_resources *pll, int div)
  1074. {
  1075. u32 reg_val;
  1076. reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0);
  1077. reg_val &= ~0xF0;
  1078. reg_val |= (div << 4);
  1079. MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0, reg_val);
  1080. }
  1081. static int pixel_clk_set_div(void *context, unsigned int reg, unsigned int div)
  1082. {
  1083. int rc;
  1084. struct mdss_pll_resources *pll = context;
  1085. rc = mdss_pll_resource_enable(pll, true);
  1086. if (rc) {
  1087. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  1088. return rc;
  1089. }
  1090. pixel_clk_set_div_sub(pll, div);
  1091. if (pll->slave)
  1092. pixel_clk_set_div_sub(pll->slave, div);
  1093. (void)mdss_pll_resource_enable(pll, false);
  1094. return 0;
  1095. }
  1096. static int bit_clk_get_div(void *context, unsigned int reg, unsigned int *div)
  1097. {
  1098. int rc;
  1099. struct mdss_pll_resources *pll = context;
  1100. u32 reg_val;
  1101. rc = mdss_pll_resource_enable(pll, true);
  1102. if (rc) {
  1103. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  1104. return rc;
  1105. }
  1106. reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0);
  1107. *div = (reg_val & 0x0F);
  1108. (void)mdss_pll_resource_enable(pll, false);
  1109. return rc;
  1110. }
  1111. static void bit_clk_set_div_sub(struct mdss_pll_resources *rsc, int div)
  1112. {
  1113. u32 reg_val;
  1114. reg_val = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG0);
  1115. reg_val &= ~0x0F;
  1116. reg_val |= div;
  1117. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG0, reg_val);
  1118. }
  1119. static int bit_clk_set_div(void *context, unsigned int reg, unsigned int div)
  1120. {
  1121. int rc;
  1122. struct mdss_pll_resources *rsc = context;
  1123. struct dsi_pll_8998 *pll;
  1124. if (!rsc) {
  1125. pr_err("pll resource not found\n");
  1126. return -EINVAL;
  1127. }
  1128. pll = rsc->priv;
  1129. if (!pll) {
  1130. pr_err("pll configuration not found\n");
  1131. return -EINVAL;
  1132. }
  1133. rc = mdss_pll_resource_enable(rsc, true);
  1134. if (rc) {
  1135. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  1136. return rc;
  1137. }
  1138. bit_clk_set_div_sub(rsc, div);
  1139. /* For slave PLL, this divider always should be set to 1 */
  1140. if (rsc->slave)
  1141. bit_clk_set_div_sub(rsc->slave, 1);
  1142. (void)mdss_pll_resource_enable(rsc, false);
  1143. return rc;
  1144. }
  1145. static struct regmap_config dsi_pll_7nm_config = {
  1146. .reg_bits = 32,
  1147. .reg_stride = 4,
  1148. .val_bits = 32,
  1149. .max_register = 0x7c0,
  1150. };
  1151. static struct regmap_bus pll_regmap_bus = {
  1152. .reg_write = pll_reg_write,
  1153. .reg_read = pll_reg_read,
  1154. };
  1155. static struct regmap_bus pclk_src_mux_regmap_bus = {
  1156. .reg_read = pclk_mux_read_sel,
  1157. .reg_write = pclk_mux_write_sel,
  1158. };
  1159. static struct regmap_bus pclk_src_regmap_bus = {
  1160. .reg_write = pixel_clk_set_div,
  1161. .reg_read = pixel_clk_get_div,
  1162. };
  1163. static struct regmap_bus bitclk_src_regmap_bus = {
  1164. .reg_write = bit_clk_set_div,
  1165. .reg_read = bit_clk_get_div,
  1166. };
  1167. static const struct clk_ops clk_ops_vco_7nm = {
  1168. .recalc_rate = vco_7nm_recalc_rate,
  1169. .set_rate = vco_7nm_set_rate,
  1170. .round_rate = vco_7nm_round_rate,
  1171. .prepare = vco_7nm_prepare,
  1172. .unprepare = vco_7nm_unprepare,
  1173. };
  1174. static struct regmap_bus mdss_mux_regmap_bus = {
  1175. .reg_write = mdss_set_mux_sel,
  1176. .reg_read = mdss_get_mux_sel,
  1177. };
  1178. /*
  1179. * Clock tree for generating DSI byte and pclk.
  1180. *
  1181. *
  1182. * +---------------+
  1183. * | vco_clk |
  1184. * +-------+-------+
  1185. * |
  1186. * |
  1187. * +---------------+
  1188. * | pll_out_div |
  1189. * | DIV(1,2,4,8) |
  1190. * +-------+-------+
  1191. * |
  1192. * +-----------------------------+--------+
  1193. * | | |
  1194. * +-------v-------+ | |
  1195. * | bitclk_src | | |
  1196. * | DIV(1..15) | | |
  1197. * +-------+-------+ | |
  1198. * | | |
  1199. * +----------+---------+ | |
  1200. * Shadow Path | | | | |
  1201. * + +-------v-------+ | +------v------+ | +------v-------+
  1202. * | | byteclk_src | | |post_bit_div | | |post_vco_div |
  1203. * | | DIV(8) | | |DIV (2) | | |DIV(4) |
  1204. * | +-------+-------+ | +------+------+ | +------+-------+
  1205. * | | | | | | |
  1206. * | | | +------+ | |
  1207. * | | +-------------+ | | +----+
  1208. * | +--------+ | | | |
  1209. * | | +-v--v-v---v------+
  1210. * +-v---------v----+ \ pclk_src_mux /
  1211. * \ byteclk_mux / \ /
  1212. * \ / +-----+-----+
  1213. * +----+-----+ | Shadow Path
  1214. * | | +
  1215. * v +-----v------+ |
  1216. * dsi_byte_clk | pclk_src | |
  1217. * | DIV(1..15) | |
  1218. * +-----+------+ |
  1219. * | |
  1220. * | |
  1221. * +--------+ |
  1222. * | |
  1223. * +---v----v----+
  1224. * \ pclk_mux /
  1225. * \ /
  1226. * +---+---+
  1227. * |
  1228. * |
  1229. * v
  1230. * dsi_pclk
  1231. *
  1232. */
  1233. static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
  1234. .ref_clk_rate = 19200000UL,
  1235. .min_rate = 1000000000UL,
  1236. .max_rate = 3500000000UL,
  1237. .hw.init = &(struct clk_init_data){
  1238. .name = "dsi0pll_vco_clk",
  1239. .parent_names = (const char *[]){"bi_tcxo"},
  1240. .num_parents = 1,
  1241. .ops = &clk_ops_vco_7nm,
  1242. },
  1243. };
  1244. static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
  1245. .ref_clk_rate = 19200000UL,
  1246. .min_rate = 1000000000UL,
  1247. .max_rate = 3500000000UL,
  1248. .hw.init = &(struct clk_init_data){
  1249. .name = "dsi1pll_vco_clk",
  1250. .parent_names = (const char *[]){"bi_tcxo"},
  1251. .num_parents = 1,
  1252. .ops = &clk_ops_vco_7nm,
  1253. },
  1254. };
  1255. static struct clk_regmap_div dsi0pll_pll_out_div = {
  1256. .reg = PLL_PLL_OUTDIV_RATE,
  1257. .shift = 0,
  1258. .width = 2,
  1259. .flags = CLK_DIVIDER_POWER_OF_TWO,
  1260. .clkr = {
  1261. .hw.init = &(struct clk_init_data){
  1262. .name = "dsi0pll_pll_out_div",
  1263. .parent_names = (const char *[]){"dsi0pll_vco_clk"},
  1264. .num_parents = 1,
  1265. .flags = CLK_SET_RATE_PARENT,
  1266. .ops = &clk_regmap_div_ops,
  1267. },
  1268. },
  1269. };
  1270. static struct clk_regmap_div dsi1pll_pll_out_div = {
  1271. .reg = PLL_PLL_OUTDIV_RATE,
  1272. .shift = 0,
  1273. .width = 2,
  1274. .flags = CLK_DIVIDER_POWER_OF_TWO,
  1275. .clkr = {
  1276. .hw.init = &(struct clk_init_data){
  1277. .name = "dsi1pll_pll_out_div",
  1278. .parent_names = (const char *[]){"dsi1pll_vco_clk"},
  1279. .num_parents = 1,
  1280. .flags = CLK_SET_RATE_PARENT,
  1281. .ops = &clk_regmap_div_ops,
  1282. },
  1283. },
  1284. };
  1285. static struct clk_regmap_div dsi0pll_bitclk_src = {
  1286. .shift = 0,
  1287. .width = 4,
  1288. .flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  1289. .clkr = {
  1290. .hw.init = &(struct clk_init_data){
  1291. .name = "dsi0pll_bitclk_src",
  1292. .parent_names = (const char *[]){"dsi0pll_pll_out_div"},
  1293. .num_parents = 1,
  1294. .flags = CLK_SET_RATE_PARENT,
  1295. .ops = &clk_regmap_div_ops,
  1296. },
  1297. },
  1298. };
  1299. static struct clk_regmap_div dsi1pll_bitclk_src = {
  1300. .shift = 0,
  1301. .width = 4,
  1302. .flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  1303. .clkr = {
  1304. .hw.init = &(struct clk_init_data){
  1305. .name = "dsi1pll_bitclk_src",
  1306. .parent_names = (const char *[]){"dsi1pll_pll_out_div"},
  1307. .num_parents = 1,
  1308. .flags = CLK_SET_RATE_PARENT,
  1309. .ops = &clk_regmap_div_ops,
  1310. },
  1311. },
  1312. };
  1313. static struct clk_fixed_factor dsi0pll_post_vco_div = {
  1314. .div = 4,
  1315. .mult = 1,
  1316. .hw.init = &(struct clk_init_data){
  1317. .name = "dsi0pll_post_vco_div",
  1318. .parent_names = (const char *[]){"dsi0pll_pll_out_div"},
  1319. .num_parents = 1,
  1320. .flags = CLK_SET_RATE_PARENT,
  1321. .ops = &clk_fixed_factor_ops,
  1322. },
  1323. };
  1324. static struct clk_fixed_factor dsi1pll_post_vco_div = {
  1325. .div = 4,
  1326. .mult = 1,
  1327. .hw.init = &(struct clk_init_data){
  1328. .name = "dsi1pll_post_vco_div",
  1329. .parent_names = (const char *[]){"dsi1pll_pll_out_div"},
  1330. .num_parents = 1,
  1331. .flags = CLK_SET_RATE_PARENT,
  1332. .ops = &clk_fixed_factor_ops,
  1333. },
  1334. };
  1335. static struct clk_fixed_factor dsi0pll_byteclk_src = {
  1336. .div = 8,
  1337. .mult = 1,
  1338. .hw.init = &(struct clk_init_data){
  1339. .name = "dsi0pll_byteclk_src",
  1340. .parent_names = (const char *[]){"dsi0pll_bitclk_src"},
  1341. .num_parents = 1,
  1342. .flags = CLK_SET_RATE_PARENT,
  1343. .ops = &clk_fixed_factor_ops,
  1344. },
  1345. };
  1346. static struct clk_fixed_factor dsi1pll_byteclk_src = {
  1347. .div = 8,
  1348. .mult = 1,
  1349. .hw.init = &(struct clk_init_data){
  1350. .name = "dsi1pll_byteclk_src",
  1351. .parent_names = (const char *[]){"dsi1pll_bitclk_src"},
  1352. .num_parents = 1,
  1353. .flags = CLK_SET_RATE_PARENT,
  1354. .ops = &clk_fixed_factor_ops,
  1355. },
  1356. };
  1357. static struct clk_fixed_factor dsi0pll_post_bit_div = {
  1358. .div = 2,
  1359. .mult = 1,
  1360. .hw.init = &(struct clk_init_data){
  1361. .name = "dsi0pll_post_bit_div",
  1362. .parent_names = (const char *[]){"dsi0pll_bitclk_src"},
  1363. .num_parents = 1,
  1364. .ops = &clk_fixed_factor_ops,
  1365. },
  1366. };
  1367. static struct clk_fixed_factor dsi1pll_post_bit_div = {
  1368. .div = 2,
  1369. .mult = 1,
  1370. .hw.init = &(struct clk_init_data){
  1371. .name = "dsi1pll_post_bit_div",
  1372. .parent_names = (const char *[]){"dsi1pll_bitclk_src"},
  1373. .num_parents = 1,
  1374. .ops = &clk_fixed_factor_ops,
  1375. },
  1376. };
  1377. static struct clk_regmap_mux dsi0pll_byteclk_mux = {
  1378. .shift = 0,
  1379. .width = 1,
  1380. .clkr = {
  1381. .hw.init = &(struct clk_init_data){
  1382. .name = "dsi0_phy_pll_out_byteclk",
  1383. .parent_names = (const char *[]){"dsi0pll_byteclk_src"},
  1384. .num_parents = 1,
  1385. .flags = CLK_SET_RATE_PARENT,
  1386. .ops = &clk_regmap_mux_closest_ops,
  1387. },
  1388. },
  1389. };
  1390. static struct clk_regmap_mux dsi1pll_byteclk_mux = {
  1391. .shift = 0,
  1392. .width = 1,
  1393. .clkr = {
  1394. .hw.init = &(struct clk_init_data){
  1395. .name = "dsi1_phy_pll_out_byteclk",
  1396. .parent_names = (const char *[]){"dsi1pll_byteclk_src"},
  1397. .num_parents = 1,
  1398. .flags = CLK_SET_RATE_PARENT,
  1399. .ops = &clk_regmap_mux_closest_ops,
  1400. },
  1401. },
  1402. };
  1403. static struct clk_regmap_mux dsi0pll_pclk_src_mux = {
  1404. .reg = PHY_CMN_CLK_CFG1,
  1405. .shift = 0,
  1406. .width = 2,
  1407. .clkr = {
  1408. .hw.init = &(struct clk_init_data){
  1409. .name = "dsi0pll_pclk_src_mux",
  1410. .parent_names = (const char *[]){"dsi0pll_bitclk_src",
  1411. "dsi0pll_post_bit_div",
  1412. "dsi0pll_pll_out_div",
  1413. "dsi0pll_post_vco_div"},
  1414. .num_parents = 4,
  1415. .ops = &clk_regmap_mux_closest_ops,
  1416. },
  1417. },
  1418. };
  1419. static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
  1420. .reg = PHY_CMN_CLK_CFG1,
  1421. .shift = 0,
  1422. .width = 2,
  1423. .clkr = {
  1424. .hw.init = &(struct clk_init_data){
  1425. .name = "dsi1pll_pclk_src_mux",
  1426. .parent_names = (const char *[]){"dsi1pll_bitclk_src",
  1427. "dsi1pll_post_bit_div",
  1428. "dsi1pll_pll_out_div",
  1429. "dsi1pll_post_vco_div"},
  1430. .num_parents = 4,
  1431. .ops = &clk_regmap_mux_closest_ops,
  1432. },
  1433. },
  1434. };
  1435. static struct clk_regmap_div dsi0pll_pclk_src = {
  1436. .shift = 0,
  1437. .width = 4,
  1438. .flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  1439. .clkr = {
  1440. .hw.init = &(struct clk_init_data){
  1441. .name = "dsi0pll_pclk_src",
  1442. .parent_names = (const char *[]){
  1443. "dsi0pll_pclk_src_mux"},
  1444. .num_parents = 1,
  1445. .flags = CLK_SET_RATE_PARENT,
  1446. .ops = &clk_regmap_div_ops,
  1447. },
  1448. },
  1449. };
  1450. static struct clk_regmap_div dsi1pll_pclk_src = {
  1451. .shift = 0,
  1452. .width = 4,
  1453. .flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  1454. .clkr = {
  1455. .hw.init = &(struct clk_init_data){
  1456. .name = "dsi1pll_pclk_src",
  1457. .parent_names = (const char *[]){
  1458. "dsi1pll_pclk_src_mux"},
  1459. .num_parents = 1,
  1460. .flags = CLK_SET_RATE_PARENT,
  1461. .ops = &clk_regmap_div_ops,
  1462. },
  1463. },
  1464. };
  1465. static struct clk_regmap_mux dsi0pll_pclk_mux = {
  1466. .shift = 0,
  1467. .width = 1,
  1468. .clkr = {
  1469. .hw.init = &(struct clk_init_data){
  1470. .name = "dsi0_phy_pll_out_dsiclk",
  1471. .parent_names = (const char *[]){"dsi0pll_pclk_src"},
  1472. .num_parents = 1,
  1473. .flags = CLK_SET_RATE_PARENT,
  1474. .ops = &clk_regmap_mux_closest_ops,
  1475. },
  1476. },
  1477. };
  1478. static struct clk_regmap_mux dsi1pll_pclk_mux = {
  1479. .shift = 0,
  1480. .width = 1,
  1481. .clkr = {
  1482. .hw.init = &(struct clk_init_data){
  1483. .name = "dsi1_phy_pll_out_dsiclk",
  1484. .parent_names = (const char *[]){"dsi1pll_pclk_src"},
  1485. .num_parents = 1,
  1486. .flags = CLK_SET_RATE_PARENT,
  1487. .ops = &clk_regmap_mux_closest_ops,
  1488. },
  1489. },
  1490. };
  1491. static struct clk_hw *mdss_dsi_pllcc_7nm[] = {
  1492. [VCO_CLK_0] = &dsi0pll_vco_clk.hw,
  1493. [PLL_OUT_DIV_0_CLK] = &dsi0pll_pll_out_div.clkr.hw,
  1494. [BITCLK_SRC_0_CLK] = &dsi0pll_bitclk_src.clkr.hw,
  1495. [BYTECLK_SRC_0_CLK] = &dsi0pll_byteclk_src.hw,
  1496. [POST_BIT_DIV_0_CLK] = &dsi0pll_post_bit_div.hw,
  1497. [POST_VCO_DIV_0_CLK] = &dsi0pll_post_vco_div.hw,
  1498. [BYTECLK_MUX_0_CLK] = &dsi0pll_byteclk_mux.clkr.hw,
  1499. [PCLK_SRC_MUX_0_CLK] = &dsi0pll_pclk_src_mux.clkr.hw,
  1500. [PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw,
  1501. [PCLK_MUX_0_CLK] = &dsi0pll_pclk_mux.clkr.hw,
  1502. [VCO_CLK_1] = &dsi1pll_vco_clk.hw,
  1503. [PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw,
  1504. [BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw,
  1505. [BYTECLK_SRC_1_CLK] = &dsi1pll_byteclk_src.hw,
  1506. [POST_BIT_DIV_1_CLK] = &dsi1pll_post_bit_div.hw,
  1507. [POST_VCO_DIV_1_CLK] = &dsi1pll_post_vco_div.hw,
  1508. [BYTECLK_MUX_1_CLK] = &dsi1pll_byteclk_mux.clkr.hw,
  1509. [PCLK_SRC_MUX_1_CLK] = &dsi1pll_pclk_src_mux.clkr.hw,
  1510. [PCLK_SRC_1_CLK] = &dsi1pll_pclk_src.clkr.hw,
  1511. [PCLK_MUX_1_CLK] = &dsi1pll_pclk_mux.clkr.hw,
  1512. };
  1513. int dsi_pll_clock_register_7nm(struct platform_device *pdev,
  1514. struct mdss_pll_resources *pll_res)
  1515. {
  1516. int rc = 0, ndx, i;
  1517. struct clk *clk;
  1518. struct clk_onecell_data *clk_data;
  1519. int num_clks = ARRAY_SIZE(mdss_dsi_pllcc_7nm);
  1520. struct regmap *rmap;
  1521. ndx = pll_res->index;
  1522. if (ndx >= DSI_PLL_MAX) {
  1523. pr_err("pll index(%d) NOT supported\n", ndx);
  1524. return -EINVAL;
  1525. }
  1526. pll_rsc_db[ndx] = pll_res;
  1527. plls[ndx].rsc = pll_res;
  1528. pll_res->priv = &plls[ndx];
  1529. pll_res->vco_delay = VCO_DELAY_USEC;
  1530. clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
  1531. if (!clk_data)
  1532. return -ENOMEM;
  1533. clk_data->clks = devm_kcalloc(&pdev->dev, num_clks,
  1534. sizeof(struct clk *), GFP_KERNEL);
  1535. if (!clk_data->clks)
  1536. return -ENOMEM;
  1537. clk_data->clk_num = num_clks;
  1538. /* Establish client data */
  1539. if (ndx == 0) {
  1540. rmap = devm_regmap_init(&pdev->dev, &pll_regmap_bus,
  1541. pll_res, &dsi_pll_7nm_config);
  1542. dsi0pll_pll_out_div.clkr.regmap = rmap;
  1543. rmap = devm_regmap_init(&pdev->dev, &bitclk_src_regmap_bus,
  1544. pll_res, &dsi_pll_7nm_config);
  1545. dsi0pll_bitclk_src.clkr.regmap = rmap;
  1546. rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
  1547. pll_res, &dsi_pll_7nm_config);
  1548. dsi0pll_pclk_src.clkr.regmap = rmap;
  1549. rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
  1550. pll_res, &dsi_pll_7nm_config);
  1551. dsi0pll_pclk_mux.clkr.regmap = rmap;
  1552. rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,
  1553. pll_res, &dsi_pll_7nm_config);
  1554. dsi0pll_pclk_src_mux.clkr.regmap = rmap;
  1555. rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
  1556. pll_res, &dsi_pll_7nm_config);
  1557. dsi0pll_byteclk_mux.clkr.regmap = rmap;
  1558. dsi0pll_vco_clk.priv = pll_res;
  1559. if (dsi_pll_7nm_is_hw_revision_v4_1(pll_res)) {
  1560. dsi0pll_vco_clk.min_rate = 600000000;
  1561. dsi0pll_vco_clk.max_rate = 5000000000;
  1562. }
  1563. for (i = VCO_CLK_0; i <= PCLK_MUX_0_CLK; i++) {
  1564. clk = devm_clk_register(&pdev->dev,
  1565. mdss_dsi_pllcc_7nm[i]);
  1566. if (IS_ERR(clk)) {
  1567. pr_err("clk registration failed for DSI clock:%d\n",
  1568. pll_res->index);
  1569. rc = -EINVAL;
  1570. goto clk_register_fail;
  1571. }
  1572. clk_data->clks[i] = clk;
  1573. }
  1574. rc = of_clk_add_provider(pdev->dev.of_node,
  1575. of_clk_src_onecell_get, clk_data);
  1576. } else {
  1577. rmap = devm_regmap_init(&pdev->dev, &pll_regmap_bus,
  1578. pll_res, &dsi_pll_7nm_config);
  1579. dsi1pll_pll_out_div.clkr.regmap = rmap;
  1580. rmap = devm_regmap_init(&pdev->dev, &bitclk_src_regmap_bus,
  1581. pll_res, &dsi_pll_7nm_config);
  1582. dsi1pll_bitclk_src.clkr.regmap = rmap;
  1583. rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
  1584. pll_res, &dsi_pll_7nm_config);
  1585. dsi1pll_pclk_src.clkr.regmap = rmap;
  1586. rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
  1587. pll_res, &dsi_pll_7nm_config);
  1588. dsi1pll_pclk_mux.clkr.regmap = rmap;
  1589. rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,
  1590. pll_res, &dsi_pll_7nm_config);
  1591. dsi1pll_pclk_src_mux.clkr.regmap = rmap;
  1592. rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
  1593. pll_res, &dsi_pll_7nm_config);
  1594. dsi1pll_byteclk_mux.clkr.regmap = rmap;
  1595. dsi1pll_vco_clk.priv = pll_res;
  1596. if (dsi_pll_7nm_is_hw_revision_v4_1(pll_res)) {
  1597. dsi1pll_vco_clk.min_rate = 600000000;
  1598. dsi1pll_vco_clk.max_rate = 5000000000;
  1599. }
  1600. for (i = VCO_CLK_1; i <= PCLK_MUX_1_CLK; i++) {
  1601. clk = devm_clk_register(&pdev->dev,
  1602. mdss_dsi_pllcc_7nm[i]);
  1603. if (IS_ERR(clk)) {
  1604. pr_err("clk registration failed for DSI clock:%d\n",
  1605. pll_res->index);
  1606. rc = -EINVAL;
  1607. goto clk_register_fail;
  1608. }
  1609. clk_data->clks[i] = clk;
  1610. }
  1611. rc = of_clk_add_provider(pdev->dev.of_node,
  1612. of_clk_src_onecell_get, clk_data);
  1613. }
  1614. if (!rc) {
  1615. pr_info("Registered DSI PLL ndx=%d, clocks successfully\n",
  1616. ndx);
  1617. return rc;
  1618. }
  1619. clk_register_fail:
  1620. return rc;
  1621. }