dsi_pll_10nm.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "%s: " fmt, __func__
  6. #include <linux/kernel.h>
  7. #include <linux/err.h>
  8. #include <linux/iopoll.h>
  9. #include <linux/delay.h>
  10. #include "dsi_pll.h"
  11. #include "pll_drv.h"
  12. #include <dt-bindings/clock/mdss-10nm-pll-clk.h>
  13. #define CREATE_TRACE_POINTS
  14. #include "pll_trace.h"
  15. #define VCO_DELAY_USEC 1
  16. #define MHZ_250 250000000UL
  17. #define MHZ_500 500000000UL
  18. #define MHZ_1000 1000000000UL
  19. #define MHZ_1100 1100000000UL
  20. #define MHZ_1900 1900000000UL
  21. #define MHZ_3000 3000000000UL
  22. /* Register Offsets from PLL base address */
  23. #define PLL_ANALOG_CONTROLS_ONE 0x000
  24. #define PLL_ANALOG_CONTROLS_TWO 0x004
  25. #define PLL_INT_LOOP_SETTINGS 0x008
  26. #define PLL_INT_LOOP_SETTINGS_TWO 0x00c
  27. #define PLL_ANALOG_CONTROLS_THREE 0x010
  28. #define PLL_ANALOG_CONTROLS_FOUR 0x014
  29. #define PLL_INT_LOOP_CONTROLS 0x018
  30. #define PLL_DSM_DIVIDER 0x01c
  31. #define PLL_FEEDBACK_DIVIDER 0x020
  32. #define PLL_SYSTEM_MUXES 0x024
  33. #define PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x028
  34. #define PLL_CMODE 0x02c
  35. #define PLL_CALIBRATION_SETTINGS 0x030
  36. #define PLL_BAND_SEL_CAL_TIMER_LOW 0x034
  37. #define PLL_BAND_SEL_CAL_TIMER_HIGH 0x038
  38. #define PLL_BAND_SEL_CAL_SETTINGS 0x03c
  39. #define PLL_BAND_SEL_MIN 0x040
  40. #define PLL_BAND_SEL_MAX 0x044
  41. #define PLL_BAND_SEL_PFILT 0x048
  42. #define PLL_BAND_SEL_IFILT 0x04c
  43. #define PLL_BAND_SEL_CAL_SETTINGS_TWO 0x050
  44. #define PLL_BAND_SEL_CAL_SETTINGS_THREE 0x054
  45. #define PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x058
  46. #define PLL_BAND_SEL_ICODE_HIGH 0x05c
  47. #define PLL_BAND_SEL_ICODE_LOW 0x060
  48. #define PLL_FREQ_DETECT_SETTINGS_ONE 0x064
  49. #define PLL_PFILT 0x07c
  50. #define PLL_IFILT 0x080
  51. #define PLL_GAIN 0x084
  52. #define PLL_ICODE_LOW 0x088
  53. #define PLL_ICODE_HIGH 0x08c
  54. #define PLL_LOCKDET 0x090
  55. #define PLL_OUTDIV 0x094
  56. #define PLL_FASTLOCK_CONTROL 0x098
  57. #define PLL_PASS_OUT_OVERRIDE_ONE 0x09c
  58. #define PLL_PASS_OUT_OVERRIDE_TWO 0x0a0
  59. #define PLL_CORE_OVERRIDE 0x0a4
  60. #define PLL_CORE_INPUT_OVERRIDE 0x0a8
  61. #define PLL_RATE_CHANGE 0x0ac
  62. #define PLL_PLL_DIGITAL_TIMERS 0x0b0
  63. #define PLL_PLL_DIGITAL_TIMERS_TWO 0x0b4
  64. #define PLL_DEC_FRAC_MUXES 0x0c8
  65. #define PLL_DECIMAL_DIV_START_1 0x0cc
  66. #define PLL_FRAC_DIV_START_LOW_1 0x0d0
  67. #define PLL_FRAC_DIV_START_MID_1 0x0d4
  68. #define PLL_FRAC_DIV_START_HIGH_1 0x0d8
  69. #define PLL_MASH_CONTROL 0x0ec
  70. #define PLL_SSC_MUX_CONTROL 0x108
  71. #define PLL_SSC_STEPSIZE_LOW_1 0x10c
  72. #define PLL_SSC_STEPSIZE_HIGH_1 0x110
  73. #define PLL_SSC_DIV_PER_LOW_1 0x114
  74. #define PLL_SSC_DIV_PER_HIGH_1 0x118
  75. #define PLL_SSC_DIV_ADJPER_LOW_1 0x11c
  76. #define PLL_SSC_DIV_ADJPER_HIGH_1 0x120
  77. #define PLL_SSC_CONTROL 0x13c
  78. #define PLL_PLL_OUTDIV_RATE 0x140
  79. #define PLL_PLL_LOCKDET_RATE_1 0x144
  80. #define PLL_PLL_PROP_GAIN_RATE_1 0x14c
  81. #define PLL_PLL_BAND_SET_RATE_1 0x154
  82. #define PLL_PLL_INT_GAIN_IFILT_BAND_1 0x15c
  83. #define PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x164
  84. #define PLL_FASTLOCK_EN_BAND 0x16c
  85. #define PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x17c
  86. #define PLL_PLL_LOCK_OVERRIDE 0x180
  87. #define PLL_PLL_LOCK_DELAY 0x184
  88. #define PLL_PLL_LOCK_MIN_DELAY 0x188
  89. #define PLL_CLOCK_INVERTERS 0x18c
  90. #define PLL_SPARE_AND_JPC_OVERRIDES 0x190
  91. #define PLL_BIAS_CONTROL_1 0x194
  92. #define PLL_BIAS_CONTROL_2 0x198
  93. #define PLL_ALOG_OBSV_BUS_CTRL_1 0x19c
  94. #define PLL_COMMON_STATUS_ONE 0x1a0
  95. /* Register Offsets from PHY base address */
  96. #define PHY_CMN_CLK_CFG0 0x010
  97. #define PHY_CMN_CLK_CFG1 0x014
  98. #define PHY_CMN_RBUF_CTRL 0x01c
  99. #define PHY_CMN_PLL_CNTRL 0x038
  100. #define PHY_CMN_CTRL_0 0x024
  101. /* Bit definition of SSC control registers */
  102. #define SSC_CENTER BIT(0)
  103. #define SSC_EN BIT(1)
  104. #define SSC_FREQ_UPDATE BIT(2)
  105. #define SSC_FREQ_UPDATE_MUX BIT(3)
  106. #define SSC_UPDATE_SSC BIT(4)
  107. #define SSC_UPDATE_SSC_MUX BIT(5)
  108. #define SSC_START BIT(6)
  109. #define SSC_START_MUX BIT(7)
  110. enum {
  111. DSI_PLL_0,
  112. DSI_PLL_1,
  113. DSI_PLL_MAX
  114. };
  115. struct dsi_pll_regs {
  116. u32 pll_prop_gain_rate;
  117. u32 pll_lockdet_rate;
  118. u32 decimal_div_start;
  119. u32 frac_div_start_low;
  120. u32 frac_div_start_mid;
  121. u32 frac_div_start_high;
  122. u32 pll_clock_inverters;
  123. u32 ssc_stepsize_low;
  124. u32 ssc_stepsize_high;
  125. u32 ssc_div_per_low;
  126. u32 ssc_div_per_high;
  127. u32 ssc_adjper_low;
  128. u32 ssc_adjper_high;
  129. u32 ssc_control;
  130. };
  131. struct dsi_pll_config {
  132. u32 ref_freq;
  133. bool div_override;
  134. u32 output_div;
  135. bool ignore_frac;
  136. bool disable_prescaler;
  137. bool enable_ssc;
  138. bool ssc_center;
  139. u32 dec_bits;
  140. u32 frac_bits;
  141. u32 lock_timer;
  142. u32 ssc_freq;
  143. u32 ssc_offset;
  144. u32 ssc_adj_per;
  145. u32 thresh_cycles;
  146. u32 refclk_cycles;
  147. };
  148. struct dsi_pll_10nm {
  149. struct mdss_pll_resources *rsc;
  150. struct dsi_pll_config pll_configuration;
  151. struct dsi_pll_regs reg_setup;
  152. };
  153. static inline int pll_reg_read(void *context, unsigned int reg,
  154. unsigned int *val)
  155. {
  156. int rc = 0;
  157. struct mdss_pll_resources *rsc = context;
  158. rc = mdss_pll_resource_enable(rsc, true);
  159. if (rc) {
  160. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  161. return rc;
  162. }
  163. *val = MDSS_PLL_REG_R(rsc->pll_base, reg);
  164. (void)mdss_pll_resource_enable(rsc, false);
  165. return rc;
  166. }
  167. static inline int pll_reg_write(void *context, unsigned int reg,
  168. unsigned int val)
  169. {
  170. int rc = 0;
  171. struct mdss_pll_resources *rsc = context;
  172. rc = mdss_pll_resource_enable(rsc, true);
  173. if (rc) {
  174. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  175. return rc;
  176. }
  177. MDSS_PLL_REG_W(rsc->pll_base, reg, val);
  178. (void)mdss_pll_resource_enable(rsc, false);
  179. return rc;
  180. }
  181. static inline int phy_reg_read(void *context, unsigned int reg,
  182. unsigned int *val)
  183. {
  184. int rc = 0;
  185. struct mdss_pll_resources *rsc = context;
  186. rc = mdss_pll_resource_enable(rsc, true);
  187. if (rc) {
  188. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  189. return rc;
  190. }
  191. *val = MDSS_PLL_REG_R(rsc->phy_base, reg);
  192. (void)mdss_pll_resource_enable(rsc, false);
  193. return rc;
  194. }
  195. static inline int phy_reg_write(void *context, unsigned int reg,
  196. unsigned int val)
  197. {
  198. int rc = 0;
  199. struct mdss_pll_resources *rsc = context;
  200. rc = mdss_pll_resource_enable(rsc, true);
  201. if (rc) {
  202. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  203. return rc;
  204. }
  205. MDSS_PLL_REG_W(rsc->phy_base, reg, val);
  206. (void)mdss_pll_resource_enable(rsc, false);
  207. return rc;
  208. }
  209. static inline int phy_reg_update_bits_sub(struct mdss_pll_resources *rsc,
  210. unsigned int reg, unsigned int mask, unsigned int val)
  211. {
  212. u32 reg_val;
  213. reg_val = MDSS_PLL_REG_R(rsc->phy_base, reg);
  214. reg_val &= ~mask;
  215. reg_val |= (val & mask);
  216. MDSS_PLL_REG_W(rsc->phy_base, reg, reg_val);
  217. return 0;
  218. }
  219. static inline int phy_reg_update_bits(void *context, unsigned int reg,
  220. unsigned int mask, unsigned int val)
  221. {
  222. int rc = 0;
  223. struct mdss_pll_resources *rsc = context;
  224. rc = mdss_pll_resource_enable(rsc, true);
  225. if (rc) {
  226. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  227. return rc;
  228. }
  229. rc = phy_reg_update_bits_sub(rsc, reg, mask, val);
  230. if (!rc && rsc->slave)
  231. rc = phy_reg_update_bits_sub(rsc->slave, reg, mask, val);
  232. (void)mdss_pll_resource_enable(rsc, false);
  233. return rc;
  234. }
  235. static inline int pclk_mux_read_sel(void *context, unsigned int reg,
  236. unsigned int *val)
  237. {
  238. int rc = 0;
  239. struct mdss_pll_resources *rsc = context;
  240. rc = mdss_pll_resource_enable(rsc, true);
  241. if (rc)
  242. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  243. else
  244. *val = (MDSS_PLL_REG_R(rsc->phy_base, reg) & 0x3);
  245. (void)mdss_pll_resource_enable(rsc, false);
  246. return rc;
  247. }
  248. static inline int pclk_mux_write_sel_sub(struct mdss_pll_resources *rsc,
  249. unsigned int reg, unsigned int val)
  250. {
  251. u32 reg_val;
  252. reg_val = MDSS_PLL_REG_R(rsc->phy_base, reg);
  253. reg_val &= ~0x03;
  254. reg_val |= val;
  255. MDSS_PLL_REG_W(rsc->phy_base, reg, reg_val);
  256. return 0;
  257. }
  258. static inline int pclk_mux_write_sel(void *context, unsigned int reg,
  259. unsigned int val)
  260. {
  261. int rc = 0;
  262. struct mdss_pll_resources *rsc = context;
  263. rc = mdss_pll_resource_enable(rsc, true);
  264. if (rc) {
  265. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  266. return rc;
  267. }
  268. rc = pclk_mux_write_sel_sub(rsc, reg, val);
  269. if (!rc && rsc->slave)
  270. rc = pclk_mux_write_sel_sub(rsc->slave, reg, val);
  271. (void)mdss_pll_resource_enable(rsc, false);
  272. /*
  273. * cache the current parent index for cases where parent
  274. * is not changing but rate is changing. In that case
  275. * clock framework won't call parent_set and hence dsiclk_sel
  276. * bit won't be programmed. e.g. dfps update use case.
  277. */
  278. rsc->cached_cfg1 = val;
  279. return rc;
  280. }
  281. static struct mdss_pll_resources *pll_rsc_db[DSI_PLL_MAX];
  282. static struct dsi_pll_10nm plls[DSI_PLL_MAX];
  283. static void dsi_pll_config_slave(struct mdss_pll_resources *rsc)
  284. {
  285. u32 reg;
  286. struct mdss_pll_resources *orsc = pll_rsc_db[DSI_PLL_1];
  287. if (!rsc)
  288. return;
  289. /* Only DSI PLL0 can act as a master */
  290. if (rsc->index != DSI_PLL_0)
  291. return;
  292. /* default configuration: source is either internal or ref clock */
  293. rsc->slave = NULL;
  294. if (!orsc) {
  295. pr_warn("slave PLL unavilable, assuming standalone config\n");
  296. return;
  297. }
  298. /* check to see if the source of DSI1 PLL bitclk is set to external */
  299. reg = MDSS_PLL_REG_R(orsc->phy_base, PHY_CMN_CLK_CFG1);
  300. reg &= (BIT(2) | BIT(3));
  301. if (reg == 0x04)
  302. rsc->slave = pll_rsc_db[DSI_PLL_1]; /* external source */
  303. pr_debug("Slave PLL %s\n", rsc->slave ? "configured" : "absent");
  304. }
  305. static void dsi_pll_setup_config(struct dsi_pll_10nm *pll,
  306. struct mdss_pll_resources *rsc)
  307. {
  308. struct dsi_pll_config *config = &pll->pll_configuration;
  309. config->ref_freq = 19200000;
  310. config->output_div = 1;
  311. config->dec_bits = 8;
  312. config->frac_bits = 18;
  313. config->lock_timer = 64;
  314. config->ssc_freq = 31500;
  315. config->ssc_offset = 5000;
  316. config->ssc_adj_per = 2;
  317. config->thresh_cycles = 32;
  318. config->refclk_cycles = 256;
  319. config->div_override = false;
  320. config->ignore_frac = false;
  321. config->disable_prescaler = false;
  322. config->enable_ssc = rsc->ssc_en;
  323. config->ssc_center = rsc->ssc_center;
  324. if (config->enable_ssc) {
  325. if (rsc->ssc_freq)
  326. config->ssc_freq = rsc->ssc_freq;
  327. if (rsc->ssc_ppm)
  328. config->ssc_offset = rsc->ssc_ppm;
  329. }
  330. dsi_pll_config_slave(rsc);
  331. }
  332. static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll,
  333. struct mdss_pll_resources *rsc)
  334. {
  335. struct dsi_pll_config *config = &pll->pll_configuration;
  336. struct dsi_pll_regs *regs = &pll->reg_setup;
  337. u64 fref = rsc->vco_ref_clk_rate;
  338. u64 pll_freq;
  339. u64 divider;
  340. u64 dec, dec_multiple;
  341. u32 frac;
  342. u64 multiplier;
  343. pll_freq = rsc->vco_current_rate;
  344. if (config->disable_prescaler)
  345. divider = fref;
  346. else
  347. divider = fref * 2;
  348. multiplier = 1 << config->frac_bits;
  349. dec_multiple = div_u64(pll_freq * multiplier, divider);
  350. div_u64_rem(dec_multiple, multiplier, &frac);
  351. dec = div_u64(dec_multiple, multiplier);
  352. if (pll_freq <= MHZ_1900)
  353. regs->pll_prop_gain_rate = 8;
  354. else if (pll_freq <= MHZ_3000)
  355. regs->pll_prop_gain_rate = 10;
  356. else
  357. regs->pll_prop_gain_rate = 12;
  358. if (pll_freq < MHZ_1100)
  359. regs->pll_clock_inverters = 8;
  360. else
  361. regs->pll_clock_inverters = 0;
  362. regs->pll_lockdet_rate = config->lock_timer;
  363. regs->decimal_div_start = dec;
  364. regs->frac_div_start_low = (frac & 0xff);
  365. regs->frac_div_start_mid = (frac & 0xff00) >> 8;
  366. regs->frac_div_start_high = (frac & 0x30000) >> 16;
  367. }
  368. static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll,
  369. struct mdss_pll_resources *rsc)
  370. {
  371. struct dsi_pll_config *config = &pll->pll_configuration;
  372. struct dsi_pll_regs *regs = &pll->reg_setup;
  373. u32 ssc_per;
  374. u32 ssc_mod;
  375. u64 ssc_step_size;
  376. u64 frac;
  377. if (!config->enable_ssc) {
  378. pr_debug("SSC not enabled\n");
  379. return;
  380. }
  381. ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1;
  382. ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
  383. ssc_per -= ssc_mod;
  384. frac = regs->frac_div_start_low |
  385. (regs->frac_div_start_mid << 8) |
  386. (regs->frac_div_start_high << 16);
  387. ssc_step_size = regs->decimal_div_start;
  388. ssc_step_size *= (1 << config->frac_bits);
  389. ssc_step_size += frac;
  390. ssc_step_size *= config->ssc_offset;
  391. ssc_step_size *= (config->ssc_adj_per + 1);
  392. ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
  393. ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
  394. regs->ssc_div_per_low = ssc_per & 0xFF;
  395. regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
  396. regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
  397. regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
  398. regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
  399. regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
  400. regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
  401. pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
  402. regs->decimal_div_start, frac, config->frac_bits);
  403. pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
  404. ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
  405. }
  406. static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll,
  407. struct mdss_pll_resources *rsc)
  408. {
  409. void __iomem *pll_base = rsc->pll_base;
  410. struct dsi_pll_regs *regs = &pll->reg_setup;
  411. if (pll->pll_configuration.enable_ssc) {
  412. pr_debug("SSC is enabled\n");
  413. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_LOW_1,
  414. regs->ssc_stepsize_low);
  415. MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_HIGH_1,
  416. regs->ssc_stepsize_high);
  417. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_LOW_1,
  418. regs->ssc_div_per_low);
  419. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_HIGH_1,
  420. regs->ssc_div_per_high);
  421. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_ADJPER_LOW_1,
  422. regs->ssc_adjper_low);
  423. MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_ADJPER_HIGH_1,
  424. regs->ssc_adjper_high);
  425. MDSS_PLL_REG_W(pll_base, PLL_SSC_CONTROL,
  426. SSC_EN | regs->ssc_control);
  427. }
  428. }
  429. static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll,
  430. struct mdss_pll_resources *rsc)
  431. {
  432. void __iomem *pll_base = rsc->pll_base;
  433. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_ONE, 0x80);
  434. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_TWO, 0x03);
  435. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_THREE, 0x00);
  436. MDSS_PLL_REG_W(pll_base, PLL_DSM_DIVIDER, 0x00);
  437. MDSS_PLL_REG_W(pll_base, PLL_FEEDBACK_DIVIDER, 0x4e);
  438. MDSS_PLL_REG_W(pll_base, PLL_CALIBRATION_SETTINGS, 0x40);
  439. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
  440. MDSS_PLL_REG_W(pll_base, PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
  441. MDSS_PLL_REG_W(pll_base, PLL_OUTDIV, 0x00);
  442. MDSS_PLL_REG_W(pll_base, PLL_CORE_OVERRIDE, 0x00);
  443. MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
  444. MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_1, 0x08);
  445. MDSS_PLL_REG_W(pll_base, PLL_PLL_BAND_SET_RATE_1, 0xc0);
  446. MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa);
  447. MDSS_PLL_REG_W(pll_base, PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
  448. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_OVERRIDE, 0x80);
  449. MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x29);
  450. MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x3f);
  451. }
  452. static void dsi_pll_init_val(struct mdss_pll_resources *rsc)
  453. {
  454. void __iomem *pll_base = rsc->pll_base;
  455. MDSS_PLL_REG_W(pll_base, PLL_CORE_INPUT_OVERRIDE, 0x10);
  456. MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_SETTINGS, 0x3f);
  457. MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_SETTINGS_TWO, 0x0);
  458. MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FOUR, 0x0);
  459. MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_CONTROLS, 0x80);
  460. MDSS_PLL_REG_W(pll_base, PLL_FREQ_UPDATE_CONTROL_OVERRIDES, 0x0);
  461. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_TIMER_LOW, 0x0);
  462. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_TIMER_HIGH, 0x02);
  463. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS, 0x82);
  464. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_MIN, 0x00);
  465. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_MAX, 0xff);
  466. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_PFILT, 0x00);
  467. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_IFILT, 0x00);
  468. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_TWO, 0x25);
  469. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_FOUR, 0x4f);
  470. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_ICODE_HIGH, 0x0a);
  471. MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_ICODE_LOW, 0x0);
  472. MDSS_PLL_REG_W(pll_base, PLL_GAIN, 0x42);
  473. MDSS_PLL_REG_W(pll_base, PLL_ICODE_LOW, 0x00);
  474. MDSS_PLL_REG_W(pll_base, PLL_ICODE_HIGH, 0x00);
  475. MDSS_PLL_REG_W(pll_base, PLL_LOCKDET, 0x30);
  476. MDSS_PLL_REG_W(pll_base, PLL_FASTLOCK_CONTROL, 0x04);
  477. MDSS_PLL_REG_W(pll_base, PLL_PASS_OUT_OVERRIDE_ONE, 0x00);
  478. MDSS_PLL_REG_W(pll_base, PLL_PASS_OUT_OVERRIDE_TWO, 0x00);
  479. MDSS_PLL_REG_W(pll_base, PLL_RATE_CHANGE, 0x01);
  480. MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS, 0x08);
  481. MDSS_PLL_REG_W(pll_base, PLL_DEC_FRAC_MUXES, 0x00);
  482. MDSS_PLL_REG_W(pll_base, PLL_MASH_CONTROL, 0x03);
  483. MDSS_PLL_REG_W(pll_base, PLL_SSC_MUX_CONTROL, 0x0);
  484. MDSS_PLL_REG_W(pll_base, PLL_SSC_CONTROL, 0x0);
  485. MDSS_PLL_REG_W(pll_base, PLL_FASTLOCK_EN_BAND, 0x03);
  486. MDSS_PLL_REG_W(pll_base, PLL_FREQ_TUNE_ACCUM_INIT_MUX, 0x0);
  487. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_MIN_DELAY, 0x19);
  488. MDSS_PLL_REG_W(pll_base, PLL_SPARE_AND_JPC_OVERRIDES, 0x0);
  489. MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x40);
  490. MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_2, 0x20);
  491. MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x0);
  492. }
  493. static void dsi_pll_commit(struct dsi_pll_10nm *pll,
  494. struct mdss_pll_resources *rsc)
  495. {
  496. void __iomem *pll_base = rsc->pll_base;
  497. struct dsi_pll_regs *reg = &pll->reg_setup;
  498. MDSS_PLL_REG_W(pll_base, PLL_CORE_INPUT_OVERRIDE, 0x12);
  499. MDSS_PLL_REG_W(pll_base, PLL_DECIMAL_DIV_START_1,
  500. reg->decimal_div_start);
  501. MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_LOW_1,
  502. reg->frac_div_start_low);
  503. MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_MID_1,
  504. reg->frac_div_start_mid);
  505. MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_HIGH_1,
  506. reg->frac_div_start_high);
  507. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCKDET_RATE_1, 0x40);
  508. MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_DELAY, 0x06);
  509. MDSS_PLL_REG_W(pll_base, PLL_CMODE, 0x10);
  510. MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS, reg->pll_clock_inverters);
  511. }
  512. static int vco_10nm_set_rate(struct clk_hw *hw, unsigned long rate,
  513. unsigned long parent_rate)
  514. {
  515. int rc;
  516. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  517. struct mdss_pll_resources *rsc = vco->priv;
  518. struct dsi_pll_10nm *pll;
  519. if (!rsc) {
  520. pr_err("pll resource not found\n");
  521. return -EINVAL;
  522. }
  523. if (rsc->pll_on)
  524. return 0;
  525. pll = rsc->priv;
  526. if (!pll) {
  527. pr_err("pll configuration not found\n");
  528. return -EINVAL;
  529. }
  530. pr_debug("ndx=%d, rate=%lu\n", rsc->index, rate);
  531. rsc->vco_current_rate = rate;
  532. rsc->vco_ref_clk_rate = vco->ref_clk_rate;
  533. rc = mdss_pll_resource_enable(rsc, true);
  534. if (rc) {
  535. pr_err("failed to enable mdss dsi pll(%d), rc=%d\n",
  536. rsc->index, rc);
  537. return rc;
  538. }
  539. dsi_pll_init_val(rsc);
  540. dsi_pll_setup_config(pll, rsc);
  541. dsi_pll_calc_dec_frac(pll, rsc);
  542. dsi_pll_calc_ssc(pll, rsc);
  543. dsi_pll_commit(pll, rsc);
  544. dsi_pll_config_hzindep_reg(pll, rsc);
  545. dsi_pll_ssc_commit(pll, rsc);
  546. /* flush, ensure all register writes are done*/
  547. wmb();
  548. mdss_pll_resource_enable(rsc, false);
  549. return 0;
  550. }
  551. static int dsi_pll_10nm_lock_status(struct mdss_pll_resources *pll)
  552. {
  553. int rc;
  554. u32 status;
  555. u32 const delay_us = 100;
  556. u32 const timeout_us = 5000;
  557. rc = readl_poll_timeout_atomic(pll->pll_base + PLL_COMMON_STATUS_ONE,
  558. status,
  559. ((status & BIT(0)) > 0),
  560. delay_us,
  561. timeout_us);
  562. if (rc)
  563. pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
  564. pll->index, status);
  565. return rc;
  566. }
  567. static void dsi_pll_disable_pll_bias(struct mdss_pll_resources *rsc)
  568. {
  569. u32 data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0);
  570. MDSS_PLL_REG_W(rsc->pll_base, PLL_SYSTEM_MUXES, 0);
  571. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data & ~BIT(5));
  572. ndelay(250);
  573. }
  574. static void dsi_pll_enable_pll_bias(struct mdss_pll_resources *rsc)
  575. {
  576. u32 data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0);
  577. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data | BIT(5));
  578. MDSS_PLL_REG_W(rsc->pll_base, PLL_SYSTEM_MUXES, 0xc0);
  579. ndelay(250);
  580. }
  581. static void dsi_pll_disable_global_clk(struct mdss_pll_resources *rsc)
  582. {
  583. u32 data;
  584. data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1);
  585. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data & ~BIT(5)));
  586. }
  587. static void dsi_pll_enable_global_clk(struct mdss_pll_resources *rsc)
  588. {
  589. u32 data;
  590. data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1);
  591. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data | BIT(5)));
  592. }
  593. static int dsi_pll_enable(struct dsi_pll_vco_clk *vco)
  594. {
  595. int rc;
  596. struct mdss_pll_resources *rsc = vco->priv;
  597. dsi_pll_enable_pll_bias(rsc);
  598. if (rsc->slave)
  599. dsi_pll_enable_pll_bias(rsc->slave);
  600. phy_reg_update_bits_sub(rsc, PHY_CMN_CLK_CFG1, 0x03, rsc->cached_cfg1);
  601. if (rsc->slave)
  602. phy_reg_update_bits_sub(rsc->slave, PHY_CMN_CLK_CFG1,
  603. 0x03, rsc->cached_cfg1);
  604. wmb(); /* ensure dsiclk_sel is always programmed before pll start */
  605. /* Start PLL */
  606. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0x01);
  607. /*
  608. * ensure all PLL configurations are written prior to checking
  609. * for PLL lock.
  610. */
  611. wmb();
  612. /* Check for PLL lock */
  613. rc = dsi_pll_10nm_lock_status(rsc);
  614. if (rc) {
  615. pr_err("PLL(%d) lock failed\n", rsc->index);
  616. goto error;
  617. }
  618. rsc->pll_on = true;
  619. dsi_pll_enable_global_clk(rsc);
  620. if (rsc->slave)
  621. dsi_pll_enable_global_clk(rsc->slave);
  622. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0x01);
  623. if (rsc->slave)
  624. MDSS_PLL_REG_W(rsc->slave->phy_base, PHY_CMN_RBUF_CTRL, 0x01);
  625. error:
  626. return rc;
  627. }
  628. static void dsi_pll_disable_sub(struct mdss_pll_resources *rsc)
  629. {
  630. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0);
  631. dsi_pll_disable_pll_bias(rsc);
  632. }
  633. static void dsi_pll_disable(struct dsi_pll_vco_clk *vco)
  634. {
  635. struct mdss_pll_resources *rsc = vco->priv;
  636. if (!rsc->pll_on &&
  637. mdss_pll_resource_enable(rsc, true)) {
  638. pr_err("failed to enable pll (%d) resources\n", rsc->index);
  639. return;
  640. }
  641. rsc->handoff_resources = false;
  642. pr_debug("stop PLL (%d)\n", rsc->index);
  643. /*
  644. * To avoid any stray glitches while
  645. * abruptly powering down the PLL
  646. * make sure to gate the clock using
  647. * the clock enable bit before powering
  648. * down the PLL
  649. */
  650. dsi_pll_disable_global_clk(rsc);
  651. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0);
  652. dsi_pll_disable_sub(rsc);
  653. if (rsc->slave) {
  654. dsi_pll_disable_global_clk(rsc->slave);
  655. dsi_pll_disable_sub(rsc->slave);
  656. }
  657. /* flush, ensure all register writes are done*/
  658. wmb();
  659. rsc->pll_on = false;
  660. }
  661. long vco_10nm_round_rate(struct clk_hw *hw, unsigned long rate,
  662. unsigned long *parent_rate)
  663. {
  664. unsigned long rrate = rate;
  665. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  666. if (rate < vco->min_rate)
  667. rrate = vco->min_rate;
  668. if (rate > vco->max_rate)
  669. rrate = vco->max_rate;
  670. *parent_rate = rrate;
  671. return rrate;
  672. }
  673. static void vco_10nm_unprepare(struct clk_hw *hw)
  674. {
  675. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  676. struct mdss_pll_resources *pll = vco->priv;
  677. if (!pll) {
  678. pr_err("dsi pll resources not available\n");
  679. return;
  680. }
  681. /*
  682. * During unprepare in continuous splash use case we want driver
  683. * to pick all dividers instead of retaining bootloader configurations.
  684. */
  685. if (!pll->handoff_resources) {
  686. pll->cached_cfg0 = MDSS_PLL_REG_R(pll->phy_base,
  687. PHY_CMN_CLK_CFG0);
  688. pll->cached_outdiv = MDSS_PLL_REG_R(pll->pll_base,
  689. PLL_PLL_OUTDIV_RATE);
  690. pr_debug("cfg0=%d,cfg1=%d, outdiv=%d\n", pll->cached_cfg0,
  691. pll->cached_cfg1, pll->cached_outdiv);
  692. pll->vco_cached_rate = clk_hw_get_rate(hw);
  693. }
  694. /*
  695. * When continuous splash screen feature is enabled, we need to cache
  696. * the mux configuration for the pixel_clk_src mux clock. The clock
  697. * framework does not call back to re-configure the mux value if it is
  698. * does not change.For such usecases, we need to ensure that the cached
  699. * value is programmed prior to PLL being locked
  700. */
  701. if (pll->handoff_resources)
  702. pll->cached_cfg1 = MDSS_PLL_REG_R(pll->phy_base,
  703. PHY_CMN_CLK_CFG1);
  704. dsi_pll_disable(vco);
  705. mdss_pll_resource_enable(pll, false);
  706. }
  707. static int vco_10nm_prepare(struct clk_hw *hw)
  708. {
  709. int rc = 0;
  710. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  711. struct mdss_pll_resources *pll = vco->priv;
  712. if (!pll) {
  713. pr_err("dsi pll resources are not available\n");
  714. return -EINVAL;
  715. }
  716. /* Skip vco recalculation for continuous splash use case */
  717. if (pll->handoff_resources)
  718. return 0;
  719. rc = mdss_pll_resource_enable(pll, true);
  720. if (rc) {
  721. pr_err("failed to enable pll (%d) resource, rc=%d\n",
  722. pll->index, rc);
  723. return rc;
  724. }
  725. if ((pll->vco_cached_rate != 0) &&
  726. (pll->vco_cached_rate == clk_hw_get_rate(hw))) {
  727. rc = hw->init->ops->set_rate(hw, pll->vco_cached_rate,
  728. pll->vco_cached_rate);
  729. if (rc) {
  730. pr_err("pll(%d) set_rate failed, rc=%d\n",
  731. pll->index, rc);
  732. mdss_pll_resource_enable(pll, false);
  733. return rc;
  734. }
  735. pr_debug("cfg0=%d, cfg1=%d\n", pll->cached_cfg0,
  736. pll->cached_cfg1);
  737. MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0,
  738. pll->cached_cfg0);
  739. MDSS_PLL_REG_W(pll->pll_base, PLL_PLL_OUTDIV_RATE,
  740. pll->cached_outdiv);
  741. }
  742. MDSS_PLL_ATRACE_BEGIN("pll_lock");
  743. trace_mdss_pll_lock_start((u64)pll->vco_cached_rate,
  744. pll->vco_current_rate,
  745. pll->cached_cfg0, pll->cached_cfg1,
  746. pll->cached_outdiv, pll->resource_ref_cnt);
  747. rc = dsi_pll_enable(vco);
  748. MDSS_PLL_ATRACE_END("pll_lock");
  749. if (rc) {
  750. mdss_pll_resource_enable(pll, false);
  751. pr_err("pll(%d) enable failed, rc=%d\n", pll->index, rc);
  752. return rc;
  753. }
  754. return rc;
  755. }
  756. static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw,
  757. unsigned long parent_rate)
  758. {
  759. struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
  760. struct mdss_pll_resources *pll = vco->priv;
  761. int rc;
  762. u64 ref_clk = vco->ref_clk_rate;
  763. u64 vco_rate;
  764. u64 multiplier;
  765. u32 frac;
  766. u32 dec;
  767. u32 outdiv;
  768. u64 pll_freq, tmp64;
  769. if (!vco->priv)
  770. pr_err("vco priv is null\n");
  771. if (!pll) {
  772. pr_err("pll is null\n");
  773. return 0;
  774. }
  775. /*
  776. * Calculate the vco rate from HW registers only for handoff cases.
  777. * For other cases where a vco_10nm_set_rate() has already been
  778. * called, just return the rate that was set earlier. This is due
  779. * to the fact that recalculating VCO rate requires us to read the
  780. * correct value of the pll_out_div divider clock, which is only set
  781. * afterwards.
  782. */
  783. if (pll->vco_current_rate != 0) {
  784. pr_debug("returning vco rate = %lld\n", pll->vco_current_rate);
  785. return pll->vco_current_rate;
  786. }
  787. rc = mdss_pll_resource_enable(pll, true);
  788. if (rc) {
  789. pr_err("failed to enable pll(%d) resource, rc=%d\n",
  790. pll->index, rc);
  791. return 0;
  792. }
  793. if (!dsi_pll_10nm_lock_status(pll))
  794. pll->handoff_resources = true;
  795. dec = MDSS_PLL_REG_R(pll->pll_base, PLL_DECIMAL_DIV_START_1);
  796. dec &= 0xFF;
  797. frac = MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_LOW_1);
  798. frac |= ((MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_MID_1) &
  799. 0xFF) <<
  800. 8);
  801. frac |= ((MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_HIGH_1) &
  802. 0x3) <<
  803. 16);
  804. /* OUTDIV_1:0 field is (log(outdiv, 2)) */
  805. outdiv = MDSS_PLL_REG_R(pll->pll_base, PLL_PLL_OUTDIV_RATE);
  806. outdiv &= 0x3;
  807. outdiv = 1 << outdiv;
  808. /*
  809. * TODO:
  810. * 1. Assumes prescaler is disabled
  811. * 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits)
  812. **/
  813. multiplier = 1 << 18;
  814. pll_freq = dec * (ref_clk * 2);
  815. tmp64 = (ref_clk * 2 * frac);
  816. pll_freq += div_u64(tmp64, multiplier);
  817. vco_rate = div_u64(pll_freq, outdiv);
  818. pr_debug("dec=0x%x, frac=0x%x, outdiv=%d, vco=%llu\n",
  819. dec, frac, outdiv, vco_rate);
  820. (void)mdss_pll_resource_enable(pll, false);
  821. return (unsigned long)vco_rate;
  822. }
  823. static int pixel_clk_get_div(void *context, unsigned int reg, unsigned int *div)
  824. {
  825. int rc;
  826. struct mdss_pll_resources *pll = context;
  827. u32 reg_val;
  828. rc = mdss_pll_resource_enable(pll, true);
  829. if (rc) {
  830. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  831. return rc;
  832. }
  833. reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0);
  834. *div = (reg_val & 0xF0) >> 4;
  835. /**
  836. * Common clock framework the divider value is interpreted as one less
  837. * hence we return one less for all dividers except when zero
  838. */
  839. if (*div != 0)
  840. *div -= 1;
  841. (void)mdss_pll_resource_enable(pll, false);
  842. return rc;
  843. }
  844. static void pixel_clk_set_div_sub(struct mdss_pll_resources *pll, int div)
  845. {
  846. u32 reg_val;
  847. reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0);
  848. reg_val &= ~0xF0;
  849. reg_val |= (div << 4);
  850. MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0, reg_val);
  851. }
  852. static int pixel_clk_set_div(void *context, unsigned int reg, unsigned int div)
  853. {
  854. int rc;
  855. struct mdss_pll_resources *pll = context;
  856. rc = mdss_pll_resource_enable(pll, true);
  857. if (rc) {
  858. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  859. return rc;
  860. }
  861. /**
  862. * In common clock framework the divider value provided is one less and
  863. * and hence adjusting the divider value by one prior to writing it to
  864. * hardware
  865. */
  866. div++;
  867. pixel_clk_set_div_sub(pll, div);
  868. if (pll->slave)
  869. pixel_clk_set_div_sub(pll->slave, div);
  870. (void)mdss_pll_resource_enable(pll, false);
  871. return 0;
  872. }
  873. static int bit_clk_get_div(void *context, unsigned int reg, unsigned int *div)
  874. {
  875. int rc;
  876. struct mdss_pll_resources *pll = context;
  877. u32 reg_val;
  878. rc = mdss_pll_resource_enable(pll, true);
  879. if (rc) {
  880. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  881. return rc;
  882. }
  883. reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0);
  884. *div = (reg_val & 0x0F);
  885. /**
  886. *Common clock framework the divider value is interpreted as one less
  887. * hence we return one less for all dividers except when zero
  888. */
  889. if (*div != 0)
  890. *div -= 1;
  891. (void)mdss_pll_resource_enable(pll, false);
  892. return rc;
  893. }
  894. static void bit_clk_set_div_sub(struct mdss_pll_resources *rsc, int div)
  895. {
  896. u32 reg_val;
  897. reg_val = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG0);
  898. reg_val &= ~0x0F;
  899. reg_val |= div;
  900. MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG0, reg_val);
  901. }
  902. static int bit_clk_set_div(void *context, unsigned int reg, unsigned int div)
  903. {
  904. int rc;
  905. struct mdss_pll_resources *rsc = context;
  906. struct dsi_pll_8998 *pll;
  907. if (!rsc) {
  908. pr_err("pll resource not found\n");
  909. return -EINVAL;
  910. }
  911. pll = rsc->priv;
  912. if (!pll) {
  913. pr_err("pll configuration not found\n");
  914. return -EINVAL;
  915. }
  916. rc = mdss_pll_resource_enable(rsc, true);
  917. if (rc) {
  918. pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
  919. return rc;
  920. }
  921. /**
  922. * In common clock framework the divider value provided is one less and
  923. * and hence adjusting the divider value by one prior to writing it to
  924. * hardware
  925. */
  926. div++;
  927. bit_clk_set_div_sub(rsc, div);
  928. /* For slave PLL, this divider always should be set to 1 */
  929. if (rsc->slave)
  930. bit_clk_set_div_sub(rsc->slave, 1);
  931. (void)mdss_pll_resource_enable(rsc, false);
  932. return rc;
  933. }
  934. static struct regmap_config dsi_pll_10nm_config = {
  935. .reg_bits = 32,
  936. .reg_stride = 4,
  937. .val_bits = 32,
  938. .max_register = 0x7c0,
  939. };
  940. static struct regmap_bus pll_regmap_bus = {
  941. .reg_write = pll_reg_write,
  942. .reg_read = pll_reg_read,
  943. };
  944. static struct regmap_bus pclk_src_mux_regmap_bus = {
  945. .reg_read = pclk_mux_read_sel,
  946. .reg_write = pclk_mux_write_sel,
  947. };
  948. static struct regmap_bus pclk_src_regmap_bus = {
  949. .reg_write = pixel_clk_set_div,
  950. .reg_read = pixel_clk_get_div,
  951. };
  952. static struct regmap_bus bitclk_src_regmap_bus = {
  953. .reg_write = bit_clk_set_div,
  954. .reg_read = bit_clk_get_div,
  955. };
  956. static const struct clk_ops clk_ops_vco_10nm = {
  957. .recalc_rate = vco_10nm_recalc_rate,
  958. .set_rate = vco_10nm_set_rate,
  959. .round_rate = vco_10nm_round_rate,
  960. .prepare = vco_10nm_prepare,
  961. .unprepare = vco_10nm_unprepare,
  962. };
  963. static struct regmap_bus mdss_mux_regmap_bus = {
  964. .reg_write = mdss_set_mux_sel,
  965. .reg_read = mdss_get_mux_sel,
  966. };
  967. /*
  968. * Clock tree for generating DSI byte and pixel clocks.
  969. *
  970. *
  971. * +---------------+
  972. * | vco_clk |
  973. * +-------+-------+
  974. * |
  975. * |
  976. * +---------------+
  977. * | pll_out_div |
  978. * | DIV(1,2,4,8) |
  979. * +-------+-------+
  980. * |
  981. * +-----------------------------+--------+
  982. * | | |
  983. * +-------v-------+ | |
  984. * | bitclk_src | | |
  985. * | DIV(1..15) | | |
  986. * +-------+-------+ | |
  987. * | | |
  988. * +----------+---------+ | |
  989. * Shadow Path | | | | |
  990. * + +-------v-------+ | +------v------+ | +------v-------+
  991. * | | byteclk_src | | |post_bit_div | | |post_vco_div |
  992. * | | DIV(8) | | |DIV (2) | | |DIV(4) |
  993. * | +-------+-------+ | +------+------+ | +------+-------+
  994. * | | | | | | |
  995. * | | | +------+ | |
  996. * | | +-------------+ | | +----+
  997. * | +--------+ | | | |
  998. * | | +-v--v-v---v------+
  999. * +-v---------v----+ \ pclk_src_mux /
  1000. * \ byteclk_mux / \ /
  1001. * \ / +-----+-----+
  1002. * +----+-----+ | Shadow Path
  1003. * | | +
  1004. * v +-----v------+ |
  1005. * dsi_byte_clk | pclk_src | |
  1006. * | DIV(1..15) | |
  1007. * +-----+------+ |
  1008. * | |
  1009. * | |
  1010. * +--------+ |
  1011. * | |
  1012. * +---v----v----+
  1013. * \ pclk_mux /
  1014. * \ /
  1015. * +---+---+
  1016. * |
  1017. * |
  1018. * v
  1019. * dsi_pclk
  1020. *
  1021. */
  1022. static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
  1023. .ref_clk_rate = 19200000UL,
  1024. .min_rate = 1000000000UL,
  1025. .max_rate = 3500000000UL,
  1026. .hw.init = &(struct clk_init_data){
  1027. .name = "dsi0pll_vco_clk",
  1028. .parent_names = (const char *[]){"bi_tcxo"},
  1029. .num_parents = 1,
  1030. .ops = &clk_ops_vco_10nm,
  1031. .flags = CLK_GET_RATE_NOCACHE,
  1032. },
  1033. };
  1034. static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
  1035. .ref_clk_rate = 19200000UL,
  1036. .min_rate = 1000000000UL,
  1037. .max_rate = 3500000000UL,
  1038. .hw.init = &(struct clk_init_data){
  1039. .name = "dsi1pll_vco_clk",
  1040. .parent_names = (const char *[]){"bi_tcxo"},
  1041. .num_parents = 1,
  1042. .ops = &clk_ops_vco_10nm,
  1043. .flags = CLK_GET_RATE_NOCACHE,
  1044. },
  1045. };
  1046. static struct clk_regmap_div dsi0pll_pll_out_div = {
  1047. .reg = PLL_PLL_OUTDIV_RATE,
  1048. .shift = 0,
  1049. .width = 2,
  1050. .flags = CLK_DIVIDER_POWER_OF_TWO,
  1051. .clkr = {
  1052. .hw.init = &(struct clk_init_data){
  1053. .name = "dsi0pll_pll_out_div",
  1054. .parent_names = (const char *[]){"dsi0pll_vco_clk"},
  1055. .num_parents = 1,
  1056. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1057. .ops = &clk_regmap_div_ops,
  1058. },
  1059. },
  1060. };
  1061. static struct clk_regmap_div dsi1pll_pll_out_div = {
  1062. .reg = PLL_PLL_OUTDIV_RATE,
  1063. .shift = 0,
  1064. .width = 2,
  1065. .flags = CLK_DIVIDER_POWER_OF_TWO,
  1066. .clkr = {
  1067. .hw.init = &(struct clk_init_data){
  1068. .name = "dsi1pll_pll_out_div",
  1069. .parent_names = (const char *[]){"dsi1pll_vco_clk"},
  1070. .num_parents = 1,
  1071. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1072. .ops = &clk_regmap_div_ops,
  1073. },
  1074. },
  1075. };
  1076. static struct clk_regmap_div dsi0pll_bitclk_src = {
  1077. .shift = 0,
  1078. .width = 4,
  1079. .clkr = {
  1080. .hw.init = &(struct clk_init_data){
  1081. .name = "dsi0pll_bitclk_src",
  1082. .parent_names = (const char *[]){"dsi0pll_pll_out_div"},
  1083. .num_parents = 1,
  1084. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1085. .ops = &clk_regmap_div_ops,
  1086. },
  1087. },
  1088. };
  1089. static struct clk_regmap_div dsi1pll_bitclk_src = {
  1090. .shift = 0,
  1091. .width = 4,
  1092. .clkr = {
  1093. .hw.init = &(struct clk_init_data){
  1094. .name = "dsi1pll_bitclk_src",
  1095. .parent_names = (const char *[]){"dsi1pll_pll_out_div"},
  1096. .num_parents = 1,
  1097. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1098. .ops = &clk_regmap_div_ops,
  1099. },
  1100. },
  1101. };
  1102. static struct clk_fixed_factor dsi0pll_post_vco_div = {
  1103. .div = 4,
  1104. .mult = 1,
  1105. .hw.init = &(struct clk_init_data){
  1106. .name = "dsi0pll_post_vco_div",
  1107. .parent_names = (const char *[]){"dsi0pll_pll_out_div"},
  1108. .num_parents = 1,
  1109. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1110. .ops = &clk_fixed_factor_ops,
  1111. },
  1112. };
  1113. static struct clk_fixed_factor dsi1pll_post_vco_div = {
  1114. .div = 4,
  1115. .mult = 1,
  1116. .hw.init = &(struct clk_init_data){
  1117. .name = "dsi1pll_post_vco_div",
  1118. .parent_names = (const char *[]){"dsi1pll_pll_out_div"},
  1119. .num_parents = 1,
  1120. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1121. .ops = &clk_fixed_factor_ops,
  1122. },
  1123. };
  1124. static struct clk_fixed_factor dsi0pll_byteclk_src = {
  1125. .div = 8,
  1126. .mult = 1,
  1127. .hw.init = &(struct clk_init_data){
  1128. .name = "dsi0pll_byteclk_src",
  1129. .parent_names = (const char *[]){"dsi0pll_bitclk_src"},
  1130. .num_parents = 1,
  1131. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1132. .ops = &clk_fixed_factor_ops,
  1133. },
  1134. };
  1135. static struct clk_fixed_factor dsi1pll_byteclk_src = {
  1136. .div = 8,
  1137. .mult = 1,
  1138. .hw.init = &(struct clk_init_data){
  1139. .name = "dsi1pll_byteclk_src",
  1140. .parent_names = (const char *[]){"dsi1pll_bitclk_src"},
  1141. .num_parents = 1,
  1142. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1143. .ops = &clk_fixed_factor_ops,
  1144. },
  1145. };
  1146. static struct clk_fixed_factor dsi0pll_post_bit_div = {
  1147. .div = 2,
  1148. .mult = 1,
  1149. .hw.init = &(struct clk_init_data){
  1150. .name = "dsi0pll_post_bit_div",
  1151. .parent_names = (const char *[]){"dsi0pll_bitclk_src"},
  1152. .num_parents = 1,
  1153. .flags = CLK_GET_RATE_NOCACHE,
  1154. .ops = &clk_fixed_factor_ops,
  1155. },
  1156. };
  1157. static struct clk_fixed_factor dsi1pll_post_bit_div = {
  1158. .div = 2,
  1159. .mult = 1,
  1160. .hw.init = &(struct clk_init_data){
  1161. .name = "dsi1pll_post_bit_div",
  1162. .parent_names = (const char *[]){"dsi1pll_bitclk_src"},
  1163. .num_parents = 1,
  1164. .flags = CLK_GET_RATE_NOCACHE,
  1165. .ops = &clk_fixed_factor_ops,
  1166. },
  1167. };
  1168. static struct clk_regmap_mux dsi0pll_byteclk_mux = {
  1169. .shift = 0,
  1170. .width = 1,
  1171. .clkr = {
  1172. .hw.init = &(struct clk_init_data){
  1173. .name = "dsi0_phy_pll_out_byteclk",
  1174. .parent_names = (const char *[]){"dsi0pll_byteclk_src"},
  1175. .num_parents = 1,
  1176. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1177. .ops = &clk_regmap_mux_closest_ops,
  1178. },
  1179. },
  1180. };
  1181. static struct clk_regmap_mux dsi1pll_byteclk_mux = {
  1182. .shift = 0,
  1183. .width = 1,
  1184. .clkr = {
  1185. .hw.init = &(struct clk_init_data){
  1186. .name = "dsi1_phy_pll_out_byteclk",
  1187. .parent_names = (const char *[]){"dsi1pll_byteclk_src"},
  1188. .num_parents = 1,
  1189. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1190. .ops = &clk_regmap_mux_closest_ops,
  1191. },
  1192. },
  1193. };
  1194. static struct clk_regmap_mux dsi0pll_pclk_src_mux = {
  1195. .reg = PHY_CMN_CLK_CFG1,
  1196. .shift = 0,
  1197. .width = 2,
  1198. .clkr = {
  1199. .hw.init = &(struct clk_init_data){
  1200. .name = "dsi0pll_pclk_src_mux",
  1201. .parent_names = (const char *[]){"dsi0pll_bitclk_src",
  1202. "dsi0pll_post_bit_div",
  1203. "dsi0pll_pll_out_div",
  1204. "dsi0pll_post_vco_div"},
  1205. .num_parents = 4,
  1206. .flags = CLK_GET_RATE_NOCACHE,
  1207. .ops = &clk_regmap_mux_closest_ops,
  1208. },
  1209. },
  1210. };
  1211. static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
  1212. .reg = PHY_CMN_CLK_CFG1,
  1213. .shift = 0,
  1214. .width = 2,
  1215. .clkr = {
  1216. .hw.init = &(struct clk_init_data){
  1217. .name = "dsi1pll_pclk_src_mux",
  1218. .parent_names = (const char *[]){"dsi1pll_bitclk_src",
  1219. "dsi1pll_post_bit_div",
  1220. "dsi1pll_pll_out_div",
  1221. "dsi1pll_post_vco_div"},
  1222. .num_parents = 4,
  1223. .flags = CLK_GET_RATE_NOCACHE,
  1224. .ops = &clk_regmap_mux_closest_ops,
  1225. },
  1226. },
  1227. };
  1228. static struct clk_regmap_div dsi0pll_pclk_src = {
  1229. .shift = 0,
  1230. .width = 4,
  1231. .clkr = {
  1232. .hw.init = &(struct clk_init_data){
  1233. .name = "dsi0pll_pclk_src",
  1234. .parent_names = (const char *[]){
  1235. "dsi0pll_pclk_src_mux"},
  1236. .num_parents = 1,
  1237. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1238. .ops = &clk_regmap_div_ops,
  1239. },
  1240. },
  1241. };
  1242. static struct clk_regmap_div dsi1pll_pclk_src = {
  1243. .shift = 0,
  1244. .width = 4,
  1245. .clkr = {
  1246. .hw.init = &(struct clk_init_data){
  1247. .name = "dsi1pll_pclk_src",
  1248. .parent_names = (const char *[]){
  1249. "dsi1pll_pclk_src_mux"},
  1250. .num_parents = 1,
  1251. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1252. .ops = &clk_regmap_div_ops,
  1253. },
  1254. },
  1255. };
  1256. static struct clk_regmap_mux dsi0pll_pclk_mux = {
  1257. .shift = 0,
  1258. .width = 1,
  1259. .clkr = {
  1260. .hw.init = &(struct clk_init_data){
  1261. .name = "dsi0_phy_pll_out_dsiclk",
  1262. .parent_names = (const char *[]){"dsi0pll_pclk_src"},
  1263. .num_parents = 1,
  1264. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1265. .ops = &clk_regmap_mux_closest_ops,
  1266. },
  1267. },
  1268. };
  1269. static struct clk_regmap_mux dsi1pll_pclk_mux = {
  1270. .shift = 0,
  1271. .width = 1,
  1272. .clkr = {
  1273. .hw.init = &(struct clk_init_data){
  1274. .name = "dsi1_phy_pll_out_dsiclk",
  1275. .parent_names = (const char *[]){"dsi1pll_pclk_src"},
  1276. .num_parents = 1,
  1277. .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
  1278. .ops = &clk_regmap_mux_closest_ops,
  1279. },
  1280. },
  1281. };
  1282. static struct clk_hw *mdss_dsi_pllcc_10nm[] = {
  1283. [VCO_CLK_0] = &dsi0pll_vco_clk.hw,
  1284. [PLL_OUT_DIV_0_CLK] = &dsi0pll_pll_out_div.clkr.hw,
  1285. [BITCLK_SRC_0_CLK] = &dsi0pll_bitclk_src.clkr.hw,
  1286. [BYTECLK_SRC_0_CLK] = &dsi0pll_byteclk_src.hw,
  1287. [POST_BIT_DIV_0_CLK] = &dsi0pll_post_bit_div.hw,
  1288. [POST_VCO_DIV_0_CLK] = &dsi0pll_post_vco_div.hw,
  1289. [BYTECLK_MUX_0_CLK] = &dsi0pll_byteclk_mux.clkr.hw,
  1290. [PCLK_SRC_MUX_0_CLK] = &dsi0pll_pclk_src_mux.clkr.hw,
  1291. [PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw,
  1292. [PCLK_MUX_0_CLK] = &dsi0pll_pclk_mux.clkr.hw,
  1293. [VCO_CLK_1] = &dsi1pll_vco_clk.hw,
  1294. [PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw,
  1295. [BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw,
  1296. [BYTECLK_SRC_1_CLK] = &dsi1pll_byteclk_src.hw,
  1297. [POST_BIT_DIV_1_CLK] = &dsi1pll_post_bit_div.hw,
  1298. [POST_VCO_DIV_1_CLK] = &dsi1pll_post_vco_div.hw,
  1299. [BYTECLK_MUX_1_CLK] = &dsi1pll_byteclk_mux.clkr.hw,
  1300. [PCLK_SRC_MUX_1_CLK] = &dsi1pll_pclk_src_mux.clkr.hw,
  1301. [PCLK_SRC_1_CLK] = &dsi1pll_pclk_src.clkr.hw,
  1302. [PCLK_MUX_1_CLK] = &dsi1pll_pclk_mux.clkr.hw,
  1303. };
  1304. int dsi_pll_clock_register_10nm(struct platform_device *pdev,
  1305. struct mdss_pll_resources *pll_res)
  1306. {
  1307. int rc = 0, ndx, i;
  1308. struct clk *clk;
  1309. struct clk_onecell_data *clk_data;
  1310. int num_clks = ARRAY_SIZE(mdss_dsi_pllcc_10nm);
  1311. struct regmap *rmap;
  1312. ndx = pll_res->index;
  1313. if (ndx >= DSI_PLL_MAX) {
  1314. pr_err("pll index(%d) NOT supported\n", ndx);
  1315. return -EINVAL;
  1316. }
  1317. pll_rsc_db[ndx] = pll_res;
  1318. plls[ndx].rsc = pll_res;
  1319. pll_res->priv = &plls[ndx];
  1320. pll_res->vco_delay = VCO_DELAY_USEC;
  1321. clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
  1322. if (!clk_data)
  1323. return -ENOMEM;
  1324. clk_data->clks = devm_kcalloc(&pdev->dev, num_clks,
  1325. sizeof(struct clk *), GFP_KERNEL);
  1326. if (!clk_data->clks)
  1327. return -ENOMEM;
  1328. clk_data->clk_num = num_clks;
  1329. /* Establish client data */
  1330. if (ndx == 0) {
  1331. rmap = devm_regmap_init(&pdev->dev, &pll_regmap_bus,
  1332. pll_res, &dsi_pll_10nm_config);
  1333. dsi0pll_pll_out_div.clkr.regmap = rmap;
  1334. rmap = devm_regmap_init(&pdev->dev, &bitclk_src_regmap_bus,
  1335. pll_res, &dsi_pll_10nm_config);
  1336. dsi0pll_bitclk_src.clkr.regmap = rmap;
  1337. rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
  1338. pll_res, &dsi_pll_10nm_config);
  1339. dsi0pll_pclk_src.clkr.regmap = rmap;
  1340. rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
  1341. pll_res, &dsi_pll_10nm_config);
  1342. dsi0pll_pclk_mux.clkr.regmap = rmap;
  1343. rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,
  1344. pll_res, &dsi_pll_10nm_config);
  1345. dsi0pll_pclk_src_mux.clkr.regmap = rmap;
  1346. rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
  1347. pll_res, &dsi_pll_10nm_config);
  1348. dsi0pll_byteclk_mux.clkr.regmap = rmap;
  1349. dsi0pll_vco_clk.priv = pll_res;
  1350. for (i = VCO_CLK_0; i <= PCLK_MUX_0_CLK; i++) {
  1351. clk = devm_clk_register(&pdev->dev,
  1352. mdss_dsi_pllcc_10nm[i]);
  1353. if (IS_ERR(clk)) {
  1354. pr_err("clk registration failed for DSI clock:%d\n",
  1355. pll_res->index);
  1356. rc = -EINVAL;
  1357. goto clk_register_fail;
  1358. }
  1359. clk_data->clks[i] = clk;
  1360. }
  1361. rc = of_clk_add_provider(pdev->dev.of_node,
  1362. of_clk_src_onecell_get, clk_data);
  1363. } else {
  1364. rmap = devm_regmap_init(&pdev->dev, &pll_regmap_bus,
  1365. pll_res, &dsi_pll_10nm_config);
  1366. dsi1pll_pll_out_div.clkr.regmap = rmap;
  1367. rmap = devm_regmap_init(&pdev->dev, &bitclk_src_regmap_bus,
  1368. pll_res, &dsi_pll_10nm_config);
  1369. dsi1pll_bitclk_src.clkr.regmap = rmap;
  1370. rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
  1371. pll_res, &dsi_pll_10nm_config);
  1372. dsi1pll_pclk_src.clkr.regmap = rmap;
  1373. rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
  1374. pll_res, &dsi_pll_10nm_config);
  1375. dsi1pll_pclk_mux.clkr.regmap = rmap;
  1376. rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,
  1377. pll_res, &dsi_pll_10nm_config);
  1378. dsi1pll_pclk_src_mux.clkr.regmap = rmap;
  1379. rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
  1380. pll_res, &dsi_pll_10nm_config);
  1381. dsi1pll_byteclk_mux.clkr.regmap = rmap;
  1382. dsi1pll_vco_clk.priv = pll_res;
  1383. for (i = VCO_CLK_1; i <= PCLK_MUX_1_CLK; i++) {
  1384. clk = devm_clk_register(&pdev->dev,
  1385. mdss_dsi_pllcc_10nm[i]);
  1386. if (IS_ERR(clk)) {
  1387. pr_err("clk registration failed for DSI clock:%d\n",
  1388. pll_res->index);
  1389. rc = -EINVAL;
  1390. goto clk_register_fail;
  1391. }
  1392. clk_data->clks[i] = clk;
  1393. }
  1394. rc = of_clk_add_provider(pdev->dev.of_node,
  1395. of_clk_src_onecell_get, clk_data);
  1396. }
  1397. if (!rc) {
  1398. pr_info("Registered DSI PLL ndx=%d, clocks successfully\n",
  1399. ndx);
  1400. return rc;
  1401. }
  1402. clk_register_fail:
  1403. return rc;
  1404. }