dp_pll_7nm.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. /*
  6. * Display Port PLL driver block diagram for branch clocks
  7. *
  8. * +------------------------------+
  9. * | DP_VCO_CLK |
  10. * | |
  11. * | +-------------------+ |
  12. * | | (DP PLL/VCO) | |
  13. * | +---------+---------+ |
  14. * | v |
  15. * | +----------+-----------+ |
  16. * | | hsclk_divsel_clk_src | |
  17. * | +----------+-----------+ |
  18. * +------------------------------+
  19. * |
  20. * +------------<---------v------------>----------+
  21. * | |
  22. * +-----v------------+ |
  23. * | dp_link_clk_src | |
  24. * | divsel_ten | |
  25. * +---------+--------+ |
  26. * | |
  27. * | |
  28. * v v
  29. * Input to DISPCC block |
  30. * for link clk, crypto clk |
  31. * and interface clock |
  32. * |
  33. * |
  34. * +--------<------------+-----------------+---<---+
  35. * | | |
  36. * +-------v------+ +--------v-----+ +--------v------+
  37. * | vco_divided | | vco_divided | | vco_divided |
  38. * | _clk_src | | _clk_src | | _clk_src |
  39. * | | | | | |
  40. * |divsel_six | | divsel_two | | divsel_four |
  41. * +-------+------+ +-----+--------+ +--------+------+
  42. * | | |
  43. * v------->----------v-------------<------v
  44. * |
  45. * +----------+---------+
  46. * | vco_divided_clk |
  47. * | _src_mux |
  48. * +---------+----------+
  49. * |
  50. * v
  51. * Input to DISPCC block
  52. * for DP pixel clock
  53. *
  54. */
  55. #define pr_fmt(fmt) "%s: " fmt, __func__
  56. #include <linux/kernel.h>
  57. #include <linux/err.h>
  58. #include <linux/delay.h>
  59. #include <dt-bindings/clock/mdss-10nm-pll-clk.h>
  60. #include "pll_drv.h"
  61. #include "dp_pll.h"
  62. #include "dp_pll_7nm.h"
  63. static struct dp_pll_db_7nm dp_pdb_7nm;
  64. static struct clk_ops mux_clk_ops;
  65. static struct regmap_config dp_pll_7nm_cfg = {
  66. .reg_bits = 32,
  67. .reg_stride = 4,
  68. .val_bits = 32,
  69. .max_register = 0x910,
  70. };
  71. static struct regmap_bus dp_pixel_mux_regmap_ops = {
  72. .reg_write = dp_mux_set_parent_7nm,
  73. .reg_read = dp_mux_get_parent_7nm,
  74. };
  75. /* Op structures */
  76. static const struct clk_ops dp_7nm_vco_clk_ops = {
  77. .recalc_rate = dp_vco_recalc_rate_7nm,
  78. .set_rate = dp_vco_set_rate_7nm,
  79. .round_rate = dp_vco_round_rate_7nm,
  80. .prepare = dp_vco_prepare_7nm,
  81. .unprepare = dp_vco_unprepare_7nm,
  82. };
  83. static struct dp_pll_vco_clk dp_vco_clk = {
  84. .min_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000,
  85. .max_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000,
  86. .hw.init = &(struct clk_init_data){
  87. .name = "dp_vco_clk",
  88. .parent_names = (const char *[]){ "xo_board" },
  89. .num_parents = 1,
  90. .ops = &dp_7nm_vco_clk_ops,
  91. },
  92. };
  93. static struct clk_fixed_factor dp_link_clk_divsel_ten = {
  94. .div = 10,
  95. .mult = 1,
  96. .hw.init = &(struct clk_init_data){
  97. .name = "dp_link_clk_divsel_ten",
  98. .parent_names =
  99. (const char *[]){ "dp_vco_clk" },
  100. .num_parents = 1,
  101. .flags = CLK_SET_RATE_PARENT,
  102. .ops = &clk_fixed_factor_ops,
  103. },
  104. };
  105. static struct clk_fixed_factor dp_vco_divsel_two_clk_src = {
  106. .div = 2,
  107. .mult = 1,
  108. .hw.init = &(struct clk_init_data){
  109. .name = "dp_vco_divsel_two_clk_src",
  110. .parent_names =
  111. (const char *[]){ "dp_vco_clk" },
  112. .num_parents = 1,
  113. .ops = &clk_fixed_factor_ops,
  114. },
  115. };
  116. static struct clk_fixed_factor dp_vco_divsel_four_clk_src = {
  117. .div = 4,
  118. .mult = 1,
  119. .hw.init = &(struct clk_init_data){
  120. .name = "dp_vco_divsel_four_clk_src",
  121. .parent_names =
  122. (const char *[]){ "dp_vco_clk" },
  123. .num_parents = 1,
  124. .ops = &clk_fixed_factor_ops,
  125. },
  126. };
  127. static struct clk_fixed_factor dp_vco_divsel_six_clk_src = {
  128. .div = 6,
  129. .mult = 1,
  130. .hw.init = &(struct clk_init_data){
  131. .name = "dp_vco_divsel_six_clk_src",
  132. .parent_names =
  133. (const char *[]){ "dp_vco_clk" },
  134. .num_parents = 1,
  135. .ops = &clk_fixed_factor_ops,
  136. },
  137. };
  138. static int clk_mux_determine_rate(struct clk_hw *hw,
  139. struct clk_rate_request *req)
  140. {
  141. int ret = 0;
  142. if (!hw || !req) {
  143. pr_err("Invalid input parameters\n");
  144. return -EINVAL;
  145. }
  146. ret = __clk_mux_determine_rate_closest(hw, req);
  147. if (ret)
  148. return ret;
  149. /* Set the new parent of mux if there is a new valid parent */
  150. if (hw->clk && req->best_parent_hw->clk)
  151. clk_set_parent(hw->clk, req->best_parent_hw->clk);
  152. return 0;
  153. }
  154. static unsigned long mux_recalc_rate(struct clk_hw *hw,
  155. unsigned long parent_rate)
  156. {
  157. struct clk *div_clk = NULL, *vco_clk = NULL;
  158. struct dp_pll_vco_clk *vco = NULL;
  159. if (!hw) {
  160. pr_err("Invalid input parameter\n");
  161. return 0;
  162. }
  163. div_clk = clk_get_parent(hw->clk);
  164. if (!div_clk)
  165. return 0;
  166. vco_clk = clk_get_parent(div_clk);
  167. if (!vco_clk)
  168. return 0;
  169. vco = to_dp_vco_hw(__clk_get_hw(vco_clk));
  170. if (!vco)
  171. return 0;
  172. if (vco->rate == DP_VCO_HSCLK_RATE_8100MHZDIV1000)
  173. return (vco->rate / 6);
  174. else if (vco->rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000)
  175. return (vco->rate / 4);
  176. else
  177. return (vco->rate / 2);
  178. }
  179. static struct clk_regmap_mux dp_vco_divided_clk_src_mux = {
  180. .reg = 0x64,
  181. .shift = 0,
  182. .width = 2,
  183. .clkr = {
  184. .hw.init = &(struct clk_init_data){
  185. .name = "dp_vco_divided_clk_src_mux",
  186. .parent_names =
  187. (const char *[]){"dp_vco_divsel_two_clk_src",
  188. "dp_vco_divsel_four_clk_src",
  189. "dp_vco_divsel_six_clk_src"},
  190. .num_parents = 3,
  191. .ops = &mux_clk_ops,
  192. .flags = CLK_SET_RATE_PARENT,
  193. },
  194. },
  195. };
  196. static struct clk_hw *mdss_dp_pllcc_7nm[] = {
  197. [DP_VCO_CLK] = &dp_vco_clk.hw,
  198. [DP_LINK_CLK_DIVSEL_TEN] = &dp_link_clk_divsel_ten.hw,
  199. [DP_VCO_DIVIDED_TWO_CLK_SRC] = &dp_vco_divsel_two_clk_src.hw,
  200. [DP_VCO_DIVIDED_FOUR_CLK_SRC] = &dp_vco_divsel_four_clk_src.hw,
  201. [DP_VCO_DIVIDED_SIX_CLK_SRC] = &dp_vco_divsel_six_clk_src.hw,
  202. [DP_VCO_DIVIDED_CLK_SRC_MUX] = &dp_vco_divided_clk_src_mux.clkr.hw,
  203. };
  204. int dp_pll_clock_register_7nm(struct platform_device *pdev,
  205. struct mdss_pll_resources *pll_res)
  206. {
  207. int rc = -ENOTSUPP, i = 0;
  208. struct clk_onecell_data *clk_data;
  209. struct clk *clk;
  210. struct regmap *regmap;
  211. int num_clks = ARRAY_SIZE(mdss_dp_pllcc_7nm);
  212. clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
  213. if (!clk_data)
  214. return -ENOMEM;
  215. clk_data->clks = devm_kcalloc(&pdev->dev, num_clks,
  216. sizeof(struct clk *), GFP_KERNEL);
  217. if (!clk_data->clks)
  218. return -ENOMEM;
  219. clk_data->clk_num = num_clks;
  220. pll_res->priv = &dp_pdb_7nm;
  221. dp_pdb_7nm.pll = pll_res;
  222. /* Set client data for vco, mux and div clocks */
  223. regmap = devm_regmap_init(&pdev->dev, &dp_pixel_mux_regmap_ops,
  224. pll_res, &dp_pll_7nm_cfg);
  225. dp_vco_divided_clk_src_mux.clkr.regmap = regmap;
  226. mux_clk_ops = clk_regmap_mux_closest_ops;
  227. mux_clk_ops.determine_rate = clk_mux_determine_rate;
  228. mux_clk_ops.recalc_rate = mux_recalc_rate;
  229. dp_vco_clk.priv = pll_res;
  230. for (i = DP_VCO_CLK; i <= DP_VCO_DIVIDED_CLK_SRC_MUX; i++) {
  231. pr_debug("reg clk: %d index: %d\n", i, pll_res->index);
  232. clk = devm_clk_register(&pdev->dev, mdss_dp_pllcc_7nm[i]);
  233. if (IS_ERR(clk)) {
  234. pr_err("clk registration failed for DP: %d\n",
  235. pll_res->index);
  236. rc = -EINVAL;
  237. goto clk_reg_fail;
  238. }
  239. clk_data->clks[i] = clk;
  240. }
  241. rc = of_clk_add_provider(pdev->dev.of_node,
  242. of_clk_src_onecell_get, clk_data);
  243. if (rc) {
  244. pr_err("Clock register failed rc=%d\n", rc);
  245. rc = -EPROBE_DEFER;
  246. goto clk_reg_fail;
  247. } else {
  248. pr_debug("SUCCESS\n");
  249. }
  250. return rc;
  251. clk_reg_fail:
  252. return rc;
  253. }