sde_hw_catalog.c 119 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  6. #include <linux/slab.h>
  7. #include <linux/of_address.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/soc/qcom/llcc-qcom.h>
  10. #include <linux/pm_qos.h>
  11. #include "sde_hw_mdss.h"
  12. #include "sde_hw_catalog.h"
  13. #include "sde_hw_catalog_format.h"
  14. #include "sde_kms.h"
  15. #include "sde_hw_uidle.h"
  16. #include "sde_connector.h"
  17. /*************************************************************
  18. * MACRO DEFINITION
  19. *************************************************************/
  20. /**
  21. * Max hardware block in certain hardware. For ex: sspp pipes
  22. * can have QSEED, pcc, igc, pa, csc, qos entries, etc. This count is
  23. * 64 based on software design. It should be increased if any of the
  24. * hardware block has more subblocks.
  25. */
  26. #define MAX_SDE_HW_BLK 64
  27. /* each entry will have register address and bit offset in that register */
  28. #define MAX_BIT_OFFSET 2
  29. /* default line width for sspp, mixer, ds (input), wb */
  30. #define DEFAULT_SDE_LINE_WIDTH 2048
  31. /* default output line width for ds */
  32. #define DEFAULT_SDE_OUTPUT_LINE_WIDTH 2560
  33. /* max mixer blend stages */
  34. #define DEFAULT_SDE_MIXER_BLENDSTAGES 7
  35. /* max bank bit for macro tile and ubwc format */
  36. #define DEFAULT_SDE_HIGHEST_BANK_BIT 15
  37. /* default ubwc version */
  38. #define DEFAULT_SDE_UBWC_VERSION SDE_HW_UBWC_VER_10
  39. /* default ubwc static config register value */
  40. #define DEFAULT_SDE_UBWC_STATIC 0x0
  41. /* default ubwc swizzle register value */
  42. #define DEFAULT_SDE_UBWC_SWIZZLE 0x0
  43. /* default ubwc macrotile mode value */
  44. #define DEFAULT_SDE_UBWC_MACROTILE_MODE 0x0
  45. /* default hardware block size if dtsi entry is not present */
  46. #define DEFAULT_SDE_HW_BLOCK_LEN 0x100
  47. /* total number of intf - dp, dsi, hdmi */
  48. #define INTF_COUNT 3
  49. #define MAX_UPSCALE_RATIO 20
  50. #define MAX_DOWNSCALE_RATIO 4
  51. #define SSPP_UNITY_SCALE 1
  52. #define MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR 11
  53. #define MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR 5
  54. #define MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT 4
  55. #define MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT 1088
  56. #define MAX_HORZ_DECIMATION 4
  57. #define MAX_VERT_DECIMATION 4
  58. #define MAX_SPLIT_DISPLAY_CTL 2
  59. #define MAX_PP_SPLIT_DISPLAY_CTL 1
  60. #define MDSS_BASE_OFFSET 0x0
  61. #define ROT_LM_OFFSET 3
  62. #define LINE_LM_OFFSET 5
  63. #define LINE_MODE_WB_OFFSET 2
  64. /**
  65. * these configurations are decided based on max mdp clock. It accounts
  66. * for max and min display resolution based on virtual hardware resource
  67. * support.
  68. */
  69. #define MAX_DISPLAY_HEIGHT_WITH_DECIMATION 2160
  70. #define MAX_DISPLAY_HEIGHT 5120
  71. #define MIN_DISPLAY_HEIGHT 0
  72. #define MIN_DISPLAY_WIDTH 0
  73. #define MAX_LM_PER_DISPLAY 2
  74. /* maximum XIN halt timeout in usec */
  75. #define VBIF_XIN_HALT_TIMEOUT 0x4000
  76. #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
  77. /* access property value based on prop_type and hardware index */
  78. #define PROP_VALUE_ACCESS(p, i, j) ((p + i)->value[j])
  79. /*
  80. * access element within PROP_TYPE_BIT_OFFSET_ARRAYs based on prop_type,
  81. * hardware index and offset array index
  82. */
  83. #define PROP_BITVALUE_ACCESS(p, i, j, k) ((p + i)->bit_value[j][k])
  84. #define DEFAULT_SBUF_HEADROOM (20)
  85. #define DEFAULT_SBUF_PREFILL (128)
  86. /*
  87. * Default parameter values
  88. */
  89. #define DEFAULT_MAX_BW_HIGH 7000000
  90. #define DEFAULT_MAX_BW_LOW 7000000
  91. #define DEFAULT_UNDERSIZED_PREFILL_LINES 2
  92. #define DEFAULT_XTRA_PREFILL_LINES 2
  93. #define DEFAULT_DEST_SCALE_PREFILL_LINES 3
  94. #define DEFAULT_MACROTILE_PREFILL_LINES 4
  95. #define DEFAULT_YUV_NV12_PREFILL_LINES 8
  96. #define DEFAULT_LINEAR_PREFILL_LINES 1
  97. #define DEFAULT_DOWNSCALING_PREFILL_LINES 1
  98. #define DEFAULT_CORE_IB_FF "6.0"
  99. #define DEFAULT_CORE_CLK_FF "1.0"
  100. #define DEFAULT_COMP_RATIO_RT \
  101. "NV12/5/1/1.23 AB24/5/1/1.23 XB24/5/1/1.23"
  102. #define DEFAULT_COMP_RATIO_NRT \
  103. "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25"
  104. #define DEFAULT_MAX_PER_PIPE_BW 2400000
  105. #define DEFAULT_AMORTIZABLE_THRESHOLD 25
  106. #define DEFAULT_MNOC_PORTS 2
  107. #define DEFAULT_AXI_BUS_WIDTH 32
  108. #define DEFAULT_CPU_MASK 0
  109. #define DEFAULT_CPU_DMA_LATENCY PM_QOS_DEFAULT_VALUE
  110. /* Uidle values */
  111. #define SDE_UIDLE_FAL10_EXIT_CNT 128
  112. #define SDE_UIDLE_FAL10_EXIT_DANGER 4
  113. #define SDE_UIDLE_FAL10_DANGER 6
  114. #define SDE_UIDLE_FAL10_TARGET_IDLE 50
  115. #define SDE_UIDLE_FAL1_TARGET_IDLE 10
  116. #define SDE_UIDLE_FAL10_THRESHOLD 12
  117. #define SDE_UIDLE_MAX_DWNSCALE 1500
  118. #define SDE_UIDLE_MAX_FPS 60
  119. /*************************************************************
  120. * DTSI PROPERTY INDEX
  121. *************************************************************/
  122. enum {
  123. HW_OFF,
  124. HW_LEN,
  125. HW_DISP,
  126. HW_PROP_MAX,
  127. };
  128. enum sde_prop {
  129. SDE_OFF,
  130. SDE_LEN,
  131. SSPP_LINEWIDTH,
  132. MIXER_LINEWIDTH,
  133. MIXER_BLEND,
  134. WB_LINEWIDTH,
  135. BANK_BIT,
  136. UBWC_VERSION,
  137. UBWC_STATIC,
  138. UBWC_SWIZZLE,
  139. QSEED_TYPE,
  140. CSC_TYPE,
  141. PANIC_PER_PIPE,
  142. SRC_SPLIT,
  143. DIM_LAYER,
  144. SMART_DMA_REV,
  145. IDLE_PC,
  146. DEST_SCALER,
  147. SMART_PANEL_ALIGN_MODE,
  148. MACROTILE_MODE,
  149. UBWC_BW_CALC_VERSION,
  150. PIPE_ORDER_VERSION,
  151. SEC_SID_MASK,
  152. SDE_PROP_MAX,
  153. };
  154. enum {
  155. PERF_MAX_BW_LOW,
  156. PERF_MAX_BW_HIGH,
  157. PERF_MIN_CORE_IB,
  158. PERF_MIN_LLCC_IB,
  159. PERF_MIN_DRAM_IB,
  160. PERF_CORE_IB_FF,
  161. PERF_CORE_CLK_FF,
  162. PERF_COMP_RATIO_RT,
  163. PERF_COMP_RATIO_NRT,
  164. PERF_UNDERSIZED_PREFILL_LINES,
  165. PERF_DEST_SCALE_PREFILL_LINES,
  166. PERF_MACROTILE_PREFILL_LINES,
  167. PERF_YUV_NV12_PREFILL_LINES,
  168. PERF_LINEAR_PREFILL_LINES,
  169. PERF_DOWNSCALING_PREFILL_LINES,
  170. PERF_XTRA_PREFILL_LINES,
  171. PERF_AMORTIZABLE_THRESHOLD,
  172. PERF_DANGER_LUT,
  173. PERF_SAFE_LUT_LINEAR,
  174. PERF_SAFE_LUT_MACROTILE,
  175. PERF_SAFE_LUT_NRT,
  176. PERF_SAFE_LUT_CWB,
  177. PERF_QOS_LUT_LINEAR,
  178. PERF_QOS_LUT_MACROTILE,
  179. PERF_QOS_LUT_NRT,
  180. PERF_QOS_LUT_CWB,
  181. PERF_CDP_SETTING,
  182. PERF_CPU_MASK,
  183. PERF_CPU_DMA_LATENCY,
  184. PERF_QOS_LUT_MACROTILE_QSEED,
  185. PERF_SAFE_LUT_MACROTILE_QSEED,
  186. PERF_NUM_MNOC_PORTS,
  187. PERF_AXI_BUS_WIDTH,
  188. PERF_PROP_MAX,
  189. };
  190. enum {
  191. SSPP_OFF,
  192. SSPP_SIZE,
  193. SSPP_TYPE,
  194. SSPP_XIN,
  195. SSPP_CLK_CTRL,
  196. SSPP_CLK_STATUS,
  197. SSPP_SCALE_SIZE,
  198. SSPP_VIG_BLOCKS,
  199. SSPP_RGB_BLOCKS,
  200. SSPP_DMA_BLOCKS,
  201. SSPP_EXCL_RECT,
  202. SSPP_SMART_DMA,
  203. SSPP_MAX_PER_PIPE_BW,
  204. SSPP_MAX_PER_PIPE_BW_HIGH,
  205. SSPP_PROP_MAX,
  206. };
  207. enum {
  208. VIG_QSEED_OFF,
  209. VIG_QSEED_LEN,
  210. VIG_CSC_OFF,
  211. VIG_HSIC_PROP,
  212. VIG_MEMCOLOR_PROP,
  213. VIG_PCC_PROP,
  214. VIG_GAMUT_PROP,
  215. VIG_IGC_PROP,
  216. VIG_INVERSE_PMA,
  217. VIG_PROP_MAX,
  218. };
  219. enum {
  220. RGB_SCALER_OFF,
  221. RGB_SCALER_LEN,
  222. RGB_PCC_PROP,
  223. RGB_PROP_MAX,
  224. };
  225. enum {
  226. DMA_IGC_PROP,
  227. DMA_GC_PROP,
  228. DMA_DGM_INVERSE_PMA,
  229. DMA_CSC_OFF,
  230. DMA_PROP_MAX,
  231. };
  232. enum {
  233. INTF_OFF,
  234. INTF_LEN,
  235. INTF_PREFETCH,
  236. INTF_TYPE,
  237. INTF_PROP_MAX,
  238. };
  239. enum {
  240. PP_OFF,
  241. PP_LEN,
  242. TE_OFF,
  243. TE_LEN,
  244. TE2_OFF,
  245. TE2_LEN,
  246. PP_SLAVE,
  247. DITHER_OFF,
  248. DITHER_LEN,
  249. DITHER_VER,
  250. PP_MERGE_3D_ID,
  251. PP_PROP_MAX,
  252. };
  253. enum {
  254. DSC_OFF,
  255. DSC_LEN,
  256. DSC_PROP_MAX,
  257. };
  258. enum {
  259. DS_TOP_OFF,
  260. DS_TOP_LEN,
  261. DS_TOP_INPUT_LINEWIDTH,
  262. DS_TOP_OUTPUT_LINEWIDTH,
  263. DS_TOP_PROP_MAX,
  264. };
  265. enum {
  266. DS_OFF,
  267. DS_LEN,
  268. DS_PROP_MAX,
  269. };
  270. enum {
  271. DSPP_TOP_OFF,
  272. DSPP_TOP_SIZE,
  273. DSPP_TOP_PROP_MAX,
  274. };
  275. enum {
  276. DSPP_OFF,
  277. DSPP_SIZE,
  278. DSPP_BLOCKS,
  279. DSPP_PROP_MAX,
  280. };
  281. enum {
  282. DSPP_IGC_PROP,
  283. DSPP_PCC_PROP,
  284. DSPP_GC_PROP,
  285. DSPP_HSIC_PROP,
  286. DSPP_MEMCOLOR_PROP,
  287. DSPP_SIXZONE_PROP,
  288. DSPP_GAMUT_PROP,
  289. DSPP_DITHER_PROP,
  290. DSPP_HIST_PROP,
  291. DSPP_VLUT_PROP,
  292. DSPP_BLOCKS_PROP_MAX,
  293. };
  294. enum {
  295. AD_OFF,
  296. AD_VERSION,
  297. AD_PROP_MAX,
  298. };
  299. enum {
  300. LTM_OFF,
  301. LTM_VERSION,
  302. LTM_PROP_MAX,
  303. };
  304. enum {
  305. MIXER_OFF,
  306. MIXER_LEN,
  307. MIXER_PAIR_MASK,
  308. MIXER_BLOCKS,
  309. MIXER_DISP,
  310. MIXER_CWB,
  311. MIXER_PROP_MAX,
  312. };
  313. enum {
  314. MIXER_GC_PROP,
  315. MIXER_BLOCKS_PROP_MAX,
  316. };
  317. enum {
  318. MIXER_BLEND_OP_OFF,
  319. MIXER_BLEND_PROP_MAX,
  320. };
  321. enum {
  322. WB_OFF,
  323. WB_LEN,
  324. WB_ID,
  325. WB_XIN_ID,
  326. WB_CLK_CTRL,
  327. WB_PROP_MAX,
  328. };
  329. enum {
  330. VBIF_OFF,
  331. VBIF_LEN,
  332. VBIF_ID,
  333. VBIF_DEFAULT_OT_RD_LIMIT,
  334. VBIF_DEFAULT_OT_WR_LIMIT,
  335. VBIF_DYNAMIC_OT_RD_LIMIT,
  336. VBIF_DYNAMIC_OT_WR_LIMIT,
  337. VBIF_MEMTYPE_0,
  338. VBIF_MEMTYPE_1,
  339. VBIF_QOS_RT_REMAP,
  340. VBIF_QOS_NRT_REMAP,
  341. VBIF_QOS_CWB_REMAP,
  342. VBIF_QOS_LUTDMA_REMAP,
  343. VBIF_PROP_MAX,
  344. };
  345. enum {
  346. UIDLE_OFF,
  347. UIDLE_LEN,
  348. UIDLE_PROP_MAX,
  349. };
  350. enum {
  351. REG_DMA_OFF,
  352. REG_DMA_VERSION,
  353. REG_DMA_TRIGGER_OFF,
  354. REG_DMA_BROADCAST_DISABLED,
  355. REG_DMA_XIN_ID,
  356. REG_DMA_CLK_CTRL,
  357. REG_DMA_PROP_MAX
  358. };
  359. /*************************************************************
  360. * dts property definition
  361. *************************************************************/
  362. enum prop_type {
  363. PROP_TYPE_BOOL,
  364. PROP_TYPE_U32,
  365. PROP_TYPE_U32_ARRAY,
  366. PROP_TYPE_STRING,
  367. PROP_TYPE_STRING_ARRAY,
  368. PROP_TYPE_BIT_OFFSET_ARRAY,
  369. PROP_TYPE_NODE,
  370. };
  371. struct sde_prop_type {
  372. /* use property index from enum property for readability purpose */
  373. u8 id;
  374. /* it should be property name based on dtsi documentation */
  375. char *prop_name;
  376. /**
  377. * if property is marked mandatory then it will fail parsing
  378. * when property is not present
  379. */
  380. u32 is_mandatory;
  381. /* property type based on "enum prop_type" */
  382. enum prop_type type;
  383. };
  384. struct sde_prop_value {
  385. u32 value[MAX_SDE_HW_BLK];
  386. u32 bit_value[MAX_SDE_HW_BLK][MAX_BIT_OFFSET];
  387. };
  388. /*************************************************************
  389. * dts property list
  390. *************************************************************/
  391. static struct sde_prop_type sde_prop[] = {
  392. {SDE_OFF, "qcom,sde-off", true, PROP_TYPE_U32},
  393. {SDE_LEN, "qcom,sde-len", false, PROP_TYPE_U32},
  394. {SSPP_LINEWIDTH, "qcom,sde-sspp-linewidth", false, PROP_TYPE_U32},
  395. {MIXER_LINEWIDTH, "qcom,sde-mixer-linewidth", false, PROP_TYPE_U32},
  396. {MIXER_BLEND, "qcom,sde-mixer-blendstages", false, PROP_TYPE_U32},
  397. {WB_LINEWIDTH, "qcom,sde-wb-linewidth", false, PROP_TYPE_U32},
  398. {BANK_BIT, "qcom,sde-highest-bank-bit", false, PROP_TYPE_U32},
  399. {UBWC_VERSION, "qcom,sde-ubwc-version", false, PROP_TYPE_U32},
  400. {UBWC_STATIC, "qcom,sde-ubwc-static", false, PROP_TYPE_U32},
  401. {UBWC_SWIZZLE, "qcom,sde-ubwc-swizzle", false, PROP_TYPE_U32},
  402. {QSEED_TYPE, "qcom,sde-qseed-type", false, PROP_TYPE_STRING},
  403. {CSC_TYPE, "qcom,sde-csc-type", false, PROP_TYPE_STRING},
  404. {PANIC_PER_PIPE, "qcom,sde-panic-per-pipe", false, PROP_TYPE_BOOL},
  405. {SRC_SPLIT, "qcom,sde-has-src-split", false, PROP_TYPE_BOOL},
  406. {DIM_LAYER, "qcom,sde-has-dim-layer", false, PROP_TYPE_BOOL},
  407. {SMART_DMA_REV, "qcom,sde-smart-dma-rev", false, PROP_TYPE_STRING},
  408. {IDLE_PC, "qcom,sde-has-idle-pc", false, PROP_TYPE_BOOL},
  409. {DEST_SCALER, "qcom,sde-has-dest-scaler", false, PROP_TYPE_BOOL},
  410. {SMART_PANEL_ALIGN_MODE, "qcom,sde-smart-panel-align-mode",
  411. false, PROP_TYPE_U32},
  412. {MACROTILE_MODE, "qcom,sde-macrotile-mode", false, PROP_TYPE_U32},
  413. {UBWC_BW_CALC_VERSION, "qcom,sde-ubwc-bw-calc-version", false,
  414. PROP_TYPE_U32},
  415. {PIPE_ORDER_VERSION, "qcom,sde-pipe-order-version", false,
  416. PROP_TYPE_U32},
  417. {SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY},
  418. };
  419. static struct sde_prop_type sde_perf_prop[] = {
  420. {PERF_MAX_BW_LOW, "qcom,sde-max-bw-low-kbps", false, PROP_TYPE_U32},
  421. {PERF_MAX_BW_HIGH, "qcom,sde-max-bw-high-kbps", false, PROP_TYPE_U32},
  422. {PERF_MIN_CORE_IB, "qcom,sde-min-core-ib-kbps", false, PROP_TYPE_U32},
  423. {PERF_MIN_LLCC_IB, "qcom,sde-min-llcc-ib-kbps", false, PROP_TYPE_U32},
  424. {PERF_MIN_DRAM_IB, "qcom,sde-min-dram-ib-kbps", false, PROP_TYPE_U32},
  425. {PERF_CORE_IB_FF, "qcom,sde-core-ib-ff", false, PROP_TYPE_STRING},
  426. {PERF_CORE_CLK_FF, "qcom,sde-core-clk-ff", false, PROP_TYPE_STRING},
  427. {PERF_COMP_RATIO_RT, "qcom,sde-comp-ratio-rt", false,
  428. PROP_TYPE_STRING},
  429. {PERF_COMP_RATIO_NRT, "qcom,sde-comp-ratio-nrt", false,
  430. PROP_TYPE_STRING},
  431. {PERF_UNDERSIZED_PREFILL_LINES, "qcom,sde-undersizedprefill-lines",
  432. false, PROP_TYPE_U32},
  433. {PERF_DEST_SCALE_PREFILL_LINES, "qcom,sde-dest-scaleprefill-lines",
  434. false, PROP_TYPE_U32},
  435. {PERF_MACROTILE_PREFILL_LINES, "qcom,sde-macrotileprefill-lines",
  436. false, PROP_TYPE_U32},
  437. {PERF_YUV_NV12_PREFILL_LINES, "qcom,sde-yuv-nv12prefill-lines",
  438. false, PROP_TYPE_U32},
  439. {PERF_LINEAR_PREFILL_LINES, "qcom,sde-linearprefill-lines",
  440. false, PROP_TYPE_U32},
  441. {PERF_DOWNSCALING_PREFILL_LINES, "qcom,sde-downscalingprefill-lines",
  442. false, PROP_TYPE_U32},
  443. {PERF_XTRA_PREFILL_LINES, "qcom,sde-xtra-prefill-lines",
  444. false, PROP_TYPE_U32},
  445. {PERF_AMORTIZABLE_THRESHOLD, "qcom,sde-amortizable-threshold",
  446. false, PROP_TYPE_U32},
  447. {PERF_DANGER_LUT, "qcom,sde-danger-lut", false, PROP_TYPE_U32_ARRAY},
  448. {PERF_SAFE_LUT_LINEAR, "qcom,sde-safe-lut-linear", false,
  449. PROP_TYPE_U32_ARRAY},
  450. {PERF_SAFE_LUT_MACROTILE, "qcom,sde-safe-lut-macrotile", false,
  451. PROP_TYPE_U32_ARRAY},
  452. {PERF_SAFE_LUT_NRT, "qcom,sde-safe-lut-nrt", false,
  453. PROP_TYPE_U32_ARRAY},
  454. {PERF_SAFE_LUT_CWB, "qcom,sde-safe-lut-cwb", false,
  455. PROP_TYPE_U32_ARRAY},
  456. {PERF_QOS_LUT_LINEAR, "qcom,sde-qos-lut-linear", false,
  457. PROP_TYPE_U32_ARRAY},
  458. {PERF_QOS_LUT_MACROTILE, "qcom,sde-qos-lut-macrotile", false,
  459. PROP_TYPE_U32_ARRAY},
  460. {PERF_QOS_LUT_NRT, "qcom,sde-qos-lut-nrt", false,
  461. PROP_TYPE_U32_ARRAY},
  462. {PERF_QOS_LUT_CWB, "qcom,sde-qos-lut-cwb", false,
  463. PROP_TYPE_U32_ARRAY},
  464. {PERF_CDP_SETTING, "qcom,sde-cdp-setting", false,
  465. PROP_TYPE_U32_ARRAY},
  466. {PERF_CPU_MASK, "qcom,sde-qos-cpu-mask", false, PROP_TYPE_U32},
  467. {PERF_CPU_DMA_LATENCY, "qcom,sde-qos-cpu-dma-latency", false,
  468. PROP_TYPE_U32},
  469. {PERF_QOS_LUT_MACROTILE_QSEED, "qcom,sde-qos-lut-macrotile-qseed",
  470. false, PROP_TYPE_U32_ARRAY},
  471. {PERF_SAFE_LUT_MACROTILE_QSEED, "qcom,sde-safe-lut-macrotile-qseed",
  472. false, PROP_TYPE_U32_ARRAY},
  473. {PERF_NUM_MNOC_PORTS, "qcom,sde-num-mnoc-ports",
  474. false, PROP_TYPE_U32},
  475. {PERF_AXI_BUS_WIDTH, "qcom,sde-axi-bus-width",
  476. false, PROP_TYPE_U32},
  477. };
  478. static struct sde_prop_type sspp_prop[] = {
  479. {SSPP_OFF, "qcom,sde-sspp-off", true, PROP_TYPE_U32_ARRAY},
  480. {SSPP_SIZE, "qcom,sde-sspp-src-size", false, PROP_TYPE_U32},
  481. {SSPP_TYPE, "qcom,sde-sspp-type", true, PROP_TYPE_STRING_ARRAY},
  482. {SSPP_XIN, "qcom,sde-sspp-xin-id", true, PROP_TYPE_U32_ARRAY},
  483. {SSPP_CLK_CTRL, "qcom,sde-sspp-clk-ctrl", false,
  484. PROP_TYPE_BIT_OFFSET_ARRAY},
  485. {SSPP_CLK_STATUS, "qcom,sde-sspp-clk-status", false,
  486. PROP_TYPE_BIT_OFFSET_ARRAY},
  487. {SSPP_SCALE_SIZE, "qcom,sde-sspp-scale-size", false, PROP_TYPE_U32},
  488. {SSPP_VIG_BLOCKS, "qcom,sde-sspp-vig-blocks", false, PROP_TYPE_NODE},
  489. {SSPP_RGB_BLOCKS, "qcom,sde-sspp-rgb-blocks", false, PROP_TYPE_NODE},
  490. {SSPP_DMA_BLOCKS, "qcom,sde-sspp-dma-blocks", false, PROP_TYPE_NODE},
  491. {SSPP_EXCL_RECT, "qcom,sde-sspp-excl-rect", false, PROP_TYPE_U32_ARRAY},
  492. {SSPP_SMART_DMA, "qcom,sde-sspp-smart-dma-priority", false,
  493. PROP_TYPE_U32_ARRAY},
  494. {SSPP_MAX_PER_PIPE_BW, "qcom,sde-max-per-pipe-bw-kbps", false,
  495. PROP_TYPE_U32_ARRAY},
  496. {SSPP_MAX_PER_PIPE_BW_HIGH, "qcom,sde-max-per-pipe-bw-high-kbps", false,
  497. PROP_TYPE_U32_ARRAY},
  498. };
  499. static struct sde_prop_type vig_prop[] = {
  500. {VIG_QSEED_OFF, "qcom,sde-vig-qseed-off", false, PROP_TYPE_U32},
  501. {VIG_QSEED_LEN, "qcom,sde-vig-qseed-size", false, PROP_TYPE_U32},
  502. {VIG_CSC_OFF, "qcom,sde-vig-csc-off", false, PROP_TYPE_U32},
  503. {VIG_HSIC_PROP, "qcom,sde-vig-hsic", false, PROP_TYPE_U32_ARRAY},
  504. {VIG_MEMCOLOR_PROP, "qcom,sde-vig-memcolor", false,
  505. PROP_TYPE_U32_ARRAY},
  506. {VIG_PCC_PROP, "qcom,sde-vig-pcc", false, PROP_TYPE_U32_ARRAY},
  507. {VIG_GAMUT_PROP, "qcom,sde-vig-gamut", false, PROP_TYPE_U32_ARRAY},
  508. {VIG_IGC_PROP, "qcom,sde-vig-igc", false, PROP_TYPE_U32_ARRAY},
  509. {VIG_INVERSE_PMA, "qcom,sde-vig-inverse-pma", false, PROP_TYPE_BOOL},
  510. };
  511. static struct sde_prop_type rgb_prop[] = {
  512. {RGB_SCALER_OFF, "qcom,sde-rgb-scaler-off", false, PROP_TYPE_U32},
  513. {RGB_SCALER_LEN, "qcom,sde-rgb-scaler-size", false, PROP_TYPE_U32},
  514. {RGB_PCC_PROP, "qcom,sde-rgb-pcc", false, PROP_TYPE_U32_ARRAY},
  515. };
  516. static struct sde_prop_type dma_prop[] = {
  517. {DMA_IGC_PROP, "qcom,sde-dma-igc", false, PROP_TYPE_U32_ARRAY},
  518. {DMA_GC_PROP, "qcom,sde-dma-gc", false, PROP_TYPE_U32_ARRAY},
  519. {DMA_DGM_INVERSE_PMA, "qcom,sde-dma-inverse-pma", false,
  520. PROP_TYPE_BOOL},
  521. {DMA_CSC_OFF, "qcom,sde-dma-csc-off", false, PROP_TYPE_U32},
  522. };
  523. static struct sde_prop_type ctl_prop[] = {
  524. {HW_OFF, "qcom,sde-ctl-off", true, PROP_TYPE_U32_ARRAY},
  525. {HW_LEN, "qcom,sde-ctl-size", false, PROP_TYPE_U32},
  526. {HW_DISP, "qcom,sde-ctl-display-pref", false, PROP_TYPE_STRING_ARRAY},
  527. };
  528. struct sde_prop_type mixer_blend_prop[] = {
  529. {MIXER_BLEND_OP_OFF, "qcom,sde-mixer-blend-op-off", true,
  530. PROP_TYPE_U32_ARRAY},
  531. };
  532. static struct sde_prop_type mixer_prop[] = {
  533. {MIXER_OFF, "qcom,sde-mixer-off", true, PROP_TYPE_U32_ARRAY},
  534. {MIXER_LEN, "qcom,sde-mixer-size", false, PROP_TYPE_U32},
  535. {MIXER_PAIR_MASK, "qcom,sde-mixer-pair-mask", true,
  536. PROP_TYPE_U32_ARRAY},
  537. {MIXER_BLOCKS, "qcom,sde-mixer-blocks", false, PROP_TYPE_NODE},
  538. {MIXER_DISP, "qcom,sde-mixer-display-pref", false,
  539. PROP_TYPE_STRING_ARRAY},
  540. {MIXER_CWB, "qcom,sde-mixer-cwb-pref", false,
  541. PROP_TYPE_STRING_ARRAY},
  542. };
  543. static struct sde_prop_type mixer_blocks_prop[] = {
  544. {MIXER_GC_PROP, "qcom,sde-mixer-gc", false, PROP_TYPE_U32_ARRAY},
  545. };
  546. static struct sde_prop_type dspp_top_prop[] = {
  547. {DSPP_TOP_OFF, "qcom,sde-dspp-top-off", true, PROP_TYPE_U32},
  548. {DSPP_TOP_SIZE, "qcom,sde-dspp-top-size", false, PROP_TYPE_U32},
  549. };
  550. static struct sde_prop_type dspp_prop[] = {
  551. {DSPP_OFF, "qcom,sde-dspp-off", true, PROP_TYPE_U32_ARRAY},
  552. {DSPP_SIZE, "qcom,sde-dspp-size", false, PROP_TYPE_U32},
  553. {DSPP_BLOCKS, "qcom,sde-dspp-blocks", false, PROP_TYPE_NODE},
  554. };
  555. static struct sde_prop_type dspp_blocks_prop[] = {
  556. {DSPP_IGC_PROP, "qcom,sde-dspp-igc", false, PROP_TYPE_U32_ARRAY},
  557. {DSPP_PCC_PROP, "qcom,sde-dspp-pcc", false, PROP_TYPE_U32_ARRAY},
  558. {DSPP_GC_PROP, "qcom,sde-dspp-gc", false, PROP_TYPE_U32_ARRAY},
  559. {DSPP_HSIC_PROP, "qcom,sde-dspp-hsic", false, PROP_TYPE_U32_ARRAY},
  560. {DSPP_MEMCOLOR_PROP, "qcom,sde-dspp-memcolor", false,
  561. PROP_TYPE_U32_ARRAY},
  562. {DSPP_SIXZONE_PROP, "qcom,sde-dspp-sixzone", false,
  563. PROP_TYPE_U32_ARRAY},
  564. {DSPP_GAMUT_PROP, "qcom,sde-dspp-gamut", false, PROP_TYPE_U32_ARRAY},
  565. {DSPP_DITHER_PROP, "qcom,sde-dspp-dither", false, PROP_TYPE_U32_ARRAY},
  566. {DSPP_HIST_PROP, "qcom,sde-dspp-hist", false, PROP_TYPE_U32_ARRAY},
  567. {DSPP_VLUT_PROP, "qcom,sde-dspp-vlut", false, PROP_TYPE_U32_ARRAY},
  568. };
  569. static struct sde_prop_type ad_prop[] = {
  570. {AD_OFF, "qcom,sde-dspp-ad-off", false, PROP_TYPE_U32_ARRAY},
  571. {AD_VERSION, "qcom,sde-dspp-ad-version", false, PROP_TYPE_U32},
  572. };
  573. static struct sde_prop_type ltm_prop[] = {
  574. {LTM_OFF, "qcom,sde-dspp-ltm-off", false, PROP_TYPE_U32_ARRAY},
  575. {LTM_VERSION, "qcom,sde-dspp-ltm-version", false, PROP_TYPE_U32},
  576. };
  577. static struct sde_prop_type ds_top_prop[] = {
  578. {DS_TOP_OFF, "qcom,sde-dest-scaler-top-off", false, PROP_TYPE_U32},
  579. {DS_TOP_LEN, "qcom,sde-dest-scaler-top-size", false, PROP_TYPE_U32},
  580. {DS_TOP_INPUT_LINEWIDTH, "qcom,sde-max-dest-scaler-input-linewidth",
  581. false, PROP_TYPE_U32},
  582. {DS_TOP_OUTPUT_LINEWIDTH, "qcom,sde-max-dest-scaler-output-linewidth",
  583. false, PROP_TYPE_U32},
  584. };
  585. static struct sde_prop_type ds_prop[] = {
  586. {DS_OFF, "qcom,sde-dest-scaler-off", false, PROP_TYPE_U32_ARRAY},
  587. {DS_LEN, "qcom,sde-dest-scaler-size", false, PROP_TYPE_U32},
  588. };
  589. static struct sde_prop_type pp_prop[] = {
  590. {PP_OFF, "qcom,sde-pp-off", true, PROP_TYPE_U32_ARRAY},
  591. {PP_LEN, "qcom,sde-pp-size", false, PROP_TYPE_U32},
  592. {TE_OFF, "qcom,sde-te-off", false, PROP_TYPE_U32_ARRAY},
  593. {TE_LEN, "qcom,sde-te-size", false, PROP_TYPE_U32},
  594. {TE2_OFF, "qcom,sde-te2-off", false, PROP_TYPE_U32_ARRAY},
  595. {TE2_LEN, "qcom,sde-te2-size", false, PROP_TYPE_U32},
  596. {PP_SLAVE, "qcom,sde-pp-slave", false, PROP_TYPE_U32_ARRAY},
  597. {DITHER_OFF, "qcom,sde-dither-off", false, PROP_TYPE_U32_ARRAY},
  598. {DITHER_LEN, "qcom,sde-dither-size", false, PROP_TYPE_U32},
  599. {DITHER_VER, "qcom,sde-dither-version", false, PROP_TYPE_U32},
  600. {PP_MERGE_3D_ID, "qcom,sde-pp-merge-3d-id", false, PROP_TYPE_U32_ARRAY},
  601. };
  602. static struct sde_prop_type dsc_prop[] = {
  603. {DSC_OFF, "qcom,sde-dsc-off", false, PROP_TYPE_U32_ARRAY},
  604. {DSC_LEN, "qcom,sde-dsc-size", false, PROP_TYPE_U32},
  605. };
  606. static struct sde_prop_type cdm_prop[] = {
  607. {HW_OFF, "qcom,sde-cdm-off", false, PROP_TYPE_U32_ARRAY},
  608. {HW_LEN, "qcom,sde-cdm-size", false, PROP_TYPE_U32},
  609. };
  610. static struct sde_prop_type intf_prop[] = {
  611. {INTF_OFF, "qcom,sde-intf-off", true, PROP_TYPE_U32_ARRAY},
  612. {INTF_LEN, "qcom,sde-intf-size", false, PROP_TYPE_U32},
  613. {INTF_PREFETCH, "qcom,sde-intf-max-prefetch-lines", false,
  614. PROP_TYPE_U32_ARRAY},
  615. {INTF_TYPE, "qcom,sde-intf-type", false, PROP_TYPE_STRING_ARRAY},
  616. };
  617. static struct sde_prop_type wb_prop[] = {
  618. {WB_OFF, "qcom,sde-wb-off", true, PROP_TYPE_U32_ARRAY},
  619. {WB_LEN, "qcom,sde-wb-size", false, PROP_TYPE_U32},
  620. {WB_ID, "qcom,sde-wb-id", true, PROP_TYPE_U32_ARRAY},
  621. {WB_XIN_ID, "qcom,sde-wb-xin-id", false, PROP_TYPE_U32_ARRAY},
  622. {WB_CLK_CTRL, "qcom,sde-wb-clk-ctrl", false,
  623. PROP_TYPE_BIT_OFFSET_ARRAY},
  624. };
  625. static struct sde_prop_type vbif_prop[] = {
  626. {VBIF_OFF, "qcom,sde-vbif-off", true, PROP_TYPE_U32_ARRAY},
  627. {VBIF_LEN, "qcom,sde-vbif-size", false, PROP_TYPE_U32},
  628. {VBIF_ID, "qcom,sde-vbif-id", false, PROP_TYPE_U32_ARRAY},
  629. {VBIF_DEFAULT_OT_RD_LIMIT, "qcom,sde-vbif-default-ot-rd-limit", false,
  630. PROP_TYPE_U32},
  631. {VBIF_DEFAULT_OT_WR_LIMIT, "qcom,sde-vbif-default-ot-wr-limit", false,
  632. PROP_TYPE_U32},
  633. {VBIF_DYNAMIC_OT_RD_LIMIT, "qcom,sde-vbif-dynamic-ot-rd-limit", false,
  634. PROP_TYPE_U32_ARRAY},
  635. {VBIF_DYNAMIC_OT_WR_LIMIT, "qcom,sde-vbif-dynamic-ot-wr-limit", false,
  636. PROP_TYPE_U32_ARRAY},
  637. {VBIF_MEMTYPE_0, "qcom,sde-vbif-memtype-0", false, PROP_TYPE_U32_ARRAY},
  638. {VBIF_MEMTYPE_1, "qcom,sde-vbif-memtype-1", false, PROP_TYPE_U32_ARRAY},
  639. {VBIF_QOS_RT_REMAP, "qcom,sde-vbif-qos-rt-remap", false,
  640. PROP_TYPE_U32_ARRAY},
  641. {VBIF_QOS_NRT_REMAP, "qcom,sde-vbif-qos-nrt-remap", false,
  642. PROP_TYPE_U32_ARRAY},
  643. {VBIF_QOS_CWB_REMAP, "qcom,sde-vbif-qos-cwb-remap", false,
  644. PROP_TYPE_U32_ARRAY},
  645. {VBIF_QOS_LUTDMA_REMAP, "qcom,sde-vbif-qos-lutdma-remap", false,
  646. PROP_TYPE_U32_ARRAY},
  647. };
  648. static struct sde_prop_type uidle_prop[] = {
  649. {UIDLE_OFF, "qcom,sde-uidle-off", false, PROP_TYPE_U32},
  650. {UIDLE_LEN, "qcom,sde-uidle-size", false, PROP_TYPE_U32},
  651. };
  652. static struct sde_prop_type reg_dma_prop[REG_DMA_PROP_MAX] = {
  653. [REG_DMA_OFF] = {REG_DMA_OFF, "qcom,sde-reg-dma-off", false,
  654. PROP_TYPE_U32},
  655. [REG_DMA_VERSION] = {REG_DMA_VERSION, "qcom,sde-reg-dma-version",
  656. false, PROP_TYPE_U32},
  657. [REG_DMA_TRIGGER_OFF] = {REG_DMA_TRIGGER_OFF,
  658. "qcom,sde-reg-dma-trigger-off", false,
  659. PROP_TYPE_U32},
  660. [REG_DMA_BROADCAST_DISABLED] = {REG_DMA_BROADCAST_DISABLED,
  661. "qcom,sde-reg-dma-broadcast-disabled", false, PROP_TYPE_BOOL},
  662. [REG_DMA_XIN_ID] = {REG_DMA_XIN_ID,
  663. "qcom,sde-reg-dma-xin-id", false, PROP_TYPE_U32},
  664. [REG_DMA_CLK_CTRL] = {REG_DMA_XIN_ID,
  665. "qcom,sde-reg-dma-clk-ctrl", false, PROP_TYPE_BIT_OFFSET_ARRAY},
  666. };
  667. static struct sde_prop_type merge_3d_prop[] = {
  668. {HW_OFF, "qcom,sde-merge-3d-off", false, PROP_TYPE_U32_ARRAY},
  669. {HW_LEN, "qcom,sde-merge-3d-size", false, PROP_TYPE_U32},
  670. };
  671. static struct sde_prop_type qdss_prop[] = {
  672. {HW_OFF, "qcom,sde-qdss-off", false, PROP_TYPE_U32_ARRAY},
  673. {HW_LEN, "qcom,sde-qdss-size", false, PROP_TYPE_U32},
  674. };
  675. /*************************************************************
  676. * static API list
  677. *************************************************************/
  678. static int _parse_dt_u32_handler(struct device_node *np,
  679. char *prop_name, u32 *offsets, int len, bool mandatory)
  680. {
  681. int rc = -EINVAL;
  682. if (len > MAX_SDE_HW_BLK) {
  683. SDE_ERROR(
  684. "prop: %s tries out of bound access for u32 array read len: %d\n",
  685. prop_name, len);
  686. return -E2BIG;
  687. }
  688. rc = of_property_read_u32_array(np, prop_name, offsets, len);
  689. if (rc && mandatory)
  690. SDE_ERROR("mandatory prop: %s u32 array read len:%d\n",
  691. prop_name, len);
  692. else if (rc)
  693. SDE_DEBUG("optional prop: %s u32 array read len:%d\n",
  694. prop_name, len);
  695. return rc;
  696. }
  697. static int _parse_dt_bit_offset(struct device_node *np,
  698. char *prop_name, struct sde_prop_value *prop_value, u32 prop_index,
  699. u32 count, bool mandatory)
  700. {
  701. int rc = 0, len, i, j;
  702. const u32 *arr;
  703. arr = of_get_property(np, prop_name, &len);
  704. if (arr) {
  705. len /= sizeof(u32);
  706. len &= ~0x1;
  707. if (len > (MAX_SDE_HW_BLK * MAX_BIT_OFFSET)) {
  708. SDE_ERROR(
  709. "prop: %s len: %d will lead to out of bound access\n",
  710. prop_name, len / MAX_BIT_OFFSET);
  711. return -E2BIG;
  712. }
  713. for (i = 0, j = 0; i < len; j++) {
  714. PROP_BITVALUE_ACCESS(prop_value, prop_index, j, 0) =
  715. be32_to_cpu(arr[i]);
  716. i++;
  717. PROP_BITVALUE_ACCESS(prop_value, prop_index, j, 1) =
  718. be32_to_cpu(arr[i]);
  719. i++;
  720. }
  721. } else {
  722. if (mandatory) {
  723. SDE_ERROR("error mandatory property '%s' not found\n",
  724. prop_name);
  725. rc = -EINVAL;
  726. } else {
  727. SDE_DEBUG("error optional property '%s' not found\n",
  728. prop_name);
  729. }
  730. }
  731. return rc;
  732. }
  733. static int _validate_dt_entry(struct device_node *np,
  734. struct sde_prop_type *sde_prop, u32 prop_size, int *prop_count,
  735. int *off_count)
  736. {
  737. int rc = 0, i, val;
  738. struct device_node *snp = NULL;
  739. if (off_count) {
  740. *off_count = of_property_count_u32_elems(np,
  741. sde_prop[0].prop_name);
  742. if ((*off_count > MAX_BLOCKS) || (*off_count < 0)) {
  743. if (sde_prop[0].is_mandatory) {
  744. SDE_ERROR(
  745. "invalid hw offset prop name:%s count: %d\n",
  746. sde_prop[0].prop_name, *off_count);
  747. rc = -EINVAL;
  748. }
  749. *off_count = 0;
  750. memset(prop_count, 0, sizeof(int) * prop_size);
  751. return rc;
  752. }
  753. }
  754. for (i = 0; i < prop_size; i++) {
  755. switch (sde_prop[i].type) {
  756. case PROP_TYPE_U32:
  757. rc = of_property_read_u32(np, sde_prop[i].prop_name,
  758. &val);
  759. break;
  760. case PROP_TYPE_U32_ARRAY:
  761. prop_count[i] = of_property_count_u32_elems(np,
  762. sde_prop[i].prop_name);
  763. if (prop_count[i] < 0)
  764. rc = prop_count[i];
  765. break;
  766. case PROP_TYPE_STRING_ARRAY:
  767. prop_count[i] = of_property_count_strings(np,
  768. sde_prop[i].prop_name);
  769. if (prop_count[i] < 0)
  770. rc = prop_count[i];
  771. break;
  772. case PROP_TYPE_BIT_OFFSET_ARRAY:
  773. of_get_property(np, sde_prop[i].prop_name, &val);
  774. prop_count[i] = val / (MAX_BIT_OFFSET * sizeof(u32));
  775. break;
  776. case PROP_TYPE_NODE:
  777. snp = of_get_child_by_name(np,
  778. sde_prop[i].prop_name);
  779. if (!snp)
  780. rc = -EINVAL;
  781. break;
  782. default:
  783. SDE_DEBUG("invalid property type:%d\n",
  784. sde_prop[i].type);
  785. break;
  786. }
  787. SDE_DEBUG(
  788. "prop id:%d prop name:%s prop type:%d prop_count:%d\n",
  789. i, sde_prop[i].prop_name,
  790. sde_prop[i].type, prop_count[i]);
  791. if (rc && sde_prop[i].is_mandatory &&
  792. ((sde_prop[i].type == PROP_TYPE_U32) ||
  793. (sde_prop[i].type == PROP_TYPE_NODE))) {
  794. SDE_ERROR("prop:%s not present\n",
  795. sde_prop[i].prop_name);
  796. goto end;
  797. } else if (sde_prop[i].type == PROP_TYPE_U32 ||
  798. sde_prop[i].type == PROP_TYPE_BOOL ||
  799. sde_prop[i].type == PROP_TYPE_NODE) {
  800. rc = 0;
  801. continue;
  802. }
  803. if (off_count && (prop_count[i] != *off_count) &&
  804. sde_prop[i].is_mandatory) {
  805. SDE_ERROR(
  806. "prop:%s count:%d is different compared to offset array:%d\n",
  807. sde_prop[i].prop_name,
  808. prop_count[i], *off_count);
  809. rc = -EINVAL;
  810. goto end;
  811. } else if (off_count && prop_count[i] != *off_count) {
  812. SDE_DEBUG(
  813. "prop:%s count:%d is different compared to offset array:%d\n",
  814. sde_prop[i].prop_name,
  815. prop_count[i], *off_count);
  816. rc = 0;
  817. prop_count[i] = 0;
  818. }
  819. if (prop_count[i] < 0) {
  820. prop_count[i] = 0;
  821. if (sde_prop[i].is_mandatory) {
  822. SDE_ERROR("prop:%s count:%d is negative\n",
  823. sde_prop[i].prop_name, prop_count[i]);
  824. rc = -EINVAL;
  825. } else {
  826. rc = 0;
  827. SDE_DEBUG("prop:%s count:%d is negative\n",
  828. sde_prop[i].prop_name, prop_count[i]);
  829. }
  830. }
  831. }
  832. end:
  833. return rc;
  834. }
  835. static int _read_dt_entry(struct device_node *np,
  836. struct sde_prop_type *sde_prop, u32 prop_size, int *prop_count,
  837. bool *prop_exists,
  838. struct sde_prop_value *prop_value)
  839. {
  840. int rc = 0, i, j;
  841. for (i = 0; i < prop_size; i++) {
  842. prop_exists[i] = true;
  843. switch (sde_prop[i].type) {
  844. case PROP_TYPE_U32:
  845. rc = of_property_read_u32(np, sde_prop[i].prop_name,
  846. &PROP_VALUE_ACCESS(prop_value, i, 0));
  847. SDE_DEBUG(
  848. "prop id:%d prop name:%s prop type:%d value:0x%x\n",
  849. i, sde_prop[i].prop_name,
  850. sde_prop[i].type,
  851. PROP_VALUE_ACCESS(prop_value, i, 0));
  852. if (rc)
  853. prop_exists[i] = false;
  854. break;
  855. case PROP_TYPE_BOOL:
  856. PROP_VALUE_ACCESS(prop_value, i, 0) =
  857. of_property_read_bool(np,
  858. sde_prop[i].prop_name);
  859. SDE_DEBUG(
  860. "prop id:%d prop name:%s prop type:%d value:0x%x\n",
  861. i, sde_prop[i].prop_name,
  862. sde_prop[i].type,
  863. PROP_VALUE_ACCESS(prop_value, i, 0));
  864. break;
  865. case PROP_TYPE_U32_ARRAY:
  866. rc = _parse_dt_u32_handler(np, sde_prop[i].prop_name,
  867. &PROP_VALUE_ACCESS(prop_value, i, 0),
  868. prop_count[i], sde_prop[i].is_mandatory);
  869. if (rc && sde_prop[i].is_mandatory) {
  870. SDE_ERROR(
  871. "%s prop validation success but read failed\n",
  872. sde_prop[i].prop_name);
  873. prop_exists[i] = false;
  874. goto end;
  875. } else {
  876. if (rc)
  877. prop_exists[i] = false;
  878. /* only for debug purpose */
  879. SDE_DEBUG(
  880. "prop id:%d prop name:%s prop type:%d",
  881. i, sde_prop[i].prop_name,
  882. sde_prop[i].type);
  883. for (j = 0; j < prop_count[i]; j++)
  884. SDE_DEBUG(" value[%d]:0x%x ", j,
  885. PROP_VALUE_ACCESS(prop_value, i,
  886. j));
  887. SDE_DEBUG("\n");
  888. }
  889. break;
  890. case PROP_TYPE_BIT_OFFSET_ARRAY:
  891. rc = _parse_dt_bit_offset(np, sde_prop[i].prop_name,
  892. prop_value, i, prop_count[i],
  893. sde_prop[i].is_mandatory);
  894. if (rc && sde_prop[i].is_mandatory) {
  895. SDE_ERROR(
  896. "%s prop validation success but read failed\n",
  897. sde_prop[i].prop_name);
  898. prop_exists[i] = false;
  899. goto end;
  900. } else {
  901. if (rc)
  902. prop_exists[i] = false;
  903. SDE_DEBUG(
  904. "prop id:%d prop name:%s prop type:%d",
  905. i, sde_prop[i].prop_name,
  906. sde_prop[i].type);
  907. for (j = 0; j < prop_count[i]; j++)
  908. SDE_DEBUG(
  909. "count[%d]: bit:0x%x off:0x%x\n", j,
  910. PROP_BITVALUE_ACCESS(prop_value,
  911. i, j, 0),
  912. PROP_BITVALUE_ACCESS(prop_value,
  913. i, j, 1));
  914. SDE_DEBUG("\n");
  915. }
  916. break;
  917. case PROP_TYPE_NODE:
  918. /* Node will be parsed in calling function */
  919. rc = 0;
  920. break;
  921. default:
  922. SDE_DEBUG("invalid property type:%d\n",
  923. sde_prop[i].type);
  924. break;
  925. }
  926. rc = 0;
  927. }
  928. end:
  929. return rc;
  930. }
  931. static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg,
  932. struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
  933. bool *prop_exists, struct sde_prop_value *prop_value, u32 *vig_count)
  934. {
  935. sblk->maxupscale = MAX_UPSCALE_RATIO;
  936. sblk->maxdwnscale = MAX_DOWNSCALE_RATIO;
  937. sspp->id = SSPP_VIG0 + *vig_count;
  938. snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u",
  939. sspp->id - SSPP_VIG0);
  940. sspp->clk_ctrl = SDE_CLK_CTRL_VIG0 + *vig_count;
  941. sspp->type = SSPP_TYPE_VIG;
  942. set_bit(SDE_PERF_SSPP_QOS, &sspp->perf_features);
  943. if (sde_cfg->vbif_qos_nlvl == 8)
  944. set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);
  945. (*vig_count)++;
  946. if (!prop_value)
  947. return;
  948. if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) {
  949. set_bit(SDE_SSPP_SCALER_QSEED2, &sspp->features);
  950. sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;
  951. sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
  952. VIG_QSEED_OFF, 0);
  953. sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,
  954. VIG_QSEED_LEN, 0);
  955. snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,
  956. "sspp_scaler%u", sspp->id - SSPP_VIG0);
  957. } else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {
  958. set_bit(SDE_SSPP_SCALER_QSEED3, &sspp->features);
  959. sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;
  960. sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
  961. VIG_QSEED_OFF, 0);
  962. sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,
  963. VIG_QSEED_LEN, 0);
  964. snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,
  965. "sspp_scaler%u", sspp->id - SSPP_VIG0);
  966. } else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3LITE) {
  967. set_bit(SDE_SSPP_SCALER_QSEED3LITE, &sspp->features);
  968. sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3LITE;
  969. sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
  970. VIG_QSEED_OFF, 0);
  971. sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,
  972. VIG_QSEED_LEN, 0);
  973. snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,
  974. "sspp_scaler%u", sspp->id - SSPP_VIG0);
  975. }
  976. sblk->csc_blk.id = SDE_SSPP_CSC;
  977. snprintf(sblk->csc_blk.name, SDE_HW_BLK_NAME_LEN,
  978. "sspp_csc%u", sspp->id - SSPP_VIG0);
  979. if (sde_cfg->csc_type == SDE_SSPP_CSC) {
  980. set_bit(SDE_SSPP_CSC, &sspp->features);
  981. sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value,
  982. VIG_CSC_OFF, 0);
  983. } else if (sde_cfg->csc_type == SDE_SSPP_CSC_10BIT) {
  984. set_bit(SDE_SSPP_CSC_10BIT, &sspp->features);
  985. sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value,
  986. VIG_CSC_OFF, 0);
  987. }
  988. sblk->hsic_blk.id = SDE_SSPP_HSIC;
  989. snprintf(sblk->hsic_blk.name, SDE_HW_BLK_NAME_LEN,
  990. "sspp_hsic%u", sspp->id - SSPP_VIG0);
  991. if (prop_exists[VIG_HSIC_PROP]) {
  992. sblk->hsic_blk.base = PROP_VALUE_ACCESS(prop_value,
  993. VIG_HSIC_PROP, 0);
  994. sblk->hsic_blk.version = PROP_VALUE_ACCESS(prop_value,
  995. VIG_HSIC_PROP, 1);
  996. sblk->hsic_blk.len = 0;
  997. set_bit(SDE_SSPP_HSIC, &sspp->features);
  998. }
  999. sblk->memcolor_blk.id = SDE_SSPP_MEMCOLOR;
  1000. snprintf(sblk->memcolor_blk.name, SDE_HW_BLK_NAME_LEN,
  1001. "sspp_memcolor%u", sspp->id - SSPP_VIG0);
  1002. if (prop_exists[VIG_MEMCOLOR_PROP]) {
  1003. sblk->memcolor_blk.base = PROP_VALUE_ACCESS(prop_value,
  1004. VIG_MEMCOLOR_PROP, 0);
  1005. sblk->memcolor_blk.version = PROP_VALUE_ACCESS(prop_value,
  1006. VIG_MEMCOLOR_PROP, 1);
  1007. sblk->memcolor_blk.len = 0;
  1008. set_bit(SDE_SSPP_MEMCOLOR, &sspp->features);
  1009. }
  1010. sblk->pcc_blk.id = SDE_SSPP_PCC;
  1011. snprintf(sblk->pcc_blk.name, SDE_HW_BLK_NAME_LEN,
  1012. "sspp_pcc%u", sspp->id - SSPP_VIG0);
  1013. if (prop_exists[VIG_PCC_PROP]) {
  1014. sblk->pcc_blk.base = PROP_VALUE_ACCESS(prop_value,
  1015. VIG_PCC_PROP, 0);
  1016. sblk->pcc_blk.version = PROP_VALUE_ACCESS(prop_value,
  1017. VIG_PCC_PROP, 1);
  1018. sblk->pcc_blk.len = 0;
  1019. set_bit(SDE_SSPP_PCC, &sspp->features);
  1020. }
  1021. if (prop_exists[VIG_GAMUT_PROP]) {
  1022. sblk->gamut_blk.id = SDE_SSPP_VIG_GAMUT;
  1023. snprintf(sblk->gamut_blk.name, SDE_HW_BLK_NAME_LEN,
  1024. "sspp_vig_gamut%u", sspp->id - SSPP_VIG0);
  1025. sblk->gamut_blk.base = PROP_VALUE_ACCESS(prop_value,
  1026. VIG_GAMUT_PROP, 0);
  1027. sblk->gamut_blk.version = PROP_VALUE_ACCESS(prop_value,
  1028. VIG_GAMUT_PROP, 1);
  1029. sblk->gamut_blk.len = 0;
  1030. set_bit(SDE_SSPP_VIG_GAMUT, &sspp->features);
  1031. }
  1032. if (prop_exists[VIG_IGC_PROP]) {
  1033. sblk->igc_blk[0].id = SDE_SSPP_VIG_IGC;
  1034. snprintf(sblk->igc_blk[0].name, SDE_HW_BLK_NAME_LEN,
  1035. "sspp_vig_igc%u", sspp->id - SSPP_VIG0);
  1036. sblk->igc_blk[0].base = PROP_VALUE_ACCESS(prop_value,
  1037. VIG_IGC_PROP, 0);
  1038. sblk->igc_blk[0].version = PROP_VALUE_ACCESS(prop_value,
  1039. VIG_IGC_PROP, 1);
  1040. sblk->igc_blk[0].len = 0;
  1041. set_bit(SDE_SSPP_VIG_IGC, &sspp->features);
  1042. }
  1043. if (PROP_VALUE_ACCESS(prop_value, VIG_INVERSE_PMA, 0))
  1044. set_bit(SDE_SSPP_INVERSE_PMA, &sspp->features);
  1045. sblk->format_list = sde_cfg->vig_formats;
  1046. sblk->virt_format_list = sde_cfg->virt_vig_formats;
  1047. if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev)) {
  1048. set_bit(SDE_SSPP_TRUE_INLINE_ROT_V1, &sspp->features);
  1049. sblk->in_rot_format_list = sde_cfg->inline_rot_formats;
  1050. sblk->in_rot_maxdwnscale_rt_num =
  1051. sde_cfg->true_inline_dwnscale_rt_num;
  1052. sblk->in_rot_maxdwnscale_rt_denom =
  1053. sde_cfg->true_inline_dwnscale_rt_denom;
  1054. sblk->in_rot_maxdwnscale_nrt =
  1055. sde_cfg->true_inline_dwnscale_nrt;
  1056. sblk->in_rot_maxheight =
  1057. MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT;
  1058. sblk->in_rot_prefill_fudge_lines =
  1059. sde_cfg->true_inline_prefill_fudge_lines;
  1060. sblk->in_rot_prefill_lines_nv12 =
  1061. sde_cfg->true_inline_prefill_lines_nv12;
  1062. sblk->in_rot_prefill_lines =
  1063. sde_cfg->true_inline_prefill_lines;
  1064. }
  1065. if (sde_cfg->sc_cfg.has_sys_cache) {
  1066. set_bit(SDE_PERF_SSPP_SYS_CACHE, &sspp->perf_features);
  1067. sblk->llcc_scid = sde_cfg->sc_cfg.llcc_scid;
  1068. sblk->llcc_slice_size =
  1069. sde_cfg->sc_cfg.llcc_slice_size;
  1070. }
  1071. }
  1072. static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg,
  1073. struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
  1074. bool *prop_exists, struct sde_prop_value *prop_value, u32 *rgb_count)
  1075. {
  1076. sblk->maxupscale = MAX_UPSCALE_RATIO;
  1077. sblk->maxdwnscale = MAX_DOWNSCALE_RATIO;
  1078. sspp->id = SSPP_RGB0 + *rgb_count;
  1079. snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u",
  1080. sspp->id - SSPP_VIG0);
  1081. sspp->clk_ctrl = SDE_CLK_CTRL_RGB0 + *rgb_count;
  1082. sspp->type = SSPP_TYPE_RGB;
  1083. set_bit(SDE_PERF_SSPP_QOS, &sspp->perf_features);
  1084. if (sde_cfg->vbif_qos_nlvl == 8)
  1085. set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);
  1086. (*rgb_count)++;
  1087. if (!prop_value)
  1088. return;
  1089. if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) {
  1090. set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
  1091. sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;
  1092. sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
  1093. RGB_SCALER_OFF, 0);
  1094. sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,
  1095. RGB_SCALER_LEN, 0);
  1096. snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,
  1097. "sspp_scaler%u", sspp->id - SSPP_VIG0);
  1098. } else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {
  1099. set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
  1100. sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;
  1101. sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
  1102. RGB_SCALER_LEN, 0);
  1103. sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,
  1104. SSPP_SCALE_SIZE, 0);
  1105. snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,
  1106. "sspp_scaler%u", sspp->id - SSPP_VIG0);
  1107. }
  1108. sblk->pcc_blk.id = SDE_SSPP_PCC;
  1109. if (prop_exists[RGB_PCC_PROP]) {
  1110. sblk->pcc_blk.base = PROP_VALUE_ACCESS(prop_value,
  1111. RGB_PCC_PROP, 0);
  1112. sblk->pcc_blk.version = PROP_VALUE_ACCESS(prop_value,
  1113. RGB_PCC_PROP, 1);
  1114. sblk->pcc_blk.len = 0;
  1115. set_bit(SDE_SSPP_PCC, &sspp->features);
  1116. }
  1117. sblk->format_list = sde_cfg->dma_formats;
  1118. sblk->virt_format_list = NULL;
  1119. }
  1120. static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
  1121. struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
  1122. struct sde_prop_value *prop_value, u32 *cursor_count)
  1123. {
  1124. if (!IS_SDE_MAJOR_MINOR_SAME(sde_cfg->hwversion, SDE_HW_VER_300))
  1125. SDE_ERROR("invalid sspp type %d, xin id %d\n",
  1126. sspp->type, sspp->xin_id);
  1127. set_bit(SDE_SSPP_CURSOR, &sspp->features);
  1128. sblk->maxupscale = SSPP_UNITY_SCALE;
  1129. sblk->maxdwnscale = SSPP_UNITY_SCALE;
  1130. sblk->format_list = sde_cfg->cursor_formats;
  1131. sblk->virt_format_list = NULL;
  1132. sspp->id = SSPP_CURSOR0 + *cursor_count;
  1133. snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u",
  1134. sspp->id - SSPP_VIG0);
  1135. sspp->clk_ctrl = SDE_CLK_CTRL_CURSOR0 + *cursor_count;
  1136. sspp->type = SSPP_TYPE_CURSOR;
  1137. (*cursor_count)++;
  1138. }
  1139. static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg,
  1140. struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
  1141. bool prop_exists[][DMA_PROP_MAX], struct sde_prop_value *prop_value,
  1142. u32 *dma_count, u32 dgm_count)
  1143. {
  1144. u32 i = 0;
  1145. sblk->maxupscale = SSPP_UNITY_SCALE;
  1146. sblk->maxdwnscale = SSPP_UNITY_SCALE;
  1147. sblk->format_list = sde_cfg->dma_formats;
  1148. sblk->virt_format_list = sde_cfg->dma_formats;
  1149. sspp->id = SSPP_DMA0 + *dma_count;
  1150. sspp->clk_ctrl = SDE_CLK_CTRL_DMA0 + *dma_count;
  1151. snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u",
  1152. sspp->id - SSPP_VIG0);
  1153. sspp->type = SSPP_TYPE_DMA;
  1154. set_bit(SDE_PERF_SSPP_QOS, &sspp->perf_features);
  1155. if (sde_cfg->vbif_qos_nlvl == 8)
  1156. set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);
  1157. (*dma_count)++;
  1158. if (!prop_value)
  1159. return;
  1160. sblk->num_igc_blk = dgm_count;
  1161. sblk->num_gc_blk = dgm_count;
  1162. sblk->num_dgm_csc_blk = dgm_count;
  1163. for (i = 0; i < dgm_count; i++) {
  1164. if (prop_exists[i][DMA_IGC_PROP]) {
  1165. sblk->igc_blk[i].id = SDE_SSPP_DMA_IGC;
  1166. snprintf(sblk->igc_blk[i].name, SDE_HW_BLK_NAME_LEN,
  1167. "sspp_dma_igc%u", sspp->id - SSPP_DMA0);
  1168. sblk->igc_blk[i].base = PROP_VALUE_ACCESS(
  1169. &prop_value[i * DMA_PROP_MAX], DMA_IGC_PROP, 0);
  1170. sblk->igc_blk[i].version = PROP_VALUE_ACCESS(
  1171. &prop_value[i * DMA_PROP_MAX], DMA_IGC_PROP, 1);
  1172. sblk->igc_blk[i].len = 0;
  1173. set_bit(SDE_SSPP_DMA_IGC, &sspp->features);
  1174. }
  1175. if (prop_exists[i][DMA_GC_PROP]) {
  1176. sblk->gc_blk[i].id = SDE_SSPP_DMA_GC;
  1177. snprintf(sblk->gc_blk[0].name, SDE_HW_BLK_NAME_LEN,
  1178. "sspp_dma_gc%u", sspp->id - SSPP_DMA0);
  1179. sblk->gc_blk[i].base = PROP_VALUE_ACCESS(
  1180. &prop_value[i * DMA_PROP_MAX], DMA_GC_PROP, 0);
  1181. sblk->gc_blk[i].version = PROP_VALUE_ACCESS(
  1182. &prop_value[i * DMA_PROP_MAX], DMA_GC_PROP, 1);
  1183. sblk->gc_blk[i].len = 0;
  1184. set_bit(SDE_SSPP_DMA_GC, &sspp->features);
  1185. }
  1186. if (PROP_VALUE_ACCESS(&prop_value[i * DMA_PROP_MAX],
  1187. DMA_DGM_INVERSE_PMA, 0))
  1188. set_bit(SDE_SSPP_DGM_INVERSE_PMA, &sspp->features);
  1189. if (prop_exists[i][DMA_CSC_OFF]) {
  1190. sblk->dgm_csc_blk[i].id = SDE_SSPP_DGM_CSC;
  1191. snprintf(sblk->csc_blk.name, SDE_HW_BLK_NAME_LEN,
  1192. "sspp_dgm_csc%u", sspp->id - SSPP_DMA0);
  1193. set_bit(SDE_SSPP_DGM_CSC, &sspp->features);
  1194. sblk->dgm_csc_blk[i].base = PROP_VALUE_ACCESS(
  1195. &prop_value[i * DMA_PROP_MAX], DMA_CSC_OFF, 0);
  1196. }
  1197. }
  1198. }
  1199. static int sde_dgm_parse_dt(struct device_node *np, u32 index,
  1200. struct sde_prop_value *prop_value, bool *prop_exists)
  1201. {
  1202. int rc = 0;
  1203. u32 child_idx = 0;
  1204. int prop_count[DMA_PROP_MAX] = {0};
  1205. struct device_node *dgm_snp = NULL;
  1206. for_each_child_of_node(np, dgm_snp) {
  1207. if (index != child_idx++)
  1208. continue;
  1209. rc = _validate_dt_entry(dgm_snp, dma_prop, ARRAY_SIZE(dma_prop),
  1210. prop_count, NULL);
  1211. if (rc)
  1212. return rc;
  1213. rc = _read_dt_entry(dgm_snp, dma_prop, ARRAY_SIZE(dma_prop),
  1214. prop_count, prop_exists,
  1215. prop_value);
  1216. }
  1217. return rc;
  1218. }
  1219. static int sde_sspp_parse_dt(struct device_node *np,
  1220. struct sde_mdss_cfg *sde_cfg)
  1221. {
  1222. int rc, prop_count[SSPP_PROP_MAX], off_count, i, j;
  1223. int vig_prop_count[VIG_PROP_MAX], rgb_prop_count[RGB_PROP_MAX];
  1224. bool prop_exists[SSPP_PROP_MAX], vig_prop_exists[VIG_PROP_MAX];
  1225. bool rgb_prop_exists[RGB_PROP_MAX];
  1226. bool dgm_prop_exists[SSPP_SUBBLK_COUNT_MAX][DMA_PROP_MAX];
  1227. struct sde_prop_value *prop_value = NULL;
  1228. struct sde_prop_value *vig_prop_value = NULL, *rgb_prop_value = NULL;
  1229. struct sde_prop_value *dgm_prop_value = NULL;
  1230. const char *type;
  1231. struct sde_sspp_cfg *sspp;
  1232. struct sde_sspp_sub_blks *sblk;
  1233. u32 vig_count = 0, dma_count = 0, rgb_count = 0, cursor_count = 0;
  1234. u32 dgm_count = 0;
  1235. struct device_node *snp = NULL;
  1236. prop_value = kcalloc(SSPP_PROP_MAX,
  1237. sizeof(struct sde_prop_value), GFP_KERNEL);
  1238. if (!prop_value) {
  1239. rc = -ENOMEM;
  1240. goto end;
  1241. }
  1242. rc = _validate_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop),
  1243. prop_count, &off_count);
  1244. if (rc)
  1245. goto end;
  1246. rc = _read_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop), prop_count,
  1247. prop_exists, prop_value);
  1248. if (rc)
  1249. goto end;
  1250. sde_cfg->sspp_count = off_count;
  1251. /* get vig feature dt properties if they exist */
  1252. snp = of_get_child_by_name(np, sspp_prop[SSPP_VIG_BLOCKS].prop_name);
  1253. if (snp) {
  1254. vig_prop_value = kcalloc(VIG_PROP_MAX,
  1255. sizeof(struct sde_prop_value), GFP_KERNEL);
  1256. if (!vig_prop_value) {
  1257. rc = -ENOMEM;
  1258. goto end;
  1259. }
  1260. rc = _validate_dt_entry(snp, vig_prop, ARRAY_SIZE(vig_prop),
  1261. vig_prop_count, NULL);
  1262. if (rc)
  1263. goto end;
  1264. rc = _read_dt_entry(snp, vig_prop, ARRAY_SIZE(vig_prop),
  1265. vig_prop_count, vig_prop_exists,
  1266. vig_prop_value);
  1267. }
  1268. /* get rgb feature dt properties if they exist */
  1269. snp = of_get_child_by_name(np, sspp_prop[SSPP_RGB_BLOCKS].prop_name);
  1270. if (snp) {
  1271. rgb_prop_value = kcalloc(RGB_PROP_MAX,
  1272. sizeof(struct sde_prop_value),
  1273. GFP_KERNEL);
  1274. if (!rgb_prop_value) {
  1275. rc = -ENOMEM;
  1276. goto end;
  1277. }
  1278. rc = _validate_dt_entry(snp, rgb_prop, ARRAY_SIZE(rgb_prop),
  1279. rgb_prop_count, NULL);
  1280. if (rc)
  1281. goto end;
  1282. rc = _read_dt_entry(snp, rgb_prop, ARRAY_SIZE(rgb_prop),
  1283. rgb_prop_count, rgb_prop_exists,
  1284. rgb_prop_value);
  1285. }
  1286. /* get dma feature dt properties if they exist */
  1287. snp = of_get_child_by_name(np, sspp_prop[SSPP_DMA_BLOCKS].prop_name);
  1288. if (snp) {
  1289. dgm_count = of_get_child_count(snp);
  1290. if (dgm_count > 0 && dgm_count <= SSPP_SUBBLK_COUNT_MAX) {
  1291. dgm_prop_value = kzalloc(dgm_count * DMA_PROP_MAX *
  1292. sizeof(struct sde_prop_value),
  1293. GFP_KERNEL);
  1294. if (!dgm_prop_value) {
  1295. rc = -ENOMEM;
  1296. goto end;
  1297. }
  1298. for (i = 0; i < dgm_count; i++)
  1299. sde_dgm_parse_dt(snp, i,
  1300. &dgm_prop_value[i * DMA_PROP_MAX],
  1301. &dgm_prop_exists[i][0]);
  1302. }
  1303. }
  1304. for (i = 0; i < off_count; i++) {
  1305. sspp = sde_cfg->sspp + i;
  1306. sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
  1307. if (!sblk) {
  1308. rc = -ENOMEM;
  1309. /* catalog deinit will release the allocated blocks */
  1310. goto end;
  1311. }
  1312. sspp->sblk = sblk;
  1313. sspp->base = PROP_VALUE_ACCESS(prop_value, SSPP_OFF, i);
  1314. sspp->len = PROP_VALUE_ACCESS(prop_value, SSPP_SIZE, 0);
  1315. sblk->maxlinewidth = sde_cfg->max_sspp_linewidth;
  1316. set_bit(SDE_SSPP_SRC, &sspp->features);
  1317. if (sde_cfg->has_cdp)
  1318. set_bit(SDE_PERF_SSPP_CDP, &sspp->perf_features);
  1319. if (sde_cfg->ts_prefill_rev == 1) {
  1320. set_bit(SDE_PERF_SSPP_TS_PREFILL, &sspp->perf_features);
  1321. } else if (sde_cfg->ts_prefill_rev == 2) {
  1322. set_bit(SDE_PERF_SSPP_TS_PREFILL, &sspp->perf_features);
  1323. set_bit(SDE_PERF_SSPP_TS_PREFILL_REC1,
  1324. &sspp->perf_features);
  1325. }
  1326. sblk->smart_dma_priority =
  1327. PROP_VALUE_ACCESS(prop_value, SSPP_SMART_DMA, i);
  1328. if (sblk->smart_dma_priority && sde_cfg->smart_dma_rev)
  1329. set_bit(sde_cfg->smart_dma_rev, &sspp->features);
  1330. sblk->src_blk.id = SDE_SSPP_SRC;
  1331. of_property_read_string_index(np,
  1332. sspp_prop[SSPP_TYPE].prop_name, i, &type);
  1333. if (!strcmp(type, "vig")) {
  1334. _sde_sspp_setup_vig(sde_cfg, sspp, sblk,
  1335. vig_prop_exists, vig_prop_value, &vig_count);
  1336. } else if (!strcmp(type, "rgb")) {
  1337. _sde_sspp_setup_rgb(sde_cfg, sspp, sblk,
  1338. rgb_prop_exists, rgb_prop_value, &rgb_count);
  1339. } else if (!strcmp(type, "cursor")) {
  1340. /* No prop values for cursor pipes */
  1341. _sde_sspp_setup_cursor(sde_cfg, sspp, sblk, NULL,
  1342. &cursor_count);
  1343. } else if (!strcmp(type, "dma")) {
  1344. _sde_sspp_setup_dma(sde_cfg, sspp, sblk,
  1345. dgm_prop_exists, dgm_prop_value, &dma_count,
  1346. dgm_count);
  1347. } else {
  1348. SDE_ERROR("invalid sspp type:%s\n", type);
  1349. rc = -EINVAL;
  1350. goto end;
  1351. }
  1352. if (sde_cfg->uidle_cfg.uidle_rev)
  1353. set_bit(SDE_PERF_SSPP_UIDLE, &sspp->perf_features);
  1354. snprintf(sblk->src_blk.name, SDE_HW_BLK_NAME_LEN, "sspp_src_%u",
  1355. sspp->id - SSPP_VIG0);
  1356. if (sspp->clk_ctrl >= SDE_CLK_CTRL_MAX) {
  1357. SDE_ERROR("%s: invalid clk ctrl: %d\n",
  1358. sblk->src_blk.name, sspp->clk_ctrl);
  1359. rc = -EINVAL;
  1360. goto end;
  1361. }
  1362. if (sde_cfg->has_decimation) {
  1363. sblk->maxhdeciexp = MAX_HORZ_DECIMATION;
  1364. sblk->maxvdeciexp = MAX_VERT_DECIMATION;
  1365. } else {
  1366. sblk->maxhdeciexp = 0;
  1367. sblk->maxvdeciexp = 0;
  1368. }
  1369. sspp->xin_id = PROP_VALUE_ACCESS(prop_value, SSPP_XIN, i);
  1370. sblk->pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE;
  1371. sblk->src_blk.len = PROP_VALUE_ACCESS(prop_value, SSPP_SIZE, 0);
  1372. if (PROP_VALUE_ACCESS(prop_value, SSPP_EXCL_RECT, i) == 1)
  1373. set_bit(SDE_SSPP_EXCL_RECT, &sspp->features);
  1374. if (prop_exists[SSPP_MAX_PER_PIPE_BW])
  1375. sblk->max_per_pipe_bw = PROP_VALUE_ACCESS(prop_value,
  1376. SSPP_MAX_PER_PIPE_BW, i);
  1377. else
  1378. sblk->max_per_pipe_bw = DEFAULT_MAX_PER_PIPE_BW;
  1379. if (prop_exists[SSPP_MAX_PER_PIPE_BW_HIGH])
  1380. sblk->max_per_pipe_bw_high =
  1381. PROP_VALUE_ACCESS(prop_value,
  1382. SSPP_MAX_PER_PIPE_BW_HIGH, i);
  1383. else
  1384. sblk->max_per_pipe_bw_high = sblk->max_per_pipe_bw;
  1385. for (j = 0; j < sde_cfg->mdp_count; j++) {
  1386. sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].reg_off =
  1387. PROP_BITVALUE_ACCESS(prop_value,
  1388. SSPP_CLK_CTRL, i, 0);
  1389. sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].bit_off =
  1390. PROP_BITVALUE_ACCESS(prop_value,
  1391. SSPP_CLK_CTRL, i, 1);
  1392. }
  1393. SDE_DEBUG(
  1394. "xin:%d ram:%d clk%d:%x/%d\n",
  1395. sspp->xin_id,
  1396. sblk->pixel_ram_size,
  1397. sspp->clk_ctrl,
  1398. sde_cfg->mdp[0].clk_ctrls[sspp->clk_ctrl].reg_off,
  1399. sde_cfg->mdp[0].clk_ctrls[sspp->clk_ctrl].bit_off);
  1400. }
  1401. end:
  1402. kfree(prop_value);
  1403. kfree(vig_prop_value);
  1404. kfree(rgb_prop_value);
  1405. kfree(dgm_prop_value);
  1406. return rc;
  1407. }
  1408. static int sde_ctl_parse_dt(struct device_node *np,
  1409. struct sde_mdss_cfg *sde_cfg)
  1410. {
  1411. int rc, prop_count[HW_PROP_MAX], i;
  1412. bool prop_exists[HW_PROP_MAX];
  1413. struct sde_prop_value *prop_value = NULL;
  1414. struct sde_ctl_cfg *ctl;
  1415. u32 off_count;
  1416. if (!sde_cfg) {
  1417. SDE_ERROR("invalid argument input param\n");
  1418. rc = -EINVAL;
  1419. goto end;
  1420. }
  1421. prop_value = kzalloc(HW_PROP_MAX *
  1422. sizeof(struct sde_prop_value), GFP_KERNEL);
  1423. if (!prop_value) {
  1424. rc = -ENOMEM;
  1425. goto end;
  1426. }
  1427. rc = _validate_dt_entry(np, ctl_prop, ARRAY_SIZE(ctl_prop), prop_count,
  1428. &off_count);
  1429. if (rc)
  1430. goto end;
  1431. sde_cfg->ctl_count = off_count;
  1432. rc = _read_dt_entry(np, ctl_prop, ARRAY_SIZE(ctl_prop), prop_count,
  1433. prop_exists, prop_value);
  1434. if (rc)
  1435. goto end;
  1436. for (i = 0; i < off_count; i++) {
  1437. const char *disp_pref = NULL;
  1438. ctl = sde_cfg->ctl + i;
  1439. ctl->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
  1440. ctl->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);
  1441. ctl->id = CTL_0 + i;
  1442. snprintf(ctl->name, SDE_HW_BLK_NAME_LEN, "ctl_%u",
  1443. ctl->id - CTL_0);
  1444. of_property_read_string_index(np,
  1445. ctl_prop[HW_DISP].prop_name, i, &disp_pref);
  1446. if (disp_pref && !strcmp(disp_pref, "primary"))
  1447. set_bit(SDE_CTL_PRIMARY_PREF, &ctl->features);
  1448. if (i < MAX_SPLIT_DISPLAY_CTL)
  1449. set_bit(SDE_CTL_SPLIT_DISPLAY, &ctl->features);
  1450. if (i < MAX_PP_SPLIT_DISPLAY_CTL)
  1451. set_bit(SDE_CTL_PINGPONG_SPLIT, &ctl->features);
  1452. if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
  1453. set_bit(SDE_CTL_ACTIVE_CFG, &ctl->features);
  1454. if (IS_SDE_UIDLE_REV_100(sde_cfg->uidle_cfg.uidle_rev))
  1455. set_bit(SDE_CTL_UIDLE, &ctl->features);
  1456. }
  1457. end:
  1458. kfree(prop_value);
  1459. return rc;
  1460. }
  1461. void sde_hw_mixer_set_preference(struct sde_mdss_cfg *sde_cfg, u32 num_lm,
  1462. uint32_t disp_type)
  1463. {
  1464. u32 i, cnt = 0, sec_cnt = 0;
  1465. if (disp_type == SDE_CONNECTOR_PRIMARY) {
  1466. for (i = 0; i < sde_cfg->mixer_count; i++) {
  1467. /* Check if lm was previously set for secondary */
  1468. /* Clear pref, primary has higher priority */
  1469. if (sde_cfg->mixer[i].features &
  1470. BIT(SDE_DISP_SECONDARY_PREF)) {
  1471. clear_bit(SDE_DISP_SECONDARY_PREF,
  1472. &sde_cfg->mixer[i].features);
  1473. sec_cnt++;
  1474. }
  1475. clear_bit(SDE_DISP_PRIMARY_PREF,
  1476. &sde_cfg->mixer[i].features);
  1477. /* Set lm for primary pref */
  1478. if (cnt < num_lm) {
  1479. set_bit(SDE_DISP_PRIMARY_PREF,
  1480. &sde_cfg->mixer[i].features);
  1481. cnt++;
  1482. }
  1483. /* After primary pref is set, now re apply secondary */
  1484. if (cnt >= num_lm && cnt < (num_lm + sec_cnt)) {
  1485. set_bit(SDE_DISP_SECONDARY_PREF,
  1486. &sde_cfg->mixer[i].features);
  1487. cnt++;
  1488. }
  1489. }
  1490. } else if (disp_type == SDE_CONNECTOR_SECONDARY) {
  1491. for (i = 0; i < sde_cfg->mixer_count; i++) {
  1492. clear_bit(SDE_DISP_SECONDARY_PREF,
  1493. &sde_cfg->mixer[i].features);
  1494. if (cnt < num_lm && !(sde_cfg->mixer[i].features &
  1495. BIT(SDE_DISP_PRIMARY_PREF))) {
  1496. set_bit(SDE_DISP_SECONDARY_PREF,
  1497. &sde_cfg->mixer[i].features);
  1498. cnt++;
  1499. }
  1500. }
  1501. }
  1502. }
  1503. static int sde_mixer_parse_dt(struct device_node *np,
  1504. struct sde_mdss_cfg *sde_cfg)
  1505. {
  1506. int rc, prop_count[MIXER_PROP_MAX], i, j;
  1507. int blocks_prop_count[MIXER_BLOCKS_PROP_MAX];
  1508. int blend_prop_count[MIXER_BLEND_PROP_MAX];
  1509. bool prop_exists[MIXER_PROP_MAX];
  1510. bool blocks_prop_exists[MIXER_BLOCKS_PROP_MAX];
  1511. bool blend_prop_exists[MIXER_BLEND_PROP_MAX];
  1512. struct sde_prop_value *prop_value = NULL, *blocks_prop_value = NULL;
  1513. struct sde_prop_value *blend_prop_value = NULL;
  1514. u32 off_count, blend_off_count, max_blendstages, lm_pair_mask;
  1515. struct sde_lm_cfg *mixer;
  1516. struct sde_lm_sub_blks *sblk;
  1517. int pp_count, dspp_count, ds_count, mixer_count;
  1518. u32 pp_idx, dspp_idx, ds_idx;
  1519. u32 mixer_base;
  1520. struct device_node *snp = NULL;
  1521. if (!sde_cfg) {
  1522. SDE_ERROR("invalid argument input param\n");
  1523. rc = -EINVAL;
  1524. goto end;
  1525. }
  1526. max_blendstages = sde_cfg->max_mixer_blendstages;
  1527. prop_value = kcalloc(MIXER_PROP_MAX,
  1528. sizeof(struct sde_prop_value), GFP_KERNEL);
  1529. if (!prop_value) {
  1530. rc = -ENOMEM;
  1531. goto end;
  1532. }
  1533. rc = _validate_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop),
  1534. prop_count, &off_count);
  1535. if (rc)
  1536. goto end;
  1537. rc = _read_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop), prop_count,
  1538. prop_exists, prop_value);
  1539. if (rc)
  1540. goto end;
  1541. pp_count = sde_cfg->pingpong_count;
  1542. dspp_count = sde_cfg->dspp_count;
  1543. ds_count = sde_cfg->ds_count;
  1544. /* get mixer feature dt properties if they exist */
  1545. snp = of_get_child_by_name(np, mixer_prop[MIXER_BLOCKS].prop_name);
  1546. if (snp) {
  1547. blocks_prop_value = kzalloc(MIXER_BLOCKS_PROP_MAX *
  1548. MAX_SDE_HW_BLK * sizeof(struct sde_prop_value),
  1549. GFP_KERNEL);
  1550. if (!blocks_prop_value) {
  1551. rc = -ENOMEM;
  1552. goto end;
  1553. }
  1554. rc = _validate_dt_entry(snp, mixer_blocks_prop,
  1555. ARRAY_SIZE(mixer_blocks_prop), blocks_prop_count, NULL);
  1556. if (rc)
  1557. goto end;
  1558. rc = _read_dt_entry(snp, mixer_blocks_prop,
  1559. ARRAY_SIZE(mixer_blocks_prop),
  1560. blocks_prop_count, blocks_prop_exists,
  1561. blocks_prop_value);
  1562. }
  1563. /* get the blend_op register offsets */
  1564. blend_prop_value = kzalloc(MIXER_BLEND_PROP_MAX *
  1565. sizeof(struct sde_prop_value), GFP_KERNEL);
  1566. if (!blend_prop_value) {
  1567. rc = -ENOMEM;
  1568. goto end;
  1569. }
  1570. rc = _validate_dt_entry(np, mixer_blend_prop,
  1571. ARRAY_SIZE(mixer_blend_prop), blend_prop_count,
  1572. &blend_off_count);
  1573. if (rc)
  1574. goto end;
  1575. rc = _read_dt_entry(np, mixer_blend_prop, ARRAY_SIZE(mixer_blend_prop),
  1576. blend_prop_count, blend_prop_exists, blend_prop_value);
  1577. if (rc)
  1578. goto end;
  1579. for (i = 0, mixer_count = 0, pp_idx = 0, dspp_idx = 0,
  1580. ds_idx = 0; i < off_count; i++) {
  1581. const char *disp_pref = NULL;
  1582. const char *cwb_pref = NULL;
  1583. mixer_base = PROP_VALUE_ACCESS(prop_value, MIXER_OFF, i);
  1584. if (!mixer_base)
  1585. continue;
  1586. mixer = sde_cfg->mixer + mixer_count;
  1587. sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
  1588. if (!sblk) {
  1589. rc = -ENOMEM;
  1590. /* catalog deinit will release the allocated blocks */
  1591. goto end;
  1592. }
  1593. mixer->sblk = sblk;
  1594. mixer->base = mixer_base;
  1595. mixer->len = PROP_VALUE_ACCESS(prop_value, MIXER_LEN, 0);
  1596. mixer->id = LM_0 + i;
  1597. snprintf(mixer->name, SDE_HW_BLK_NAME_LEN, "lm_%u",
  1598. mixer->id - LM_0);
  1599. if (!prop_exists[MIXER_LEN])
  1600. mixer->len = DEFAULT_SDE_HW_BLOCK_LEN;
  1601. lm_pair_mask = PROP_VALUE_ACCESS(prop_value,
  1602. MIXER_PAIR_MASK, i);
  1603. if (lm_pair_mask)
  1604. mixer->lm_pair_mask = 1 << lm_pair_mask;
  1605. sblk->maxblendstages = max_blendstages;
  1606. sblk->maxwidth = sde_cfg->max_mixer_width;
  1607. for (j = 0; j < blend_off_count; j++)
  1608. sblk->blendstage_base[j] =
  1609. PROP_VALUE_ACCESS(blend_prop_value,
  1610. MIXER_BLEND_OP_OFF, j);
  1611. if (sde_cfg->has_src_split)
  1612. set_bit(SDE_MIXER_SOURCESPLIT, &mixer->features);
  1613. if (sde_cfg->has_dim_layer)
  1614. set_bit(SDE_DIM_LAYER, &mixer->features);
  1615. of_property_read_string_index(np,
  1616. mixer_prop[MIXER_DISP].prop_name, i, &disp_pref);
  1617. if (disp_pref && !strcmp(disp_pref, "primary"))
  1618. set_bit(SDE_DISP_PRIMARY_PREF, &mixer->features);
  1619. of_property_read_string_index(np,
  1620. mixer_prop[MIXER_CWB].prop_name, i, &cwb_pref);
  1621. if (cwb_pref && !strcmp(cwb_pref, "cwb"))
  1622. set_bit(SDE_DISP_CWB_PREF, &mixer->features);
  1623. mixer->pingpong = pp_count > 0 ? pp_idx + PINGPONG_0
  1624. : PINGPONG_MAX;
  1625. mixer->dspp = dspp_count > 0 ? dspp_idx + DSPP_0
  1626. : DSPP_MAX;
  1627. mixer->ds = ds_count > 0 ? ds_idx + DS_0 : DS_MAX;
  1628. pp_count--;
  1629. dspp_count--;
  1630. ds_count--;
  1631. pp_idx++;
  1632. dspp_idx++;
  1633. ds_idx++;
  1634. mixer_count++;
  1635. sblk->gc.id = SDE_MIXER_GC;
  1636. if (blocks_prop_value && blocks_prop_exists[MIXER_GC_PROP]) {
  1637. sblk->gc.base = PROP_VALUE_ACCESS(blocks_prop_value,
  1638. MIXER_GC_PROP, 0);
  1639. sblk->gc.version = PROP_VALUE_ACCESS(blocks_prop_value,
  1640. MIXER_GC_PROP, 1);
  1641. sblk->gc.len = 0;
  1642. set_bit(SDE_MIXER_GC, &mixer->features);
  1643. }
  1644. }
  1645. sde_cfg->mixer_count = mixer_count;
  1646. end:
  1647. kfree(prop_value);
  1648. kfree(blocks_prop_value);
  1649. kfree(blend_prop_value);
  1650. return rc;
  1651. }
  1652. static int sde_intf_parse_dt(struct device_node *np,
  1653. struct sde_mdss_cfg *sde_cfg)
  1654. {
  1655. int rc, prop_count[INTF_PROP_MAX], i;
  1656. struct sde_prop_value *prop_value = NULL;
  1657. bool prop_exists[INTF_PROP_MAX];
  1658. u32 off_count;
  1659. u32 dsi_count = 0, none_count = 0, hdmi_count = 0, dp_count = 0;
  1660. const char *type;
  1661. struct sde_intf_cfg *intf;
  1662. if (!sde_cfg) {
  1663. SDE_ERROR("invalid argument\n");
  1664. rc = -EINVAL;
  1665. goto end;
  1666. }
  1667. prop_value = kzalloc(INTF_PROP_MAX *
  1668. sizeof(struct sde_prop_value), GFP_KERNEL);
  1669. if (!prop_value) {
  1670. rc = -ENOMEM;
  1671. goto end;
  1672. }
  1673. rc = _validate_dt_entry(np, intf_prop, ARRAY_SIZE(intf_prop),
  1674. prop_count, &off_count);
  1675. if (rc)
  1676. goto end;
  1677. sde_cfg->intf_count = off_count;
  1678. rc = _read_dt_entry(np, intf_prop, ARRAY_SIZE(intf_prop), prop_count,
  1679. prop_exists, prop_value);
  1680. if (rc)
  1681. goto end;
  1682. for (i = 0; i < off_count; i++) {
  1683. intf = sde_cfg->intf + i;
  1684. intf->base = PROP_VALUE_ACCESS(prop_value, INTF_OFF, i);
  1685. intf->len = PROP_VALUE_ACCESS(prop_value, INTF_LEN, 0);
  1686. intf->id = INTF_0 + i;
  1687. snprintf(intf->name, SDE_HW_BLK_NAME_LEN, "intf_%u",
  1688. intf->id - INTF_0);
  1689. if (!prop_exists[INTF_LEN])
  1690. intf->len = DEFAULT_SDE_HW_BLOCK_LEN;
  1691. intf->prog_fetch_lines_worst_case =
  1692. !prop_exists[INTF_PREFETCH] ?
  1693. sde_cfg->perf.min_prefill_lines :
  1694. PROP_VALUE_ACCESS(prop_value, INTF_PREFETCH, i);
  1695. of_property_read_string_index(np,
  1696. intf_prop[INTF_TYPE].prop_name, i, &type);
  1697. if (!strcmp(type, "dsi")) {
  1698. intf->type = INTF_DSI;
  1699. intf->controller_id = dsi_count;
  1700. dsi_count++;
  1701. } else if (!strcmp(type, "hdmi")) {
  1702. intf->type = INTF_HDMI;
  1703. intf->controller_id = hdmi_count;
  1704. hdmi_count++;
  1705. } else if (!strcmp(type, "dp")) {
  1706. intf->type = INTF_DP;
  1707. intf->controller_id = dp_count;
  1708. dp_count++;
  1709. } else {
  1710. intf->type = INTF_NONE;
  1711. intf->controller_id = none_count;
  1712. none_count++;
  1713. }
  1714. if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
  1715. set_bit(SDE_INTF_INPUT_CTRL, &intf->features);
  1716. if (IS_SDE_MAJOR_SAME((sde_cfg->hwversion),
  1717. SDE_HW_VER_500) ||
  1718. IS_SDE_MAJOR_SAME((sde_cfg->hwversion),
  1719. SDE_HW_VER_600))
  1720. set_bit(SDE_INTF_TE, &intf->features);
  1721. }
  1722. end:
  1723. kfree(prop_value);
  1724. return rc;
  1725. }
  1726. static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
  1727. {
  1728. int rc, prop_count[WB_PROP_MAX], i, j;
  1729. struct sde_prop_value *prop_value = NULL;
  1730. bool prop_exists[WB_PROP_MAX];
  1731. u32 off_count;
  1732. struct sde_wb_cfg *wb;
  1733. struct sde_wb_sub_blocks *sblk;
  1734. if (!sde_cfg) {
  1735. SDE_ERROR("invalid argument\n");
  1736. rc = -EINVAL;
  1737. goto end;
  1738. }
  1739. prop_value = kzalloc(WB_PROP_MAX *
  1740. sizeof(struct sde_prop_value), GFP_KERNEL);
  1741. if (!prop_value) {
  1742. rc = -ENOMEM;
  1743. goto end;
  1744. }
  1745. rc = _validate_dt_entry(np, wb_prop, ARRAY_SIZE(wb_prop), prop_count,
  1746. &off_count);
  1747. if (rc)
  1748. goto end;
  1749. sde_cfg->wb_count = off_count;
  1750. rc = _read_dt_entry(np, wb_prop, ARRAY_SIZE(wb_prop), prop_count,
  1751. prop_exists, prop_value);
  1752. if (rc)
  1753. goto end;
  1754. for (i = 0; i < off_count; i++) {
  1755. wb = sde_cfg->wb + i;
  1756. sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
  1757. if (!sblk) {
  1758. rc = -ENOMEM;
  1759. /* catalog deinit will release the allocated blocks */
  1760. goto end;
  1761. }
  1762. wb->sblk = sblk;
  1763. wb->base = PROP_VALUE_ACCESS(prop_value, WB_OFF, i);
  1764. wb->id = WB_0 + PROP_VALUE_ACCESS(prop_value, WB_ID, i);
  1765. snprintf(wb->name, SDE_HW_BLK_NAME_LEN, "wb_%u",
  1766. wb->id - WB_0);
  1767. wb->clk_ctrl = SDE_CLK_CTRL_WB0 +
  1768. PROP_VALUE_ACCESS(prop_value, WB_ID, i);
  1769. wb->xin_id = PROP_VALUE_ACCESS(prop_value, WB_XIN_ID, i);
  1770. if (wb->clk_ctrl >= SDE_CLK_CTRL_MAX) {
  1771. SDE_ERROR("%s: invalid clk ctrl: %d\n",
  1772. wb->name, wb->clk_ctrl);
  1773. rc = -EINVAL;
  1774. goto end;
  1775. }
  1776. if (IS_SDE_MAJOR_MINOR_SAME((sde_cfg->hwversion),
  1777. SDE_HW_VER_170))
  1778. wb->vbif_idx = VBIF_NRT;
  1779. else
  1780. wb->vbif_idx = VBIF_RT;
  1781. wb->len = PROP_VALUE_ACCESS(prop_value, WB_LEN, 0);
  1782. if (!prop_exists[WB_LEN])
  1783. wb->len = DEFAULT_SDE_HW_BLOCK_LEN;
  1784. sblk->maxlinewidth = sde_cfg->max_wb_linewidth;
  1785. if (wb->id >= LINE_MODE_WB_OFFSET)
  1786. set_bit(SDE_WB_LINE_MODE, &wb->features);
  1787. else
  1788. set_bit(SDE_WB_BLOCK_MODE, &wb->features);
  1789. set_bit(SDE_WB_TRAFFIC_SHAPER, &wb->features);
  1790. set_bit(SDE_WB_YUV_CONFIG, &wb->features);
  1791. if (sde_cfg->has_cdp)
  1792. set_bit(SDE_WB_CDP, &wb->features);
  1793. set_bit(SDE_WB_QOS, &wb->features);
  1794. if (sde_cfg->vbif_qos_nlvl == 8)
  1795. set_bit(SDE_WB_QOS_8LVL, &wb->features);
  1796. if (sde_cfg->has_wb_ubwc)
  1797. set_bit(SDE_WB_UBWC, &wb->features);
  1798. set_bit(SDE_WB_XY_ROI_OFFSET, &wb->features);
  1799. if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
  1800. set_bit(SDE_WB_INPUT_CTRL, &wb->features);
  1801. if (sde_cfg->has_cwb_support) {
  1802. set_bit(SDE_WB_HAS_CWB, &wb->features);
  1803. if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
  1804. set_bit(SDE_WB_CWB_CTRL, &wb->features);
  1805. }
  1806. for (j = 0; j < sde_cfg->mdp_count; j++) {
  1807. sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].reg_off =
  1808. PROP_BITVALUE_ACCESS(prop_value,
  1809. WB_CLK_CTRL, i, 0);
  1810. sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].bit_off =
  1811. PROP_BITVALUE_ACCESS(prop_value,
  1812. WB_CLK_CTRL, i, 1);
  1813. }
  1814. wb->format_list = sde_cfg->wb_formats;
  1815. SDE_DEBUG(
  1816. "wb:%d xin:%d vbif:%d clk%d:%x/%d\n",
  1817. wb->id - WB_0,
  1818. wb->xin_id,
  1819. wb->vbif_idx,
  1820. wb->clk_ctrl,
  1821. sde_cfg->mdp[0].clk_ctrls[wb->clk_ctrl].reg_off,
  1822. sde_cfg->mdp[0].clk_ctrls[wb->clk_ctrl].bit_off);
  1823. }
  1824. end:
  1825. kfree(prop_value);
  1826. return rc;
  1827. }
  1828. static void _sde_dspp_setup_blocks(struct sde_mdss_cfg *sde_cfg,
  1829. struct sde_dspp_cfg *dspp, struct sde_dspp_sub_blks *sblk,
  1830. bool *prop_exists, struct sde_prop_value *prop_value)
  1831. {
  1832. sblk->igc.id = SDE_DSPP_IGC;
  1833. if (prop_exists[DSPP_IGC_PROP]) {
  1834. sblk->igc.base = PROP_VALUE_ACCESS(prop_value,
  1835. DSPP_IGC_PROP, 0);
  1836. sblk->igc.version = PROP_VALUE_ACCESS(prop_value,
  1837. DSPP_IGC_PROP, 1);
  1838. sblk->igc.len = 0;
  1839. set_bit(SDE_DSPP_IGC, &dspp->features);
  1840. }
  1841. sblk->pcc.id = SDE_DSPP_PCC;
  1842. if (prop_exists[DSPP_PCC_PROP]) {
  1843. sblk->pcc.base = PROP_VALUE_ACCESS(prop_value,
  1844. DSPP_PCC_PROP, 0);
  1845. sblk->pcc.version = PROP_VALUE_ACCESS(prop_value,
  1846. DSPP_PCC_PROP, 1);
  1847. sblk->pcc.len = 0;
  1848. set_bit(SDE_DSPP_PCC, &dspp->features);
  1849. }
  1850. sblk->gc.id = SDE_DSPP_GC;
  1851. if (prop_exists[DSPP_GC_PROP]) {
  1852. sblk->gc.base = PROP_VALUE_ACCESS(prop_value, DSPP_GC_PROP, 0);
  1853. sblk->gc.version = PROP_VALUE_ACCESS(prop_value,
  1854. DSPP_GC_PROP, 1);
  1855. sblk->gc.len = 0;
  1856. set_bit(SDE_DSPP_GC, &dspp->features);
  1857. }
  1858. sblk->gamut.id = SDE_DSPP_GAMUT;
  1859. if (prop_exists[DSPP_GAMUT_PROP]) {
  1860. sblk->gamut.base = PROP_VALUE_ACCESS(prop_value,
  1861. DSPP_GAMUT_PROP, 0);
  1862. sblk->gamut.version = PROP_VALUE_ACCESS(prop_value,
  1863. DSPP_GAMUT_PROP, 1);
  1864. sblk->gamut.len = 0;
  1865. set_bit(SDE_DSPP_GAMUT, &dspp->features);
  1866. }
  1867. sblk->dither.id = SDE_DSPP_DITHER;
  1868. if (prop_exists[DSPP_DITHER_PROP]) {
  1869. sblk->dither.base = PROP_VALUE_ACCESS(prop_value,
  1870. DSPP_DITHER_PROP, 0);
  1871. sblk->dither.version = PROP_VALUE_ACCESS(prop_value,
  1872. DSPP_DITHER_PROP, 1);
  1873. sblk->dither.len = 0;
  1874. set_bit(SDE_DSPP_DITHER, &dspp->features);
  1875. }
  1876. sblk->hist.id = SDE_DSPP_HIST;
  1877. if (prop_exists[DSPP_HIST_PROP]) {
  1878. sblk->hist.base = PROP_VALUE_ACCESS(prop_value,
  1879. DSPP_HIST_PROP, 0);
  1880. sblk->hist.version = PROP_VALUE_ACCESS(prop_value,
  1881. DSPP_HIST_PROP, 1);
  1882. sblk->hist.len = 0;
  1883. set_bit(SDE_DSPP_HIST, &dspp->features);
  1884. }
  1885. sblk->hsic.id = SDE_DSPP_HSIC;
  1886. if (prop_exists[DSPP_HSIC_PROP]) {
  1887. sblk->hsic.base = PROP_VALUE_ACCESS(prop_value,
  1888. DSPP_HSIC_PROP, 0);
  1889. sblk->hsic.version = PROP_VALUE_ACCESS(prop_value,
  1890. DSPP_HSIC_PROP, 1);
  1891. sblk->hsic.len = 0;
  1892. set_bit(SDE_DSPP_HSIC, &dspp->features);
  1893. }
  1894. sblk->memcolor.id = SDE_DSPP_MEMCOLOR;
  1895. if (prop_exists[DSPP_MEMCOLOR_PROP]) {
  1896. sblk->memcolor.base = PROP_VALUE_ACCESS(prop_value,
  1897. DSPP_MEMCOLOR_PROP, 0);
  1898. sblk->memcolor.version = PROP_VALUE_ACCESS(prop_value,
  1899. DSPP_MEMCOLOR_PROP, 1);
  1900. sblk->memcolor.len = 0;
  1901. set_bit(SDE_DSPP_MEMCOLOR, &dspp->features);
  1902. }
  1903. sblk->sixzone.id = SDE_DSPP_SIXZONE;
  1904. if (prop_exists[DSPP_SIXZONE_PROP]) {
  1905. sblk->sixzone.base = PROP_VALUE_ACCESS(prop_value,
  1906. DSPP_SIXZONE_PROP, 0);
  1907. sblk->sixzone.version = PROP_VALUE_ACCESS(prop_value,
  1908. DSPP_SIXZONE_PROP, 1);
  1909. sblk->sixzone.len = 0;
  1910. set_bit(SDE_DSPP_SIXZONE, &dspp->features);
  1911. }
  1912. sblk->vlut.id = SDE_DSPP_VLUT;
  1913. if (prop_exists[DSPP_VLUT_PROP]) {
  1914. sblk->vlut.base = PROP_VALUE_ACCESS(prop_value,
  1915. DSPP_VLUT_PROP, 0);
  1916. sblk->vlut.version = PROP_VALUE_ACCESS(prop_value,
  1917. DSPP_VLUT_PROP, 1);
  1918. sblk->sixzone.len = 0;
  1919. set_bit(SDE_DSPP_VLUT, &dspp->features);
  1920. }
  1921. }
  1922. static int sde_rot_parse_dt(struct device_node *np,
  1923. struct sde_mdss_cfg *sde_cfg)
  1924. {
  1925. struct platform_device *pdev;
  1926. struct of_phandle_args phargs;
  1927. struct llcc_slice_desc *slice;
  1928. int rc = 0;
  1929. rc = of_parse_phandle_with_args(np,
  1930. "qcom,sde-inline-rotator", "#list-cells",
  1931. 0, &phargs);
  1932. if (rc) {
  1933. /*
  1934. * This is not a fatal error, system cache can be disabled
  1935. * in device tree, anyways recommendation is to have it
  1936. * enabled, so print an error but don't fail
  1937. */
  1938. SDE_DEBUG("sys cache will be disabled rc:%d\n", rc);
  1939. rc = 0;
  1940. goto exit;
  1941. }
  1942. if (!phargs.np || !phargs.args_count) {
  1943. SDE_ERROR("wrong phandle args %d %d\n",
  1944. !phargs.np, !phargs.args_count);
  1945. rc = -EINVAL;
  1946. goto exit;
  1947. }
  1948. pdev = of_find_device_by_node(phargs.np);
  1949. if (!pdev) {
  1950. SDE_ERROR("invalid sde rotator node\n");
  1951. goto exit;
  1952. }
  1953. slice = llcc_slice_getd(LLCC_ROTATOR);
  1954. if (IS_ERR_OR_NULL(slice)) {
  1955. SDE_ERROR("failed to get rotator slice!\n");
  1956. rc = -EINVAL;
  1957. goto cleanup;
  1958. }
  1959. sde_cfg->sc_cfg.llcc_scid = llcc_get_slice_id(slice);
  1960. sde_cfg->sc_cfg.llcc_slice_size = llcc_get_slice_size(slice);
  1961. llcc_slice_putd(slice);
  1962. sde_cfg->sc_cfg.has_sys_cache = true;
  1963. SDE_DEBUG("rotator llcc scid:%d slice_size:%zukb\n",
  1964. sde_cfg->sc_cfg.llcc_scid, sde_cfg->sc_cfg.llcc_slice_size);
  1965. cleanup:
  1966. of_node_put(phargs.np);
  1967. exit:
  1968. return rc;
  1969. }
  1970. static int sde_dspp_top_parse_dt(struct device_node *np,
  1971. struct sde_mdss_cfg *sde_cfg)
  1972. {
  1973. int rc, prop_count[DSPP_TOP_PROP_MAX];
  1974. bool prop_exists[DSPP_TOP_PROP_MAX];
  1975. struct sde_prop_value *prop_value = NULL;
  1976. u32 off_count;
  1977. if (!sde_cfg) {
  1978. SDE_ERROR("invalid argument\n");
  1979. rc = -EINVAL;
  1980. goto end;
  1981. }
  1982. prop_value = kzalloc(DSPP_TOP_PROP_MAX *
  1983. sizeof(struct sde_prop_value), GFP_KERNEL);
  1984. if (!prop_value) {
  1985. rc = -ENOMEM;
  1986. goto end;
  1987. }
  1988. rc = _validate_dt_entry(np, dspp_top_prop, ARRAY_SIZE(dspp_top_prop),
  1989. prop_count, &off_count);
  1990. if (rc)
  1991. goto end;
  1992. rc = _read_dt_entry(np, dspp_top_prop, ARRAY_SIZE(dspp_top_prop),
  1993. prop_count, prop_exists, prop_value);
  1994. if (rc)
  1995. goto end;
  1996. if (off_count != 1) {
  1997. SDE_ERROR("invalid dspp_top off_count:%d\n", off_count);
  1998. rc = -EINVAL;
  1999. goto end;
  2000. }
  2001. sde_cfg->dspp_top.base =
  2002. PROP_VALUE_ACCESS(prop_value, DSPP_TOP_OFF, 0);
  2003. sde_cfg->dspp_top.len =
  2004. PROP_VALUE_ACCESS(prop_value, DSPP_TOP_SIZE, 0);
  2005. snprintf(sde_cfg->dspp_top.name, SDE_HW_BLK_NAME_LEN, "dspp_top");
  2006. end:
  2007. kfree(prop_value);
  2008. return rc;
  2009. }
  2010. static int sde_dspp_parse_dt(struct device_node *np,
  2011. struct sde_mdss_cfg *sde_cfg)
  2012. {
  2013. int rc, prop_count[DSPP_PROP_MAX], i;
  2014. int ad_prop_count[AD_PROP_MAX];
  2015. int ltm_prop_count[LTM_PROP_MAX];
  2016. bool prop_exists[DSPP_PROP_MAX], ad_prop_exists[AD_PROP_MAX];
  2017. bool ltm_prop_exists[LTM_PROP_MAX];
  2018. bool blocks_prop_exists[DSPP_BLOCKS_PROP_MAX];
  2019. struct sde_prop_value *ad_prop_value = NULL, *ltm_prop_value = NULL;
  2020. int blocks_prop_count[DSPP_BLOCKS_PROP_MAX];
  2021. struct sde_prop_value *prop_value = NULL, *blocks_prop_value = NULL;
  2022. u32 off_count, ad_off_count, ltm_off_count;
  2023. struct sde_dspp_cfg *dspp;
  2024. struct sde_dspp_sub_blks *sblk;
  2025. struct device_node *snp = NULL;
  2026. if (!sde_cfg) {
  2027. SDE_ERROR("invalid argument\n");
  2028. rc = -EINVAL;
  2029. goto end;
  2030. }
  2031. prop_value = kzalloc(DSPP_PROP_MAX *
  2032. sizeof(struct sde_prop_value), GFP_KERNEL);
  2033. if (!prop_value) {
  2034. rc = -ENOMEM;
  2035. goto end;
  2036. }
  2037. rc = _validate_dt_entry(np, dspp_prop, ARRAY_SIZE(dspp_prop),
  2038. prop_count, &off_count);
  2039. if (rc)
  2040. goto end;
  2041. sde_cfg->dspp_count = off_count;
  2042. rc = _read_dt_entry(np, dspp_prop, ARRAY_SIZE(dspp_prop), prop_count,
  2043. prop_exists, prop_value);
  2044. if (rc)
  2045. goto end;
  2046. /* Parse AD dtsi entries */
  2047. ad_prop_value = kcalloc(AD_PROP_MAX,
  2048. sizeof(struct sde_prop_value), GFP_KERNEL);
  2049. if (!ad_prop_value) {
  2050. rc = -ENOMEM;
  2051. goto end;
  2052. }
  2053. rc = _validate_dt_entry(np, ad_prop, ARRAY_SIZE(ad_prop),
  2054. ad_prop_count, &ad_off_count);
  2055. if (rc)
  2056. goto end;
  2057. rc = _read_dt_entry(np, ad_prop, ARRAY_SIZE(ad_prop), ad_prop_count,
  2058. ad_prop_exists, ad_prop_value);
  2059. if (rc)
  2060. goto end;
  2061. /* Parse LTM dtsi entries */
  2062. ltm_prop_value = kcalloc(LTM_PROP_MAX,
  2063. sizeof(struct sde_prop_value), GFP_KERNEL);
  2064. if (!ltm_prop_value) {
  2065. rc = -ENOMEM;
  2066. goto end;
  2067. }
  2068. rc = _validate_dt_entry(np, ltm_prop, ARRAY_SIZE(ltm_prop),
  2069. ltm_prop_count, &ltm_off_count);
  2070. if (rc)
  2071. goto end;
  2072. rc = _read_dt_entry(np, ltm_prop, ARRAY_SIZE(ltm_prop), ltm_prop_count,
  2073. ltm_prop_exists, ltm_prop_value);
  2074. if (rc)
  2075. goto end;
  2076. /* get DSPP feature dt properties if they exist */
  2077. snp = of_get_child_by_name(np, dspp_prop[DSPP_BLOCKS].prop_name);
  2078. if (snp) {
  2079. blocks_prop_value = kzalloc(DSPP_BLOCKS_PROP_MAX *
  2080. MAX_SDE_HW_BLK * sizeof(struct sde_prop_value),
  2081. GFP_KERNEL);
  2082. if (!blocks_prop_value) {
  2083. rc = -ENOMEM;
  2084. goto end;
  2085. }
  2086. rc = _validate_dt_entry(snp, dspp_blocks_prop,
  2087. ARRAY_SIZE(dspp_blocks_prop), blocks_prop_count, NULL);
  2088. if (rc)
  2089. goto end;
  2090. rc = _read_dt_entry(snp, dspp_blocks_prop,
  2091. ARRAY_SIZE(dspp_blocks_prop), blocks_prop_count,
  2092. blocks_prop_exists, blocks_prop_value);
  2093. if (rc)
  2094. goto end;
  2095. }
  2096. for (i = 0; i < off_count; i++) {
  2097. dspp = sde_cfg->dspp + i;
  2098. dspp->base = PROP_VALUE_ACCESS(prop_value, DSPP_OFF, i);
  2099. dspp->len = PROP_VALUE_ACCESS(prop_value, DSPP_SIZE, 0);
  2100. dspp->id = DSPP_0 + i;
  2101. snprintf(dspp->name, SDE_HW_BLK_NAME_LEN, "dspp_%u",
  2102. dspp->id - DSPP_0);
  2103. sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
  2104. if (!sblk) {
  2105. rc = -ENOMEM;
  2106. /* catalog deinit will release the allocated blocks */
  2107. goto end;
  2108. }
  2109. dspp->sblk = sblk;
  2110. if (blocks_prop_value)
  2111. _sde_dspp_setup_blocks(sde_cfg, dspp, sblk,
  2112. blocks_prop_exists, blocks_prop_value);
  2113. sblk->ad.id = SDE_DSPP_AD;
  2114. sde_cfg->ad_count = ad_off_count;
  2115. if (ad_prop_value && (i < ad_off_count) &&
  2116. ad_prop_exists[AD_OFF]) {
  2117. sblk->ad.base = PROP_VALUE_ACCESS(ad_prop_value,
  2118. AD_OFF, i);
  2119. sblk->ad.version = PROP_VALUE_ACCESS(ad_prop_value,
  2120. AD_VERSION, 0);
  2121. set_bit(SDE_DSPP_AD, &dspp->features);
  2122. }
  2123. sblk->ltm.id = SDE_DSPP_LTM;
  2124. sde_cfg->ltm_count = ltm_off_count;
  2125. if (ltm_prop_value && (i < ltm_off_count) &&
  2126. ltm_prop_exists[LTM_OFF]) {
  2127. sblk->ltm.base = PROP_VALUE_ACCESS(ltm_prop_value,
  2128. LTM_OFF, i);
  2129. sblk->ltm.version = PROP_VALUE_ACCESS(ltm_prop_value,
  2130. LTM_VERSION, 0);
  2131. set_bit(SDE_DSPP_LTM, &dspp->features);
  2132. }
  2133. }
  2134. end:
  2135. kfree(prop_value);
  2136. kfree(ad_prop_value);
  2137. kfree(ltm_prop_value);
  2138. kfree(blocks_prop_value);
  2139. return rc;
  2140. }
  2141. static int sde_ds_parse_dt(struct device_node *np,
  2142. struct sde_mdss_cfg *sde_cfg)
  2143. {
  2144. int rc, prop_count[DS_PROP_MAX], top_prop_count[DS_TOP_PROP_MAX], i;
  2145. struct sde_prop_value *prop_value = NULL, *top_prop_value = NULL;
  2146. bool prop_exists[DS_PROP_MAX], top_prop_exists[DS_TOP_PROP_MAX];
  2147. u32 off_count = 0, top_off_count = 0;
  2148. struct sde_ds_cfg *ds;
  2149. struct sde_ds_top_cfg *ds_top = NULL;
  2150. if (!sde_cfg) {
  2151. SDE_ERROR("invalid argument\n");
  2152. rc = -EINVAL;
  2153. goto end;
  2154. }
  2155. if (!sde_cfg->mdp[0].has_dest_scaler) {
  2156. SDE_DEBUG("dest scaler feature not supported\n");
  2157. rc = 0;
  2158. goto end;
  2159. }
  2160. /* Parse the dest scaler top register offset and capabilities */
  2161. top_prop_value = kzalloc(DS_TOP_PROP_MAX *
  2162. sizeof(struct sde_prop_value), GFP_KERNEL);
  2163. if (!top_prop_value) {
  2164. rc = -ENOMEM;
  2165. goto end;
  2166. }
  2167. rc = _validate_dt_entry(np, ds_top_prop,
  2168. ARRAY_SIZE(ds_top_prop),
  2169. top_prop_count, &top_off_count);
  2170. if (rc)
  2171. goto end;
  2172. rc = _read_dt_entry(np, ds_top_prop,
  2173. ARRAY_SIZE(ds_top_prop), top_prop_count,
  2174. top_prop_exists, top_prop_value);
  2175. if (rc)
  2176. goto end;
  2177. /* Parse the offset of each dest scaler block */
  2178. prop_value = kcalloc(DS_PROP_MAX,
  2179. sizeof(struct sde_prop_value), GFP_KERNEL);
  2180. if (!prop_value) {
  2181. rc = -ENOMEM;
  2182. goto end;
  2183. }
  2184. rc = _validate_dt_entry(np, ds_prop, ARRAY_SIZE(ds_prop), prop_count,
  2185. &off_count);
  2186. if (rc)
  2187. goto end;
  2188. sde_cfg->ds_count = off_count;
  2189. rc = _read_dt_entry(np, ds_prop, ARRAY_SIZE(ds_prop), prop_count,
  2190. prop_exists, prop_value);
  2191. if (rc)
  2192. goto end;
  2193. if (!off_count)
  2194. goto end;
  2195. ds_top = kzalloc(sizeof(struct sde_ds_top_cfg), GFP_KERNEL);
  2196. if (!ds_top) {
  2197. rc = -ENOMEM;
  2198. goto end;
  2199. }
  2200. ds_top->id = DS_TOP;
  2201. snprintf(ds_top->name, SDE_HW_BLK_NAME_LEN, "ds_top_%u",
  2202. ds_top->id - DS_TOP);
  2203. ds_top->base = PROP_VALUE_ACCESS(top_prop_value, DS_TOP_OFF, 0);
  2204. ds_top->len = PROP_VALUE_ACCESS(top_prop_value, DS_TOP_LEN, 0);
  2205. ds_top->maxupscale = MAX_UPSCALE_RATIO;
  2206. ds_top->maxinputwidth = PROP_VALUE_ACCESS(top_prop_value,
  2207. DS_TOP_INPUT_LINEWIDTH, 0);
  2208. if (!top_prop_exists[DS_TOP_INPUT_LINEWIDTH])
  2209. ds_top->maxinputwidth = DEFAULT_SDE_LINE_WIDTH;
  2210. ds_top->maxoutputwidth = PROP_VALUE_ACCESS(top_prop_value,
  2211. DS_TOP_OUTPUT_LINEWIDTH, 0);
  2212. if (!top_prop_exists[DS_TOP_OUTPUT_LINEWIDTH])
  2213. ds_top->maxoutputwidth = DEFAULT_SDE_OUTPUT_LINE_WIDTH;
  2214. for (i = 0; i < off_count; i++) {
  2215. ds = sde_cfg->ds + i;
  2216. ds->top = ds_top;
  2217. ds->base = PROP_VALUE_ACCESS(prop_value, DS_OFF, i);
  2218. ds->id = DS_0 + i;
  2219. ds->len = PROP_VALUE_ACCESS(prop_value, DS_LEN, 0);
  2220. snprintf(ds->name, SDE_HW_BLK_NAME_LEN, "ds_%u",
  2221. ds->id - DS_0);
  2222. if (!prop_exists[DS_LEN])
  2223. ds->len = DEFAULT_SDE_HW_BLOCK_LEN;
  2224. if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3)
  2225. set_bit(SDE_SSPP_SCALER_QSEED3, &ds->features);
  2226. else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
  2227. set_bit(SDE_SSPP_SCALER_QSEED3LITE, &ds->features);
  2228. }
  2229. end:
  2230. kfree(top_prop_value);
  2231. kfree(prop_value);
  2232. return rc;
  2233. };
  2234. static int sde_dsc_parse_dt(struct device_node *np,
  2235. struct sde_mdss_cfg *sde_cfg)
  2236. {
  2237. int rc, prop_count[MAX_BLOCKS], i;
  2238. struct sde_prop_value *prop_value = NULL;
  2239. bool prop_exists[DSC_PROP_MAX];
  2240. u32 off_count;
  2241. struct sde_dsc_cfg *dsc;
  2242. if (!sde_cfg) {
  2243. SDE_ERROR("invalid argument\n");
  2244. rc = -EINVAL;
  2245. goto end;
  2246. }
  2247. prop_value = kzalloc(DSC_PROP_MAX *
  2248. sizeof(struct sde_prop_value), GFP_KERNEL);
  2249. if (!prop_value) {
  2250. rc = -ENOMEM;
  2251. goto end;
  2252. }
  2253. rc = _validate_dt_entry(np, dsc_prop, ARRAY_SIZE(dsc_prop), prop_count,
  2254. &off_count);
  2255. if (rc)
  2256. goto end;
  2257. sde_cfg->dsc_count = off_count;
  2258. rc = _read_dt_entry(np, dsc_prop, ARRAY_SIZE(dsc_prop), prop_count,
  2259. prop_exists, prop_value);
  2260. if (rc)
  2261. goto end;
  2262. for (i = 0; i < off_count; i++) {
  2263. dsc = sde_cfg->dsc + i;
  2264. dsc->base = PROP_VALUE_ACCESS(prop_value, DSC_OFF, i);
  2265. dsc->id = DSC_0 + i;
  2266. dsc->len = PROP_VALUE_ACCESS(prop_value, DSC_LEN, 0);
  2267. snprintf(dsc->name, SDE_HW_BLK_NAME_LEN, "dsc_%u",
  2268. dsc->id - DSC_0);
  2269. if (!prop_exists[DSC_LEN])
  2270. dsc->len = DEFAULT_SDE_HW_BLOCK_LEN;
  2271. if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
  2272. set_bit(SDE_DSC_OUTPUT_CTRL, &dsc->features);
  2273. }
  2274. end:
  2275. kfree(prop_value);
  2276. return rc;
  2277. };
  2278. static int sde_cdm_parse_dt(struct device_node *np,
  2279. struct sde_mdss_cfg *sde_cfg)
  2280. {
  2281. int rc, prop_count[HW_PROP_MAX], i;
  2282. struct sde_prop_value *prop_value = NULL;
  2283. bool prop_exists[HW_PROP_MAX];
  2284. u32 off_count;
  2285. struct sde_cdm_cfg *cdm;
  2286. if (!sde_cfg) {
  2287. SDE_ERROR("invalid argument\n");
  2288. rc = -EINVAL;
  2289. goto end;
  2290. }
  2291. prop_value = kzalloc(HW_PROP_MAX *
  2292. sizeof(struct sde_prop_value), GFP_KERNEL);
  2293. if (!prop_value) {
  2294. rc = -ENOMEM;
  2295. goto end;
  2296. }
  2297. rc = _validate_dt_entry(np, cdm_prop, ARRAY_SIZE(cdm_prop), prop_count,
  2298. &off_count);
  2299. if (rc)
  2300. goto end;
  2301. sde_cfg->cdm_count = off_count;
  2302. rc = _read_dt_entry(np, cdm_prop, ARRAY_SIZE(cdm_prop), prop_count,
  2303. prop_exists, prop_value);
  2304. if (rc)
  2305. goto end;
  2306. for (i = 0; i < off_count; i++) {
  2307. cdm = sde_cfg->cdm + i;
  2308. cdm->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
  2309. cdm->id = CDM_0 + i;
  2310. snprintf(cdm->name, SDE_HW_BLK_NAME_LEN, "cdm_%u",
  2311. cdm->id - CDM_0);
  2312. cdm->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);
  2313. /* intf3 and wb2 for cdm block */
  2314. cdm->wb_connect = sde_cfg->wb_count ? BIT(WB_2) : BIT(31);
  2315. cdm->intf_connect = sde_cfg->intf_count ? BIT(INTF_3) : BIT(31);
  2316. if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
  2317. set_bit(SDE_CDM_INPUT_CTRL, &cdm->features);
  2318. }
  2319. end:
  2320. kfree(prop_value);
  2321. return rc;
  2322. }
  2323. static int sde_uidle_parse_dt(struct device_node *np,
  2324. struct sde_mdss_cfg *sde_cfg)
  2325. {
  2326. int rc = 0, prop_count[UIDLE_PROP_MAX];
  2327. bool prop_exists[UIDLE_PROP_MAX];
  2328. struct sde_prop_value *prop_value = NULL;
  2329. u32 off_count;
  2330. if (!sde_cfg) {
  2331. SDE_ERROR("invalid argument\n");
  2332. return -EINVAL;
  2333. }
  2334. if (!sde_cfg->uidle_cfg.uidle_rev)
  2335. return 0;
  2336. prop_value = kcalloc(UIDLE_PROP_MAX,
  2337. sizeof(struct sde_prop_value), GFP_KERNEL);
  2338. if (!prop_value)
  2339. return -ENOMEM;
  2340. rc = _validate_dt_entry(np, uidle_prop, ARRAY_SIZE(uidle_prop),
  2341. prop_count, &off_count);
  2342. if (rc)
  2343. goto end;
  2344. rc = _read_dt_entry(np, uidle_prop, ARRAY_SIZE(uidle_prop), prop_count,
  2345. prop_exists, prop_value);
  2346. if (rc)
  2347. goto end;
  2348. if (!prop_exists[UIDLE_LEN] || !prop_exists[UIDLE_OFF]) {
  2349. SDE_DEBUG("offset/len missing, will disable uidle:%d,%d\n",
  2350. prop_exists[UIDLE_LEN], prop_exists[UIDLE_OFF]);
  2351. rc = -EINVAL;
  2352. goto end;
  2353. }
  2354. sde_cfg->uidle_cfg.id = UIDLE;
  2355. sde_cfg->uidle_cfg.base =
  2356. PROP_VALUE_ACCESS(prop_value, UIDLE_OFF, 0);
  2357. sde_cfg->uidle_cfg.len =
  2358. PROP_VALUE_ACCESS(prop_value, UIDLE_LEN, 0);
  2359. /* validate */
  2360. if (!sde_cfg->uidle_cfg.base || !sde_cfg->uidle_cfg.len) {
  2361. SDE_ERROR("invalid reg/len [%d, %d], will disable uidle\n",
  2362. sde_cfg->uidle_cfg.base, sde_cfg->uidle_cfg.len);
  2363. rc = -EINVAL;
  2364. }
  2365. end:
  2366. if (rc && sde_cfg->uidle_cfg.uidle_rev) {
  2367. SDE_DEBUG("wrong dt entries, will disable uidle\n");
  2368. sde_cfg->uidle_cfg.uidle_rev = 0;
  2369. }
  2370. kfree(prop_value);
  2371. /* optional feature, so always return success */
  2372. return 0;
  2373. }
  2374. static int _sde_vbif_populate_ot_parsing(struct sde_vbif_cfg *vbif,
  2375. struct sde_prop_value *prop_value, int *prop_count)
  2376. {
  2377. int j, k;
  2378. vbif->default_ot_rd_limit = PROP_VALUE_ACCESS(prop_value,
  2379. VBIF_DEFAULT_OT_RD_LIMIT, 0);
  2380. SDE_DEBUG("default_ot_rd_limit=%u\n",
  2381. vbif->default_ot_rd_limit);
  2382. vbif->default_ot_wr_limit = PROP_VALUE_ACCESS(prop_value,
  2383. VBIF_DEFAULT_OT_WR_LIMIT, 0);
  2384. SDE_DEBUG("default_ot_wr_limit=%u\n",
  2385. vbif->default_ot_wr_limit);
  2386. vbif->dynamic_ot_rd_tbl.count =
  2387. prop_count[VBIF_DYNAMIC_OT_RD_LIMIT] / 2;
  2388. SDE_DEBUG("dynamic_ot_rd_tbl.count=%u\n",
  2389. vbif->dynamic_ot_rd_tbl.count);
  2390. if (vbif->dynamic_ot_rd_tbl.count) {
  2391. vbif->dynamic_ot_rd_tbl.cfg = kcalloc(
  2392. vbif->dynamic_ot_rd_tbl.count,
  2393. sizeof(struct sde_vbif_dynamic_ot_cfg),
  2394. GFP_KERNEL);
  2395. if (!vbif->dynamic_ot_rd_tbl.cfg)
  2396. return -ENOMEM;
  2397. }
  2398. for (j = 0, k = 0; j < vbif->dynamic_ot_rd_tbl.count; j++) {
  2399. vbif->dynamic_ot_rd_tbl.cfg[j].pps = (u64)
  2400. PROP_VALUE_ACCESS(prop_value,
  2401. VBIF_DYNAMIC_OT_RD_LIMIT, k++);
  2402. vbif->dynamic_ot_rd_tbl.cfg[j].ot_limit =
  2403. PROP_VALUE_ACCESS(prop_value,
  2404. VBIF_DYNAMIC_OT_RD_LIMIT, k++);
  2405. SDE_DEBUG("dynamic_ot_rd_tbl[%d].cfg=<%llu %u>\n", j,
  2406. vbif->dynamic_ot_rd_tbl.cfg[j].pps,
  2407. vbif->dynamic_ot_rd_tbl.cfg[j].ot_limit);
  2408. }
  2409. vbif->dynamic_ot_wr_tbl.count =
  2410. prop_count[VBIF_DYNAMIC_OT_WR_LIMIT] / 2;
  2411. SDE_DEBUG("dynamic_ot_wr_tbl.count=%u\n",
  2412. vbif->dynamic_ot_wr_tbl.count);
  2413. if (vbif->dynamic_ot_wr_tbl.count) {
  2414. vbif->dynamic_ot_wr_tbl.cfg = kcalloc(
  2415. vbif->dynamic_ot_wr_tbl.count,
  2416. sizeof(struct sde_vbif_dynamic_ot_cfg),
  2417. GFP_KERNEL);
  2418. if (!vbif->dynamic_ot_wr_tbl.cfg)
  2419. return -ENOMEM;
  2420. }
  2421. for (j = 0, k = 0; j < vbif->dynamic_ot_wr_tbl.count; j++) {
  2422. vbif->dynamic_ot_wr_tbl.cfg[j].pps = (u64)
  2423. PROP_VALUE_ACCESS(prop_value,
  2424. VBIF_DYNAMIC_OT_WR_LIMIT, k++);
  2425. vbif->dynamic_ot_wr_tbl.cfg[j].ot_limit =
  2426. PROP_VALUE_ACCESS(prop_value,
  2427. VBIF_DYNAMIC_OT_WR_LIMIT, k++);
  2428. SDE_DEBUG("dynamic_ot_wr_tbl[%d].cfg=<%llu %u>\n", j,
  2429. vbif->dynamic_ot_wr_tbl.cfg[j].pps,
  2430. vbif->dynamic_ot_wr_tbl.cfg[j].ot_limit);
  2431. }
  2432. if (vbif->default_ot_rd_limit || vbif->default_ot_wr_limit ||
  2433. vbif->dynamic_ot_rd_tbl.count ||
  2434. vbif->dynamic_ot_wr_tbl.count)
  2435. set_bit(SDE_VBIF_QOS_OTLIM, &vbif->features);
  2436. return 0;
  2437. }
  2438. static int _sde_vbif_populate_qos_parsing(struct sde_mdss_cfg *sde_cfg,
  2439. struct sde_vbif_cfg *vbif, struct sde_prop_value *prop_value,
  2440. int *prop_count)
  2441. {
  2442. int i, j;
  2443. int prop_index = VBIF_QOS_RT_REMAP;
  2444. for (i = VBIF_RT_CLIENT;
  2445. ((i < VBIF_MAX_CLIENT) && (prop_index < VBIF_PROP_MAX));
  2446. i++, prop_index++) {
  2447. vbif->qos_tbl[i].npriority_lvl = prop_count[prop_index];
  2448. SDE_DEBUG("qos_tbl[%d].npriority_lvl=%u\n",
  2449. i, vbif->qos_tbl[i].npriority_lvl);
  2450. if (vbif->qos_tbl[i].npriority_lvl == sde_cfg->vbif_qos_nlvl) {
  2451. vbif->qos_tbl[i].priority_lvl = kcalloc(
  2452. vbif->qos_tbl[i].npriority_lvl,
  2453. sizeof(u32), GFP_KERNEL);
  2454. if (!vbif->qos_tbl[i].priority_lvl)
  2455. return -ENOMEM;
  2456. } else if (vbif->qos_tbl[i].npriority_lvl) {
  2457. vbif->qos_tbl[i].npriority_lvl = 0;
  2458. vbif->qos_tbl[i].priority_lvl = NULL;
  2459. SDE_ERROR("invalid qos table for client:%d, prop:%d\n",
  2460. i, prop_index);
  2461. }
  2462. for (j = 0; j < vbif->qos_tbl[i].npriority_lvl; j++) {
  2463. vbif->qos_tbl[i].priority_lvl[j] =
  2464. PROP_VALUE_ACCESS(prop_value, prop_index, j);
  2465. SDE_DEBUG("client:%d, prop:%d, lvl[%d]=%u\n",
  2466. i, prop_index, j,
  2467. vbif->qos_tbl[i].priority_lvl[j]);
  2468. }
  2469. if (vbif->qos_tbl[i].npriority_lvl)
  2470. set_bit(SDE_VBIF_QOS_REMAP, &vbif->features);
  2471. }
  2472. return 0;
  2473. }
  2474. static int _sde_vbif_populate(struct sde_mdss_cfg *sde_cfg,
  2475. struct sde_vbif_cfg *vbif, struct sde_prop_value *prop_value,
  2476. int *prop_count, u32 vbif_len, int i)
  2477. {
  2478. int j, k, rc;
  2479. vbif = sde_cfg->vbif + i;
  2480. vbif->base = PROP_VALUE_ACCESS(prop_value, VBIF_OFF, i);
  2481. vbif->len = vbif_len;
  2482. vbif->id = VBIF_0 + PROP_VALUE_ACCESS(prop_value, VBIF_ID, i);
  2483. snprintf(vbif->name, SDE_HW_BLK_NAME_LEN, "vbif_%u",
  2484. vbif->id - VBIF_0);
  2485. SDE_DEBUG("vbif:%d\n", vbif->id - VBIF_0);
  2486. vbif->xin_halt_timeout = VBIF_XIN_HALT_TIMEOUT;
  2487. rc = _sde_vbif_populate_ot_parsing(vbif, prop_value, prop_count);
  2488. if (rc)
  2489. return rc;
  2490. rc = _sde_vbif_populate_qos_parsing(sde_cfg, vbif, prop_value,
  2491. prop_count);
  2492. if (rc)
  2493. return rc;
  2494. vbif->memtype_count = prop_count[VBIF_MEMTYPE_0] +
  2495. prop_count[VBIF_MEMTYPE_1];
  2496. if (vbif->memtype_count > MAX_XIN_COUNT) {
  2497. vbif->memtype_count = 0;
  2498. SDE_ERROR("too many memtype defs, ignoring entries\n");
  2499. }
  2500. for (j = 0, k = 0; j < prop_count[VBIF_MEMTYPE_0]; j++)
  2501. vbif->memtype[k++] = PROP_VALUE_ACCESS(
  2502. prop_value, VBIF_MEMTYPE_0, j);
  2503. for (j = 0; j < prop_count[VBIF_MEMTYPE_1]; j++)
  2504. vbif->memtype[k++] = PROP_VALUE_ACCESS(
  2505. prop_value, VBIF_MEMTYPE_1, j);
  2506. return 0;
  2507. }
  2508. static int sde_vbif_parse_dt(struct device_node *np,
  2509. struct sde_mdss_cfg *sde_cfg)
  2510. {
  2511. int rc, prop_count[VBIF_PROP_MAX], i;
  2512. struct sde_prop_value *prop_value = NULL;
  2513. bool prop_exists[VBIF_PROP_MAX];
  2514. u32 off_count, vbif_len;
  2515. struct sde_vbif_cfg *vbif;
  2516. if (!sde_cfg) {
  2517. SDE_ERROR("invalid argument\n");
  2518. rc = -EINVAL;
  2519. goto end;
  2520. }
  2521. prop_value = kzalloc(VBIF_PROP_MAX *
  2522. sizeof(struct sde_prop_value), GFP_KERNEL);
  2523. if (!prop_value) {
  2524. rc = -ENOMEM;
  2525. goto end;
  2526. }
  2527. rc = _validate_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop),
  2528. prop_count, &off_count);
  2529. if (rc)
  2530. goto end;
  2531. rc = _validate_dt_entry(np, &vbif_prop[VBIF_DYNAMIC_OT_RD_LIMIT], 1,
  2532. &prop_count[VBIF_DYNAMIC_OT_RD_LIMIT], NULL);
  2533. if (rc)
  2534. goto end;
  2535. rc = _validate_dt_entry(np, &vbif_prop[VBIF_DYNAMIC_OT_WR_LIMIT], 1,
  2536. &prop_count[VBIF_DYNAMIC_OT_WR_LIMIT], NULL);
  2537. if (rc)
  2538. goto end;
  2539. rc = _validate_dt_entry(np, &vbif_prop[VBIF_MEMTYPE_0], 1,
  2540. &prop_count[VBIF_MEMTYPE_0], NULL);
  2541. if (rc)
  2542. goto end;
  2543. rc = _validate_dt_entry(np, &vbif_prop[VBIF_MEMTYPE_1], 1,
  2544. &prop_count[VBIF_MEMTYPE_1], NULL);
  2545. if (rc)
  2546. goto end;
  2547. rc = _validate_dt_entry(np, &vbif_prop[VBIF_QOS_RT_REMAP], 1,
  2548. &prop_count[VBIF_QOS_RT_REMAP], NULL);
  2549. if (rc)
  2550. goto end;
  2551. rc = _validate_dt_entry(np, &vbif_prop[VBIF_QOS_NRT_REMAP], 1,
  2552. &prop_count[VBIF_QOS_NRT_REMAP], NULL);
  2553. if (rc)
  2554. goto end;
  2555. rc = _validate_dt_entry(np, &vbif_prop[VBIF_QOS_CWB_REMAP], 1,
  2556. &prop_count[VBIF_QOS_CWB_REMAP], NULL);
  2557. if (rc)
  2558. goto end;
  2559. rc = _validate_dt_entry(np, &vbif_prop[VBIF_QOS_LUTDMA_REMAP], 1,
  2560. &prop_count[VBIF_QOS_LUTDMA_REMAP], NULL);
  2561. if (rc)
  2562. goto end;
  2563. sde_cfg->vbif_count = off_count;
  2564. rc = _read_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop), prop_count,
  2565. prop_exists, prop_value);
  2566. if (rc)
  2567. goto end;
  2568. vbif_len = PROP_VALUE_ACCESS(prop_value, VBIF_LEN, 0);
  2569. if (!prop_exists[VBIF_LEN])
  2570. vbif_len = DEFAULT_SDE_HW_BLOCK_LEN;
  2571. for (i = 0; i < off_count; i++) {
  2572. rc = _sde_vbif_populate(sde_cfg, vbif, prop_value,
  2573. prop_count, vbif_len, i);
  2574. if (rc)
  2575. goto end;
  2576. }
  2577. end:
  2578. kfree(prop_value);
  2579. return rc;
  2580. }
  2581. static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
  2582. {
  2583. int rc, prop_count[PP_PROP_MAX], i;
  2584. struct sde_prop_value *prop_value = NULL;
  2585. bool prop_exists[PP_PROP_MAX];
  2586. u32 off_count, major_version;
  2587. struct sde_pingpong_cfg *pp;
  2588. struct sde_pingpong_sub_blks *sblk;
  2589. if (!sde_cfg) {
  2590. SDE_ERROR("invalid argument\n");
  2591. rc = -EINVAL;
  2592. goto end;
  2593. }
  2594. prop_value = kzalloc(PP_PROP_MAX *
  2595. sizeof(struct sde_prop_value), GFP_KERNEL);
  2596. if (!prop_value) {
  2597. rc = -ENOMEM;
  2598. goto end;
  2599. }
  2600. rc = _validate_dt_entry(np, pp_prop, ARRAY_SIZE(pp_prop), prop_count,
  2601. &off_count);
  2602. if (rc)
  2603. goto end;
  2604. sde_cfg->pingpong_count = off_count;
  2605. rc = _read_dt_entry(np, pp_prop, ARRAY_SIZE(pp_prop), prop_count,
  2606. prop_exists, prop_value);
  2607. if (rc)
  2608. goto end;
  2609. for (i = 0; i < off_count; i++) {
  2610. pp = sde_cfg->pingpong + i;
  2611. sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
  2612. if (!sblk) {
  2613. rc = -ENOMEM;
  2614. /* catalog deinit will release the allocated blocks */
  2615. goto end;
  2616. }
  2617. pp->sblk = sblk;
  2618. pp->base = PROP_VALUE_ACCESS(prop_value, PP_OFF, i);
  2619. pp->id = PINGPONG_0 + i;
  2620. snprintf(pp->name, SDE_HW_BLK_NAME_LEN, "pingpong_%u",
  2621. pp->id - PINGPONG_0);
  2622. pp->len = PROP_VALUE_ACCESS(prop_value, PP_LEN, 0);
  2623. sblk->te.base = PROP_VALUE_ACCESS(prop_value, TE_OFF, i);
  2624. sblk->te.id = SDE_PINGPONG_TE;
  2625. snprintf(sblk->te.name, SDE_HW_BLK_NAME_LEN, "te_%u",
  2626. pp->id - PINGPONG_0);
  2627. major_version = SDE_HW_MAJOR(sde_cfg->hwversion);
  2628. if (major_version < SDE_HW_MAJOR(SDE_HW_VER_500))
  2629. set_bit(SDE_PINGPONG_TE, &pp->features);
  2630. sblk->te2.base = PROP_VALUE_ACCESS(prop_value, TE2_OFF, i);
  2631. if (sblk->te2.base) {
  2632. sblk->te2.id = SDE_PINGPONG_TE2;
  2633. snprintf(sblk->te2.name, SDE_HW_BLK_NAME_LEN, "te2_%u",
  2634. pp->id - PINGPONG_0);
  2635. set_bit(SDE_PINGPONG_TE2, &pp->features);
  2636. set_bit(SDE_PINGPONG_SPLIT, &pp->features);
  2637. }
  2638. if (PROP_VALUE_ACCESS(prop_value, PP_SLAVE, i))
  2639. set_bit(SDE_PINGPONG_SLAVE, &pp->features);
  2640. sblk->dsc.base = PROP_VALUE_ACCESS(prop_value, DSC_OFF, i);
  2641. if (sblk->dsc.base) {
  2642. sblk->dsc.id = SDE_PINGPONG_DSC;
  2643. snprintf(sblk->dsc.name, SDE_HW_BLK_NAME_LEN, "dsc_%u",
  2644. pp->id - PINGPONG_0);
  2645. set_bit(SDE_PINGPONG_DSC, &pp->features);
  2646. }
  2647. sblk->dither.base = PROP_VALUE_ACCESS(prop_value, DITHER_OFF,
  2648. i);
  2649. if (sblk->dither.base) {
  2650. sblk->dither.id = SDE_PINGPONG_DITHER;
  2651. snprintf(sblk->dither.name, SDE_HW_BLK_NAME_LEN,
  2652. "dither_%u", pp->id);
  2653. set_bit(SDE_PINGPONG_DITHER, &pp->features);
  2654. }
  2655. sblk->dither.len = PROP_VALUE_ACCESS(prop_value, DITHER_LEN, 0);
  2656. sblk->dither.version = PROP_VALUE_ACCESS(prop_value, DITHER_VER,
  2657. 0);
  2658. if (prop_exists[PP_MERGE_3D_ID]) {
  2659. set_bit(SDE_PINGPONG_MERGE_3D, &pp->features);
  2660. pp->merge_3d_id = PROP_VALUE_ACCESS(prop_value,
  2661. PP_MERGE_3D_ID, i) + 1;
  2662. }
  2663. }
  2664. end:
  2665. kfree(prop_value);
  2666. return rc;
  2667. }
  2668. static int _sde_parse_prop_check(struct sde_mdss_cfg *cfg,
  2669. bool prop_exists[SDE_PROP_MAX], struct sde_prop_value *prop_value)
  2670. {
  2671. cfg->max_sspp_linewidth = PROP_VALUE_ACCESS(prop_value,
  2672. SSPP_LINEWIDTH, 0);
  2673. if (!prop_exists[SSPP_LINEWIDTH])
  2674. cfg->max_sspp_linewidth = DEFAULT_SDE_LINE_WIDTH;
  2675. cfg->max_mixer_width = PROP_VALUE_ACCESS(prop_value,
  2676. MIXER_LINEWIDTH, 0);
  2677. if (!prop_exists[MIXER_LINEWIDTH])
  2678. cfg->max_mixer_width = DEFAULT_SDE_LINE_WIDTH;
  2679. cfg->max_mixer_blendstages = PROP_VALUE_ACCESS(prop_value,
  2680. MIXER_BLEND, 0);
  2681. if (!prop_exists[MIXER_BLEND])
  2682. cfg->max_mixer_blendstages = DEFAULT_SDE_MIXER_BLENDSTAGES;
  2683. cfg->max_wb_linewidth = PROP_VALUE_ACCESS(prop_value, WB_LINEWIDTH, 0);
  2684. if (!prop_exists[WB_LINEWIDTH])
  2685. cfg->max_wb_linewidth = DEFAULT_SDE_LINE_WIDTH;
  2686. cfg->mdp[0].highest_bank_bit = PROP_VALUE_ACCESS(prop_value,
  2687. BANK_BIT, 0);
  2688. if (!prop_exists[BANK_BIT])
  2689. cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT;
  2690. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  2691. cfg->mdp[0].highest_bank_bit = 0x02;
  2692. cfg->ubwc_version = SDE_HW_UBWC_VER(PROP_VALUE_ACCESS(prop_value,
  2693. UBWC_VERSION, 0));
  2694. if (!prop_exists[UBWC_VERSION])
  2695. cfg->ubwc_version = DEFAULT_SDE_UBWC_VERSION;
  2696. cfg->macrotile_mode = PROP_VALUE_ACCESS(prop_value, MACROTILE_MODE, 0);
  2697. if (!prop_exists[MACROTILE_MODE])
  2698. cfg->macrotile_mode = DEFAULT_SDE_UBWC_MACROTILE_MODE;
  2699. cfg->ubwc_bw_calc_version =
  2700. PROP_VALUE_ACCESS(prop_value, UBWC_BW_CALC_VERSION, 0);
  2701. cfg->mdp[0].ubwc_static = PROP_VALUE_ACCESS(prop_value, UBWC_STATIC, 0);
  2702. if (!prop_exists[UBWC_STATIC])
  2703. cfg->mdp[0].ubwc_static = DEFAULT_SDE_UBWC_STATIC;
  2704. cfg->mdp[0].ubwc_swizzle = PROP_VALUE_ACCESS(prop_value,
  2705. UBWC_SWIZZLE, 0);
  2706. if (!prop_exists[UBWC_SWIZZLE])
  2707. cfg->mdp[0].ubwc_swizzle = DEFAULT_SDE_UBWC_SWIZZLE;
  2708. cfg->mdp[0].has_dest_scaler =
  2709. PROP_VALUE_ACCESS(prop_value, DEST_SCALER, 0);
  2710. cfg->mdp[0].smart_panel_align_mode =
  2711. PROP_VALUE_ACCESS(prop_value, SMART_PANEL_ALIGN_MODE, 0);
  2712. return 0;
  2713. }
  2714. static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
  2715. {
  2716. int rc, i, dma_rc, len, prop_count[SDE_PROP_MAX];
  2717. struct sde_prop_value *prop_value = NULL;
  2718. bool prop_exists[SDE_PROP_MAX];
  2719. const char *type;
  2720. u32 major_version;
  2721. if (!cfg) {
  2722. SDE_ERROR("invalid argument\n");
  2723. return -EINVAL;
  2724. }
  2725. prop_value = kzalloc(SDE_PROP_MAX *
  2726. sizeof(struct sde_prop_value), GFP_KERNEL);
  2727. if (!prop_value)
  2728. return -ENOMEM;
  2729. rc = _validate_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,
  2730. &len);
  2731. if (rc)
  2732. goto end;
  2733. rc = _validate_dt_entry(np, &sde_prop[SEC_SID_MASK], 1,
  2734. &prop_count[SEC_SID_MASK], NULL);
  2735. if (rc)
  2736. goto end;
  2737. rc = _read_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,
  2738. prop_exists, prop_value);
  2739. if (rc)
  2740. goto end;
  2741. cfg->mdss_count = 1;
  2742. cfg->mdss[0].base = MDSS_BASE_OFFSET;
  2743. cfg->mdss[0].id = MDP_TOP;
  2744. snprintf(cfg->mdss[0].name, SDE_HW_BLK_NAME_LEN, "mdss_%u",
  2745. cfg->mdss[0].id - MDP_TOP);
  2746. cfg->mdp_count = 1;
  2747. cfg->mdp[0].id = MDP_TOP;
  2748. snprintf(cfg->mdp[0].name, SDE_HW_BLK_NAME_LEN, "top_%u",
  2749. cfg->mdp[0].id - MDP_TOP);
  2750. cfg->mdp[0].base = PROP_VALUE_ACCESS(prop_value, SDE_OFF, 0);
  2751. cfg->mdp[0].len = PROP_VALUE_ACCESS(prop_value, SDE_LEN, 0);
  2752. if (!prop_exists[SDE_LEN])
  2753. cfg->mdp[0].len = DEFAULT_SDE_HW_BLOCK_LEN;
  2754. rc = _sde_parse_prop_check(cfg, prop_exists, prop_value);
  2755. if (rc)
  2756. SDE_ERROR("sde parse property check failed\n");
  2757. major_version = SDE_HW_MAJOR(cfg->hwversion);
  2758. if (major_version < SDE_HW_MAJOR(SDE_HW_VER_500))
  2759. set_bit(SDE_MDP_VSYNC_SEL, &cfg->mdp[0].features);
  2760. if (prop_exists[SEC_SID_MASK]) {
  2761. cfg->sec_sid_mask_count = prop_count[SEC_SID_MASK];
  2762. for (i = 0; i < cfg->sec_sid_mask_count; i++)
  2763. cfg->sec_sid_mask[i] =
  2764. PROP_VALUE_ACCESS(prop_value, SEC_SID_MASK, i);
  2765. }
  2766. rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);
  2767. if (!rc && !strcmp(type, "qseedv3")) {
  2768. cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;
  2769. } else if (!rc && !strcmp(type, "qseedv3lite")) {
  2770. cfg->qseed_type = SDE_SSPP_SCALER_QSEED3LITE;
  2771. } else if (!rc && !strcmp(type, "qseedv2")) {
  2772. cfg->qseed_type = SDE_SSPP_SCALER_QSEED2;
  2773. } else if (rc) {
  2774. SDE_DEBUG("invalid QSEED configuration\n");
  2775. rc = 0;
  2776. }
  2777. rc = of_property_read_string(np, sde_prop[CSC_TYPE].prop_name, &type);
  2778. if (!rc && !strcmp(type, "csc")) {
  2779. cfg->csc_type = SDE_SSPP_CSC;
  2780. } else if (!rc && !strcmp(type, "csc-10bit")) {
  2781. cfg->csc_type = SDE_SSPP_CSC_10BIT;
  2782. } else if (rc) {
  2783. SDE_DEBUG("invalid csc configuration\n");
  2784. rc = 0;
  2785. }
  2786. /*
  2787. * Current SDE support only Smart DMA 2.0-2.5.
  2788. * No support for Smart DMA 1.0 yet.
  2789. */
  2790. cfg->smart_dma_rev = 0;
  2791. dma_rc = of_property_read_string(np, sde_prop[SMART_DMA_REV].prop_name,
  2792. &type);
  2793. if (dma_rc) {
  2794. SDE_DEBUG("invalid SMART_DMA_REV node in device tree: %d\n",
  2795. dma_rc);
  2796. } else if (!strcmp(type, "smart_dma_v2p5")) {
  2797. cfg->smart_dma_rev = SDE_SSPP_SMART_DMA_V2p5;
  2798. } else if (!strcmp(type, "smart_dma_v2")) {
  2799. cfg->smart_dma_rev = SDE_SSPP_SMART_DMA_V2;
  2800. } else if (!strcmp(type, "smart_dma_v1")) {
  2801. SDE_ERROR("smart dma 1.0 is not supported in SDE\n");
  2802. } else {
  2803. SDE_DEBUG("unknown smart dma version\n");
  2804. }
  2805. cfg->has_src_split = PROP_VALUE_ACCESS(prop_value, SRC_SPLIT, 0);
  2806. cfg->has_dim_layer = PROP_VALUE_ACCESS(prop_value, DIM_LAYER, 0);
  2807. cfg->has_idle_pc = PROP_VALUE_ACCESS(prop_value, IDLE_PC, 0);
  2808. cfg->pipe_order_type = PROP_VALUE_ACCESS(prop_value,
  2809. PIPE_ORDER_VERSION, 0);
  2810. end:
  2811. kfree(prop_value);
  2812. return rc;
  2813. }
  2814. static int sde_parse_reg_dma_dt(struct device_node *np,
  2815. struct sde_mdss_cfg *sde_cfg)
  2816. {
  2817. int rc = 0, i, prop_count[REG_DMA_PROP_MAX];
  2818. struct sde_prop_value *prop_value = NULL;
  2819. u32 off_count;
  2820. bool prop_exists[REG_DMA_PROP_MAX];
  2821. prop_value = kcalloc(REG_DMA_PROP_MAX,
  2822. sizeof(struct sde_prop_value), GFP_KERNEL);
  2823. if (!prop_value) {
  2824. rc = -ENOMEM;
  2825. goto end;
  2826. }
  2827. rc = _validate_dt_entry(np, reg_dma_prop, ARRAY_SIZE(reg_dma_prop),
  2828. prop_count, &off_count);
  2829. if (rc || !off_count)
  2830. goto end;
  2831. rc = _read_dt_entry(np, reg_dma_prop, ARRAY_SIZE(reg_dma_prop),
  2832. prop_count, prop_exists, prop_value);
  2833. if (rc)
  2834. goto end;
  2835. sde_cfg->reg_dma_count = off_count;
  2836. sde_cfg->dma_cfg.base = PROP_VALUE_ACCESS(prop_value, REG_DMA_OFF, 0);
  2837. sde_cfg->dma_cfg.version = PROP_VALUE_ACCESS(prop_value,
  2838. REG_DMA_VERSION, 0);
  2839. sde_cfg->dma_cfg.trigger_sel_off = PROP_VALUE_ACCESS(prop_value,
  2840. REG_DMA_TRIGGER_OFF, 0);
  2841. sde_cfg->dma_cfg.broadcast_disabled = PROP_VALUE_ACCESS(prop_value,
  2842. REG_DMA_BROADCAST_DISABLED, 0);
  2843. sde_cfg->dma_cfg.xin_id = PROP_VALUE_ACCESS(prop_value,
  2844. REG_DMA_XIN_ID, 0);
  2845. sde_cfg->dma_cfg.clk_ctrl = SDE_CLK_CTRL_LUTDMA;
  2846. sde_cfg->dma_cfg.vbif_idx = VBIF_RT;
  2847. for (i = 0; i < sde_cfg->mdp_count; i++) {
  2848. sde_cfg->mdp[i].clk_ctrls[sde_cfg->dma_cfg.clk_ctrl].reg_off =
  2849. PROP_BITVALUE_ACCESS(prop_value,
  2850. REG_DMA_CLK_CTRL, 0, 0);
  2851. sde_cfg->mdp[i].clk_ctrls[sde_cfg->dma_cfg.clk_ctrl].bit_off =
  2852. PROP_BITVALUE_ACCESS(prop_value,
  2853. REG_DMA_CLK_CTRL, 0, 1);
  2854. }
  2855. end:
  2856. kfree(prop_value);
  2857. /* reg dma is optional feature hence return 0 */
  2858. return 0;
  2859. }
  2860. static int _sde_perf_parse_dt_validate(struct device_node *np, int *prop_count)
  2861. {
  2862. int rc, len;
  2863. rc = _validate_dt_entry(np, sde_perf_prop, ARRAY_SIZE(sde_perf_prop),
  2864. prop_count, &len);
  2865. if (rc)
  2866. return rc;
  2867. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_DANGER_LUT], 1,
  2868. &prop_count[PERF_DANGER_LUT], NULL);
  2869. if (rc)
  2870. return rc;
  2871. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_SAFE_LUT_LINEAR], 1,
  2872. &prop_count[PERF_SAFE_LUT_LINEAR], NULL);
  2873. if (rc)
  2874. return rc;
  2875. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_SAFE_LUT_MACROTILE], 1,
  2876. &prop_count[PERF_SAFE_LUT_MACROTILE], NULL);
  2877. if (rc)
  2878. return rc;
  2879. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_SAFE_LUT_NRT], 1,
  2880. &prop_count[PERF_SAFE_LUT_NRT], NULL);
  2881. if (rc)
  2882. return rc;
  2883. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_SAFE_LUT_CWB], 1,
  2884. &prop_count[PERF_SAFE_LUT_CWB], NULL);
  2885. if (rc)
  2886. return rc;
  2887. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_QOS_LUT_LINEAR], 1,
  2888. &prop_count[PERF_QOS_LUT_LINEAR], NULL);
  2889. if (rc)
  2890. return rc;
  2891. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_QOS_LUT_MACROTILE], 1,
  2892. &prop_count[PERF_QOS_LUT_MACROTILE], NULL);
  2893. if (rc)
  2894. return rc;
  2895. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_QOS_LUT_NRT], 1,
  2896. &prop_count[PERF_QOS_LUT_NRT], NULL);
  2897. if (rc)
  2898. return rc;
  2899. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_QOS_LUT_CWB], 1,
  2900. &prop_count[PERF_QOS_LUT_CWB], NULL);
  2901. if (rc)
  2902. return rc;
  2903. rc = _validate_dt_entry(np, &sde_perf_prop[PERF_CDP_SETTING], 1,
  2904. &prop_count[PERF_CDP_SETTING], NULL);
  2905. if (rc)
  2906. return rc;
  2907. rc = _validate_dt_entry(np,
  2908. &sde_perf_prop[PERF_QOS_LUT_MACROTILE_QSEED], 1,
  2909. &prop_count[PERF_QOS_LUT_MACROTILE_QSEED], NULL);
  2910. if (rc)
  2911. return rc;
  2912. rc = _validate_dt_entry(np,
  2913. &sde_perf_prop[PERF_SAFE_LUT_MACROTILE_QSEED], 1,
  2914. &prop_count[PERF_SAFE_LUT_MACROTILE_QSEED], NULL);
  2915. return rc;
  2916. }
  2917. static int _sde_perf_parse_dt_cfg_qos(struct sde_mdss_cfg *cfg, int *prop_count,
  2918. struct sde_prop_value *prop_value, bool *prop_exists)
  2919. {
  2920. int j, k;
  2921. if (prop_exists[PERF_DANGER_LUT] && prop_count[PERF_DANGER_LUT] <=
  2922. SDE_QOS_LUT_USAGE_MAX) {
  2923. for (j = 0; j < prop_count[PERF_DANGER_LUT]; j++) {
  2924. cfg->perf.danger_lut_tbl[j] =
  2925. PROP_VALUE_ACCESS(prop_value,
  2926. PERF_DANGER_LUT, j);
  2927. SDE_DEBUG("danger usage:%d lut:0x%x\n",
  2928. j, cfg->perf.danger_lut_tbl[j]);
  2929. }
  2930. }
  2931. for (j = 0; j < SDE_QOS_LUT_USAGE_MAX; j++) {
  2932. static const u32 safe_key[SDE_QOS_LUT_USAGE_MAX] = {
  2933. [SDE_QOS_LUT_USAGE_LINEAR] =
  2934. PERF_SAFE_LUT_LINEAR,
  2935. [SDE_QOS_LUT_USAGE_MACROTILE] =
  2936. PERF_SAFE_LUT_MACROTILE,
  2937. [SDE_QOS_LUT_USAGE_NRT] =
  2938. PERF_SAFE_LUT_NRT,
  2939. [SDE_QOS_LUT_USAGE_CWB] =
  2940. PERF_SAFE_LUT_CWB,
  2941. [SDE_QOS_LUT_USAGE_MACROTILE_QSEED] =
  2942. PERF_SAFE_LUT_MACROTILE_QSEED,
  2943. };
  2944. const u32 entry_size = 2;
  2945. int m, count;
  2946. int key = safe_key[j];
  2947. if (!prop_exists[key])
  2948. continue;
  2949. count = prop_count[key] / entry_size;
  2950. cfg->perf.sfe_lut_tbl[j].entries = kcalloc(count,
  2951. sizeof(struct sde_qos_lut_entry), GFP_KERNEL);
  2952. if (!cfg->perf.sfe_lut_tbl[j].entries)
  2953. return -ENOMEM;
  2954. for (k = 0, m = 0; k < count; k++, m += entry_size) {
  2955. u64 lut_lo;
  2956. cfg->perf.sfe_lut_tbl[j].entries[k].fl =
  2957. PROP_VALUE_ACCESS(prop_value, key, m);
  2958. lut_lo = PROP_VALUE_ACCESS(prop_value, key, m + 1);
  2959. cfg->perf.sfe_lut_tbl[j].entries[k].lut = lut_lo;
  2960. SDE_DEBUG("safe usage:%d.%d fl:%d lut:0x%llx\n",
  2961. j, k,
  2962. cfg->perf.sfe_lut_tbl[j].entries[k].fl,
  2963. cfg->perf.sfe_lut_tbl[j].entries[k].lut);
  2964. }
  2965. cfg->perf.sfe_lut_tbl[j].nentry = count;
  2966. }
  2967. for (j = 0; j < SDE_QOS_LUT_USAGE_MAX; j++) {
  2968. static const u32 prop_key[SDE_QOS_LUT_USAGE_MAX] = {
  2969. [SDE_QOS_LUT_USAGE_LINEAR] =
  2970. PERF_QOS_LUT_LINEAR,
  2971. [SDE_QOS_LUT_USAGE_MACROTILE] =
  2972. PERF_QOS_LUT_MACROTILE,
  2973. [SDE_QOS_LUT_USAGE_NRT] =
  2974. PERF_QOS_LUT_NRT,
  2975. [SDE_QOS_LUT_USAGE_CWB] =
  2976. PERF_QOS_LUT_CWB,
  2977. [SDE_QOS_LUT_USAGE_MACROTILE_QSEED] =
  2978. PERF_QOS_LUT_MACROTILE_QSEED,
  2979. };
  2980. const u32 entry_size = 3;
  2981. int m, count;
  2982. int key = prop_key[j];
  2983. if (!prop_exists[key])
  2984. continue;
  2985. count = prop_count[key] / entry_size;
  2986. cfg->perf.qos_lut_tbl[j].entries = kcalloc(count,
  2987. sizeof(struct sde_qos_lut_entry), GFP_KERNEL);
  2988. if (!cfg->perf.qos_lut_tbl[j].entries)
  2989. return -ENOMEM;
  2990. for (k = 0, m = 0; k < count; k++, m += entry_size) {
  2991. u64 lut_hi, lut_lo;
  2992. cfg->perf.qos_lut_tbl[j].entries[k].fl =
  2993. PROP_VALUE_ACCESS(prop_value, key, m);
  2994. lut_hi = PROP_VALUE_ACCESS(prop_value, key, m + 1);
  2995. lut_lo = PROP_VALUE_ACCESS(prop_value, key, m + 2);
  2996. cfg->perf.qos_lut_tbl[j].entries[k].lut =
  2997. (lut_hi << 32) | lut_lo;
  2998. SDE_DEBUG("usage:%d.%d fl:%d lut:0x%llx\n",
  2999. j, k,
  3000. cfg->perf.qos_lut_tbl[j].entries[k].fl,
  3001. cfg->perf.qos_lut_tbl[j].entries[k].lut);
  3002. }
  3003. cfg->perf.qos_lut_tbl[j].nentry = count;
  3004. }
  3005. return 0;
  3006. }
  3007. static void _sde_perf_parse_dt_cfg_populate(struct sde_mdss_cfg *cfg,
  3008. int *prop_count,
  3009. struct sde_prop_value *prop_value,
  3010. bool *prop_exists)
  3011. {
  3012. cfg->perf.max_bw_low =
  3013. prop_exists[PERF_MAX_BW_LOW] ?
  3014. PROP_VALUE_ACCESS(prop_value, PERF_MAX_BW_LOW, 0) :
  3015. DEFAULT_MAX_BW_LOW;
  3016. cfg->perf.max_bw_high =
  3017. prop_exists[PERF_MAX_BW_HIGH] ?
  3018. PROP_VALUE_ACCESS(prop_value, PERF_MAX_BW_HIGH, 0) :
  3019. DEFAULT_MAX_BW_HIGH;
  3020. cfg->perf.min_core_ib =
  3021. prop_exists[PERF_MIN_CORE_IB] ?
  3022. PROP_VALUE_ACCESS(prop_value, PERF_MIN_CORE_IB, 0) :
  3023. DEFAULT_MAX_BW_LOW;
  3024. cfg->perf.min_llcc_ib =
  3025. prop_exists[PERF_MIN_LLCC_IB] ?
  3026. PROP_VALUE_ACCESS(prop_value, PERF_MIN_LLCC_IB, 0) :
  3027. DEFAULT_MAX_BW_LOW;
  3028. cfg->perf.min_dram_ib =
  3029. prop_exists[PERF_MIN_DRAM_IB] ?
  3030. PROP_VALUE_ACCESS(prop_value, PERF_MIN_DRAM_IB, 0) :
  3031. DEFAULT_MAX_BW_LOW;
  3032. cfg->perf.undersized_prefill_lines =
  3033. prop_exists[PERF_UNDERSIZED_PREFILL_LINES] ?
  3034. PROP_VALUE_ACCESS(prop_value,
  3035. PERF_UNDERSIZED_PREFILL_LINES, 0) :
  3036. DEFAULT_UNDERSIZED_PREFILL_LINES;
  3037. cfg->perf.xtra_prefill_lines =
  3038. prop_exists[PERF_XTRA_PREFILL_LINES] ?
  3039. PROP_VALUE_ACCESS(prop_value,
  3040. PERF_XTRA_PREFILL_LINES, 0) :
  3041. DEFAULT_XTRA_PREFILL_LINES;
  3042. cfg->perf.dest_scale_prefill_lines =
  3043. prop_exists[PERF_DEST_SCALE_PREFILL_LINES] ?
  3044. PROP_VALUE_ACCESS(prop_value,
  3045. PERF_DEST_SCALE_PREFILL_LINES, 0) :
  3046. DEFAULT_DEST_SCALE_PREFILL_LINES;
  3047. cfg->perf.macrotile_prefill_lines =
  3048. prop_exists[PERF_MACROTILE_PREFILL_LINES] ?
  3049. PROP_VALUE_ACCESS(prop_value,
  3050. PERF_MACROTILE_PREFILL_LINES, 0) :
  3051. DEFAULT_MACROTILE_PREFILL_LINES;
  3052. cfg->perf.yuv_nv12_prefill_lines =
  3053. prop_exists[PERF_YUV_NV12_PREFILL_LINES] ?
  3054. PROP_VALUE_ACCESS(prop_value,
  3055. PERF_YUV_NV12_PREFILL_LINES, 0) :
  3056. DEFAULT_YUV_NV12_PREFILL_LINES;
  3057. cfg->perf.linear_prefill_lines =
  3058. prop_exists[PERF_LINEAR_PREFILL_LINES] ?
  3059. PROP_VALUE_ACCESS(prop_value,
  3060. PERF_LINEAR_PREFILL_LINES, 0) :
  3061. DEFAULT_LINEAR_PREFILL_LINES;
  3062. cfg->perf.downscaling_prefill_lines =
  3063. prop_exists[PERF_DOWNSCALING_PREFILL_LINES] ?
  3064. PROP_VALUE_ACCESS(prop_value,
  3065. PERF_DOWNSCALING_PREFILL_LINES, 0) :
  3066. DEFAULT_DOWNSCALING_PREFILL_LINES;
  3067. cfg->perf.amortizable_threshold =
  3068. prop_exists[PERF_AMORTIZABLE_THRESHOLD] ?
  3069. PROP_VALUE_ACCESS(prop_value,
  3070. PERF_AMORTIZABLE_THRESHOLD, 0) :
  3071. DEFAULT_AMORTIZABLE_THRESHOLD;
  3072. cfg->perf.num_mnoc_ports =
  3073. prop_exists[PERF_NUM_MNOC_PORTS] ?
  3074. PROP_VALUE_ACCESS(prop_value,
  3075. PERF_NUM_MNOC_PORTS, 0) :
  3076. DEFAULT_MNOC_PORTS;
  3077. cfg->perf.axi_bus_width =
  3078. prop_exists[PERF_AXI_BUS_WIDTH] ?
  3079. PROP_VALUE_ACCESS(prop_value,
  3080. PERF_AXI_BUS_WIDTH, 0) :
  3081. DEFAULT_AXI_BUS_WIDTH;
  3082. }
  3083. static int _sde_perf_parse_dt_cfg(struct device_node *np,
  3084. struct sde_mdss_cfg *cfg, int *prop_count,
  3085. struct sde_prop_value *prop_value, bool *prop_exists)
  3086. {
  3087. int rc, j;
  3088. const char *str = NULL;
  3089. /*
  3090. * The following performance parameters (e.g. core_ib_ff) are
  3091. * mapped directly as device tree string constants.
  3092. */
  3093. rc = of_property_read_string(np,
  3094. sde_perf_prop[PERF_CORE_IB_FF].prop_name, &str);
  3095. cfg->perf.core_ib_ff = rc ? DEFAULT_CORE_IB_FF : str;
  3096. rc = of_property_read_string(np,
  3097. sde_perf_prop[PERF_CORE_CLK_FF].prop_name, &str);
  3098. cfg->perf.core_clk_ff = rc ? DEFAULT_CORE_CLK_FF : str;
  3099. rc = of_property_read_string(np,
  3100. sde_perf_prop[PERF_COMP_RATIO_RT].prop_name, &str);
  3101. cfg->perf.comp_ratio_rt = rc ? DEFAULT_COMP_RATIO_RT : str;
  3102. rc = of_property_read_string(np,
  3103. sde_perf_prop[PERF_COMP_RATIO_NRT].prop_name, &str);
  3104. cfg->perf.comp_ratio_nrt = rc ? DEFAULT_COMP_RATIO_NRT : str;
  3105. rc = 0;
  3106. _sde_perf_parse_dt_cfg_populate(cfg, prop_count, prop_value,
  3107. prop_exists);
  3108. rc = _sde_perf_parse_dt_cfg_qos(cfg, prop_count, prop_value,
  3109. prop_exists);
  3110. if (rc)
  3111. return rc;
  3112. if (prop_exists[PERF_CDP_SETTING]) {
  3113. const u32 prop_size = 2;
  3114. u32 count = prop_count[PERF_CDP_SETTING] / prop_size;
  3115. count = min_t(u32, count, SDE_PERF_CDP_USAGE_MAX);
  3116. for (j = 0; j < count; j++) {
  3117. cfg->perf.cdp_cfg[j].rd_enable =
  3118. PROP_VALUE_ACCESS(prop_value,
  3119. PERF_CDP_SETTING, j * prop_size);
  3120. cfg->perf.cdp_cfg[j].wr_enable =
  3121. PROP_VALUE_ACCESS(prop_value,
  3122. PERF_CDP_SETTING, j * prop_size + 1);
  3123. SDE_DEBUG("cdp usage:%d rd:%d wr:%d\n",
  3124. j, cfg->perf.cdp_cfg[j].rd_enable,
  3125. cfg->perf.cdp_cfg[j].wr_enable);
  3126. }
  3127. cfg->has_cdp = true;
  3128. }
  3129. cfg->perf.cpu_mask =
  3130. prop_exists[PERF_CPU_MASK] ?
  3131. PROP_VALUE_ACCESS(prop_value, PERF_CPU_MASK, 0) :
  3132. DEFAULT_CPU_MASK;
  3133. cfg->perf.cpu_dma_latency =
  3134. prop_exists[PERF_CPU_DMA_LATENCY] ?
  3135. PROP_VALUE_ACCESS(prop_value, PERF_CPU_DMA_LATENCY, 0) :
  3136. DEFAULT_CPU_DMA_LATENCY;
  3137. return 0;
  3138. }
  3139. static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
  3140. {
  3141. int rc, prop_count[PERF_PROP_MAX];
  3142. struct sde_prop_value *prop_value = NULL;
  3143. bool prop_exists[PERF_PROP_MAX];
  3144. if (!cfg) {
  3145. SDE_ERROR("invalid argument\n");
  3146. rc = -EINVAL;
  3147. goto end;
  3148. }
  3149. prop_value = kzalloc(PERF_PROP_MAX *
  3150. sizeof(struct sde_prop_value), GFP_KERNEL);
  3151. if (!prop_value) {
  3152. rc = -ENOMEM;
  3153. goto end;
  3154. }
  3155. rc = _sde_perf_parse_dt_validate(np, prop_count);
  3156. if (rc)
  3157. goto freeprop;
  3158. rc = _read_dt_entry(np, sde_perf_prop, ARRAY_SIZE(sde_perf_prop),
  3159. prop_count, prop_exists, prop_value);
  3160. if (rc)
  3161. goto freeprop;
  3162. rc = _sde_perf_parse_dt_cfg(np, cfg, prop_count, prop_value,
  3163. prop_exists);
  3164. freeprop:
  3165. kfree(prop_value);
  3166. end:
  3167. return rc;
  3168. }
  3169. static int sde_parse_merge_3d_dt(struct device_node *np,
  3170. struct sde_mdss_cfg *sde_cfg)
  3171. {
  3172. int rc, prop_count[HW_PROP_MAX], off_count, i;
  3173. struct sde_prop_value *prop_value = NULL;
  3174. bool prop_exists[HW_PROP_MAX];
  3175. struct sde_merge_3d_cfg *merge_3d;
  3176. prop_value = kcalloc(HW_PROP_MAX, sizeof(struct sde_prop_value),
  3177. GFP_KERNEL);
  3178. if (!prop_value)
  3179. return -ENOMEM;
  3180. rc = _validate_dt_entry(np, merge_3d_prop, ARRAY_SIZE(merge_3d_prop),
  3181. prop_count, &off_count);
  3182. if (rc)
  3183. goto end;
  3184. sde_cfg->merge_3d_count = off_count;
  3185. rc = _read_dt_entry(np, merge_3d_prop, ARRAY_SIZE(merge_3d_prop),
  3186. prop_count,
  3187. prop_exists, prop_value);
  3188. if (rc) {
  3189. sde_cfg->merge_3d_count = 0;
  3190. goto end;
  3191. }
  3192. for (i = 0; i < off_count; i++) {
  3193. merge_3d = sde_cfg->merge_3d + i;
  3194. merge_3d->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
  3195. merge_3d->id = MERGE_3D_0 + i;
  3196. snprintf(merge_3d->name, SDE_HW_BLK_NAME_LEN, "merge_3d_%u",
  3197. merge_3d->id - MERGE_3D_0);
  3198. merge_3d->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);
  3199. }
  3200. end:
  3201. kfree(prop_value);
  3202. return rc;
  3203. }
  3204. static int sde_qdss_parse_dt(struct device_node *np,
  3205. struct sde_mdss_cfg *sde_cfg)
  3206. {
  3207. int rc, prop_count[HW_PROP_MAX], i;
  3208. struct sde_prop_value *prop_value = NULL;
  3209. bool prop_exists[HW_PROP_MAX];
  3210. u32 off_count;
  3211. struct sde_qdss_cfg *qdss;
  3212. if (!sde_cfg) {
  3213. SDE_ERROR("invalid argument\n");
  3214. return -EINVAL;
  3215. }
  3216. prop_value = kzalloc(HW_PROP_MAX *
  3217. sizeof(struct sde_prop_value), GFP_KERNEL);
  3218. if (!prop_value)
  3219. return -ENOMEM;
  3220. rc = _validate_dt_entry(np, qdss_prop, ARRAY_SIZE(qdss_prop),
  3221. prop_count, &off_count);
  3222. if (rc) {
  3223. sde_cfg->qdss_count = 0;
  3224. goto end;
  3225. }
  3226. sde_cfg->qdss_count = off_count;
  3227. rc = _read_dt_entry(np, qdss_prop, ARRAY_SIZE(qdss_prop), prop_count,
  3228. prop_exists, prop_value);
  3229. if (rc)
  3230. goto end;
  3231. for (i = 0; i < off_count; i++) {
  3232. qdss = sde_cfg->qdss + i;
  3233. qdss->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
  3234. qdss->id = QDSS_0 + i;
  3235. snprintf(qdss->name, SDE_HW_BLK_NAME_LEN, "qdss_%u",
  3236. qdss->id - QDSS_0);
  3237. qdss->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);
  3238. }
  3239. end:
  3240. kfree(prop_value);
  3241. return rc;
  3242. }
  3243. static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
  3244. uint32_t hw_rev)
  3245. {
  3246. int rc = 0;
  3247. uint32_t dma_list_size, vig_list_size, wb2_list_size;
  3248. uint32_t virt_vig_list_size, in_rot_list_size = 0;
  3249. uint32_t cursor_list_size = 0;
  3250. uint32_t index = 0;
  3251. if (sde_cfg->has_cursor) {
  3252. cursor_list_size = ARRAY_SIZE(cursor_formats);
  3253. sde_cfg->cursor_formats = kcalloc(cursor_list_size,
  3254. sizeof(struct sde_format_extended), GFP_KERNEL);
  3255. if (!sde_cfg->cursor_formats) {
  3256. rc = -ENOMEM;
  3257. goto end;
  3258. }
  3259. index = sde_copy_formats(sde_cfg->cursor_formats,
  3260. cursor_list_size, 0, cursor_formats,
  3261. ARRAY_SIZE(cursor_formats));
  3262. }
  3263. dma_list_size = ARRAY_SIZE(plane_formats);
  3264. vig_list_size = ARRAY_SIZE(plane_formats_vig);
  3265. if (sde_cfg->has_vig_p010)
  3266. vig_list_size += ARRAY_SIZE(p010_ubwc_formats);
  3267. virt_vig_list_size = ARRAY_SIZE(plane_formats);
  3268. wb2_list_size = ARRAY_SIZE(wb2_formats);
  3269. if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev))
  3270. in_rot_list_size = ARRAY_SIZE(true_inline_rot_v1_fmts);
  3271. sde_cfg->dma_formats = kcalloc(dma_list_size,
  3272. sizeof(struct sde_format_extended), GFP_KERNEL);
  3273. if (!sde_cfg->dma_formats) {
  3274. rc = -ENOMEM;
  3275. goto end;
  3276. }
  3277. sde_cfg->vig_formats = kcalloc(vig_list_size,
  3278. sizeof(struct sde_format_extended), GFP_KERNEL);
  3279. if (!sde_cfg->vig_formats) {
  3280. rc = -ENOMEM;
  3281. goto end;
  3282. }
  3283. sde_cfg->virt_vig_formats = kcalloc(virt_vig_list_size,
  3284. sizeof(struct sde_format_extended), GFP_KERNEL);
  3285. if (!sde_cfg->virt_vig_formats) {
  3286. rc = -ENOMEM;
  3287. goto end;
  3288. }
  3289. sde_cfg->wb_formats = kcalloc(wb2_list_size,
  3290. sizeof(struct sde_format_extended), GFP_KERNEL);
  3291. if (!sde_cfg->wb_formats) {
  3292. SDE_ERROR("failed to allocate wb format list\n");
  3293. rc = -ENOMEM;
  3294. goto end;
  3295. }
  3296. if (in_rot_list_size) {
  3297. sde_cfg->inline_rot_formats = kcalloc(in_rot_list_size,
  3298. sizeof(struct sde_format_extended), GFP_KERNEL);
  3299. if (!sde_cfg->inline_rot_formats) {
  3300. SDE_ERROR("failed to alloc inline rot format list\n");
  3301. rc = -ENOMEM;
  3302. goto end;
  3303. }
  3304. }
  3305. index = sde_copy_formats(sde_cfg->dma_formats, dma_list_size,
  3306. 0, plane_formats, ARRAY_SIZE(plane_formats));
  3307. index = sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
  3308. 0, plane_formats_vig, ARRAY_SIZE(plane_formats_vig));
  3309. if (sde_cfg->has_vig_p010)
  3310. index += sde_copy_formats(sde_cfg->vig_formats,
  3311. vig_list_size, index, p010_ubwc_formats,
  3312. ARRAY_SIZE(p010_ubwc_formats));
  3313. index = sde_copy_formats(sde_cfg->virt_vig_formats, virt_vig_list_size,
  3314. 0, plane_formats, ARRAY_SIZE(plane_formats));
  3315. index = sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,
  3316. 0, wb2_formats, ARRAY_SIZE(wb2_formats));
  3317. if (in_rot_list_size)
  3318. index = sde_copy_formats(sde_cfg->inline_rot_formats,
  3319. in_rot_list_size, 0, true_inline_rot_v1_fmts,
  3320. ARRAY_SIZE(true_inline_rot_v1_fmts));
  3321. end:
  3322. return rc;
  3323. }
  3324. static void _sde_hw_setup_uidle(struct sde_uidle_cfg *uidle_cfg)
  3325. {
  3326. if (!uidle_cfg->uidle_rev)
  3327. return;
  3328. if (IS_SDE_UIDLE_REV_100(uidle_cfg->uidle_rev)) {
  3329. uidle_cfg->fal10_exit_cnt = SDE_UIDLE_FAL10_EXIT_CNT;
  3330. uidle_cfg->fal10_exit_danger = SDE_UIDLE_FAL10_EXIT_DANGER;
  3331. uidle_cfg->fal10_danger = SDE_UIDLE_FAL10_DANGER;
  3332. uidle_cfg->fal10_target_idle_time = SDE_UIDLE_FAL10_TARGET_IDLE;
  3333. uidle_cfg->fal1_target_idle_time = SDE_UIDLE_FAL1_TARGET_IDLE;
  3334. uidle_cfg->fal10_threshold = SDE_UIDLE_FAL10_THRESHOLD;
  3335. uidle_cfg->max_dwnscale = SDE_UIDLE_MAX_DWNSCALE;
  3336. uidle_cfg->max_fps = SDE_UIDLE_MAX_FPS;
  3337. uidle_cfg->debugfs_ctrl = true;
  3338. } else {
  3339. pr_err("invalid uidle rev:0x%x, disabling uidle\n",
  3340. uidle_cfg->uidle_rev);
  3341. uidle_cfg->uidle_rev = 0;
  3342. }
  3343. }
  3344. static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
  3345. {
  3346. int i, rc = 0;
  3347. if (!sde_cfg)
  3348. return -EINVAL;
  3349. for (i = 0; i < MDSS_INTR_MAX; i++)
  3350. set_bit(i, sde_cfg->mdss_irqs);
  3351. if (IS_MSM8996_TARGET(hw_rev)) {
  3352. sde_cfg->perf.min_prefill_lines = 21;
  3353. clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
  3354. clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
  3355. sde_cfg->has_decimation = true;
  3356. } else if (IS_MSM8998_TARGET(hw_rev)) {
  3357. sde_cfg->has_wb_ubwc = true;
  3358. sde_cfg->perf.min_prefill_lines = 25;
  3359. sde_cfg->vbif_qos_nlvl = 4;
  3360. sde_cfg->ts_prefill_rev = 1;
  3361. clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
  3362. clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
  3363. sde_cfg->has_decimation = true;
  3364. sde_cfg->has_cursor = true;
  3365. sde_cfg->has_hdr = true;
  3366. } else if (IS_SDM845_TARGET(hw_rev)) {
  3367. sde_cfg->has_wb_ubwc = true;
  3368. sde_cfg->has_cwb_support = true;
  3369. sde_cfg->perf.min_prefill_lines = 24;
  3370. sde_cfg->vbif_qos_nlvl = 8;
  3371. sde_cfg->ts_prefill_rev = 2;
  3372. sde_cfg->sui_misr_supported = true;
  3373. sde_cfg->sui_block_xin_mask = 0x3F71;
  3374. clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
  3375. clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
  3376. sde_cfg->has_decimation = true;
  3377. sde_cfg->has_hdr = true;
  3378. sde_cfg->has_vig_p010 = true;
  3379. } else if (IS_SDM670_TARGET(hw_rev)) {
  3380. sde_cfg->has_wb_ubwc = true;
  3381. sde_cfg->perf.min_prefill_lines = 24;
  3382. sde_cfg->vbif_qos_nlvl = 8;
  3383. sde_cfg->ts_prefill_rev = 2;
  3384. clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
  3385. clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
  3386. sde_cfg->has_decimation = true;
  3387. sde_cfg->has_hdr = true;
  3388. sde_cfg->has_vig_p010 = true;
  3389. } else if (IS_SM8150_TARGET(hw_rev)) {
  3390. sde_cfg->has_cwb_support = true;
  3391. sde_cfg->has_wb_ubwc = true;
  3392. sde_cfg->has_qsync = true;
  3393. sde_cfg->has_hdr = true;
  3394. sde_cfg->has_hdr_plus = true;
  3395. set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
  3396. sde_cfg->has_vig_p010 = true;
  3397. sde_cfg->perf.min_prefill_lines = 24;
  3398. sde_cfg->vbif_qos_nlvl = 8;
  3399. sde_cfg->ts_prefill_rev = 2;
  3400. sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
  3401. sde_cfg->delay_prg_fetch_start = true;
  3402. sde_cfg->sui_ns_allowed = true;
  3403. sde_cfg->sui_misr_supported = true;
  3404. sde_cfg->sui_block_xin_mask = 0x3F71;
  3405. sde_cfg->has_sui_blendstage = true;
  3406. sde_cfg->has_qos_fl_nocalc = true;
  3407. sde_cfg->has_3d_merge_reset = true;
  3408. clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
  3409. clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
  3410. sde_cfg->has_decimation = true;
  3411. } else if (IS_SDMSHRIKE_TARGET(hw_rev)) {
  3412. sde_cfg->has_wb_ubwc = true;
  3413. sde_cfg->perf.min_prefill_lines = 24;
  3414. sde_cfg->vbif_qos_nlvl = 8;
  3415. sde_cfg->ts_prefill_rev = 2;
  3416. sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
  3417. sde_cfg->delay_prg_fetch_start = true;
  3418. clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
  3419. clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
  3420. sde_cfg->has_decimation = true;
  3421. sde_cfg->has_hdr = true;
  3422. sde_cfg->has_vig_p010 = true;
  3423. } else if (IS_SM6150_TARGET(hw_rev)) {
  3424. sde_cfg->has_cwb_support = true;
  3425. sde_cfg->has_qsync = true;
  3426. sde_cfg->perf.min_prefill_lines = 24;
  3427. sde_cfg->vbif_qos_nlvl = 8;
  3428. sde_cfg->ts_prefill_rev = 2;
  3429. sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
  3430. sde_cfg->delay_prg_fetch_start = true;
  3431. sde_cfg->sui_ns_allowed = true;
  3432. sde_cfg->sui_misr_supported = true;
  3433. sde_cfg->has_decimation = true;
  3434. sde_cfg->sui_block_xin_mask = 0x2EE1;
  3435. sde_cfg->has_sui_blendstage = true;
  3436. sde_cfg->has_qos_fl_nocalc = true;
  3437. sde_cfg->has_3d_merge_reset = true;
  3438. clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
  3439. clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
  3440. sde_cfg->has_hdr = true;
  3441. sde_cfg->has_vig_p010 = true;
  3442. } else if (IS_SDMMAGPIE_TARGET(hw_rev)) {
  3443. sde_cfg->has_cwb_support = true;
  3444. sde_cfg->has_wb_ubwc = true;
  3445. sde_cfg->has_qsync = true;
  3446. sde_cfg->perf.min_prefill_lines = 24;
  3447. sde_cfg->vbif_qos_nlvl = 8;
  3448. sde_cfg->ts_prefill_rev = 2;
  3449. sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
  3450. sde_cfg->delay_prg_fetch_start = true;
  3451. sde_cfg->sui_ns_allowed = true;
  3452. sde_cfg->sui_misr_supported = true;
  3453. sde_cfg->sui_block_xin_mask = 0xE71;
  3454. sde_cfg->has_sui_blendstage = true;
  3455. sde_cfg->has_qos_fl_nocalc = true;
  3456. sde_cfg->has_3d_merge_reset = true;
  3457. } else if (IS_KONA_TARGET(hw_rev)) {
  3458. sde_cfg->has_cwb_support = true;
  3459. sde_cfg->has_wb_ubwc = true;
  3460. sde_cfg->has_qsync = true;
  3461. sde_cfg->perf.min_prefill_lines = 35;
  3462. sde_cfg->vbif_qos_nlvl = 8;
  3463. sde_cfg->ts_prefill_rev = 2;
  3464. sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
  3465. sde_cfg->delay_prg_fetch_start = true;
  3466. sde_cfg->sui_ns_allowed = true;
  3467. sde_cfg->sui_misr_supported = true;
  3468. sde_cfg->sui_block_xin_mask = 0x3F71;
  3469. sde_cfg->has_sui_blendstage = true;
  3470. sde_cfg->has_qos_fl_nocalc = true;
  3471. sde_cfg->has_3d_merge_reset = true;
  3472. clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);
  3473. clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);
  3474. sde_cfg->has_hdr = true;
  3475. sde_cfg->has_hdr_plus = true;
  3476. set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
  3477. sde_cfg->has_vig_p010 = true;
  3478. sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;
  3479. sde_cfg->true_inline_dwnscale_rt_num =
  3480. MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;
  3481. sde_cfg->true_inline_dwnscale_rt_denom =
  3482. MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;
  3483. sde_cfg->true_inline_dwnscale_nrt =
  3484. MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;
  3485. sde_cfg->true_inline_prefill_fudge_lines = 2;
  3486. sde_cfg->true_inline_prefill_lines_nv12 = 32;
  3487. sde_cfg->true_inline_prefill_lines = 48;
  3488. sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_0;
  3489. } else if (IS_SAIPAN_TARGET(hw_rev)) {
  3490. sde_cfg->has_cwb_support = true;
  3491. sde_cfg->has_wb_ubwc = true;
  3492. sde_cfg->has_qsync = true;
  3493. sde_cfg->perf.min_prefill_lines = 24;
  3494. sde_cfg->vbif_qos_nlvl = 8;
  3495. sde_cfg->ts_prefill_rev = 2;
  3496. sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
  3497. sde_cfg->delay_prg_fetch_start = true;
  3498. sde_cfg->sui_ns_allowed = true;
  3499. sde_cfg->sui_misr_supported = true;
  3500. sde_cfg->sui_block_xin_mask = 0xE71;
  3501. sde_cfg->has_sui_blendstage = true;
  3502. sde_cfg->has_qos_fl_nocalc = true;
  3503. sde_cfg->has_3d_merge_reset = true;
  3504. clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);
  3505. clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);
  3506. sde_cfg->has_hdr = true;
  3507. sde_cfg->has_hdr_plus = true;
  3508. set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
  3509. sde_cfg->has_vig_p010 = true;
  3510. sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;
  3511. sde_cfg->true_inline_dwnscale_rt_num =
  3512. MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;
  3513. sde_cfg->true_inline_dwnscale_rt_denom =
  3514. MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;
  3515. sde_cfg->true_inline_dwnscale_nrt =
  3516. MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;
  3517. sde_cfg->true_inline_prefill_fudge_lines = 2;
  3518. sde_cfg->true_inline_prefill_lines_nv12 = 32;
  3519. sde_cfg->true_inline_prefill_lines = 48;
  3520. } else if (IS_SDMTRINKET_TARGET(hw_rev)) {
  3521. sde_cfg->has_cwb_support = true;
  3522. sde_cfg->has_qsync = true;
  3523. sde_cfg->perf.min_prefill_lines = 24;
  3524. sde_cfg->vbif_qos_nlvl = 8;
  3525. sde_cfg->ts_prefill_rev = 2;
  3526. sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
  3527. sde_cfg->delay_prg_fetch_start = true;
  3528. sde_cfg->sui_ns_allowed = true;
  3529. sde_cfg->sui_misr_supported = true;
  3530. sde_cfg->sui_block_xin_mask = 0xC61;
  3531. sde_cfg->has_hdr = false;
  3532. sde_cfg->has_sui_blendstage = true;
  3533. } else {
  3534. SDE_ERROR("unsupported chipset id:%X\n", hw_rev);
  3535. sde_cfg->perf.min_prefill_lines = 0xffff;
  3536. rc = -ENODEV;
  3537. }
  3538. if (!rc)
  3539. rc = sde_hardware_format_caps(sde_cfg, hw_rev);
  3540. _sde_hw_setup_uidle(&sde_cfg->uidle_cfg);
  3541. return rc;
  3542. }
  3543. static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg,
  3544. uint32_t hw_rev)
  3545. {
  3546. int rc = 0, i;
  3547. u32 max_horz_deci = 0, max_vert_deci = 0;
  3548. if (!sde_cfg)
  3549. return -EINVAL;
  3550. if (sde_cfg->has_sui_blendstage)
  3551. sde_cfg->sui_supported_blendstage =
  3552. sde_cfg->max_mixer_blendstages - SDE_STAGE_0;
  3553. for (i = 0; i < sde_cfg->sspp_count; i++) {
  3554. if (sde_cfg->sspp[i].sblk) {
  3555. max_horz_deci = max(max_horz_deci,
  3556. sde_cfg->sspp[i].sblk->maxhdeciexp);
  3557. max_vert_deci = max(max_vert_deci,
  3558. sde_cfg->sspp[i].sblk->maxvdeciexp);
  3559. }
  3560. if (sde_cfg->has_qos_fl_nocalc)
  3561. set_bit(SDE_PERF_SSPP_QOS_FL_NOCALC,
  3562. &sde_cfg->sspp[i].perf_features);
  3563. /*
  3564. * set sec-ui blocked SSPP feature flag based on blocked
  3565. * xin-mask if sec-ui-misr feature is enabled;
  3566. */
  3567. if (sde_cfg->sui_misr_supported
  3568. && (sde_cfg->sui_block_xin_mask
  3569. & BIT(sde_cfg->sspp[i].xin_id)))
  3570. set_bit(SDE_SSPP_BLOCK_SEC_UI,
  3571. &sde_cfg->sspp[i].features);
  3572. }
  3573. /* this should be updated based on HW rev in future */
  3574. sde_cfg->max_lm_per_display = MAX_LM_PER_DISPLAY;
  3575. if (max_horz_deci)
  3576. sde_cfg->max_display_width = sde_cfg->max_sspp_linewidth *
  3577. max_horz_deci;
  3578. else
  3579. sde_cfg->max_display_width = sde_cfg->max_mixer_width *
  3580. sde_cfg->max_lm_per_display;
  3581. if (max_vert_deci)
  3582. sde_cfg->max_display_height =
  3583. MAX_DISPLAY_HEIGHT_WITH_DECIMATION * max_vert_deci;
  3584. else
  3585. sde_cfg->max_display_height = MAX_DISPLAY_HEIGHT;
  3586. sde_cfg->min_display_height = MIN_DISPLAY_HEIGHT;
  3587. sde_cfg->min_display_width = MIN_DISPLAY_WIDTH;
  3588. return rc;
  3589. }
  3590. void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg)
  3591. {
  3592. int i, j;
  3593. if (!sde_cfg)
  3594. return;
  3595. for (i = 0; i < sde_cfg->sspp_count; i++)
  3596. kfree(sde_cfg->sspp[i].sblk);
  3597. for (i = 0; i < sde_cfg->mixer_count; i++)
  3598. kfree(sde_cfg->mixer[i].sblk);
  3599. for (i = 0; i < sde_cfg->wb_count; i++)
  3600. kfree(sde_cfg->wb[i].sblk);
  3601. for (i = 0; i < sde_cfg->dspp_count; i++)
  3602. kfree(sde_cfg->dspp[i].sblk);
  3603. if (sde_cfg->ds_count)
  3604. kfree(sde_cfg->ds[0].top);
  3605. for (i = 0; i < sde_cfg->pingpong_count; i++)
  3606. kfree(sde_cfg->pingpong[i].sblk);
  3607. for (i = 0; i < sde_cfg->vbif_count; i++) {
  3608. kfree(sde_cfg->vbif[i].dynamic_ot_rd_tbl.cfg);
  3609. kfree(sde_cfg->vbif[i].dynamic_ot_wr_tbl.cfg);
  3610. for (j = VBIF_RT_CLIENT; j < VBIF_MAX_CLIENT; j++)
  3611. kfree(sde_cfg->vbif[i].qos_tbl[j].priority_lvl);
  3612. }
  3613. for (i = 0; i < SDE_QOS_LUT_USAGE_MAX; i++) {
  3614. kfree(sde_cfg->perf.sfe_lut_tbl[i].entries);
  3615. kfree(sde_cfg->perf.qos_lut_tbl[i].entries);
  3616. }
  3617. kfree(sde_cfg->dma_formats);
  3618. kfree(sde_cfg->cursor_formats);
  3619. kfree(sde_cfg->vig_formats);
  3620. kfree(sde_cfg->wb_formats);
  3621. kfree(sde_cfg->virt_vig_formats);
  3622. kfree(sde_cfg->inline_rot_formats);
  3623. kfree(sde_cfg);
  3624. }
  3625. /*************************************************************
  3626. * hardware catalog init
  3627. *************************************************************/
  3628. struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev)
  3629. {
  3630. int rc;
  3631. struct sde_mdss_cfg *sde_cfg;
  3632. struct device_node *np = dev->dev->of_node;
  3633. sde_cfg = kzalloc(sizeof(*sde_cfg), GFP_KERNEL);
  3634. if (!sde_cfg)
  3635. return ERR_PTR(-ENOMEM);
  3636. sde_cfg->hwversion = hw_rev;
  3637. rc = _sde_hardware_pre_caps(sde_cfg, hw_rev);
  3638. if (rc)
  3639. goto end;
  3640. rc = sde_top_parse_dt(np, sde_cfg);
  3641. if (rc)
  3642. goto end;
  3643. rc = sde_perf_parse_dt(np, sde_cfg);
  3644. if (rc)
  3645. goto end;
  3646. rc = sde_rot_parse_dt(np, sde_cfg);
  3647. if (rc)
  3648. goto end;
  3649. /* uidle must be done before sspp and ctl,
  3650. * so if something goes wrong, we won't
  3651. * enable it in ctl and sspp.
  3652. */
  3653. rc = sde_uidle_parse_dt(np, sde_cfg);
  3654. if (rc)
  3655. goto end;
  3656. rc = sde_ctl_parse_dt(np, sde_cfg);
  3657. if (rc)
  3658. goto end;
  3659. rc = sde_sspp_parse_dt(np, sde_cfg);
  3660. if (rc)
  3661. goto end;
  3662. rc = sde_dspp_top_parse_dt(np, sde_cfg);
  3663. if (rc)
  3664. goto end;
  3665. rc = sde_dspp_parse_dt(np, sde_cfg);
  3666. if (rc)
  3667. goto end;
  3668. rc = sde_ds_parse_dt(np, sde_cfg);
  3669. if (rc)
  3670. goto end;
  3671. rc = sde_dsc_parse_dt(np, sde_cfg);
  3672. if (rc)
  3673. goto end;
  3674. rc = sde_pp_parse_dt(np, sde_cfg);
  3675. if (rc)
  3676. goto end;
  3677. /* mixer parsing should be done after dspp,
  3678. * ds and pp for mapping setup
  3679. */
  3680. rc = sde_mixer_parse_dt(np, sde_cfg);
  3681. if (rc)
  3682. goto end;
  3683. rc = sde_intf_parse_dt(np, sde_cfg);
  3684. if (rc)
  3685. goto end;
  3686. rc = sde_wb_parse_dt(np, sde_cfg);
  3687. if (rc)
  3688. goto end;
  3689. /* cdm parsing should be done after intf and wb for mapping setup */
  3690. rc = sde_cdm_parse_dt(np, sde_cfg);
  3691. if (rc)
  3692. goto end;
  3693. rc = sde_vbif_parse_dt(np, sde_cfg);
  3694. if (rc)
  3695. goto end;
  3696. rc = sde_parse_reg_dma_dt(np, sde_cfg);
  3697. if (rc)
  3698. goto end;
  3699. rc = sde_parse_merge_3d_dt(np, sde_cfg);
  3700. if (rc)
  3701. goto end;
  3702. rc = sde_qdss_parse_dt(np, sde_cfg);
  3703. if (rc)
  3704. goto end;
  3705. rc = _sde_hardware_post_caps(sde_cfg, hw_rev);
  3706. if (rc)
  3707. goto end;
  3708. return sde_cfg;
  3709. end:
  3710. sde_hw_catalog_deinit(sde_cfg);
  3711. return NULL;
  3712. }