dp_catalog.c 69 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
  6. #include <linux/delay.h>
  7. #include <drm/drm_dp_helper.h>
  8. #include "dp_catalog.h"
  9. #include "dp_reg.h"
  10. #define DP_GET_MSB(x) (x >> 8)
  11. #define DP_GET_LSB(x) (x & 0xff)
  12. #define dp_catalog_get_priv(x) ({ \
  13. struct dp_catalog *dp_catalog; \
  14. dp_catalog = container_of(x, struct dp_catalog, x); \
  15. container_of(dp_catalog, struct dp_catalog_private, \
  16. dp_catalog); \
  17. })
  18. #define DP_INTERRUPT_STATUS1 \
  19. (DP_INTR_AUX_I2C_DONE| \
  20. DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
  21. DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \
  22. DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \
  23. DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR)
  24. #define DP_INTR_MASK1 (DP_INTERRUPT_STATUS1 << 2)
  25. #define DP_INTERRUPT_STATUS2 \
  26. (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
  27. DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
  28. #define DP_INTR_MASK2 (DP_INTERRUPT_STATUS2 << 2)
  29. #define DP_INTERRUPT_STATUS5 \
  30. (DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
  31. #define DP_INTR_MASK5 (DP_INTERRUPT_STATUS5 << 2)
  32. #define dp_catalog_fill_io(x) { \
  33. catalog->io.x = parser->get_io(parser, #x); \
  34. }
  35. #define dp_catalog_fill_io_buf(x) { \
  36. parser->get_io_buf(parser, #x); \
  37. }
  38. static u8 const vm_pre_emphasis[4][4] = {
  39. {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */
  40. {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */
  41. {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */
  42. {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
  43. };
  44. /* voltage swing, 0.2v and 1.0v are not support */
  45. static u8 const vm_voltage_swing[4][4] = {
  46. {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */
  47. {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */
  48. {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
  49. {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
  50. };
  51. enum dp_flush_bit {
  52. DP_PPS_FLUSH,
  53. DP_DHDR_FLUSH,
  54. };
  55. struct dp_catalog_io {
  56. struct dp_io_data *dp_ahb;
  57. struct dp_io_data *dp_aux;
  58. struct dp_io_data *dp_link;
  59. struct dp_io_data *dp_p0;
  60. struct dp_io_data *dp_phy;
  61. struct dp_io_data *dp_ln_tx0;
  62. struct dp_io_data *dp_ln_tx1;
  63. struct dp_io_data *dp_mmss_cc;
  64. struct dp_io_data *dp_pll;
  65. struct dp_io_data *usb3_dp_com;
  66. struct dp_io_data *hdcp_physical;
  67. struct dp_io_data *dp_p1;
  68. struct dp_io_data *dp_tcsr;
  69. };
  70. /* audio related catalog functions */
  71. struct dp_catalog_private {
  72. struct device *dev;
  73. struct dp_catalog_io io;
  74. struct dp_parser *parser;
  75. u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
  76. struct dp_catalog dp_catalog;
  77. char exe_mode[SZ_4];
  78. };
  79. /* aux related catalog functions */
  80. static u32 dp_catalog_aux_read_data(struct dp_catalog_aux *aux)
  81. {
  82. struct dp_catalog_private *catalog;
  83. struct dp_io_data *io_data;
  84. if (!aux) {
  85. pr_err("invalid input\n");
  86. goto end;
  87. }
  88. catalog = dp_catalog_get_priv(aux);
  89. io_data = catalog->io.dp_aux;
  90. return dp_read(catalog->exe_mode, io_data, DP_AUX_DATA);
  91. end:
  92. return 0;
  93. }
  94. static int dp_catalog_aux_write_data(struct dp_catalog_aux *aux)
  95. {
  96. int rc = 0;
  97. struct dp_catalog_private *catalog;
  98. struct dp_io_data *io_data;
  99. if (!aux) {
  100. pr_err("invalid input\n");
  101. rc = -EINVAL;
  102. goto end;
  103. }
  104. catalog = dp_catalog_get_priv(aux);
  105. io_data = catalog->io.dp_aux;
  106. dp_write(catalog->exe_mode, io_data, DP_AUX_DATA, aux->data);
  107. end:
  108. return rc;
  109. }
  110. static int dp_catalog_aux_write_trans(struct dp_catalog_aux *aux)
  111. {
  112. int rc = 0;
  113. struct dp_catalog_private *catalog;
  114. struct dp_io_data *io_data;
  115. if (!aux) {
  116. pr_err("invalid input\n");
  117. rc = -EINVAL;
  118. goto end;
  119. }
  120. catalog = dp_catalog_get_priv(aux);
  121. io_data = catalog->io.dp_aux;
  122. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, aux->data);
  123. end:
  124. return rc;
  125. }
  126. static int dp_catalog_aux_clear_trans(struct dp_catalog_aux *aux, bool read)
  127. {
  128. int rc = 0;
  129. u32 data = 0;
  130. struct dp_catalog_private *catalog;
  131. struct dp_io_data *io_data;
  132. if (!aux) {
  133. pr_err("invalid input\n");
  134. rc = -EINVAL;
  135. goto end;
  136. }
  137. catalog = dp_catalog_get_priv(aux);
  138. io_data = catalog->io.dp_aux;
  139. if (read) {
  140. data = dp_read(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL);
  141. data &= ~BIT(9);
  142. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, data);
  143. } else {
  144. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, 0);
  145. }
  146. end:
  147. return rc;
  148. }
  149. static void dp_catalog_aux_clear_hw_interrupts(struct dp_catalog_aux *aux)
  150. {
  151. struct dp_catalog_private *catalog;
  152. struct dp_io_data *io_data;
  153. u32 data = 0;
  154. if (!aux) {
  155. pr_err("invalid input\n");
  156. return;
  157. }
  158. catalog = dp_catalog_get_priv(aux);
  159. io_data = catalog->io.dp_phy;
  160. data = dp_read(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_STATUS);
  161. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f);
  162. wmb(); /* make sure 0x1f is written before next write */
  163. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f);
  164. wmb(); /* make sure 0x9f is written before next write */
  165. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0);
  166. wmb(); /* make sure register is cleared */
  167. }
  168. static void dp_catalog_aux_reset(struct dp_catalog_aux *aux)
  169. {
  170. u32 aux_ctrl;
  171. struct dp_catalog_private *catalog;
  172. struct dp_io_data *io_data;
  173. if (!aux) {
  174. pr_err("invalid input\n");
  175. return;
  176. }
  177. catalog = dp_catalog_get_priv(aux);
  178. io_data = catalog->io.dp_aux;
  179. aux_ctrl = dp_read(catalog->exe_mode, io_data, DP_AUX_CTRL);
  180. aux_ctrl |= BIT(1);
  181. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  182. usleep_range(1000, 1010); /* h/w recommended delay */
  183. aux_ctrl &= ~BIT(1);
  184. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  185. wmb(); /* make sure AUX reset is done here */
  186. }
  187. static void dp_catalog_aux_enable(struct dp_catalog_aux *aux, bool enable)
  188. {
  189. u32 aux_ctrl;
  190. struct dp_catalog_private *catalog;
  191. struct dp_io_data *io_data;
  192. if (!aux) {
  193. pr_err("invalid input\n");
  194. return;
  195. }
  196. catalog = dp_catalog_get_priv(aux);
  197. io_data = catalog->io.dp_aux;
  198. aux_ctrl = dp_read(catalog->exe_mode, io_data, DP_AUX_CTRL);
  199. if (enable) {
  200. aux_ctrl |= BIT(0);
  201. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  202. wmb(); /* make sure AUX module is enabled */
  203. dp_write(catalog->exe_mode, io_data, DP_TIMEOUT_COUNT, 0xffff);
  204. dp_write(catalog->exe_mode, io_data, DP_AUX_LIMITS, 0xffff);
  205. } else {
  206. aux_ctrl &= ~BIT(0);
  207. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  208. }
  209. }
  210. static void dp_catalog_aux_update_cfg(struct dp_catalog_aux *aux,
  211. struct dp_aux_cfg *cfg, enum dp_phy_aux_config_type type)
  212. {
  213. struct dp_catalog_private *catalog;
  214. u32 new_index = 0, current_index = 0;
  215. struct dp_io_data *io_data;
  216. if (!aux || !cfg || (type >= PHY_AUX_CFG_MAX)) {
  217. pr_err("invalid input\n");
  218. return;
  219. }
  220. catalog = dp_catalog_get_priv(aux);
  221. io_data = catalog->io.dp_phy;
  222. current_index = cfg[type].current_index;
  223. new_index = (current_index + 1) % cfg[type].cfg_cnt;
  224. pr_debug("Updating %s from 0x%08x to 0x%08x\n",
  225. dp_phy_aux_config_type_to_string(type),
  226. cfg[type].lut[current_index], cfg[type].lut[new_index]);
  227. dp_write(catalog->exe_mode, io_data, cfg[type].offset,
  228. cfg[type].lut[new_index]);
  229. cfg[type].current_index = new_index;
  230. }
  231. static void dp_catalog_aux_setup(struct dp_catalog_aux *aux,
  232. struct dp_aux_cfg *cfg)
  233. {
  234. struct dp_catalog_private *catalog;
  235. struct dp_io_data *io_data;
  236. int i = 0;
  237. if (!aux || !cfg) {
  238. pr_err("invalid input\n");
  239. return;
  240. }
  241. catalog = dp_catalog_get_priv(aux);
  242. io_data = catalog->io.dp_phy;
  243. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x65);
  244. wmb(); /* make sure PD programming happened */
  245. /* Turn on BIAS current for PHY/PLL */
  246. io_data = catalog->io.dp_pll;
  247. dp_write(catalog->exe_mode, io_data, QSERDES_COM_BIAS_EN_CLKBUFLR_EN,
  248. 0x1b);
  249. io_data = catalog->io.dp_phy;
  250. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x02);
  251. wmb(); /* make sure PD programming happened */
  252. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x7d);
  253. /* Turn on BIAS current for PHY/PLL */
  254. io_data = catalog->io.dp_pll;
  255. dp_write(catalog->exe_mode, io_data, QSERDES_COM_BIAS_EN_CLKBUFLR_EN,
  256. 0x3f);
  257. /* DP AUX CFG register programming */
  258. io_data = catalog->io.dp_phy;
  259. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  260. dp_write(catalog->exe_mode, io_data, cfg[i].offset,
  261. cfg[i].lut[cfg[i].current_index]);
  262. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_MASK, 0x1F);
  263. wmb(); /* make sure AUX configuration is done before enabling it */
  264. }
  265. static void dp_catalog_aux_get_irq(struct dp_catalog_aux *aux, bool cmd_busy)
  266. {
  267. u32 ack;
  268. struct dp_catalog_private *catalog;
  269. struct dp_io_data *io_data;
  270. if (!aux) {
  271. pr_err("invalid input\n");
  272. return;
  273. }
  274. catalog = dp_catalog_get_priv(aux);
  275. io_data = catalog->io.dp_ahb;
  276. aux->isr = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS);
  277. aux->isr &= ~DP_INTR_MASK1;
  278. ack = aux->isr & DP_INTERRUPT_STATUS1;
  279. ack <<= 1;
  280. ack |= DP_INTR_MASK1;
  281. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS, ack);
  282. }
  283. /* controller related catalog functions */
  284. static u32 dp_catalog_ctrl_read_hdcp_status(struct dp_catalog_ctrl *ctrl)
  285. {
  286. struct dp_catalog_private *catalog;
  287. struct dp_io_data *io_data;
  288. if (!ctrl) {
  289. pr_err("invalid input\n");
  290. return -EINVAL;
  291. }
  292. catalog = dp_catalog_get_priv(ctrl);
  293. io_data = catalog->io.dp_ahb;
  294. return dp_read(catalog->exe_mode, io_data, DP_HDCP_STATUS);
  295. }
  296. static void dp_catalog_panel_setup_vsif_infoframe_sdp(
  297. struct dp_catalog_panel *panel)
  298. {
  299. struct dp_catalog_private *catalog;
  300. struct drm_msm_ext_hdr_metadata *hdr;
  301. struct dp_io_data *io_data;
  302. u32 header, parity, data, mst_offset = 0;
  303. u8 buf[SZ_64], off = 0;
  304. if (panel->stream_id >= DP_STREAM_MAX) {
  305. pr_err("invalid stream_id:%d\n", panel->stream_id);
  306. return;
  307. }
  308. if (panel->stream_id == DP_STREAM_1)
  309. mst_offset = MMSS_DP1_VSCEXT_0 - MMSS_DP_VSCEXT_0;
  310. catalog = dp_catalog_get_priv(panel);
  311. hdr = &panel->hdr_data.hdr_meta;
  312. io_data = catalog->io.dp_link;
  313. /* HEADER BYTE 1 */
  314. header = panel->hdr_data.vscext_header_byte1;
  315. parity = dp_header_get_parity(header);
  316. data = ((header << HEADER_BYTE_1_BIT)
  317. | (parity << PARITY_BYTE_1_BIT));
  318. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_0 + mst_offset,
  319. data);
  320. memcpy(buf + off, &data, sizeof(data));
  321. off += sizeof(data);
  322. /* HEADER BYTE 2 */
  323. header = panel->hdr_data.vscext_header_byte2;
  324. parity = dp_header_get_parity(header);
  325. data = ((header << HEADER_BYTE_2_BIT)
  326. | (parity << PARITY_BYTE_2_BIT));
  327. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_1 + mst_offset,
  328. data);
  329. /* HEADER BYTE 3 */
  330. header = panel->hdr_data.vscext_header_byte3;
  331. parity = dp_header_get_parity(header);
  332. data = ((header << HEADER_BYTE_3_BIT)
  333. | (parity << PARITY_BYTE_3_BIT));
  334. data |= dp_read(catalog->exe_mode, io_data,
  335. MMSS_DP_VSCEXT_1 + mst_offset);
  336. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_1 + mst_offset,
  337. data);
  338. memcpy(buf + off, &data, sizeof(data));
  339. off += sizeof(data);
  340. print_hex_dump(KERN_DEBUG, "[drm-dp] VSCEXT: ",
  341. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  342. }
  343. static void dp_catalog_panel_setup_hdr_infoframe_sdp(
  344. struct dp_catalog_panel *panel)
  345. {
  346. struct dp_catalog_private *catalog;
  347. struct drm_msm_ext_hdr_metadata *hdr;
  348. struct dp_io_data *io_data;
  349. u32 header, parity, data, mst_offset = 0;
  350. u8 buf[SZ_64], off = 0;
  351. if (panel->stream_id >= DP_STREAM_MAX) {
  352. pr_err("invalid stream_id:%d\n", panel->stream_id);
  353. return;
  354. }
  355. if (panel->stream_id == DP_STREAM_1)
  356. mst_offset = MMSS_DP1_GENERIC2_0 - MMSS_DP_GENERIC2_0;
  357. catalog = dp_catalog_get_priv(panel);
  358. hdr = &panel->hdr_data.hdr_meta;
  359. io_data = catalog->io.dp_link;
  360. /* HEADER BYTE 1 */
  361. header = panel->hdr_data.shdr_header_byte1;
  362. parity = dp_header_get_parity(header);
  363. data = ((header << HEADER_BYTE_1_BIT)
  364. | (parity << PARITY_BYTE_1_BIT));
  365. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_0 + mst_offset,
  366. data);
  367. memcpy(buf + off, &data, sizeof(data));
  368. off += sizeof(data);
  369. /* HEADER BYTE 2 */
  370. header = panel->hdr_data.shdr_header_byte2;
  371. parity = dp_header_get_parity(header);
  372. data = ((header << HEADER_BYTE_2_BIT)
  373. | (parity << PARITY_BYTE_2_BIT));
  374. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_1 + mst_offset,
  375. data);
  376. /* HEADER BYTE 3 */
  377. header = panel->hdr_data.shdr_header_byte3;
  378. parity = dp_header_get_parity(header);
  379. data = ((header << HEADER_BYTE_3_BIT)
  380. | (parity << PARITY_BYTE_3_BIT));
  381. data |= dp_read(catalog->exe_mode, io_data,
  382. MMSS_DP_VSCEXT_1 + mst_offset);
  383. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_1 + mst_offset,
  384. data);
  385. memcpy(buf + off, &data, sizeof(data));
  386. off += sizeof(data);
  387. data = panel->hdr_data.version;
  388. data |= panel->hdr_data.length << 8;
  389. data |= hdr->eotf << 16;
  390. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_2 + mst_offset,
  391. data);
  392. memcpy(buf + off, &data, sizeof(data));
  393. off += sizeof(data);
  394. data = (DP_GET_LSB(hdr->display_primaries_x[0]) |
  395. (DP_GET_MSB(hdr->display_primaries_x[0]) << 8) |
  396. (DP_GET_LSB(hdr->display_primaries_y[0]) << 16) |
  397. (DP_GET_MSB(hdr->display_primaries_y[0]) << 24));
  398. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_3 + mst_offset,
  399. data);
  400. memcpy(buf + off, &data, sizeof(data));
  401. off += sizeof(data);
  402. data = (DP_GET_LSB(hdr->display_primaries_x[1]) |
  403. (DP_GET_MSB(hdr->display_primaries_x[1]) << 8) |
  404. (DP_GET_LSB(hdr->display_primaries_y[1]) << 16) |
  405. (DP_GET_MSB(hdr->display_primaries_y[1]) << 24));
  406. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_4 + mst_offset,
  407. data);
  408. memcpy(buf + off, &data, sizeof(data));
  409. off += sizeof(data);
  410. data = (DP_GET_LSB(hdr->display_primaries_x[2]) |
  411. (DP_GET_MSB(hdr->display_primaries_x[2]) << 8) |
  412. (DP_GET_LSB(hdr->display_primaries_y[2]) << 16) |
  413. (DP_GET_MSB(hdr->display_primaries_y[2]) << 24));
  414. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_5 + mst_offset,
  415. data);
  416. memcpy(buf + off, &data, sizeof(data));
  417. off += sizeof(data);
  418. data = (DP_GET_LSB(hdr->white_point_x) |
  419. (DP_GET_MSB(hdr->white_point_x) << 8) |
  420. (DP_GET_LSB(hdr->white_point_y) << 16) |
  421. (DP_GET_MSB(hdr->white_point_y) << 24));
  422. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_6 + mst_offset,
  423. data);
  424. memcpy(buf + off, &data, sizeof(data));
  425. off += sizeof(data);
  426. data = (DP_GET_LSB(hdr->max_luminance) |
  427. (DP_GET_MSB(hdr->max_luminance) << 8) |
  428. (DP_GET_LSB(hdr->min_luminance) << 16) |
  429. (DP_GET_MSB(hdr->min_luminance) << 24));
  430. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_7 + mst_offset,
  431. data);
  432. memcpy(buf + off, &data, sizeof(data));
  433. off += sizeof(data);
  434. data = (DP_GET_LSB(hdr->max_content_light_level) |
  435. (DP_GET_MSB(hdr->max_content_light_level) << 8) |
  436. (DP_GET_LSB(hdr->max_average_light_level) << 16) |
  437. (DP_GET_MSB(hdr->max_average_light_level) << 24));
  438. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_8 + mst_offset,
  439. data);
  440. memcpy(buf + off, &data, sizeof(data));
  441. off += sizeof(data);
  442. data = 0;
  443. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_9 + mst_offset,
  444. data);
  445. memcpy(buf + off, &data, sizeof(data));
  446. off += sizeof(data);
  447. print_hex_dump(KERN_DEBUG, "[drm-dp] HDR: ",
  448. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  449. }
  450. static void dp_catalog_panel_setup_vsc_sdp(struct dp_catalog_panel *panel)
  451. {
  452. struct dp_catalog_private *catalog;
  453. struct dp_io_data *io_data;
  454. u32 header, parity, data, mst_offset = 0;
  455. u8 bpc, off = 0;
  456. u8 buf[SZ_128];
  457. if (!panel) {
  458. pr_err("invalid input\n");
  459. return;
  460. }
  461. if (panel->stream_id >= DP_STREAM_MAX) {
  462. pr_err("invalid stream_id:%d\n", panel->stream_id);
  463. return;
  464. }
  465. if (panel->stream_id == DP_STREAM_1)
  466. mst_offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  467. catalog = dp_catalog_get_priv(panel);
  468. io_data = catalog->io.dp_link;
  469. /* HEADER BYTE 1 */
  470. header = panel->hdr_data.vsc_header_byte1;
  471. parity = dp_header_get_parity(header);
  472. data = ((header << HEADER_BYTE_1_BIT)
  473. | (parity << PARITY_BYTE_1_BIT));
  474. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_0 + mst_offset,
  475. data);
  476. memcpy(buf + off, &data, sizeof(data));
  477. off += sizeof(data);
  478. /* HEADER BYTE 2 */
  479. header = panel->hdr_data.vsc_header_byte2;
  480. parity = dp_header_get_parity(header);
  481. data = ((header << HEADER_BYTE_2_BIT)
  482. | (parity << PARITY_BYTE_2_BIT));
  483. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_1 + mst_offset,
  484. data);
  485. /* HEADER BYTE 3 */
  486. header = panel->hdr_data.vsc_header_byte3;
  487. parity = dp_header_get_parity(header);
  488. data = ((header << HEADER_BYTE_3_BIT)
  489. | (parity << PARITY_BYTE_3_BIT));
  490. data |= dp_read(catalog->exe_mode, io_data,
  491. MMSS_DP_GENERIC0_1 + mst_offset);
  492. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_1 + mst_offset,
  493. data);
  494. memcpy(buf + off, &data, sizeof(data));
  495. off += sizeof(data);
  496. data = 0;
  497. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_2 + mst_offset,
  498. data);
  499. memcpy(buf + off, &data, sizeof(data));
  500. off += sizeof(data);
  501. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_3 + mst_offset,
  502. data);
  503. memcpy(buf + off, &data, sizeof(data));
  504. off += sizeof(data);
  505. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_4 + mst_offset,
  506. data);
  507. memcpy(buf + off, &data, sizeof(data));
  508. off += sizeof(data);
  509. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_5 + mst_offset,
  510. data);
  511. memcpy(buf + off, &data, sizeof(data));
  512. off += sizeof(data);
  513. switch (panel->hdr_data.bpc) {
  514. default:
  515. case 10:
  516. bpc = BIT(1);
  517. break;
  518. case 8:
  519. bpc = BIT(0);
  520. break;
  521. case 6:
  522. bpc = 0;
  523. break;
  524. }
  525. data = (panel->hdr_data.colorimetry & 0xF) |
  526. ((panel->hdr_data.pixel_encoding & 0xF) << 4) |
  527. (bpc << 8) |
  528. ((panel->hdr_data.dynamic_range & 0x1) << 15) |
  529. ((panel->hdr_data.content_type & 0x7) << 16);
  530. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_6 + mst_offset,
  531. data);
  532. memcpy(buf + off, &data, sizeof(data));
  533. off += sizeof(data);
  534. data = 0;
  535. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_7 + mst_offset,
  536. data);
  537. memcpy(buf + off, &data, sizeof(data));
  538. off += sizeof(data);
  539. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_8 + mst_offset,
  540. data);
  541. memcpy(buf + off, &data, sizeof(data));
  542. off += sizeof(data);
  543. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_9 + mst_offset,
  544. data);
  545. memcpy(buf + off, &data, sizeof(data));
  546. off += sizeof(data);
  547. print_hex_dump(KERN_DEBUG, "[drm-dp] VSC: ",
  548. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  549. }
  550. static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en,
  551. u32 dhdr_max_pkts)
  552. {
  553. struct dp_catalog_private *catalog;
  554. struct dp_io_data *io_data;
  555. u32 cfg, cfg2, cfg4, misc;
  556. u32 sdp_cfg_off = 0;
  557. u32 sdp_cfg2_off = 0;
  558. u32 sdp_cfg3_off = 0;
  559. u32 sdp_cfg4_off = 0;
  560. u32 misc1_misc0_off = 0;
  561. if (!panel) {
  562. pr_err("invalid input\n");
  563. return;
  564. }
  565. if (panel->stream_id >= DP_STREAM_MAX) {
  566. pr_err("invalid stream_id:%d\n", panel->stream_id);
  567. return;
  568. }
  569. catalog = dp_catalog_get_priv(panel);
  570. io_data = catalog->io.dp_link;
  571. if (panel->stream_id == DP_STREAM_1) {
  572. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  573. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  574. sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
  575. sdp_cfg4_off = MMSS_DP1_SDP_CFG4 - MMSS_DP_SDP_CFG4;
  576. misc1_misc0_off = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  577. }
  578. cfg = dp_read(catalog->exe_mode, io_data,
  579. MMSS_DP_SDP_CFG + sdp_cfg_off);
  580. cfg2 = dp_read(catalog->exe_mode, io_data,
  581. MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  582. misc = dp_read(catalog->exe_mode, io_data,
  583. DP_MISC1_MISC0 + misc1_misc0_off);
  584. if (en) {
  585. if (dhdr_max_pkts) {
  586. /* VSCEXT_SDP_EN */
  587. cfg |= BIT(16);
  588. /* DHDR_EN, DHDR_PACKET_LIMIT */
  589. cfg4 = (dhdr_max_pkts << 1) | BIT(0);
  590. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4
  591. + sdp_cfg4_off, cfg4);
  592. dp_catalog_panel_setup_vsif_infoframe_sdp(panel);
  593. }
  594. /* GEN0_SDP_EN, GEN2_SDP_EN */
  595. cfg |= BIT(17) | BIT(19);
  596. dp_write(catalog->exe_mode, io_data,
  597. MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  598. /* GENERIC0_SDPSIZE GENERIC2_SDPSIZE */
  599. cfg2 |= BIT(16) | BIT(20);
  600. dp_write(catalog->exe_mode, io_data,
  601. MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  602. dp_catalog_panel_setup_vsc_sdp(panel);
  603. dp_catalog_panel_setup_hdr_infoframe_sdp(panel);
  604. /* indicates presence of VSC (BIT(6) of MISC1) */
  605. misc |= BIT(14);
  606. if (panel->hdr_data.hdr_meta.eotf)
  607. pr_debug("Enabled\n");
  608. else
  609. pr_debug("Reset\n");
  610. } else {
  611. /* VSCEXT_SDP_EN, GEN0_SDP_EN */
  612. cfg &= ~BIT(16) & ~BIT(17) & ~BIT(19);
  613. dp_write(catalog->exe_mode, io_data,
  614. MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  615. /* GENERIC0_SDPSIZE GENERIC2_SDPSIZE */
  616. cfg2 &= ~BIT(16) & ~BIT(20);
  617. dp_write(catalog->exe_mode, io_data,
  618. MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  619. /* DHDR_EN, DHDR_PACKET_LIMIT */
  620. cfg4 = 0;
  621. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4
  622. + sdp_cfg4_off, cfg4);
  623. /* switch back to MSA */
  624. misc &= ~BIT(14);
  625. pr_debug("Disabled\n");
  626. }
  627. dp_write(catalog->exe_mode, io_data, DP_MISC1_MISC0 + misc1_misc0_off,
  628. misc);
  629. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  630. 0x01);
  631. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  632. 0x00);
  633. }
  634. static void dp_catalog_panel_update_transfer_unit(
  635. struct dp_catalog_panel *panel)
  636. {
  637. struct dp_catalog_private *catalog;
  638. struct dp_io_data *io_data;
  639. if (!panel || panel->stream_id >= DP_STREAM_MAX) {
  640. pr_err("invalid input\n");
  641. return;
  642. }
  643. catalog = dp_catalog_get_priv(panel);
  644. io_data = catalog->io.dp_link;
  645. dp_write(catalog->exe_mode, io_data, DP_VALID_BOUNDARY,
  646. panel->valid_boundary);
  647. dp_write(catalog->exe_mode, io_data, DP_TU, panel->dp_tu);
  648. dp_write(catalog->exe_mode, io_data, DP_VALID_BOUNDARY_2,
  649. panel->valid_boundary2);
  650. }
  651. static void dp_catalog_ctrl_state_ctrl(struct dp_catalog_ctrl *ctrl, u32 state)
  652. {
  653. struct dp_catalog_private *catalog;
  654. struct dp_io_data *io_data;
  655. if (!ctrl) {
  656. pr_err("invalid input\n");
  657. return;
  658. }
  659. catalog = dp_catalog_get_priv(ctrl);
  660. io_data = catalog->io.dp_link;
  661. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, state);
  662. /* make sure to change the hw state */
  663. wmb();
  664. }
  665. static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt)
  666. {
  667. struct dp_catalog_private *catalog;
  668. struct dp_io_data *io_data;
  669. u32 cfg;
  670. if (!ctrl) {
  671. pr_err("invalid input\n");
  672. return;
  673. }
  674. catalog = dp_catalog_get_priv(ctrl);
  675. io_data = catalog->io.dp_link;
  676. cfg = dp_read(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL);
  677. cfg &= ~(BIT(4) | BIT(5));
  678. cfg |= (ln_cnt - 1) << 4;
  679. dp_write(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL, cfg);
  680. cfg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  681. cfg |= 0x02000000;
  682. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, cfg);
  683. pr_debug("DP_MAINLINK_CTRL=0x%x\n", cfg);
  684. }
  685. static void dp_catalog_panel_config_ctrl(struct dp_catalog_panel *panel,
  686. u32 cfg)
  687. {
  688. struct dp_catalog_private *catalog;
  689. struct dp_io_data *io_data;
  690. u32 strm_reg_off = 0, mainlink_ctrl;
  691. if (!panel) {
  692. pr_err("invalid input\n");
  693. return;
  694. }
  695. if (panel->stream_id >= DP_STREAM_MAX) {
  696. pr_err("invalid stream_id:%d\n", panel->stream_id);
  697. return;
  698. }
  699. catalog = dp_catalog_get_priv(panel);
  700. io_data = catalog->io.dp_link;
  701. if (panel->stream_id == DP_STREAM_1)
  702. strm_reg_off = DP1_CONFIGURATION_CTRL - DP_CONFIGURATION_CTRL;
  703. pr_debug("DP_CONFIGURATION_CTRL=0x%x\n", cfg);
  704. dp_write(catalog->exe_mode, io_data,
  705. DP_CONFIGURATION_CTRL + strm_reg_off, cfg);
  706. mainlink_ctrl = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  707. if (panel->stream_id == DP_STREAM_0)
  708. io_data = catalog->io.dp_p0;
  709. else if (panel->stream_id == DP_STREAM_1)
  710. io_data = catalog->io.dp_p1;
  711. if (mainlink_ctrl & BIT(8))
  712. dp_write(catalog->exe_mode, io_data, MMSS_DP_ASYNC_FIFO_CONFIG,
  713. 0x01);
  714. else
  715. dp_write(catalog->exe_mode, io_data, MMSS_DP_ASYNC_FIFO_CONFIG,
  716. 0x00);
  717. }
  718. static void dp_catalog_panel_config_dto(struct dp_catalog_panel *panel,
  719. bool ack)
  720. {
  721. struct dp_catalog_private *catalog;
  722. struct dp_io_data *io_data;
  723. u32 dsc_dto;
  724. if (!panel) {
  725. pr_err("invalid input\n");
  726. return;
  727. }
  728. if (panel->stream_id >= DP_STREAM_MAX) {
  729. pr_err("invalid stream_id:%d\n", panel->stream_id);
  730. return;
  731. }
  732. catalog = dp_catalog_get_priv(panel);
  733. io_data = catalog->io.dp_link;
  734. switch (panel->stream_id) {
  735. case DP_STREAM_0:
  736. io_data = catalog->io.dp_p0;
  737. break;
  738. case DP_STREAM_1:
  739. io_data = catalog->io.dp_p1;
  740. break;
  741. default:
  742. pr_err("invalid stream id\n");
  743. return;
  744. }
  745. dsc_dto = dp_read(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO);
  746. if (ack)
  747. dsc_dto = BIT(1);
  748. else
  749. dsc_dto &= ~BIT(1);
  750. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO, dsc_dto);
  751. }
  752. static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl,
  753. bool flipped, char *lane_map)
  754. {
  755. struct dp_catalog_private *catalog;
  756. struct dp_io_data *io_data;
  757. if (!ctrl) {
  758. pr_err("invalid input\n");
  759. return;
  760. }
  761. catalog = dp_catalog_get_priv(ctrl);
  762. io_data = catalog->io.dp_link;
  763. dp_write(catalog->exe_mode, io_data, DP_LOGICAL2PHYSICAL_LANE_MAPPING,
  764. 0xe4);
  765. }
  766. static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl,
  767. u8 ln_pnswap)
  768. {
  769. struct dp_catalog_private *catalog;
  770. struct dp_io_data *io_data;
  771. u32 cfg0, cfg1;
  772. catalog = dp_catalog_get_priv(ctrl);
  773. cfg0 = 0x0a;
  774. cfg1 = 0x0a;
  775. cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;
  776. cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;
  777. cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;
  778. cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;
  779. io_data = catalog->io.dp_ln_tx0;
  780. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg0);
  781. io_data = catalog->io.dp_ln_tx1;
  782. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg1);
  783. }
  784. static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl,
  785. bool enable)
  786. {
  787. u32 mainlink_ctrl, reg;
  788. struct dp_catalog_private *catalog;
  789. struct dp_io_data *io_data;
  790. if (!ctrl) {
  791. pr_err("invalid input\n");
  792. return;
  793. }
  794. catalog = dp_catalog_get_priv(ctrl);
  795. io_data = catalog->io.dp_link;
  796. if (enable) {
  797. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  798. mainlink_ctrl = reg & ~(0x03);
  799. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  800. mainlink_ctrl);
  801. wmb(); /* make sure mainlink is turned off before reset */
  802. mainlink_ctrl = reg | 0x02;
  803. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  804. mainlink_ctrl);
  805. wmb(); /* make sure mainlink entered reset */
  806. mainlink_ctrl = reg & ~(0x03);
  807. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  808. mainlink_ctrl);
  809. wmb(); /* make sure mainlink reset done */
  810. mainlink_ctrl = reg | 0x01;
  811. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  812. mainlink_ctrl);
  813. wmb(); /* make sure mainlink turned on */
  814. } else {
  815. mainlink_ctrl = dp_read(catalog->exe_mode, io_data,
  816. DP_MAINLINK_CTRL);
  817. mainlink_ctrl &= ~BIT(0);
  818. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  819. mainlink_ctrl);
  820. }
  821. }
  822. static void dp_catalog_panel_config_misc(struct dp_catalog_panel *panel)
  823. {
  824. struct dp_catalog_private *catalog;
  825. struct dp_io_data *io_data;
  826. u32 reg_offset = 0;
  827. if (!panel) {
  828. pr_err("invalid input\n");
  829. return;
  830. }
  831. if (panel->stream_id >= DP_STREAM_MAX) {
  832. pr_err("invalid stream_id:%d\n", panel->stream_id);
  833. return;
  834. }
  835. catalog = dp_catalog_get_priv(panel);
  836. io_data = catalog->io.dp_link;
  837. if (panel->stream_id == DP_STREAM_1)
  838. reg_offset = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  839. pr_debug("misc settings = 0x%x\n", panel->misc_val);
  840. dp_write(catalog->exe_mode, io_data, DP_MISC1_MISC0 + reg_offset,
  841. panel->misc_val);
  842. }
  843. static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
  844. u32 rate, u32 stream_rate_khz)
  845. {
  846. u32 pixel_m, pixel_n;
  847. u32 mvid, nvid;
  848. u32 const nvid_fixed = 0x8000;
  849. u32 const link_rate_hbr2 = 540000;
  850. u32 const link_rate_hbr3 = 810000;
  851. struct dp_catalog_private *catalog;
  852. struct dp_io_data *io_data;
  853. u32 strm_reg_off = 0;
  854. u32 mvid_reg_off = 0, nvid_reg_off = 0;
  855. if (!panel) {
  856. pr_err("invalid input\n");
  857. return;
  858. }
  859. if (panel->stream_id >= DP_STREAM_MAX) {
  860. pr_err("invalid stream_id:%d\n", panel->stream_id);
  861. return;
  862. }
  863. catalog = dp_catalog_get_priv(panel);
  864. io_data = catalog->io.dp_mmss_cc;
  865. if (panel->stream_id == DP_STREAM_1)
  866. strm_reg_off = MMSS_DP_PIXEL1_M - MMSS_DP_PIXEL_M;
  867. pixel_m = dp_read(catalog->exe_mode, io_data,
  868. MMSS_DP_PIXEL_M + strm_reg_off);
  869. pixel_n = dp_read(catalog->exe_mode, io_data,
  870. MMSS_DP_PIXEL_N + strm_reg_off);
  871. pr_debug("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n);
  872. mvid = (pixel_m & 0xFFFF) * 5;
  873. nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
  874. if (nvid < nvid_fixed) {
  875. u32 temp;
  876. temp = (nvid_fixed / nvid) * nvid;
  877. mvid = (nvid_fixed / nvid) * mvid;
  878. nvid = temp;
  879. }
  880. pr_debug("rate = %d\n", rate);
  881. if (panel->widebus_en)
  882. mvid <<= 1;
  883. if (link_rate_hbr2 == rate)
  884. nvid *= 2;
  885. if (link_rate_hbr3 == rate)
  886. nvid *= 3;
  887. io_data = catalog->io.dp_link;
  888. if (panel->stream_id == DP_STREAM_1) {
  889. mvid_reg_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID;
  890. nvid_reg_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID;
  891. }
  892. pr_debug("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
  893. dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_MVID + mvid_reg_off,
  894. mvid);
  895. dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID + nvid_reg_off,
  896. nvid);
  897. }
  898. static void dp_catalog_ctrl_set_pattern(struct dp_catalog_ctrl *ctrl,
  899. u32 pattern)
  900. {
  901. int bit, cnt = 10;
  902. u32 data;
  903. struct dp_catalog_private *catalog;
  904. struct dp_io_data *io_data;
  905. if (!ctrl) {
  906. pr_err("invalid input\n");
  907. return;
  908. }
  909. catalog = dp_catalog_get_priv(ctrl);
  910. io_data = catalog->io.dp_link;
  911. bit = 1;
  912. bit <<= (pattern - 1);
  913. pr_debug("hw: bit=%d train=%d\n", bit, pattern);
  914. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, bit);
  915. bit = 8;
  916. bit <<= (pattern - 1);
  917. while (cnt--) {
  918. data = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  919. if (data & bit)
  920. break;
  921. }
  922. if (cnt == 0)
  923. pr_err("set link_train=%d failed\n", pattern);
  924. }
  925. static void dp_catalog_ctrl_usb_reset(struct dp_catalog_ctrl *ctrl, bool flip)
  926. {
  927. struct dp_catalog_private *catalog;
  928. struct dp_io_data *io_data;
  929. if (!ctrl) {
  930. pr_err("invalid input\n");
  931. return;
  932. }
  933. catalog = dp_catalog_get_priv(ctrl);
  934. io_data = catalog->io.usb3_dp_com;
  935. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_RESET_OVRD_CTRL, 0x0a);
  936. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_PHY_MODE_CTRL, 0x02);
  937. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SW_RESET, 0x01);
  938. /* make sure usb3 com phy software reset is done */
  939. wmb();
  940. if (!flip) { /* CC1 */
  941. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_TYPEC_CTRL,
  942. 0x02);
  943. } else { /* CC2 */
  944. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_TYPEC_CTRL,
  945. 0x03);
  946. }
  947. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SWI_CTRL, 0x00);
  948. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SW_RESET, 0x00);
  949. /* make sure the software reset is done */
  950. wmb();
  951. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_POWER_DOWN_CTRL, 0x01);
  952. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_RESET_OVRD_CTRL, 0x00);
  953. /* make sure phy is brought out of reset */
  954. wmb();
  955. }
  956. static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
  957. bool enable)
  958. {
  959. struct dp_catalog_private *catalog;
  960. struct dp_io_data *io_data;
  961. if (!panel) {
  962. pr_err("invalid input\n");
  963. return;
  964. }
  965. if (panel->stream_id >= DP_STREAM_MAX) {
  966. pr_err("invalid stream_id:%d\n", panel->stream_id);
  967. return;
  968. }
  969. catalog = dp_catalog_get_priv(panel);
  970. if (panel->stream_id == DP_STREAM_0)
  971. io_data = catalog->io.dp_p0;
  972. else if (panel->stream_id == DP_STREAM_1)
  973. io_data = catalog->io.dp_p1;
  974. if (!enable) {
  975. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_MAIN_CONTROL,
  976. 0x0);
  977. dp_write(catalog->exe_mode, io_data, MMSS_DP_BIST_ENABLE, 0x0);
  978. dp_write(catalog->exe_mode, io_data, MMSS_DP_TIMING_ENGINE_EN,
  979. 0x0);
  980. wmb(); /* ensure Timing generator is turned off */
  981. return;
  982. }
  983. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG, 0x0);
  984. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_HSYNC_CTL,
  985. panel->hsync_ctl);
  986. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PERIOD_F0,
  987. panel->vsync_period * panel->hsync_period);
  988. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0,
  989. panel->v_sync_width * panel->hsync_period);
  990. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
  991. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1,
  992. 0);
  993. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_HCTL,
  994. panel->display_hctl);
  995. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_HCTL, 0);
  996. dp_write(catalog->exe_mode, io_data, MMSS_INTF_DISPLAY_V_START_F0,
  997. panel->display_v_start);
  998. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_V_END_F0,
  999. panel->display_v_end);
  1000. dp_write(catalog->exe_mode, io_data, MMSS_INTF_DISPLAY_V_START_F1, 0);
  1001. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
  1002. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
  1003. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
  1004. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
  1005. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
  1006. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_POLARITY_CTL, 0);
  1007. wmb(); /* ensure TPG registers are programmed */
  1008. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_MAIN_CONTROL, 0x100);
  1009. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_VIDEO_CONFIG, 0x5);
  1010. wmb(); /* ensure TPG config is programmed */
  1011. dp_write(catalog->exe_mode, io_data, MMSS_DP_BIST_ENABLE, 0x1);
  1012. dp_write(catalog->exe_mode, io_data, MMSS_DP_TIMING_ENGINE_EN, 0x1);
  1013. wmb(); /* ensure Timing generator is turned on */
  1014. }
  1015. static void dp_catalog_panel_dsc_cfg(struct dp_catalog_panel *panel)
  1016. {
  1017. struct dp_catalog_private *catalog;
  1018. struct dp_io_data *io_data;
  1019. u32 reg, offset;
  1020. int i;
  1021. if (!panel) {
  1022. pr_err("invalid input\n");
  1023. return;
  1024. }
  1025. if (panel->stream_id >= DP_STREAM_MAX) {
  1026. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1027. return;
  1028. }
  1029. catalog = dp_catalog_get_priv(panel);
  1030. if (panel->stream_id == DP_STREAM_0)
  1031. io_data = catalog->io.dp_p0;
  1032. else
  1033. io_data = catalog->io.dp_p1;
  1034. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO_COUNT,
  1035. panel->dsc.dto_count);
  1036. reg = dp_read(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO);
  1037. if (panel->dsc.dto_en) {
  1038. reg |= BIT(0);
  1039. reg |= (panel->dsc.dto_n << 8);
  1040. reg |= (panel->dsc.dto_d << 16);
  1041. }
  1042. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO, reg);
  1043. io_data = catalog->io.dp_link;
  1044. if (panel->stream_id == DP_STREAM_0)
  1045. offset = 0;
  1046. else
  1047. offset = DP1_COMPRESSION_MODE_CTRL - DP_COMPRESSION_MODE_CTRL;
  1048. dp_write(catalog->exe_mode, io_data, DP_PPS_HB_0_3 + offset, 0x7F1000);
  1049. dp_write(catalog->exe_mode, io_data, DP_PPS_PB_0_3 + offset, 0xA22300);
  1050. for (i = 0; i < panel->dsc.parity_word_len; i++)
  1051. dp_write(catalog->exe_mode, io_data,
  1052. DP_PPS_PB_4_7 + (i << 2) + offset,
  1053. panel->dsc.parity_word[i]);
  1054. for (i = 0; i < panel->dsc.pps_word_len; i++)
  1055. dp_write(catalog->exe_mode, io_data,
  1056. DP_PPS_PPS_0_3 + (i << 2) + offset,
  1057. panel->dsc.pps_word[i]);
  1058. reg = 0;
  1059. if (panel->dsc.dsc_en) {
  1060. reg = BIT(0);
  1061. reg |= (panel->dsc.eol_byte_num << 3);
  1062. reg |= (panel->dsc.slice_per_pkt << 5);
  1063. reg |= (panel->dsc.bytes_per_pkt << 16);
  1064. reg |= (panel->dsc.be_in_lane << 10);
  1065. }
  1066. dp_write(catalog->exe_mode, io_data,
  1067. DP_COMPRESSION_MODE_CTRL + offset, reg);
  1068. pr_debug("compression:0x%x for stream:%d\n",
  1069. reg, panel->stream_id);
  1070. }
  1071. static void dp_catalog_panel_dp_flush(struct dp_catalog_panel *panel,
  1072. enum dp_flush_bit flush_bit)
  1073. {
  1074. struct dp_catalog_private *catalog;
  1075. struct dp_io_data *io_data;
  1076. u32 dp_flush, offset;
  1077. if (!panel) {
  1078. pr_err("invalid input\n");
  1079. return;
  1080. }
  1081. if (panel->stream_id >= DP_STREAM_MAX) {
  1082. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1083. return;
  1084. }
  1085. catalog = dp_catalog_get_priv(panel);
  1086. io_data = catalog->io.dp_link;
  1087. if (panel->stream_id == DP_STREAM_0)
  1088. offset = 0;
  1089. else
  1090. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1091. dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset);
  1092. dp_flush |= BIT(flush_bit);
  1093. dp_write(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset, dp_flush);
  1094. }
  1095. static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel)
  1096. {
  1097. dp_catalog_panel_dp_flush(panel, DP_PPS_FLUSH);
  1098. pr_debug("pps flush for stream:%d\n", panel->stream_id);
  1099. }
  1100. static void dp_catalog_panel_dhdr_flush(struct dp_catalog_panel *panel)
  1101. {
  1102. dp_catalog_panel_dp_flush(panel, DP_DHDR_FLUSH);
  1103. pr_debug("dhdr flush for stream:%d\n", panel->stream_id);
  1104. }
  1105. static bool dp_catalog_panel_dhdr_busy(struct dp_catalog_panel *panel)
  1106. {
  1107. struct dp_catalog_private *catalog;
  1108. struct dp_io_data *io_data;
  1109. u32 dp_flush, offset;
  1110. if (panel->stream_id >= DP_STREAM_MAX) {
  1111. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1112. return false;
  1113. }
  1114. catalog = dp_catalog_get_priv(panel);
  1115. io_data = catalog->io.dp_link;
  1116. if (panel->stream_id == DP_STREAM_0)
  1117. offset = 0;
  1118. else
  1119. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1120. dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset);
  1121. return dp_flush & BIT(DP_DHDR_FLUSH) ? true : false;
  1122. }
  1123. static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl)
  1124. {
  1125. u32 sw_reset;
  1126. struct dp_catalog_private *catalog;
  1127. struct dp_io_data *io_data;
  1128. if (!ctrl) {
  1129. pr_err("invalid input\n");
  1130. return;
  1131. }
  1132. catalog = dp_catalog_get_priv(ctrl);
  1133. io_data = catalog->io.dp_ahb;
  1134. sw_reset = dp_read(catalog->exe_mode, io_data, DP_SW_RESET);
  1135. sw_reset |= BIT(0);
  1136. dp_write(catalog->exe_mode, io_data, DP_SW_RESET, sw_reset);
  1137. usleep_range(1000, 1010); /* h/w recommended delay */
  1138. sw_reset &= ~BIT(0);
  1139. dp_write(catalog->exe_mode, io_data, DP_SW_RESET, sw_reset);
  1140. }
  1141. static bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog_ctrl *ctrl)
  1142. {
  1143. u32 data;
  1144. int cnt = 10;
  1145. struct dp_catalog_private *catalog;
  1146. struct dp_io_data *io_data;
  1147. if (!ctrl) {
  1148. pr_err("invalid input\n");
  1149. goto end;
  1150. }
  1151. catalog = dp_catalog_get_priv(ctrl);
  1152. io_data = catalog->io.dp_link;
  1153. while (--cnt) {
  1154. /* DP_MAINLINK_READY */
  1155. data = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  1156. if (data & BIT(0))
  1157. return true;
  1158. usleep_range(1000, 1010); /* 1ms wait before next reg read */
  1159. }
  1160. pr_err("mainlink not ready\n");
  1161. end:
  1162. return false;
  1163. }
  1164. static void dp_catalog_ctrl_enable_irq(struct dp_catalog_ctrl *ctrl,
  1165. bool enable)
  1166. {
  1167. struct dp_catalog_private *catalog;
  1168. struct dp_io_data *io_data;
  1169. if (!ctrl) {
  1170. pr_err("invalid input\n");
  1171. return;
  1172. }
  1173. catalog = dp_catalog_get_priv(ctrl);
  1174. io_data = catalog->io.dp_ahb;
  1175. if (enable) {
  1176. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS,
  1177. DP_INTR_MASK1);
  1178. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2,
  1179. DP_INTR_MASK2);
  1180. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5,
  1181. DP_INTR_MASK5);
  1182. } else {
  1183. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS, 0x00);
  1184. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2, 0x00);
  1185. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5, 0x00);
  1186. }
  1187. }
  1188. static void dp_catalog_ctrl_get_interrupt(struct dp_catalog_ctrl *ctrl)
  1189. {
  1190. u32 ack = 0;
  1191. struct dp_catalog_private *catalog;
  1192. struct dp_io_data *io_data;
  1193. if (!ctrl) {
  1194. pr_err("invalid input\n");
  1195. return;
  1196. }
  1197. catalog = dp_catalog_get_priv(ctrl);
  1198. io_data = catalog->io.dp_ahb;
  1199. ctrl->isr = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS2);
  1200. ctrl->isr &= ~DP_INTR_MASK2;
  1201. ack = ctrl->isr & DP_INTERRUPT_STATUS2;
  1202. ack <<= 1;
  1203. ack |= DP_INTR_MASK2;
  1204. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2, ack);
  1205. ctrl->isr5 = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS5);
  1206. ctrl->isr5 &= ~DP_INTR_MASK5;
  1207. ack = ctrl->isr5 & DP_INTERRUPT_STATUS5;
  1208. ack <<= 1;
  1209. ack |= DP_INTR_MASK5;
  1210. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5, ack);
  1211. }
  1212. static void dp_catalog_ctrl_phy_reset(struct dp_catalog_ctrl *ctrl)
  1213. {
  1214. struct dp_catalog_private *catalog;
  1215. struct dp_io_data *io_data;
  1216. if (!ctrl) {
  1217. pr_err("invalid input\n");
  1218. return;
  1219. }
  1220. catalog = dp_catalog_get_priv(ctrl);
  1221. io_data = catalog->io.dp_ahb;
  1222. dp_write(catalog->exe_mode, io_data, DP_PHY_CTRL, 0x5); /* bit 0 & 2 */
  1223. usleep_range(1000, 1010); /* h/w recommended delay */
  1224. dp_write(catalog->exe_mode, io_data, DP_PHY_CTRL, 0x0);
  1225. wmb(); /* make sure PHY reset done */
  1226. }
  1227. static void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog_ctrl *ctrl,
  1228. bool flipped, u8 ln_cnt)
  1229. {
  1230. u32 info = 0x0;
  1231. struct dp_catalog_private *catalog;
  1232. struct dp_io_data *io_data;
  1233. u8 orientation = BIT(!!flipped);
  1234. if (!ctrl) {
  1235. pr_err("invalid input\n");
  1236. return;
  1237. }
  1238. catalog = dp_catalog_get_priv(ctrl);
  1239. io_data = catalog->io.dp_phy;
  1240. info |= (ln_cnt & 0x0F);
  1241. info |= ((orientation & 0x0F) << 4);
  1242. pr_debug("Shared Info = 0x%x\n", info);
  1243. dp_write(catalog->exe_mode, io_data, DP_PHY_SPARE0, info);
  1244. }
  1245. static void dp_catalog_ctrl_update_vx_px(struct dp_catalog_ctrl *ctrl,
  1246. u8 v_level, u8 p_level, bool high)
  1247. {
  1248. struct dp_catalog_private *catalog;
  1249. struct dp_io_data *io_data;
  1250. u8 value0, value1;
  1251. if (!ctrl) {
  1252. pr_err("invalid input\n");
  1253. return;
  1254. }
  1255. catalog = dp_catalog_get_priv(ctrl);
  1256. pr_debug("hw: v=%d p=%d\n", v_level, p_level);
  1257. value0 = vm_voltage_swing[v_level][p_level];
  1258. value1 = vm_pre_emphasis[v_level][p_level];
  1259. /* program default setting first */
  1260. io_data = catalog->io.dp_ln_tx0;
  1261. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A);
  1262. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  1263. io_data = catalog->io.dp_ln_tx1;
  1264. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A);
  1265. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  1266. /* Enable MUX to use Cursor values from these registers */
  1267. value0 |= BIT(5);
  1268. value1 |= BIT(5);
  1269. /* Configure host and panel only if both values are allowed */
  1270. if (value0 != 0xFF && value1 != 0xFF) {
  1271. io_data = catalog->io.dp_ln_tx0;
  1272. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0);
  1273. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL,
  1274. value1);
  1275. io_data = catalog->io.dp_ln_tx1;
  1276. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0);
  1277. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL,
  1278. value1);
  1279. pr_debug("hw: vx_value=0x%x px_value=0x%x\n",
  1280. value0, value1);
  1281. } else {
  1282. pr_err("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
  1283. v_level, value0, p_level, value1);
  1284. }
  1285. }
  1286. static void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog_ctrl *ctrl,
  1287. u32 pattern)
  1288. {
  1289. struct dp_catalog_private *catalog;
  1290. u32 value = 0x0;
  1291. struct dp_io_data *io_data = NULL;
  1292. if (!ctrl) {
  1293. pr_err("invalid input\n");
  1294. return;
  1295. }
  1296. catalog = dp_catalog_get_priv(ctrl);
  1297. io_data = catalog->io.dp_link;
  1298. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x0);
  1299. switch (pattern) {
  1300. case DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING:
  1301. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x1);
  1302. break;
  1303. case DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT:
  1304. value &= ~(1 << 16);
  1305. dp_write(catalog->exe_mode, io_data,
  1306. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1307. value |= 0xFC;
  1308. dp_write(catalog->exe_mode, io_data,
  1309. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1310. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS, 0x2);
  1311. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x10);
  1312. break;
  1313. case DP_TEST_PHY_PATTERN_PRBS7:
  1314. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x20);
  1315. break;
  1316. case DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN:
  1317. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x40);
  1318. /* 00111110000011111000001111100000 */
  1319. dp_write(catalog->exe_mode, io_data,
  1320. DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0);
  1321. /* 00001111100000111110000011111000 */
  1322. dp_write(catalog->exe_mode, io_data,
  1323. DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8);
  1324. /* 1111100000111110 */
  1325. dp_write(catalog->exe_mode, io_data,
  1326. DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E);
  1327. break;
  1328. case DP_TEST_PHY_PATTERN_CP2520_PATTERN_1:
  1329. value = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1330. value &= ~BIT(4);
  1331. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, value);
  1332. value = BIT(16);
  1333. dp_write(catalog->exe_mode, io_data,
  1334. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1335. value |= 0xFC;
  1336. dp_write(catalog->exe_mode, io_data,
  1337. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1338. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS, 0x2);
  1339. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x10);
  1340. value = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1341. value |= BIT(0);
  1342. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, value);
  1343. break;
  1344. case DP_TEST_PHY_PATTERN_CP2520_PATTERN_3:
  1345. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, 0x11);
  1346. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x8);
  1347. break;
  1348. default:
  1349. pr_debug("No valid test pattern requested: 0x%x\n", pattern);
  1350. return;
  1351. }
  1352. /* Make sure the test pattern is programmed in the hardware */
  1353. wmb();
  1354. }
  1355. static u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog_ctrl *ctrl)
  1356. {
  1357. struct dp_catalog_private *catalog;
  1358. struct dp_io_data *io_data = NULL;
  1359. if (!ctrl) {
  1360. pr_err("invalid input\n");
  1361. return 0;
  1362. }
  1363. catalog = dp_catalog_get_priv(ctrl);
  1364. io_data = catalog->io.dp_link;
  1365. return dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  1366. }
  1367. static void dp_catalog_ctrl_fec_config(struct dp_catalog_ctrl *ctrl,
  1368. bool enable)
  1369. {
  1370. struct dp_catalog_private *catalog;
  1371. struct dp_io_data *io_data = NULL;
  1372. u32 reg;
  1373. if (!ctrl) {
  1374. pr_err("invalid input\n");
  1375. return;
  1376. }
  1377. catalog = dp_catalog_get_priv(ctrl);
  1378. io_data = catalog->io.dp_link;
  1379. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1380. /*
  1381. * fec_en = BIT(12)
  1382. * fec_seq_mode = BIT(22)
  1383. * sde_flush = BIT(23) | BIT(24)
  1384. * fb_boundary_sel = BIT(25)
  1385. */
  1386. if (enable)
  1387. reg |= BIT(12) | BIT(22) | BIT(23) | BIT(24) | BIT(25);
  1388. else
  1389. reg &= ~BIT(12);
  1390. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, reg);
  1391. /* make sure mainlink configuration is updated with fec sequence */
  1392. wmb();
  1393. }
  1394. static int dp_catalog_reg_dump(struct dp_catalog *dp_catalog,
  1395. char *name, u8 **out_buf, u32 *out_buf_len)
  1396. {
  1397. int ret = 0;
  1398. u8 *buf;
  1399. u32 len;
  1400. struct dp_io_data *io_data;
  1401. struct dp_catalog_private *catalog;
  1402. struct dp_parser *parser;
  1403. if (!dp_catalog) {
  1404. pr_err("invalid input\n");
  1405. return -EINVAL;
  1406. }
  1407. catalog = container_of(dp_catalog, struct dp_catalog_private,
  1408. dp_catalog);
  1409. parser = catalog->parser;
  1410. parser->get_io_buf(parser, name);
  1411. io_data = parser->get_io(parser, name);
  1412. if (!io_data) {
  1413. pr_err("IO %s not found\n", name);
  1414. ret = -EINVAL;
  1415. goto end;
  1416. }
  1417. buf = io_data->buf;
  1418. len = io_data->io.len;
  1419. if (!buf || !len) {
  1420. pr_err("no buffer available\n");
  1421. ret = -ENOMEM;
  1422. goto end;
  1423. }
  1424. if (!strcmp(catalog->exe_mode, "hw") ||
  1425. !strcmp(catalog->exe_mode, "all")) {
  1426. u32 i, data;
  1427. u32 const rowsize = 4;
  1428. void __iomem *addr = io_data->io.base;
  1429. memset(buf, 0, len);
  1430. for (i = 0; i < len / rowsize; i++) {
  1431. data = readl_relaxed(addr);
  1432. memcpy(buf + (rowsize * i), &data, sizeof(u32));
  1433. addr += rowsize;
  1434. }
  1435. }
  1436. *out_buf = buf;
  1437. *out_buf_len = len;
  1438. end:
  1439. if (ret)
  1440. parser->clear_io_buf(parser);
  1441. return ret;
  1442. }
  1443. static void dp_catalog_ctrl_mst_config(struct dp_catalog_ctrl *ctrl,
  1444. bool enable)
  1445. {
  1446. struct dp_catalog_private *catalog;
  1447. struct dp_io_data *io_data = NULL;
  1448. u32 reg;
  1449. if (!ctrl) {
  1450. pr_err("invalid input\n");
  1451. return;
  1452. }
  1453. catalog = dp_catalog_get_priv(ctrl);
  1454. io_data = catalog->io.dp_link;
  1455. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1456. if (enable)
  1457. reg |= (0x04000100);
  1458. else
  1459. reg &= ~(0x04000100);
  1460. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, reg);
  1461. /* make sure mainlink MST configuration is updated */
  1462. wmb();
  1463. }
  1464. static void dp_catalog_ctrl_trigger_act(struct dp_catalog_ctrl *ctrl)
  1465. {
  1466. struct dp_catalog_private *catalog;
  1467. struct dp_io_data *io_data = NULL;
  1468. if (!ctrl) {
  1469. pr_err("invalid input\n");
  1470. return;
  1471. }
  1472. catalog = dp_catalog_get_priv(ctrl);
  1473. io_data = catalog->io.dp_link;
  1474. dp_write(catalog->exe_mode, io_data, DP_MST_ACT, 0x1);
  1475. /* make sure ACT signal is performed */
  1476. wmb();
  1477. }
  1478. static void dp_catalog_ctrl_read_act_complete_sts(struct dp_catalog_ctrl *ctrl,
  1479. bool *sts)
  1480. {
  1481. struct dp_catalog_private *catalog;
  1482. struct dp_io_data *io_data = NULL;
  1483. u32 reg;
  1484. if (!ctrl || !sts) {
  1485. pr_err("invalid input\n");
  1486. return;
  1487. }
  1488. *sts = false;
  1489. catalog = dp_catalog_get_priv(ctrl);
  1490. io_data = catalog->io.dp_link;
  1491. reg = dp_read(catalog->exe_mode, io_data, DP_MST_ACT);
  1492. if (!reg)
  1493. *sts = true;
  1494. }
  1495. static void dp_catalog_ctrl_channel_alloc(struct dp_catalog_ctrl *ctrl,
  1496. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1497. {
  1498. struct dp_catalog_private *catalog;
  1499. struct dp_io_data *io_data = NULL;
  1500. u32 i, slot_reg_1, slot_reg_2, slot;
  1501. u32 reg_off = 0;
  1502. int const num_slots_per_reg = 32;
  1503. if (!ctrl || ch >= DP_STREAM_MAX) {
  1504. pr_err("invalid input. ch %d\n", ch);
  1505. return;
  1506. }
  1507. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1508. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1509. pr_err("invalid slots start %d, tot %d\n",
  1510. ch_start_slot, tot_slot_cnt);
  1511. return;
  1512. }
  1513. catalog = dp_catalog_get_priv(ctrl);
  1514. io_data = catalog->io.dp_link;
  1515. pr_debug("ch %d, start_slot %d, tot_slot %d\n",
  1516. ch, ch_start_slot, tot_slot_cnt);
  1517. if (ch == DP_STREAM_1)
  1518. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1519. slot_reg_1 = 0;
  1520. slot_reg_2 = 0;
  1521. if (ch_start_slot && tot_slot_cnt) {
  1522. ch_start_slot--;
  1523. for (i = 0; i < tot_slot_cnt; i++) {
  1524. if (ch_start_slot < num_slots_per_reg) {
  1525. slot_reg_1 |= BIT(ch_start_slot);
  1526. } else {
  1527. slot = ch_start_slot - num_slots_per_reg;
  1528. slot_reg_2 |= BIT(slot);
  1529. }
  1530. ch_start_slot++;
  1531. }
  1532. }
  1533. pr_debug("ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1534. slot_reg_1, slot_reg_2);
  1535. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_1_32 + reg_off,
  1536. slot_reg_1);
  1537. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_33_63 + reg_off,
  1538. slot_reg_2);
  1539. }
  1540. static void dp_catalog_ctrl_channel_dealloc(struct dp_catalog_ctrl *ctrl,
  1541. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1542. {
  1543. struct dp_catalog_private *catalog;
  1544. struct dp_io_data *io_data = NULL;
  1545. u32 i, slot_reg_1, slot_reg_2, slot;
  1546. u32 reg_off = 0;
  1547. if (!ctrl || ch >= DP_STREAM_MAX) {
  1548. pr_err("invalid input. ch %d\n", ch);
  1549. return;
  1550. }
  1551. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1552. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1553. pr_err("invalid slots start %d, tot %d\n",
  1554. ch_start_slot, tot_slot_cnt);
  1555. return;
  1556. }
  1557. catalog = dp_catalog_get_priv(ctrl);
  1558. io_data = catalog->io.dp_link;
  1559. pr_debug("dealloc ch %d, start_slot %d, tot_slot %d\n",
  1560. ch, ch_start_slot, tot_slot_cnt);
  1561. if (ch == DP_STREAM_1)
  1562. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1563. slot_reg_1 = dp_read(catalog->exe_mode, io_data,
  1564. DP_DP0_TIMESLOT_1_32 + reg_off);
  1565. slot_reg_2 = dp_read(catalog->exe_mode, io_data,
  1566. DP_DP0_TIMESLOT_33_63 + reg_off);
  1567. ch_start_slot = ch_start_slot - 1;
  1568. for (i = 0; i < tot_slot_cnt; i++) {
  1569. if (ch_start_slot < 33) {
  1570. slot_reg_1 &= ~BIT(ch_start_slot);
  1571. } else {
  1572. slot = ch_start_slot - 33;
  1573. slot_reg_2 &= ~BIT(slot);
  1574. }
  1575. ch_start_slot++;
  1576. }
  1577. pr_debug("dealloc ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1578. slot_reg_1, slot_reg_2);
  1579. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_1_32 + reg_off,
  1580. slot_reg_1);
  1581. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_33_63 + reg_off,
  1582. slot_reg_2);
  1583. }
  1584. static void dp_catalog_ctrl_update_rg(struct dp_catalog_ctrl *ctrl, u32 ch,
  1585. u32 x_int, u32 y_frac_enum)
  1586. {
  1587. struct dp_catalog_private *catalog;
  1588. struct dp_io_data *io_data = NULL;
  1589. u32 rg, reg_off = 0;
  1590. if (!ctrl || ch >= DP_STREAM_MAX) {
  1591. pr_err("invalid input. ch %d\n", ch);
  1592. return;
  1593. }
  1594. catalog = dp_catalog_get_priv(ctrl);
  1595. io_data = catalog->io.dp_link;
  1596. rg = y_frac_enum;
  1597. rg |= (x_int << 16);
  1598. pr_debug("ch: %d x_int:%d y_frac_enum:%d rg:%d\n", ch, x_int,
  1599. y_frac_enum, rg);
  1600. if (ch == DP_STREAM_1)
  1601. reg_off = DP_DP1_RG - DP_DP0_RG;
  1602. dp_write(catalog->exe_mode, io_data, DP_DP0_RG + reg_off, rg);
  1603. }
  1604. static void dp_catalog_ctrl_mainlink_levels(struct dp_catalog_ctrl *ctrl,
  1605. u8 lane_cnt)
  1606. {
  1607. struct dp_catalog_private *catalog;
  1608. struct dp_io_data *io_data;
  1609. u32 mainlink_levels, safe_to_exit_level = 14;
  1610. catalog = dp_catalog_get_priv(ctrl);
  1611. io_data = catalog->io.dp_link;
  1612. switch (lane_cnt) {
  1613. case 1:
  1614. safe_to_exit_level = 14;
  1615. break;
  1616. case 2:
  1617. safe_to_exit_level = 8;
  1618. break;
  1619. case 4:
  1620. safe_to_exit_level = 5;
  1621. break;
  1622. default:
  1623. pr_debug("setting the default safe_to_exit_level = %u\n",
  1624. safe_to_exit_level);
  1625. break;
  1626. }
  1627. mainlink_levels = dp_read(catalog->exe_mode, io_data,
  1628. DP_MAINLINK_LEVELS);
  1629. mainlink_levels &= 0xFE0;
  1630. mainlink_levels |= safe_to_exit_level;
  1631. pr_debug("mainlink_level = 0x%x, safe_to_exit_level = 0x%x\n",
  1632. mainlink_levels, safe_to_exit_level);
  1633. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS,
  1634. mainlink_levels);
  1635. }
  1636. /* panel related catalog functions */
  1637. static int dp_catalog_panel_timing_cfg(struct dp_catalog_panel *panel)
  1638. {
  1639. struct dp_catalog_private *catalog;
  1640. struct dp_io_data *io_data;
  1641. u32 offset = 0, reg;
  1642. if (!panel) {
  1643. pr_err("invalid input\n");
  1644. goto end;
  1645. }
  1646. if (panel->stream_id >= DP_STREAM_MAX) {
  1647. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1648. goto end;
  1649. }
  1650. catalog = dp_catalog_get_priv(panel);
  1651. io_data = catalog->io.dp_link;
  1652. if (panel->stream_id == DP_STREAM_1)
  1653. offset = DP1_TOTAL_HOR_VER - DP_TOTAL_HOR_VER;
  1654. dp_write(catalog->exe_mode, io_data, DP_TOTAL_HOR_VER + offset,
  1655. panel->total);
  1656. dp_write(catalog->exe_mode, io_data,
  1657. DP_START_HOR_VER_FROM_SYNC + offset, panel->sync_start);
  1658. dp_write(catalog->exe_mode, io_data,
  1659. DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, panel->width_blanking);
  1660. dp_write(catalog->exe_mode, io_data, DP_ACTIVE_HOR_VER + offset,
  1661. panel->dp_active);
  1662. if (panel->stream_id == DP_STREAM_0)
  1663. io_data = catalog->io.dp_p0;
  1664. else
  1665. io_data = catalog->io.dp_p1;
  1666. reg = dp_read(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG);
  1667. if (panel->widebus_en)
  1668. reg |= BIT(4);
  1669. else
  1670. reg &= ~BIT(4);
  1671. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG, reg);
  1672. end:
  1673. return 0;
  1674. }
  1675. static void dp_catalog_hpd_config_hpd(struct dp_catalog_hpd *hpd, bool en)
  1676. {
  1677. struct dp_catalog_private *catalog;
  1678. struct dp_io_data *io_data;
  1679. if (!hpd) {
  1680. pr_err("invalid input\n");
  1681. return;
  1682. }
  1683. catalog = dp_catalog_get_priv(hpd);
  1684. io_data = catalog->io.dp_aux;
  1685. if (en) {
  1686. u32 reftimer = dp_read(catalog->exe_mode, io_data,
  1687. DP_DP_HPD_REFTIMER);
  1688. /* Arm only the UNPLUG and HPD_IRQ interrupts */
  1689. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_ACK, 0xF);
  1690. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_MASK, 0xA);
  1691. /* Enable REFTIMER to count 1ms */
  1692. reftimer |= BIT(16);
  1693. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_REFTIMER,
  1694. reftimer);
  1695. /* Connect_time is 250us & disconnect_time is 2ms */
  1696. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_EVENT_TIME_0,
  1697. 0x3E800FA);
  1698. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_EVENT_TIME_1,
  1699. 0x1F407D0);
  1700. /* Enable HPD */
  1701. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_CTRL, 0x1);
  1702. } else {
  1703. /* Disable HPD */
  1704. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_CTRL, 0x0);
  1705. }
  1706. }
  1707. static u32 dp_catalog_hpd_get_interrupt(struct dp_catalog_hpd *hpd)
  1708. {
  1709. u32 isr = 0;
  1710. struct dp_catalog_private *catalog;
  1711. struct dp_io_data *io_data;
  1712. if (!hpd) {
  1713. pr_err("invalid input\n");
  1714. return isr;
  1715. }
  1716. catalog = dp_catalog_get_priv(hpd);
  1717. io_data = catalog->io.dp_aux;
  1718. isr = dp_read(catalog->exe_mode, io_data, DP_DP_HPD_INT_STATUS);
  1719. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_ACK, (isr & 0xf));
  1720. return isr;
  1721. }
  1722. static void dp_catalog_audio_init(struct dp_catalog_audio *audio)
  1723. {
  1724. struct dp_catalog_private *catalog;
  1725. static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] = {
  1726. {
  1727. MMSS_DP_AUDIO_STREAM_0,
  1728. MMSS_DP_AUDIO_STREAM_1,
  1729. MMSS_DP_AUDIO_STREAM_1,
  1730. },
  1731. {
  1732. MMSS_DP_AUDIO_TIMESTAMP_0,
  1733. MMSS_DP_AUDIO_TIMESTAMP_1,
  1734. MMSS_DP_AUDIO_TIMESTAMP_1,
  1735. },
  1736. {
  1737. MMSS_DP_AUDIO_INFOFRAME_0,
  1738. MMSS_DP_AUDIO_INFOFRAME_1,
  1739. MMSS_DP_AUDIO_INFOFRAME_1,
  1740. },
  1741. {
  1742. MMSS_DP_AUDIO_COPYMANAGEMENT_0,
  1743. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1744. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1745. },
  1746. {
  1747. MMSS_DP_AUDIO_ISRC_0,
  1748. MMSS_DP_AUDIO_ISRC_1,
  1749. MMSS_DP_AUDIO_ISRC_1,
  1750. },
  1751. };
  1752. if (!audio)
  1753. return;
  1754. catalog = dp_catalog_get_priv(audio);
  1755. catalog->audio_map = sdp_map;
  1756. }
  1757. static void dp_catalog_audio_config_sdp(struct dp_catalog_audio *audio)
  1758. {
  1759. struct dp_catalog_private *catalog;
  1760. struct dp_io_data *io_data;
  1761. u32 sdp_cfg = 0, sdp_cfg_off = 0;
  1762. u32 sdp_cfg2 = 0, sdp_cfg2_off = 0;
  1763. if (!audio)
  1764. return;
  1765. if (audio->stream_id >= DP_STREAM_MAX) {
  1766. pr_err("invalid stream id:%d\n", audio->stream_id);
  1767. return;
  1768. }
  1769. if (audio->stream_id == DP_STREAM_1) {
  1770. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  1771. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  1772. }
  1773. catalog = dp_catalog_get_priv(audio);
  1774. io_data = catalog->io.dp_link;
  1775. sdp_cfg = dp_read(catalog->exe_mode, io_data,
  1776. MMSS_DP_SDP_CFG + sdp_cfg_off);
  1777. /* AUDIO_TIMESTAMP_SDP_EN */
  1778. sdp_cfg |= BIT(1);
  1779. /* AUDIO_STREAM_SDP_EN */
  1780. sdp_cfg |= BIT(2);
  1781. /* AUDIO_COPY_MANAGEMENT_SDP_EN */
  1782. sdp_cfg |= BIT(5);
  1783. /* AUDIO_ISRC_SDP_EN */
  1784. sdp_cfg |= BIT(6);
  1785. /* AUDIO_INFOFRAME_SDP_EN */
  1786. sdp_cfg |= BIT(20);
  1787. pr_debug("sdp_cfg = 0x%x\n", sdp_cfg);
  1788. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG + sdp_cfg_off,
  1789. sdp_cfg);
  1790. sdp_cfg2 = dp_read(catalog->exe_mode, io_data,
  1791. MMSS_DP_SDP_CFG2 + sdp_cfg_off);
  1792. /* IFRM_REGSRC -> Do not use reg values */
  1793. sdp_cfg2 &= ~BIT(0);
  1794. /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */
  1795. sdp_cfg2 &= ~BIT(1);
  1796. pr_debug("sdp_cfg2 = 0x%x\n", sdp_cfg2);
  1797. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg_off,
  1798. sdp_cfg2);
  1799. }
  1800. static void dp_catalog_audio_get_header(struct dp_catalog_audio *audio)
  1801. {
  1802. struct dp_catalog_private *catalog;
  1803. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  1804. struct dp_io_data *io_data;
  1805. enum dp_catalog_audio_sdp_type sdp;
  1806. enum dp_catalog_audio_header_type header;
  1807. if (!audio)
  1808. return;
  1809. catalog = dp_catalog_get_priv(audio);
  1810. io_data = catalog->io.dp_link;
  1811. sdp_map = catalog->audio_map;
  1812. sdp = audio->sdp_type;
  1813. header = audio->sdp_header;
  1814. audio->data = dp_read(catalog->exe_mode, io_data, sdp_map[sdp][header]);
  1815. }
  1816. static void dp_catalog_audio_set_header(struct dp_catalog_audio *audio)
  1817. {
  1818. struct dp_catalog_private *catalog;
  1819. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  1820. struct dp_io_data *io_data;
  1821. enum dp_catalog_audio_sdp_type sdp;
  1822. enum dp_catalog_audio_header_type header;
  1823. u32 data;
  1824. if (!audio)
  1825. return;
  1826. catalog = dp_catalog_get_priv(audio);
  1827. io_data = catalog->io.dp_link;
  1828. sdp_map = catalog->audio_map;
  1829. sdp = audio->sdp_type;
  1830. header = audio->sdp_header;
  1831. data = audio->data;
  1832. dp_write(catalog->exe_mode, io_data, sdp_map[sdp][header], data);
  1833. }
  1834. static void dp_catalog_audio_config_acr(struct dp_catalog_audio *audio)
  1835. {
  1836. struct dp_catalog_private *catalog;
  1837. struct dp_io_data *io_data;
  1838. u32 acr_ctrl, select;
  1839. catalog = dp_catalog_get_priv(audio);
  1840. select = audio->data;
  1841. io_data = catalog->io.dp_link;
  1842. acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
  1843. pr_debug("select = 0x%x, acr_ctrl = 0x%x\n", select, acr_ctrl);
  1844. dp_write(catalog->exe_mode, io_data, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
  1845. }
  1846. static void dp_catalog_audio_enable(struct dp_catalog_audio *audio)
  1847. {
  1848. struct dp_catalog_private *catalog;
  1849. struct dp_io_data *io_data;
  1850. bool enable;
  1851. u32 audio_ctrl;
  1852. catalog = dp_catalog_get_priv(audio);
  1853. io_data = catalog->io.dp_link;
  1854. enable = !!audio->data;
  1855. audio_ctrl = dp_read(catalog->exe_mode, io_data, MMSS_DP_AUDIO_CFG);
  1856. if (enable)
  1857. audio_ctrl |= BIT(0);
  1858. else
  1859. audio_ctrl &= ~BIT(0);
  1860. pr_debug("dp_audio_cfg = 0x%x\n", audio_ctrl);
  1861. dp_write(catalog->exe_mode, io_data, MMSS_DP_AUDIO_CFG, audio_ctrl);
  1862. /* make sure audio engine is disabled */
  1863. wmb();
  1864. }
  1865. static void dp_catalog_config_spd_header(struct dp_catalog_panel *panel)
  1866. {
  1867. struct dp_catalog_private *catalog;
  1868. struct dp_io_data *io_data;
  1869. u32 value, new_value, offset = 0;
  1870. u8 parity_byte;
  1871. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  1872. return;
  1873. catalog = dp_catalog_get_priv(panel);
  1874. io_data = catalog->io.dp_link;
  1875. if (panel->stream_id == DP_STREAM_1)
  1876. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  1877. /* Config header and parity byte 1 */
  1878. value = dp_read(catalog->exe_mode, io_data,
  1879. MMSS_DP_GENERIC1_0 + offset);
  1880. new_value = 0x83;
  1881. parity_byte = dp_header_get_parity(new_value);
  1882. value |= ((new_value << HEADER_BYTE_1_BIT)
  1883. | (parity_byte << PARITY_BYTE_1_BIT));
  1884. pr_debug("Header Byte 1: value = 0x%x, parity_byte = 0x%x\n",
  1885. value, parity_byte);
  1886. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_0 + offset,
  1887. value);
  1888. /* Config header and parity byte 2 */
  1889. value = dp_read(catalog->exe_mode, io_data,
  1890. MMSS_DP_GENERIC1_1 + offset);
  1891. new_value = 0x1b;
  1892. parity_byte = dp_header_get_parity(new_value);
  1893. value |= ((new_value << HEADER_BYTE_2_BIT)
  1894. | (parity_byte << PARITY_BYTE_2_BIT));
  1895. pr_debug("Header Byte 2: value = 0x%x, parity_byte = 0x%x\n",
  1896. value, parity_byte);
  1897. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_1 + offset,
  1898. value);
  1899. /* Config header and parity byte 3 */
  1900. value = dp_read(catalog->exe_mode, io_data,
  1901. MMSS_DP_GENERIC1_1 + offset);
  1902. new_value = (0x0 | (0x12 << 2));
  1903. parity_byte = dp_header_get_parity(new_value);
  1904. value |= ((new_value << HEADER_BYTE_3_BIT)
  1905. | (parity_byte << PARITY_BYTE_3_BIT));
  1906. pr_debug("Header Byte 3: value = 0x%x, parity_byte = 0x%x\n",
  1907. new_value, parity_byte);
  1908. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_1 + offset,
  1909. value);
  1910. }
  1911. static void dp_catalog_panel_config_spd(struct dp_catalog_panel *panel)
  1912. {
  1913. struct dp_catalog_private *catalog;
  1914. struct dp_io_data *io_data;
  1915. u32 spd_cfg = 0, spd_cfg2 = 0;
  1916. u8 *vendor = NULL, *product = NULL;
  1917. u32 offset = 0;
  1918. u32 sdp_cfg_off = 0;
  1919. u32 sdp_cfg2_off = 0;
  1920. u32 sdp_cfg3_off = 0;
  1921. /*
  1922. * Source Device Information
  1923. * 00h unknown
  1924. * 01h Digital STB
  1925. * 02h DVD
  1926. * 03h D-VHS
  1927. * 04h HDD Video
  1928. * 05h DVC
  1929. * 06h DSC
  1930. * 07h Video CD
  1931. * 08h Game
  1932. * 09h PC general
  1933. * 0ah Bluray-Disc
  1934. * 0bh Super Audio CD
  1935. * 0ch HD DVD
  1936. * 0dh PMP
  1937. * 0eh-ffh reserved
  1938. */
  1939. u32 device_type = 0;
  1940. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  1941. return;
  1942. catalog = dp_catalog_get_priv(panel);
  1943. io_data = catalog->io.dp_link;
  1944. if (panel->stream_id == DP_STREAM_1)
  1945. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  1946. dp_catalog_config_spd_header(panel);
  1947. vendor = panel->spd_vendor_name;
  1948. product = panel->spd_product_description;
  1949. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_2 + offset,
  1950. ((vendor[0] & 0x7f) |
  1951. ((vendor[1] & 0x7f) << 8) |
  1952. ((vendor[2] & 0x7f) << 16) |
  1953. ((vendor[3] & 0x7f) << 24)));
  1954. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_3 + offset,
  1955. ((vendor[4] & 0x7f) |
  1956. ((vendor[5] & 0x7f) << 8) |
  1957. ((vendor[6] & 0x7f) << 16) |
  1958. ((vendor[7] & 0x7f) << 24)));
  1959. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_4 + offset,
  1960. ((product[0] & 0x7f) |
  1961. ((product[1] & 0x7f) << 8) |
  1962. ((product[2] & 0x7f) << 16) |
  1963. ((product[3] & 0x7f) << 24)));
  1964. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_5 + offset,
  1965. ((product[4] & 0x7f) |
  1966. ((product[5] & 0x7f) << 8) |
  1967. ((product[6] & 0x7f) << 16) |
  1968. ((product[7] & 0x7f) << 24)));
  1969. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_6 + offset,
  1970. ((product[8] & 0x7f) |
  1971. ((product[9] & 0x7f) << 8) |
  1972. ((product[10] & 0x7f) << 16) |
  1973. ((product[11] & 0x7f) << 24)));
  1974. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_7 + offset,
  1975. ((product[12] & 0x7f) |
  1976. ((product[13] & 0x7f) << 8) |
  1977. ((product[14] & 0x7f) << 16) |
  1978. ((product[15] & 0x7f) << 24)));
  1979. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_8 + offset,
  1980. device_type);
  1981. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_9 + offset, 0x00);
  1982. if (panel->stream_id == DP_STREAM_1) {
  1983. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  1984. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  1985. sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
  1986. }
  1987. spd_cfg = dp_read(catalog->exe_mode, io_data,
  1988. MMSS_DP_SDP_CFG + sdp_cfg_off);
  1989. /* GENERIC1_SDP for SPD Infoframe */
  1990. spd_cfg |= BIT(18);
  1991. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG + sdp_cfg_off,
  1992. spd_cfg);
  1993. spd_cfg2 = dp_read(catalog->exe_mode, io_data,
  1994. MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  1995. /* 28 data bytes for SPD Infoframe with GENERIC1 set */
  1996. spd_cfg2 |= BIT(17);
  1997. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg2_off,
  1998. spd_cfg2);
  1999. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  2000. 0x1);
  2001. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  2002. 0x0);
  2003. }
  2004. static void dp_catalog_get_io_buf(struct dp_catalog_private *catalog)
  2005. {
  2006. struct dp_parser *parser = catalog->parser;
  2007. dp_catalog_fill_io_buf(dp_ahb);
  2008. dp_catalog_fill_io_buf(dp_aux);
  2009. dp_catalog_fill_io_buf(dp_link);
  2010. dp_catalog_fill_io_buf(dp_p0);
  2011. dp_catalog_fill_io_buf(dp_phy);
  2012. dp_catalog_fill_io_buf(dp_ln_tx0);
  2013. dp_catalog_fill_io_buf(dp_ln_tx1);
  2014. dp_catalog_fill_io_buf(dp_pll);
  2015. dp_catalog_fill_io_buf(usb3_dp_com);
  2016. dp_catalog_fill_io_buf(dp_mmss_cc);
  2017. dp_catalog_fill_io_buf(hdcp_physical);
  2018. dp_catalog_fill_io_buf(dp_p1);
  2019. dp_catalog_fill_io_buf(dp_tcsr);
  2020. }
  2021. static void dp_catalog_get_io(struct dp_catalog_private *catalog)
  2022. {
  2023. struct dp_parser *parser = catalog->parser;
  2024. dp_catalog_fill_io(dp_ahb);
  2025. dp_catalog_fill_io(dp_aux);
  2026. dp_catalog_fill_io(dp_link);
  2027. dp_catalog_fill_io(dp_p0);
  2028. dp_catalog_fill_io(dp_phy);
  2029. dp_catalog_fill_io(dp_ln_tx0);
  2030. dp_catalog_fill_io(dp_ln_tx1);
  2031. dp_catalog_fill_io(dp_pll);
  2032. dp_catalog_fill_io(usb3_dp_com);
  2033. dp_catalog_fill_io(dp_mmss_cc);
  2034. dp_catalog_fill_io(hdcp_physical);
  2035. dp_catalog_fill_io(dp_p1);
  2036. dp_catalog_fill_io(dp_tcsr);
  2037. }
  2038. static void dp_catalog_set_exe_mode(struct dp_catalog *dp_catalog, char *mode)
  2039. {
  2040. struct dp_catalog_private *catalog;
  2041. if (!dp_catalog) {
  2042. pr_err("invalid input\n");
  2043. return;
  2044. }
  2045. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2046. dp_catalog);
  2047. strlcpy(catalog->exe_mode, mode, sizeof(catalog->exe_mode));
  2048. if (!strcmp(catalog->exe_mode, "hw"))
  2049. catalog->parser->clear_io_buf(catalog->parser);
  2050. else
  2051. dp_catalog_get_io_buf(catalog);
  2052. if (dp_catalog->priv.data && dp_catalog->priv.put)
  2053. dp_catalog->priv.set_exe_mode(dp_catalog, mode);
  2054. }
  2055. static int dp_catalog_init(struct device *dev, struct dp_catalog *catalog,
  2056. struct dp_parser *parser)
  2057. {
  2058. int rc = 0;
  2059. struct dp_catalog_private *catalog_priv;
  2060. catalog_priv = container_of(catalog, struct dp_catalog_private,
  2061. dp_catalog);
  2062. if (parser->hw_cfg.phy_version == DP_PHY_VERSION_4_2_0)
  2063. rc = dp_catalog_get_v420(dev, catalog, &catalog_priv->io);
  2064. else if (parser->hw_cfg.phy_version == DP_PHY_VERSION_2_0_0)
  2065. rc = dp_catalog_get_v200(dev, catalog, &catalog_priv->io);
  2066. return rc;
  2067. }
  2068. void dp_catalog_put(struct dp_catalog *dp_catalog)
  2069. {
  2070. struct dp_catalog_private *catalog;
  2071. if (!dp_catalog)
  2072. return;
  2073. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2074. dp_catalog);
  2075. if (dp_catalog->priv.data && dp_catalog->priv.put)
  2076. dp_catalog->priv.put(dp_catalog);
  2077. catalog->parser->clear_io_buf(catalog->parser);
  2078. devm_kfree(catalog->dev, catalog);
  2079. }
  2080. struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser)
  2081. {
  2082. int rc = 0;
  2083. struct dp_catalog *dp_catalog;
  2084. struct dp_catalog_private *catalog;
  2085. struct dp_catalog_aux aux = {
  2086. .read_data = dp_catalog_aux_read_data,
  2087. .write_data = dp_catalog_aux_write_data,
  2088. .write_trans = dp_catalog_aux_write_trans,
  2089. .clear_trans = dp_catalog_aux_clear_trans,
  2090. .reset = dp_catalog_aux_reset,
  2091. .update_aux_cfg = dp_catalog_aux_update_cfg,
  2092. .enable = dp_catalog_aux_enable,
  2093. .setup = dp_catalog_aux_setup,
  2094. .get_irq = dp_catalog_aux_get_irq,
  2095. .clear_hw_interrupts = dp_catalog_aux_clear_hw_interrupts,
  2096. };
  2097. struct dp_catalog_ctrl ctrl = {
  2098. .state_ctrl = dp_catalog_ctrl_state_ctrl,
  2099. .config_ctrl = dp_catalog_ctrl_config_ctrl,
  2100. .lane_mapping = dp_catalog_ctrl_lane_mapping,
  2101. .lane_pnswap = dp_catalog_ctrl_lane_pnswap,
  2102. .mainlink_ctrl = dp_catalog_ctrl_mainlink_ctrl,
  2103. .set_pattern = dp_catalog_ctrl_set_pattern,
  2104. .reset = dp_catalog_ctrl_reset,
  2105. .usb_reset = dp_catalog_ctrl_usb_reset,
  2106. .mainlink_ready = dp_catalog_ctrl_mainlink_ready,
  2107. .enable_irq = dp_catalog_ctrl_enable_irq,
  2108. .phy_reset = dp_catalog_ctrl_phy_reset,
  2109. .phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg,
  2110. .update_vx_px = dp_catalog_ctrl_update_vx_px,
  2111. .get_interrupt = dp_catalog_ctrl_get_interrupt,
  2112. .read_hdcp_status = dp_catalog_ctrl_read_hdcp_status,
  2113. .send_phy_pattern = dp_catalog_ctrl_send_phy_pattern,
  2114. .read_phy_pattern = dp_catalog_ctrl_read_phy_pattern,
  2115. .mst_config = dp_catalog_ctrl_mst_config,
  2116. .trigger_act = dp_catalog_ctrl_trigger_act,
  2117. .read_act_complete_sts = dp_catalog_ctrl_read_act_complete_sts,
  2118. .channel_alloc = dp_catalog_ctrl_channel_alloc,
  2119. .update_rg = dp_catalog_ctrl_update_rg,
  2120. .channel_dealloc = dp_catalog_ctrl_channel_dealloc,
  2121. .fec_config = dp_catalog_ctrl_fec_config,
  2122. .mainlink_levels = dp_catalog_ctrl_mainlink_levels,
  2123. };
  2124. struct dp_catalog_hpd hpd = {
  2125. .config_hpd = dp_catalog_hpd_config_hpd,
  2126. .get_interrupt = dp_catalog_hpd_get_interrupt,
  2127. };
  2128. struct dp_catalog_audio audio = {
  2129. .init = dp_catalog_audio_init,
  2130. .config_acr = dp_catalog_audio_config_acr,
  2131. .enable = dp_catalog_audio_enable,
  2132. .config_sdp = dp_catalog_audio_config_sdp,
  2133. .set_header = dp_catalog_audio_set_header,
  2134. .get_header = dp_catalog_audio_get_header,
  2135. };
  2136. struct dp_catalog_panel panel = {
  2137. .timing_cfg = dp_catalog_panel_timing_cfg,
  2138. .config_hdr = dp_catalog_panel_config_hdr,
  2139. .tpg_config = dp_catalog_panel_tpg_cfg,
  2140. .config_spd = dp_catalog_panel_config_spd,
  2141. .config_misc = dp_catalog_panel_config_misc,
  2142. .config_msa = dp_catalog_panel_config_msa,
  2143. .update_transfer_unit = dp_catalog_panel_update_transfer_unit,
  2144. .config_ctrl = dp_catalog_panel_config_ctrl,
  2145. .config_dto = dp_catalog_panel_config_dto,
  2146. .dsc_cfg = dp_catalog_panel_dsc_cfg,
  2147. .pps_flush = dp_catalog_panel_pps_flush,
  2148. .dhdr_flush = dp_catalog_panel_dhdr_flush,
  2149. .dhdr_busy = dp_catalog_panel_dhdr_busy,
  2150. };
  2151. if (!dev || !parser) {
  2152. pr_err("invalid input\n");
  2153. rc = -EINVAL;
  2154. goto error;
  2155. }
  2156. catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL);
  2157. if (!catalog) {
  2158. rc = -ENOMEM;
  2159. goto error;
  2160. }
  2161. catalog->dev = dev;
  2162. catalog->parser = parser;
  2163. dp_catalog_get_io(catalog);
  2164. strlcpy(catalog->exe_mode, "hw", sizeof(catalog->exe_mode));
  2165. dp_catalog = &catalog->dp_catalog;
  2166. dp_catalog->aux = aux;
  2167. dp_catalog->ctrl = ctrl;
  2168. dp_catalog->hpd = hpd;
  2169. dp_catalog->audio = audio;
  2170. dp_catalog->panel = panel;
  2171. rc = dp_catalog_init(dev, dp_catalog, parser);
  2172. if (rc) {
  2173. dp_catalog_put(dp_catalog);
  2174. goto error;
  2175. }
  2176. dp_catalog->set_exe_mode = dp_catalog_set_exe_mode;
  2177. dp_catalog->get_reg_dump = dp_catalog_reg_dump;
  2178. return dp_catalog;
  2179. error:
  2180. return ERR_PTR(rc);
  2181. }