31d659e7e7
Changes to incorporate the different clock names for lito and kona. Change-Id: I607366f75426a819226aa252819b507dba07109d Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
425 行
10 KiB
C
425 行
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "pll_drv.h"
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#include "dsi_pll.h"
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#include "dp_pll.h"
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#include "hdmi_pll.h"
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int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable)
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{
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int rc = 0;
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int changed = 0;
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if (!pll_res) {
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pr_err("Invalid input parameters\n");
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return -EINVAL;
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}
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/*
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* Don't turn off resources during handoff or add more than
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* 1 refcount.
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*/
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if (pll_res->handoff_resources &&
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(!enable || (enable & pll_res->resource_enable))) {
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pr_debug("Do not turn on/off pll resources during handoff case\n");
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return rc;
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}
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if (enable) {
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if (pll_res->resource_ref_cnt == 0)
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changed++;
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pll_res->resource_ref_cnt++;
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} else {
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if (pll_res->resource_ref_cnt) {
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pll_res->resource_ref_cnt--;
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if (pll_res->resource_ref_cnt == 0)
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changed++;
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} else {
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pr_err("PLL Resources already OFF\n");
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}
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}
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if (changed) {
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rc = mdss_pll_util_resource_enable(pll_res, enable);
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if (rc)
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pr_err("Resource update failed rc=%d\n", rc);
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else
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pll_res->resource_enable = enable;
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}
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return rc;
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}
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static int mdss_pll_resource_init(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int rc = 0;
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struct dss_module_power *mp = &pll_res->mp;
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rc = msm_dss_config_vreg(&pdev->dev,
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mp->vreg_config, mp->num_vreg, 1);
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if (rc) {
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pr_err("Vreg config failed rc=%d\n", rc);
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goto vreg_err;
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}
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rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
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if (rc) {
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pr_err("Clock get failed rc=%d\n", rc);
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goto clk_err;
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}
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return rc;
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clk_err:
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msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
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vreg_err:
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return rc;
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}
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static void mdss_pll_resource_deinit(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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struct dss_module_power *mp = &pll_res->mp;
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msm_dss_put_clk(mp->clk_config, mp->num_clk);
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msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
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}
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static void mdss_pll_resource_release(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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struct dss_module_power *mp = &pll_res->mp;
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mp->num_vreg = 0;
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mp->num_clk = 0;
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}
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static int mdss_pll_resource_parse(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int rc = 0;
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const char *compatible_stream;
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rc = mdss_pll_util_resource_parse(pdev, pll_res);
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if (rc) {
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pr_err("Failed to parse the resources rc=%d\n", rc);
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goto end;
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}
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compatible_stream = of_get_property(pdev->dev.of_node,
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"compatible", NULL);
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if (!compatible_stream) {
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pr_err("Failed to parse the compatible stream\n");
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goto err;
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}
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if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_10nm"))
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pll_res->pll_interface_type = MDSS_DSI_PLL_10NM;
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if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_10nm"))
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pll_res->pll_interface_type = MDSS_DP_PLL_10NM;
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else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_7nm"))
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pll_res->pll_interface_type = MDSS_DP_PLL_7NM;
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else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_7nm_v2"))
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pll_res->pll_interface_type = MDSS_DP_PLL_7NM_V2;
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else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm"))
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pll_res->pll_interface_type = MDSS_DSI_PLL_7NM;
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else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm_v2"))
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pll_res->pll_interface_type = MDSS_DSI_PLL_7NM_V2;
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else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm_v4_1"))
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pll_res->pll_interface_type = MDSS_DSI_PLL_7NM_V4_1;
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else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_28lpm"))
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pll_res->pll_interface_type = MDSS_DSI_PLL_28LPM;
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else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_14nm"))
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pll_res->pll_interface_type = MDSS_DSI_PLL_14NM;
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else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_14nm"))
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pll_res->pll_interface_type = MDSS_DP_PLL_14NM;
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else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_28lpm"))
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pll_res->pll_interface_type = MDSS_HDMI_PLL_28LPM;
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else
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goto err;
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return rc;
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err:
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mdss_pll_resource_release(pdev, pll_res);
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end:
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return rc;
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}
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static int mdss_pll_clock_register(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int rc;
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switch (pll_res->pll_interface_type) {
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case MDSS_DSI_PLL_10NM:
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rc = dsi_pll_clock_register_10nm(pdev, pll_res);
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break;
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case MDSS_DP_PLL_10NM:
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rc = dp_pll_clock_register_10nm(pdev, pll_res);
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break;
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case MDSS_DSI_PLL_7NM:
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case MDSS_DSI_PLL_7NM_V2:
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case MDSS_DSI_PLL_7NM_V4_1:
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rc = dsi_pll_clock_register_7nm(pdev, pll_res);
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break;
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case MDSS_DP_PLL_7NM:
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case MDSS_DP_PLL_7NM_V2:
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rc = dp_pll_clock_register_7nm(pdev, pll_res);
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break;
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case MDSS_DSI_PLL_28LPM:
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rc = dsi_pll_clock_register_28lpm(pdev, pll_res);
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break;
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case MDSS_DSI_PLL_14NM:
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rc = dsi_pll_clock_register_14nm(pdev, pll_res);
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break;
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case MDSS_DP_PLL_14NM:
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rc = dp_pll_clock_register_14nm(pdev, pll_res);
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break;
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case MDSS_HDMI_PLL_28LPM:
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rc = hdmi_pll_clock_register_28lpm(pdev, pll_res);
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break;
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case MDSS_UNKNOWN_PLL:
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default:
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rc = -EINVAL;
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break;
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}
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if (rc)
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pr_err("Pll ndx=%d clock register failed rc=%d\n",
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pll_res->index, rc);
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return rc;
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}
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static inline int mdss_pll_get_ioresurces(struct platform_device *pdev,
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void __iomem **regmap, char *resource_name)
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{
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int rc = 0;
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struct resource *rsc = platform_get_resource_byname(pdev,
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IORESOURCE_MEM, resource_name);
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if (rsc) {
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if (!regmap)
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return -ENOMEM;
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*regmap = devm_ioremap(&pdev->dev,
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rsc->start, resource_size(rsc));
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if (!*regmap)
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return -ENOMEM;
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}
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return rc;
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}
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static int mdss_pll_probe(struct platform_device *pdev)
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{
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int rc = 0;
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const char *label;
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struct mdss_pll_resources *pll_res;
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if (!pdev->dev.of_node) {
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pr_err("MDSS pll driver only supports device tree probe\n");
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return -ENOTSUPP;
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}
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label = of_get_property(pdev->dev.of_node, "label", NULL);
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if (!label)
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pr_info("MDSS pll label not specified\n");
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else
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pr_info("MDSS pll label = %s\n", label);
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pll_res = devm_kzalloc(&pdev->dev, sizeof(struct mdss_pll_resources),
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GFP_KERNEL);
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if (!pll_res)
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return -ENOMEM;
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platform_set_drvdata(pdev, pll_res);
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rc = of_property_read_u32(pdev->dev.of_node, "cell-index",
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&pll_res->index);
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if (rc) {
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pr_err("Unable to get the cell-index rc=%d\n", rc);
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pll_res->index = 0;
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}
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pll_res->ssc_en = of_property_read_bool(pdev->dev.of_node,
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"qcom,dsi-pll-ssc-en");
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if (pll_res->ssc_en) {
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pr_info("%s: label=%s PLL SSC enabled\n", __func__, label);
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rc = of_property_read_u32(pdev->dev.of_node,
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"qcom,ssc-frequency-hz", &pll_res->ssc_freq);
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rc = of_property_read_u32(pdev->dev.of_node,
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"qcom,ssc-ppm", &pll_res->ssc_ppm);
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pll_res->ssc_center = false;
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label = of_get_property(pdev->dev.of_node,
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"qcom,dsi-pll-ssc-mode", NULL);
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if (label && !strcmp(label, "center-spread"))
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pll_res->ssc_center = true;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->pll_base, "pll_base")) {
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pr_err("Unable to remap pll base resources\n");
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return -ENOMEM;
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}
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pr_debug("%s: ndx=%d base=%p\n", __func__,
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pll_res->index, pll_res->pll_base);
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rc = mdss_pll_resource_parse(pdev, pll_res);
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if (rc) {
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pr_err("Pll resource parsing from dt failed rc=%d\n", rc);
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return rc;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->phy_base, "phy_base")) {
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pr_err("Unable to remap pll phy base resources\n");
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return -ENOMEM;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->dyn_pll_base,
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"dynamic_pll_base")) {
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pr_err("Unable to remap dynamic pll base resources\n");
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return -ENOMEM;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->ln_tx0_base,
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"ln_tx0_base")) {
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pr_err("Unable to remap Lane TX0 base resources\n");
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return -ENOMEM;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->ln_tx0_tran_base,
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"ln_tx0_tran_base")) {
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pr_err("Unable to remap Lane TX0 base resources\n");
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return -ENOMEM;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->ln_tx0_vmode_base,
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"ln_tx0_vmode_base")) {
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pr_err("Unable to remap Lane TX0 base resources\n");
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return -ENOMEM;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->ln_tx1_base,
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"ln_tx1_base")) {
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pr_err("Unable to remap Lane TX1 base resources\n");
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return -ENOMEM;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->ln_tx1_tran_base,
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"ln_tx1_tran_base")) {
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pr_err("Unable to remap Lane TX1 base resources\n");
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return -ENOMEM;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->ln_tx1_vmode_base,
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"ln_tx1_vmode_base")) {
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pr_err("Unable to remap Lane TX1 base resources\n");
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return -ENOMEM;
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}
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if (mdss_pll_get_ioresurces(pdev, &pll_res->gdsc_base, "gdsc_base")) {
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pr_err("Unable to remap gdsc base resources\n");
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return -ENOMEM;
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}
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rc = mdss_pll_resource_init(pdev, pll_res);
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if (rc) {
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pr_err("Pll ndx=%d resource init failed rc=%d\n",
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pll_res->index, rc);
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return rc;
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}
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rc = mdss_pll_clock_register(pdev, pll_res);
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if (rc) {
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pr_err("Pll ndx=%d clock register failed rc=%d\n",
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pll_res->index, rc);
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goto clock_register_error;
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}
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return rc;
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clock_register_error:
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mdss_pll_resource_deinit(pdev, pll_res);
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return rc;
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}
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static int mdss_pll_remove(struct platform_device *pdev)
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{
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struct mdss_pll_resources *pll_res;
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pll_res = platform_get_drvdata(pdev);
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if (!pll_res) {
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pr_err("Invalid PLL resource data\n");
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return 0;
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}
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mdss_pll_resource_deinit(pdev, pll_res);
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mdss_pll_resource_release(pdev, pll_res);
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return 0;
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}
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static const struct of_device_id mdss_pll_dt_match[] = {
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{.compatible = "qcom,mdss_dsi_pll_10nm"},
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{.compatible = "qcom,mdss_dp_pll_10nm"},
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{.compatible = "qcom,mdss_dsi_pll_7nm"},
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{.compatible = "qcom,mdss_dsi_pll_7nm_v2"},
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{.compatible = "qcom,mdss_dsi_pll_7nm_v4_1"},
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{.compatible = "qcom,mdss_dp_pll_7nm"},
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{.compatible = "qcom,mdss_dp_pll_7nm_v2"},
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{.compatible = "qcom,mdss_dsi_pll_28lpm"},
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{.compatible = "qcom,mdss_dsi_pll_14nm"},
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{.compatible = "qcom,mdss_dp_pll_14nm"},
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{},
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};
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MODULE_DEVICE_TABLE(of, mdss_clock_dt_match);
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static struct platform_driver mdss_pll_driver = {
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.probe = mdss_pll_probe,
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.remove = mdss_pll_remove,
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.driver = {
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.name = "mdss_pll",
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.of_match_table = mdss_pll_dt_match,
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},
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};
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static int __init mdss_pll_driver_init(void)
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{
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int rc;
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rc = platform_driver_register(&mdss_pll_driver);
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if (rc)
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pr_err("mdss_register_pll_driver() failed!\n");
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return rc;
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}
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fs_initcall(mdss_pll_driver_init);
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static void __exit mdss_pll_driver_deinit(void)
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{
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platform_driver_unregister(&mdss_pll_driver);
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}
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module_exit(mdss_pll_driver_deinit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("mdss pll driver");
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