dsi_display.c 194 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define DSI_CLOCK_BITRATE_RADIX 10
  28. #define MAX_TE_SOURCE_ID 2
  29. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  30. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  31. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  32. {.boot_param = dsi_display_primary},
  33. {.boot_param = dsi_display_secondary},
  34. };
  35. static const struct of_device_id dsi_display_dt_match[] = {
  36. {.compatible = "qcom,dsi-display"},
  37. {}
  38. };
  39. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  40. u32 mask, bool enable)
  41. {
  42. int i;
  43. struct dsi_display_ctrl *ctrl;
  44. if (!display)
  45. return;
  46. display_for_each_ctrl(i, display) {
  47. ctrl = &display->ctrl[i];
  48. if (!ctrl)
  49. continue;
  50. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  51. }
  52. }
  53. static int dsi_display_config_clk_gating(struct dsi_display *display,
  54. bool enable)
  55. {
  56. int rc = 0, i = 0;
  57. struct dsi_display_ctrl *mctrl, *ctrl;
  58. enum dsi_clk_gate_type clk_selection;
  59. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  60. if (!display) {
  61. DSI_ERR("Invalid params\n");
  62. return -EINVAL;
  63. }
  64. if (display->panel->host_config.force_hs_clk_lane) {
  65. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  66. return 0;
  67. }
  68. mctrl = &display->ctrl[display->clk_master_idx];
  69. if (!mctrl) {
  70. DSI_ERR("Invalid controller\n");
  71. return -EINVAL;
  72. }
  73. clk_selection = display->clk_gating_config;
  74. if (!enable) {
  75. /* for disable path, make sure to disable all clk gating */
  76. clk_selection = DSI_CLK_ALL;
  77. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  78. /* Default selection, no overrides */
  79. clk_selection = default_clk_select;
  80. } else if (clk_selection == DSI_CLK_NONE) {
  81. clk_selection = 0;
  82. }
  83. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  84. enable ? "Enabling" : "Disabling",
  85. clk_selection & BYTE_CLK ? "yes" : "no",
  86. clk_selection & PIXEL_CLK ? "yes" : "no",
  87. clk_selection & DSI_PHY ? "yes" : "no");
  88. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  89. if (rc) {
  90. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  91. display->name, enable ? "enable" : "disable",
  92. clk_selection, rc);
  93. return rc;
  94. }
  95. display_for_each_ctrl(i, display) {
  96. ctrl = &display->ctrl[i];
  97. if (!ctrl->ctrl || (ctrl == mctrl))
  98. continue;
  99. /**
  100. * In Split DSI usecase we should not enable clock gating on
  101. * DSI PHY1 to ensure no display atrifacts are seen.
  102. */
  103. clk_selection &= ~DSI_PHY;
  104. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  105. clk_selection);
  106. if (rc) {
  107. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  108. display->name, enable ? "enable" : "disable",
  109. clk_selection, rc);
  110. return rc;
  111. }
  112. }
  113. return 0;
  114. }
  115. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  116. bool enable)
  117. {
  118. int i;
  119. struct dsi_display_ctrl *ctrl;
  120. if (!display)
  121. return;
  122. display_for_each_ctrl(i, display) {
  123. ctrl = &display->ctrl[i];
  124. if (!ctrl)
  125. continue;
  126. ctrl->ctrl->esd_check_underway = enable;
  127. }
  128. }
  129. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  130. {
  131. int i;
  132. struct dsi_display_ctrl *ctrl;
  133. if (!display)
  134. return;
  135. display_for_each_ctrl(i, display) {
  136. ctrl = &display->ctrl[i];
  137. if (!ctrl)
  138. continue;
  139. dsi_ctrl_irq_update(ctrl->ctrl, en);
  140. }
  141. }
  142. void dsi_rect_intersect(const struct dsi_rect *r1,
  143. const struct dsi_rect *r2,
  144. struct dsi_rect *result)
  145. {
  146. int l, t, r, b;
  147. if (!r1 || !r2 || !result)
  148. return;
  149. l = max(r1->x, r2->x);
  150. t = max(r1->y, r2->y);
  151. r = min((r1->x + r1->w), (r2->x + r2->w));
  152. b = min((r1->y + r1->h), (r2->y + r2->h));
  153. if (r <= l || b <= t) {
  154. memset(result, 0, sizeof(*result));
  155. } else {
  156. result->x = l;
  157. result->y = t;
  158. result->w = r - l;
  159. result->h = b - t;
  160. }
  161. }
  162. int dsi_display_set_backlight(struct drm_connector *connector,
  163. void *display, u32 bl_lvl)
  164. {
  165. struct dsi_display *dsi_display = display;
  166. struct dsi_panel *panel;
  167. u32 bl_scale, bl_scale_sv;
  168. u64 bl_temp;
  169. int rc = 0;
  170. if (dsi_display == NULL || dsi_display->panel == NULL)
  171. return -EINVAL;
  172. panel = dsi_display->panel;
  173. mutex_lock(&panel->panel_lock);
  174. if (!dsi_panel_initialized(panel)) {
  175. rc = -EINVAL;
  176. goto error;
  177. }
  178. panel->bl_config.bl_level = bl_lvl;
  179. /* scale backlight */
  180. bl_scale = panel->bl_config.bl_scale;
  181. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  182. bl_scale_sv = panel->bl_config.bl_scale_sv;
  183. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  184. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  185. bl_scale, bl_scale_sv, (u32)bl_temp);
  186. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  187. DSI_CORE_CLK, DSI_CLK_ON);
  188. if (rc) {
  189. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  190. dsi_display->name, rc);
  191. goto error;
  192. }
  193. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  194. if (rc)
  195. DSI_ERR("unable to set backlight\n");
  196. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  197. DSI_CORE_CLK, DSI_CLK_OFF);
  198. if (rc) {
  199. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  200. dsi_display->name, rc);
  201. goto error;
  202. }
  203. error:
  204. mutex_unlock(&panel->panel_lock);
  205. return rc;
  206. }
  207. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  208. {
  209. int rc = 0;
  210. int i;
  211. struct dsi_display_ctrl *m_ctrl, *ctrl;
  212. m_ctrl = &display->ctrl[display->cmd_master_idx];
  213. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  214. if (display->cmd_engine_refcount > 0) {
  215. display->cmd_engine_refcount++;
  216. goto done;
  217. }
  218. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
  219. if (rc) {
  220. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  221. display->name, rc);
  222. goto done;
  223. }
  224. display_for_each_ctrl(i, display) {
  225. ctrl = &display->ctrl[i];
  226. if (!ctrl->ctrl || (ctrl == m_ctrl))
  227. continue;
  228. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  229. DSI_CTRL_ENGINE_ON);
  230. if (rc) {
  231. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  232. display->name, rc);
  233. goto error_disable_master;
  234. }
  235. }
  236. display->cmd_engine_refcount++;
  237. goto done;
  238. error_disable_master:
  239. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
  240. done:
  241. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  242. return rc;
  243. }
  244. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  245. {
  246. int rc = 0;
  247. int i;
  248. struct dsi_display_ctrl *m_ctrl, *ctrl;
  249. m_ctrl = &display->ctrl[display->cmd_master_idx];
  250. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  251. if (display->cmd_engine_refcount == 0) {
  252. DSI_ERR("[%s] Invalid refcount\n", display->name);
  253. goto done;
  254. } else if (display->cmd_engine_refcount > 1) {
  255. display->cmd_engine_refcount--;
  256. goto done;
  257. }
  258. display_for_each_ctrl(i, display) {
  259. ctrl = &display->ctrl[i];
  260. if (!ctrl->ctrl || (ctrl == m_ctrl))
  261. continue;
  262. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  263. DSI_CTRL_ENGINE_OFF);
  264. if (rc)
  265. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  266. display->name, rc);
  267. }
  268. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
  269. if (rc) {
  270. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  271. display->name, rc);
  272. goto error;
  273. }
  274. error:
  275. display->cmd_engine_refcount = 0;
  276. done:
  277. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  278. return rc;
  279. }
  280. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  281. {
  282. struct dsi_display *display;
  283. struct dsi_display_ctrl *display_ctrl;
  284. int rc, cnt;
  285. if (!cb_data) {
  286. DSI_ERR("aspace cb called with invalid cb_data\n");
  287. return;
  288. }
  289. display = (struct dsi_display *)cb_data;
  290. /*
  291. * acquire panel_lock to make sure no commands are in-progress
  292. * while detaching the non-secure context banks
  293. */
  294. dsi_panel_acquire_panel_lock(display->panel);
  295. if (is_detach) {
  296. /* invalidate the stored iova */
  297. display->cmd_buffer_iova = 0;
  298. /* return the virtual address mapping */
  299. msm_gem_put_vaddr(display->tx_cmd_buf);
  300. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  301. } else {
  302. rc = msm_gem_get_iova(display->tx_cmd_buf,
  303. display->aspace, &(display->cmd_buffer_iova));
  304. if (rc) {
  305. DSI_ERR("failed to get the iova rc %d\n", rc);
  306. goto end;
  307. }
  308. display->vaddr =
  309. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  310. if (IS_ERR_OR_NULL(display->vaddr)) {
  311. DSI_ERR("failed to get va rc %d\n", rc);
  312. goto end;
  313. }
  314. }
  315. display_for_each_ctrl(cnt, display) {
  316. display_ctrl = &display->ctrl[cnt];
  317. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  318. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  319. display_ctrl->ctrl->vaddr = display->vaddr;
  320. display_ctrl->ctrl->secure_mode = is_detach;
  321. }
  322. end:
  323. /* release panel_lock */
  324. dsi_panel_release_panel_lock(display->panel);
  325. }
  326. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  327. {
  328. struct dsi_display *display = (struct dsi_display *)data;
  329. /*
  330. * This irq handler is used for sole purpose of identifying
  331. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  332. * in case of display not being initialized yet
  333. */
  334. if (!display)
  335. return IRQ_HANDLED;
  336. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  337. complete_all(&display->esd_te_gate);
  338. return IRQ_HANDLED;
  339. }
  340. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  341. bool enable)
  342. {
  343. if (!display) {
  344. DSI_ERR("Invalid params\n");
  345. return;
  346. }
  347. /* Handle unbalanced irq enable/disable calls */
  348. if (enable && !display->is_te_irq_enabled) {
  349. enable_irq(gpio_to_irq(display->disp_te_gpio));
  350. display->is_te_irq_enabled = true;
  351. } else if (!enable && display->is_te_irq_enabled) {
  352. disable_irq(gpio_to_irq(display->disp_te_gpio));
  353. display->is_te_irq_enabled = false;
  354. }
  355. }
  356. static void dsi_display_register_te_irq(struct dsi_display *display)
  357. {
  358. int rc = 0;
  359. struct platform_device *pdev;
  360. struct device *dev;
  361. unsigned int te_irq;
  362. pdev = display->pdev;
  363. if (!pdev) {
  364. DSI_ERR("invalid platform device\n");
  365. return;
  366. }
  367. dev = &pdev->dev;
  368. if (!dev) {
  369. DSI_ERR("invalid device\n");
  370. return;
  371. }
  372. if (!gpio_is_valid(display->disp_te_gpio)) {
  373. rc = -EINVAL;
  374. goto error;
  375. }
  376. init_completion(&display->esd_te_gate);
  377. te_irq = gpio_to_irq(display->disp_te_gpio);
  378. /* Avoid deferred spurious irqs with disable_irq() */
  379. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  380. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  381. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  382. "TE_GPIO", display);
  383. if (rc) {
  384. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  385. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  386. goto error;
  387. }
  388. disable_irq(te_irq);
  389. display->is_te_irq_enabled = false;
  390. return;
  391. error:
  392. /* disable the TE based ESD check */
  393. DSI_WARN("Unable to register for TE IRQ\n");
  394. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  395. display->panel->esd_config.esd_enabled = false;
  396. }
  397. /* Allocate memory for cmd dma tx buffer */
  398. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  399. {
  400. int rc = 0, cnt = 0;
  401. struct dsi_display_ctrl *display_ctrl;
  402. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  403. SZ_4K,
  404. MSM_BO_UNCACHED);
  405. if ((display->tx_cmd_buf) == NULL) {
  406. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  407. rc = -ENOMEM;
  408. goto error;
  409. }
  410. display->cmd_buffer_size = SZ_4K;
  411. display->aspace = msm_gem_smmu_address_space_get(
  412. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  413. if (!display->aspace) {
  414. DSI_ERR("failed to get aspace\n");
  415. rc = -EINVAL;
  416. goto free_gem;
  417. }
  418. /* register to aspace */
  419. rc = msm_gem_address_space_register_cb(display->aspace,
  420. dsi_display_aspace_cb_locked, (void *)display);
  421. if (rc) {
  422. DSI_ERR("failed to register callback %d\n", rc);
  423. goto free_gem;
  424. }
  425. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  426. &(display->cmd_buffer_iova));
  427. if (rc) {
  428. DSI_ERR("failed to get the iova rc %d\n", rc);
  429. goto free_aspace_cb;
  430. }
  431. display->vaddr =
  432. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  433. if (IS_ERR_OR_NULL(display->vaddr)) {
  434. DSI_ERR("failed to get va rc %d\n", rc);
  435. rc = -EINVAL;
  436. goto put_iova;
  437. }
  438. display_for_each_ctrl(cnt, display) {
  439. display_ctrl = &display->ctrl[cnt];
  440. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  441. display_ctrl->ctrl->cmd_buffer_iova =
  442. display->cmd_buffer_iova;
  443. display_ctrl->ctrl->vaddr = display->vaddr;
  444. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  445. }
  446. return rc;
  447. put_iova:
  448. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  449. free_aspace_cb:
  450. msm_gem_address_space_unregister_cb(display->aspace,
  451. dsi_display_aspace_cb_locked, display);
  452. free_gem:
  453. mutex_lock(&display->drm_dev->struct_mutex);
  454. msm_gem_free_object(display->tx_cmd_buf);
  455. mutex_unlock(&display->drm_dev->struct_mutex);
  456. error:
  457. return rc;
  458. }
  459. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  460. {
  461. int i, j = 0;
  462. int len = 0, *lenp;
  463. int group = 0, count = 0;
  464. struct drm_panel_esd_config *config;
  465. if (!panel)
  466. return false;
  467. config = &(panel->esd_config);
  468. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  469. count = config->status_cmd.count;
  470. for (i = 0; i < count; i++)
  471. len += lenp[i];
  472. for (i = 0; i < len; i++)
  473. j += len;
  474. for (j = 0; j < config->groups; ++j) {
  475. for (i = 0; i < len; ++i) {
  476. if (config->return_buf[i] !=
  477. config->status_value[group + i]) {
  478. DRM_ERROR("mismatch: 0x%x\n",
  479. config->return_buf[i]);
  480. break;
  481. }
  482. }
  483. if (i == len)
  484. return true;
  485. group += len;
  486. }
  487. return false;
  488. }
  489. static void dsi_display_parse_te_data(struct dsi_display *display)
  490. {
  491. struct platform_device *pdev;
  492. struct device *dev;
  493. int rc = 0;
  494. u32 val = 0;
  495. pdev = display->pdev;
  496. if (!pdev) {
  497. DSI_ERR("Invalid platform device\n");
  498. return;
  499. }
  500. dev = &pdev->dev;
  501. if (!dev) {
  502. DSI_ERR("Invalid platform device\n");
  503. return;
  504. }
  505. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  506. "qcom,platform-te-gpio", 0);
  507. if (display->fw)
  508. rc = dsi_parser_read_u32(display->parser_node,
  509. "qcom,panel-te-source", &val);
  510. else
  511. rc = of_property_read_u32(dev->of_node,
  512. "qcom,panel-te-source", &val);
  513. if (rc || (val > MAX_TE_SOURCE_ID)) {
  514. DSI_ERR("invalid vsync source selection\n");
  515. val = 0;
  516. }
  517. display->te_source = val;
  518. }
  519. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  520. struct dsi_panel *panel)
  521. {
  522. int i, rc = 0, count = 0, start = 0, *lenp;
  523. struct drm_panel_esd_config *config;
  524. struct dsi_cmd_desc *cmds;
  525. u32 flags = 0;
  526. if (!panel || !ctrl || !ctrl->ctrl)
  527. return -EINVAL;
  528. /*
  529. * When DSI controller is not in initialized state, we do not want to
  530. * report a false ESD failure and hence we defer until next read
  531. * happen.
  532. */
  533. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  534. return 1;
  535. config = &(panel->esd_config);
  536. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  537. count = config->status_cmd.count;
  538. cmds = config->status_cmd.cmds;
  539. flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ |
  540. DSI_CTRL_CMD_CUSTOM_DMA_SCHED);
  541. for (i = 0; i < count; ++i) {
  542. memset(config->status_buf, 0x0, SZ_4K);
  543. if (cmds[i].last_command) {
  544. cmds[i].msg.flags |= MIPI_DSI_MSG_LASTCOMMAND;
  545. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  546. }
  547. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  548. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  549. cmds[i].msg.rx_buf = config->status_buf;
  550. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  551. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i].msg, &flags);
  552. if (rc <= 0) {
  553. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  554. return rc;
  555. }
  556. memcpy(config->return_buf + start,
  557. config->status_buf, lenp[i]);
  558. start += lenp[i];
  559. }
  560. return rc;
  561. }
  562. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  563. struct dsi_panel *panel)
  564. {
  565. int rc = 0;
  566. rc = dsi_display_read_status(ctrl, panel);
  567. if (rc <= 0) {
  568. goto exit;
  569. } else {
  570. /*
  571. * panel status read successfully.
  572. * check for validity of the data read back.
  573. */
  574. rc = dsi_display_validate_reg_read(panel);
  575. if (!rc) {
  576. rc = -EINVAL;
  577. goto exit;
  578. }
  579. }
  580. exit:
  581. return rc;
  582. }
  583. static int dsi_display_status_reg_read(struct dsi_display *display)
  584. {
  585. int rc = 0, i;
  586. struct dsi_display_ctrl *m_ctrl, *ctrl;
  587. DSI_DEBUG(" ++\n");
  588. m_ctrl = &display->ctrl[display->cmd_master_idx];
  589. if (display->tx_cmd_buf == NULL) {
  590. rc = dsi_host_alloc_cmd_tx_buffer(display);
  591. if (rc) {
  592. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  593. goto done;
  594. }
  595. }
  596. rc = dsi_display_cmd_engine_enable(display);
  597. if (rc) {
  598. DSI_ERR("cmd engine enable failed\n");
  599. return -EPERM;
  600. }
  601. rc = dsi_display_validate_status(m_ctrl, display->panel);
  602. if (rc <= 0) {
  603. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  604. display->name, rc);
  605. goto exit;
  606. }
  607. if (!display->panel->sync_broadcast_en)
  608. goto exit;
  609. display_for_each_ctrl(i, display) {
  610. ctrl = &display->ctrl[i];
  611. if (ctrl == m_ctrl)
  612. continue;
  613. rc = dsi_display_validate_status(ctrl, display->panel);
  614. if (rc <= 0) {
  615. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  616. display->name, rc);
  617. goto exit;
  618. }
  619. }
  620. exit:
  621. dsi_display_cmd_engine_disable(display);
  622. done:
  623. return rc;
  624. }
  625. static int dsi_display_status_bta_request(struct dsi_display *display)
  626. {
  627. int rc = 0;
  628. DSI_DEBUG(" ++\n");
  629. /* TODO: trigger SW BTA and wait for acknowledgment */
  630. return rc;
  631. }
  632. static int dsi_display_status_check_te(struct dsi_display *display)
  633. {
  634. int rc = 1;
  635. int const esd_te_timeout = msecs_to_jiffies(3*20);
  636. dsi_display_change_te_irq_status(display, true);
  637. reinit_completion(&display->esd_te_gate);
  638. if (!wait_for_completion_timeout(&display->esd_te_gate,
  639. esd_te_timeout)) {
  640. DSI_ERR("TE check failed\n");
  641. rc = -EINVAL;
  642. }
  643. dsi_display_change_te_irq_status(display, false);
  644. return rc;
  645. }
  646. int dsi_display_check_status(struct drm_connector *connector, void *display,
  647. bool te_check_override)
  648. {
  649. struct dsi_display *dsi_display = display;
  650. struct dsi_panel *panel;
  651. u32 status_mode;
  652. int rc = 0x1, ret;
  653. u32 mask;
  654. if (!dsi_display || !dsi_display->panel)
  655. return -EINVAL;
  656. panel = dsi_display->panel;
  657. dsi_panel_acquire_panel_lock(panel);
  658. if (!panel->panel_initialized) {
  659. DSI_DEBUG("Panel not initialized\n");
  660. goto release_panel_lock;
  661. }
  662. /* Prevent another ESD check,when ESD recovery is underway */
  663. if (atomic_read(&panel->esd_recovery_pending))
  664. goto release_panel_lock;
  665. status_mode = panel->esd_config.status_mode;
  666. if (status_mode == ESD_MODE_SW_SIM_SUCCESS)
  667. goto release_panel_lock;
  668. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  669. rc = -EINVAL;
  670. goto release_panel_lock;
  671. }
  672. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  673. if (te_check_override && gpio_is_valid(dsi_display->disp_te_gpio))
  674. status_mode = ESD_MODE_PANEL_TE;
  675. if (status_mode == ESD_MODE_PANEL_TE) {
  676. rc = dsi_display_status_check_te(dsi_display);
  677. goto exit;
  678. }
  679. ret = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  680. DSI_ALL_CLKS, DSI_CLK_ON);
  681. if (ret)
  682. goto release_panel_lock;
  683. /* Mask error interrupts before attempting ESD read */
  684. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  685. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  686. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
  687. if (status_mode == ESD_MODE_REG_READ) {
  688. rc = dsi_display_status_reg_read(dsi_display);
  689. } else if (status_mode == ESD_MODE_SW_BTA) {
  690. rc = dsi_display_status_bta_request(dsi_display);
  691. } else if (status_mode == ESD_MODE_PANEL_TE) {
  692. rc = dsi_display_status_check_te(dsi_display);
  693. } else {
  694. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  695. panel->esd_config.esd_enabled = false;
  696. }
  697. /* Unmask error interrupts if check passed*/
  698. if (rc > 0) {
  699. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  700. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
  701. false);
  702. }
  703. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  704. DSI_ALL_CLKS, DSI_CLK_OFF);
  705. exit:
  706. /* Handle Panel failures during display disable sequence */
  707. if (rc <=0)
  708. atomic_set(&panel->esd_recovery_pending, 1);
  709. release_panel_lock:
  710. dsi_panel_release_panel_lock(panel);
  711. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  712. return rc;
  713. }
  714. static int dsi_display_cmd_prepare(const char *cmd_buf, u32 cmd_buf_len,
  715. struct dsi_cmd_desc *cmd, u8 *payload, u32 payload_len)
  716. {
  717. int i;
  718. memset(cmd, 0x00, sizeof(*cmd));
  719. cmd->msg.type = cmd_buf[0];
  720. cmd->last_command = (cmd_buf[1] == 1);
  721. cmd->msg.channel = cmd_buf[2];
  722. cmd->msg.flags = cmd_buf[3];
  723. cmd->msg.ctrl = 0;
  724. cmd->post_wait_ms = cmd->msg.wait_ms = cmd_buf[4];
  725. cmd->msg.tx_len = ((cmd_buf[5] << 8) | (cmd_buf[6]));
  726. if (cmd->msg.tx_len > payload_len) {
  727. DSI_ERR("Incorrect payload length tx_len %zu, payload_len %d\n",
  728. cmd->msg.tx_len, payload_len);
  729. return -EINVAL;
  730. }
  731. for (i = 0; i < cmd->msg.tx_len; i++)
  732. payload[i] = cmd_buf[7 + i];
  733. cmd->msg.tx_buf = payload;
  734. return 0;
  735. }
  736. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  737. bool *state)
  738. {
  739. struct dsi_display_ctrl *ctrl;
  740. int i, rc = -EINVAL;
  741. display_for_each_ctrl(i, dsi_display) {
  742. ctrl = &dsi_display->ctrl[i];
  743. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  744. if (rc)
  745. break;
  746. }
  747. return rc;
  748. }
  749. int dsi_display_cmd_transfer(struct drm_connector *connector,
  750. void *display, const char *cmd_buf,
  751. u32 cmd_buf_len)
  752. {
  753. struct dsi_display *dsi_display = display;
  754. struct dsi_cmd_desc cmd;
  755. u8 cmd_payload[MAX_CMD_PAYLOAD_SIZE];
  756. int rc = 0;
  757. bool state = false;
  758. if (!dsi_display || !cmd_buf) {
  759. DSI_ERR("[DSI] invalid params\n");
  760. return -EINVAL;
  761. }
  762. DSI_DEBUG("[DSI] Display command transfer\n");
  763. rc = dsi_display_cmd_prepare(cmd_buf, cmd_buf_len,
  764. &cmd, cmd_payload, MAX_CMD_PAYLOAD_SIZE);
  765. if (rc) {
  766. DSI_ERR("[DSI] command prepare failed. rc %d\n", rc);
  767. return rc;
  768. }
  769. mutex_lock(&dsi_display->display_lock);
  770. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  771. /**
  772. * Handle scenario where a command transfer is initiated through
  773. * sysfs interface when device is in suepnd state.
  774. */
  775. if (!rc && !state) {
  776. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  777. );
  778. rc = -EPERM;
  779. goto end;
  780. }
  781. if (rc || !state) {
  782. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  783. state, rc);
  784. rc = -EPERM;
  785. goto end;
  786. }
  787. rc = dsi_display->host.ops->transfer(&dsi_display->host,
  788. &cmd.msg);
  789. end:
  790. mutex_unlock(&dsi_display->display_lock);
  791. return rc;
  792. }
  793. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  794. bool enable)
  795. {
  796. int i;
  797. struct dsi_display_ctrl *ctrl;
  798. if (!display || !display->panel->host_config.force_hs_clk_lane)
  799. return;
  800. display_for_each_ctrl(i, display) {
  801. ctrl = &display->ctrl[i];
  802. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  803. }
  804. }
  805. int dsi_display_soft_reset(void *display)
  806. {
  807. struct dsi_display *dsi_display;
  808. struct dsi_display_ctrl *ctrl;
  809. int rc = 0;
  810. int i;
  811. if (!display)
  812. return -EINVAL;
  813. dsi_display = display;
  814. display_for_each_ctrl(i, dsi_display) {
  815. ctrl = &dsi_display->ctrl[i];
  816. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  817. if (rc) {
  818. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  819. dsi_display->name, i, rc);
  820. break;
  821. }
  822. }
  823. return rc;
  824. }
  825. enum dsi_pixel_format dsi_display_get_dst_format(
  826. struct drm_connector *connector,
  827. void *display)
  828. {
  829. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  830. struct dsi_display *dsi_display = (struct dsi_display *)display;
  831. if (!dsi_display || !dsi_display->panel) {
  832. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  833. dsi_display,
  834. ((dsi_display) ? dsi_display->panel : NULL));
  835. return format;
  836. }
  837. format = dsi_display->panel->host_config.dst_format;
  838. return format;
  839. }
  840. static void _dsi_display_setup_misr(struct dsi_display *display)
  841. {
  842. int i;
  843. display_for_each_ctrl(i, display) {
  844. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  845. display->misr_enable,
  846. display->misr_frame_count);
  847. }
  848. }
  849. int dsi_display_set_power(struct drm_connector *connector,
  850. int power_mode, void *disp)
  851. {
  852. struct dsi_display *display = disp;
  853. int rc = 0;
  854. if (!display || !display->panel) {
  855. DSI_ERR("invalid display/panel\n");
  856. return -EINVAL;
  857. }
  858. switch (power_mode) {
  859. case SDE_MODE_DPMS_LP1:
  860. rc = dsi_panel_set_lp1(display->panel);
  861. break;
  862. case SDE_MODE_DPMS_LP2:
  863. rc = dsi_panel_set_lp2(display->panel);
  864. break;
  865. case SDE_MODE_DPMS_ON:
  866. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  867. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  868. rc = dsi_panel_set_nolp(display->panel);
  869. break;
  870. case SDE_MODE_DPMS_OFF:
  871. default:
  872. return rc;
  873. }
  874. DSI_DEBUG("Power mode transition from %d to %d %s",
  875. display->panel->power_mode, power_mode,
  876. rc ? "failed" : "successful");
  877. if (!rc)
  878. display->panel->power_mode = power_mode;
  879. return rc;
  880. }
  881. #ifdef CONFIG_DEBUG_FS
  882. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  883. {
  884. u32 status_mode = 0;
  885. if (!display->panel) {
  886. DSI_ERR("Invalid panel data\n");
  887. return false;
  888. }
  889. status_mode = display->panel->esd_config.status_mode;
  890. if (status_mode == ESD_MODE_PANEL_TE &&
  891. gpio_is_valid(display->disp_te_gpio))
  892. return true;
  893. return false;
  894. }
  895. static ssize_t debugfs_dump_info_read(struct file *file,
  896. char __user *user_buf,
  897. size_t user_len,
  898. loff_t *ppos)
  899. {
  900. struct dsi_display *display = file->private_data;
  901. char *buf;
  902. u32 len = 0;
  903. int i;
  904. if (!display)
  905. return -ENODEV;
  906. if (*ppos)
  907. return 0;
  908. buf = kzalloc(SZ_4K, GFP_KERNEL);
  909. if (!buf)
  910. return -ENOMEM;
  911. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  912. len += snprintf(buf + len, (SZ_4K - len),
  913. "\tResolution = %dx%d\n",
  914. display->config.video_timing.h_active,
  915. display->config.video_timing.v_active);
  916. display_for_each_ctrl(i, display) {
  917. len += snprintf(buf + len, (SZ_4K - len),
  918. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  919. i, display->ctrl[i].ctrl->name,
  920. display->ctrl[i].phy->name);
  921. }
  922. len += snprintf(buf + len, (SZ_4K - len),
  923. "\tPanel = %s\n", display->panel->name);
  924. len += snprintf(buf + len, (SZ_4K - len),
  925. "\tClock master = %s\n",
  926. display->ctrl[display->clk_master_idx].ctrl->name);
  927. if (len > user_len)
  928. len = user_len;
  929. if (copy_to_user(user_buf, buf, len)) {
  930. kfree(buf);
  931. return -EFAULT;
  932. }
  933. *ppos += len;
  934. kfree(buf);
  935. return len;
  936. }
  937. static ssize_t debugfs_misr_setup(struct file *file,
  938. const char __user *user_buf,
  939. size_t user_len,
  940. loff_t *ppos)
  941. {
  942. struct dsi_display *display = file->private_data;
  943. char *buf;
  944. int rc = 0;
  945. size_t len;
  946. u32 enable, frame_count;
  947. if (!display)
  948. return -ENODEV;
  949. if (*ppos)
  950. return 0;
  951. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  952. if (!buf)
  953. return -ENOMEM;
  954. /* leave room for termination char */
  955. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  956. if (copy_from_user(buf, user_buf, len)) {
  957. rc = -EINVAL;
  958. goto error;
  959. }
  960. buf[len] = '\0'; /* terminate the string */
  961. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  962. rc = -EINVAL;
  963. goto error;
  964. }
  965. display->misr_enable = enable;
  966. display->misr_frame_count = frame_count;
  967. mutex_lock(&display->display_lock);
  968. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  969. DSI_CORE_CLK, DSI_CLK_ON);
  970. if (rc) {
  971. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  972. display->name, rc);
  973. goto unlock;
  974. }
  975. _dsi_display_setup_misr(display);
  976. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  977. DSI_CORE_CLK, DSI_CLK_OFF);
  978. if (rc) {
  979. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  980. display->name, rc);
  981. goto unlock;
  982. }
  983. rc = user_len;
  984. unlock:
  985. mutex_unlock(&display->display_lock);
  986. error:
  987. kfree(buf);
  988. return rc;
  989. }
  990. static ssize_t debugfs_misr_read(struct file *file,
  991. char __user *user_buf,
  992. size_t user_len,
  993. loff_t *ppos)
  994. {
  995. struct dsi_display *display = file->private_data;
  996. char *buf;
  997. u32 len = 0;
  998. int rc = 0;
  999. struct dsi_ctrl *dsi_ctrl;
  1000. int i;
  1001. u32 misr;
  1002. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1003. if (!display)
  1004. return -ENODEV;
  1005. if (*ppos)
  1006. return 0;
  1007. buf = kzalloc(max_len, GFP_KERNEL);
  1008. if (ZERO_OR_NULL_PTR(buf))
  1009. return -ENOMEM;
  1010. mutex_lock(&display->display_lock);
  1011. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1012. DSI_CORE_CLK, DSI_CLK_ON);
  1013. if (rc) {
  1014. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1015. display->name, rc);
  1016. goto error;
  1017. }
  1018. display_for_each_ctrl(i, display) {
  1019. dsi_ctrl = display->ctrl[i].ctrl;
  1020. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1021. len += snprintf((buf + len), max_len - len,
  1022. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1023. if (len >= max_len)
  1024. break;
  1025. }
  1026. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1027. DSI_CORE_CLK, DSI_CLK_OFF);
  1028. if (rc) {
  1029. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1030. display->name, rc);
  1031. goto error;
  1032. }
  1033. if (copy_to_user(user_buf, buf, max_len)) {
  1034. rc = -EFAULT;
  1035. goto error;
  1036. }
  1037. *ppos += len;
  1038. error:
  1039. mutex_unlock(&display->display_lock);
  1040. kfree(buf);
  1041. return len;
  1042. }
  1043. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1044. const char __user *user_buf,
  1045. size_t user_len,
  1046. loff_t *ppos)
  1047. {
  1048. struct dsi_display *display = file->private_data;
  1049. char *buf;
  1050. int rc = 0;
  1051. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1052. u32 esd_trigger;
  1053. size_t len;
  1054. if (!display)
  1055. return -ENODEV;
  1056. if (*ppos)
  1057. return 0;
  1058. if (user_len > sizeof(u32))
  1059. return -EINVAL;
  1060. if (!user_len || !user_buf)
  1061. return -EINVAL;
  1062. if (!display->panel ||
  1063. atomic_read(&display->panel->esd_recovery_pending))
  1064. return user_len;
  1065. if (!esd_config->esd_enabled) {
  1066. DSI_ERR("ESD feature is not enabled\n");
  1067. return -EINVAL;
  1068. }
  1069. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1070. if (!buf)
  1071. return -ENOMEM;
  1072. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1073. if (copy_from_user(buf, user_buf, len)) {
  1074. rc = -EINVAL;
  1075. goto error;
  1076. }
  1077. buf[len] = '\0'; /* terminate the string */
  1078. if (kstrtouint(buf, 10, &esd_trigger)) {
  1079. rc = -EINVAL;
  1080. goto error;
  1081. }
  1082. if (esd_trigger != 1) {
  1083. rc = -EINVAL;
  1084. goto error;
  1085. }
  1086. display->esd_trigger = esd_trigger;
  1087. if (display->esd_trigger) {
  1088. DSI_INFO("ESD attack triggered by user\n");
  1089. rc = dsi_panel_trigger_esd_attack(display->panel);
  1090. if (rc) {
  1091. DSI_ERR("Failed to trigger ESD attack\n");
  1092. goto error;
  1093. }
  1094. }
  1095. rc = len;
  1096. error:
  1097. kfree(buf);
  1098. return rc;
  1099. }
  1100. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1101. const char __user *user_buf,
  1102. size_t user_len,
  1103. loff_t *ppos)
  1104. {
  1105. struct dsi_display *display = file->private_data;
  1106. struct drm_panel_esd_config *esd_config;
  1107. char *buf;
  1108. int rc = 0;
  1109. size_t len;
  1110. if (!display)
  1111. return -ENODEV;
  1112. if (*ppos)
  1113. return 0;
  1114. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1115. if (ZERO_OR_NULL_PTR(buf))
  1116. return -ENOMEM;
  1117. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1118. if (copy_from_user(buf, user_buf, len)) {
  1119. rc = -EINVAL;
  1120. goto error;
  1121. }
  1122. buf[len] = '\0'; /* terminate the string */
  1123. if (!display->panel) {
  1124. rc = -EINVAL;
  1125. goto error;
  1126. }
  1127. esd_config = &display->panel->esd_config;
  1128. if (!esd_config) {
  1129. DSI_ERR("Invalid panel esd config\n");
  1130. rc = -EINVAL;
  1131. goto error;
  1132. }
  1133. if (!esd_config->esd_enabled)
  1134. goto error;
  1135. if (!strcmp(buf, "te_signal_check\n")) {
  1136. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1137. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1138. goto error;
  1139. }
  1140. DSI_INFO("ESD check is switched to TE mode by user\n");
  1141. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1142. dsi_display_change_te_irq_status(display, true);
  1143. }
  1144. if (!strcmp(buf, "reg_read\n")) {
  1145. DSI_INFO("ESD check is switched to reg read by user\n");
  1146. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1147. if (rc) {
  1148. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1149. rc);
  1150. rc = user_len;
  1151. goto error;
  1152. }
  1153. esd_config->status_mode = ESD_MODE_REG_READ;
  1154. if (dsi_display_is_te_based_esd(display))
  1155. dsi_display_change_te_irq_status(display, false);
  1156. }
  1157. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1158. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1159. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1160. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1161. rc = len;
  1162. error:
  1163. kfree(buf);
  1164. return rc;
  1165. }
  1166. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1167. char __user *user_buf,
  1168. size_t user_len,
  1169. loff_t *ppos)
  1170. {
  1171. struct dsi_display *display = file->private_data;
  1172. struct drm_panel_esd_config *esd_config;
  1173. char *buf;
  1174. int rc = 0;
  1175. size_t len = 0;
  1176. if (!display)
  1177. return -ENODEV;
  1178. if (*ppos)
  1179. return 0;
  1180. if (!display->panel) {
  1181. DSI_ERR("invalid panel data\n");
  1182. return -EINVAL;
  1183. }
  1184. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1185. if (ZERO_OR_NULL_PTR(buf))
  1186. return -ENOMEM;
  1187. esd_config = &display->panel->esd_config;
  1188. if (!esd_config) {
  1189. DSI_ERR("Invalid panel esd config\n");
  1190. rc = -EINVAL;
  1191. goto error;
  1192. }
  1193. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1194. if (!esd_config->esd_enabled) {
  1195. rc = snprintf(buf, len, "ESD feature not enabled");
  1196. goto output_mode;
  1197. }
  1198. switch (esd_config->status_mode) {
  1199. case ESD_MODE_REG_READ:
  1200. rc = snprintf(buf, len, "reg_read");
  1201. break;
  1202. case ESD_MODE_PANEL_TE:
  1203. rc = snprintf(buf, len, "te_signal_check");
  1204. break;
  1205. case ESD_MODE_SW_SIM_FAILURE:
  1206. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1207. break;
  1208. case ESD_MODE_SW_SIM_SUCCESS:
  1209. rc = snprintf(buf, len, "esd_sw_sim_success");
  1210. break;
  1211. default:
  1212. rc = snprintf(buf, len, "invalid");
  1213. break;
  1214. }
  1215. output_mode:
  1216. if (!rc) {
  1217. rc = -EINVAL;
  1218. goto error;
  1219. }
  1220. if (copy_to_user(user_buf, buf, len)) {
  1221. rc = -EFAULT;
  1222. goto error;
  1223. }
  1224. *ppos += len;
  1225. error:
  1226. kfree(buf);
  1227. return len;
  1228. }
  1229. static const struct file_operations dump_info_fops = {
  1230. .open = simple_open,
  1231. .read = debugfs_dump_info_read,
  1232. };
  1233. static const struct file_operations misr_data_fops = {
  1234. .open = simple_open,
  1235. .read = debugfs_misr_read,
  1236. .write = debugfs_misr_setup,
  1237. };
  1238. static const struct file_operations esd_trigger_fops = {
  1239. .open = simple_open,
  1240. .write = debugfs_esd_trigger_check,
  1241. };
  1242. static const struct file_operations esd_check_mode_fops = {
  1243. .open = simple_open,
  1244. .write = debugfs_alter_esd_check_mode,
  1245. .read = debugfs_read_esd_check_mode,
  1246. };
  1247. static int dsi_display_debugfs_init(struct dsi_display *display)
  1248. {
  1249. int rc = 0;
  1250. struct dentry *dir, *dump_file, *misr_data;
  1251. char name[MAX_NAME_SIZE];
  1252. int i;
  1253. dir = debugfs_create_dir(display->name, NULL);
  1254. if (IS_ERR_OR_NULL(dir)) {
  1255. rc = PTR_ERR(dir);
  1256. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1257. display->name, rc);
  1258. goto error;
  1259. }
  1260. dump_file = debugfs_create_file("dump_info",
  1261. 0400,
  1262. dir,
  1263. display,
  1264. &dump_info_fops);
  1265. if (IS_ERR_OR_NULL(dump_file)) {
  1266. rc = PTR_ERR(dump_file);
  1267. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1268. display->name, rc);
  1269. goto error_remove_dir;
  1270. }
  1271. dump_file = debugfs_create_file("esd_trigger",
  1272. 0644,
  1273. dir,
  1274. display,
  1275. &esd_trigger_fops);
  1276. if (IS_ERR_OR_NULL(dump_file)) {
  1277. rc = PTR_ERR(dump_file);
  1278. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1279. display->name, rc);
  1280. goto error_remove_dir;
  1281. }
  1282. dump_file = debugfs_create_file("esd_check_mode",
  1283. 0644,
  1284. dir,
  1285. display,
  1286. &esd_check_mode_fops);
  1287. if (IS_ERR_OR_NULL(dump_file)) {
  1288. rc = PTR_ERR(dump_file);
  1289. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1290. display->name, rc);
  1291. goto error_remove_dir;
  1292. }
  1293. misr_data = debugfs_create_file("misr_data",
  1294. 0600,
  1295. dir,
  1296. display,
  1297. &misr_data_fops);
  1298. if (IS_ERR_OR_NULL(misr_data)) {
  1299. rc = PTR_ERR(misr_data);
  1300. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1301. display->name, rc);
  1302. goto error_remove_dir;
  1303. }
  1304. display_for_each_ctrl(i, display) {
  1305. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1306. if (!phy || !phy->name)
  1307. continue;
  1308. snprintf(name, ARRAY_SIZE(name),
  1309. "%s_allow_phy_power_off", phy->name);
  1310. dump_file = debugfs_create_bool(name, 0600, dir,
  1311. &phy->allow_phy_power_off);
  1312. if (IS_ERR_OR_NULL(dump_file)) {
  1313. rc = PTR_ERR(dump_file);
  1314. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1315. display->name, name, rc);
  1316. goto error_remove_dir;
  1317. }
  1318. snprintf(name, ARRAY_SIZE(name),
  1319. "%s_regulator_min_datarate_bps", phy->name);
  1320. dump_file = debugfs_create_u32(name, 0600, dir,
  1321. &phy->regulator_min_datarate_bps);
  1322. if (IS_ERR_OR_NULL(dump_file)) {
  1323. rc = PTR_ERR(dump_file);
  1324. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1325. display->name, name, rc);
  1326. goto error_remove_dir;
  1327. }
  1328. }
  1329. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1330. &display->panel->ulps_feature_enabled)) {
  1331. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1332. display->name);
  1333. goto error_remove_dir;
  1334. }
  1335. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1336. &display->panel->ulps_suspend_enabled)) {
  1337. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1338. display->name);
  1339. goto error_remove_dir;
  1340. }
  1341. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1342. &display->ulps_enabled)) {
  1343. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1344. display->name);
  1345. goto error_remove_dir;
  1346. }
  1347. if (!debugfs_create_u32("clk_gating_config", 0600, dir,
  1348. &display->clk_gating_config)) {
  1349. DSI_ERR("[%s] debugfs create clk gating config failed\n",
  1350. display->name);
  1351. goto error_remove_dir;
  1352. }
  1353. display->root = dir;
  1354. dsi_parser_dbg_init(display->parser, dir);
  1355. return rc;
  1356. error_remove_dir:
  1357. debugfs_remove(dir);
  1358. error:
  1359. return rc;
  1360. }
  1361. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1362. {
  1363. debugfs_remove_recursive(display->root);
  1364. return 0;
  1365. }
  1366. #else
  1367. static int dsi_display_debugfs_init(struct dsi_display *display)
  1368. {
  1369. return 0;
  1370. }
  1371. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1372. {
  1373. return 0;
  1374. }
  1375. #endif /* CONFIG_DEBUG_FS */
  1376. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1377. struct dsi_display_mode *mode)
  1378. {
  1379. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1380. bool is_split_link = host->split_link.split_link_enabled;
  1381. u32 sublinks_count = host->split_link.num_sublinks;
  1382. if (is_split_link && sublinks_count > 1) {
  1383. mode->timing.h_active /= sublinks_count;
  1384. mode->timing.h_front_porch /= sublinks_count;
  1385. mode->timing.h_sync_width /= sublinks_count;
  1386. mode->timing.h_back_porch /= sublinks_count;
  1387. mode->timing.h_skew /= sublinks_count;
  1388. mode->pixel_clk_khz /= sublinks_count;
  1389. } else {
  1390. if (mode->priv_info->dsc_enabled)
  1391. mode->priv_info->dsc.config.pic_width =
  1392. mode->timing.h_active;
  1393. mode->timing.h_active /= display->ctrl_count;
  1394. mode->timing.h_front_porch /= display->ctrl_count;
  1395. mode->timing.h_sync_width /= display->ctrl_count;
  1396. mode->timing.h_back_porch /= display->ctrl_count;
  1397. mode->timing.h_skew /= display->ctrl_count;
  1398. mode->pixel_clk_khz /= display->ctrl_count;
  1399. }
  1400. }
  1401. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1402. bool enable)
  1403. {
  1404. /* TODO: make checks based on cont. splash */
  1405. DSI_DEBUG("checking ulps req validity\n");
  1406. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1407. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1408. return false;
  1409. }
  1410. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1411. !display->panel->ulps_suspend_enabled) {
  1412. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1413. return false;
  1414. }
  1415. if (!dsi_panel_initialized(display->panel) &&
  1416. !display->panel->ulps_suspend_enabled) {
  1417. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1418. return false;
  1419. }
  1420. if (enable && display->ulps_enabled) {
  1421. DSI_DEBUG("ULPS already enabled\n");
  1422. return false;
  1423. } else if (!enable && !display->ulps_enabled) {
  1424. DSI_DEBUG("ULPS already disabled\n");
  1425. return false;
  1426. }
  1427. /*
  1428. * No need to enter ULPS when transitioning from splash screen to
  1429. * boot animation since it is expected that the clocks would be turned
  1430. * right back on.
  1431. */
  1432. if (enable && display->is_cont_splash_enabled)
  1433. return false;
  1434. return true;
  1435. }
  1436. /**
  1437. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1438. * @dsi_display: DSI display handle.
  1439. * @enable: enable/disable ULPS.
  1440. *
  1441. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1442. *
  1443. * Return: error code.
  1444. */
  1445. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1446. {
  1447. int rc = 0;
  1448. int i = 0;
  1449. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1450. if (!display) {
  1451. DSI_ERR("Invalid params\n");
  1452. return -EINVAL;
  1453. }
  1454. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1455. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1456. __func__, enable);
  1457. return 0;
  1458. }
  1459. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1460. /*
  1461. * ULPS entry-exit can be either through the DSI controller or
  1462. * the DSI PHY depending on hardware variation. For some chipsets,
  1463. * both controller version and phy version ulps entry-exit ops can
  1464. * be present. To handle such cases, send ulps request through PHY,
  1465. * if ulps request is handled in PHY, then no need to send request
  1466. * through controller.
  1467. */
  1468. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1469. display->clamp_enabled);
  1470. if (rc == DSI_PHY_ULPS_ERROR) {
  1471. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1472. return -EINVAL;
  1473. }
  1474. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1475. display_for_each_ctrl(i, display) {
  1476. ctrl = &display->ctrl[i];
  1477. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1478. continue;
  1479. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1480. enable, display->clamp_enabled);
  1481. if (rc == DSI_PHY_ULPS_ERROR) {
  1482. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1483. enable);
  1484. return -EINVAL;
  1485. }
  1486. }
  1487. }
  1488. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1489. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1490. if (rc) {
  1491. DSI_ERR("Ulps controller state change(%d) failed\n",
  1492. enable);
  1493. return rc;
  1494. }
  1495. display_for_each_ctrl(i, display) {
  1496. ctrl = &display->ctrl[i];
  1497. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1498. continue;
  1499. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1500. if (rc) {
  1501. DSI_ERR("Ulps controller state change(%d) failed\n",
  1502. enable);
  1503. return rc;
  1504. }
  1505. }
  1506. }
  1507. display->ulps_enabled = enable;
  1508. return 0;
  1509. }
  1510. /**
  1511. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1512. * @dsi_display: DSI display handle.
  1513. * @enable: enable/disable clamping.
  1514. *
  1515. * Return: error code.
  1516. */
  1517. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1518. {
  1519. int rc = 0;
  1520. int i = 0;
  1521. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1522. bool ulps_enabled = false;
  1523. if (!display) {
  1524. DSI_ERR("Invalid params\n");
  1525. return -EINVAL;
  1526. }
  1527. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1528. ulps_enabled = display->ulps_enabled;
  1529. /*
  1530. * Clamp control can be either through the DSI controller or
  1531. * the DSI PHY depending on hardware variation
  1532. */
  1533. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1534. if (rc) {
  1535. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1536. return rc;
  1537. }
  1538. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1539. if (rc) {
  1540. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1541. return rc;
  1542. }
  1543. display_for_each_ctrl(i, display) {
  1544. ctrl = &display->ctrl[i];
  1545. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1546. continue;
  1547. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1548. if (rc) {
  1549. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1550. return rc;
  1551. }
  1552. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1553. if (rc) {
  1554. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1555. enable);
  1556. return rc;
  1557. }
  1558. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1559. enable ? "enabled" : "disabled", i);
  1560. }
  1561. display->clamp_enabled = enable;
  1562. return 0;
  1563. }
  1564. /**
  1565. * dsi_display_setup_ctrl() - setup DSI controller.
  1566. * @dsi_display: DSI display handle.
  1567. *
  1568. * Return: error code.
  1569. */
  1570. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1571. {
  1572. int rc = 0;
  1573. int i = 0;
  1574. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1575. if (!display) {
  1576. DSI_ERR("Invalid params\n");
  1577. return -EINVAL;
  1578. }
  1579. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1580. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1581. if (rc) {
  1582. DSI_ERR("DSI controller setup failed\n");
  1583. return rc;
  1584. }
  1585. display_for_each_ctrl(i, display) {
  1586. ctrl = &display->ctrl[i];
  1587. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1588. continue;
  1589. rc = dsi_ctrl_setup(ctrl->ctrl);
  1590. if (rc) {
  1591. DSI_ERR("DSI controller setup failed\n");
  1592. return rc;
  1593. }
  1594. }
  1595. return 0;
  1596. }
  1597. static int dsi_display_phy_enable(struct dsi_display *display);
  1598. /**
  1599. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1600. * @dsi_display: DSI display handle.
  1601. * @mmss_clamp: True if clamp is enabled.
  1602. *
  1603. * Return: error code.
  1604. */
  1605. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1606. bool mmss_clamp)
  1607. {
  1608. int rc = 0;
  1609. int i = 0;
  1610. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1611. if (!display) {
  1612. DSI_ERR("Invalid params\n");
  1613. return -EINVAL;
  1614. }
  1615. if (mmss_clamp && !display->phy_idle_power_off) {
  1616. dsi_display_phy_enable(display);
  1617. return 0;
  1618. }
  1619. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1620. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1621. if (rc) {
  1622. DSI_ERR("DSI controller setup failed\n");
  1623. return rc;
  1624. }
  1625. display_for_each_ctrl(i, display) {
  1626. ctrl = &display->ctrl[i];
  1627. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1628. continue;
  1629. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1630. if (rc) {
  1631. DSI_ERR("DSI controller setup failed\n");
  1632. return rc;
  1633. }
  1634. }
  1635. display->phy_idle_power_off = false;
  1636. return 0;
  1637. }
  1638. /**
  1639. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  1640. * @dsi_display: DSI display handle.
  1641. *
  1642. * Return: error code.
  1643. */
  1644. static int dsi_display_phy_idle_off(struct dsi_display *display)
  1645. {
  1646. int rc = 0;
  1647. int i = 0;
  1648. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1649. if (!display) {
  1650. DSI_ERR("Invalid params\n");
  1651. return -EINVAL;
  1652. }
  1653. display_for_each_ctrl(i, display) {
  1654. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1655. if (!phy)
  1656. continue;
  1657. if (!phy->allow_phy_power_off) {
  1658. DSI_DEBUG("phy doesn't support this feature\n");
  1659. return 0;
  1660. }
  1661. }
  1662. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1663. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  1664. if (rc) {
  1665. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  1666. display->name, rc);
  1667. return rc;
  1668. }
  1669. display_for_each_ctrl(i, display) {
  1670. ctrl = &display->ctrl[i];
  1671. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1672. continue;
  1673. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  1674. if (rc) {
  1675. DSI_ERR("DSI controller setup failed\n");
  1676. return rc;
  1677. }
  1678. }
  1679. display->phy_idle_power_off = true;
  1680. return 0;
  1681. }
  1682. void dsi_display_enable_event(struct drm_connector *connector,
  1683. struct dsi_display *display,
  1684. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  1685. bool enable)
  1686. {
  1687. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  1688. int i;
  1689. if (!display) {
  1690. DSI_ERR("invalid display\n");
  1691. return;
  1692. }
  1693. if (event_info)
  1694. event_info->event_idx = event_idx;
  1695. switch (event_idx) {
  1696. case SDE_CONN_EVENT_VID_DONE:
  1697. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  1698. break;
  1699. case SDE_CONN_EVENT_CMD_DONE:
  1700. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  1701. break;
  1702. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  1703. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  1704. if (event_info) {
  1705. display_for_each_ctrl(i, display)
  1706. display->ctrl[i].ctrl->recovery_cb =
  1707. *event_info;
  1708. }
  1709. break;
  1710. case SDE_CONN_EVENT_PANEL_ID:
  1711. if (event_info)
  1712. display_for_each_ctrl(i, display)
  1713. display->ctrl[i].ctrl->panel_id_cb
  1714. = *event_info;
  1715. break;
  1716. default:
  1717. /* nothing to do */
  1718. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  1719. return;
  1720. }
  1721. if (enable) {
  1722. display_for_each_ctrl(i, display)
  1723. dsi_ctrl_enable_status_interrupt(
  1724. display->ctrl[i].ctrl, irq_status_idx,
  1725. event_info);
  1726. } else {
  1727. display_for_each_ctrl(i, display)
  1728. dsi_ctrl_disable_status_interrupt(
  1729. display->ctrl[i].ctrl, irq_status_idx);
  1730. }
  1731. }
  1732. /**
  1733. * dsi_config_host_engine_state_for_cont_splash()- update host engine state
  1734. * during continuous splash.
  1735. * @display: Handle to dsi display
  1736. *
  1737. */
  1738. static void dsi_config_host_engine_state_for_cont_splash
  1739. (struct dsi_display *display)
  1740. {
  1741. int i;
  1742. struct dsi_display_ctrl *ctrl;
  1743. enum dsi_engine_state host_state = DSI_CTRL_ENGINE_ON;
  1744. /* Sequence does not matter for split dsi usecases */
  1745. display_for_each_ctrl(i, display) {
  1746. ctrl = &display->ctrl[i];
  1747. if (!ctrl->ctrl)
  1748. continue;
  1749. dsi_ctrl_update_host_engine_state_for_cont_splash(ctrl->ctrl,
  1750. host_state);
  1751. }
  1752. }
  1753. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  1754. {
  1755. int rc = 0;
  1756. int i;
  1757. struct dsi_display_ctrl *ctrl;
  1758. /* Sequence does not matter for split dsi usecases */
  1759. display_for_each_ctrl(i, display) {
  1760. ctrl = &display->ctrl[i];
  1761. if (!ctrl->ctrl)
  1762. continue;
  1763. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  1764. DSI_CTRL_POWER_VREG_ON);
  1765. if (rc) {
  1766. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  1767. ctrl->ctrl->name, rc);
  1768. goto error;
  1769. }
  1770. }
  1771. return rc;
  1772. error:
  1773. for (i = i - 1; i >= 0; i--) {
  1774. ctrl = &display->ctrl[i];
  1775. if (!ctrl->ctrl)
  1776. continue;
  1777. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  1778. DSI_CTRL_POWER_VREG_OFF);
  1779. }
  1780. return rc;
  1781. }
  1782. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  1783. {
  1784. int rc = 0;
  1785. int i;
  1786. struct dsi_display_ctrl *ctrl;
  1787. /* Sequence does not matter for split dsi usecases */
  1788. display_for_each_ctrl(i, display) {
  1789. ctrl = &display->ctrl[i];
  1790. if (!ctrl->ctrl)
  1791. continue;
  1792. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  1793. DSI_CTRL_POWER_VREG_OFF);
  1794. if (rc) {
  1795. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  1796. ctrl->ctrl->name, rc);
  1797. goto error;
  1798. }
  1799. }
  1800. error:
  1801. return rc;
  1802. }
  1803. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  1804. unsigned int display_type)
  1805. {
  1806. char *boot_str = NULL;
  1807. char *str = NULL;
  1808. char *sw_te = NULL;
  1809. unsigned long cmdline_topology = NO_OVERRIDE;
  1810. unsigned long cmdline_timing = NO_OVERRIDE;
  1811. unsigned long panel_id = NO_OVERRIDE;
  1812. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  1813. DSI_ERR("display_type=%d not supported\n", display_type);
  1814. goto end;
  1815. }
  1816. if (display_type == DSI_PRIMARY)
  1817. boot_str = dsi_display_primary;
  1818. else
  1819. boot_str = dsi_display_secondary;
  1820. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  1821. if (sw_te)
  1822. display->sw_te_using_wd = true;
  1823. str = strnstr(boot_str, ":panelid", strlen(boot_str));
  1824. if (str) {
  1825. if (kstrtol(str + strlen(":panelid"), INT_BASE_10,
  1826. (unsigned long *)&panel_id)) {
  1827. DSI_INFO("panel id not found: %s\n", boot_str);
  1828. } else {
  1829. DSI_INFO("panel id found: %lx\n", panel_id);
  1830. display->panel_id = panel_id;
  1831. }
  1832. }
  1833. str = strnstr(boot_str, ":config", strlen(boot_str));
  1834. if (str) {
  1835. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  1836. DSI_ERR("invalid config index override: %s\n",
  1837. boot_str);
  1838. goto end;
  1839. }
  1840. }
  1841. str = strnstr(boot_str, ":timing", strlen(boot_str));
  1842. if (str) {
  1843. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  1844. DSI_ERR("invalid timing index override: %s\n",
  1845. boot_str);
  1846. cmdline_topology = NO_OVERRIDE;
  1847. goto end;
  1848. }
  1849. }
  1850. DSI_DEBUG("successfully parsed command line topology and timing\n");
  1851. end:
  1852. display->cmdline_topology = cmdline_topology;
  1853. display->cmdline_timing = cmdline_timing;
  1854. }
  1855. /**
  1856. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  1857. *
  1858. * Return: returns error status
  1859. */
  1860. static int dsi_display_parse_boot_display_selection(void)
  1861. {
  1862. char *pos = NULL;
  1863. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  1864. int i, j;
  1865. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  1866. strlcpy(disp_buf, boot_displays[i].boot_param,
  1867. MAX_CMDLINE_PARAM_LEN);
  1868. pos = strnstr(disp_buf, ":", MAX_CMDLINE_PARAM_LEN);
  1869. /* Use ':' as a delimiter to retrieve the display name */
  1870. if (!pos) {
  1871. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  1872. continue;
  1873. }
  1874. for (j = 0; (disp_buf + j) < pos; j++)
  1875. boot_displays[i].name[j] = *(disp_buf + j);
  1876. boot_displays[i].name[j] = '\0';
  1877. boot_displays[i].boot_disp_en = true;
  1878. }
  1879. return 0;
  1880. }
  1881. static int dsi_display_phy_power_on(struct dsi_display *display)
  1882. {
  1883. int rc = 0;
  1884. int i;
  1885. struct dsi_display_ctrl *ctrl;
  1886. /* Sequence does not matter for split dsi usecases */
  1887. display_for_each_ctrl(i, display) {
  1888. ctrl = &display->ctrl[i];
  1889. if (!ctrl->ctrl)
  1890. continue;
  1891. rc = dsi_phy_set_power_state(ctrl->phy, true);
  1892. if (rc) {
  1893. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  1894. ctrl->phy->name, rc);
  1895. goto error;
  1896. }
  1897. }
  1898. return rc;
  1899. error:
  1900. for (i = i - 1; i >= 0; i--) {
  1901. ctrl = &display->ctrl[i];
  1902. if (!ctrl->phy)
  1903. continue;
  1904. (void)dsi_phy_set_power_state(ctrl->phy, false);
  1905. }
  1906. return rc;
  1907. }
  1908. static int dsi_display_phy_power_off(struct dsi_display *display)
  1909. {
  1910. int rc = 0;
  1911. int i;
  1912. struct dsi_display_ctrl *ctrl;
  1913. /* Sequence does not matter for split dsi usecases */
  1914. display_for_each_ctrl(i, display) {
  1915. ctrl = &display->ctrl[i];
  1916. if (!ctrl->phy)
  1917. continue;
  1918. rc = dsi_phy_set_power_state(ctrl->phy, false);
  1919. if (rc) {
  1920. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  1921. ctrl->ctrl->name, rc);
  1922. goto error;
  1923. }
  1924. }
  1925. error:
  1926. return rc;
  1927. }
  1928. static int dsi_display_set_clk_src(struct dsi_display *display)
  1929. {
  1930. int rc = 0;
  1931. int i;
  1932. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1933. /*
  1934. * For CPHY mode, the parent of mux_clks need to be set
  1935. * to Cphy_clks to have correct dividers for byte and
  1936. * pixel clocks.
  1937. */
  1938. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) {
  1939. rc = dsi_clk_update_parent(&display->clock_info.cphy_clks,
  1940. &display->clock_info.mux_clks);
  1941. if (rc) {
  1942. DSI_ERR("failed update mux parent to shadow\n");
  1943. return rc;
  1944. }
  1945. }
  1946. /*
  1947. * In case of split DSI usecases, the clock for master controller should
  1948. * be enabled before the other controller. Master controller in the
  1949. * clock context refers to the controller that sources the clock.
  1950. */
  1951. m_ctrl = &display->ctrl[display->clk_master_idx];
  1952. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
  1953. &display->clock_info.mux_clks);
  1954. if (rc) {
  1955. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n",
  1956. display->name, rc);
  1957. return rc;
  1958. }
  1959. /* Turn on rest of the controllers */
  1960. display_for_each_ctrl(i, display) {
  1961. ctrl = &display->ctrl[i];
  1962. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1963. continue;
  1964. rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
  1965. &display->clock_info.mux_clks);
  1966. if (rc) {
  1967. DSI_ERR("[%s] failed to set source clocks, rc=%d\n",
  1968. display->name, rc);
  1969. return rc;
  1970. }
  1971. }
  1972. return 0;
  1973. }
  1974. static int dsi_display_phy_reset_config(struct dsi_display *display,
  1975. bool enable)
  1976. {
  1977. int rc = 0;
  1978. int i;
  1979. struct dsi_display_ctrl *ctrl;
  1980. display_for_each_ctrl(i, display) {
  1981. ctrl = &display->ctrl[i];
  1982. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  1983. if (rc) {
  1984. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  1985. display->name, enable ? "mask" : "unmask", rc);
  1986. return rc;
  1987. }
  1988. }
  1989. return 0;
  1990. }
  1991. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  1992. {
  1993. struct dsi_display_ctrl *ctrl;
  1994. int i;
  1995. if (!display)
  1996. return;
  1997. display_for_each_ctrl(i, display) {
  1998. ctrl = &display->ctrl[i];
  1999. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2000. }
  2001. /*
  2002. * After retime buffer synchronization we need to turn of clk_en_sel
  2003. * bit on each phy. Avoid this for Cphy.
  2004. */
  2005. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2006. return;
  2007. display_for_each_ctrl(i, display) {
  2008. ctrl = &display->ctrl[i];
  2009. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2010. }
  2011. }
  2012. static int dsi_display_ctrl_update(struct dsi_display *display)
  2013. {
  2014. int rc = 0;
  2015. int i;
  2016. struct dsi_display_ctrl *ctrl;
  2017. display_for_each_ctrl(i, display) {
  2018. ctrl = &display->ctrl[i];
  2019. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2020. if (rc) {
  2021. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2022. display->name, i, rc);
  2023. goto error_host_deinit;
  2024. }
  2025. }
  2026. return 0;
  2027. error_host_deinit:
  2028. for (i = i - 1; i >= 0; i--) {
  2029. ctrl = &display->ctrl[i];
  2030. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2031. }
  2032. return rc;
  2033. }
  2034. static int dsi_display_ctrl_init(struct dsi_display *display)
  2035. {
  2036. int rc = 0;
  2037. int i;
  2038. struct dsi_display_ctrl *ctrl;
  2039. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2040. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2041. * we will programe DSI controller as part of core clock enable.
  2042. * After that we should not re-configure DSI controller again here for
  2043. * usecases where we are resuming from ulps suspend as it might put
  2044. * the HW in bad state.
  2045. */
  2046. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2047. display_for_each_ctrl(i, display) {
  2048. ctrl = &display->ctrl[i];
  2049. rc = dsi_ctrl_host_init(ctrl->ctrl,
  2050. display->is_cont_splash_enabled);
  2051. if (rc) {
  2052. DSI_ERR("[%s] failed to init host_%d, rc=%d\n",
  2053. display->name, i, rc);
  2054. goto error_host_deinit;
  2055. }
  2056. }
  2057. } else {
  2058. display_for_each_ctrl(i, display) {
  2059. ctrl = &display->ctrl[i];
  2060. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2061. DSI_CTRL_OP_HOST_INIT,
  2062. true);
  2063. if (rc)
  2064. DSI_DEBUG("host init update failed rc=%d\n",
  2065. rc);
  2066. }
  2067. }
  2068. return rc;
  2069. error_host_deinit:
  2070. for (i = i - 1; i >= 0; i--) {
  2071. ctrl = &display->ctrl[i];
  2072. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2073. }
  2074. return rc;
  2075. }
  2076. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2077. {
  2078. int rc = 0;
  2079. int i;
  2080. struct dsi_display_ctrl *ctrl;
  2081. display_for_each_ctrl(i, display) {
  2082. ctrl = &display->ctrl[i];
  2083. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2084. if (rc) {
  2085. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2086. display->name, i, rc);
  2087. }
  2088. }
  2089. return rc;
  2090. }
  2091. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2092. {
  2093. int rc = 0;
  2094. int i;
  2095. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2096. /* Host engine states are already taken care for
  2097. * continuous splash case
  2098. */
  2099. if (display->is_cont_splash_enabled) {
  2100. DSI_DEBUG("cont splash enabled, host enable not required\n");
  2101. return 0;
  2102. }
  2103. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2104. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
  2105. if (rc) {
  2106. DSI_ERR("[%s] failed to enable host engine, rc=%d\n",
  2107. display->name, rc);
  2108. goto error;
  2109. }
  2110. display_for_each_ctrl(i, display) {
  2111. ctrl = &display->ctrl[i];
  2112. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2113. continue;
  2114. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2115. DSI_CTRL_ENGINE_ON);
  2116. if (rc) {
  2117. DSI_ERR("[%s] failed to enable sl host engine, rc=%d\n",
  2118. display->name, rc);
  2119. goto error_disable_master;
  2120. }
  2121. }
  2122. return rc;
  2123. error_disable_master:
  2124. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
  2125. error:
  2126. return rc;
  2127. }
  2128. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2129. {
  2130. int rc = 0;
  2131. int i;
  2132. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2133. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2134. /*
  2135. * For platforms where ULPS is controlled by DSI controller block,
  2136. * do not disable dsi controller block if lanes are to be
  2137. * kept in ULPS during suspend. So just update the SW state
  2138. * and return early.
  2139. */
  2140. if (display->panel->ulps_suspend_enabled &&
  2141. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2142. display_for_each_ctrl(i, display) {
  2143. ctrl = &display->ctrl[i];
  2144. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2145. DSI_CTRL_OP_HOST_ENGINE,
  2146. false);
  2147. if (rc)
  2148. DSI_DEBUG("host state update failed %d\n", rc);
  2149. }
  2150. return rc;
  2151. }
  2152. display_for_each_ctrl(i, display) {
  2153. ctrl = &display->ctrl[i];
  2154. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2155. continue;
  2156. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2157. DSI_CTRL_ENGINE_OFF);
  2158. if (rc)
  2159. DSI_ERR("[%s] failed to disable host engine, rc=%d\n",
  2160. display->name, rc);
  2161. }
  2162. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
  2163. if (rc) {
  2164. DSI_ERR("[%s] failed to disable host engine, rc=%d\n",
  2165. display->name, rc);
  2166. goto error;
  2167. }
  2168. error:
  2169. return rc;
  2170. }
  2171. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2172. {
  2173. int rc = 0;
  2174. int i;
  2175. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2176. m_ctrl = &display->ctrl[display->video_master_idx];
  2177. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
  2178. if (rc) {
  2179. DSI_ERR("[%s] failed to enable vid engine, rc=%d\n",
  2180. display->name, rc);
  2181. goto error;
  2182. }
  2183. display_for_each_ctrl(i, display) {
  2184. ctrl = &display->ctrl[i];
  2185. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2186. continue;
  2187. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2188. DSI_CTRL_ENGINE_ON);
  2189. if (rc) {
  2190. DSI_ERR("[%s] failed to enable vid engine, rc=%d\n",
  2191. display->name, rc);
  2192. goto error_disable_master;
  2193. }
  2194. }
  2195. return rc;
  2196. error_disable_master:
  2197. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
  2198. error:
  2199. return rc;
  2200. }
  2201. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2202. {
  2203. int rc = 0;
  2204. int i;
  2205. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2206. m_ctrl = &display->ctrl[display->video_master_idx];
  2207. display_for_each_ctrl(i, display) {
  2208. ctrl = &display->ctrl[i];
  2209. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2210. continue;
  2211. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2212. DSI_CTRL_ENGINE_OFF);
  2213. if (rc)
  2214. DSI_ERR("[%s] failed to disable vid engine, rc=%d\n",
  2215. display->name, rc);
  2216. }
  2217. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
  2218. if (rc)
  2219. DSI_ERR("[%s] failed to disable mvid engine, rc=%d\n",
  2220. display->name, rc);
  2221. return rc;
  2222. }
  2223. static int dsi_display_phy_enable(struct dsi_display *display)
  2224. {
  2225. int rc = 0;
  2226. int i;
  2227. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2228. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2229. m_ctrl = &display->ctrl[display->clk_master_idx];
  2230. if (display->ctrl_count > 1)
  2231. m_src = DSI_PLL_SOURCE_NATIVE;
  2232. rc = dsi_phy_enable(m_ctrl->phy,
  2233. &display->config,
  2234. m_src,
  2235. true,
  2236. display->is_cont_splash_enabled);
  2237. if (rc) {
  2238. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  2239. display->name, rc);
  2240. goto error;
  2241. }
  2242. display_for_each_ctrl(i, display) {
  2243. ctrl = &display->ctrl[i];
  2244. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2245. continue;
  2246. rc = dsi_phy_enable(ctrl->phy,
  2247. &display->config,
  2248. DSI_PLL_SOURCE_NON_NATIVE,
  2249. true,
  2250. display->is_cont_splash_enabled);
  2251. if (rc) {
  2252. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  2253. display->name, rc);
  2254. goto error_disable_master;
  2255. }
  2256. }
  2257. return rc;
  2258. error_disable_master:
  2259. (void)dsi_phy_disable(m_ctrl->phy);
  2260. error:
  2261. return rc;
  2262. }
  2263. static int dsi_display_phy_disable(struct dsi_display *display)
  2264. {
  2265. int rc = 0;
  2266. int i;
  2267. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2268. m_ctrl = &display->ctrl[display->clk_master_idx];
  2269. display_for_each_ctrl(i, display) {
  2270. ctrl = &display->ctrl[i];
  2271. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2272. continue;
  2273. rc = dsi_phy_disable(ctrl->phy);
  2274. if (rc)
  2275. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  2276. display->name, rc);
  2277. }
  2278. rc = dsi_phy_disable(m_ctrl->phy);
  2279. if (rc)
  2280. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  2281. display->name, rc);
  2282. return rc;
  2283. }
  2284. static int dsi_display_wake_up(struct dsi_display *display)
  2285. {
  2286. return 0;
  2287. }
  2288. static int dsi_display_broadcast_cmd(struct dsi_display *display,
  2289. const struct mipi_dsi_msg *msg)
  2290. {
  2291. int rc = 0;
  2292. u32 flags, m_flags;
  2293. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2294. int i;
  2295. m_flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_BROADCAST_MASTER |
  2296. DSI_CTRL_CMD_DEFER_TRIGGER | DSI_CTRL_CMD_FETCH_MEMORY);
  2297. flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER |
  2298. DSI_CTRL_CMD_FETCH_MEMORY);
  2299. if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) {
  2300. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  2301. m_flags |= DSI_CTRL_CMD_LAST_COMMAND;
  2302. }
  2303. if (display->queue_cmd_waits ||
  2304. msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE) {
  2305. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2306. m_flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2307. }
  2308. /*
  2309. * 1. Setup commands in FIFO
  2310. * 2. Trigger commands
  2311. */
  2312. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2313. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, msg, &m_flags);
  2314. if (rc) {
  2315. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2316. display->name, rc);
  2317. goto error;
  2318. }
  2319. display_for_each_ctrl(i, display) {
  2320. ctrl = &display->ctrl[i];
  2321. if (ctrl == m_ctrl)
  2322. continue;
  2323. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, msg, &flags);
  2324. if (rc) {
  2325. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2326. display->name, rc);
  2327. goto error;
  2328. }
  2329. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, flags);
  2330. if (rc) {
  2331. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2332. display->name, rc);
  2333. goto error;
  2334. }
  2335. }
  2336. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, m_flags);
  2337. if (rc) {
  2338. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2339. display->name, rc);
  2340. goto error;
  2341. }
  2342. error:
  2343. return rc;
  2344. }
  2345. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2346. {
  2347. int rc = 0;
  2348. int i;
  2349. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2350. /* For continuous splash use case ctrl states are updated
  2351. * separately and hence we do an early return
  2352. */
  2353. if (display->is_cont_splash_enabled) {
  2354. DSI_DEBUG("cont splash enabled, phy sw reset not required\n");
  2355. return 0;
  2356. }
  2357. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2358. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2359. if (rc) {
  2360. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2361. goto error;
  2362. }
  2363. display_for_each_ctrl(i, display) {
  2364. ctrl = &display->ctrl[i];
  2365. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2366. continue;
  2367. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2368. if (rc) {
  2369. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2370. display->name, rc);
  2371. goto error;
  2372. }
  2373. }
  2374. error:
  2375. return rc;
  2376. }
  2377. static int dsi_host_attach(struct mipi_dsi_host *host,
  2378. struct mipi_dsi_device *dsi)
  2379. {
  2380. return 0;
  2381. }
  2382. static int dsi_host_detach(struct mipi_dsi_host *host,
  2383. struct mipi_dsi_device *dsi)
  2384. {
  2385. return 0;
  2386. }
  2387. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
  2388. const struct mipi_dsi_msg *msg)
  2389. {
  2390. struct dsi_display *display;
  2391. int rc = 0, ret = 0;
  2392. if (!host || !msg) {
  2393. DSI_ERR("Invalid params\n");
  2394. return 0;
  2395. }
  2396. display = to_dsi_display(host);
  2397. /* Avoid sending DCS commands when ESD recovery is pending */
  2398. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2399. DSI_DEBUG("ESD recovery pending\n");
  2400. return 0;
  2401. }
  2402. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2403. DSI_ALL_CLKS, DSI_CLK_ON);
  2404. if (rc) {
  2405. DSI_ERR("[%s] failed to enable all DSI clocks, rc=%d\n",
  2406. display->name, rc);
  2407. goto error;
  2408. }
  2409. rc = dsi_display_wake_up(display);
  2410. if (rc) {
  2411. DSI_ERR("[%s] failed to wake up display, rc=%d\n",
  2412. display->name, rc);
  2413. goto error_disable_clks;
  2414. }
  2415. rc = dsi_display_cmd_engine_enable(display);
  2416. if (rc) {
  2417. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2418. display->name, rc);
  2419. goto error_disable_clks;
  2420. }
  2421. if (display->tx_cmd_buf == NULL) {
  2422. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2423. if (rc) {
  2424. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2425. goto error_disable_cmd_engine;
  2426. }
  2427. }
  2428. if (display->ctrl_count > 1 && !(msg->flags & MIPI_DSI_MSG_UNICAST)) {
  2429. rc = dsi_display_broadcast_cmd(display, msg);
  2430. if (rc) {
  2431. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n",
  2432. display->name, rc);
  2433. goto error_disable_cmd_engine;
  2434. }
  2435. } else {
  2436. int ctrl_idx = (msg->flags & MIPI_DSI_MSG_UNICAST) ?
  2437. msg->ctrl : 0;
  2438. u32 cmd_flags = DSI_CTRL_CMD_FETCH_MEMORY;
  2439. if (display->queue_cmd_waits ||
  2440. msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  2441. cmd_flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2442. rc = dsi_ctrl_cmd_transfer(display->ctrl[ctrl_idx].ctrl, msg,
  2443. &cmd_flags);
  2444. if (rc) {
  2445. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2446. display->name, rc);
  2447. goto error_disable_cmd_engine;
  2448. }
  2449. }
  2450. error_disable_cmd_engine:
  2451. ret = dsi_display_cmd_engine_disable(display);
  2452. if (ret) {
  2453. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  2454. display->name, ret);
  2455. }
  2456. error_disable_clks:
  2457. ret = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2458. DSI_ALL_CLKS, DSI_CLK_OFF);
  2459. if (ret) {
  2460. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  2461. display->name, ret);
  2462. }
  2463. error:
  2464. return rc;
  2465. }
  2466. static struct mipi_dsi_host_ops dsi_host_ops = {
  2467. .attach = dsi_host_attach,
  2468. .detach = dsi_host_detach,
  2469. .transfer = dsi_host_transfer,
  2470. };
  2471. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2472. {
  2473. int rc = 0;
  2474. struct mipi_dsi_host *host = &display->host;
  2475. host->dev = &display->pdev->dev;
  2476. host->ops = &dsi_host_ops;
  2477. rc = mipi_dsi_host_register(host);
  2478. if (rc) {
  2479. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2480. display->name, rc);
  2481. goto error;
  2482. }
  2483. error:
  2484. return rc;
  2485. }
  2486. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2487. {
  2488. int rc = 0;
  2489. struct mipi_dsi_host *host = &display->host;
  2490. mipi_dsi_host_unregister(host);
  2491. host->dev = NULL;
  2492. host->ops = NULL;
  2493. return rc;
  2494. }
  2495. static int dsi_display_clocks_deinit(struct dsi_display *display)
  2496. {
  2497. int rc = 0;
  2498. struct dsi_clk_link_set *src = &display->clock_info.src_clks;
  2499. struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
  2500. struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
  2501. if (src->byte_clk) {
  2502. devm_clk_put(&display->pdev->dev, src->byte_clk);
  2503. src->byte_clk = NULL;
  2504. }
  2505. if (src->pixel_clk) {
  2506. devm_clk_put(&display->pdev->dev, src->pixel_clk);
  2507. src->pixel_clk = NULL;
  2508. }
  2509. if (mux->byte_clk) {
  2510. devm_clk_put(&display->pdev->dev, mux->byte_clk);
  2511. mux->byte_clk = NULL;
  2512. }
  2513. if (mux->pixel_clk) {
  2514. devm_clk_put(&display->pdev->dev, mux->pixel_clk);
  2515. mux->pixel_clk = NULL;
  2516. }
  2517. if (shadow->byte_clk) {
  2518. devm_clk_put(&display->pdev->dev, shadow->byte_clk);
  2519. shadow->byte_clk = NULL;
  2520. }
  2521. if (shadow->pixel_clk) {
  2522. devm_clk_put(&display->pdev->dev, shadow->pixel_clk);
  2523. shadow->pixel_clk = NULL;
  2524. }
  2525. return rc;
  2526. }
  2527. static bool dsi_display_check_prefix(const char *clk_prefix,
  2528. const char *clk_name)
  2529. {
  2530. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2531. }
  2532. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2533. char *dsi_clk_name)
  2534. {
  2535. if (display->fw)
  2536. return dsi_parser_count_strings(display->parser_node,
  2537. dsi_clk_name);
  2538. else
  2539. return of_property_count_strings(display->panel_node,
  2540. dsi_clk_name);
  2541. }
  2542. static void dsi_display_get_clock_name(struct dsi_display *display,
  2543. char *dsi_clk_name, int index,
  2544. const char **clk_name)
  2545. {
  2546. if (display->fw)
  2547. dsi_parser_read_string_index(display->parser_node,
  2548. dsi_clk_name, index, clk_name);
  2549. else
  2550. of_property_read_string_index(display->panel_node,
  2551. dsi_clk_name, index, clk_name);
  2552. }
  2553. static int dsi_display_clocks_init(struct dsi_display *display)
  2554. {
  2555. int i, rc = 0, num_clk = 0;
  2556. const char *clk_name;
  2557. const char *src_byte = "src_byte", *src_pixel = "src_pixel";
  2558. const char *mux_byte = "mux_byte", *mux_pixel = "mux_pixel";
  2559. const char *cphy_byte = "cphy_byte", *cphy_pixel = "cphy_pixel";
  2560. const char *shadow_byte = "shadow_byte", *shadow_pixel = "shadow_pixel";
  2561. struct clk *dsi_clk;
  2562. struct dsi_clk_link_set *src = &display->clock_info.src_clks;
  2563. struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
  2564. struct dsi_clk_link_set *cphy = &display->clock_info.cphy_clks;
  2565. struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
  2566. struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);
  2567. char *dsi_clock_name;
  2568. if (!strcmp(display->display_type, "primary"))
  2569. dsi_clock_name = "qcom,dsi-select-clocks";
  2570. else
  2571. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2572. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2573. DSI_DEBUG("clk count=%d\n", num_clk);
  2574. for (i = 0; i < num_clk; i++) {
  2575. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2576. &clk_name);
  2577. DSI_DEBUG("clock name:%s\n", clk_name);
  2578. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2579. if (IS_ERR_OR_NULL(dsi_clk)) {
  2580. rc = PTR_ERR(dsi_clk);
  2581. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2582. if (dsi_display_check_prefix(mux_byte, clk_name)) {
  2583. mux->byte_clk = NULL;
  2584. goto error;
  2585. }
  2586. if (dsi_display_check_prefix(mux_pixel, clk_name)) {
  2587. mux->pixel_clk = NULL;
  2588. goto error;
  2589. }
  2590. if (dsi_display_check_prefix(cphy_byte, clk_name)) {
  2591. cphy->byte_clk = NULL;
  2592. goto error;
  2593. }
  2594. if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
  2595. cphy->pixel_clk = NULL;
  2596. goto error;
  2597. }
  2598. if (dyn_clk_caps->dyn_clk_support &&
  2599. (display->panel->panel_mode ==
  2600. DSI_OP_VIDEO_MODE)) {
  2601. if (dsi_display_check_prefix(src_byte,
  2602. clk_name))
  2603. src->byte_clk = NULL;
  2604. if (dsi_display_check_prefix(src_pixel,
  2605. clk_name))
  2606. src->pixel_clk = NULL;
  2607. if (dsi_display_check_prefix(shadow_byte,
  2608. clk_name))
  2609. shadow->byte_clk = NULL;
  2610. if (dsi_display_check_prefix(shadow_pixel,
  2611. clk_name))
  2612. shadow->pixel_clk = NULL;
  2613. dyn_clk_caps->dyn_clk_support = false;
  2614. }
  2615. }
  2616. if (dsi_display_check_prefix(src_byte, clk_name)) {
  2617. src->byte_clk = dsi_clk;
  2618. continue;
  2619. }
  2620. if (dsi_display_check_prefix(src_pixel, clk_name)) {
  2621. src->pixel_clk = dsi_clk;
  2622. continue;
  2623. }
  2624. if (dsi_display_check_prefix(cphy_byte, clk_name)) {
  2625. cphy->byte_clk = dsi_clk;
  2626. continue;
  2627. }
  2628. if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
  2629. cphy->pixel_clk = dsi_clk;
  2630. continue;
  2631. }
  2632. if (dsi_display_check_prefix(mux_byte, clk_name)) {
  2633. mux->byte_clk = dsi_clk;
  2634. continue;
  2635. }
  2636. if (dsi_display_check_prefix(mux_pixel, clk_name)) {
  2637. mux->pixel_clk = dsi_clk;
  2638. continue;
  2639. }
  2640. if (dsi_display_check_prefix(shadow_byte, clk_name)) {
  2641. shadow->byte_clk = dsi_clk;
  2642. continue;
  2643. }
  2644. if (dsi_display_check_prefix(shadow_pixel, clk_name)) {
  2645. shadow->pixel_clk = dsi_clk;
  2646. continue;
  2647. }
  2648. }
  2649. return 0;
  2650. error:
  2651. (void)dsi_display_clocks_deinit(display);
  2652. return rc;
  2653. }
  2654. static int dsi_display_clk_ctrl_cb(void *priv,
  2655. struct dsi_clk_ctrl_info clk_state_info)
  2656. {
  2657. int rc = 0;
  2658. struct dsi_display *display = NULL;
  2659. void *clk_handle = NULL;
  2660. if (!priv) {
  2661. DSI_ERR("Invalid params\n");
  2662. return -EINVAL;
  2663. }
  2664. display = priv;
  2665. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2666. clk_handle = display->mdp_clk_handle;
  2667. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2668. clk_handle = display->dsi_clk_handle;
  2669. } else {
  2670. DSI_ERR("invalid clk handle, return error\n");
  2671. return -EINVAL;
  2672. }
  2673. /*
  2674. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2675. * to turn off DSI clocks.
  2676. */
  2677. rc = dsi_display_clk_ctrl(clk_handle,
  2678. clk_state_info.clk_type, clk_state_info.clk_state);
  2679. if (rc) {
  2680. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2681. display->name, clk_state_info.clk_state,
  2682. clk_state_info.clk_type, rc);
  2683. return rc;
  2684. }
  2685. return 0;
  2686. }
  2687. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  2688. {
  2689. int i;
  2690. struct dsi_display_ctrl *ctrl;
  2691. if (!display)
  2692. return;
  2693. display_for_each_ctrl(i, display) {
  2694. ctrl = &display->ctrl[i];
  2695. if (!ctrl)
  2696. continue;
  2697. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  2698. }
  2699. }
  2700. int dsi_pre_clkoff_cb(void *priv,
  2701. enum dsi_clk_type clk,
  2702. enum dsi_lclk_type l_type,
  2703. enum dsi_clk_state new_state)
  2704. {
  2705. int rc = 0, i;
  2706. struct dsi_display *display = priv;
  2707. struct dsi_display_ctrl *ctrl;
  2708. /*
  2709. * If Idle Power Collapse occurs immediately after a CMD
  2710. * transfer with an asynchronous wait for DMA done, ensure
  2711. * that the work queued is scheduled and completed before turning
  2712. * off the clocks and disabling interrupts to validate the command
  2713. * transfer.
  2714. */
  2715. display_for_each_ctrl(i, display) {
  2716. ctrl = &display->ctrl[i];
  2717. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  2718. continue;
  2719. flush_workqueue(display->dma_cmd_workq);
  2720. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  2721. ctrl->ctrl->dma_wait_queued = false;
  2722. }
  2723. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2724. (l_type & DSI_LINK_LP_CLK)) {
  2725. /*
  2726. * If continuous clock is enabled then disable it
  2727. * before entering into ULPS Mode.
  2728. */
  2729. if (display->panel->host_config.force_hs_clk_lane)
  2730. _dsi_display_continuous_clk_ctrl(display, false);
  2731. /*
  2732. * If ULPS feature is enabled, enter ULPS first.
  2733. * However, when blanking the panel, we should enter ULPS
  2734. * only if ULPS during suspend feature is enabled.
  2735. */
  2736. if (!dsi_panel_initialized(display->panel)) {
  2737. if (display->panel->ulps_suspend_enabled)
  2738. rc = dsi_display_set_ulps(display, true);
  2739. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  2740. rc = dsi_display_set_ulps(display, true);
  2741. }
  2742. if (rc)
  2743. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  2744. __func__, rc);
  2745. }
  2746. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2747. (l_type & DSI_LINK_HS_CLK)) {
  2748. /*
  2749. * PHY clock gating should be disabled before the PLL and the
  2750. * branch clocks are turned off. Otherwise, it is possible that
  2751. * the clock RCGs may not be turned off correctly resulting
  2752. * in clock warnings.
  2753. */
  2754. rc = dsi_display_config_clk_gating(display, false);
  2755. if (rc)
  2756. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  2757. display->name, rc);
  2758. }
  2759. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  2760. /*
  2761. * Enable DSI clamps only if entering idle power collapse or
  2762. * when ULPS during suspend is enabled..
  2763. */
  2764. if (dsi_panel_initialized(display->panel) ||
  2765. display->panel->ulps_suspend_enabled) {
  2766. dsi_display_phy_idle_off(display);
  2767. rc = dsi_display_set_clamp(display, true);
  2768. if (rc)
  2769. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  2770. __func__, rc);
  2771. rc = dsi_display_phy_reset_config(display, false);
  2772. if (rc)
  2773. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  2774. __func__, rc);
  2775. } else {
  2776. /* Make sure that controller is not in ULPS state when
  2777. * the DSI link is not active.
  2778. */
  2779. rc = dsi_display_set_ulps(display, false);
  2780. if (rc)
  2781. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  2782. __func__, rc);
  2783. }
  2784. /* dsi will not be able to serve irqs from here on */
  2785. dsi_display_ctrl_irq_update(display, false);
  2786. /* cache the MISR values */
  2787. display_for_each_ctrl(i, display) {
  2788. ctrl = &display->ctrl[i];
  2789. if (!ctrl->ctrl)
  2790. continue;
  2791. dsi_ctrl_cache_misr(ctrl->ctrl);
  2792. }
  2793. }
  2794. return rc;
  2795. }
  2796. int dsi_post_clkon_cb(void *priv,
  2797. enum dsi_clk_type clk,
  2798. enum dsi_lclk_type l_type,
  2799. enum dsi_clk_state curr_state)
  2800. {
  2801. int rc = 0;
  2802. struct dsi_display *display = priv;
  2803. bool mmss_clamp = false;
  2804. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  2805. mmss_clamp = display->clamp_enabled;
  2806. /*
  2807. * controller setup is needed if coming out of idle
  2808. * power collapse with clamps enabled.
  2809. */
  2810. if (mmss_clamp)
  2811. dsi_display_ctrl_setup(display);
  2812. /*
  2813. * Phy setup is needed if coming out of idle
  2814. * power collapse with clamps enabled.
  2815. */
  2816. if (display->phy_idle_power_off || mmss_clamp)
  2817. dsi_display_phy_idle_on(display, mmss_clamp);
  2818. if (display->ulps_enabled && mmss_clamp) {
  2819. /*
  2820. * ULPS Entry Request. This is needed if the lanes were
  2821. * in ULPS prior to power collapse, since after
  2822. * power collapse and reset, the DSI controller resets
  2823. * back to idle state and not ULPS. This ulps entry
  2824. * request will transition the state of the DSI
  2825. * controller to ULPS which will match the state of the
  2826. * DSI phy. This needs to be done prior to disabling
  2827. * the DSI clamps.
  2828. *
  2829. * Also, reset the ulps flag so that ulps_config
  2830. * function would reconfigure the controller state to
  2831. * ULPS.
  2832. */
  2833. display->ulps_enabled = false;
  2834. rc = dsi_display_set_ulps(display, true);
  2835. if (rc) {
  2836. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  2837. __func__, rc);
  2838. goto error;
  2839. }
  2840. }
  2841. rc = dsi_display_phy_reset_config(display, true);
  2842. if (rc) {
  2843. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  2844. __func__, rc);
  2845. goto error;
  2846. }
  2847. rc = dsi_display_set_clamp(display, false);
  2848. if (rc) {
  2849. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  2850. __func__, rc);
  2851. goto error;
  2852. }
  2853. }
  2854. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  2855. /*
  2856. * Toggle the resync FIFO everytime clock changes, except
  2857. * when cont-splash screen transition is going on.
  2858. * Toggling resync FIFO during cont splash transition
  2859. * can lead to blinks on the display.
  2860. */
  2861. if (!display->is_cont_splash_enabled)
  2862. dsi_display_toggle_resync_fifo(display);
  2863. if (display->ulps_enabled) {
  2864. rc = dsi_display_set_ulps(display, false);
  2865. if (rc) {
  2866. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  2867. __func__, rc);
  2868. goto error;
  2869. }
  2870. }
  2871. if (display->panel->host_config.force_hs_clk_lane)
  2872. _dsi_display_continuous_clk_ctrl(display, true);
  2873. rc = dsi_display_config_clk_gating(display, true);
  2874. if (rc) {
  2875. DSI_ERR("[%s] failed to enable clk gating %d\n",
  2876. display->name, rc);
  2877. goto error;
  2878. }
  2879. }
  2880. /* enable dsi to serve irqs */
  2881. if (clk & DSI_CORE_CLK)
  2882. dsi_display_ctrl_irq_update(display, true);
  2883. error:
  2884. return rc;
  2885. }
  2886. int dsi_post_clkoff_cb(void *priv,
  2887. enum dsi_clk_type clk_type,
  2888. enum dsi_lclk_type l_type,
  2889. enum dsi_clk_state curr_state)
  2890. {
  2891. int rc = 0;
  2892. struct dsi_display *display = priv;
  2893. if (!display) {
  2894. DSI_ERR("%s: Invalid arg\n", __func__);
  2895. return -EINVAL;
  2896. }
  2897. if ((clk_type & DSI_CORE_CLK) &&
  2898. (curr_state == DSI_CLK_OFF)) {
  2899. rc = dsi_display_phy_power_off(display);
  2900. if (rc)
  2901. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  2902. display->name, rc);
  2903. rc = dsi_display_ctrl_power_off(display);
  2904. if (rc)
  2905. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  2906. display->name, rc);
  2907. }
  2908. return rc;
  2909. }
  2910. int dsi_pre_clkon_cb(void *priv,
  2911. enum dsi_clk_type clk_type,
  2912. enum dsi_lclk_type l_type,
  2913. enum dsi_clk_state new_state)
  2914. {
  2915. int rc = 0;
  2916. struct dsi_display *display = priv;
  2917. if (!display) {
  2918. DSI_ERR("%s: invalid input\n", __func__);
  2919. return -EINVAL;
  2920. }
  2921. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  2922. /*
  2923. * Enable DSI core power
  2924. * 1.> PANEL_PM are controlled as part of
  2925. * panel_power_ctrl. Needed not be handled here.
  2926. * 2.> CORE_PM are controlled by dsi clk manager.
  2927. * 3.> CTRL_PM need to be enabled/disabled
  2928. * only during unblank/blank. Their state should
  2929. * not be changed during static screen.
  2930. */
  2931. DSI_DEBUG("updating power states for ctrl and phy\n");
  2932. rc = dsi_display_ctrl_power_on(display);
  2933. if (rc) {
  2934. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  2935. display->name, rc);
  2936. return rc;
  2937. }
  2938. rc = dsi_display_phy_power_on(display);
  2939. if (rc) {
  2940. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  2941. display->name, rc);
  2942. return rc;
  2943. }
  2944. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  2945. }
  2946. return rc;
  2947. }
  2948. static void __set_lane_map_v2(u8 *lane_map_v2,
  2949. enum dsi_phy_data_lanes lane0,
  2950. enum dsi_phy_data_lanes lane1,
  2951. enum dsi_phy_data_lanes lane2,
  2952. enum dsi_phy_data_lanes lane3)
  2953. {
  2954. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  2955. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  2956. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  2957. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  2958. }
  2959. static int dsi_display_parse_lane_map(struct dsi_display *display)
  2960. {
  2961. int rc = 0, i = 0;
  2962. const char *data;
  2963. u8 temp[DSI_LANE_MAX - 1];
  2964. if (!display) {
  2965. DSI_ERR("invalid params\n");
  2966. return -EINVAL;
  2967. }
  2968. /* lane-map-v2 supersedes lane-map-v1 setting */
  2969. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  2970. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  2971. if (!rc) {
  2972. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  2973. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  2974. return 0;
  2975. } else if (rc != EINVAL) {
  2976. DSI_DEBUG("Incorrect mapping, configure default\n");
  2977. goto set_default;
  2978. }
  2979. /* lane-map older version, for DSI controller version < 2.0 */
  2980. data = of_get_property(display->pdev->dev.of_node,
  2981. "qcom,lane-map", NULL);
  2982. if (!data)
  2983. goto set_default;
  2984. if (!strcmp(data, "lane_map_3012")) {
  2985. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  2986. __set_lane_map_v2(display->lane_map.lane_map_v2,
  2987. DSI_PHYSICAL_LANE_1,
  2988. DSI_PHYSICAL_LANE_2,
  2989. DSI_PHYSICAL_LANE_3,
  2990. DSI_PHYSICAL_LANE_0);
  2991. } else if (!strcmp(data, "lane_map_2301")) {
  2992. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  2993. __set_lane_map_v2(display->lane_map.lane_map_v2,
  2994. DSI_PHYSICAL_LANE_2,
  2995. DSI_PHYSICAL_LANE_3,
  2996. DSI_PHYSICAL_LANE_0,
  2997. DSI_PHYSICAL_LANE_1);
  2998. } else if (!strcmp(data, "lane_map_1230")) {
  2999. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3000. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3001. DSI_PHYSICAL_LANE_3,
  3002. DSI_PHYSICAL_LANE_0,
  3003. DSI_PHYSICAL_LANE_1,
  3004. DSI_PHYSICAL_LANE_2);
  3005. } else if (!strcmp(data, "lane_map_0321")) {
  3006. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3007. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3008. DSI_PHYSICAL_LANE_0,
  3009. DSI_PHYSICAL_LANE_3,
  3010. DSI_PHYSICAL_LANE_2,
  3011. DSI_PHYSICAL_LANE_1);
  3012. } else if (!strcmp(data, "lane_map_1032")) {
  3013. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3014. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3015. DSI_PHYSICAL_LANE_1,
  3016. DSI_PHYSICAL_LANE_0,
  3017. DSI_PHYSICAL_LANE_3,
  3018. DSI_PHYSICAL_LANE_2);
  3019. } else if (!strcmp(data, "lane_map_2103")) {
  3020. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3021. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3022. DSI_PHYSICAL_LANE_2,
  3023. DSI_PHYSICAL_LANE_1,
  3024. DSI_PHYSICAL_LANE_0,
  3025. DSI_PHYSICAL_LANE_3);
  3026. } else if (!strcmp(data, "lane_map_3210")) {
  3027. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3028. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3029. DSI_PHYSICAL_LANE_3,
  3030. DSI_PHYSICAL_LANE_2,
  3031. DSI_PHYSICAL_LANE_1,
  3032. DSI_PHYSICAL_LANE_0);
  3033. } else {
  3034. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3035. __func__, data);
  3036. goto set_default;
  3037. }
  3038. return 0;
  3039. set_default:
  3040. /* default lane mapping */
  3041. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3042. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3043. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3044. return 0;
  3045. }
  3046. static int dsi_display_get_phandle_index(
  3047. struct dsi_display *display,
  3048. const char *propname, int count, int index)
  3049. {
  3050. struct device_node *disp_node = display->panel_node;
  3051. u32 *val = NULL;
  3052. int rc = 0;
  3053. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3054. if (ZERO_OR_NULL_PTR(val)) {
  3055. rc = -ENOMEM;
  3056. goto end;
  3057. }
  3058. if (index >= count)
  3059. goto end;
  3060. if (display->fw)
  3061. rc = dsi_parser_read_u32_array(display->parser_node,
  3062. propname, val, count);
  3063. else
  3064. rc = of_property_read_u32_array(disp_node, propname,
  3065. val, count);
  3066. if (rc)
  3067. goto end;
  3068. rc = val[index];
  3069. DSI_DEBUG("%s index=%d\n", propname, rc);
  3070. end:
  3071. kfree(val);
  3072. return rc;
  3073. }
  3074. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3075. const char *propname)
  3076. {
  3077. if (display->fw)
  3078. return dsi_parser_count_u32_elems(display->parser_node,
  3079. propname);
  3080. else
  3081. return of_property_count_u32_elems(display->panel_node,
  3082. propname);
  3083. }
  3084. static int dsi_display_parse_dt(struct dsi_display *display)
  3085. {
  3086. int i, rc = 0;
  3087. u32 phy_count = 0;
  3088. struct device_node *of_node = display->pdev->dev.of_node;
  3089. char *dsi_ctrl_name, *dsi_phy_name;
  3090. if (!strcmp(display->display_type, "primary")) {
  3091. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3092. dsi_phy_name = "qcom,dsi-phy-num";
  3093. } else {
  3094. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3095. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3096. }
  3097. display->ctrl_count = dsi_display_get_phandle_count(display,
  3098. dsi_ctrl_name);
  3099. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3100. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3101. display->ctrl_count, phy_count);
  3102. if (!phy_count || !display->ctrl_count) {
  3103. DSI_ERR("no ctrl/phys found\n");
  3104. rc = -ENODEV;
  3105. goto error;
  3106. }
  3107. if (phy_count != display->ctrl_count) {
  3108. DSI_ERR("different ctrl and phy counts\n");
  3109. rc = -ENODEV;
  3110. goto error;
  3111. }
  3112. display_for_each_ctrl(i, display) {
  3113. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3114. int index;
  3115. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3116. display->ctrl_count, i);
  3117. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3118. "qcom,dsi-ctrl", index);
  3119. of_node_put(ctrl->ctrl_of_node);
  3120. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3121. display->ctrl_count, i);
  3122. ctrl->phy_of_node = of_parse_phandle(of_node,
  3123. "qcom,dsi-phy", index);
  3124. of_node_put(ctrl->phy_of_node);
  3125. }
  3126. /* Parse TE data */
  3127. dsi_display_parse_te_data(display);
  3128. /* Parse all external bridges from port 0 */
  3129. display_for_each_ctrl(i, display) {
  3130. display->ext_bridge[i].node_of =
  3131. of_graph_get_remote_node(of_node, 0, i);
  3132. if (display->ext_bridge[i].node_of)
  3133. display->ext_bridge_cnt++;
  3134. else
  3135. break;
  3136. }
  3137. DSI_DEBUG("success\n");
  3138. error:
  3139. return rc;
  3140. }
  3141. static int dsi_display_res_init(struct dsi_display *display)
  3142. {
  3143. int rc = 0;
  3144. int i;
  3145. struct dsi_display_ctrl *ctrl;
  3146. display_for_each_ctrl(i, display) {
  3147. ctrl = &display->ctrl[i];
  3148. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3149. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3150. rc = PTR_ERR(ctrl->ctrl);
  3151. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3152. ctrl->ctrl = NULL;
  3153. goto error_ctrl_put;
  3154. }
  3155. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3156. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3157. rc = PTR_ERR(ctrl->phy);
  3158. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3159. dsi_ctrl_put(ctrl->ctrl);
  3160. ctrl->phy = NULL;
  3161. goto error_ctrl_put;
  3162. }
  3163. }
  3164. display->panel = dsi_panel_get(&display->pdev->dev,
  3165. display->panel_node,
  3166. display->parser_node,
  3167. display->display_type,
  3168. display->cmdline_topology);
  3169. if (IS_ERR_OR_NULL(display->panel)) {
  3170. rc = PTR_ERR(display->panel);
  3171. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3172. display->panel = NULL;
  3173. goto error_ctrl_put;
  3174. }
  3175. display_for_each_ctrl(i, display) {
  3176. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3177. phy->cfg.force_clk_lane_hs =
  3178. display->panel->host_config.force_hs_clk_lane;
  3179. phy->cfg.phy_type =
  3180. display->panel->host_config.phy_type;
  3181. }
  3182. rc = dsi_display_parse_lane_map(display);
  3183. if (rc) {
  3184. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3185. goto error_ctrl_put;
  3186. }
  3187. rc = dsi_display_clocks_init(display);
  3188. if (rc) {
  3189. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3190. goto error_ctrl_put;
  3191. }
  3192. display->is_active = true;
  3193. return 0;
  3194. error_ctrl_put:
  3195. for (i = i - 1; i >= 0; i--) {
  3196. ctrl = &display->ctrl[i];
  3197. dsi_ctrl_put(ctrl->ctrl);
  3198. dsi_phy_put(ctrl->phy);
  3199. }
  3200. return rc;
  3201. }
  3202. static int dsi_display_res_deinit(struct dsi_display *display)
  3203. {
  3204. int rc = 0;
  3205. int i;
  3206. struct dsi_display_ctrl *ctrl;
  3207. rc = dsi_display_clocks_deinit(display);
  3208. if (rc)
  3209. DSI_ERR("clocks deinit failed, rc=%d\n", rc);
  3210. display_for_each_ctrl(i, display) {
  3211. ctrl = &display->ctrl[i];
  3212. dsi_phy_put(ctrl->phy);
  3213. dsi_ctrl_put(ctrl->ctrl);
  3214. }
  3215. if (display->panel)
  3216. dsi_panel_put(display->panel);
  3217. return rc;
  3218. }
  3219. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3220. struct dsi_display_mode *mode,
  3221. u32 flags)
  3222. {
  3223. int rc = 0;
  3224. int i;
  3225. struct dsi_display_ctrl *ctrl;
  3226. /*
  3227. * To set a mode:
  3228. * 1. Controllers should be turned off.
  3229. * 2. Link clocks should be off.
  3230. * 3. Phy should be disabled.
  3231. */
  3232. display_for_each_ctrl(i, display) {
  3233. ctrl = &display->ctrl[i];
  3234. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3235. (ctrl->phy_enabled)) {
  3236. rc = -EINVAL;
  3237. goto error;
  3238. }
  3239. }
  3240. error:
  3241. return rc;
  3242. }
  3243. static bool dsi_display_is_seamless_dfps_possible(
  3244. const struct dsi_display *display,
  3245. const struct dsi_display_mode *tgt,
  3246. const enum dsi_dfps_type dfps_type)
  3247. {
  3248. struct dsi_display_mode *cur;
  3249. if (!display || !tgt || !display->panel) {
  3250. DSI_ERR("Invalid params\n");
  3251. return false;
  3252. }
  3253. cur = display->panel->cur_mode;
  3254. if (cur->timing.h_active != tgt->timing.h_active) {
  3255. DSI_DEBUG("timing.h_active differs %d %d\n",
  3256. cur->timing.h_active, tgt->timing.h_active);
  3257. return false;
  3258. }
  3259. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3260. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3261. cur->timing.h_back_porch,
  3262. tgt->timing.h_back_porch);
  3263. return false;
  3264. }
  3265. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3266. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3267. cur->timing.h_sync_width,
  3268. tgt->timing.h_sync_width);
  3269. return false;
  3270. }
  3271. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3272. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3273. cur->timing.h_front_porch,
  3274. tgt->timing.h_front_porch);
  3275. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3276. return false;
  3277. }
  3278. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3279. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3280. cur->timing.h_skew,
  3281. tgt->timing.h_skew);
  3282. return false;
  3283. }
  3284. /* skip polarity comparison */
  3285. if (cur->timing.v_active != tgt->timing.v_active) {
  3286. DSI_DEBUG("timing.v_active differs %d %d\n",
  3287. cur->timing.v_active,
  3288. tgt->timing.v_active);
  3289. return false;
  3290. }
  3291. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3292. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3293. cur->timing.v_back_porch,
  3294. tgt->timing.v_back_porch);
  3295. return false;
  3296. }
  3297. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3298. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3299. cur->timing.v_sync_width,
  3300. tgt->timing.v_sync_width);
  3301. return false;
  3302. }
  3303. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3304. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3305. cur->timing.v_front_porch,
  3306. tgt->timing.v_front_porch);
  3307. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3308. return false;
  3309. }
  3310. /* skip polarity comparison */
  3311. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3312. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3313. cur->timing.refresh_rate,
  3314. tgt->timing.refresh_rate);
  3315. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3316. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3317. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3318. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3319. DSI_DEBUG("flags differs %d %d\n",
  3320. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3321. return true;
  3322. }
  3323. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3324. {
  3325. struct dsi_host_common_cfg *config;
  3326. struct dsi_display_ctrl *m_ctrl;
  3327. int phy_ver;
  3328. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3329. config = &display->panel->host_config;
  3330. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3331. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3332. config->byte_intf_clk_div = 1;
  3333. else
  3334. config->byte_intf_clk_div = 2;
  3335. }
  3336. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3337. u32 bit_clk_rate)
  3338. {
  3339. int rc = 0;
  3340. int i;
  3341. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3342. if (!display->panel) {
  3343. DSI_ERR("Invalid params\n");
  3344. return -EINVAL;
  3345. }
  3346. if (bit_clk_rate == 0) {
  3347. DSI_ERR("Invalid bit clock rate\n");
  3348. return -EINVAL;
  3349. }
  3350. display->config.bit_clk_rate_hz = bit_clk_rate;
  3351. display_for_each_ctrl(i, display) {
  3352. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3353. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3354. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3355. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3356. byte_intf_clk_rate;
  3357. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3358. struct dsi_host_common_cfg *host_cfg;
  3359. mutex_lock(&ctrl->ctrl_lock);
  3360. host_cfg = &display->panel->host_config;
  3361. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3362. num_of_lanes++;
  3363. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3364. num_of_lanes++;
  3365. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3366. num_of_lanes++;
  3367. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3368. num_of_lanes++;
  3369. if (num_of_lanes == 0) {
  3370. DSI_ERR("Invalid lane count\n");
  3371. rc = -EINVAL;
  3372. goto error;
  3373. }
  3374. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3375. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3376. bit_rate_per_lane = bit_rate;
  3377. do_div(bit_rate_per_lane, num_of_lanes);
  3378. pclk_rate = bit_rate;
  3379. do_div(pclk_rate, bpp);
  3380. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3381. bit_rate_per_lane = bit_rate;
  3382. do_div(bit_rate_per_lane, num_of_lanes);
  3383. byte_clk_rate = bit_rate_per_lane;
  3384. do_div(byte_clk_rate, 8);
  3385. byte_intf_clk_rate = byte_clk_rate;
  3386. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3387. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3388. } else {
  3389. do_div(bit_rate, bits_per_symbol);
  3390. bit_rate *= num_of_symbols;
  3391. bit_rate_per_lane = bit_rate;
  3392. do_div(bit_rate_per_lane, num_of_lanes);
  3393. byte_clk_rate = bit_rate_per_lane;
  3394. do_div(byte_clk_rate, 7);
  3395. /* For CPHY, byte_intf_clk is same as byte_clk */
  3396. byte_intf_clk_rate = byte_clk_rate;
  3397. }
  3398. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3399. bit_rate, bit_rate_per_lane);
  3400. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3401. byte_clk_rate, byte_intf_clk_rate);
  3402. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3403. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3404. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3405. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3406. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3407. ctrl->clk_freq, ctrl->cell_index);
  3408. if (rc) {
  3409. DSI_ERR("Failed to update link frequencies\n");
  3410. goto error;
  3411. }
  3412. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3413. error:
  3414. mutex_unlock(&ctrl->ctrl_lock);
  3415. /* TODO: recover ctrl->clk_freq in case of failure */
  3416. if (rc)
  3417. return rc;
  3418. }
  3419. return 0;
  3420. }
  3421. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3422. struct dsi_dyn_clk_delay *delay,
  3423. struct dsi_display_mode *mode)
  3424. {
  3425. u32 esc_clk_rate_hz;
  3426. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3427. u32 hsync_period = 0;
  3428. struct dsi_display_ctrl *m_ctrl;
  3429. struct dsi_ctrl *dsi_ctrl;
  3430. struct dsi_phy_cfg *cfg;
  3431. m_ctrl = &display->ctrl[display->clk_master_idx];
  3432. dsi_ctrl = m_ctrl->ctrl;
  3433. cfg = &(m_ctrl->phy->cfg);
  3434. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate * 1000;
  3435. pclk_to_esc_ratio = ((dsi_ctrl->clk_freq.pix_clk_rate * 1000) /
  3436. esc_clk_rate_hz);
  3437. byte_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 1000) /
  3438. esc_clk_rate_hz);
  3439. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4 * 1000) /
  3440. esc_clk_rate_hz);
  3441. hsync_period = dsi_h_total_dce(&mode->timing);
  3442. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3443. if (!display->panel->video_config.eof_bllp_lp11_en)
  3444. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3445. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3446. (display->config.common_config.t_clk_post + 1)) /
  3447. byte_to_esc_ratio) +
  3448. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3449. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3450. ((cfg->timing.lane_v3[3] * 4) +
  3451. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3452. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3453. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3454. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3455. hr_bit_to_esc_ratio);
  3456. delay->pipe_delay2 = 0;
  3457. if (display->panel->host_config.force_hs_clk_lane)
  3458. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3459. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3460. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3461. hr_bit_to_esc_ratio);
  3462. /* 130 us pll delay recommended by h/w doc */
  3463. delay->pll_delay = ((130 * esc_clk_rate_hz) / 1000000) * 2;
  3464. }
  3465. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3466. struct link_clk_freq *bkp_freq)
  3467. {
  3468. int rc = 0, i;
  3469. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3470. m_ctrl = &display->ctrl[display->clk_master_idx];
  3471. dsi_clk_prepare_enable(&display->clock_info.src_clks);
  3472. rc = dsi_clk_update_parent(&display->clock_info.shadow_clks,
  3473. &display->clock_info.mux_clks);
  3474. if (rc) {
  3475. DSI_ERR("failed update mux parent to shadow\n");
  3476. goto exit;
  3477. }
  3478. display_for_each_ctrl(i, display) {
  3479. ctrl = &display->ctrl[i];
  3480. if (!ctrl->ctrl)
  3481. continue;
  3482. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3483. ctrl->ctrl->clk_freq.byte_clk_rate,
  3484. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3485. if (rc) {
  3486. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3487. goto recover_byte_clk;
  3488. }
  3489. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3490. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3491. if (rc) {
  3492. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3493. goto recover_pix_clk;
  3494. }
  3495. }
  3496. display_for_each_ctrl(i, display) {
  3497. ctrl = &display->ctrl[i];
  3498. if (ctrl == m_ctrl)
  3499. continue;
  3500. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3501. }
  3502. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3503. /* wait for dynamic refresh done */
  3504. display_for_each_ctrl(i, display) {
  3505. ctrl = &display->ctrl[i];
  3506. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3507. if (rc) {
  3508. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3509. goto recover_pix_clk;
  3510. } else {
  3511. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3512. i ? "slave" : "master");
  3513. }
  3514. }
  3515. display_for_each_ctrl(i, display) {
  3516. ctrl = &display->ctrl[i];
  3517. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3518. }
  3519. rc = dsi_clk_update_parent(&display->clock_info.src_clks,
  3520. &display->clock_info.mux_clks);
  3521. if (rc)
  3522. DSI_ERR("could not switch back to src clks %d\n", rc);
  3523. dsi_clk_disable_unprepare(&display->clock_info.src_clks);
  3524. return rc;
  3525. recover_pix_clk:
  3526. display_for_each_ctrl(i, display) {
  3527. ctrl = &display->ctrl[i];
  3528. if (!ctrl->ctrl)
  3529. continue;
  3530. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3531. bkp_freq->pix_clk_rate, i);
  3532. }
  3533. recover_byte_clk:
  3534. display_for_each_ctrl(i, display) {
  3535. ctrl = &display->ctrl[i];
  3536. if (!ctrl->ctrl)
  3537. continue;
  3538. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3539. bkp_freq->byte_clk_rate,
  3540. bkp_freq->byte_intf_clk_rate, i);
  3541. }
  3542. exit:
  3543. dsi_clk_disable_unprepare(&display->clock_info.src_clks);
  3544. return rc;
  3545. }
  3546. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3547. struct dsi_display_mode *mode)
  3548. {
  3549. int rc = 0, mask, i;
  3550. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3551. struct dsi_dyn_clk_delay delay;
  3552. struct link_clk_freq bkp_freq;
  3553. dsi_panel_acquire_panel_lock(display->panel);
  3554. m_ctrl = &display->ctrl[display->clk_master_idx];
  3555. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3556. /* mask PLL unlock, FIFO overflow and underflow errors */
  3557. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3558. BIT(DSI_FIFO_OVERFLOW);
  3559. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3560. /* update the phy timings based on new mode */
  3561. display_for_each_ctrl(i, display) {
  3562. ctrl = &display->ctrl[i];
  3563. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3564. }
  3565. /* back up existing rates to handle failure case */
  3566. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3567. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3568. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3569. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3570. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3571. if (rc) {
  3572. DSI_ERR("failed set link frequencies %d\n", rc);
  3573. goto exit;
  3574. }
  3575. /* calculate pipe delays */
  3576. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3577. /* configure dynamic refresh ctrl registers */
  3578. display_for_each_ctrl(i, display) {
  3579. ctrl = &display->ctrl[i];
  3580. if (!ctrl->phy)
  3581. continue;
  3582. if (ctrl == m_ctrl)
  3583. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3584. else
  3585. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3586. false);
  3587. }
  3588. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3589. exit:
  3590. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3591. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3592. DSI_CLK_OFF);
  3593. /* store newly calculated phy timings in mode private info */
  3594. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3595. mode->priv_info->phy_timing_val,
  3596. mode->priv_info->phy_timing_len);
  3597. dsi_panel_release_panel_lock(display->panel);
  3598. return rc;
  3599. }
  3600. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3601. int clk_rate)
  3602. {
  3603. int rc = 0;
  3604. if (clk_rate <= 0) {
  3605. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3606. return -EINVAL;
  3607. }
  3608. if (clk_rate == display->cached_clk_rate) {
  3609. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  3610. return rc;
  3611. }
  3612. display->cached_clk_rate = clk_rate;
  3613. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  3614. if (!rc) {
  3615. DSI_INFO("%s: bit clk is ready to be configured to '%d'\n",
  3616. __func__, clk_rate);
  3617. atomic_set(&display->clkrate_change_pending, 1);
  3618. } else {
  3619. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  3620. __func__, clk_rate, rc);
  3621. /* Caching clock failed, so don't go on doing so. */
  3622. atomic_set(&display->clkrate_change_pending, 0);
  3623. display->cached_clk_rate = 0;
  3624. }
  3625. return rc;
  3626. }
  3627. static int dsi_display_dfps_update(struct dsi_display *display,
  3628. struct dsi_display_mode *dsi_mode)
  3629. {
  3630. struct dsi_mode_info *timing;
  3631. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3632. struct dsi_display_mode *panel_mode;
  3633. struct dsi_dfps_capabilities dfps_caps;
  3634. int rc = 0;
  3635. int i = 0;
  3636. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3637. if (!display || !dsi_mode || !display->panel) {
  3638. DSI_ERR("Invalid params\n");
  3639. return -EINVAL;
  3640. }
  3641. timing = &dsi_mode->timing;
  3642. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3643. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3644. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  3645. DSI_ERR("dfps or constant fps not supported\n");
  3646. return -ENOTSUPP;
  3647. }
  3648. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  3649. DSI_ERR("dfps clock method not supported\n");
  3650. return -ENOTSUPP;
  3651. }
  3652. /* For split DSI, update the clock master first */
  3653. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  3654. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  3655. m_ctrl = &display->ctrl[display->clk_master_idx];
  3656. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  3657. if (rc) {
  3658. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3659. display->name, i, rc);
  3660. goto error;
  3661. }
  3662. /* Update the rest of the controllers */
  3663. display_for_each_ctrl(i, display) {
  3664. ctrl = &display->ctrl[i];
  3665. if (!ctrl->ctrl || (ctrl == m_ctrl))
  3666. continue;
  3667. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  3668. if (rc) {
  3669. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3670. display->name, i, rc);
  3671. goto error;
  3672. }
  3673. }
  3674. panel_mode = display->panel->cur_mode;
  3675. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  3676. /*
  3677. * dsi_mode_flags flags are used to communicate with other drm driver
  3678. * components, and are transient. They aren't inherently part of the
  3679. * display panel's mode and shouldn't be saved into the cached currently
  3680. * active mode.
  3681. */
  3682. panel_mode->dsi_mode_flags = 0;
  3683. error:
  3684. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  3685. return rc;
  3686. }
  3687. static int dsi_display_dfps_calc_front_porch(
  3688. u32 old_fps,
  3689. u32 new_fps,
  3690. u32 a_total,
  3691. u32 b_total,
  3692. u32 b_fp,
  3693. u32 *b_fp_out)
  3694. {
  3695. s32 b_fp_new;
  3696. int add_porches, diff;
  3697. if (!b_fp_out) {
  3698. DSI_ERR("Invalid params\n");
  3699. return -EINVAL;
  3700. }
  3701. if (!a_total || !new_fps) {
  3702. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  3703. return -EINVAL;
  3704. }
  3705. /*
  3706. * Keep clock, other porches constant, use new fps, calc front porch
  3707. * new_vtotal = old_vtotal * (old_fps / new_fps )
  3708. * new_vfp - old_vfp = new_vtotal - old_vtotal
  3709. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  3710. */
  3711. diff = abs(old_fps - new_fps);
  3712. add_porches = mult_frac(b_total, diff, new_fps);
  3713. if (old_fps > new_fps)
  3714. b_fp_new = b_fp + add_porches;
  3715. else
  3716. b_fp_new = b_fp - add_porches;
  3717. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  3718. new_fps, a_total, b_total, b_fp, b_fp_new);
  3719. if (b_fp_new < 0) {
  3720. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  3721. return -EINVAL;
  3722. }
  3723. /**
  3724. * TODO: To differentiate from clock method when communicating to the
  3725. * other components, perhaps we should set clk here to original value
  3726. */
  3727. *b_fp_out = b_fp_new;
  3728. return 0;
  3729. }
  3730. /**
  3731. * dsi_display_get_dfps_timing() - Get the new dfps values.
  3732. * @display: DSI display handle.
  3733. * @adj_mode: Mode value structure to be changed.
  3734. * It contains old timing values and latest fps value.
  3735. * New timing values are updated based on new fps.
  3736. * @curr_refresh_rate: Current fps rate.
  3737. * If zero , current fps rate is taken from
  3738. * display->panel->cur_mode.
  3739. * Return: error code.
  3740. */
  3741. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  3742. struct dsi_display_mode *adj_mode,
  3743. u32 curr_refresh_rate)
  3744. {
  3745. struct dsi_dfps_capabilities dfps_caps;
  3746. struct dsi_display_mode per_ctrl_mode;
  3747. struct dsi_mode_info *timing;
  3748. struct dsi_ctrl *m_ctrl;
  3749. int rc = 0;
  3750. if (!display || !adj_mode) {
  3751. DSI_ERR("Invalid params\n");
  3752. return -EINVAL;
  3753. }
  3754. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  3755. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3756. if (!dfps_caps.dfps_support) {
  3757. DSI_ERR("dfps not supported by panel\n");
  3758. return -EINVAL;
  3759. }
  3760. per_ctrl_mode = *adj_mode;
  3761. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  3762. if (!curr_refresh_rate) {
  3763. if (!dsi_display_is_seamless_dfps_possible(display,
  3764. &per_ctrl_mode, dfps_caps.type)) {
  3765. DSI_ERR("seamless dynamic fps not supported for mode\n");
  3766. return -EINVAL;
  3767. }
  3768. if (display->panel->cur_mode) {
  3769. curr_refresh_rate =
  3770. display->panel->cur_mode->timing.refresh_rate;
  3771. } else {
  3772. DSI_ERR("cur_mode is not initialized\n");
  3773. return -EINVAL;
  3774. }
  3775. }
  3776. /* TODO: Remove this direct reference to the dsi_ctrl */
  3777. timing = &per_ctrl_mode.timing;
  3778. switch (dfps_caps.type) {
  3779. case DSI_DFPS_IMMEDIATE_VFP:
  3780. rc = dsi_display_dfps_calc_front_porch(
  3781. curr_refresh_rate,
  3782. timing->refresh_rate,
  3783. dsi_h_total_dce(timing),
  3784. DSI_V_TOTAL(timing),
  3785. timing->v_front_porch,
  3786. &adj_mode->timing.v_front_porch);
  3787. break;
  3788. case DSI_DFPS_IMMEDIATE_HFP:
  3789. rc = dsi_display_dfps_calc_front_porch(
  3790. curr_refresh_rate,
  3791. timing->refresh_rate,
  3792. DSI_V_TOTAL(timing),
  3793. dsi_h_total_dce(timing),
  3794. timing->h_front_porch,
  3795. &adj_mode->timing.h_front_porch);
  3796. if (!rc)
  3797. adj_mode->timing.h_front_porch *= display->ctrl_count;
  3798. break;
  3799. default:
  3800. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  3801. rc = -ENOTSUPP;
  3802. }
  3803. return rc;
  3804. }
  3805. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  3806. struct dsi_display_mode *adj_mode)
  3807. {
  3808. int rc = 0;
  3809. if (!display || !adj_mode) {
  3810. DSI_ERR("Invalid params\n");
  3811. return false;
  3812. }
  3813. /* Currently the only seamless transition is dynamic fps */
  3814. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  3815. if (rc) {
  3816. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  3817. } else {
  3818. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  3819. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  3820. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  3821. }
  3822. return rc;
  3823. }
  3824. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  3825. struct dsi_display_mode *to_mode)
  3826. {
  3827. u32 cur_fps, to_fps;
  3828. u32 cur_h_active, to_h_active;
  3829. u32 cur_v_active, to_v_active;
  3830. cur_fps = cur_mode->timing.refresh_rate;
  3831. to_fps = to_mode->timing.refresh_rate;
  3832. cur_h_active = cur_mode->timing.h_active;
  3833. cur_v_active = cur_mode->timing.v_active;
  3834. to_h_active = to_mode->timing.h_active;
  3835. to_v_active = to_mode->timing.v_active;
  3836. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  3837. (cur_fps != to_fps)) {
  3838. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  3839. DSI_DEBUG("DMS Modeset with FPS change\n");
  3840. } else {
  3841. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  3842. }
  3843. }
  3844. static int dsi_display_set_mode_sub(struct dsi_display *display,
  3845. struct dsi_display_mode *mode,
  3846. u32 flags)
  3847. {
  3848. int rc = 0, clk_rate = 0;
  3849. int i;
  3850. struct dsi_display_ctrl *ctrl;
  3851. struct dsi_display_mode_priv_info *priv_info;
  3852. bool commit_phy_timing = false;
  3853. priv_info = mode->priv_info;
  3854. if (!priv_info) {
  3855. DSI_ERR("[%s] failed to get private info of the display mode\n",
  3856. display->name);
  3857. return -EINVAL;
  3858. }
  3859. SDE_EVT32(mode->dsi_mode_flags);
  3860. if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) {
  3861. display->config.panel_mode = mode->panel_mode;
  3862. display->panel->panel_mode = mode->panel_mode;
  3863. }
  3864. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  3865. mode,
  3866. &display->config);
  3867. if (rc) {
  3868. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  3869. display->name, rc);
  3870. goto error;
  3871. }
  3872. memcpy(&display->config.lane_map, &display->lane_map,
  3873. sizeof(display->lane_map));
  3874. if (mode->dsi_mode_flags &
  3875. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  3876. rc = dsi_display_dfps_update(display, mode);
  3877. if (rc) {
  3878. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  3879. display->name, rc);
  3880. goto error;
  3881. }
  3882. display_for_each_ctrl(i, display) {
  3883. ctrl = &display->ctrl[i];
  3884. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  3885. &display->config, mode, mode->dsi_mode_flags,
  3886. display->dsi_clk_handle);
  3887. if (rc) {
  3888. DSI_ERR("failed to update ctrl config\n");
  3889. goto error;
  3890. }
  3891. }
  3892. if (priv_info->phy_timing_len) {
  3893. display_for_each_ctrl(i, display) {
  3894. ctrl = &display->ctrl[i];
  3895. rc = dsi_phy_set_timing_params(ctrl->phy,
  3896. priv_info->phy_timing_val,
  3897. priv_info->phy_timing_len,
  3898. commit_phy_timing);
  3899. if (rc)
  3900. DSI_ERR("Fail to add timing params\n");
  3901. }
  3902. }
  3903. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  3904. return rc;
  3905. }
  3906. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  3907. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  3908. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  3909. if (rc)
  3910. DSI_ERR("dynamic clk change failed %d\n", rc);
  3911. /*
  3912. * skip rest of the opearations since
  3913. * dsi_display_dynamic_clk_switch_vid() already takes
  3914. * care of them.
  3915. */
  3916. return rc;
  3917. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  3918. clk_rate = mode->timing.clk_rate_hz;
  3919. rc = dsi_display_dynamic_clk_configure_cmd(display,
  3920. clk_rate);
  3921. if (rc) {
  3922. DSI_ERR("Failed to configure dynamic clk\n");
  3923. return rc;
  3924. }
  3925. }
  3926. }
  3927. display_for_each_ctrl(i, display) {
  3928. ctrl = &display->ctrl[i];
  3929. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  3930. mode, mode->dsi_mode_flags,
  3931. display->dsi_clk_handle);
  3932. if (rc) {
  3933. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  3934. display->name, rc);
  3935. goto error;
  3936. }
  3937. }
  3938. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  3939. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  3940. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  3941. u64 to_bitclk = mode->timing.clk_rate_hz;
  3942. commit_phy_timing = true;
  3943. /* No need to set clkrate pending flag if clocks are same */
  3944. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  3945. atomic_set(&display->clkrate_change_pending, 1);
  3946. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  3947. }
  3948. if (priv_info->phy_timing_len) {
  3949. display_for_each_ctrl(i, display) {
  3950. ctrl = &display->ctrl[i];
  3951. rc = dsi_phy_set_timing_params(ctrl->phy,
  3952. priv_info->phy_timing_val,
  3953. priv_info->phy_timing_len,
  3954. commit_phy_timing);
  3955. if (rc)
  3956. DSI_ERR("failed to add DSI PHY timing params\n");
  3957. }
  3958. }
  3959. error:
  3960. return rc;
  3961. }
  3962. /**
  3963. * _dsi_display_dev_init - initializes the display device
  3964. * Initialization will acquire references to the resources required for the
  3965. * display hardware to function.
  3966. * @display: Handle to the display
  3967. * Returns: Zero on success
  3968. */
  3969. static int _dsi_display_dev_init(struct dsi_display *display)
  3970. {
  3971. int rc = 0;
  3972. if (!display) {
  3973. DSI_ERR("invalid display\n");
  3974. return -EINVAL;
  3975. }
  3976. if (!display->panel_node)
  3977. return 0;
  3978. mutex_lock(&display->display_lock);
  3979. display->parser = dsi_parser_get(&display->pdev->dev);
  3980. if (display->fw && display->parser)
  3981. display->parser_node = dsi_parser_get_head_node(
  3982. display->parser, display->fw->data,
  3983. display->fw->size);
  3984. rc = dsi_display_parse_dt(display);
  3985. if (rc) {
  3986. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  3987. goto error;
  3988. }
  3989. rc = dsi_display_res_init(display);
  3990. if (rc) {
  3991. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  3992. display->name, rc);
  3993. goto error;
  3994. }
  3995. error:
  3996. mutex_unlock(&display->display_lock);
  3997. return rc;
  3998. }
  3999. /**
  4000. * _dsi_display_dev_deinit - deinitializes the display device
  4001. * All the resources acquired during device init will be released.
  4002. * @display: Handle to the display
  4003. * Returns: Zero on success
  4004. */
  4005. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4006. {
  4007. int rc = 0;
  4008. if (!display) {
  4009. DSI_ERR("invalid display\n");
  4010. return -EINVAL;
  4011. }
  4012. mutex_lock(&display->display_lock);
  4013. rc = dsi_display_res_deinit(display);
  4014. if (rc)
  4015. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4016. display->name, rc);
  4017. mutex_unlock(&display->display_lock);
  4018. return rc;
  4019. }
  4020. /**
  4021. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4022. * @dsi_display: Pointer to dsi display
  4023. * Returns: Zero on success
  4024. */
  4025. int dsi_display_cont_splash_config(void *dsi_display)
  4026. {
  4027. struct dsi_display *display = dsi_display;
  4028. int rc = 0;
  4029. /* Vote for gdsc required to read register address space */
  4030. if (!display) {
  4031. DSI_ERR("invalid input display param\n");
  4032. return -EINVAL;
  4033. }
  4034. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4035. if (rc < 0) {
  4036. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4037. rc);
  4038. return rc;
  4039. }
  4040. mutex_lock(&display->display_lock);
  4041. display->is_cont_splash_enabled = true;
  4042. /* Update splash status for clock manager */
  4043. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4044. display->is_cont_splash_enabled);
  4045. /* Set up ctrl isr before enabling core clk */
  4046. dsi_display_ctrl_isr_configure(display, true);
  4047. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4048. * regulator are inplicit from pre clk on callback
  4049. */
  4050. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4051. DSI_ALL_CLKS, DSI_CLK_ON);
  4052. if (rc) {
  4053. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4054. display->name, rc);
  4055. goto clk_manager_update;
  4056. }
  4057. /* Vote on panel regulator will be removed during suspend path */
  4058. rc = dsi_pwr_enable_regulator(&display->panel->power_info, true);
  4059. if (rc) {
  4060. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4061. display->panel->name, rc);
  4062. goto clks_disabled;
  4063. }
  4064. dsi_config_host_engine_state_for_cont_splash(display);
  4065. mutex_unlock(&display->display_lock);
  4066. /* Set the current brightness level */
  4067. dsi_panel_bl_handoff(display->panel);
  4068. return rc;
  4069. clks_disabled:
  4070. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4071. DSI_ALL_CLKS, DSI_CLK_OFF);
  4072. clk_manager_update:
  4073. dsi_display_ctrl_isr_configure(display, false);
  4074. /* Update splash status for clock manager */
  4075. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4076. false);
  4077. pm_runtime_put_sync(display->drm_dev->dev);
  4078. display->is_cont_splash_enabled = false;
  4079. mutex_unlock(&display->display_lock);
  4080. return rc;
  4081. }
  4082. /**
  4083. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4084. * @display: Pointer to dsi display
  4085. * Returns: Zero on success
  4086. */
  4087. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4088. {
  4089. int rc = 0;
  4090. if (!display->is_cont_splash_enabled)
  4091. return 0;
  4092. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4093. DSI_ALL_CLKS, DSI_CLK_OFF);
  4094. if (rc)
  4095. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4096. display->name, rc);
  4097. pm_runtime_put_sync(display->drm_dev->dev);
  4098. display->is_cont_splash_enabled = false;
  4099. /* Update splash status for clock manager */
  4100. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4101. display->is_cont_splash_enabled);
  4102. return rc;
  4103. }
  4104. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4105. {
  4106. int rc = 0;
  4107. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4108. if (!rc) {
  4109. DSI_INFO("dsi bit clk has been configured to %d\n",
  4110. display->cached_clk_rate);
  4111. atomic_set(&display->clkrate_change_pending, 0);
  4112. } else {
  4113. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4114. display->cached_clk_rate, rc);
  4115. }
  4116. return rc;
  4117. }
  4118. static int dsi_display_validate_split_link(struct dsi_display *display)
  4119. {
  4120. int i, rc = 0;
  4121. struct dsi_display_ctrl *ctrl;
  4122. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4123. if (!host->split_link.split_link_enabled)
  4124. return 0;
  4125. if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4126. DSI_ERR("[%s] split link is not supported in command mode\n",
  4127. display->name);
  4128. rc = -ENOTSUPP;
  4129. goto error;
  4130. }
  4131. display_for_each_ctrl(i, display) {
  4132. ctrl = &display->ctrl[i];
  4133. if (!ctrl->ctrl->split_link_supported) {
  4134. DSI_ERR("[%s] split link is not supported by hw\n",
  4135. display->name);
  4136. rc = -ENOTSUPP;
  4137. goto error;
  4138. }
  4139. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4140. }
  4141. DSI_DEBUG("Split link is enabled\n");
  4142. return 0;
  4143. error:
  4144. host->split_link.split_link_enabled = false;
  4145. return rc;
  4146. }
  4147. /**
  4148. * dsi_display_bind - bind dsi device with controlling device
  4149. * @dev: Pointer to base of platform device
  4150. * @master: Pointer to container of drm device
  4151. * @data: Pointer to private data
  4152. * Returns: Zero on success
  4153. */
  4154. static int dsi_display_bind(struct device *dev,
  4155. struct device *master,
  4156. void *data)
  4157. {
  4158. struct dsi_display_ctrl *display_ctrl;
  4159. struct drm_device *drm;
  4160. struct dsi_display *display;
  4161. struct dsi_clk_info info;
  4162. struct clk_ctrl_cb clk_cb;
  4163. void *handle = NULL;
  4164. struct platform_device *pdev = to_platform_device(dev);
  4165. char *client1 = "dsi_clk_client";
  4166. char *client2 = "mdp_event_client";
  4167. int i, rc = 0;
  4168. if (!dev || !pdev || !master) {
  4169. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4170. dev, pdev, master);
  4171. return -EINVAL;
  4172. }
  4173. drm = dev_get_drvdata(master);
  4174. display = platform_get_drvdata(pdev);
  4175. if (!drm || !display) {
  4176. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4177. drm, display);
  4178. return -EINVAL;
  4179. }
  4180. if (!display->panel_node)
  4181. return 0;
  4182. if (!display->fw)
  4183. display->name = display->panel_node->name;
  4184. /* defer bind if ext bridge driver is not loaded */
  4185. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4186. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4187. if (!of_drm_find_bridge(
  4188. display->ext_bridge[i].node_of)) {
  4189. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4190. display->ext_bridge[i].node_of->full_name);
  4191. return -EPROBE_DEFER;
  4192. }
  4193. }
  4194. }
  4195. mutex_lock(&display->display_lock);
  4196. rc = dsi_display_validate_split_link(display);
  4197. if (rc) {
  4198. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4199. display->name, rc);
  4200. goto error;
  4201. }
  4202. rc = dsi_display_debugfs_init(display);
  4203. if (rc) {
  4204. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4205. goto error;
  4206. }
  4207. atomic_set(&display->clkrate_change_pending, 0);
  4208. display->cached_clk_rate = 0;
  4209. memset(&info, 0x0, sizeof(info));
  4210. display_for_each_ctrl(i, display) {
  4211. display_ctrl = &display->ctrl[i];
  4212. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4213. if (rc) {
  4214. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4215. display->name, i, rc);
  4216. goto error_ctrl_deinit;
  4217. }
  4218. display_ctrl->ctrl->horiz_index = i;
  4219. rc = dsi_phy_drv_init(display_ctrl->phy);
  4220. if (rc) {
  4221. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4222. display->name, i, rc);
  4223. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4224. goto error_ctrl_deinit;
  4225. }
  4226. display_ctrl->ctrl->dma_cmd_workq = display->dma_cmd_workq;
  4227. memcpy(&info.c_clks[i],
  4228. (&display_ctrl->ctrl->clk_info.core_clks),
  4229. sizeof(struct dsi_core_clk_info));
  4230. memcpy(&info.l_hs_clks[i],
  4231. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4232. sizeof(struct dsi_link_hs_clk_info));
  4233. memcpy(&info.l_lp_clks[i],
  4234. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4235. sizeof(struct dsi_link_lp_clk_info));
  4236. info.c_clks[i].drm = drm;
  4237. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4238. }
  4239. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4240. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4241. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4242. info.post_clkon_cb = dsi_post_clkon_cb;
  4243. info.priv_data = display;
  4244. info.master_ndx = display->clk_master_idx;
  4245. info.dsi_ctrl_count = display->ctrl_count;
  4246. snprintf(info.name, MAX_STRING_LEN,
  4247. "DSI_MNGR-%s", display->name);
  4248. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4249. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4250. rc = PTR_ERR(display->clk_mngr);
  4251. display->clk_mngr = NULL;
  4252. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4253. goto error_ctrl_deinit;
  4254. }
  4255. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4256. if (IS_ERR_OR_NULL(handle)) {
  4257. rc = PTR_ERR(handle);
  4258. DSI_ERR("failed to register %s client, rc = %d\n",
  4259. client1, rc);
  4260. goto error_clk_deinit;
  4261. } else {
  4262. display->dsi_clk_handle = handle;
  4263. }
  4264. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4265. if (IS_ERR_OR_NULL(handle)) {
  4266. rc = PTR_ERR(handle);
  4267. DSI_ERR("failed to register %s client, rc = %d\n",
  4268. client2, rc);
  4269. goto error_clk_client_deinit;
  4270. } else {
  4271. display->mdp_clk_handle = handle;
  4272. }
  4273. clk_cb.priv = display;
  4274. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4275. display_for_each_ctrl(i, display) {
  4276. display_ctrl = &display->ctrl[i];
  4277. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4278. if (rc) {
  4279. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4280. display->name, i, rc);
  4281. goto error_ctrl_deinit;
  4282. }
  4283. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4284. if (rc) {
  4285. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4286. display->name, i, rc);
  4287. goto error_ctrl_deinit;
  4288. }
  4289. }
  4290. dsi_display_update_byte_intf_div(display);
  4291. rc = dsi_display_mipi_host_init(display);
  4292. if (rc) {
  4293. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4294. display->name, rc);
  4295. goto error_ctrl_deinit;
  4296. }
  4297. rc = dsi_panel_drv_init(display->panel, &display->host);
  4298. if (rc) {
  4299. if (rc != -EPROBE_DEFER)
  4300. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4301. display->name, rc);
  4302. goto error_host_deinit;
  4303. }
  4304. DSI_INFO("Successfully bind display panel '%s'\n", display->name);
  4305. display->drm_dev = drm;
  4306. display_for_each_ctrl(i, display) {
  4307. display_ctrl = &display->ctrl[i];
  4308. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4309. continue;
  4310. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4311. &display_ctrl->ctrl->clk_freq);
  4312. if (rc) {
  4313. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4314. display->name, rc);
  4315. goto error;
  4316. }
  4317. }
  4318. /* Remove the panel vote that was added during dsi display probe */
  4319. if (display->panel) {
  4320. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4321. false);
  4322. if (rc) {
  4323. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4324. display->panel->name, rc);
  4325. goto error_host_deinit;
  4326. }
  4327. }
  4328. /* register te irq handler */
  4329. dsi_display_register_te_irq(display);
  4330. goto error;
  4331. error_host_deinit:
  4332. (void)dsi_display_mipi_host_deinit(display);
  4333. error_clk_client_deinit:
  4334. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4335. error_clk_deinit:
  4336. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4337. error_ctrl_deinit:
  4338. for (i = i - 1; i >= 0; i--) {
  4339. display_ctrl = &display->ctrl[i];
  4340. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4341. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4342. }
  4343. (void)dsi_display_debugfs_deinit(display);
  4344. error:
  4345. mutex_unlock(&display->display_lock);
  4346. return rc;
  4347. }
  4348. /**
  4349. * dsi_display_unbind - unbind dsi from controlling device
  4350. * @dev: Pointer to base of platform device
  4351. * @master: Pointer to container of drm device
  4352. * @data: Pointer to private data
  4353. */
  4354. static void dsi_display_unbind(struct device *dev,
  4355. struct device *master, void *data)
  4356. {
  4357. struct dsi_display_ctrl *display_ctrl;
  4358. struct dsi_display *display;
  4359. struct platform_device *pdev = to_platform_device(dev);
  4360. int i, rc = 0;
  4361. if (!dev || !pdev) {
  4362. DSI_ERR("invalid param(s)\n");
  4363. return;
  4364. }
  4365. display = platform_get_drvdata(pdev);
  4366. if (!display) {
  4367. DSI_ERR("invalid display\n");
  4368. return;
  4369. }
  4370. mutex_lock(&display->display_lock);
  4371. rc = dsi_panel_drv_deinit(display->panel);
  4372. if (rc)
  4373. DSI_ERR("[%s] failed to deinit panel driver, rc=%d\n",
  4374. display->name, rc);
  4375. rc = dsi_display_mipi_host_deinit(display);
  4376. if (rc)
  4377. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4378. display->name,
  4379. rc);
  4380. display_for_each_ctrl(i, display) {
  4381. display_ctrl = &display->ctrl[i];
  4382. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4383. if (rc)
  4384. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4385. display->name, i, rc);
  4386. display->ctrl->ctrl->dma_cmd_workq = NULL;
  4387. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4388. if (rc)
  4389. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4390. display->name, i, rc);
  4391. }
  4392. atomic_set(&display->clkrate_change_pending, 0);
  4393. (void)dsi_display_debugfs_deinit(display);
  4394. mutex_unlock(&display->display_lock);
  4395. }
  4396. static const struct component_ops dsi_display_comp_ops = {
  4397. .bind = dsi_display_bind,
  4398. .unbind = dsi_display_unbind,
  4399. };
  4400. static struct platform_driver dsi_display_driver = {
  4401. .probe = dsi_display_dev_probe,
  4402. .remove = dsi_display_dev_remove,
  4403. .driver = {
  4404. .name = "msm-dsi-display",
  4405. .of_match_table = dsi_display_dt_match,
  4406. .suppress_bind_attrs = true,
  4407. },
  4408. };
  4409. static int dsi_display_init(struct dsi_display *display)
  4410. {
  4411. int rc = 0;
  4412. struct platform_device *pdev = display->pdev;
  4413. mutex_init(&display->display_lock);
  4414. rc = _dsi_display_dev_init(display);
  4415. if (rc) {
  4416. DSI_ERR("device init failed, rc=%d\n", rc);
  4417. goto end;
  4418. }
  4419. /*
  4420. * Vote on panel regulator is added to make sure panel regulators
  4421. * are ON until dsi bind is completed for cont-splash enabled usecase.
  4422. * This panel regulator vote will be removed after bind is done.
  4423. * For GKI, adding this vote will make sure that sync_state
  4424. * kernel driver doesn't disable the panel regulators before
  4425. * splash_config() function adds vote for these regulators.
  4426. */
  4427. if (display->panel) {
  4428. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4429. true);
  4430. if (rc) {
  4431. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4432. display->panel->name, rc);
  4433. return rc;
  4434. }
  4435. }
  4436. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4437. if (rc)
  4438. DSI_ERR("component add failed, rc=%d\n", rc);
  4439. DSI_DEBUG("component add success: %s\n", display->name);
  4440. end:
  4441. return rc;
  4442. }
  4443. static void dsi_display_firmware_display(const struct firmware *fw,
  4444. void *context)
  4445. {
  4446. struct dsi_display *display = context;
  4447. if (fw) {
  4448. DSI_DEBUG("reading data from firmware, size=%zd\n",
  4449. fw->size);
  4450. display->fw = fw;
  4451. display->name = "dsi_firmware_display";
  4452. }
  4453. if (dsi_display_init(display))
  4454. return;
  4455. DSI_DEBUG("success\n");
  4456. }
  4457. int dsi_display_dev_probe(struct platform_device *pdev)
  4458. {
  4459. struct dsi_display *display = NULL;
  4460. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4461. int rc = 0, index = DSI_PRIMARY;
  4462. bool firm_req = false;
  4463. struct dsi_display_boot_param *boot_disp;
  4464. if (!pdev || !pdev->dev.of_node) {
  4465. DSI_ERR("pdev not found\n");
  4466. rc = -ENODEV;
  4467. goto end;
  4468. }
  4469. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4470. if (!display) {
  4471. rc = -ENOMEM;
  4472. goto end;
  4473. }
  4474. display->dma_cmd_workq = create_singlethread_workqueue(
  4475. "dsi_dma_cmd_workq");
  4476. if (!display->dma_cmd_workq) {
  4477. DSI_ERR("failed to create work queue\n");
  4478. rc = -EINVAL;
  4479. goto end;
  4480. }
  4481. /* initialize panel id to UINT64_MAX */
  4482. display->panel_id = ~0x0;
  4483. display->display_type = of_get_property(pdev->dev.of_node,
  4484. "label", NULL);
  4485. if (!display->display_type)
  4486. display->display_type = "primary";
  4487. if (!strcmp(display->display_type, "secondary"))
  4488. index = DSI_SECONDARY;
  4489. boot_disp = &boot_displays[index];
  4490. node = pdev->dev.of_node;
  4491. if (boot_disp->boot_disp_en) {
  4492. mdp_node = of_parse_phandle(node, "qcom,mdp", 0);
  4493. if (!mdp_node) {
  4494. DSI_ERR("mdp_node not found\n");
  4495. rc = -ENODEV;
  4496. goto end;
  4497. }
  4498. /* The panel name should be same as UEFI name index */
  4499. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4500. if (!panel_node)
  4501. DSI_WARN("panel_node %s not found\n", boot_disp->name);
  4502. } else {
  4503. panel_node = of_parse_phandle(node,
  4504. "qcom,dsi-default-panel", 0);
  4505. if (!panel_node)
  4506. DSI_WARN("default panel not found\n");
  4507. if (IS_ENABLED(CONFIG_DSI_PARSER))
  4508. firm_req = !request_firmware_nowait(
  4509. THIS_MODULE, 1, "dsi_prop",
  4510. &pdev->dev, GFP_KERNEL, display,
  4511. dsi_display_firmware_display);
  4512. }
  4513. boot_disp->node = pdev->dev.of_node;
  4514. boot_disp->disp = display;
  4515. display->panel_node = panel_node;
  4516. display->pdev = pdev;
  4517. display->boot_disp = boot_disp;
  4518. dsi_display_parse_cmdline_topology(display, index);
  4519. platform_set_drvdata(pdev, display);
  4520. /* initialize display in firmware callback */
  4521. if (!firm_req) {
  4522. rc = dsi_display_init(display);
  4523. if (rc)
  4524. goto end;
  4525. }
  4526. return 0;
  4527. end:
  4528. if (display)
  4529. devm_kfree(&pdev->dev, display);
  4530. return rc;
  4531. }
  4532. int dsi_display_dev_remove(struct platform_device *pdev)
  4533. {
  4534. int rc = 0, i = 0;
  4535. struct dsi_display *display;
  4536. struct dsi_display_ctrl *ctrl;
  4537. if (!pdev) {
  4538. DSI_ERR("Invalid device\n");
  4539. return -EINVAL;
  4540. }
  4541. display = platform_get_drvdata(pdev);
  4542. /* decrement ref count */
  4543. of_node_put(display->panel_node);
  4544. if (display->dma_cmd_workq) {
  4545. flush_workqueue(display->dma_cmd_workq);
  4546. destroy_workqueue(display->dma_cmd_workq);
  4547. display->dma_cmd_workq = NULL;
  4548. display_for_each_ctrl(i, display) {
  4549. ctrl = &display->ctrl[i];
  4550. if (!ctrl->ctrl)
  4551. continue;
  4552. ctrl->ctrl->dma_cmd_workq = NULL;
  4553. }
  4554. }
  4555. (void)_dsi_display_dev_deinit(display);
  4556. platform_set_drvdata(pdev, NULL);
  4557. devm_kfree(&pdev->dev, display);
  4558. return rc;
  4559. }
  4560. int dsi_display_get_num_of_displays(void)
  4561. {
  4562. int i, count = 0;
  4563. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  4564. struct dsi_display *display = boot_displays[i].disp;
  4565. if (display && display->panel_node)
  4566. count++;
  4567. }
  4568. return count;
  4569. }
  4570. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  4571. {
  4572. int index = 0, count = 0;
  4573. if (!display_array || !max_display_count) {
  4574. DSI_ERR("invalid params\n");
  4575. return 0;
  4576. }
  4577. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  4578. struct dsi_display *display = boot_displays[index].disp;
  4579. if (display && display->panel_node)
  4580. display_array[count++] = display;
  4581. }
  4582. return count;
  4583. }
  4584. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  4585. {
  4586. if (!display)
  4587. return;
  4588. mutex_lock(&display->display_lock);
  4589. display->is_active = is_active;
  4590. mutex_unlock(&display->display_lock);
  4591. }
  4592. int dsi_display_drm_bridge_init(struct dsi_display *display,
  4593. struct drm_encoder *enc)
  4594. {
  4595. int rc = 0;
  4596. struct dsi_bridge *bridge;
  4597. struct msm_drm_private *priv = NULL;
  4598. if (!display || !display->drm_dev || !enc) {
  4599. DSI_ERR("invalid param(s)\n");
  4600. return -EINVAL;
  4601. }
  4602. mutex_lock(&display->display_lock);
  4603. priv = display->drm_dev->dev_private;
  4604. if (!priv) {
  4605. DSI_ERR("Private data is not present\n");
  4606. rc = -EINVAL;
  4607. goto error;
  4608. }
  4609. if (display->bridge) {
  4610. DSI_ERR("display is already initialize\n");
  4611. goto error;
  4612. }
  4613. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  4614. if (IS_ERR_OR_NULL(bridge)) {
  4615. rc = PTR_ERR(bridge);
  4616. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  4617. goto error;
  4618. }
  4619. display->bridge = bridge;
  4620. priv->bridges[priv->num_bridges++] = &bridge->base;
  4621. error:
  4622. mutex_unlock(&display->display_lock);
  4623. return rc;
  4624. }
  4625. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  4626. {
  4627. int rc = 0;
  4628. if (!display) {
  4629. DSI_ERR("Invalid params\n");
  4630. return -EINVAL;
  4631. }
  4632. mutex_lock(&display->display_lock);
  4633. dsi_drm_bridge_cleanup(display->bridge);
  4634. display->bridge = NULL;
  4635. mutex_unlock(&display->display_lock);
  4636. return rc;
  4637. }
  4638. /* Hook functions to call external connector, pointer validation is
  4639. * done in dsi_display_drm_ext_bridge_init.
  4640. */
  4641. static enum drm_connector_status dsi_display_drm_ext_detect(
  4642. struct drm_connector *connector,
  4643. bool force,
  4644. void *disp)
  4645. {
  4646. struct dsi_display *display = disp;
  4647. return display->ext_conn->funcs->detect(display->ext_conn, force);
  4648. }
  4649. static int dsi_display_drm_ext_get_modes(
  4650. struct drm_connector *connector, void *disp,
  4651. const struct msm_resource_caps_info *avail_res)
  4652. {
  4653. struct dsi_display *display = disp;
  4654. struct drm_display_mode *pmode, *pt;
  4655. int count;
  4656. /* if there are modes defined in panel, ignore external modes */
  4657. if (display->panel->num_timing_nodes)
  4658. return dsi_connector_get_modes(connector, disp, avail_res);
  4659. count = display->ext_conn->helper_private->get_modes(
  4660. display->ext_conn);
  4661. list_for_each_entry_safe(pmode, pt,
  4662. &display->ext_conn->probed_modes, head) {
  4663. list_move_tail(&pmode->head, &connector->probed_modes);
  4664. }
  4665. connector->display_info = display->ext_conn->display_info;
  4666. return count;
  4667. }
  4668. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  4669. struct drm_connector *connector,
  4670. struct drm_display_mode *mode,
  4671. void *disp, const struct msm_resource_caps_info *avail_res)
  4672. {
  4673. struct dsi_display *display = disp;
  4674. enum drm_mode_status status;
  4675. /* always do internal mode_valid check */
  4676. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  4677. if (status != MODE_OK)
  4678. return status;
  4679. return display->ext_conn->helper_private->mode_valid(
  4680. display->ext_conn, mode);
  4681. }
  4682. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  4683. void *disp,
  4684. struct drm_atomic_state *state)
  4685. {
  4686. struct dsi_display *display = disp;
  4687. struct drm_connector_state *c_state;
  4688. c_state = drm_atomic_get_new_connector_state(state, connector);
  4689. return display->ext_conn->helper_private->atomic_check(
  4690. display->ext_conn, state);
  4691. }
  4692. static int dsi_display_ext_get_info(struct drm_connector *connector,
  4693. struct msm_display_info *info, void *disp)
  4694. {
  4695. struct dsi_display *display;
  4696. int i;
  4697. if (!info || !disp) {
  4698. DSI_ERR("invalid params\n");
  4699. return -EINVAL;
  4700. }
  4701. display = disp;
  4702. if (!display->panel) {
  4703. DSI_ERR("invalid display panel\n");
  4704. return -EINVAL;
  4705. }
  4706. mutex_lock(&display->display_lock);
  4707. memset(info, 0, sizeof(struct msm_display_info));
  4708. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  4709. info->num_of_h_tiles = display->ctrl_count;
  4710. for (i = 0; i < info->num_of_h_tiles; i++)
  4711. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  4712. info->is_connected = connector->status != connector_status_disconnected;
  4713. if (!strcmp(display->display_type, "primary"))
  4714. info->display_type = SDE_CONNECTOR_PRIMARY;
  4715. else if (!strcmp(display->display_type, "secondary"))
  4716. info->display_type = SDE_CONNECTOR_SECONDARY;
  4717. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  4718. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  4719. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  4720. mutex_unlock(&display->display_lock);
  4721. return 0;
  4722. }
  4723. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  4724. const struct drm_display_mode *drm_mode,
  4725. struct msm_mode_info *mode_info,
  4726. void *display, const struct msm_resource_caps_info *avail_res)
  4727. {
  4728. struct msm_display_topology *topology;
  4729. if (!drm_mode || !mode_info ||
  4730. !avail_res || !avail_res->max_mixer_width)
  4731. return -EINVAL;
  4732. memset(mode_info, 0, sizeof(*mode_info));
  4733. mode_info->frame_rate = drm_mode->vrefresh;
  4734. mode_info->vtotal = drm_mode->vtotal;
  4735. topology = &mode_info->topology;
  4736. topology->num_lm = (avail_res->max_mixer_width
  4737. <= drm_mode->hdisplay) ? 2 : 1;
  4738. topology->num_enc = 0;
  4739. topology->num_intf = topology->num_lm;
  4740. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  4741. return 0;
  4742. }
  4743. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  4744. struct drm_bridge *bridge)
  4745. {
  4746. struct msm_drm_private *priv;
  4747. struct sde_kms *sde_kms;
  4748. struct drm_connector *conn;
  4749. struct drm_connector_list_iter conn_iter;
  4750. struct sde_connector *sde_conn;
  4751. struct dsi_display *display;
  4752. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  4753. int i;
  4754. if (!bridge || !bridge->encoder) {
  4755. SDE_ERROR("invalid argument\n");
  4756. return NULL;
  4757. }
  4758. priv = bridge->dev->dev_private;
  4759. sde_kms = to_sde_kms(priv->kms);
  4760. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  4761. drm_for_each_connector_iter(conn, &conn_iter) {
  4762. sde_conn = to_sde_connector(conn);
  4763. if (sde_conn->encoder == bridge->encoder) {
  4764. display = sde_conn->display;
  4765. display_for_each_ctrl(i, display) {
  4766. if (display->ext_bridge[i].bridge == bridge) {
  4767. dsi_bridge = &display->ext_bridge[i];
  4768. break;
  4769. }
  4770. }
  4771. }
  4772. }
  4773. drm_connector_list_iter_end(&conn_iter);
  4774. return dsi_bridge;
  4775. }
  4776. static void dsi_display_drm_ext_adjust_timing(
  4777. const struct dsi_display *display,
  4778. struct drm_display_mode *mode)
  4779. {
  4780. mode->hdisplay /= display->ctrl_count;
  4781. mode->hsync_start /= display->ctrl_count;
  4782. mode->hsync_end /= display->ctrl_count;
  4783. mode->htotal /= display->ctrl_count;
  4784. mode->hskew /= display->ctrl_count;
  4785. mode->clock /= display->ctrl_count;
  4786. }
  4787. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  4788. struct drm_bridge *bridge,
  4789. const struct drm_display_mode *mode)
  4790. {
  4791. struct dsi_display_ext_bridge *ext_bridge;
  4792. struct drm_display_mode tmp;
  4793. ext_bridge = dsi_display_ext_get_bridge(bridge);
  4794. if (!ext_bridge)
  4795. return MODE_ERROR;
  4796. tmp = *mode;
  4797. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  4798. return ext_bridge->orig_funcs->mode_valid(bridge, &tmp);
  4799. }
  4800. static bool dsi_display_drm_ext_bridge_mode_fixup(
  4801. struct drm_bridge *bridge,
  4802. const struct drm_display_mode *mode,
  4803. struct drm_display_mode *adjusted_mode)
  4804. {
  4805. struct dsi_display_ext_bridge *ext_bridge;
  4806. struct drm_display_mode tmp;
  4807. ext_bridge = dsi_display_ext_get_bridge(bridge);
  4808. if (!ext_bridge)
  4809. return false;
  4810. tmp = *mode;
  4811. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  4812. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  4813. }
  4814. static void dsi_display_drm_ext_bridge_mode_set(
  4815. struct drm_bridge *bridge,
  4816. const struct drm_display_mode *mode,
  4817. const struct drm_display_mode *adjusted_mode)
  4818. {
  4819. struct dsi_display_ext_bridge *ext_bridge;
  4820. struct drm_display_mode tmp;
  4821. ext_bridge = dsi_display_ext_get_bridge(bridge);
  4822. if (!ext_bridge)
  4823. return;
  4824. tmp = *mode;
  4825. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  4826. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  4827. }
  4828. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  4829. struct mipi_dsi_device *dsi)
  4830. {
  4831. struct dsi_display *display = to_dsi_display(host);
  4832. struct dsi_panel *panel;
  4833. if (!host || !dsi || !display->panel) {
  4834. DSI_ERR("Invalid param\n");
  4835. return -EINVAL;
  4836. }
  4837. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  4838. dsi->name, dsi->channel, dsi->lanes,
  4839. dsi->format, dsi->mode_flags);
  4840. panel = display->panel;
  4841. panel->host_config.data_lanes = 0;
  4842. if (dsi->lanes > 0)
  4843. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  4844. if (dsi->lanes > 1)
  4845. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  4846. if (dsi->lanes > 2)
  4847. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  4848. if (dsi->lanes > 3)
  4849. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  4850. switch (dsi->format) {
  4851. case MIPI_DSI_FMT_RGB888:
  4852. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  4853. break;
  4854. case MIPI_DSI_FMT_RGB666:
  4855. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  4856. break;
  4857. case MIPI_DSI_FMT_RGB666_PACKED:
  4858. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  4859. break;
  4860. case MIPI_DSI_FMT_RGB565:
  4861. default:
  4862. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  4863. break;
  4864. }
  4865. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  4866. panel->panel_mode = DSI_OP_VIDEO_MODE;
  4867. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  4868. panel->video_config.traffic_mode =
  4869. DSI_VIDEO_TRAFFIC_BURST_MODE;
  4870. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  4871. panel->video_config.traffic_mode =
  4872. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  4873. else
  4874. panel->video_config.traffic_mode =
  4875. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  4876. panel->video_config.hsa_lp11_en =
  4877. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  4878. panel->video_config.hbp_lp11_en =
  4879. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  4880. panel->video_config.hfp_lp11_en =
  4881. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  4882. panel->video_config.pulse_mode_hsa_he =
  4883. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  4884. panel->video_config.bllp_lp11_en =
  4885. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BLLP;
  4886. panel->video_config.eof_bllp_lp11_en =
  4887. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_EOF_BLLP;
  4888. } else {
  4889. panel->panel_mode = DSI_OP_CMD_MODE;
  4890. DSI_ERR("command mode not supported by ext bridge\n");
  4891. return -ENOTSUPP;
  4892. }
  4893. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  4894. return 0;
  4895. }
  4896. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  4897. .attach = dsi_host_ext_attach,
  4898. .detach = dsi_host_detach,
  4899. .transfer = dsi_host_transfer,
  4900. };
  4901. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display * display)
  4902. {
  4903. if (!display || !display->panel) {
  4904. pr_err("invalid param(s)\n");
  4905. return NULL;
  4906. }
  4907. return &display->panel->drm_panel;
  4908. }
  4909. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  4910. struct drm_encoder *encoder, struct drm_connector *connector)
  4911. {
  4912. struct drm_device *drm;
  4913. struct drm_bridge *bridge;
  4914. struct drm_bridge *ext_bridge;
  4915. struct drm_connector *ext_conn;
  4916. struct sde_connector *sde_conn;
  4917. struct drm_bridge *prev_bridge;
  4918. int rc = 0, i;
  4919. if (!display || !encoder || !connector)
  4920. return -EINVAL;
  4921. drm = encoder->dev;
  4922. bridge = encoder->bridge;
  4923. sde_conn = to_sde_connector(connector);
  4924. prev_bridge = bridge;
  4925. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  4926. return 0;
  4927. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4928. struct dsi_display_ext_bridge *ext_bridge_info =
  4929. &display->ext_bridge[i];
  4930. /* return if ext bridge is already initialized */
  4931. if (ext_bridge_info->bridge)
  4932. return 0;
  4933. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  4934. if (IS_ERR_OR_NULL(ext_bridge)) {
  4935. rc = PTR_ERR(ext_bridge);
  4936. DSI_ERR("failed to find ext bridge\n");
  4937. goto error;
  4938. }
  4939. /* override functions for mode adjustment */
  4940. if (display->ext_bridge_cnt > 1) {
  4941. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  4942. if (ext_bridge->funcs->mode_fixup)
  4943. ext_bridge_info->bridge_funcs.mode_fixup =
  4944. dsi_display_drm_ext_bridge_mode_fixup;
  4945. if (ext_bridge->funcs->mode_valid)
  4946. ext_bridge_info->bridge_funcs.mode_valid =
  4947. dsi_display_drm_ext_bridge_mode_valid;
  4948. if (ext_bridge->funcs->mode_set)
  4949. ext_bridge_info->bridge_funcs.mode_set =
  4950. dsi_display_drm_ext_bridge_mode_set;
  4951. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  4952. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  4953. }
  4954. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge);
  4955. if (rc) {
  4956. DSI_ERR("[%s] ext brige attach failed, %d\n",
  4957. display->name, rc);
  4958. goto error;
  4959. }
  4960. ext_bridge_info->display = display;
  4961. ext_bridge_info->bridge = ext_bridge;
  4962. prev_bridge = ext_bridge;
  4963. /* ext bridge will init its own connector during attach,
  4964. * we need to extract it out of the connector list
  4965. */
  4966. spin_lock_irq(&drm->mode_config.connector_list_lock);
  4967. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  4968. struct drm_connector, head);
  4969. if (ext_conn && ext_conn != connector &&
  4970. ext_conn->encoder_ids[0] == bridge->encoder->base.id) {
  4971. list_del_init(&ext_conn->head);
  4972. display->ext_conn = ext_conn;
  4973. }
  4974. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  4975. /* if there is no valid external connector created, or in split
  4976. * mode, default setting is used from panel defined in DT file.
  4977. */
  4978. if (!display->ext_conn ||
  4979. !display->ext_conn->funcs ||
  4980. !display->ext_conn->helper_private ||
  4981. display->ext_bridge_cnt > 1) {
  4982. display->ext_conn = NULL;
  4983. continue;
  4984. }
  4985. /* otherwise, hook up the functions to use external connector */
  4986. if (display->ext_conn->funcs->detect)
  4987. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  4988. if (display->ext_conn->helper_private->get_modes)
  4989. sde_conn->ops.get_modes =
  4990. dsi_display_drm_ext_get_modes;
  4991. if (display->ext_conn->helper_private->mode_valid)
  4992. sde_conn->ops.mode_valid =
  4993. dsi_display_drm_ext_mode_valid;
  4994. if (display->ext_conn->helper_private->atomic_check)
  4995. sde_conn->ops.atomic_check =
  4996. dsi_display_drm_ext_atomic_check;
  4997. sde_conn->ops.get_info =
  4998. dsi_display_ext_get_info;
  4999. sde_conn->ops.get_mode_info =
  5000. dsi_display_ext_get_mode_info;
  5001. /* add support to attach/detach */
  5002. display->host.ops = &dsi_host_ext_ops;
  5003. }
  5004. return 0;
  5005. error:
  5006. return rc;
  5007. }
  5008. int dsi_display_get_info(struct drm_connector *connector,
  5009. struct msm_display_info *info, void *disp)
  5010. {
  5011. struct dsi_display *display;
  5012. struct dsi_panel_phy_props phy_props;
  5013. struct dsi_host_common_cfg *host;
  5014. int i, rc;
  5015. if (!info || !disp) {
  5016. DSI_ERR("invalid params\n");
  5017. return -EINVAL;
  5018. }
  5019. display = disp;
  5020. if (!display->panel) {
  5021. DSI_ERR("invalid display panel\n");
  5022. return -EINVAL;
  5023. }
  5024. mutex_lock(&display->display_lock);
  5025. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5026. if (rc) {
  5027. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5028. display->name, rc);
  5029. goto error;
  5030. }
  5031. memset(info, 0, sizeof(struct msm_display_info));
  5032. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5033. info->num_of_h_tiles = display->ctrl_count;
  5034. for (i = 0; i < info->num_of_h_tiles; i++)
  5035. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5036. info->is_connected = display->is_active;
  5037. if (!strcmp(display->display_type, "primary"))
  5038. info->display_type = SDE_CONNECTOR_PRIMARY;
  5039. else if (!strcmp(display->display_type, "secondary"))
  5040. info->display_type = SDE_CONNECTOR_SECONDARY;
  5041. info->width_mm = phy_props.panel_width_mm;
  5042. info->height_mm = phy_props.panel_height_mm;
  5043. info->max_width = 1920;
  5044. info->max_height = 1080;
  5045. info->qsync_min_fps =
  5046. display->panel->qsync_min_fps;
  5047. info->poms_align_vsync = display->panel->poms_align_vsync;
  5048. switch (display->panel->panel_mode) {
  5049. case DSI_OP_VIDEO_MODE:
  5050. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5051. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5052. if (display->panel->panel_mode_switch_enabled)
  5053. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5054. break;
  5055. case DSI_OP_CMD_MODE:
  5056. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5057. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5058. if (display->panel->panel_mode_switch_enabled)
  5059. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5060. info->is_te_using_watchdog_timer =
  5061. display->panel->te_using_watchdog_timer |
  5062. display->sw_te_using_wd;
  5063. break;
  5064. default:
  5065. DSI_ERR("unknwown dsi panel mode %d\n",
  5066. display->panel->panel_mode);
  5067. break;
  5068. }
  5069. if (display->panel->esd_config.esd_enabled &&
  5070. !display->sw_te_using_wd)
  5071. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5072. info->te_source = display->te_source;
  5073. host = &display->panel->host_config;
  5074. if (host->split_link.split_link_enabled)
  5075. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5076. error:
  5077. mutex_unlock(&display->display_lock);
  5078. return rc;
  5079. }
  5080. int dsi_display_get_mode_count(struct dsi_display *display,
  5081. u32 *count)
  5082. {
  5083. if (!display || !display->panel) {
  5084. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5085. display ? display->panel != NULL : 0);
  5086. return -EINVAL;
  5087. }
  5088. mutex_lock(&display->display_lock);
  5089. *count = display->panel->num_display_modes;
  5090. mutex_unlock(&display->display_lock);
  5091. return 0;
  5092. }
  5093. void dsi_display_adjust_mode_timing(
  5094. struct dsi_dyn_clk_caps *dyn_clk_caps,
  5095. struct dsi_display_mode *dsi_mode,
  5096. int lanes, int bpp)
  5097. {
  5098. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5099. /* Constant FPS is not supported on command mode */
  5100. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  5101. return;
  5102. if (!dyn_clk_caps->maintain_const_fps)
  5103. return;
  5104. /*
  5105. * When there is a dynamic clock switch, there is small change
  5106. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5107. * is adjusted. It has been assumed that the refined porch values
  5108. * are supported by the panel. This logic can be enhanced further
  5109. * in future by taking min/max porches supported by the panel.
  5110. */
  5111. switch (dyn_clk_caps->type) {
  5112. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5113. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5114. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5115. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5116. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5117. do_div(new_htotal, div);
  5118. if (old_htotal > new_htotal)
  5119. dsi_mode->timing.h_front_porch -=
  5120. (old_htotal - new_htotal);
  5121. else
  5122. dsi_mode->timing.h_front_porch +=
  5123. (new_htotal - old_htotal);
  5124. break;
  5125. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5126. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5127. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5128. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5129. do_div(new_vtotal, div);
  5130. dsi_mode->timing.v_front_porch = new_vtotal -
  5131. dsi_mode->timing.v_back_porch -
  5132. dsi_mode->timing.v_sync_width -
  5133. dsi_mode->timing.v_active;
  5134. break;
  5135. default:
  5136. break;
  5137. }
  5138. }
  5139. static void _dsi_display_populate_bit_clks(struct dsi_display *display,
  5140. int start, int end, u32 *mode_idx)
  5141. {
  5142. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5143. struct dsi_display_mode *src, *dst;
  5144. struct dsi_host_common_cfg *cfg;
  5145. int i, j, total_modes, bpp, lanes = 0;
  5146. if (!display || !mode_idx)
  5147. return;
  5148. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5149. if (!dyn_clk_caps->dyn_clk_support)
  5150. return;
  5151. cfg = &(display->panel->host_config);
  5152. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5153. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5154. lanes++;
  5155. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5156. lanes++;
  5157. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5158. lanes++;
  5159. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5160. lanes++;
  5161. total_modes = display->panel->num_display_modes;
  5162. for (i = start; i < end; i++) {
  5163. src = &display->modes[i];
  5164. if (!src)
  5165. return;
  5166. /*
  5167. * TODO: currently setting the first bit rate in
  5168. * the list as preferred rate. But ideally should
  5169. * be based on user or device tree preferrence.
  5170. */
  5171. src->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[0];
  5172. dsi_display_adjust_mode_timing(dyn_clk_caps, src, lanes, bpp);
  5173. src->pixel_clk_khz =
  5174. div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5175. src->pixel_clk_khz /= 1000;
  5176. src->pixel_clk_khz *= display->ctrl_count;
  5177. }
  5178. for (i = 1; i < dyn_clk_caps->bit_clk_list_len; i++) {
  5179. if (*mode_idx >= total_modes)
  5180. return;
  5181. for (j = start; j < end; j++) {
  5182. src = &display->modes[j];
  5183. dst = &display->modes[*mode_idx];
  5184. if (!src || !dst) {
  5185. DSI_ERR("invalid mode index\n");
  5186. return;
  5187. }
  5188. memcpy(dst, src, sizeof(struct dsi_display_mode));
  5189. dst->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[i];
  5190. dsi_display_adjust_mode_timing(dyn_clk_caps, dst, lanes,
  5191. bpp);
  5192. dst->pixel_clk_khz =
  5193. div_u64(dst->timing.clk_rate_hz * lanes, bpp);
  5194. dst->pixel_clk_khz /= 1000;
  5195. dst->pixel_clk_khz *= display->ctrl_count;
  5196. (*mode_idx)++;
  5197. }
  5198. }
  5199. }
  5200. void dsi_display_put_mode(struct dsi_display *display,
  5201. struct dsi_display_mode *mode)
  5202. {
  5203. dsi_panel_put_mode(mode);
  5204. }
  5205. int dsi_display_get_modes(struct dsi_display *display,
  5206. struct dsi_display_mode **out_modes)
  5207. {
  5208. struct dsi_dfps_capabilities dfps_caps;
  5209. struct dsi_display_ctrl *ctrl;
  5210. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5211. bool is_split_link, is_cmd_mode;
  5212. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5213. u32 sublinks_count, mode_idx, array_idx = 0;
  5214. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5215. int i, start, end, rc = -EINVAL;
  5216. if (!display || !out_modes) {
  5217. DSI_ERR("Invalid params\n");
  5218. return -EINVAL;
  5219. }
  5220. *out_modes = NULL;
  5221. ctrl = &display->ctrl[0];
  5222. mutex_lock(&display->display_lock);
  5223. if (display->modes)
  5224. goto exit;
  5225. display_mode_count = display->panel->num_display_modes;
  5226. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5227. GFP_KERNEL);
  5228. if (!display->modes) {
  5229. rc = -ENOMEM;
  5230. goto error;
  5231. }
  5232. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5233. if (rc) {
  5234. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5235. display->name);
  5236. goto error;
  5237. }
  5238. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5239. timing_mode_count = display->panel->num_timing_nodes;
  5240. /* Validate command line timing */
  5241. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5242. (display->cmdline_timing >= timing_mode_count))
  5243. display->cmdline_timing = NO_OVERRIDE;
  5244. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5245. struct dsi_display_mode display_mode;
  5246. int topology_override = NO_OVERRIDE;
  5247. bool is_preferred = false;
  5248. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5249. if (display->cmdline_timing == mode_idx) {
  5250. topology_override = display->cmdline_topology;
  5251. is_preferred = true;
  5252. }
  5253. memset(&display_mode, 0, sizeof(display_mode));
  5254. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5255. &display_mode,
  5256. topology_override);
  5257. if (rc) {
  5258. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5259. display->name, mode_idx);
  5260. goto error;
  5261. }
  5262. is_cmd_mode = (display_mode.panel_mode == DSI_OP_CMD_MODE);
  5263. /* Setup widebus support */
  5264. display_mode.priv_info->widebus_support =
  5265. ctrl->ctrl->hw.widebus_support;
  5266. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5267. is_cmd_mode) ? 1 : dfps_caps.dfps_list_len);
  5268. /* Calculate dsi frame transfer time */
  5269. if (is_cmd_mode) {
  5270. dsi_panel_calc_dsi_transfer_time(
  5271. &display->panel->host_config,
  5272. &display_mode, frame_threshold_us);
  5273. display_mode.priv_info->dsi_transfer_time_us =
  5274. display_mode.timing.dsi_transfer_time_us;
  5275. display_mode.priv_info->min_dsi_clk_hz =
  5276. display_mode.timing.min_dsi_clk_hz;
  5277. display_mode.priv_info->mdp_transfer_time_us =
  5278. display_mode.timing.mdp_transfer_time_us;
  5279. }
  5280. is_split_link = host->split_link.split_link_enabled;
  5281. sublinks_count = host->split_link.num_sublinks;
  5282. if (is_split_link && sublinks_count > 1) {
  5283. display_mode.timing.h_active *= sublinks_count;
  5284. display_mode.timing.h_front_porch *= sublinks_count;
  5285. display_mode.timing.h_sync_width *= sublinks_count;
  5286. display_mode.timing.h_back_porch *= sublinks_count;
  5287. display_mode.timing.h_skew *= sublinks_count;
  5288. display_mode.pixel_clk_khz *= sublinks_count;
  5289. } else {
  5290. display_mode.timing.h_active *= display->ctrl_count;
  5291. display_mode.timing.h_front_porch *=
  5292. display->ctrl_count;
  5293. display_mode.timing.h_sync_width *=
  5294. display->ctrl_count;
  5295. display_mode.timing.h_back_porch *=
  5296. display->ctrl_count;
  5297. display_mode.timing.h_skew *= display->ctrl_count;
  5298. display_mode.pixel_clk_khz *= display->ctrl_count;
  5299. }
  5300. start = array_idx;
  5301. for (i = 0; i < num_dfps_rates; i++) {
  5302. struct dsi_display_mode *sub_mode =
  5303. &display->modes[array_idx];
  5304. u32 curr_refresh_rate;
  5305. if (!sub_mode) {
  5306. DSI_ERR("invalid mode data\n");
  5307. rc = -EFAULT;
  5308. goto error;
  5309. }
  5310. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5311. array_idx++;
  5312. if (!dfps_caps.dfps_support || is_cmd_mode)
  5313. continue;
  5314. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5315. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5316. dsi_display_get_dfps_timing(display, sub_mode,
  5317. curr_refresh_rate);
  5318. }
  5319. end = array_idx;
  5320. /*
  5321. * if POMS is enabled and boot up mode is video mode,
  5322. * skip bit clk rates update for command mode,
  5323. * else if dynamic clk switch is supported then update all
  5324. * the bit clk rates.
  5325. */
  5326. if (is_cmd_mode &&
  5327. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  5328. continue;
  5329. _dsi_display_populate_bit_clks(display, start, end, &array_idx);
  5330. if (is_preferred) {
  5331. /* Set first timing sub mode as preferred mode */
  5332. display->modes[start].is_preferred = true;
  5333. }
  5334. }
  5335. exit:
  5336. *out_modes = display->modes;
  5337. rc = 0;
  5338. error:
  5339. if (rc)
  5340. kfree(display->modes);
  5341. mutex_unlock(&display->display_lock);
  5342. return rc;
  5343. }
  5344. int dsi_display_get_panel_vfp(void *dsi_display,
  5345. int h_active, int v_active)
  5346. {
  5347. int i, rc = 0;
  5348. u32 count, refresh_rate = 0;
  5349. struct dsi_dfps_capabilities dfps_caps;
  5350. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5351. struct dsi_host_common_cfg *host;
  5352. if (!display || !display->panel)
  5353. return -EINVAL;
  5354. mutex_lock(&display->display_lock);
  5355. count = display->panel->num_display_modes;
  5356. if (display->panel->cur_mode)
  5357. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5358. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5359. if (dfps_caps.dfps_support)
  5360. refresh_rate = dfps_caps.max_refresh_rate;
  5361. if (!refresh_rate) {
  5362. mutex_unlock(&display->display_lock);
  5363. DSI_ERR("Null Refresh Rate\n");
  5364. return -EINVAL;
  5365. }
  5366. host = &display->panel->host_config;
  5367. if (host->split_link.split_link_enabled)
  5368. h_active *= host->split_link.num_sublinks;
  5369. else
  5370. h_active *= display->ctrl_count;
  5371. for (i = 0; i < count; i++) {
  5372. struct dsi_display_mode *m = &display->modes[i];
  5373. if (m && v_active == m->timing.v_active &&
  5374. h_active == m->timing.h_active &&
  5375. refresh_rate == m->timing.refresh_rate) {
  5376. rc = m->timing.v_front_porch;
  5377. break;
  5378. }
  5379. }
  5380. mutex_unlock(&display->display_lock);
  5381. return rc;
  5382. }
  5383. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5384. {
  5385. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5386. u32 count, i;
  5387. int rc = 0;
  5388. *num_lm = 0;
  5389. mutex_lock(&display->display_lock);
  5390. count = display->panel->num_display_modes;
  5391. mutex_unlock(&display->display_lock);
  5392. if (!display->modes) {
  5393. struct dsi_display_mode *m;
  5394. rc = dsi_display_get_modes(display, &m);
  5395. if (rc)
  5396. return rc;
  5397. }
  5398. mutex_lock(&display->display_lock);
  5399. for (i = 0; i < count; i++) {
  5400. struct dsi_display_mode *m = &display->modes[i];
  5401. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5402. }
  5403. mutex_unlock(&display->display_lock);
  5404. return rc;
  5405. }
  5406. int dsi_display_find_mode(struct dsi_display *display,
  5407. const struct dsi_display_mode *cmp,
  5408. struct dsi_display_mode **out_mode)
  5409. {
  5410. u32 count, i;
  5411. int rc;
  5412. if (!display || !out_mode)
  5413. return -EINVAL;
  5414. *out_mode = NULL;
  5415. mutex_lock(&display->display_lock);
  5416. count = display->panel->num_display_modes;
  5417. mutex_unlock(&display->display_lock);
  5418. if (!display->modes) {
  5419. struct dsi_display_mode *m;
  5420. rc = dsi_display_get_modes(display, &m);
  5421. if (rc)
  5422. return rc;
  5423. }
  5424. mutex_lock(&display->display_lock);
  5425. for (i = 0; i < count; i++) {
  5426. struct dsi_display_mode *m = &display->modes[i];
  5427. if (cmp->timing.v_active == m->timing.v_active &&
  5428. cmp->timing.h_active == m->timing.h_active &&
  5429. cmp->timing.refresh_rate == m->timing.refresh_rate &&
  5430. cmp->panel_mode == m->panel_mode &&
  5431. cmp->pixel_clk_khz == m->pixel_clk_khz) {
  5432. *out_mode = m;
  5433. rc = 0;
  5434. break;
  5435. }
  5436. }
  5437. mutex_unlock(&display->display_lock);
  5438. if (!*out_mode) {
  5439. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  5440. display->name, cmp->timing.v_active,
  5441. cmp->timing.h_active, cmp->timing.refresh_rate,
  5442. cmp->pixel_clk_khz);
  5443. rc = -ENOENT;
  5444. }
  5445. return rc;
  5446. }
  5447. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  5448. struct dsi_display_mode *adj)
  5449. {
  5450. /*
  5451. * If there is a change in the hfp or vfp of the current and adjoining
  5452. * mode,then either it is a dfps mode switch or dynamic clk change with
  5453. * constant fps.
  5454. */
  5455. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  5456. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  5457. return true;
  5458. else
  5459. return false;
  5460. }
  5461. /**
  5462. * dsi_display_validate_mode_change() - Validate mode change case.
  5463. * @display: DSI display handle.
  5464. * @cur_mode: Current mode.
  5465. * @adj_mode: Mode to be set.
  5466. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  5467. * is change in hfp or vfp but vactive and hactive are same.
  5468. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  5469. * is change in clk but vactive and hactive are same.
  5470. * Return: error code.
  5471. */
  5472. int dsi_display_validate_mode_change(struct dsi_display *display,
  5473. struct dsi_display_mode *cur_mode,
  5474. struct dsi_display_mode *adj_mode)
  5475. {
  5476. int rc = 0;
  5477. struct dsi_dfps_capabilities dfps_caps;
  5478. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5479. if (!display || !adj_mode) {
  5480. DSI_ERR("Invalid params\n");
  5481. return -EINVAL;
  5482. }
  5483. if (!display->panel || !display->panel->cur_mode) {
  5484. DSI_DEBUG("Current panel mode not set\n");
  5485. return rc;
  5486. }
  5487. mutex_lock(&display->display_lock);
  5488. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5489. if ((cur_mode->timing.v_active == adj_mode->timing.v_active) &&
  5490. (cur_mode->timing.h_active == adj_mode->timing.h_active) &&
  5491. (cur_mode->panel_mode == adj_mode->panel_mode)) {
  5492. /* dfps and dynamic clock with const fps use case */
  5493. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  5494. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5495. if (dfps_caps.dfps_support ||
  5496. dyn_clk_caps->maintain_const_fps) {
  5497. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  5498. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  5499. SDE_EVT32(cur_mode->timing.refresh_rate,
  5500. adj_mode->timing.refresh_rate,
  5501. cur_mode->timing.h_front_porch,
  5502. adj_mode->timing.h_front_porch);
  5503. }
  5504. }
  5505. /* dynamic clk change use case */
  5506. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  5507. if (dyn_clk_caps->dyn_clk_support) {
  5508. DSI_DEBUG("dynamic clk change detected\n");
  5509. if ((adj_mode->dsi_mode_flags &
  5510. DSI_MODE_FLAG_VRR) &&
  5511. (!dyn_clk_caps->maintain_const_fps)) {
  5512. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  5513. rc = -ENOTSUPP;
  5514. goto error;
  5515. }
  5516. adj_mode->dsi_mode_flags |=
  5517. DSI_MODE_FLAG_DYN_CLK;
  5518. SDE_EVT32(cur_mode->pixel_clk_khz,
  5519. adj_mode->pixel_clk_khz);
  5520. }
  5521. }
  5522. }
  5523. error:
  5524. mutex_unlock(&display->display_lock);
  5525. return rc;
  5526. }
  5527. int dsi_display_validate_mode(struct dsi_display *display,
  5528. struct dsi_display_mode *mode,
  5529. u32 flags)
  5530. {
  5531. int rc = 0;
  5532. int i;
  5533. struct dsi_display_ctrl *ctrl;
  5534. struct dsi_display_mode adj_mode;
  5535. if (!display || !mode) {
  5536. DSI_ERR("Invalid params\n");
  5537. return -EINVAL;
  5538. }
  5539. mutex_lock(&display->display_lock);
  5540. adj_mode = *mode;
  5541. adjust_timing_by_ctrl_count(display, &adj_mode);
  5542. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  5543. if (rc) {
  5544. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  5545. display->name, rc);
  5546. goto error;
  5547. }
  5548. display_for_each_ctrl(i, display) {
  5549. ctrl = &display->ctrl[i];
  5550. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  5551. if (rc) {
  5552. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  5553. display->name, rc);
  5554. goto error;
  5555. }
  5556. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  5557. if (rc) {
  5558. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  5559. display->name, rc);
  5560. goto error;
  5561. }
  5562. }
  5563. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  5564. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  5565. rc = dsi_display_validate_mode_seamless(display, mode);
  5566. if (rc) {
  5567. DSI_ERR("[%s] seamless not possible rc=%d\n",
  5568. display->name, rc);
  5569. goto error;
  5570. }
  5571. }
  5572. error:
  5573. mutex_unlock(&display->display_lock);
  5574. return rc;
  5575. }
  5576. int dsi_display_set_mode(struct dsi_display *display,
  5577. struct dsi_display_mode *mode,
  5578. u32 flags)
  5579. {
  5580. int rc = 0;
  5581. struct dsi_display_mode adj_mode;
  5582. struct dsi_mode_info timing;
  5583. if (!display || !mode || !display->panel) {
  5584. DSI_ERR("Invalid params\n");
  5585. return -EINVAL;
  5586. }
  5587. mutex_lock(&display->display_lock);
  5588. adj_mode = *mode;
  5589. timing = adj_mode.timing;
  5590. adjust_timing_by_ctrl_count(display, &adj_mode);
  5591. if (!display->panel->cur_mode) {
  5592. display->panel->cur_mode =
  5593. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  5594. if (!display->panel->cur_mode) {
  5595. rc = -ENOMEM;
  5596. goto error;
  5597. }
  5598. }
  5599. /*For dynamic DSI setting, use specified clock rate */
  5600. if (display->cached_clk_rate > 0)
  5601. adj_mode.priv_info->clk_rate_hz = display->cached_clk_rate;
  5602. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  5603. if (rc) {
  5604. DSI_ERR("[%s] mode cannot be set\n", display->name);
  5605. goto error;
  5606. }
  5607. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  5608. if (rc) {
  5609. DSI_ERR("[%s] failed to set mode\n", display->name);
  5610. goto error;
  5611. }
  5612. DSI_INFO("mdp_transfer_time_us=%d us\n",
  5613. adj_mode.priv_info->mdp_transfer_time_us);
  5614. DSI_INFO("hactive= %d,vactive= %d,fps=%d\n",
  5615. timing.h_active, timing.v_active,
  5616. timing.refresh_rate);
  5617. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  5618. error:
  5619. mutex_unlock(&display->display_lock);
  5620. return rc;
  5621. }
  5622. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  5623. {
  5624. int rc = 0;
  5625. int i;
  5626. struct dsi_display_ctrl *ctrl;
  5627. if (!display) {
  5628. DSI_ERR("Invalid params\n");
  5629. return -EINVAL;
  5630. }
  5631. display_for_each_ctrl(i, display) {
  5632. ctrl = &display->ctrl[i];
  5633. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  5634. if (rc) {
  5635. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  5636. display->name, i);
  5637. goto error;
  5638. }
  5639. }
  5640. display->is_tpg_enabled = enable;
  5641. error:
  5642. return rc;
  5643. }
  5644. static int dsi_display_pre_switch(struct dsi_display *display)
  5645. {
  5646. int rc = 0;
  5647. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  5648. DSI_CORE_CLK, DSI_CLK_ON);
  5649. if (rc) {
  5650. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  5651. display->name, rc);
  5652. goto error;
  5653. }
  5654. rc = dsi_display_ctrl_update(display);
  5655. if (rc) {
  5656. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  5657. display->name, rc);
  5658. goto error_ctrl_clk_off;
  5659. }
  5660. rc = dsi_display_set_clk_src(display);
  5661. if (rc) {
  5662. DSI_ERR("[%s] failed to set DSI link clock source, rc=%d\n",
  5663. display->name, rc);
  5664. goto error_ctrl_deinit;
  5665. }
  5666. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  5667. DSI_LINK_CLK, DSI_CLK_ON);
  5668. if (rc) {
  5669. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  5670. display->name, rc);
  5671. goto error_ctrl_deinit;
  5672. }
  5673. goto error;
  5674. error_ctrl_deinit:
  5675. (void)dsi_display_ctrl_deinit(display);
  5676. error_ctrl_clk_off:
  5677. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  5678. DSI_CORE_CLK, DSI_CLK_OFF);
  5679. error:
  5680. return rc;
  5681. }
  5682. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  5683. {
  5684. int i;
  5685. struct dsi_display_ctrl *ctrl;
  5686. display_for_each_ctrl(i, display) {
  5687. ctrl = &display->ctrl[i];
  5688. if (!ctrl->ctrl)
  5689. continue;
  5690. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  5691. return false;
  5692. }
  5693. return true;
  5694. }
  5695. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  5696. {
  5697. struct dsi_display *display = NULL;
  5698. display = container_of(work, struct dsi_display, fifo_underflow_work);
  5699. if (!display || !display->panel ||
  5700. atomic_read(&display->panel->esd_recovery_pending)) {
  5701. DSI_DEBUG("Invalid recovery use case\n");
  5702. return;
  5703. }
  5704. mutex_lock(&display->display_lock);
  5705. if (!_dsi_display_validate_host_state(display)) {
  5706. mutex_unlock(&display->display_lock);
  5707. return;
  5708. }
  5709. DSI_INFO("handle DSI FIFO underflow error\n");
  5710. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  5711. dsi_display_clk_ctrl(display->dsi_clk_handle,
  5712. DSI_ALL_CLKS, DSI_CLK_ON);
  5713. dsi_display_soft_reset(display);
  5714. dsi_display_clk_ctrl(display->dsi_clk_handle,
  5715. DSI_ALL_CLKS, DSI_CLK_OFF);
  5716. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  5717. mutex_unlock(&display->display_lock);
  5718. }
  5719. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  5720. {
  5721. struct dsi_display *display = NULL;
  5722. struct dsi_display_ctrl *ctrl;
  5723. int i, rc;
  5724. int mask = BIT(20); /* clock lane */
  5725. int (*cb_func)(void *event_usr_ptr,
  5726. uint32_t event_idx, uint32_t instance_idx,
  5727. uint32_t data0, uint32_t data1,
  5728. uint32_t data2, uint32_t data3);
  5729. void *data;
  5730. u32 version = 0;
  5731. display = container_of(work, struct dsi_display, fifo_overflow_work);
  5732. if (!display || !display->panel ||
  5733. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  5734. atomic_read(&display->panel->esd_recovery_pending)) {
  5735. DSI_DEBUG("Invalid recovery use case\n");
  5736. return;
  5737. }
  5738. mutex_lock(&display->display_lock);
  5739. if (!_dsi_display_validate_host_state(display)) {
  5740. mutex_unlock(&display->display_lock);
  5741. return;
  5742. }
  5743. DSI_INFO("handle DSI FIFO overflow error\n");
  5744. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  5745. dsi_display_clk_ctrl(display->dsi_clk_handle,
  5746. DSI_ALL_CLKS, DSI_CLK_ON);
  5747. /*
  5748. * below recovery sequence is not applicable to
  5749. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  5750. */
  5751. ctrl = &display->ctrl[display->clk_master_idx];
  5752. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  5753. if (!version || (version < 0x20020001))
  5754. goto end;
  5755. /* reset ctrl and lanes */
  5756. display_for_each_ctrl(i, display) {
  5757. ctrl = &display->ctrl[i];
  5758. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  5759. rc = dsi_phy_lane_reset(ctrl->phy);
  5760. }
  5761. /* wait for display line count to be in active area */
  5762. ctrl = &display->ctrl[display->clk_master_idx];
  5763. if (ctrl->ctrl->recovery_cb.event_cb) {
  5764. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  5765. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  5766. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  5767. display->clk_master_idx, 0, 0, 0, 0);
  5768. if (rc < 0) {
  5769. DSI_DEBUG("sde callback failed\n");
  5770. goto end;
  5771. }
  5772. }
  5773. /* Enable Video mode for DSI controller */
  5774. display_for_each_ctrl(i, display) {
  5775. ctrl = &display->ctrl[i];
  5776. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  5777. }
  5778. /*
  5779. * Add sufficient delay to make sure
  5780. * pixel transmission has started
  5781. */
  5782. udelay(200);
  5783. end:
  5784. dsi_display_clk_ctrl(display->dsi_clk_handle,
  5785. DSI_ALL_CLKS, DSI_CLK_OFF);
  5786. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  5787. mutex_unlock(&display->display_lock);
  5788. }
  5789. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  5790. {
  5791. struct dsi_display *display = NULL;
  5792. struct dsi_display_ctrl *ctrl;
  5793. int i, rc;
  5794. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  5795. int (*cb_func)(void *event_usr_ptr,
  5796. uint32_t event_idx, uint32_t instance_idx,
  5797. uint32_t data0, uint32_t data1,
  5798. uint32_t data2, uint32_t data3);
  5799. void *data;
  5800. u32 version = 0;
  5801. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  5802. if (!display || !display->panel ||
  5803. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  5804. atomic_read(&display->panel->esd_recovery_pending)) {
  5805. DSI_DEBUG("Invalid recovery use case\n");
  5806. return;
  5807. }
  5808. mutex_lock(&display->display_lock);
  5809. if (!_dsi_display_validate_host_state(display)) {
  5810. mutex_unlock(&display->display_lock);
  5811. return;
  5812. }
  5813. DSI_INFO("handle DSI LP RX Timeout error\n");
  5814. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  5815. dsi_display_clk_ctrl(display->dsi_clk_handle,
  5816. DSI_ALL_CLKS, DSI_CLK_ON);
  5817. /*
  5818. * below recovery sequence is not applicable to
  5819. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  5820. */
  5821. ctrl = &display->ctrl[display->clk_master_idx];
  5822. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  5823. if (!version || (version < 0x20020001))
  5824. goto end;
  5825. /* reset ctrl and lanes */
  5826. display_for_each_ctrl(i, display) {
  5827. ctrl = &display->ctrl[i];
  5828. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  5829. rc = dsi_phy_lane_reset(ctrl->phy);
  5830. }
  5831. ctrl = &display->ctrl[display->clk_master_idx];
  5832. if (ctrl->ctrl->recovery_cb.event_cb) {
  5833. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  5834. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  5835. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  5836. display->clk_master_idx, 0, 0, 0, 0);
  5837. if (rc < 0) {
  5838. DSI_DEBUG("Target is in suspend/shutdown\n");
  5839. goto end;
  5840. }
  5841. }
  5842. /* Enable Video mode for DSI controller */
  5843. display_for_each_ctrl(i, display) {
  5844. ctrl = &display->ctrl[i];
  5845. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  5846. }
  5847. /*
  5848. * Add sufficient delay to make sure
  5849. * pixel transmission as started
  5850. */
  5851. udelay(200);
  5852. end:
  5853. dsi_display_clk_ctrl(display->dsi_clk_handle,
  5854. DSI_ALL_CLKS, DSI_CLK_OFF);
  5855. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  5856. mutex_unlock(&display->display_lock);
  5857. }
  5858. static int dsi_display_cb_error_handler(void *data,
  5859. uint32_t event_idx, uint32_t instance_idx,
  5860. uint32_t data0, uint32_t data1,
  5861. uint32_t data2, uint32_t data3)
  5862. {
  5863. struct dsi_display *display = data;
  5864. if (!display || !(display->err_workq))
  5865. return -EINVAL;
  5866. switch (event_idx) {
  5867. case DSI_FIFO_UNDERFLOW:
  5868. queue_work(display->err_workq, &display->fifo_underflow_work);
  5869. break;
  5870. case DSI_FIFO_OVERFLOW:
  5871. queue_work(display->err_workq, &display->fifo_overflow_work);
  5872. break;
  5873. case DSI_LP_Rx_TIMEOUT:
  5874. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  5875. break;
  5876. default:
  5877. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  5878. break;
  5879. }
  5880. return 0;
  5881. }
  5882. static void dsi_display_register_error_handler(struct dsi_display *display)
  5883. {
  5884. int i = 0;
  5885. struct dsi_display_ctrl *ctrl;
  5886. struct dsi_event_cb_info event_info;
  5887. if (!display)
  5888. return;
  5889. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  5890. if (!display->err_workq) {
  5891. DSI_ERR("failed to create dsi workq!\n");
  5892. return;
  5893. }
  5894. INIT_WORK(&display->fifo_underflow_work,
  5895. dsi_display_handle_fifo_underflow);
  5896. INIT_WORK(&display->fifo_overflow_work,
  5897. dsi_display_handle_fifo_overflow);
  5898. INIT_WORK(&display->lp_rx_timeout_work,
  5899. dsi_display_handle_lp_rx_timeout);
  5900. memset(&event_info, 0, sizeof(event_info));
  5901. event_info.event_cb = dsi_display_cb_error_handler;
  5902. event_info.event_usr_ptr = display;
  5903. display_for_each_ctrl(i, display) {
  5904. ctrl = &display->ctrl[i];
  5905. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  5906. }
  5907. }
  5908. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  5909. {
  5910. int i = 0;
  5911. struct dsi_display_ctrl *ctrl;
  5912. if (!display)
  5913. return;
  5914. display_for_each_ctrl(i, display) {
  5915. ctrl = &display->ctrl[i];
  5916. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  5917. 0, sizeof(struct dsi_event_cb_info));
  5918. }
  5919. if (display->err_workq) {
  5920. destroy_workqueue(display->err_workq);
  5921. display->err_workq = NULL;
  5922. }
  5923. }
  5924. int dsi_display_prepare(struct dsi_display *display)
  5925. {
  5926. int rc = 0;
  5927. struct dsi_display_mode *mode;
  5928. if (!display) {
  5929. DSI_ERR("Invalid params\n");
  5930. return -EINVAL;
  5931. }
  5932. if (!display->panel->cur_mode) {
  5933. DSI_ERR("no valid mode set for the display\n");
  5934. return -EINVAL;
  5935. }
  5936. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  5937. mutex_lock(&display->display_lock);
  5938. mode = display->panel->cur_mode;
  5939. dsi_display_set_ctrl_esd_check_flag(display, false);
  5940. /* Set up ctrl isr before enabling core clk */
  5941. dsi_display_ctrl_isr_configure(display, true);
  5942. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  5943. if (display->is_cont_splash_enabled &&
  5944. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  5945. DSI_ERR("DMS not supported on first frame\n");
  5946. rc = -EINVAL;
  5947. goto error;
  5948. }
  5949. if (!display->is_cont_splash_enabled) {
  5950. /* update dsi ctrl for new mode */
  5951. rc = dsi_display_pre_switch(display);
  5952. if (rc)
  5953. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  5954. display->name, rc);
  5955. goto error;
  5956. }
  5957. }
  5958. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) &&
  5959. (!display->is_cont_splash_enabled)) {
  5960. /*
  5961. * For continuous splash usecase we skip panel
  5962. * pre prepare since the regulator vote is already
  5963. * taken care in splash resource init
  5964. */
  5965. rc = dsi_panel_pre_prepare(display->panel);
  5966. if (rc) {
  5967. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  5968. display->name, rc);
  5969. goto error;
  5970. }
  5971. }
  5972. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  5973. DSI_CORE_CLK, DSI_CLK_ON);
  5974. if (rc) {
  5975. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  5976. display->name, rc);
  5977. goto error_panel_post_unprep;
  5978. }
  5979. /*
  5980. * If ULPS during suspend feature is enabled, then DSI PHY was
  5981. * left on during suspend. In this case, we do not need to reset/init
  5982. * PHY. This would have already been done when the CORE clocks are
  5983. * turned on. However, if cont splash is disabled, the first time DSI
  5984. * is powered on, phy init needs to be done unconditionally.
  5985. */
  5986. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  5987. rc = dsi_display_phy_sw_reset(display);
  5988. if (rc) {
  5989. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  5990. display->name, rc);
  5991. goto error_ctrl_clk_off;
  5992. }
  5993. rc = dsi_display_phy_enable(display);
  5994. if (rc) {
  5995. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  5996. display->name, rc);
  5997. goto error_ctrl_clk_off;
  5998. }
  5999. }
  6000. rc = dsi_display_set_clk_src(display);
  6001. if (rc) {
  6002. DSI_ERR("[%s] failed to set DSI link clock source, rc=%d\n",
  6003. display->name, rc);
  6004. goto error_phy_disable;
  6005. }
  6006. rc = dsi_display_ctrl_init(display);
  6007. if (rc) {
  6008. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6009. display->name, rc);
  6010. goto error_phy_disable;
  6011. }
  6012. /* Set up DSI ERROR event callback */
  6013. dsi_display_register_error_handler(display);
  6014. rc = dsi_display_ctrl_host_enable(display);
  6015. if (rc) {
  6016. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6017. display->name, rc);
  6018. goto error_ctrl_deinit;
  6019. }
  6020. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6021. DSI_LINK_CLK, DSI_CLK_ON);
  6022. if (rc) {
  6023. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6024. display->name, rc);
  6025. goto error_host_engine_off;
  6026. }
  6027. if (!display->is_cont_splash_enabled) {
  6028. /*
  6029. * For continuous splash usecase, skip panel prepare and
  6030. * ctl reset since the pnael and ctrl is already in active
  6031. * state and panel on commands are not needed
  6032. */
  6033. rc = dsi_display_soft_reset(display);
  6034. if (rc) {
  6035. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6036. display->name, rc);
  6037. goto error_ctrl_link_off;
  6038. }
  6039. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)) {
  6040. rc = dsi_panel_prepare(display->panel);
  6041. if (rc) {
  6042. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6043. display->name, rc);
  6044. goto error_ctrl_link_off;
  6045. }
  6046. }
  6047. }
  6048. goto error;
  6049. error_ctrl_link_off:
  6050. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6051. DSI_LINK_CLK, DSI_CLK_OFF);
  6052. error_host_engine_off:
  6053. (void)dsi_display_ctrl_host_disable(display);
  6054. error_ctrl_deinit:
  6055. (void)dsi_display_ctrl_deinit(display);
  6056. error_phy_disable:
  6057. (void)dsi_display_phy_disable(display);
  6058. error_ctrl_clk_off:
  6059. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6060. DSI_CORE_CLK, DSI_CLK_OFF);
  6061. error_panel_post_unprep:
  6062. (void)dsi_panel_post_unprepare(display->panel);
  6063. error:
  6064. mutex_unlock(&display->display_lock);
  6065. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6066. return rc;
  6067. }
  6068. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6069. const struct dsi_display_ctrl *ctrl,
  6070. const struct msm_roi_list *req_rois,
  6071. struct dsi_rect *out_roi)
  6072. {
  6073. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6074. struct dsi_display_mode *cur_mode;
  6075. struct msm_roi_caps *roi_caps;
  6076. struct dsi_rect req_roi = { 0 };
  6077. int rc = 0;
  6078. cur_mode = display->panel->cur_mode;
  6079. if (!cur_mode)
  6080. return 0;
  6081. roi_caps = &cur_mode->priv_info->roi_caps;
  6082. if (req_rois->num_rects > roi_caps->num_roi) {
  6083. DSI_ERR("request for %d rois greater than max %d\n",
  6084. req_rois->num_rects,
  6085. roi_caps->num_roi);
  6086. rc = -EINVAL;
  6087. goto exit;
  6088. }
  6089. /**
  6090. * if no rois, user wants to reset back to full resolution
  6091. * note: h_active is already divided by ctrl_count
  6092. */
  6093. if (!req_rois->num_rects) {
  6094. *out_roi = *bounds;
  6095. goto exit;
  6096. }
  6097. /* intersect with the bounds */
  6098. req_roi.x = req_rois->roi[0].x1;
  6099. req_roi.y = req_rois->roi[0].y1;
  6100. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6101. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6102. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6103. exit:
  6104. /* adjust the ctrl origin to be top left within the ctrl */
  6105. out_roi->x = out_roi->x - bounds->x;
  6106. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6107. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6108. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6109. bounds->x, bounds->y, bounds->w, bounds->h,
  6110. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6111. return rc;
  6112. }
  6113. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6114. {
  6115. int i;
  6116. int rc = 0;
  6117. if (!display->panel->qsync_min_fps) {
  6118. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6119. return 0;
  6120. }
  6121. mutex_lock(&display->display_lock);
  6122. display_for_each_ctrl(i, display) {
  6123. if (enable) {
  6124. /* send the commands to enable qsync */
  6125. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6126. if (rc) {
  6127. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6128. goto exit;
  6129. }
  6130. } else {
  6131. /* send the commands to enable qsync */
  6132. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6133. if (rc) {
  6134. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6135. goto exit;
  6136. }
  6137. }
  6138. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6139. }
  6140. exit:
  6141. SDE_EVT32(enable, display->panel->qsync_min_fps, rc);
  6142. mutex_unlock(&display->display_lock);
  6143. return rc;
  6144. }
  6145. static int dsi_display_set_roi(struct dsi_display *display,
  6146. struct msm_roi_list *rois)
  6147. {
  6148. struct dsi_display_mode *cur_mode;
  6149. struct msm_roi_caps *roi_caps;
  6150. int rc = 0;
  6151. int i;
  6152. if (!display || !rois || !display->panel)
  6153. return -EINVAL;
  6154. cur_mode = display->panel->cur_mode;
  6155. if (!cur_mode)
  6156. return 0;
  6157. roi_caps = &cur_mode->priv_info->roi_caps;
  6158. if (!roi_caps->enabled)
  6159. return 0;
  6160. display_for_each_ctrl(i, display) {
  6161. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6162. struct dsi_rect ctrl_roi;
  6163. bool changed = false;
  6164. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6165. if (rc) {
  6166. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6167. return rc;
  6168. }
  6169. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6170. if (rc) {
  6171. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6172. return rc;
  6173. }
  6174. if (!changed)
  6175. continue;
  6176. /* send the new roi to the panel via dcs commands */
  6177. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6178. if (rc) {
  6179. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6180. return rc;
  6181. }
  6182. /* re-program the ctrl with the timing based on the new roi */
  6183. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6184. if (rc) {
  6185. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6186. return rc;
  6187. }
  6188. }
  6189. return rc;
  6190. }
  6191. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6192. struct dsi_display *display,
  6193. struct msm_display_kickoff_params *params)
  6194. {
  6195. int rc = 0;
  6196. int i;
  6197. /* check and setup MISR */
  6198. if (display->misr_enable)
  6199. _dsi_display_setup_misr(display);
  6200. rc = dsi_display_set_roi(display, params->rois);
  6201. /* dynamic DSI clock setting */
  6202. if (atomic_read(&display->clkrate_change_pending)) {
  6203. mutex_lock(&display->display_lock);
  6204. /*
  6205. * acquire panel_lock to make sure no commands are in progress
  6206. */
  6207. dsi_panel_acquire_panel_lock(display->panel);
  6208. /*
  6209. * Wait for DSI command engine not to be busy sending data
  6210. * from display engine.
  6211. * If waiting fails, return "rc" instead of below "ret" so as
  6212. * not to impact DRM commit. The clock updating would be
  6213. * deferred to the next DRM commit.
  6214. */
  6215. display_for_each_ctrl(i, display) {
  6216. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6217. int ret = 0;
  6218. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6219. if (ret)
  6220. goto wait_failure;
  6221. }
  6222. /*
  6223. * Don't check the return value so as not to impact DRM commit
  6224. * when error occurs.
  6225. */
  6226. (void)dsi_display_force_update_dsi_clk(display);
  6227. wait_failure:
  6228. /* release panel_lock */
  6229. dsi_panel_release_panel_lock(display->panel);
  6230. mutex_unlock(&display->display_lock);
  6231. }
  6232. return rc;
  6233. }
  6234. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6235. {
  6236. int rc = 0;
  6237. if (!display || !display->panel) {
  6238. DSI_ERR("Invalid params\n");
  6239. return -EINVAL;
  6240. }
  6241. if (!display->panel->cur_mode) {
  6242. DSI_ERR("no valid mode set for the display\n");
  6243. return -EINVAL;
  6244. }
  6245. if (!display->is_cont_splash_enabled)
  6246. return 0;
  6247. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6248. rc = dsi_display_vid_engine_enable(display);
  6249. if (rc) {
  6250. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6251. display->name, rc);
  6252. goto error_out;
  6253. }
  6254. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6255. rc = dsi_display_cmd_engine_enable(display);
  6256. if (rc) {
  6257. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6258. display->name, rc);
  6259. goto error_out;
  6260. }
  6261. } else {
  6262. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6263. rc = -EINVAL;
  6264. }
  6265. error_out:
  6266. return rc;
  6267. }
  6268. int dsi_display_pre_commit(void *display,
  6269. struct msm_display_conn_params *params)
  6270. {
  6271. bool enable = false;
  6272. int rc = 0;
  6273. if (!display || !params) {
  6274. pr_err("Invalid params\n");
  6275. return -EINVAL;
  6276. }
  6277. if (params->qsync_update) {
  6278. enable = (params->qsync_mode > 0) ? true : false;
  6279. rc = dsi_display_qsync(display, enable);
  6280. if (rc)
  6281. pr_err("%s failed to send qsync commands\n",
  6282. __func__);
  6283. SDE_EVT32(params->qsync_mode, rc);
  6284. }
  6285. return rc;
  6286. }
  6287. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6288. {
  6289. if (display->panel_id != ~0x0 &&
  6290. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6291. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6292. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6293. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6294. 0, ((display->panel_id & 0xffffffff00000000) >> 31),
  6295. (display->panel_id & 0xffffffff), 0, 0);
  6296. }
  6297. }
  6298. int dsi_display_enable(struct dsi_display *display)
  6299. {
  6300. int rc = 0;
  6301. struct dsi_display_mode *mode;
  6302. if (!display || !display->panel) {
  6303. DSI_ERR("Invalid params\n");
  6304. return -EINVAL;
  6305. }
  6306. if (!display->panel->cur_mode) {
  6307. DSI_ERR("no valid mode set for the display\n");
  6308. return -EINVAL;
  6309. }
  6310. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6311. /* Engine states and panel states are populated during splash
  6312. * resource init and hence we return early
  6313. */
  6314. if (display->is_cont_splash_enabled) {
  6315. dsi_display_config_ctrl_for_cont_splash(display);
  6316. rc = dsi_display_splash_res_cleanup(display);
  6317. if (rc) {
  6318. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6319. rc);
  6320. return -EINVAL;
  6321. }
  6322. display->panel->panel_initialized = true;
  6323. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6324. dsi_display_panel_id_notification(display);
  6325. return 0;
  6326. }
  6327. mutex_lock(&display->display_lock);
  6328. mode = display->panel->cur_mode;
  6329. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6330. rc = dsi_panel_post_switch(display->panel);
  6331. if (rc) {
  6332. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6333. display->name, rc);
  6334. goto error;
  6335. }
  6336. } else if (!(display->panel->cur_mode->dsi_mode_flags &
  6337. DSI_MODE_FLAG_POMS)){
  6338. rc = dsi_panel_enable(display->panel);
  6339. if (rc) {
  6340. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6341. display->name, rc);
  6342. goto error;
  6343. }
  6344. }
  6345. dsi_display_panel_id_notification(display);
  6346. /* Block sending pps command if modeset is due to fps difference */
  6347. if ((mode->priv_info->dsc_enabled ||
  6348. mode->priv_info->vdc_enabled) &&
  6349. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6350. rc = dsi_panel_update_pps(display->panel);
  6351. if (rc) {
  6352. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6353. display->name, rc);
  6354. goto error;
  6355. }
  6356. }
  6357. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6358. rc = dsi_panel_switch(display->panel);
  6359. if (rc)
  6360. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6361. display->name, rc);
  6362. goto error;
  6363. }
  6364. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6365. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6366. rc = dsi_display_vid_engine_enable(display);
  6367. if (rc) {
  6368. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6369. display->name, rc);
  6370. goto error_disable_panel;
  6371. }
  6372. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6373. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6374. rc = dsi_display_cmd_engine_enable(display);
  6375. if (rc) {
  6376. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6377. display->name, rc);
  6378. goto error_disable_panel;
  6379. }
  6380. } else {
  6381. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6382. rc = -EINVAL;
  6383. goto error_disable_panel;
  6384. }
  6385. goto error;
  6386. error_disable_panel:
  6387. (void)dsi_panel_disable(display->panel);
  6388. error:
  6389. mutex_unlock(&display->display_lock);
  6390. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6391. return rc;
  6392. }
  6393. int dsi_display_post_enable(struct dsi_display *display)
  6394. {
  6395. int rc = 0;
  6396. if (!display) {
  6397. DSI_ERR("Invalid params\n");
  6398. return -EINVAL;
  6399. }
  6400. mutex_lock(&display->display_lock);
  6401. if (display->panel->cur_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) {
  6402. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6403. dsi_panel_mode_switch_to_cmd(display->panel);
  6404. if (display->config.panel_mode == DSI_OP_VIDEO_MODE)
  6405. dsi_panel_mode_switch_to_vid(display->panel);
  6406. } else {
  6407. rc = dsi_panel_post_enable(display->panel);
  6408. if (rc)
  6409. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  6410. display->name, rc);
  6411. }
  6412. /* remove the clk vote for CMD mode panels */
  6413. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6414. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6415. DSI_ALL_CLKS, DSI_CLK_OFF);
  6416. mutex_unlock(&display->display_lock);
  6417. return rc;
  6418. }
  6419. int dsi_display_pre_disable(struct dsi_display *display)
  6420. {
  6421. int rc = 0;
  6422. if (!display) {
  6423. DSI_ERR("Invalid params\n");
  6424. return -EINVAL;
  6425. }
  6426. mutex_lock(&display->display_lock);
  6427. /* enable the clk vote for CMD mode panels */
  6428. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6429. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6430. DSI_ALL_CLKS, DSI_CLK_ON);
  6431. if (display->poms_pending) {
  6432. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6433. dsi_panel_pre_mode_switch_to_video(display->panel);
  6434. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6435. /*
  6436. * Add unbalanced vote for clock & cmd engine to enable
  6437. * async trigger of pre video to cmd mode switch.
  6438. */
  6439. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6440. DSI_ALL_CLKS, DSI_CLK_ON);
  6441. if (rc) {
  6442. DSI_ERR("[%s]failed to enable all clocks,rc=%d",
  6443. display->name, rc);
  6444. goto exit;
  6445. }
  6446. rc = dsi_display_cmd_engine_enable(display);
  6447. if (rc) {
  6448. DSI_ERR("[%s]failed to enable cmd engine,rc=%d",
  6449. display->name, rc);
  6450. goto error_disable_clks;
  6451. }
  6452. dsi_panel_pre_mode_switch_to_cmd(display->panel);
  6453. }
  6454. } else {
  6455. rc = dsi_panel_pre_disable(display->panel);
  6456. if (rc)
  6457. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  6458. display->name, rc);
  6459. }
  6460. goto exit;
  6461. error_disable_clks:
  6462. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6463. DSI_ALL_CLKS, DSI_CLK_OFF);
  6464. if (rc)
  6465. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  6466. display->name, rc);
  6467. exit:
  6468. mutex_unlock(&display->display_lock);
  6469. return rc;
  6470. }
  6471. static void dsi_display_handle_poms_te(struct work_struct *work)
  6472. {
  6473. struct dsi_display *display = NULL;
  6474. struct delayed_work *dw = to_delayed_work(work);
  6475. struct mipi_dsi_device *dsi;
  6476. int rc = 0;
  6477. display = container_of(dw, struct dsi_display, poms_te_work);
  6478. if (!display || !display->panel) {
  6479. DSI_ERR("Invalid params\n");
  6480. return;
  6481. }
  6482. dsi = &display->panel->mipi_device;
  6483. rc = mipi_dsi_dcs_set_tear_off(dsi);
  6484. if (rc < 0)
  6485. DSI_ERR("failed to set tear off\n");
  6486. }
  6487. int dsi_display_disable(struct dsi_display *display)
  6488. {
  6489. int rc = 0;
  6490. if (!display) {
  6491. DSI_ERR("Invalid params\n");
  6492. return -EINVAL;
  6493. }
  6494. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6495. mutex_lock(&display->display_lock);
  6496. /* cancel delayed work */
  6497. if (display->poms_pending &&
  6498. display->panel->poms_align_vsync)
  6499. cancel_delayed_work_sync(&display->poms_te_work);
  6500. rc = dsi_display_wake_up(display);
  6501. if (rc)
  6502. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  6503. display->name, rc);
  6504. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6505. rc = dsi_display_vid_engine_disable(display);
  6506. if (rc)
  6507. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  6508. display->name, rc);
  6509. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6510. /**
  6511. * On POMS request , disable panel TE through
  6512. * delayed work queue.
  6513. */
  6514. if (display->poms_pending &&
  6515. display->panel->poms_align_vsync) {
  6516. INIT_DELAYED_WORK(&display->poms_te_work,
  6517. dsi_display_handle_poms_te);
  6518. queue_delayed_work(system_wq,
  6519. &display->poms_te_work,
  6520. msecs_to_jiffies(100));
  6521. }
  6522. rc = dsi_display_cmd_engine_disable(display);
  6523. if (rc)
  6524. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  6525. display->name, rc);
  6526. } else {
  6527. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6528. rc = -EINVAL;
  6529. }
  6530. if (!display->poms_pending) {
  6531. rc = dsi_panel_disable(display->panel);
  6532. if (rc)
  6533. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  6534. display->name, rc);
  6535. }
  6536. mutex_unlock(&display->display_lock);
  6537. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6538. return rc;
  6539. }
  6540. int dsi_display_update_pps(char *pps_cmd, void *disp)
  6541. {
  6542. struct dsi_display *display;
  6543. if (pps_cmd == NULL || disp == NULL) {
  6544. DSI_ERR("Invalid parameter\n");
  6545. return -EINVAL;
  6546. }
  6547. display = disp;
  6548. mutex_lock(&display->display_lock);
  6549. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  6550. mutex_unlock(&display->display_lock);
  6551. return 0;
  6552. }
  6553. int dsi_display_unprepare(struct dsi_display *display)
  6554. {
  6555. int rc = 0, i;
  6556. struct dsi_display_ctrl *ctrl;
  6557. if (!display) {
  6558. DSI_ERR("Invalid params\n");
  6559. return -EINVAL;
  6560. }
  6561. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6562. mutex_lock(&display->display_lock);
  6563. rc = dsi_display_wake_up(display);
  6564. if (rc)
  6565. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  6566. display->name, rc);
  6567. if (!display->poms_pending) {
  6568. rc = dsi_panel_unprepare(display->panel);
  6569. if (rc)
  6570. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  6571. display->name, rc);
  6572. }
  6573. /* Remove additional vote added for pre_mode_switch_to_cmd */
  6574. if (display->poms_pending &&
  6575. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6576. display_for_each_ctrl(i, display) {
  6577. ctrl = &display->ctrl[i];
  6578. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  6579. continue;
  6580. flush_workqueue(display->dma_cmd_workq);
  6581. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  6582. ctrl->ctrl->dma_wait_queued = false;
  6583. }
  6584. dsi_display_cmd_engine_disable(display);
  6585. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6586. DSI_ALL_CLKS, DSI_CLK_OFF);
  6587. }
  6588. rc = dsi_display_ctrl_host_disable(display);
  6589. if (rc)
  6590. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  6591. display->name, rc);
  6592. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6593. DSI_LINK_CLK, DSI_CLK_OFF);
  6594. if (rc)
  6595. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  6596. display->name, rc);
  6597. rc = dsi_display_ctrl_deinit(display);
  6598. if (rc)
  6599. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  6600. display->name, rc);
  6601. if (!display->panel->ulps_suspend_enabled) {
  6602. rc = dsi_display_phy_disable(display);
  6603. if (rc)
  6604. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  6605. display->name, rc);
  6606. }
  6607. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6608. DSI_CORE_CLK, DSI_CLK_OFF);
  6609. if (rc)
  6610. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  6611. display->name, rc);
  6612. /* destrory dsi isr set up */
  6613. dsi_display_ctrl_isr_configure(display, false);
  6614. if (!display->poms_pending) {
  6615. rc = dsi_panel_post_unprepare(display->panel);
  6616. if (rc)
  6617. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  6618. display->name, rc);
  6619. }
  6620. mutex_unlock(&display->display_lock);
  6621. /* Free up DSI ERROR event callback */
  6622. dsi_display_unregister_error_handler(display);
  6623. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6624. return rc;
  6625. }
  6626. void __init dsi_display_register(void)
  6627. {
  6628. dsi_phy_drv_register();
  6629. dsi_ctrl_drv_register();
  6630. dsi_display_parse_boot_display_selection();
  6631. platform_driver_register(&dsi_display_driver);
  6632. }
  6633. void __exit dsi_display_unregister(void)
  6634. {
  6635. platform_driver_unregister(&dsi_display_driver);
  6636. dsi_ctrl_drv_unregister();
  6637. dsi_phy_drv_unregister();
  6638. }
  6639. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  6640. 0600);
  6641. MODULE_PARM_DESC(dsi_display0,
  6642. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  6643. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  6644. 0600);
  6645. MODULE_PARM_DESC(dsi_display1,
  6646. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");