dsi_display.c 217 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define MAX_TE_RECHECKS 5
  28. #define DSI_CLOCK_BITRATE_RADIX 10
  29. #define MAX_TE_SOURCE_ID 2
  30. #define SEC_PANEL_NAME_MAX_LEN 256
  31. #define DSI_MODE_MATCH_ACTIVE_TIMINGS (1 << 0)
  32. #define DSI_MODE_MATCH_PORCH_TIMINGS (1 << 1)
  33. #define DSI_MODE_MATCH_FULL_TIMINGS (DSI_MODE_MATCH_ACTIVE_TIMINGS | DSI_MODE_MATCH_PORCH_TIMINGS)
  34. u8 dbgfs_tx_cmd_buf[SZ_4K];
  35. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  36. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  37. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  38. {.boot_param = dsi_display_primary},
  39. {.boot_param = dsi_display_secondary},
  40. };
  41. static void dsi_display_panel_id_notification(struct dsi_display *display);
  42. static const struct of_device_id dsi_display_dt_match[] = {
  43. {.compatible = "qcom,dsi-display"},
  44. {}
  45. };
  46. bool is_skip_op_required(struct dsi_display *display)
  47. {
  48. if (!display)
  49. return false;
  50. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  51. }
  52. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  53. u32 mask, bool enable)
  54. {
  55. int i;
  56. struct dsi_display_ctrl *ctrl;
  57. if (!display)
  58. return;
  59. display_for_each_ctrl(i, display) {
  60. ctrl = &display->ctrl[i];
  61. if (!ctrl)
  62. continue;
  63. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  64. }
  65. }
  66. static int dsi_display_config_clk_gating(struct dsi_display *display,
  67. bool enable)
  68. {
  69. int rc = 0, i = 0;
  70. struct dsi_display_ctrl *mctrl, *ctrl;
  71. enum dsi_clk_gate_type clk_selection;
  72. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  73. if (!display) {
  74. DSI_ERR("Invalid params\n");
  75. return -EINVAL;
  76. }
  77. if (display->panel->host_config.force_hs_clk_lane) {
  78. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  79. return 0;
  80. }
  81. mctrl = &display->ctrl[display->clk_master_idx];
  82. if (!mctrl) {
  83. DSI_ERR("Invalid controller\n");
  84. return -EINVAL;
  85. }
  86. clk_selection = display->clk_gating_config;
  87. if (!enable) {
  88. /* for disable path, make sure to disable all clk gating */
  89. clk_selection = DSI_CLK_ALL;
  90. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  91. /* Default selection, no overrides */
  92. clk_selection = default_clk_select;
  93. } else if (clk_selection == DSI_CLK_NONE) {
  94. clk_selection = 0;
  95. }
  96. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  97. enable ? "Enabling" : "Disabling",
  98. clk_selection & BYTE_CLK ? "yes" : "no",
  99. clk_selection & PIXEL_CLK ? "yes" : "no",
  100. clk_selection & DSI_PHY ? "yes" : "no");
  101. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  102. if (rc) {
  103. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  104. display->name, enable ? "enable" : "disable",
  105. clk_selection, rc);
  106. return rc;
  107. }
  108. display_for_each_ctrl(i, display) {
  109. ctrl = &display->ctrl[i];
  110. if (!ctrl->ctrl || (ctrl == mctrl))
  111. continue;
  112. /**
  113. * In Split DSI usecase we should not enable clock gating on
  114. * DSI PHY1 to ensure no display atrifacts are seen.
  115. */
  116. clk_selection &= ~DSI_PHY;
  117. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  118. clk_selection);
  119. if (rc) {
  120. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  121. display->name, enable ? "enable" : "disable",
  122. clk_selection, rc);
  123. return rc;
  124. }
  125. }
  126. return 0;
  127. }
  128. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  129. bool enable)
  130. {
  131. int i;
  132. struct dsi_display_ctrl *ctrl;
  133. if (!display)
  134. return;
  135. display_for_each_ctrl(i, display) {
  136. ctrl = &display->ctrl[i];
  137. if (!ctrl)
  138. continue;
  139. ctrl->ctrl->esd_check_underway = enable;
  140. }
  141. }
  142. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  143. {
  144. int i;
  145. struct dsi_display_ctrl *ctrl;
  146. if (!display)
  147. return;
  148. display_for_each_ctrl(i, display) {
  149. ctrl = &display->ctrl[i];
  150. if (!ctrl)
  151. continue;
  152. dsi_ctrl_irq_update(ctrl->ctrl, en);
  153. }
  154. }
  155. void dsi_rect_intersect(const struct dsi_rect *r1,
  156. const struct dsi_rect *r2,
  157. struct dsi_rect *result)
  158. {
  159. int l, t, r, b;
  160. if (!r1 || !r2 || !result)
  161. return;
  162. l = max(r1->x, r2->x);
  163. t = max(r1->y, r2->y);
  164. r = min((r1->x + r1->w), (r2->x + r2->w));
  165. b = min((r1->y + r1->h), (r2->y + r2->h));
  166. if (r <= l || b <= t) {
  167. memset(result, 0, sizeof(*result));
  168. } else {
  169. result->x = l;
  170. result->y = t;
  171. result->w = r - l;
  172. result->h = b - t;
  173. }
  174. }
  175. int dsi_display_set_backlight(struct drm_connector *connector,
  176. void *display, u32 bl_lvl)
  177. {
  178. struct dsi_display *dsi_display = display;
  179. struct dsi_panel *panel;
  180. u32 bl_scale, bl_scale_sv;
  181. u64 bl_temp;
  182. int rc = 0;
  183. if (dsi_display == NULL || dsi_display->panel == NULL)
  184. return -EINVAL;
  185. panel = dsi_display->panel;
  186. mutex_lock(&panel->panel_lock);
  187. if (!dsi_panel_initialized(panel)) {
  188. rc = -EINVAL;
  189. goto error;
  190. }
  191. panel->bl_config.bl_level = bl_lvl;
  192. /* scale backlight */
  193. bl_scale = panel->bl_config.bl_scale;
  194. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  195. bl_scale_sv = panel->bl_config.bl_scale_sv;
  196. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  197. if (bl_temp > panel->bl_config.bl_max_level)
  198. bl_temp = panel->bl_config.bl_max_level;
  199. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  200. bl_scale, bl_scale_sv, (u32)bl_temp);
  201. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  202. DSI_CORE_CLK, DSI_CLK_ON);
  203. if (rc) {
  204. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  205. dsi_display->name, rc);
  206. goto error;
  207. }
  208. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  209. if (rc)
  210. DSI_ERR("unable to set backlight\n");
  211. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  212. DSI_CORE_CLK, DSI_CLK_OFF);
  213. if (rc) {
  214. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  215. dsi_display->name, rc);
  216. goto error;
  217. }
  218. error:
  219. mutex_unlock(&panel->panel_lock);
  220. return rc;
  221. }
  222. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  223. {
  224. int rc = 0;
  225. int i;
  226. struct dsi_display_ctrl *m_ctrl, *ctrl;
  227. bool skip_op = is_skip_op_required(display);
  228. m_ctrl = &display->ctrl[display->cmd_master_idx];
  229. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  230. if (display->cmd_engine_refcount > 0) {
  231. display->cmd_engine_refcount++;
  232. goto done;
  233. }
  234. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  235. DSI_CTRL_ENGINE_ON, skip_op);
  236. if (rc) {
  237. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  238. display->name, skip_op, rc);
  239. goto done;
  240. }
  241. display_for_each_ctrl(i, display) {
  242. ctrl = &display->ctrl[i];
  243. if (!ctrl->ctrl || (ctrl == m_ctrl))
  244. continue;
  245. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  246. DSI_CTRL_ENGINE_ON, skip_op);
  247. if (rc) {
  248. DSI_ERR(
  249. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  250. display->name, skip_op, rc);
  251. goto error_disable_master;
  252. }
  253. }
  254. display->cmd_engine_refcount++;
  255. goto done;
  256. error_disable_master:
  257. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  258. DSI_CTRL_ENGINE_OFF, skip_op);
  259. done:
  260. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  261. return rc;
  262. }
  263. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  264. {
  265. int rc = 0;
  266. int i;
  267. struct dsi_display_ctrl *m_ctrl, *ctrl;
  268. bool skip_op = is_skip_op_required(display);
  269. m_ctrl = &display->ctrl[display->cmd_master_idx];
  270. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  271. if (display->cmd_engine_refcount == 0) {
  272. DSI_ERR("[%s] Invalid refcount\n", display->name);
  273. goto done;
  274. } else if (display->cmd_engine_refcount > 1) {
  275. display->cmd_engine_refcount--;
  276. goto done;
  277. }
  278. display_for_each_ctrl(i, display) {
  279. ctrl = &display->ctrl[i];
  280. if (!ctrl->ctrl || (ctrl == m_ctrl))
  281. continue;
  282. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  283. DSI_CTRL_ENGINE_OFF, skip_op);
  284. if (rc)
  285. DSI_ERR(
  286. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  287. display->name, skip_op, rc);
  288. }
  289. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  290. DSI_CTRL_ENGINE_OFF, skip_op);
  291. if (rc) {
  292. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  293. display->name, skip_op, rc);
  294. goto error;
  295. }
  296. error:
  297. display->cmd_engine_refcount = 0;
  298. done:
  299. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  300. return rc;
  301. }
  302. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  303. {
  304. struct dsi_display *display;
  305. struct dsi_display_ctrl *display_ctrl;
  306. int rc, cnt;
  307. if (!cb_data) {
  308. DSI_ERR("aspace cb called with invalid cb_data\n");
  309. return;
  310. }
  311. display = (struct dsi_display *)cb_data;
  312. /*
  313. * acquire panel_lock to make sure no commands are in-progress
  314. * while detaching the non-secure context banks
  315. */
  316. dsi_panel_acquire_panel_lock(display->panel);
  317. if (is_detach) {
  318. /* invalidate the stored iova */
  319. display->cmd_buffer_iova = 0;
  320. /* return the virtual address mapping */
  321. msm_gem_put_vaddr(display->tx_cmd_buf);
  322. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  323. } else {
  324. rc = msm_gem_get_iova(display->tx_cmd_buf,
  325. display->aspace, &(display->cmd_buffer_iova));
  326. if (rc) {
  327. DSI_ERR("failed to get the iova rc %d\n", rc);
  328. goto end;
  329. }
  330. display->vaddr =
  331. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  332. if (IS_ERR_OR_NULL(display->vaddr)) {
  333. DSI_ERR("failed to get va rc %d\n", rc);
  334. goto end;
  335. }
  336. }
  337. display_for_each_ctrl(cnt, display) {
  338. display_ctrl = &display->ctrl[cnt];
  339. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  340. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  341. display_ctrl->ctrl->vaddr = display->vaddr;
  342. display_ctrl->ctrl->secure_mode = is_detach;
  343. }
  344. end:
  345. /* release panel_lock */
  346. dsi_panel_release_panel_lock(display->panel);
  347. }
  348. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  349. {
  350. struct dsi_display *display = (struct dsi_display *)data;
  351. /*
  352. * This irq handler is used for sole purpose of identifying
  353. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  354. * in case of display not being initialized yet
  355. */
  356. if (!display)
  357. return IRQ_HANDLED;
  358. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  359. complete_all(&display->esd_te_gate);
  360. return IRQ_HANDLED;
  361. }
  362. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  363. bool enable)
  364. {
  365. if (!display) {
  366. DSI_ERR("Invalid params\n");
  367. return;
  368. }
  369. /* Handle unbalanced irq enable/disable calls */
  370. if (enable && !display->is_te_irq_enabled) {
  371. enable_irq(gpio_to_irq(display->disp_te_gpio));
  372. display->is_te_irq_enabled = true;
  373. } else if (!enable && display->is_te_irq_enabled) {
  374. disable_irq(gpio_to_irq(display->disp_te_gpio));
  375. display->is_te_irq_enabled = false;
  376. }
  377. }
  378. static void dsi_display_register_te_irq(struct dsi_display *display)
  379. {
  380. int rc = 0;
  381. struct platform_device *pdev;
  382. struct device *dev;
  383. unsigned int te_irq;
  384. pdev = display->pdev;
  385. if (!pdev) {
  386. DSI_ERR("invalid platform device\n");
  387. return;
  388. }
  389. dev = &pdev->dev;
  390. if (!dev) {
  391. DSI_ERR("invalid device\n");
  392. return;
  393. }
  394. if (display->trusted_vm_env) {
  395. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  396. return;
  397. }
  398. if (!gpio_is_valid(display->disp_te_gpio)) {
  399. rc = -EINVAL;
  400. goto error;
  401. }
  402. init_completion(&display->esd_te_gate);
  403. te_irq = gpio_to_irq(display->disp_te_gpio);
  404. /* Avoid deferred spurious irqs with disable_irq() */
  405. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  406. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  407. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  408. "TE_GPIO", display);
  409. if (rc) {
  410. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  411. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  412. goto error;
  413. }
  414. disable_irq(te_irq);
  415. display->is_te_irq_enabled = false;
  416. return;
  417. error:
  418. /* disable the TE based ESD check */
  419. DSI_WARN("Unable to register for TE IRQ\n");
  420. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  421. display->panel->esd_config.esd_enabled = false;
  422. }
  423. /* Allocate memory for cmd dma tx buffer */
  424. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  425. {
  426. int rc = 0, cnt = 0;
  427. struct dsi_display_ctrl *display_ctrl;
  428. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  429. SZ_4K,
  430. MSM_BO_UNCACHED);
  431. if ((display->tx_cmd_buf) == NULL) {
  432. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  433. rc = -ENOMEM;
  434. goto error;
  435. }
  436. display->cmd_buffer_size = SZ_4K;
  437. display->aspace = msm_gem_smmu_address_space_get(
  438. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  439. if (PTR_ERR(display->aspace) == -ENODEV) {
  440. display->aspace = NULL;
  441. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  442. } else if (IS_ERR_OR_NULL(display->aspace)) {
  443. rc = PTR_ERR(display->aspace);
  444. display->aspace = NULL;
  445. DSI_ERR("failed to get aspace %d\n", rc);
  446. goto free_gem;
  447. } else if (display->aspace) {
  448. /* register to aspace */
  449. rc = msm_gem_address_space_register_cb(display->aspace,
  450. dsi_display_aspace_cb_locked, (void *)display);
  451. if (rc) {
  452. DSI_ERR("failed to register callback %d\n", rc);
  453. goto free_gem;
  454. }
  455. }
  456. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  457. &(display->cmd_buffer_iova));
  458. if (rc) {
  459. DSI_ERR("failed to get the iova rc %d\n", rc);
  460. goto free_aspace_cb;
  461. }
  462. display->vaddr =
  463. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  464. if (IS_ERR_OR_NULL(display->vaddr)) {
  465. DSI_ERR("failed to get va rc %d\n", rc);
  466. rc = -EINVAL;
  467. goto put_iova;
  468. }
  469. display_for_each_ctrl(cnt, display) {
  470. display_ctrl = &display->ctrl[cnt];
  471. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  472. display_ctrl->ctrl->cmd_buffer_iova =
  473. display->cmd_buffer_iova;
  474. display_ctrl->ctrl->vaddr = display->vaddr;
  475. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  476. }
  477. return rc;
  478. put_iova:
  479. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  480. free_aspace_cb:
  481. msm_gem_address_space_unregister_cb(display->aspace,
  482. dsi_display_aspace_cb_locked, display);
  483. free_gem:
  484. mutex_lock(&display->drm_dev->struct_mutex);
  485. msm_gem_free_object(display->tx_cmd_buf);
  486. mutex_unlock(&display->drm_dev->struct_mutex);
  487. error:
  488. return rc;
  489. }
  490. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  491. {
  492. int i, j = 0;
  493. int len = 0, *lenp;
  494. int group = 0, count = 0;
  495. struct drm_panel_esd_config *config;
  496. if (!panel)
  497. return false;
  498. config = &(panel->esd_config);
  499. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  500. count = config->status_cmd.count;
  501. for (i = 0; i < count; i++)
  502. len += lenp[i];
  503. for (i = 0; i < len; i++)
  504. j += len;
  505. for (j = 0; j < config->groups; ++j) {
  506. for (i = 0; i < len; ++i) {
  507. if (config->return_buf[i] !=
  508. config->status_value[group + i]) {
  509. DRM_ERROR("mismatch: 0x%x\n",
  510. config->return_buf[i]);
  511. break;
  512. }
  513. }
  514. if (i == len)
  515. return true;
  516. group += len;
  517. }
  518. return false;
  519. }
  520. static void dsi_display_parse_demura_data(struct dsi_display *display)
  521. {
  522. int rc = 0;
  523. display->panel_id = ~0x0;
  524. if (display->fw) {
  525. DSI_DEBUG("FW definition unsupported for Demura panel data\n");
  526. return;
  527. }
  528. rc = of_property_read_u64(display->pdev->dev.of_node,
  529. "qcom,demura-panel-id", &display->panel_id);
  530. if (rc) {
  531. DSI_DEBUG("No panel ID is present for this display\n");
  532. } else if (!display->panel_id) {
  533. DSI_DEBUG("Dummy panel ID node present for this display\n");
  534. display->panel_id = ~0x0;
  535. } else {
  536. DSI_DEBUG("panel id found: %lx\n", display->panel_id);
  537. }
  538. }
  539. static void dsi_display_parse_te_data(struct dsi_display *display)
  540. {
  541. struct platform_device *pdev;
  542. struct device *dev;
  543. int rc = 0;
  544. u32 val = 0;
  545. pdev = display->pdev;
  546. if (!pdev) {
  547. DSI_ERR("Invalid platform device\n");
  548. return;
  549. }
  550. dev = &pdev->dev;
  551. if (!dev) {
  552. DSI_ERR("Invalid platform device\n");
  553. return;
  554. }
  555. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  556. "qcom,platform-te-gpio", 0);
  557. if (display->fw)
  558. rc = dsi_parser_read_u32(display->parser_node,
  559. "qcom,panel-te-source", &val);
  560. else
  561. rc = of_property_read_u32(dev->of_node,
  562. "qcom,panel-te-source", &val);
  563. if (rc || (val > MAX_TE_SOURCE_ID)) {
  564. DSI_ERR("invalid vsync source selection\n");
  565. val = 0;
  566. }
  567. display->te_source = val;
  568. }
  569. static void dsi_display_set_cmd_tx_ctrl_flags(struct dsi_display *display,
  570. struct dsi_cmd_desc *cmd)
  571. {
  572. struct dsi_display_ctrl *ctrl, *m_ctrl;
  573. struct mipi_dsi_msg *msg = &cmd->msg;
  574. u32 flags = 0;
  575. int i = 0;
  576. m_ctrl = &display->ctrl[display->clk_master_idx];
  577. display_for_each_ctrl(i, display) {
  578. ctrl = &display->ctrl[i];
  579. if (!ctrl->ctrl)
  580. continue;
  581. /*
  582. * Set cmd transfer mode flags.
  583. * 1) Default selection is CMD fetch from memory.
  584. * 2) In secure session override and use FIFO rather than
  585. * memory.
  586. * 3) If cmd_len is greater than FIFO size non embedded mode of
  587. * tx is used.
  588. */
  589. flags = DSI_CTRL_CMD_FETCH_MEMORY;
  590. if (ctrl->ctrl->secure_mode) {
  591. flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
  592. flags |= DSI_CTRL_CMD_FIFO_STORE;
  593. } else if (msg->tx_len > DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES) {
  594. flags |= DSI_CTRL_CMD_NON_EMBEDDED_MODE;
  595. }
  596. /* Set flags needed for broadcast. Read commands are always unicast */
  597. if (!(msg->flags & MIPI_DSI_MSG_UNICAST_COMMAND) && (display->ctrl_count > 1))
  598. flags |= DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER;
  599. /*
  600. * Set flags for command scheduling.
  601. * 1) In video mode command DMA scheduling is default.
  602. * 2) In command mode command DMA scheduling depends on message
  603. * flag and TE needs to be running.
  604. */
  605. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  606. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  607. } else {
  608. if (msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED)
  609. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  610. if (!display->enabled)
  611. flags &= ~DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  612. }
  613. /* Set flags for last command */
  614. if (!(msg->flags & MIPI_DSI_MSG_BATCH_COMMAND))
  615. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  616. /*
  617. * Set flags for asynchronous wait.
  618. * Asynchronous wait is supported in the following scenarios
  619. * 1) queue_cmd_waits is set by connector and
  620. * - commands are not sent using DSI FIFO memory
  621. * - commands are not sent in non-embedded mode
  622. * - not a video mode panel
  623. * - no explicit msg post_wait_ms is specified
  624. * - not a read command
  625. * 2) if async override msg flag is present
  626. */
  627. if (display->queue_cmd_waits)
  628. if (!(flags & DSI_CTRL_CMD_FIFO_STORE) &&
  629. !(flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) &&
  630. !(display->panel->panel_mode == DSI_OP_VIDEO_MODE) &&
  631. (cmd->post_wait_ms == 0) &&
  632. !(cmd->ctrl_flags & DSI_CTRL_CMD_READ))
  633. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  634. if (msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  635. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  636. }
  637. cmd->ctrl_flags |= flags;
  638. }
  639. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  640. struct dsi_display *display)
  641. {
  642. int i, rc = 0, count = 0, start = 0, *lenp;
  643. struct drm_panel_esd_config *config;
  644. struct dsi_cmd_desc *cmds;
  645. struct dsi_panel *panel;
  646. u32 flags = 0;
  647. if (!display->panel || !ctrl || !ctrl->ctrl)
  648. return -EINVAL;
  649. panel = display->panel;
  650. /*
  651. * When DSI controller is not in initialized state, we do not want to
  652. * report a false ESD failure and hence we defer until next read
  653. * happen.
  654. */
  655. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  656. return 1;
  657. config = &(panel->esd_config);
  658. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  659. count = config->status_cmd.count;
  660. cmds = config->status_cmd.cmds;
  661. flags = DSI_CTRL_CMD_READ;
  662. for (i = 0; i < count; ++i) {
  663. memset(config->status_buf, 0x0, SZ_4K);
  664. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  665. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  666. cmds[i].msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  667. cmds[i].msg.rx_buf = config->status_buf;
  668. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  669. cmds[i].ctrl_flags = flags;
  670. dsi_display_set_cmd_tx_ctrl_flags(display,&cmds[i]);
  671. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i]);
  672. if (rc <= 0) {
  673. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  674. return rc;
  675. }
  676. memcpy(config->return_buf + start,
  677. config->status_buf, lenp[i]);
  678. start += lenp[i];
  679. }
  680. return rc;
  681. }
  682. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  683. struct dsi_display *display)
  684. {
  685. int rc = 0;
  686. rc = dsi_display_read_status(ctrl, display);
  687. if (rc <= 0) {
  688. goto exit;
  689. } else {
  690. /*
  691. * panel status read successfully.
  692. * check for validity of the data read back.
  693. */
  694. rc = dsi_display_validate_reg_read(display->panel);
  695. if (!rc) {
  696. rc = -EINVAL;
  697. goto exit;
  698. }
  699. }
  700. exit:
  701. return rc;
  702. }
  703. static int dsi_display_status_reg_read(struct dsi_display *display)
  704. {
  705. int rc = 0, i;
  706. struct dsi_display_ctrl *m_ctrl, *ctrl;
  707. DSI_DEBUG(" ++\n");
  708. m_ctrl = &display->ctrl[display->cmd_master_idx];
  709. if (display->tx_cmd_buf == NULL) {
  710. rc = dsi_host_alloc_cmd_tx_buffer(display);
  711. if (rc) {
  712. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  713. goto done;
  714. }
  715. }
  716. rc = dsi_display_cmd_engine_enable(display);
  717. if (rc) {
  718. DSI_ERR("cmd engine enable failed\n");
  719. return -EPERM;
  720. }
  721. rc = dsi_display_validate_status(m_ctrl, display);
  722. if (rc <= 0) {
  723. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  724. display->name, rc);
  725. goto exit;
  726. }
  727. if (!display->panel->sync_broadcast_en)
  728. goto exit;
  729. display_for_each_ctrl(i, display) {
  730. ctrl = &display->ctrl[i];
  731. if (ctrl == m_ctrl)
  732. continue;
  733. rc = dsi_display_validate_status(ctrl, display);
  734. if (rc <= 0) {
  735. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  736. display->name, rc);
  737. goto exit;
  738. }
  739. }
  740. exit:
  741. dsi_display_cmd_engine_disable(display);
  742. done:
  743. return rc;
  744. }
  745. static int dsi_display_status_bta_request(struct dsi_display *display)
  746. {
  747. int rc = 0;
  748. DSI_DEBUG(" ++\n");
  749. /* TODO: trigger SW BTA and wait for acknowledgment */
  750. return rc;
  751. }
  752. static void dsi_display_release_te_irq(struct dsi_display *display)
  753. {
  754. int te_irq = 0;
  755. te_irq = gpio_to_irq(display->disp_te_gpio);
  756. if (te_irq)
  757. free_irq(te_irq, display);
  758. }
  759. static int dsi_display_status_check_te(struct dsi_display *display,
  760. int rechecks)
  761. {
  762. int rc = 1, i = 0;
  763. int const esd_te_timeout = msecs_to_jiffies(3*20);
  764. if (!rechecks)
  765. return rc;
  766. /* register te irq handler */
  767. dsi_display_register_te_irq(display);
  768. dsi_display_change_te_irq_status(display, true);
  769. for (i = 0; i < rechecks; i++) {
  770. reinit_completion(&display->esd_te_gate);
  771. if (!wait_for_completion_timeout(&display->esd_te_gate,
  772. esd_te_timeout)) {
  773. DSI_ERR("TE check failed\n");
  774. dsi_display_change_te_irq_status(display, false);
  775. return -EINVAL;
  776. }
  777. }
  778. dsi_display_change_te_irq_status(display, false);
  779. dsi_display_release_te_irq(display);
  780. return rc;
  781. }
  782. int dsi_display_check_status(struct drm_connector *connector, void *display,
  783. bool te_check_override)
  784. {
  785. struct dsi_display *dsi_display = display;
  786. struct dsi_panel *panel;
  787. u32 status_mode;
  788. int rc = 0x1, ret;
  789. u32 mask;
  790. int te_rechecks = 1;
  791. if (!dsi_display || !dsi_display->panel)
  792. return -EINVAL;
  793. panel = dsi_display->panel;
  794. dsi_panel_acquire_panel_lock(panel);
  795. if (!panel->panel_initialized) {
  796. DSI_DEBUG("Panel not initialized\n");
  797. goto release_panel_lock;
  798. }
  799. /* Prevent another ESD check,when ESD recovery is underway */
  800. if (atomic_read(&panel->esd_recovery_pending))
  801. goto release_panel_lock;
  802. status_mode = panel->esd_config.status_mode;
  803. if ((status_mode == ESD_MODE_SW_SIM_SUCCESS) ||
  804. (dsi_display->sw_te_using_wd) ||
  805. (dsi_display->panel->te_using_watchdog_timer))
  806. goto release_panel_lock;
  807. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  808. rc = -EINVAL;
  809. goto release_panel_lock;
  810. }
  811. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
  812. if (te_check_override)
  813. te_rechecks = MAX_TE_RECHECKS;
  814. if ((dsi_display->trusted_vm_env) ||
  815. (panel->panel_mode == DSI_OP_VIDEO_MODE))
  816. te_rechecks = 0;
  817. ret = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  818. DSI_ALL_CLKS, DSI_CLK_ON);
  819. if (ret)
  820. goto release_panel_lock;
  821. /* Mask error interrupts before attempting ESD read */
  822. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  823. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  824. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
  825. if (status_mode == ESD_MODE_REG_READ) {
  826. rc = dsi_display_status_reg_read(dsi_display);
  827. } else if (status_mode == ESD_MODE_SW_BTA) {
  828. rc = dsi_display_status_bta_request(dsi_display);
  829. } else if (status_mode == ESD_MODE_PANEL_TE) {
  830. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  831. te_check_override = false;
  832. } else {
  833. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  834. panel->esd_config.esd_enabled = false;
  835. }
  836. if (rc <= 0 && te_check_override)
  837. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  838. /* Unmask error interrupts if check passed*/
  839. if (rc > 0) {
  840. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  841. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
  842. false);
  843. if (te_check_override && panel->esd_config.esd_enabled == false)
  844. rc = dsi_display_status_check_te(dsi_display,
  845. te_rechecks);
  846. }
  847. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  848. DSI_ALL_CLKS, DSI_CLK_OFF);
  849. /* Handle Panel failures during display disable sequence */
  850. if (rc <=0)
  851. atomic_set(&panel->esd_recovery_pending, 1);
  852. release_panel_lock:
  853. dsi_panel_release_panel_lock(panel);
  854. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
  855. return rc;
  856. }
  857. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  858. bool *state)
  859. {
  860. struct dsi_display_ctrl *ctrl;
  861. int i, rc = -EINVAL;
  862. display_for_each_ctrl(i, dsi_display) {
  863. ctrl = &dsi_display->ctrl[i];
  864. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  865. if (rc)
  866. break;
  867. }
  868. return rc;
  869. }
  870. static int dsi_display_cmd_rx(struct dsi_display *display,
  871. struct dsi_cmd_desc *cmd)
  872. {
  873. struct dsi_display_ctrl *m_ctrl = NULL;
  874. u32 mask = 0, flags = 0;
  875. int rc = 0;
  876. if (!display || !display->panel)
  877. return -EINVAL;
  878. m_ctrl = &display->ctrl[display->cmd_master_idx];
  879. if (!m_ctrl || !m_ctrl->ctrl)
  880. return -EINVAL;
  881. /* acquire panel_lock to make sure no commands are in progress */
  882. dsi_panel_acquire_panel_lock(display->panel);
  883. if (!display->panel->panel_initialized) {
  884. DSI_DEBUG("panel not initialized\n");
  885. goto release_panel_lock;
  886. }
  887. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  888. DSI_ALL_CLKS, DSI_CLK_ON);
  889. if (rc)
  890. goto release_panel_lock;
  891. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  892. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  893. rc = dsi_display_cmd_engine_enable(display);
  894. if (rc) {
  895. DSI_ERR("cmd engine enable failed rc = %d\n", rc);
  896. goto error;
  897. }
  898. flags = DSI_CTRL_CMD_READ;
  899. cmd->ctrl_flags = flags;
  900. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  901. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  902. if (rc <= 0)
  903. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  904. dsi_display_cmd_engine_disable(display);
  905. error:
  906. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  907. dsi_display_clk_ctrl(display->dsi_clk_handle,
  908. DSI_ALL_CLKS, DSI_CLK_OFF);
  909. release_panel_lock:
  910. dsi_panel_release_panel_lock(display->panel);
  911. return rc;
  912. }
  913. int dsi_display_cmd_transfer(struct drm_connector *connector,
  914. void *display, const char *cmd_buf,
  915. u32 cmd_buf_len)
  916. {
  917. struct dsi_display *dsi_display = display;
  918. int rc = 0, cnt = 0, i = 0;
  919. bool state = false, transfer = false;
  920. struct dsi_panel_cmd_set *set;
  921. if (!dsi_display || !cmd_buf) {
  922. DSI_ERR("[DSI] invalid params\n");
  923. return -EINVAL;
  924. }
  925. DSI_DEBUG("[DSI] Display command transfer\n");
  926. if (!(cmd_buf[3] & MIPI_DSI_MSG_BATCH_COMMAND))
  927. transfer = true;
  928. mutex_lock(&dsi_display->display_lock);
  929. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  930. /**
  931. * Handle scenario where a command transfer is initiated through
  932. * sysfs interface when device is in suepnd state.
  933. */
  934. if (!rc && !state) {
  935. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  936. );
  937. rc = -EPERM;
  938. goto end;
  939. }
  940. if (rc || !state) {
  941. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  942. state, rc);
  943. rc = -EPERM;
  944. goto end;
  945. }
  946. /*
  947. * Reset the dbgfs buffer if the commands sent exceed the available
  948. * buffer size. For video mode, limiting the buffer size to 2K to
  949. * ensure no performance issues.
  950. */
  951. if (dsi_display->panel->panel_mode == DSI_OP_CMD_MODE) {
  952. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_4K) {
  953. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  954. dsi_display->tx_cmd_buf_ndx = 0;
  955. }
  956. } else {
  957. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_2K) {
  958. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  959. dsi_display->tx_cmd_buf_ndx = 0;
  960. }
  961. }
  962. memcpy(&dbgfs_tx_cmd_buf[dsi_display->tx_cmd_buf_ndx], cmd_buf,
  963. cmd_buf_len);
  964. dsi_display->tx_cmd_buf_ndx += cmd_buf_len;
  965. if (transfer) {
  966. struct dsi_cmd_desc *cmds;
  967. set = &dsi_display->cmd_set;
  968. set->count = 0;
  969. dsi_panel_get_cmd_pkt_count(dbgfs_tx_cmd_buf,
  970. dsi_display->tx_cmd_buf_ndx, &cnt);
  971. dsi_panel_alloc_cmd_packets(set, cnt);
  972. dsi_panel_create_cmd_packets(dbgfs_tx_cmd_buf,
  973. dsi_display->tx_cmd_buf_ndx, cnt, set->cmds);
  974. cmds = set->cmds;
  975. dsi_display->tx_cmd_buf_ndx = 0;
  976. for (i = 0; i < cnt; i++) {
  977. rc = dsi_host_transfer_sub(&dsi_display->host, cmds);
  978. if (rc < 0) {
  979. DSI_ERR("failed to send command, rc=%d\n", rc);
  980. break;
  981. }
  982. if (cmds->post_wait_ms)
  983. usleep_range(cmds->post_wait_ms*1000,
  984. ((cmds->post_wait_ms*1000)+10));
  985. cmds++;
  986. }
  987. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  988. dsi_panel_destroy_cmd_packets(set);
  989. dsi_panel_dealloc_cmd_packets(set);
  990. }
  991. end:
  992. mutex_unlock(&dsi_display->display_lock);
  993. return rc;
  994. }
  995. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  996. bool enable)
  997. {
  998. int i;
  999. struct dsi_display_ctrl *ctrl;
  1000. if (!display || !display->panel->host_config.force_hs_clk_lane)
  1001. return;
  1002. display_for_each_ctrl(i, display) {
  1003. ctrl = &display->ctrl[i];
  1004. /*
  1005. * For phy ver 4.0 chipsets, configure DSI controller and
  1006. * DSI PHY to force clk lane to HS mode always whereas
  1007. * for other phy ver chipsets, configure DSI controller only.
  1008. */
  1009. if (ctrl->phy->hw.ops.set_continuous_clk) {
  1010. dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
  1011. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  1012. dsi_phy_set_continuous_clk(ctrl->phy, enable);
  1013. } else {
  1014. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  1015. }
  1016. }
  1017. }
  1018. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  1019. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len)
  1020. {
  1021. struct dsi_display *dsi_display = display;
  1022. struct dsi_cmd_desc cmd = {};
  1023. bool state = false;
  1024. int rc = -1;
  1025. if (!dsi_display || !cmd_buf || !recv_buf) {
  1026. DSI_ERR("[DSI] invalid params\n");
  1027. return -EINVAL;
  1028. }
  1029. rc = dsi_panel_create_cmd_packets(cmd_buf, cmd_buf_len, 1, &cmd);
  1030. if (rc) {
  1031. DSI_ERR("[DSI] command packet create failed, rc = %d\n", rc);
  1032. return rc;
  1033. }
  1034. cmd.msg.rx_buf = recv_buf;
  1035. cmd.msg.rx_len = recv_buf_len;
  1036. cmd.msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  1037. mutex_lock(&dsi_display->display_lock);
  1038. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  1039. if (rc || !state) {
  1040. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  1041. state, rc);
  1042. rc = -EPERM;
  1043. goto end;
  1044. }
  1045. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  1046. if (rc <= 0)
  1047. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  1048. end:
  1049. mutex_unlock(&dsi_display->display_lock);
  1050. return rc;
  1051. }
  1052. int dsi_display_soft_reset(void *display)
  1053. {
  1054. struct dsi_display *dsi_display;
  1055. struct dsi_display_ctrl *ctrl;
  1056. int rc = 0;
  1057. int i;
  1058. if (!display)
  1059. return -EINVAL;
  1060. dsi_display = display;
  1061. display_for_each_ctrl(i, dsi_display) {
  1062. ctrl = &dsi_display->ctrl[i];
  1063. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  1064. if (rc) {
  1065. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  1066. dsi_display->name, i, rc);
  1067. break;
  1068. }
  1069. }
  1070. return rc;
  1071. }
  1072. enum dsi_pixel_format dsi_display_get_dst_format(
  1073. struct drm_connector *connector,
  1074. void *display)
  1075. {
  1076. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  1077. struct dsi_display *dsi_display = (struct dsi_display *)display;
  1078. if (!dsi_display || !dsi_display->panel) {
  1079. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  1080. dsi_display,
  1081. ((dsi_display) ? dsi_display->panel : NULL));
  1082. return format;
  1083. }
  1084. format = dsi_display->panel->host_config.dst_format;
  1085. return format;
  1086. }
  1087. static void _dsi_display_setup_misr(struct dsi_display *display)
  1088. {
  1089. int i;
  1090. display_for_each_ctrl(i, display) {
  1091. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  1092. display->misr_enable,
  1093. display->misr_frame_count);
  1094. }
  1095. }
  1096. int dsi_display_set_power(struct drm_connector *connector,
  1097. int power_mode, void *disp)
  1098. {
  1099. struct dsi_display *display = disp;
  1100. int rc = 0;
  1101. if (!display || !display->panel) {
  1102. DSI_ERR("invalid display/panel\n");
  1103. return -EINVAL;
  1104. }
  1105. switch (power_mode) {
  1106. case SDE_MODE_DPMS_LP1:
  1107. rc = dsi_panel_set_lp1(display->panel);
  1108. break;
  1109. case SDE_MODE_DPMS_LP2:
  1110. rc = dsi_panel_set_lp2(display->panel);
  1111. break;
  1112. case SDE_MODE_DPMS_ON:
  1113. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  1114. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  1115. rc = dsi_panel_set_nolp(display->panel);
  1116. break;
  1117. case SDE_MODE_DPMS_OFF:
  1118. default:
  1119. return rc;
  1120. }
  1121. SDE_EVT32(display->panel->power_mode, power_mode, rc);
  1122. DSI_DEBUG("Power mode transition from %d to %d %s",
  1123. display->panel->power_mode, power_mode,
  1124. rc ? "failed" : "successful");
  1125. if (!rc)
  1126. display->panel->power_mode = power_mode;
  1127. return rc;
  1128. }
  1129. #ifdef CONFIG_DEBUG_FS
  1130. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  1131. {
  1132. u32 status_mode = 0;
  1133. if (!display->panel) {
  1134. DSI_ERR("Invalid panel data\n");
  1135. return false;
  1136. }
  1137. status_mode = display->panel->esd_config.status_mode;
  1138. if (status_mode == ESD_MODE_PANEL_TE &&
  1139. gpio_is_valid(display->disp_te_gpio))
  1140. return true;
  1141. return false;
  1142. }
  1143. static ssize_t debugfs_dump_info_read(struct file *file,
  1144. char __user *user_buf,
  1145. size_t user_len,
  1146. loff_t *ppos)
  1147. {
  1148. struct dsi_display *display = file->private_data;
  1149. struct dsi_mode_info *m;
  1150. char *buf;
  1151. u32 len = 0;
  1152. int i;
  1153. if (!display)
  1154. return -ENODEV;
  1155. if (*ppos)
  1156. return 0;
  1157. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1158. if (!buf)
  1159. return -ENOMEM;
  1160. m = &display->config.video_timing;
  1161. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1162. len += snprintf(buf + len, (SZ_4K - len),
  1163. "\tResolution = %d(%d|%d|%d|%d)x%d(%d|%d|%d|%d)@%dfps %llu Hz\n",
  1164. m->h_active, m->h_back_porch, m->h_front_porch, m->h_sync_width,
  1165. m->h_sync_polarity, m->v_active, m->v_back_porch, m->v_front_porch,
  1166. m->v_sync_width, m->v_sync_polarity, m->refresh_rate, m->clk_rate_hz);
  1167. display_for_each_ctrl(i, display) {
  1168. len += snprintf(buf + len, (SZ_4K - len),
  1169. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1170. i, display->ctrl[i].ctrl->name,
  1171. display->ctrl[i].phy->name);
  1172. }
  1173. len += snprintf(buf + len, (SZ_4K - len),
  1174. "\tPanel = %s\n", display->panel->name);
  1175. len += snprintf(buf + len, (SZ_4K - len),
  1176. "\tClock master = %s\n",
  1177. display->ctrl[display->clk_master_idx].ctrl->name);
  1178. if (len > user_len)
  1179. len = user_len;
  1180. if (copy_to_user(user_buf, buf, len)) {
  1181. kfree(buf);
  1182. return -EFAULT;
  1183. }
  1184. *ppos += len;
  1185. kfree(buf);
  1186. return len;
  1187. }
  1188. static ssize_t debugfs_misr_setup(struct file *file,
  1189. const char __user *user_buf,
  1190. size_t user_len,
  1191. loff_t *ppos)
  1192. {
  1193. struct dsi_display *display = file->private_data;
  1194. char *buf;
  1195. int rc = 0;
  1196. size_t len;
  1197. u32 enable, frame_count;
  1198. if (!display)
  1199. return -ENODEV;
  1200. if (*ppos)
  1201. return 0;
  1202. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1203. if (!buf)
  1204. return -ENOMEM;
  1205. /* leave room for termination char */
  1206. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1207. if (copy_from_user(buf, user_buf, len)) {
  1208. rc = -EINVAL;
  1209. goto error;
  1210. }
  1211. buf[len] = '\0'; /* terminate the string */
  1212. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1213. rc = -EINVAL;
  1214. goto error;
  1215. }
  1216. display->misr_enable = enable;
  1217. display->misr_frame_count = frame_count;
  1218. mutex_lock(&display->display_lock);
  1219. if (!display->hw_ownership) {
  1220. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1221. display->name);
  1222. rc = -EOPNOTSUPP;
  1223. goto unlock;
  1224. }
  1225. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1226. DSI_CORE_CLK, DSI_CLK_ON);
  1227. if (rc) {
  1228. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1229. display->name, rc);
  1230. goto unlock;
  1231. }
  1232. _dsi_display_setup_misr(display);
  1233. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1234. DSI_CORE_CLK, DSI_CLK_OFF);
  1235. if (rc) {
  1236. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1237. display->name, rc);
  1238. goto unlock;
  1239. }
  1240. rc = user_len;
  1241. unlock:
  1242. mutex_unlock(&display->display_lock);
  1243. error:
  1244. kfree(buf);
  1245. return rc;
  1246. }
  1247. static ssize_t debugfs_misr_read(struct file *file,
  1248. char __user *user_buf,
  1249. size_t user_len,
  1250. loff_t *ppos)
  1251. {
  1252. struct dsi_display *display = file->private_data;
  1253. char *buf;
  1254. u32 len = 0;
  1255. int rc = 0;
  1256. struct dsi_ctrl *dsi_ctrl;
  1257. int i;
  1258. u32 misr;
  1259. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1260. if (!display)
  1261. return -ENODEV;
  1262. if (*ppos)
  1263. return 0;
  1264. buf = kzalloc(max_len, GFP_KERNEL);
  1265. if (ZERO_OR_NULL_PTR(buf))
  1266. return -ENOMEM;
  1267. mutex_lock(&display->display_lock);
  1268. if (!display->hw_ownership) {
  1269. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1270. display->name);
  1271. rc = -EOPNOTSUPP;
  1272. goto error;
  1273. }
  1274. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1275. DSI_CORE_CLK, DSI_CLK_ON);
  1276. if (rc) {
  1277. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1278. display->name, rc);
  1279. goto error;
  1280. }
  1281. display_for_each_ctrl(i, display) {
  1282. dsi_ctrl = display->ctrl[i].ctrl;
  1283. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1284. len += snprintf((buf + len), max_len - len,
  1285. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1286. if (len >= max_len)
  1287. break;
  1288. }
  1289. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1290. DSI_CORE_CLK, DSI_CLK_OFF);
  1291. if (rc) {
  1292. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1293. display->name, rc);
  1294. goto error;
  1295. }
  1296. if (copy_to_user(user_buf, buf, max_len)) {
  1297. rc = -EFAULT;
  1298. goto error;
  1299. }
  1300. *ppos += len;
  1301. error:
  1302. mutex_unlock(&display->display_lock);
  1303. kfree(buf);
  1304. return len;
  1305. }
  1306. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1307. const char __user *user_buf,
  1308. size_t user_len,
  1309. loff_t *ppos)
  1310. {
  1311. struct dsi_display *display = file->private_data;
  1312. char *buf;
  1313. int rc = 0;
  1314. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1315. u32 esd_trigger;
  1316. size_t len;
  1317. if (!display)
  1318. return -ENODEV;
  1319. if (*ppos)
  1320. return 0;
  1321. if (user_len > sizeof(u32))
  1322. return -EINVAL;
  1323. if (!user_len || !user_buf)
  1324. return -EINVAL;
  1325. if (!display->panel ||
  1326. atomic_read(&display->panel->esd_recovery_pending))
  1327. return user_len;
  1328. if (!esd_config->esd_enabled) {
  1329. DSI_ERR("ESD feature is not enabled\n");
  1330. return -EINVAL;
  1331. }
  1332. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1333. if (!buf)
  1334. return -ENOMEM;
  1335. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1336. if (copy_from_user(buf, user_buf, len)) {
  1337. rc = -EINVAL;
  1338. goto error;
  1339. }
  1340. buf[len] = '\0'; /* terminate the string */
  1341. if (kstrtouint(buf, 10, &esd_trigger)) {
  1342. rc = -EINVAL;
  1343. goto error;
  1344. }
  1345. if (esd_trigger != 1) {
  1346. rc = -EINVAL;
  1347. goto error;
  1348. }
  1349. display->esd_trigger = esd_trigger;
  1350. mutex_lock(&display->display_lock);
  1351. if (!display->hw_ownership) {
  1352. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1353. display->name);
  1354. rc = -EOPNOTSUPP;
  1355. goto unlock;
  1356. }
  1357. if (display->esd_trigger) {
  1358. DSI_INFO("ESD attack triggered by user\n");
  1359. rc = dsi_panel_trigger_esd_attack(display->panel,
  1360. display->trusted_vm_env);
  1361. if (rc) {
  1362. DSI_ERR("Failed to trigger ESD attack\n");
  1363. goto error;
  1364. }
  1365. }
  1366. rc = len;
  1367. unlock:
  1368. mutex_unlock(&display->display_lock);
  1369. error:
  1370. kfree(buf);
  1371. return rc;
  1372. }
  1373. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1374. const char __user *user_buf,
  1375. size_t user_len,
  1376. loff_t *ppos)
  1377. {
  1378. struct dsi_display *display = file->private_data;
  1379. struct drm_panel_esd_config *esd_config;
  1380. char *buf;
  1381. int rc = 0;
  1382. size_t len;
  1383. if (!display)
  1384. return -ENODEV;
  1385. if (*ppos)
  1386. return 0;
  1387. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1388. if (ZERO_OR_NULL_PTR(buf))
  1389. return -ENOMEM;
  1390. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1391. if (copy_from_user(buf, user_buf, len)) {
  1392. rc = -EINVAL;
  1393. goto error;
  1394. }
  1395. buf[len] = '\0'; /* terminate the string */
  1396. if (!display->panel) {
  1397. rc = -EINVAL;
  1398. goto error;
  1399. }
  1400. esd_config = &display->panel->esd_config;
  1401. if (!esd_config) {
  1402. DSI_ERR("Invalid panel esd config\n");
  1403. rc = -EINVAL;
  1404. goto error;
  1405. }
  1406. if (!esd_config->esd_enabled) {
  1407. rc = -EINVAL;
  1408. goto error;
  1409. }
  1410. if (!strcmp(buf, "te_signal_check\n")) {
  1411. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1412. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1413. rc = -EINVAL;
  1414. goto error;
  1415. }
  1416. DSI_INFO("ESD check is switched to TE mode by user\n");
  1417. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1418. dsi_display_change_te_irq_status(display, true);
  1419. }
  1420. if (!strcmp(buf, "reg_read\n")) {
  1421. DSI_INFO("ESD check is switched to reg read by user\n");
  1422. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1423. if (rc) {
  1424. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1425. rc);
  1426. rc = user_len;
  1427. goto error;
  1428. }
  1429. esd_config->status_mode = ESD_MODE_REG_READ;
  1430. if (dsi_display_is_te_based_esd(display))
  1431. dsi_display_change_te_irq_status(display, false);
  1432. }
  1433. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1434. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1435. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1436. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1437. rc = len;
  1438. error:
  1439. kfree(buf);
  1440. return rc;
  1441. }
  1442. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1443. char __user *user_buf,
  1444. size_t user_len,
  1445. loff_t *ppos)
  1446. {
  1447. struct dsi_display *display = file->private_data;
  1448. struct drm_panel_esd_config *esd_config;
  1449. char *buf;
  1450. int rc = 0;
  1451. size_t len = 0;
  1452. if (!display)
  1453. return -ENODEV;
  1454. if (*ppos)
  1455. return 0;
  1456. if (!display->panel) {
  1457. DSI_ERR("invalid panel data\n");
  1458. return -EINVAL;
  1459. }
  1460. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1461. if (ZERO_OR_NULL_PTR(buf))
  1462. return -ENOMEM;
  1463. esd_config = &display->panel->esd_config;
  1464. if (!esd_config) {
  1465. DSI_ERR("Invalid panel esd config\n");
  1466. rc = -EINVAL;
  1467. goto error;
  1468. }
  1469. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1470. if (!esd_config->esd_enabled) {
  1471. rc = snprintf(buf, len, "ESD feature not enabled");
  1472. goto output_mode;
  1473. }
  1474. switch (esd_config->status_mode) {
  1475. case ESD_MODE_REG_READ:
  1476. rc = snprintf(buf, len, "reg_read");
  1477. break;
  1478. case ESD_MODE_PANEL_TE:
  1479. rc = snprintf(buf, len, "te_signal_check");
  1480. break;
  1481. case ESD_MODE_SW_SIM_FAILURE:
  1482. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1483. break;
  1484. case ESD_MODE_SW_SIM_SUCCESS:
  1485. rc = snprintf(buf, len, "esd_sw_sim_success");
  1486. break;
  1487. default:
  1488. rc = snprintf(buf, len, "invalid");
  1489. break;
  1490. }
  1491. output_mode:
  1492. if (!rc) {
  1493. rc = -EINVAL;
  1494. goto error;
  1495. }
  1496. if (copy_to_user(user_buf, buf, len)) {
  1497. rc = -EFAULT;
  1498. goto error;
  1499. }
  1500. *ppos += len;
  1501. error:
  1502. kfree(buf);
  1503. return len;
  1504. }
  1505. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1506. const char __user *user_buf,
  1507. size_t user_len,
  1508. loff_t *ppos)
  1509. {
  1510. struct dsi_display *display = file->private_data;
  1511. struct dsi_display_ctrl *display_ctrl;
  1512. char *buf;
  1513. int rc = 0;
  1514. u32 line = 0, window = 0;
  1515. size_t len;
  1516. int i;
  1517. if (!display)
  1518. return -ENODEV;
  1519. if (*ppos)
  1520. return 0;
  1521. buf = kzalloc(256, GFP_KERNEL);
  1522. if (ZERO_OR_NULL_PTR(buf))
  1523. return -ENOMEM;
  1524. len = min_t(size_t, user_len, 255);
  1525. if (copy_from_user(buf, user_buf, len)) {
  1526. rc = -EINVAL;
  1527. goto error;
  1528. }
  1529. buf[len] = '\0'; /* terminate the string */
  1530. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1531. return -EFAULT;
  1532. display_for_each_ctrl(i, display) {
  1533. struct dsi_ctrl *ctrl;
  1534. display_ctrl = &display->ctrl[i];
  1535. if (!display_ctrl->ctrl)
  1536. continue;
  1537. ctrl = display_ctrl->ctrl;
  1538. ctrl->host_config.common_config.dma_sched_line = line;
  1539. ctrl->host_config.common_config.dma_sched_window = window;
  1540. }
  1541. rc = len;
  1542. error:
  1543. kfree(buf);
  1544. return rc;
  1545. }
  1546. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1547. char __user *user_buf,
  1548. size_t user_len,
  1549. loff_t *ppos)
  1550. {
  1551. struct dsi_display *display = file->private_data;
  1552. struct dsi_display_ctrl *m_ctrl;
  1553. struct dsi_ctrl *ctrl;
  1554. char *buf;
  1555. u32 len = 0;
  1556. int rc = 0;
  1557. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1558. if (!display)
  1559. return -ENODEV;
  1560. if (*ppos)
  1561. return 0;
  1562. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1563. ctrl = m_ctrl->ctrl;
  1564. buf = kzalloc(max_len, GFP_KERNEL);
  1565. if (ZERO_OR_NULL_PTR(buf))
  1566. return -ENOMEM;
  1567. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1568. ctrl->host_config.common_config.dma_sched_line);
  1569. len += scnprintf((buf + len), max_len - len,
  1570. "Schedule command window width: %d\n",
  1571. ctrl->host_config.common_config.dma_sched_window);
  1572. if (len > max_len)
  1573. len = max_len;
  1574. if (copy_to_user(user_buf, buf, len)) {
  1575. rc = -EFAULT;
  1576. goto error;
  1577. }
  1578. *ppos += len;
  1579. error:
  1580. kfree(buf);
  1581. return len;
  1582. }
  1583. static const struct file_operations dump_info_fops = {
  1584. .open = simple_open,
  1585. .read = debugfs_dump_info_read,
  1586. };
  1587. static const struct file_operations misr_data_fops = {
  1588. .open = simple_open,
  1589. .read = debugfs_misr_read,
  1590. .write = debugfs_misr_setup,
  1591. };
  1592. static const struct file_operations esd_trigger_fops = {
  1593. .open = simple_open,
  1594. .write = debugfs_esd_trigger_check,
  1595. };
  1596. static const struct file_operations esd_check_mode_fops = {
  1597. .open = simple_open,
  1598. .write = debugfs_alter_esd_check_mode,
  1599. .read = debugfs_read_esd_check_mode,
  1600. };
  1601. static const struct file_operations dsi_command_scheduling_fops = {
  1602. .open = simple_open,
  1603. .write = debugfs_update_cmd_scheduling_params,
  1604. .read = debugfs_read_cmd_scheduling_params,
  1605. };
  1606. static int dsi_display_debugfs_init(struct dsi_display *display)
  1607. {
  1608. int rc = 0;
  1609. struct dentry *dir, *dump_file, *misr_data;
  1610. char name[MAX_NAME_SIZE];
  1611. char panel_name[SEC_PANEL_NAME_MAX_LEN];
  1612. char secondary_panel_str[] = "_secondary";
  1613. int i;
  1614. strlcpy(panel_name, display->name, SEC_PANEL_NAME_MAX_LEN);
  1615. if (strcmp(display->display_type, "secondary") == 0)
  1616. strlcat(panel_name, secondary_panel_str, SEC_PANEL_NAME_MAX_LEN);
  1617. dir = debugfs_create_dir(panel_name, NULL);
  1618. if (IS_ERR_OR_NULL(dir)) {
  1619. rc = PTR_ERR(dir);
  1620. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1621. display->name, rc);
  1622. goto error;
  1623. }
  1624. dump_file = debugfs_create_file("dump_info",
  1625. 0400,
  1626. dir,
  1627. display,
  1628. &dump_info_fops);
  1629. if (IS_ERR_OR_NULL(dump_file)) {
  1630. rc = PTR_ERR(dump_file);
  1631. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1632. display->name, rc);
  1633. goto error_remove_dir;
  1634. }
  1635. dump_file = debugfs_create_file("esd_trigger",
  1636. 0644,
  1637. dir,
  1638. display,
  1639. &esd_trigger_fops);
  1640. if (IS_ERR_OR_NULL(dump_file)) {
  1641. rc = PTR_ERR(dump_file);
  1642. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1643. display->name, rc);
  1644. goto error_remove_dir;
  1645. }
  1646. dump_file = debugfs_create_file("esd_check_mode",
  1647. 0644,
  1648. dir,
  1649. display,
  1650. &esd_check_mode_fops);
  1651. if (IS_ERR_OR_NULL(dump_file)) {
  1652. rc = PTR_ERR(dump_file);
  1653. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1654. display->name, rc);
  1655. goto error_remove_dir;
  1656. }
  1657. dump_file = debugfs_create_file("cmd_sched_params",
  1658. 0644,
  1659. dir,
  1660. display,
  1661. &dsi_command_scheduling_fops);
  1662. if (IS_ERR_OR_NULL(dump_file)) {
  1663. rc = PTR_ERR(dump_file);
  1664. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1665. display->name, rc);
  1666. goto error_remove_dir;
  1667. }
  1668. misr_data = debugfs_create_file("misr_data",
  1669. 0600,
  1670. dir,
  1671. display,
  1672. &misr_data_fops);
  1673. if (IS_ERR_OR_NULL(misr_data)) {
  1674. rc = PTR_ERR(misr_data);
  1675. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1676. display->name, rc);
  1677. goto error_remove_dir;
  1678. }
  1679. display_for_each_ctrl(i, display) {
  1680. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1681. if (!phy || !phy->name)
  1682. continue;
  1683. snprintf(name, ARRAY_SIZE(name),
  1684. "%s_allow_phy_power_off", phy->name);
  1685. dump_file = debugfs_create_bool(name, 0600, dir,
  1686. &phy->allow_phy_power_off);
  1687. if (IS_ERR_OR_NULL(dump_file)) {
  1688. rc = PTR_ERR(dump_file);
  1689. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1690. display->name, name, rc);
  1691. goto error_remove_dir;
  1692. }
  1693. snprintf(name, ARRAY_SIZE(name),
  1694. "%s_regulator_min_datarate_bps", phy->name);
  1695. debugfs_create_u32(name, 0600, dir, &phy->regulator_min_datarate_bps);
  1696. }
  1697. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1698. &display->panel->ulps_feature_enabled)) {
  1699. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1700. display->name);
  1701. goto error_remove_dir;
  1702. }
  1703. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1704. &display->panel->ulps_suspend_enabled)) {
  1705. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1706. display->name);
  1707. goto error_remove_dir;
  1708. }
  1709. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1710. &display->ulps_enabled)) {
  1711. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1712. display->name);
  1713. goto error_remove_dir;
  1714. }
  1715. debugfs_create_u32("clk_gating_config", 0600, dir, &display->clk_gating_config);
  1716. display->root = dir;
  1717. dsi_parser_dbg_init(display->parser, dir);
  1718. return rc;
  1719. error_remove_dir:
  1720. debugfs_remove(dir);
  1721. error:
  1722. return rc;
  1723. }
  1724. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1725. {
  1726. debugfs_remove_recursive(display->root);
  1727. return 0;
  1728. }
  1729. #else
  1730. static int dsi_display_debugfs_init(struct dsi_display *display)
  1731. {
  1732. return 0;
  1733. }
  1734. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1735. {
  1736. return 0;
  1737. }
  1738. #endif /* CONFIG_DEBUG_FS */
  1739. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1740. struct dsi_display_mode *mode)
  1741. {
  1742. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1743. bool is_split_link = host->split_link.enabled;
  1744. u32 sublinks_count = host->split_link.num_sublinks;
  1745. if (is_split_link && sublinks_count > 1) {
  1746. mode->timing.h_active /= sublinks_count;
  1747. mode->timing.h_front_porch /= sublinks_count;
  1748. mode->timing.h_sync_width /= sublinks_count;
  1749. mode->timing.h_back_porch /= sublinks_count;
  1750. mode->timing.h_skew /= sublinks_count;
  1751. mode->pixel_clk_khz /= sublinks_count;
  1752. } else {
  1753. if (mode->priv_info->dsc_enabled)
  1754. mode->priv_info->dsc.config.pic_width =
  1755. mode->timing.h_active;
  1756. mode->timing.h_active /= display->ctrl_count;
  1757. mode->timing.h_front_porch /= display->ctrl_count;
  1758. mode->timing.h_sync_width /= display->ctrl_count;
  1759. mode->timing.h_back_porch /= display->ctrl_count;
  1760. mode->timing.h_skew /= display->ctrl_count;
  1761. mode->pixel_clk_khz /= display->ctrl_count;
  1762. }
  1763. }
  1764. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1765. bool enable)
  1766. {
  1767. /* TODO: make checks based on cont. splash */
  1768. DSI_DEBUG("checking ulps req validity\n");
  1769. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1770. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1771. return false;
  1772. }
  1773. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1774. !display->panel->ulps_suspend_enabled) {
  1775. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1776. return false;
  1777. }
  1778. if (!dsi_panel_initialized(display->panel) &&
  1779. !display->panel->ulps_suspend_enabled) {
  1780. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1781. return false;
  1782. }
  1783. if (enable && display->ulps_enabled) {
  1784. DSI_DEBUG("ULPS already enabled\n");
  1785. return false;
  1786. } else if (!enable && !display->ulps_enabled) {
  1787. DSI_DEBUG("ULPS already disabled\n");
  1788. return false;
  1789. }
  1790. /*
  1791. * No need to enter ULPS when transitioning from splash screen to
  1792. * boot animation or trusted vm environments since it is expected
  1793. * that the clocks would be turned right back on.
  1794. */
  1795. if (enable && is_skip_op_required(display))
  1796. return false;
  1797. return true;
  1798. }
  1799. /**
  1800. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1801. * @dsi_display: DSI display handle.
  1802. * @enable: enable/disable ULPS.
  1803. *
  1804. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1805. *
  1806. * Return: error code.
  1807. */
  1808. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1809. {
  1810. int rc = 0;
  1811. int i = 0;
  1812. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1813. if (!display) {
  1814. DSI_ERR("Invalid params\n");
  1815. return -EINVAL;
  1816. }
  1817. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1818. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1819. __func__, enable);
  1820. return 0;
  1821. }
  1822. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1823. /*
  1824. * ULPS entry-exit can be either through the DSI controller or
  1825. * the DSI PHY depending on hardware variation. For some chipsets,
  1826. * both controller version and phy version ulps entry-exit ops can
  1827. * be present. To handle such cases, send ulps request through PHY,
  1828. * if ulps request is handled in PHY, then no need to send request
  1829. * through controller.
  1830. */
  1831. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1832. display->clamp_enabled);
  1833. if (rc == DSI_PHY_ULPS_ERROR) {
  1834. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1835. return -EINVAL;
  1836. }
  1837. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1838. display_for_each_ctrl(i, display) {
  1839. ctrl = &display->ctrl[i];
  1840. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1841. continue;
  1842. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1843. enable, display->clamp_enabled);
  1844. if (rc == DSI_PHY_ULPS_ERROR) {
  1845. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1846. enable);
  1847. return -EINVAL;
  1848. }
  1849. }
  1850. }
  1851. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1852. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1853. if (rc) {
  1854. DSI_ERR("Ulps controller state change(%d) failed\n",
  1855. enable);
  1856. return rc;
  1857. }
  1858. display_for_each_ctrl(i, display) {
  1859. ctrl = &display->ctrl[i];
  1860. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1861. continue;
  1862. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1863. if (rc) {
  1864. DSI_ERR("Ulps controller state change(%d) failed\n",
  1865. enable);
  1866. return rc;
  1867. }
  1868. }
  1869. }
  1870. display->ulps_enabled = enable;
  1871. return 0;
  1872. }
  1873. /**
  1874. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1875. * @dsi_display: DSI display handle.
  1876. * @enable: enable/disable clamping.
  1877. *
  1878. * Return: error code.
  1879. */
  1880. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1881. {
  1882. int rc = 0;
  1883. int i = 0;
  1884. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1885. bool ulps_enabled = false;
  1886. if (!display) {
  1887. DSI_ERR("Invalid params\n");
  1888. return -EINVAL;
  1889. }
  1890. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1891. ulps_enabled = display->ulps_enabled;
  1892. /*
  1893. * Clamp control can be either through the DSI controller or
  1894. * the DSI PHY depending on hardware variation
  1895. */
  1896. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1897. if (rc) {
  1898. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1899. return rc;
  1900. }
  1901. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1902. if (rc) {
  1903. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1904. return rc;
  1905. }
  1906. display_for_each_ctrl(i, display) {
  1907. ctrl = &display->ctrl[i];
  1908. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1909. continue;
  1910. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1911. if (rc) {
  1912. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1913. return rc;
  1914. }
  1915. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1916. if (rc) {
  1917. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1918. enable);
  1919. return rc;
  1920. }
  1921. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1922. enable ? "enabled" : "disabled", i);
  1923. }
  1924. display->clamp_enabled = enable;
  1925. return 0;
  1926. }
  1927. /**
  1928. * dsi_display_setup_ctrl() - setup DSI controller.
  1929. * @dsi_display: DSI display handle.
  1930. *
  1931. * Return: error code.
  1932. */
  1933. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1934. {
  1935. int rc = 0;
  1936. int i = 0;
  1937. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1938. if (!display) {
  1939. DSI_ERR("Invalid params\n");
  1940. return -EINVAL;
  1941. }
  1942. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1943. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1944. if (rc) {
  1945. DSI_ERR("DSI controller setup failed\n");
  1946. return rc;
  1947. }
  1948. display_for_each_ctrl(i, display) {
  1949. ctrl = &display->ctrl[i];
  1950. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1951. continue;
  1952. rc = dsi_ctrl_setup(ctrl->ctrl);
  1953. if (rc) {
  1954. DSI_ERR("DSI controller setup failed\n");
  1955. return rc;
  1956. }
  1957. }
  1958. return 0;
  1959. }
  1960. static int dsi_display_phy_enable(struct dsi_display *display);
  1961. /**
  1962. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1963. * @dsi_display: DSI display handle.
  1964. * @mmss_clamp: True if clamp is enabled.
  1965. *
  1966. * Return: error code.
  1967. */
  1968. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1969. bool mmss_clamp)
  1970. {
  1971. int rc = 0;
  1972. int i = 0;
  1973. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1974. if (!display) {
  1975. DSI_ERR("Invalid params\n");
  1976. return -EINVAL;
  1977. }
  1978. if (mmss_clamp && !display->phy_idle_power_off) {
  1979. dsi_display_phy_enable(display);
  1980. return 0;
  1981. }
  1982. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1983. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1984. if (rc) {
  1985. DSI_ERR("DSI controller setup failed\n");
  1986. return rc;
  1987. }
  1988. display_for_each_ctrl(i, display) {
  1989. ctrl = &display->ctrl[i];
  1990. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1991. continue;
  1992. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1993. if (rc) {
  1994. DSI_ERR("DSI controller setup failed\n");
  1995. return rc;
  1996. }
  1997. }
  1998. display->phy_idle_power_off = false;
  1999. return 0;
  2000. }
  2001. /**
  2002. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  2003. * @dsi_display: DSI display handle.
  2004. *
  2005. * Return: error code.
  2006. */
  2007. static int dsi_display_phy_idle_off(struct dsi_display *display)
  2008. {
  2009. int rc = 0;
  2010. int i = 0;
  2011. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2012. if (!display) {
  2013. DSI_ERR("Invalid params\n");
  2014. return -EINVAL;
  2015. }
  2016. display_for_each_ctrl(i, display) {
  2017. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  2018. if (!phy)
  2019. continue;
  2020. if (!phy->allow_phy_power_off) {
  2021. DSI_DEBUG("phy doesn't support this feature\n");
  2022. return 0;
  2023. }
  2024. }
  2025. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2026. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  2027. if (rc) {
  2028. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2029. display->name, rc);
  2030. return rc;
  2031. }
  2032. display_for_each_ctrl(i, display) {
  2033. ctrl = &display->ctrl[i];
  2034. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2035. continue;
  2036. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  2037. if (rc) {
  2038. DSI_ERR("DSI controller setup failed\n");
  2039. return rc;
  2040. }
  2041. }
  2042. display->phy_idle_power_off = true;
  2043. return 0;
  2044. }
  2045. void dsi_display_enable_event(struct drm_connector *connector,
  2046. struct dsi_display *display,
  2047. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  2048. bool enable)
  2049. {
  2050. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  2051. int i;
  2052. if (!display) {
  2053. DSI_ERR("invalid display\n");
  2054. return;
  2055. }
  2056. if (event_info)
  2057. event_info->event_idx = event_idx;
  2058. switch (event_idx) {
  2059. case SDE_CONN_EVENT_VID_DONE:
  2060. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  2061. break;
  2062. case SDE_CONN_EVENT_CMD_DONE:
  2063. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  2064. break;
  2065. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  2066. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  2067. if (event_info) {
  2068. display_for_each_ctrl(i, display)
  2069. display->ctrl[i].ctrl->recovery_cb =
  2070. *event_info;
  2071. }
  2072. break;
  2073. case SDE_CONN_EVENT_PANEL_ID:
  2074. if (event_info)
  2075. display_for_each_ctrl(i, display)
  2076. display->ctrl[i].ctrl->panel_id_cb
  2077. = *event_info;
  2078. dsi_display_panel_id_notification(display);
  2079. break;
  2080. default:
  2081. /* nothing to do */
  2082. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  2083. return;
  2084. }
  2085. if (enable) {
  2086. display_for_each_ctrl(i, display)
  2087. dsi_ctrl_enable_status_interrupt(
  2088. display->ctrl[i].ctrl, irq_status_idx,
  2089. event_info);
  2090. } else {
  2091. display_for_each_ctrl(i, display)
  2092. dsi_ctrl_disable_status_interrupt(
  2093. display->ctrl[i].ctrl, irq_status_idx);
  2094. }
  2095. }
  2096. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  2097. {
  2098. int rc = 0;
  2099. int i;
  2100. struct dsi_display_ctrl *ctrl;
  2101. /* Sequence does not matter for split dsi usecases */
  2102. display_for_each_ctrl(i, display) {
  2103. ctrl = &display->ctrl[i];
  2104. if (!ctrl->ctrl)
  2105. continue;
  2106. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2107. DSI_CTRL_POWER_VREG_ON);
  2108. if (rc) {
  2109. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2110. ctrl->ctrl->name, rc);
  2111. goto error;
  2112. }
  2113. }
  2114. return rc;
  2115. error:
  2116. for (i = i - 1; i >= 0; i--) {
  2117. ctrl = &display->ctrl[i];
  2118. if (!ctrl->ctrl)
  2119. continue;
  2120. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  2121. DSI_CTRL_POWER_VREG_OFF);
  2122. }
  2123. return rc;
  2124. }
  2125. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  2126. {
  2127. int rc = 0;
  2128. int i;
  2129. struct dsi_display_ctrl *ctrl;
  2130. /* Sequence does not matter for split dsi usecases */
  2131. display_for_each_ctrl(i, display) {
  2132. ctrl = &display->ctrl[i];
  2133. if (!ctrl->ctrl)
  2134. continue;
  2135. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2136. DSI_CTRL_POWER_VREG_OFF);
  2137. if (rc) {
  2138. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2139. ctrl->ctrl->name, rc);
  2140. goto error;
  2141. }
  2142. }
  2143. error:
  2144. return rc;
  2145. }
  2146. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  2147. unsigned int display_type)
  2148. {
  2149. char *boot_str = NULL;
  2150. char *str = NULL;
  2151. char *sw_te = NULL;
  2152. unsigned long cmdline_topology = NO_OVERRIDE;
  2153. unsigned long cmdline_timing = NO_OVERRIDE;
  2154. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2155. DSI_ERR("display_type=%d not supported\n", display_type);
  2156. goto end;
  2157. }
  2158. if (display_type == DSI_PRIMARY)
  2159. boot_str = dsi_display_primary;
  2160. else
  2161. boot_str = dsi_display_secondary;
  2162. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2163. if (sw_te)
  2164. display->sw_te_using_wd = true;
  2165. str = strnstr(boot_str, ":config", strlen(boot_str));
  2166. if (str) {
  2167. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2168. DSI_ERR("invalid config index override: %s\n",
  2169. boot_str);
  2170. goto end;
  2171. }
  2172. }
  2173. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2174. if (str) {
  2175. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2176. DSI_ERR("invalid timing index override: %s\n",
  2177. boot_str);
  2178. cmdline_topology = NO_OVERRIDE;
  2179. goto end;
  2180. }
  2181. }
  2182. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2183. end:
  2184. display->cmdline_topology = cmdline_topology;
  2185. display->cmdline_timing = cmdline_timing;
  2186. }
  2187. /**
  2188. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2189. *
  2190. * Return: returns error status
  2191. */
  2192. static int dsi_display_parse_boot_display_selection(void)
  2193. {
  2194. char *pos = NULL;
  2195. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2196. int i, j;
  2197. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2198. strlcpy(disp_buf, boot_displays[i].boot_param,
  2199. MAX_CMDLINE_PARAM_LEN);
  2200. pos = strnstr(disp_buf, ":", strlen(disp_buf));
  2201. /* Use ':' as a delimiter to retrieve the display name */
  2202. if (!pos) {
  2203. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2204. continue;
  2205. }
  2206. for (j = 0; (disp_buf + j) < pos; j++)
  2207. boot_displays[i].name[j] = *(disp_buf + j);
  2208. boot_displays[i].name[j] = '\0';
  2209. boot_displays[i].boot_disp_en = true;
  2210. }
  2211. return 0;
  2212. }
  2213. static int dsi_display_phy_power_on(struct dsi_display *display)
  2214. {
  2215. int rc = 0;
  2216. int i;
  2217. struct dsi_display_ctrl *ctrl;
  2218. /* Sequence does not matter for split dsi usecases */
  2219. display_for_each_ctrl(i, display) {
  2220. ctrl = &display->ctrl[i];
  2221. if (!ctrl->ctrl)
  2222. continue;
  2223. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2224. if (rc) {
  2225. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2226. ctrl->phy->name, rc);
  2227. goto error;
  2228. }
  2229. }
  2230. return rc;
  2231. error:
  2232. for (i = i - 1; i >= 0; i--) {
  2233. ctrl = &display->ctrl[i];
  2234. if (!ctrl->phy)
  2235. continue;
  2236. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2237. }
  2238. return rc;
  2239. }
  2240. static int dsi_display_phy_power_off(struct dsi_display *display)
  2241. {
  2242. int rc = 0;
  2243. int i;
  2244. struct dsi_display_ctrl *ctrl;
  2245. /* Sequence does not matter for split dsi usecases */
  2246. display_for_each_ctrl(i, display) {
  2247. ctrl = &display->ctrl[i];
  2248. if (!ctrl->phy)
  2249. continue;
  2250. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2251. if (rc) {
  2252. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2253. ctrl->ctrl->name, rc);
  2254. goto error;
  2255. }
  2256. }
  2257. error:
  2258. return rc;
  2259. }
  2260. static int dsi_display_set_clk_src(struct dsi_display *display, bool set_xo)
  2261. {
  2262. int rc = 0;
  2263. int i;
  2264. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2265. struct dsi_ctrl_clk_info *info;
  2266. if (display->trusted_vm_env)
  2267. return 0;
  2268. /*
  2269. * In case of split DSI usecases, the clock for master controller should
  2270. * be enabled before the other controller. Master controller in the
  2271. * clock context refers to the controller that sources the clock. While turning off the
  2272. * clocks, the source is set to xo.
  2273. */
  2274. m_ctrl = &display->ctrl[display->clk_master_idx];
  2275. info = &m_ctrl->ctrl->clk_info;
  2276. if (!set_xo)
  2277. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.pll_clks);
  2278. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2279. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &info->xo_clk);
  2280. if (rc) {
  2281. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n", display->name, rc);
  2282. return rc;
  2283. }
  2284. /* Set source for the rest of the controllers */
  2285. display_for_each_ctrl(i, display) {
  2286. ctrl = &display->ctrl[i];
  2287. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2288. continue;
  2289. info = &ctrl->ctrl->clk_info;
  2290. if (!set_xo)
  2291. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &display->clock_info.pll_clks);
  2292. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2293. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &info->xo_clk);
  2294. if (rc) {
  2295. DSI_ERR("[%s] failed to set source clocks, rc=%d\n", display->name, rc);
  2296. return rc;
  2297. }
  2298. }
  2299. return 0;
  2300. }
  2301. int dsi_display_phy_pll_toggle(void *priv, bool prepare)
  2302. {
  2303. int rc = 0;
  2304. struct dsi_display *display = priv;
  2305. struct dsi_display_ctrl *m_ctrl;
  2306. if (!display) {
  2307. DSI_ERR("invalid arguments\n");
  2308. return -EINVAL;
  2309. }
  2310. rc = dsi_display_set_clk_src(display, !prepare);
  2311. m_ctrl = &display->ctrl[display->clk_master_idx];
  2312. if (!m_ctrl->phy) {
  2313. DSI_ERR("[%s] PHY not found\n", display->name);
  2314. return -EINVAL;
  2315. }
  2316. rc = dsi_phy_pll_toggle(m_ctrl->phy, prepare);
  2317. return rc;
  2318. }
  2319. int dsi_display_phy_configure(void *priv, bool commit)
  2320. {
  2321. int rc = 0;
  2322. struct dsi_display *display = priv;
  2323. struct dsi_display_ctrl *m_ctrl;
  2324. struct dsi_pll_resource *pll_res;
  2325. struct dsi_ctrl *ctrl;
  2326. if (!display) {
  2327. DSI_ERR("invalid arguments\n");
  2328. return -EINVAL;
  2329. }
  2330. m_ctrl = &display->ctrl[display->clk_master_idx];
  2331. if ((!m_ctrl->phy) || (!m_ctrl->ctrl)) {
  2332. DSI_ERR("[%s] PHY not found\n", display->name);
  2333. return -EINVAL;
  2334. }
  2335. pll_res = m_ctrl->phy->pll;
  2336. if (!pll_res) {
  2337. DSI_ERR("[%s] PLL res not found\n", display->name);
  2338. return -EINVAL;
  2339. }
  2340. ctrl = m_ctrl->ctrl;
  2341. pll_res->byteclk_rate = ctrl->clk_freq.byte_clk_rate;
  2342. pll_res->pclk_rate = ctrl->clk_freq.pix_clk_rate;
  2343. rc = dsi_phy_configure(m_ctrl->phy, commit);
  2344. return rc;
  2345. }
  2346. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2347. bool enable)
  2348. {
  2349. int rc = 0;
  2350. int i;
  2351. struct dsi_display_ctrl *ctrl;
  2352. display_for_each_ctrl(i, display) {
  2353. ctrl = &display->ctrl[i];
  2354. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2355. if (rc) {
  2356. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2357. display->name, enable ? "mask" : "unmask", rc);
  2358. return rc;
  2359. }
  2360. }
  2361. return 0;
  2362. }
  2363. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2364. {
  2365. struct dsi_display_ctrl *ctrl;
  2366. int i;
  2367. if (!display)
  2368. return;
  2369. display_for_each_ctrl(i, display) {
  2370. ctrl = &display->ctrl[i];
  2371. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2372. }
  2373. /*
  2374. * After retime buffer synchronization we need to turn of clk_en_sel
  2375. * bit on each phy. Avoid this for Cphy.
  2376. */
  2377. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2378. return;
  2379. display_for_each_ctrl(i, display) {
  2380. ctrl = &display->ctrl[i];
  2381. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2382. }
  2383. }
  2384. static int dsi_display_ctrl_update(struct dsi_display *display)
  2385. {
  2386. int rc = 0;
  2387. int i;
  2388. struct dsi_display_ctrl *ctrl;
  2389. display_for_each_ctrl(i, display) {
  2390. ctrl = &display->ctrl[i];
  2391. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2392. if (rc) {
  2393. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2394. display->name, i, rc);
  2395. goto error_host_deinit;
  2396. }
  2397. }
  2398. return 0;
  2399. error_host_deinit:
  2400. for (i = i - 1; i >= 0; i--) {
  2401. ctrl = &display->ctrl[i];
  2402. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2403. }
  2404. return rc;
  2405. }
  2406. static int dsi_display_ctrl_init(struct dsi_display *display)
  2407. {
  2408. int rc = 0;
  2409. int i;
  2410. struct dsi_display_ctrl *ctrl;
  2411. bool skip_op = is_skip_op_required(display);
  2412. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2413. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2414. * we will programe DSI controller as part of core clock enable.
  2415. * After that we should not re-configure DSI controller again here for
  2416. * usecases where we are resuming from ulps suspend as it might put
  2417. * the HW in bad state.
  2418. */
  2419. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2420. display_for_each_ctrl(i, display) {
  2421. ctrl = &display->ctrl[i];
  2422. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2423. if (rc) {
  2424. DSI_ERR(
  2425. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2426. display->name, i, skip_op, rc);
  2427. goto error_host_deinit;
  2428. }
  2429. }
  2430. } else {
  2431. display_for_each_ctrl(i, display) {
  2432. ctrl = &display->ctrl[i];
  2433. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2434. DSI_CTRL_OP_HOST_INIT,
  2435. true);
  2436. if (rc)
  2437. DSI_DEBUG("host init update failed rc=%d\n",
  2438. rc);
  2439. }
  2440. }
  2441. return rc;
  2442. error_host_deinit:
  2443. for (i = i - 1; i >= 0; i--) {
  2444. ctrl = &display->ctrl[i];
  2445. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2446. }
  2447. return rc;
  2448. }
  2449. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2450. {
  2451. int rc = 0;
  2452. int i;
  2453. struct dsi_display_ctrl *ctrl;
  2454. display_for_each_ctrl(i, display) {
  2455. ctrl = &display->ctrl[i];
  2456. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2457. if (rc) {
  2458. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2459. display->name, i, rc);
  2460. }
  2461. }
  2462. return rc;
  2463. }
  2464. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2465. {
  2466. int rc = 0;
  2467. int i;
  2468. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2469. bool skip_op = is_skip_op_required(display);
  2470. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2471. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2472. DSI_CTRL_ENGINE_ON, skip_op);
  2473. if (rc) {
  2474. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2475. display->name, skip_op, rc);
  2476. goto error;
  2477. }
  2478. display_for_each_ctrl(i, display) {
  2479. ctrl = &display->ctrl[i];
  2480. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2481. continue;
  2482. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2483. DSI_CTRL_ENGINE_ON, skip_op);
  2484. if (rc) {
  2485. DSI_ERR(
  2486. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2487. display->name, skip_op, rc);
  2488. goto error_disable_master;
  2489. }
  2490. }
  2491. return rc;
  2492. error_disable_master:
  2493. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2494. DSI_CTRL_ENGINE_OFF, skip_op);
  2495. error:
  2496. return rc;
  2497. }
  2498. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2499. {
  2500. int rc = 0;
  2501. int i;
  2502. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2503. bool skip_op = is_skip_op_required(display);
  2504. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2505. /*
  2506. * For platforms where ULPS is controlled by DSI controller block,
  2507. * do not disable dsi controller block if lanes are to be
  2508. * kept in ULPS during suspend. So just update the SW state
  2509. * and return early.
  2510. */
  2511. if (display->panel->ulps_suspend_enabled &&
  2512. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2513. display_for_each_ctrl(i, display) {
  2514. ctrl = &display->ctrl[i];
  2515. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2516. DSI_CTRL_OP_HOST_ENGINE,
  2517. false);
  2518. if (rc)
  2519. DSI_DEBUG("host state update failed %d\n", rc);
  2520. }
  2521. return rc;
  2522. }
  2523. display_for_each_ctrl(i, display) {
  2524. ctrl = &display->ctrl[i];
  2525. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2526. continue;
  2527. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2528. DSI_CTRL_ENGINE_OFF, skip_op);
  2529. if (rc)
  2530. DSI_ERR(
  2531. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2532. display->name, skip_op, rc);
  2533. }
  2534. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2535. DSI_CTRL_ENGINE_OFF, skip_op);
  2536. if (rc) {
  2537. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2538. display->name, skip_op, rc);
  2539. goto error;
  2540. }
  2541. error:
  2542. return rc;
  2543. }
  2544. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2545. {
  2546. int rc = 0;
  2547. int i;
  2548. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2549. bool skip_op = is_skip_op_required(display);
  2550. m_ctrl = &display->ctrl[display->video_master_idx];
  2551. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2552. DSI_CTRL_ENGINE_ON, skip_op);
  2553. if (rc) {
  2554. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2555. display->name, skip_op, rc);
  2556. goto error;
  2557. }
  2558. display_for_each_ctrl(i, display) {
  2559. ctrl = &display->ctrl[i];
  2560. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2561. continue;
  2562. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2563. DSI_CTRL_ENGINE_ON, skip_op);
  2564. if (rc) {
  2565. DSI_ERR(
  2566. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2567. display->name, skip_op, rc);
  2568. goto error_disable_master;
  2569. }
  2570. }
  2571. return rc;
  2572. error_disable_master:
  2573. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2574. DSI_CTRL_ENGINE_OFF, skip_op);
  2575. error:
  2576. return rc;
  2577. }
  2578. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2579. {
  2580. int rc = 0;
  2581. int i;
  2582. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2583. bool skip_op = is_skip_op_required(display);
  2584. m_ctrl = &display->ctrl[display->video_master_idx];
  2585. display_for_each_ctrl(i, display) {
  2586. ctrl = &display->ctrl[i];
  2587. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2588. continue;
  2589. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2590. DSI_CTRL_ENGINE_OFF, skip_op);
  2591. if (rc)
  2592. DSI_ERR(
  2593. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2594. display->name, skip_op, rc);
  2595. }
  2596. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2597. DSI_CTRL_ENGINE_OFF, skip_op);
  2598. if (rc)
  2599. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2600. display->name, skip_op, rc);
  2601. return rc;
  2602. }
  2603. static int dsi_display_phy_enable(struct dsi_display *display)
  2604. {
  2605. int rc = 0;
  2606. int i;
  2607. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2608. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2609. bool skip_op = is_skip_op_required(display);
  2610. m_ctrl = &display->ctrl[display->clk_master_idx];
  2611. if (display->ctrl_count > 1)
  2612. m_src = DSI_PLL_SOURCE_NATIVE;
  2613. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2614. m_src, true, skip_op);
  2615. if (rc) {
  2616. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2617. display->name, skip_op, rc);
  2618. goto error;
  2619. }
  2620. display_for_each_ctrl(i, display) {
  2621. ctrl = &display->ctrl[i];
  2622. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2623. continue;
  2624. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2625. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2626. if (rc) {
  2627. DSI_ERR(
  2628. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2629. display->name, skip_op, rc);
  2630. goto error_disable_master;
  2631. }
  2632. }
  2633. return rc;
  2634. error_disable_master:
  2635. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2636. error:
  2637. return rc;
  2638. }
  2639. static int dsi_display_phy_disable(struct dsi_display *display)
  2640. {
  2641. int rc = 0;
  2642. int i;
  2643. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2644. bool skip_op = is_skip_op_required(display);
  2645. m_ctrl = &display->ctrl[display->clk_master_idx];
  2646. display_for_each_ctrl(i, display) {
  2647. ctrl = &display->ctrl[i];
  2648. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2649. continue;
  2650. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2651. if (rc)
  2652. DSI_ERR(
  2653. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2654. display->name, skip_op, rc);
  2655. }
  2656. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2657. if (rc)
  2658. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2659. display->name, skip_op, rc);
  2660. return rc;
  2661. }
  2662. static int dsi_display_wake_up(struct dsi_display *display)
  2663. {
  2664. return 0;
  2665. }
  2666. static void dsi_display_mask_overflow(struct dsi_display *display, u32 flags,
  2667. bool enable)
  2668. {
  2669. struct dsi_display_ctrl *ctrl;
  2670. int i;
  2671. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2672. return;
  2673. display_for_each_ctrl(i, display) {
  2674. ctrl = &display->ctrl[i];
  2675. if (!ctrl)
  2676. continue;
  2677. dsi_ctrl_mask_overflow(ctrl->ctrl, enable);
  2678. }
  2679. }
  2680. static int dsi_display_broadcast_cmd(struct dsi_display *display, struct dsi_cmd_desc *cmd)
  2681. {
  2682. int rc = 0;
  2683. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2684. int i;
  2685. /*
  2686. * 1. Setup commands in FIFO
  2687. * 2. Trigger commands
  2688. */
  2689. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2690. dsi_display_mask_overflow(display, cmd->ctrl_flags, true);
  2691. cmd->ctrl_flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2692. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  2693. if (rc) {
  2694. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2695. display->name, rc);
  2696. goto error;
  2697. }
  2698. cmd->ctrl_flags &= ~DSI_CTRL_CMD_BROADCAST_MASTER;
  2699. display_for_each_ctrl(i, display) {
  2700. ctrl = &display->ctrl[i];
  2701. if (ctrl == m_ctrl)
  2702. continue;
  2703. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, cmd);
  2704. if (rc) {
  2705. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2706. display->name, rc);
  2707. goto error;
  2708. }
  2709. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, cmd->ctrl_flags);
  2710. if (rc) {
  2711. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2712. display->name, rc);
  2713. goto error;
  2714. }
  2715. }
  2716. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, cmd->ctrl_flags | DSI_CTRL_CMD_BROADCAST_MASTER);
  2717. if (rc) {
  2718. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2719. display->name, rc);
  2720. goto error;
  2721. }
  2722. error:
  2723. dsi_display_mask_overflow(display, cmd->ctrl_flags, false);
  2724. return rc;
  2725. }
  2726. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2727. {
  2728. int rc = 0;
  2729. int i;
  2730. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2731. /*
  2732. * For continuous splash and trusted vm environment,
  2733. * ctrl states are updated separately and hence we do
  2734. * an early return
  2735. */
  2736. if (is_skip_op_required(display)) {
  2737. DSI_DEBUG(
  2738. "cont splash/trusted vm use case, phy sw reset not required\n");
  2739. return 0;
  2740. }
  2741. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2742. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2743. if (rc) {
  2744. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2745. goto error;
  2746. }
  2747. display_for_each_ctrl(i, display) {
  2748. ctrl = &display->ctrl[i];
  2749. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2750. continue;
  2751. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2752. if (rc) {
  2753. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2754. display->name, rc);
  2755. goto error;
  2756. }
  2757. }
  2758. error:
  2759. return rc;
  2760. }
  2761. static int dsi_host_attach(struct mipi_dsi_host *host,
  2762. struct mipi_dsi_device *dsi)
  2763. {
  2764. return 0;
  2765. }
  2766. static int dsi_host_detach(struct mipi_dsi_host *host,
  2767. struct mipi_dsi_device *dsi)
  2768. {
  2769. return 0;
  2770. }
  2771. int dsi_host_transfer_sub(struct mipi_dsi_host *host, struct dsi_cmd_desc *cmd)
  2772. {
  2773. struct dsi_display *display;
  2774. int rc = 0, ret = 0;
  2775. if (!host || !cmd) {
  2776. DSI_ERR("Invalid params\n");
  2777. return 0;
  2778. }
  2779. display = to_dsi_display(host);
  2780. /* Avoid sending DCS commands when ESD recovery is pending */
  2781. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2782. DSI_DEBUG("ESD recovery pending\n");
  2783. return 0;
  2784. }
  2785. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2786. DSI_ALL_CLKS, DSI_CLK_ON);
  2787. if (rc) {
  2788. DSI_ERR("[%s] failed to enable all DSI clocks, rc=%d\n",
  2789. display->name, rc);
  2790. goto error;
  2791. }
  2792. rc = dsi_display_wake_up(display);
  2793. if (rc) {
  2794. DSI_ERR("[%s] failed to wake up display, rc=%d\n",
  2795. display->name, rc);
  2796. goto error_disable_clks;
  2797. }
  2798. rc = dsi_display_cmd_engine_enable(display);
  2799. if (rc) {
  2800. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2801. display->name, rc);
  2802. goto error_disable_clks;
  2803. }
  2804. if (display->tx_cmd_buf == NULL) {
  2805. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2806. if (rc) {
  2807. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2808. goto error_disable_cmd_engine;
  2809. }
  2810. }
  2811. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  2812. if (cmd->ctrl_flags & DSI_CTRL_CMD_BROADCAST) {
  2813. rc = dsi_display_broadcast_cmd(display, cmd);
  2814. if (rc) {
  2815. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n", display->name, rc);
  2816. goto error_disable_cmd_engine;
  2817. }
  2818. } else {
  2819. int idx = cmd->ctrl;
  2820. rc = dsi_ctrl_cmd_transfer(display->ctrl[idx].ctrl, cmd);
  2821. if (rc) {
  2822. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2823. display->name, rc);
  2824. goto error_disable_cmd_engine;
  2825. }
  2826. }
  2827. error_disable_cmd_engine:
  2828. ret = dsi_display_cmd_engine_disable(display);
  2829. if (ret) {
  2830. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  2831. display->name, ret);
  2832. }
  2833. error_disable_clks:
  2834. ret = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2835. DSI_ALL_CLKS, DSI_CLK_OFF);
  2836. if (ret) {
  2837. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  2838. display->name, ret);
  2839. }
  2840. error:
  2841. return rc;
  2842. }
  2843. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg)
  2844. {
  2845. int rc = 0;
  2846. struct dsi_cmd_desc cmd;
  2847. if (!msg) {
  2848. DSI_ERR("Invalid params\n");
  2849. return 0;
  2850. }
  2851. memcpy(&cmd.msg, msg, sizeof(*msg));
  2852. cmd.ctrl = 0;
  2853. cmd.post_wait_ms = 0;
  2854. cmd.ctrl_flags = 0;
  2855. rc = dsi_host_transfer_sub(host, &cmd);
  2856. return rc;
  2857. }
  2858. static struct mipi_dsi_host_ops dsi_host_ops = {
  2859. .attach = dsi_host_attach,
  2860. .detach = dsi_host_detach,
  2861. .transfer = dsi_host_transfer,
  2862. };
  2863. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2864. {
  2865. int rc = 0;
  2866. struct mipi_dsi_host *host = &display->host;
  2867. host->dev = &display->pdev->dev;
  2868. host->ops = &dsi_host_ops;
  2869. rc = mipi_dsi_host_register(host);
  2870. if (rc) {
  2871. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2872. display->name, rc);
  2873. goto error;
  2874. }
  2875. error:
  2876. return rc;
  2877. }
  2878. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2879. {
  2880. int rc = 0;
  2881. struct mipi_dsi_host *host = &display->host;
  2882. mipi_dsi_host_unregister(host);
  2883. host->dev = NULL;
  2884. host->ops = NULL;
  2885. return rc;
  2886. }
  2887. static bool dsi_display_check_prefix(const char *clk_prefix,
  2888. const char *clk_name)
  2889. {
  2890. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2891. }
  2892. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2893. char *dsi_clk_name)
  2894. {
  2895. if (display->fw)
  2896. return dsi_parser_count_strings(display->parser_node,
  2897. dsi_clk_name);
  2898. else
  2899. return of_property_count_strings(display->panel_node,
  2900. dsi_clk_name);
  2901. }
  2902. static void dsi_display_get_clock_name(struct dsi_display *display,
  2903. char *dsi_clk_name, int index,
  2904. const char **clk_name)
  2905. {
  2906. if (display->fw)
  2907. dsi_parser_read_string_index(display->parser_node,
  2908. dsi_clk_name, index, clk_name);
  2909. else
  2910. of_property_read_string_index(display->panel_node,
  2911. dsi_clk_name, index, clk_name);
  2912. }
  2913. static int dsi_display_clocks_init(struct dsi_display *display)
  2914. {
  2915. int i, rc = 0, num_clk = 0;
  2916. const char *clk_name;
  2917. const char *pll_byte = "pll_byte", *pll_dsi = "pll_dsi";
  2918. struct clk *dsi_clk;
  2919. struct dsi_clk_link_set *pll = &display->clock_info.pll_clks;
  2920. char *dsi_clock_name;
  2921. if (!strcmp(display->display_type, "primary"))
  2922. dsi_clock_name = "qcom,dsi-select-clocks";
  2923. else
  2924. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2925. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2926. for (i = 0; i < num_clk; i++) {
  2927. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2928. &clk_name);
  2929. DSI_DEBUG("clock name:%s\n", clk_name);
  2930. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2931. if (IS_ERR_OR_NULL(dsi_clk)) {
  2932. rc = PTR_ERR(dsi_clk);
  2933. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2934. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2935. pll->byte_clk = NULL;
  2936. goto error;
  2937. }
  2938. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2939. pll->pixel_clk = NULL;
  2940. goto error;
  2941. }
  2942. }
  2943. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2944. pll->byte_clk = dsi_clk;
  2945. continue;
  2946. }
  2947. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2948. pll->pixel_clk = dsi_clk;
  2949. continue;
  2950. }
  2951. }
  2952. return 0;
  2953. error:
  2954. return rc;
  2955. }
  2956. static int dsi_display_clk_ctrl_cb(void *priv,
  2957. struct dsi_clk_ctrl_info clk_state_info)
  2958. {
  2959. int rc = 0;
  2960. struct dsi_display *display = NULL;
  2961. void *clk_handle = NULL;
  2962. if (!priv) {
  2963. DSI_ERR("Invalid params\n");
  2964. return -EINVAL;
  2965. }
  2966. display = priv;
  2967. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2968. clk_handle = display->mdp_clk_handle;
  2969. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2970. clk_handle = display->dsi_clk_handle;
  2971. } else {
  2972. DSI_ERR("invalid clk handle, return error\n");
  2973. return -EINVAL;
  2974. }
  2975. /*
  2976. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2977. * to turn off DSI clocks.
  2978. */
  2979. rc = dsi_display_clk_ctrl(clk_handle,
  2980. clk_state_info.clk_type, clk_state_info.clk_state);
  2981. if (rc) {
  2982. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2983. display->name, clk_state_info.clk_state,
  2984. clk_state_info.clk_type, rc);
  2985. return rc;
  2986. }
  2987. return 0;
  2988. }
  2989. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  2990. {
  2991. int i;
  2992. struct dsi_display_ctrl *ctrl;
  2993. if (!display)
  2994. return;
  2995. display_for_each_ctrl(i, display) {
  2996. ctrl = &display->ctrl[i];
  2997. if (!ctrl)
  2998. continue;
  2999. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  3000. }
  3001. }
  3002. int dsi_pre_clkoff_cb(void *priv,
  3003. enum dsi_clk_type clk,
  3004. enum dsi_lclk_type l_type,
  3005. enum dsi_clk_state new_state)
  3006. {
  3007. int rc = 0, i;
  3008. struct dsi_display *display = priv;
  3009. struct dsi_display_ctrl *ctrl;
  3010. /*
  3011. * If Idle Power Collapse occurs immediately after a CMD
  3012. * transfer with an asynchronous wait for DMA done, ensure
  3013. * that the work queued is scheduled and completed before turning
  3014. * off the clocks and disabling interrupts to validate the command
  3015. * transfer.
  3016. */
  3017. display_for_each_ctrl(i, display) {
  3018. ctrl = &display->ctrl[i];
  3019. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  3020. continue;
  3021. flush_workqueue(display->dma_cmd_workq);
  3022. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  3023. ctrl->ctrl->dma_wait_queued = false;
  3024. }
  3025. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3026. (l_type & DSI_LINK_LP_CLK)) {
  3027. /*
  3028. * If continuous clock is enabled then disable it
  3029. * before entering into ULPS Mode.
  3030. */
  3031. if (display->panel->host_config.force_hs_clk_lane)
  3032. _dsi_display_continuous_clk_ctrl(display, false);
  3033. /*
  3034. * If ULPS feature is enabled, enter ULPS first.
  3035. * However, when blanking the panel, we should enter ULPS
  3036. * only if ULPS during suspend feature is enabled.
  3037. */
  3038. if (!dsi_panel_initialized(display->panel)) {
  3039. if (display->panel->ulps_suspend_enabled)
  3040. rc = dsi_display_set_ulps(display, true);
  3041. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  3042. rc = dsi_display_set_ulps(display, true);
  3043. }
  3044. if (rc)
  3045. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  3046. __func__, rc);
  3047. }
  3048. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3049. (l_type & DSI_LINK_HS_CLK)) {
  3050. /*
  3051. * PHY clock gating should be disabled before the PLL and the
  3052. * branch clocks are turned off. Otherwise, it is possible that
  3053. * the clock RCGs may not be turned off correctly resulting
  3054. * in clock warnings.
  3055. */
  3056. rc = dsi_display_config_clk_gating(display, false);
  3057. if (rc)
  3058. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  3059. display->name, rc);
  3060. }
  3061. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  3062. /*
  3063. * Enable DSI clamps only if entering idle power collapse or
  3064. * when ULPS during suspend is enabled..
  3065. */
  3066. if (dsi_panel_initialized(display->panel) ||
  3067. display->panel->ulps_suspend_enabled) {
  3068. dsi_display_phy_idle_off(display);
  3069. rc = dsi_display_set_clamp(display, true);
  3070. if (rc)
  3071. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  3072. __func__, rc);
  3073. rc = dsi_display_phy_reset_config(display, false);
  3074. if (rc)
  3075. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3076. __func__, rc);
  3077. } else {
  3078. /* Make sure that controller is not in ULPS state when
  3079. * the DSI link is not active.
  3080. */
  3081. rc = dsi_display_set_ulps(display, false);
  3082. if (rc)
  3083. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  3084. __func__, rc);
  3085. }
  3086. /* dsi will not be able to serve irqs from here on */
  3087. dsi_display_ctrl_irq_update(display, false);
  3088. /* cache the MISR values */
  3089. display_for_each_ctrl(i, display) {
  3090. ctrl = &display->ctrl[i];
  3091. if (!ctrl->ctrl)
  3092. continue;
  3093. dsi_ctrl_cache_misr(ctrl->ctrl);
  3094. }
  3095. }
  3096. return rc;
  3097. }
  3098. int dsi_post_clkon_cb(void *priv,
  3099. enum dsi_clk_type clk,
  3100. enum dsi_lclk_type l_type,
  3101. enum dsi_clk_state curr_state)
  3102. {
  3103. int rc = 0;
  3104. struct dsi_display *display = priv;
  3105. bool mmss_clamp = false;
  3106. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3107. mmss_clamp = display->clamp_enabled;
  3108. /*
  3109. * controller setup is needed if coming out of idle
  3110. * power collapse with clamps enabled.
  3111. */
  3112. if (mmss_clamp)
  3113. dsi_display_ctrl_setup(display);
  3114. /*
  3115. * Phy setup is needed if coming out of idle
  3116. * power collapse with clamps enabled.
  3117. */
  3118. if (display->phy_idle_power_off || mmss_clamp)
  3119. dsi_display_phy_idle_on(display, mmss_clamp);
  3120. if (display->ulps_enabled && mmss_clamp) {
  3121. /*
  3122. * ULPS Entry Request. This is needed if the lanes were
  3123. * in ULPS prior to power collapse, since after
  3124. * power collapse and reset, the DSI controller resets
  3125. * back to idle state and not ULPS. This ulps entry
  3126. * request will transition the state of the DSI
  3127. * controller to ULPS which will match the state of the
  3128. * DSI phy. This needs to be done prior to disabling
  3129. * the DSI clamps.
  3130. *
  3131. * Also, reset the ulps flag so that ulps_config
  3132. * function would reconfigure the controller state to
  3133. * ULPS.
  3134. */
  3135. display->ulps_enabled = false;
  3136. rc = dsi_display_set_ulps(display, true);
  3137. if (rc) {
  3138. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3139. __func__, rc);
  3140. goto error;
  3141. }
  3142. }
  3143. rc = dsi_display_phy_reset_config(display, true);
  3144. if (rc) {
  3145. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3146. __func__, rc);
  3147. goto error;
  3148. }
  3149. rc = dsi_display_set_clamp(display, false);
  3150. if (rc) {
  3151. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3152. __func__, rc);
  3153. goto error;
  3154. }
  3155. }
  3156. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3157. /*
  3158. * Toggle the resync FIFO everytime clock changes, except
  3159. * when cont-splash screen transition is going on.
  3160. * Toggling resync FIFO during cont splash transition
  3161. * can lead to blinks on the display.
  3162. */
  3163. if (!display->is_cont_splash_enabled)
  3164. dsi_display_toggle_resync_fifo(display);
  3165. if (display->ulps_enabled) {
  3166. rc = dsi_display_set_ulps(display, false);
  3167. if (rc) {
  3168. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3169. __func__, rc);
  3170. goto error;
  3171. }
  3172. }
  3173. if (display->panel->host_config.force_hs_clk_lane)
  3174. _dsi_display_continuous_clk_ctrl(display, true);
  3175. rc = dsi_display_config_clk_gating(display, true);
  3176. if (rc) {
  3177. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3178. display->name, rc);
  3179. goto error;
  3180. }
  3181. }
  3182. /* enable dsi to serve irqs */
  3183. if (clk & DSI_CORE_CLK)
  3184. dsi_display_ctrl_irq_update(display, true);
  3185. error:
  3186. return rc;
  3187. }
  3188. int dsi_post_clkoff_cb(void *priv,
  3189. enum dsi_clk_type clk_type,
  3190. enum dsi_lclk_type l_type,
  3191. enum dsi_clk_state curr_state)
  3192. {
  3193. int rc = 0;
  3194. struct dsi_display *display = priv;
  3195. if (!display) {
  3196. DSI_ERR("%s: Invalid arg\n", __func__);
  3197. return -EINVAL;
  3198. }
  3199. if ((clk_type & DSI_CORE_CLK) &&
  3200. (curr_state == DSI_CLK_OFF)) {
  3201. rc = dsi_display_phy_power_off(display);
  3202. if (rc)
  3203. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3204. display->name, rc);
  3205. rc = dsi_display_ctrl_power_off(display);
  3206. if (rc)
  3207. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3208. display->name, rc);
  3209. }
  3210. return rc;
  3211. }
  3212. int dsi_pre_clkon_cb(void *priv,
  3213. enum dsi_clk_type clk_type,
  3214. enum dsi_lclk_type l_type,
  3215. enum dsi_clk_state new_state)
  3216. {
  3217. int rc = 0;
  3218. struct dsi_display *display = priv;
  3219. if (!display) {
  3220. DSI_ERR("%s: invalid input\n", __func__);
  3221. return -EINVAL;
  3222. }
  3223. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3224. /*
  3225. * Enable DSI core power
  3226. * 1.> PANEL_PM are controlled as part of
  3227. * panel_power_ctrl. Needed not be handled here.
  3228. * 2.> CTRL_PM need to be enabled/disabled
  3229. * only during unblank/blank. Their state should
  3230. * not be changed during static screen.
  3231. */
  3232. DSI_DEBUG("updating power states for ctrl and phy\n");
  3233. rc = dsi_display_ctrl_power_on(display);
  3234. if (rc) {
  3235. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3236. display->name, rc);
  3237. return rc;
  3238. }
  3239. rc = dsi_display_phy_power_on(display);
  3240. if (rc) {
  3241. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3242. display->name, rc);
  3243. return rc;
  3244. }
  3245. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3246. }
  3247. return rc;
  3248. }
  3249. static void __set_lane_map_v2(u8 *lane_map_v2,
  3250. enum dsi_phy_data_lanes lane0,
  3251. enum dsi_phy_data_lanes lane1,
  3252. enum dsi_phy_data_lanes lane2,
  3253. enum dsi_phy_data_lanes lane3)
  3254. {
  3255. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3256. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3257. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3258. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3259. }
  3260. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3261. {
  3262. int rc = 0, i = 0;
  3263. const char *data;
  3264. u8 temp[DSI_LANE_MAX - 1];
  3265. if (!display) {
  3266. DSI_ERR("invalid params\n");
  3267. return -EINVAL;
  3268. }
  3269. /* lane-map-v2 supersedes lane-map-v1 setting */
  3270. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3271. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3272. if (!rc) {
  3273. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3274. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3275. return 0;
  3276. } else if (rc != EINVAL) {
  3277. DSI_DEBUG("Incorrect mapping, configure default\n");
  3278. goto set_default;
  3279. }
  3280. /* lane-map older version, for DSI controller version < 2.0 */
  3281. data = of_get_property(display->pdev->dev.of_node,
  3282. "qcom,lane-map", NULL);
  3283. if (!data)
  3284. goto set_default;
  3285. if (!strcmp(data, "lane_map_3012")) {
  3286. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3287. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3288. DSI_PHYSICAL_LANE_1,
  3289. DSI_PHYSICAL_LANE_2,
  3290. DSI_PHYSICAL_LANE_3,
  3291. DSI_PHYSICAL_LANE_0);
  3292. } else if (!strcmp(data, "lane_map_2301")) {
  3293. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3294. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3295. DSI_PHYSICAL_LANE_2,
  3296. DSI_PHYSICAL_LANE_3,
  3297. DSI_PHYSICAL_LANE_0,
  3298. DSI_PHYSICAL_LANE_1);
  3299. } else if (!strcmp(data, "lane_map_1230")) {
  3300. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3301. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3302. DSI_PHYSICAL_LANE_3,
  3303. DSI_PHYSICAL_LANE_0,
  3304. DSI_PHYSICAL_LANE_1,
  3305. DSI_PHYSICAL_LANE_2);
  3306. } else if (!strcmp(data, "lane_map_0321")) {
  3307. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3308. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3309. DSI_PHYSICAL_LANE_0,
  3310. DSI_PHYSICAL_LANE_3,
  3311. DSI_PHYSICAL_LANE_2,
  3312. DSI_PHYSICAL_LANE_1);
  3313. } else if (!strcmp(data, "lane_map_1032")) {
  3314. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3315. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3316. DSI_PHYSICAL_LANE_1,
  3317. DSI_PHYSICAL_LANE_0,
  3318. DSI_PHYSICAL_LANE_3,
  3319. DSI_PHYSICAL_LANE_2);
  3320. } else if (!strcmp(data, "lane_map_2103")) {
  3321. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3322. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3323. DSI_PHYSICAL_LANE_2,
  3324. DSI_PHYSICAL_LANE_1,
  3325. DSI_PHYSICAL_LANE_0,
  3326. DSI_PHYSICAL_LANE_3);
  3327. } else if (!strcmp(data, "lane_map_3210")) {
  3328. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3329. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3330. DSI_PHYSICAL_LANE_3,
  3331. DSI_PHYSICAL_LANE_2,
  3332. DSI_PHYSICAL_LANE_1,
  3333. DSI_PHYSICAL_LANE_0);
  3334. } else {
  3335. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3336. __func__, data);
  3337. goto set_default;
  3338. }
  3339. return 0;
  3340. set_default:
  3341. /* default lane mapping */
  3342. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3343. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3344. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3345. return 0;
  3346. }
  3347. static int dsi_display_get_phandle_index(
  3348. struct dsi_display *display,
  3349. const char *propname, int count, int index)
  3350. {
  3351. struct device_node *disp_node = display->panel_node;
  3352. u32 *val = NULL;
  3353. int rc = 0;
  3354. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3355. if (ZERO_OR_NULL_PTR(val)) {
  3356. rc = -ENOMEM;
  3357. goto end;
  3358. }
  3359. if (index >= count)
  3360. goto end;
  3361. if (display->fw)
  3362. rc = dsi_parser_read_u32_array(display->parser_node,
  3363. propname, val, count);
  3364. else
  3365. rc = of_property_read_u32_array(disp_node, propname,
  3366. val, count);
  3367. if (rc)
  3368. goto end;
  3369. rc = val[index];
  3370. DSI_DEBUG("%s index=%d\n", propname, rc);
  3371. end:
  3372. kfree(val);
  3373. return rc;
  3374. }
  3375. static bool dsi_display_validate_res(struct dsi_display *display)
  3376. {
  3377. struct device_node *of_node = display->pdev->dev.of_node;
  3378. struct of_phandle_iterator it;
  3379. bool ctrl_avail = false;
  3380. bool phy_avail = false;
  3381. /*
  3382. * At least if one of the controller or PHY is present or has been probed, the
  3383. * dsi_display_dev_probe can pass this check. Exact ctrl and PHY match will be
  3384. * done after the DT is parsed.
  3385. */
  3386. of_phandle_iterator_init(&it, of_node, "qcom,dsi-ctrl", NULL, 0);
  3387. while (of_phandle_iterator_next(&it) == 0)
  3388. ctrl_avail |= dsi_ctrl_check_resource(it.node);
  3389. of_phandle_iterator_init(&it, of_node, "qcom,dsi-phy", NULL, 0);
  3390. while (of_phandle_iterator_next(&it) == 0)
  3391. phy_avail |= dsi_phy_check_resource(it.node);
  3392. return (ctrl_avail & phy_avail);
  3393. }
  3394. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3395. const char *propname)
  3396. {
  3397. if (display->fw)
  3398. return dsi_parser_count_u32_elems(display->parser_node,
  3399. propname);
  3400. else
  3401. return of_property_count_u32_elems(display->panel_node,
  3402. propname);
  3403. }
  3404. static int dsi_display_parse_dt(struct dsi_display *display)
  3405. {
  3406. int i, rc = 0;
  3407. u32 phy_count = 0;
  3408. struct device_node *of_node = display->pdev->dev.of_node;
  3409. char *dsi_ctrl_name, *dsi_phy_name;
  3410. if (!strcmp(display->display_type, "primary")) {
  3411. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3412. dsi_phy_name = "qcom,dsi-phy-num";
  3413. } else {
  3414. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3415. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3416. }
  3417. display->ctrl_count = dsi_display_get_phandle_count(display,
  3418. dsi_ctrl_name);
  3419. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3420. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3421. display->ctrl_count, phy_count);
  3422. if (!phy_count || !display->ctrl_count) {
  3423. DSI_ERR("no ctrl/phys found\n");
  3424. rc = -ENODEV;
  3425. goto error;
  3426. }
  3427. if (phy_count != display->ctrl_count) {
  3428. DSI_ERR("different ctrl and phy counts\n");
  3429. rc = -ENODEV;
  3430. goto error;
  3431. }
  3432. display_for_each_ctrl(i, display) {
  3433. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3434. int index;
  3435. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3436. display->ctrl_count, i);
  3437. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3438. "qcom,dsi-ctrl", index);
  3439. of_node_put(ctrl->ctrl_of_node);
  3440. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3441. display->ctrl_count, i);
  3442. ctrl->phy_of_node = of_parse_phandle(of_node,
  3443. "qcom,dsi-phy", index);
  3444. of_node_put(ctrl->phy_of_node);
  3445. }
  3446. /* Parse TE data */
  3447. dsi_display_parse_te_data(display);
  3448. /* Parse all external bridges from port 0 */
  3449. display_for_each_ctrl(i, display) {
  3450. display->ext_bridge[i].node_of =
  3451. of_graph_get_remote_node(of_node, 0, i);
  3452. if (display->ext_bridge[i].node_of)
  3453. display->ext_bridge_cnt++;
  3454. else
  3455. break;
  3456. }
  3457. /* Parse Demura data */
  3458. dsi_display_parse_demura_data(display);
  3459. DSI_DEBUG("success\n");
  3460. error:
  3461. return rc;
  3462. }
  3463. static bool dsi_display_validate_panel_resources(struct dsi_display *display)
  3464. {
  3465. if (!display->panel->te_using_watchdog_timer) {
  3466. if (!gpio_is_valid(display->panel->reset_config.reset_gpio)) {
  3467. DSI_ERR("invalid reset gpio for the panel\n");
  3468. return false;
  3469. }
  3470. } else {
  3471. display->panel->power_info.count = 0;
  3472. DSI_DEBUG("no dir set and no request for gpios in sim panel\n");
  3473. }
  3474. return true;
  3475. }
  3476. static int dsi_display_res_init(struct dsi_display *display)
  3477. {
  3478. int rc = 0;
  3479. int i;
  3480. struct dsi_display_ctrl *ctrl;
  3481. display_for_each_ctrl(i, display) {
  3482. ctrl = &display->ctrl[i];
  3483. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3484. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3485. rc = PTR_ERR(ctrl->ctrl);
  3486. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3487. ctrl->ctrl = NULL;
  3488. goto error_ctrl_put;
  3489. }
  3490. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3491. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3492. rc = PTR_ERR(ctrl->phy);
  3493. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3494. dsi_ctrl_put(ctrl->ctrl);
  3495. ctrl->phy = NULL;
  3496. goto error_ctrl_put;
  3497. }
  3498. }
  3499. display->panel = dsi_panel_get(&display->pdev->dev,
  3500. display->panel_node,
  3501. display->parser_node,
  3502. display->display_type,
  3503. display->cmdline_topology,
  3504. display->trusted_vm_env);
  3505. if (IS_ERR_OR_NULL(display->panel)) {
  3506. rc = PTR_ERR(display->panel);
  3507. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3508. display->panel = NULL;
  3509. goto error_ctrl_put;
  3510. }
  3511. display->panel->te_using_watchdog_timer |= display->sw_te_using_wd;
  3512. if (!dsi_display_validate_panel_resources(display))
  3513. goto error_ctrl_put;
  3514. display_for_each_ctrl(i, display) {
  3515. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3516. struct dsi_host_common_cfg *host = &display->panel->host_config;
  3517. phy->cfg.force_clk_lane_hs =
  3518. display->panel->host_config.force_hs_clk_lane;
  3519. phy->cfg.phy_type =
  3520. display->panel->host_config.phy_type;
  3521. /*
  3522. * Parse the dynamic clock trim codes for PLL, for video mode panels that have
  3523. * dynamic clock property set.
  3524. */
  3525. if ((display->panel->dyn_clk_caps.dyn_clk_support) &&
  3526. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  3527. dsi_phy_pll_parse_dfps_data(phy);
  3528. phy->cfg.split_link.enabled = host->split_link.enabled;
  3529. phy->cfg.split_link.num_sublinks = host->split_link.num_sublinks;
  3530. phy->cfg.split_link.lanes_per_sublink = host->split_link.lanes_per_sublink;
  3531. }
  3532. rc = dsi_display_parse_lane_map(display);
  3533. if (rc) {
  3534. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3535. goto error_ctrl_put;
  3536. }
  3537. rc = dsi_display_clocks_init(display);
  3538. if (rc) {
  3539. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3540. goto error_ctrl_put;
  3541. }
  3542. /**
  3543. * In trusted vm, the connectors will not be enabled
  3544. * until the HW resources are assigned and accepted.
  3545. */
  3546. if (display->trusted_vm_env) {
  3547. display->is_active = false;
  3548. display->hw_ownership = false;
  3549. } else {
  3550. display->is_active = true;
  3551. display->hw_ownership = true;
  3552. }
  3553. return 0;
  3554. error_ctrl_put:
  3555. for (i = i - 1; i >= 0; i--) {
  3556. ctrl = &display->ctrl[i];
  3557. dsi_ctrl_put(ctrl->ctrl);
  3558. dsi_phy_put(ctrl->phy);
  3559. }
  3560. return rc;
  3561. }
  3562. static int dsi_display_res_deinit(struct dsi_display *display)
  3563. {
  3564. int rc = 0;
  3565. int i;
  3566. struct dsi_display_ctrl *ctrl;
  3567. display_for_each_ctrl(i, display) {
  3568. ctrl = &display->ctrl[i];
  3569. dsi_phy_put(ctrl->phy);
  3570. dsi_ctrl_put(ctrl->ctrl);
  3571. }
  3572. if (display->panel)
  3573. dsi_panel_put(display->panel);
  3574. return rc;
  3575. }
  3576. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3577. struct dsi_display_mode *mode,
  3578. u32 flags)
  3579. {
  3580. int rc = 0;
  3581. int i;
  3582. struct dsi_display_ctrl *ctrl;
  3583. /*
  3584. * To set a mode:
  3585. * 1. Controllers should be turned off.
  3586. * 2. Link clocks should be off.
  3587. * 3. Phy should be disabled.
  3588. */
  3589. display_for_each_ctrl(i, display) {
  3590. ctrl = &display->ctrl[i];
  3591. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3592. (ctrl->phy_enabled)) {
  3593. rc = -EINVAL;
  3594. goto error;
  3595. }
  3596. }
  3597. error:
  3598. return rc;
  3599. }
  3600. static bool dsi_display_is_seamless_dfps_possible(
  3601. const struct dsi_display *display,
  3602. const struct dsi_display_mode *tgt,
  3603. const enum dsi_dfps_type dfps_type)
  3604. {
  3605. struct dsi_display_mode *cur;
  3606. if (!display || !tgt || !display->panel) {
  3607. DSI_ERR("Invalid params\n");
  3608. return false;
  3609. }
  3610. cur = display->panel->cur_mode;
  3611. if (cur->timing.h_active != tgt->timing.h_active) {
  3612. DSI_DEBUG("timing.h_active differs %d %d\n",
  3613. cur->timing.h_active, tgt->timing.h_active);
  3614. return false;
  3615. }
  3616. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3617. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3618. cur->timing.h_back_porch,
  3619. tgt->timing.h_back_porch);
  3620. return false;
  3621. }
  3622. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3623. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3624. cur->timing.h_sync_width,
  3625. tgt->timing.h_sync_width);
  3626. return false;
  3627. }
  3628. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3629. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3630. cur->timing.h_front_porch,
  3631. tgt->timing.h_front_porch);
  3632. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3633. return false;
  3634. }
  3635. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3636. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3637. cur->timing.h_skew,
  3638. tgt->timing.h_skew);
  3639. return false;
  3640. }
  3641. /* skip polarity comparison */
  3642. if (cur->timing.v_active != tgt->timing.v_active) {
  3643. DSI_DEBUG("timing.v_active differs %d %d\n",
  3644. cur->timing.v_active,
  3645. tgt->timing.v_active);
  3646. return false;
  3647. }
  3648. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3649. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3650. cur->timing.v_back_porch,
  3651. tgt->timing.v_back_porch);
  3652. return false;
  3653. }
  3654. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3655. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3656. cur->timing.v_sync_width,
  3657. tgt->timing.v_sync_width);
  3658. return false;
  3659. }
  3660. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3661. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3662. cur->timing.v_front_porch,
  3663. tgt->timing.v_front_porch);
  3664. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3665. return false;
  3666. }
  3667. /* skip polarity comparison */
  3668. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3669. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3670. cur->timing.refresh_rate,
  3671. tgt->timing.refresh_rate);
  3672. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3673. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3674. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3675. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3676. DSI_DEBUG("flags differs %d %d\n",
  3677. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3678. return true;
  3679. }
  3680. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3681. {
  3682. struct dsi_host_common_cfg *config;
  3683. struct dsi_display_ctrl *m_ctrl;
  3684. int phy_ver;
  3685. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3686. config = &display->panel->host_config;
  3687. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3688. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3689. config->byte_intf_clk_div = 1;
  3690. else
  3691. config->byte_intf_clk_div = 2;
  3692. }
  3693. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3694. u32 bit_clk_rate)
  3695. {
  3696. int rc = 0;
  3697. int i;
  3698. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3699. if (!display->panel) {
  3700. DSI_ERR("Invalid params\n");
  3701. return -EINVAL;
  3702. }
  3703. if (bit_clk_rate == 0) {
  3704. DSI_ERR("Invalid bit clock rate\n");
  3705. return -EINVAL;
  3706. }
  3707. display->config.bit_clk_rate_hz = bit_clk_rate;
  3708. display_for_each_ctrl(i, display) {
  3709. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3710. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3711. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3712. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3713. byte_intf_clk_rate;
  3714. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3715. struct dsi_host_common_cfg *host_cfg;
  3716. mutex_lock(&ctrl->ctrl_lock);
  3717. host_cfg = &display->panel->host_config;
  3718. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3719. num_of_lanes++;
  3720. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3721. num_of_lanes++;
  3722. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3723. num_of_lanes++;
  3724. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3725. num_of_lanes++;
  3726. if (num_of_lanes == 0) {
  3727. DSI_ERR("Invalid lane count\n");
  3728. rc = -EINVAL;
  3729. goto error;
  3730. }
  3731. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3732. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3733. bit_rate_per_lane = bit_rate;
  3734. do_div(bit_rate_per_lane, num_of_lanes);
  3735. pclk_rate = bit_rate;
  3736. do_div(pclk_rate, bpp);
  3737. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3738. bit_rate_per_lane = bit_rate;
  3739. do_div(bit_rate_per_lane, num_of_lanes);
  3740. byte_clk_rate = bit_rate_per_lane;
  3741. do_div(byte_clk_rate, 8);
  3742. byte_intf_clk_rate = byte_clk_rate;
  3743. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3744. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3745. } else {
  3746. bit_rate_per_lane = bit_clk_rate;
  3747. pclk_rate *= bits_per_symbol;
  3748. do_div(pclk_rate, num_of_symbols);
  3749. byte_clk_rate = bit_clk_rate;
  3750. do_div(byte_clk_rate, num_of_symbols);
  3751. /* For CPHY, byte_intf_clk is same as byte_clk */
  3752. byte_intf_clk_rate = byte_clk_rate;
  3753. }
  3754. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3755. bit_rate, bit_rate_per_lane);
  3756. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3757. byte_clk_rate, byte_intf_clk_rate);
  3758. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3759. SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
  3760. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3761. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3762. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3763. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3764. ctrl->clk_freq, ctrl->cell_index);
  3765. if (rc) {
  3766. DSI_ERR("Failed to update link frequencies\n");
  3767. goto error;
  3768. }
  3769. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3770. error:
  3771. mutex_unlock(&ctrl->ctrl_lock);
  3772. /* TODO: recover ctrl->clk_freq in case of failure */
  3773. if (rc)
  3774. return rc;
  3775. }
  3776. return 0;
  3777. }
  3778. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3779. struct dsi_dyn_clk_delay *delay,
  3780. struct dsi_display_mode *mode)
  3781. {
  3782. u32 esc_clk_rate_hz;
  3783. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3784. u32 hsync_period = 0;
  3785. struct dsi_display_ctrl *m_ctrl;
  3786. struct dsi_ctrl *dsi_ctrl;
  3787. struct dsi_phy_cfg *cfg;
  3788. int phy_ver;
  3789. m_ctrl = &display->ctrl[display->clk_master_idx];
  3790. dsi_ctrl = m_ctrl->ctrl;
  3791. cfg = &(m_ctrl->phy->cfg);
  3792. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3793. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3794. esc_clk_rate_hz);
  3795. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3796. esc_clk_rate_hz);
  3797. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3798. esc_clk_rate_hz);
  3799. hsync_period = dsi_h_total_dce(&mode->timing);
  3800. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3801. if (!display->panel->video_config.eof_bllp_lp11_en)
  3802. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3803. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3804. (display->config.common_config.t_clk_post + 1)) /
  3805. byte_to_esc_ratio) +
  3806. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3807. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3808. ((cfg->timing.lane_v3[3] * 4) +
  3809. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3810. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3811. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3812. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3813. hr_bit_to_esc_ratio);
  3814. delay->pipe_delay2 = 0;
  3815. if (display->panel->host_config.force_hs_clk_lane)
  3816. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3817. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3818. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3819. hr_bit_to_esc_ratio);
  3820. /*
  3821. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3822. * 25us pll delay recommended for phy ver 4.0
  3823. */
  3824. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3825. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3826. delay->pll_delay = 100;
  3827. else
  3828. delay->pll_delay = 25;
  3829. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3830. }
  3831. /*
  3832. * dsi_display_is_type_cphy - check if panel type is cphy
  3833. * @display: Pointer to private display structure
  3834. * Returns: True if panel type is cphy
  3835. */
  3836. static inline bool dsi_display_is_type_cphy(struct dsi_display *display)
  3837. {
  3838. return (display->panel->host_config.phy_type ==
  3839. DSI_PHY_TYPE_CPHY) ? true : false;
  3840. }
  3841. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3842. struct link_clk_freq *bkp_freq)
  3843. {
  3844. int rc = 0, i;
  3845. u8 ctrl_version;
  3846. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3847. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3848. struct dsi_clk_link_set *enable_clk;
  3849. m_ctrl = &display->ctrl[display->clk_master_idx];
  3850. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3851. ctrl_version = m_ctrl->ctrl->version;
  3852. enable_clk = &display->clock_info.pll_clks;
  3853. dsi_clk_prepare_enable(enable_clk);
  3854. dsi_display_phy_configure(display, false);
  3855. display_for_each_ctrl(i, display) {
  3856. ctrl = &display->ctrl[i];
  3857. if (!ctrl->ctrl)
  3858. continue;
  3859. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3860. ctrl->ctrl->clk_freq.byte_clk_rate,
  3861. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3862. if (rc) {
  3863. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3864. goto recover_byte_clk;
  3865. }
  3866. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3867. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3868. if (rc) {
  3869. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3870. goto recover_pix_clk;
  3871. }
  3872. }
  3873. display_for_each_ctrl(i, display) {
  3874. ctrl = &display->ctrl[i];
  3875. if (ctrl == m_ctrl)
  3876. continue;
  3877. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3878. }
  3879. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3880. /*
  3881. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3882. * and with constant fps, as dynamic refresh will applied with
  3883. * next mdp intf ctrl flush.
  3884. */
  3885. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3886. (dyn_clk_caps->maintain_const_fps))
  3887. return 0;
  3888. /* wait for dynamic refresh done */
  3889. display_for_each_ctrl(i, display) {
  3890. ctrl = &display->ctrl[i];
  3891. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3892. if (rc) {
  3893. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3894. goto recover_pix_clk;
  3895. } else {
  3896. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3897. i ? "slave" : "master");
  3898. }
  3899. }
  3900. display_for_each_ctrl(i, display) {
  3901. ctrl = &display->ctrl[i];
  3902. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3903. }
  3904. if (rc)
  3905. DSI_ERR("could not switch back to src clks %d\n", rc);
  3906. dsi_clk_disable_unprepare(enable_clk);
  3907. return rc;
  3908. recover_pix_clk:
  3909. display_for_each_ctrl(i, display) {
  3910. ctrl = &display->ctrl[i];
  3911. if (!ctrl->ctrl)
  3912. continue;
  3913. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3914. bkp_freq->pix_clk_rate, i);
  3915. }
  3916. recover_byte_clk:
  3917. display_for_each_ctrl(i, display) {
  3918. ctrl = &display->ctrl[i];
  3919. if (!ctrl->ctrl)
  3920. continue;
  3921. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3922. bkp_freq->byte_clk_rate,
  3923. bkp_freq->byte_intf_clk_rate, i);
  3924. }
  3925. return rc;
  3926. }
  3927. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3928. struct dsi_display_mode *mode)
  3929. {
  3930. int rc = 0, mask, i;
  3931. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3932. struct dsi_dyn_clk_delay delay;
  3933. struct link_clk_freq bkp_freq;
  3934. dsi_panel_acquire_panel_lock(display->panel);
  3935. m_ctrl = &display->ctrl[display->clk_master_idx];
  3936. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3937. /* mask PLL unlock, FIFO overflow and underflow errors */
  3938. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3939. BIT(DSI_FIFO_OVERFLOW);
  3940. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3941. /* update the phy timings based on new mode */
  3942. display_for_each_ctrl(i, display) {
  3943. ctrl = &display->ctrl[i];
  3944. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3945. }
  3946. /* back up existing rates to handle failure case */
  3947. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3948. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3949. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3950. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3951. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3952. if (rc) {
  3953. DSI_ERR("failed set link frequencies %d\n", rc);
  3954. goto exit;
  3955. }
  3956. /* calculate pipe delays */
  3957. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3958. /* configure dynamic refresh ctrl registers */
  3959. display_for_each_ctrl(i, display) {
  3960. ctrl = &display->ctrl[i];
  3961. if (!ctrl->phy)
  3962. continue;
  3963. if (ctrl == m_ctrl)
  3964. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3965. else
  3966. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3967. false);
  3968. }
  3969. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3970. exit:
  3971. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3972. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3973. DSI_CLK_OFF);
  3974. /* store newly calculated phy timings in mode private info */
  3975. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3976. mode->priv_info->phy_timing_val,
  3977. mode->priv_info->phy_timing_len);
  3978. dsi_panel_release_panel_lock(display->panel);
  3979. return rc;
  3980. }
  3981. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3982. int clk_rate)
  3983. {
  3984. int rc = 0;
  3985. if (clk_rate <= 0) {
  3986. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3987. return -EINVAL;
  3988. }
  3989. if (clk_rate == display->cached_clk_rate) {
  3990. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  3991. return rc;
  3992. }
  3993. display->cached_clk_rate = clk_rate;
  3994. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  3995. if (!rc) {
  3996. DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
  3997. __func__, clk_rate);
  3998. atomic_set(&display->clkrate_change_pending, 1);
  3999. } else {
  4000. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  4001. __func__, clk_rate, rc);
  4002. /* Caching clock failed, so don't go on doing so. */
  4003. atomic_set(&display->clkrate_change_pending, 0);
  4004. display->cached_clk_rate = 0;
  4005. }
  4006. return rc;
  4007. }
  4008. static int dsi_display_dfps_update(struct dsi_display *display,
  4009. struct dsi_display_mode *dsi_mode)
  4010. {
  4011. struct dsi_mode_info *timing;
  4012. struct dsi_display_ctrl *m_ctrl, *ctrl;
  4013. struct dsi_display_mode *panel_mode;
  4014. struct dsi_dfps_capabilities dfps_caps;
  4015. int rc = 0;
  4016. int i = 0;
  4017. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4018. if (!display || !dsi_mode || !display->panel) {
  4019. DSI_ERR("Invalid params\n");
  4020. return -EINVAL;
  4021. }
  4022. timing = &dsi_mode->timing;
  4023. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4024. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4025. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  4026. DSI_ERR("dfps or constant fps not supported\n");
  4027. return -ENOTSUPP;
  4028. }
  4029. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  4030. DSI_ERR("dfps clock method not supported\n");
  4031. return -ENOTSUPP;
  4032. }
  4033. /* For split DSI, update the clock master first */
  4034. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  4035. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  4036. m_ctrl = &display->ctrl[display->clk_master_idx];
  4037. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  4038. if (rc) {
  4039. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  4040. display->name, i, rc);
  4041. goto error;
  4042. }
  4043. /* Update the rest of the controllers */
  4044. display_for_each_ctrl(i, display) {
  4045. ctrl = &display->ctrl[i];
  4046. if (!ctrl->ctrl || (ctrl == m_ctrl))
  4047. continue;
  4048. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  4049. if (rc) {
  4050. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  4051. display->name, i, rc);
  4052. goto error;
  4053. }
  4054. }
  4055. panel_mode = display->panel->cur_mode;
  4056. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  4057. /*
  4058. * dsi_mode_flags flags are used to communicate with other drm driver
  4059. * components, and are transient. They aren't inherently part of the
  4060. * display panel's mode and shouldn't be saved into the cached currently
  4061. * active mode.
  4062. */
  4063. panel_mode->dsi_mode_flags = 0;
  4064. error:
  4065. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  4066. return rc;
  4067. }
  4068. static int dsi_display_dfps_calc_front_porch(
  4069. u32 old_fps,
  4070. u32 new_fps,
  4071. u32 a_total,
  4072. u32 b_total,
  4073. u32 b_fp,
  4074. u32 *b_fp_out)
  4075. {
  4076. s32 b_fp_new;
  4077. int add_porches, diff;
  4078. if (!b_fp_out) {
  4079. DSI_ERR("Invalid params\n");
  4080. return -EINVAL;
  4081. }
  4082. if (!a_total || !new_fps) {
  4083. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  4084. return -EINVAL;
  4085. }
  4086. /*
  4087. * Keep clock, other porches constant, use new fps, calc front porch
  4088. * new_vtotal = old_vtotal * (old_fps / new_fps )
  4089. * new_vfp - old_vfp = new_vtotal - old_vtotal
  4090. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  4091. */
  4092. diff = abs(old_fps - new_fps);
  4093. add_porches = mult_frac(b_total, diff, new_fps);
  4094. if (old_fps > new_fps)
  4095. b_fp_new = b_fp + add_porches;
  4096. else
  4097. b_fp_new = b_fp - add_porches;
  4098. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  4099. new_fps, a_total, b_total, b_fp, b_fp_new);
  4100. if (b_fp_new < 0) {
  4101. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  4102. return -EINVAL;
  4103. }
  4104. /**
  4105. * TODO: To differentiate from clock method when communicating to the
  4106. * other components, perhaps we should set clk here to original value
  4107. */
  4108. *b_fp_out = b_fp_new;
  4109. return 0;
  4110. }
  4111. /**
  4112. * dsi_display_get_dfps_timing() - Get the new dfps values.
  4113. * @display: DSI display handle.
  4114. * @adj_mode: Mode value structure to be changed.
  4115. * It contains old timing values and latest fps value.
  4116. * New timing values are updated based on new fps.
  4117. * @curr_refresh_rate: Current fps rate.
  4118. * If zero , current fps rate is taken from
  4119. * display->panel->cur_mode.
  4120. * Return: error code.
  4121. */
  4122. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  4123. struct dsi_display_mode *adj_mode,
  4124. u32 curr_refresh_rate)
  4125. {
  4126. struct dsi_dfps_capabilities dfps_caps;
  4127. struct dsi_display_mode per_ctrl_mode;
  4128. struct dsi_mode_info *timing;
  4129. struct dsi_ctrl *m_ctrl;
  4130. int rc = 0;
  4131. if (!display || !adj_mode) {
  4132. DSI_ERR("Invalid params\n");
  4133. return -EINVAL;
  4134. }
  4135. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  4136. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4137. if (!dfps_caps.dfps_support) {
  4138. DSI_ERR("dfps not supported by panel\n");
  4139. return -EINVAL;
  4140. }
  4141. per_ctrl_mode = *adj_mode;
  4142. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  4143. if (!curr_refresh_rate) {
  4144. if (!dsi_display_is_seamless_dfps_possible(display,
  4145. &per_ctrl_mode, dfps_caps.type)) {
  4146. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4147. return -EINVAL;
  4148. }
  4149. if (display->panel->cur_mode) {
  4150. curr_refresh_rate =
  4151. display->panel->cur_mode->timing.refresh_rate;
  4152. } else {
  4153. DSI_ERR("cur_mode is not initialized\n");
  4154. return -EINVAL;
  4155. }
  4156. }
  4157. /* TODO: Remove this direct reference to the dsi_ctrl */
  4158. timing = &per_ctrl_mode.timing;
  4159. switch (dfps_caps.type) {
  4160. case DSI_DFPS_IMMEDIATE_VFP:
  4161. rc = dsi_display_dfps_calc_front_porch(
  4162. curr_refresh_rate,
  4163. timing->refresh_rate,
  4164. dsi_h_total_dce(timing),
  4165. DSI_V_TOTAL(timing),
  4166. timing->v_front_porch,
  4167. &adj_mode->timing.v_front_porch);
  4168. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
  4169. curr_refresh_rate, timing->refresh_rate,
  4170. timing->v_front_porch, adj_mode->timing.v_front_porch);
  4171. break;
  4172. case DSI_DFPS_IMMEDIATE_HFP:
  4173. rc = dsi_display_dfps_calc_front_porch(
  4174. curr_refresh_rate,
  4175. timing->refresh_rate,
  4176. DSI_V_TOTAL(timing),
  4177. dsi_h_total_dce(timing),
  4178. timing->h_front_porch,
  4179. &adj_mode->timing.h_front_porch);
  4180. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
  4181. curr_refresh_rate, timing->refresh_rate,
  4182. timing->h_front_porch, adj_mode->timing.h_front_porch);
  4183. if (!rc)
  4184. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4185. break;
  4186. default:
  4187. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4188. rc = -ENOTSUPP;
  4189. }
  4190. return rc;
  4191. }
  4192. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4193. struct dsi_display_mode *adj_mode)
  4194. {
  4195. int rc = 0;
  4196. if (!display || !adj_mode) {
  4197. DSI_ERR("Invalid params\n");
  4198. return false;
  4199. }
  4200. /* Currently the only seamless transition is dynamic fps */
  4201. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4202. if (rc) {
  4203. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4204. } else {
  4205. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4206. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4207. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4208. }
  4209. return rc;
  4210. }
  4211. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4212. struct dsi_display_mode *to_mode)
  4213. {
  4214. u32 cur_fps, to_fps;
  4215. u32 cur_h_active, to_h_active;
  4216. u32 cur_v_active, to_v_active;
  4217. cur_fps = cur_mode->timing.refresh_rate;
  4218. to_fps = to_mode->timing.refresh_rate;
  4219. cur_h_active = cur_mode->timing.h_active;
  4220. cur_v_active = cur_mode->timing.v_active;
  4221. to_h_active = to_mode->timing.h_active;
  4222. to_v_active = to_mode->timing.v_active;
  4223. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4224. (cur_fps != to_fps)) {
  4225. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4226. DSI_DEBUG("DMS Modeset with FPS change\n");
  4227. } else {
  4228. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4229. }
  4230. }
  4231. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4232. struct dsi_display_mode *mode,
  4233. u32 flags)
  4234. {
  4235. int rc = 0, clk_rate = 0;
  4236. int i;
  4237. struct dsi_display_ctrl *ctrl;
  4238. struct dsi_display_ctrl *mctrl;
  4239. struct dsi_display_mode_priv_info *priv_info;
  4240. bool commit_phy_timing = false;
  4241. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4242. priv_info = mode->priv_info;
  4243. if (!priv_info) {
  4244. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4245. display->name);
  4246. return -EINVAL;
  4247. }
  4248. SDE_EVT32(mode->dsi_mode_flags, display->panel->panel_mode);
  4249. if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  4250. display->panel->panel_mode = DSI_OP_VIDEO_MODE;
  4251. else if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  4252. display->panel->panel_mode = DSI_OP_CMD_MODE;
  4253. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4254. mode,
  4255. &display->config);
  4256. if (rc) {
  4257. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4258. display->name, rc);
  4259. goto error;
  4260. }
  4261. memcpy(&display->config.lane_map, &display->lane_map,
  4262. sizeof(display->lane_map));
  4263. mctrl = &display->ctrl[display->clk_master_idx];
  4264. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4265. if (mode->dsi_mode_flags &
  4266. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4267. display_for_each_ctrl(i, display) {
  4268. ctrl = &display->ctrl[i];
  4269. if (!ctrl->ctrl || (ctrl != mctrl))
  4270. continue;
  4271. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4272. true);
  4273. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4274. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4275. (dyn_clk_caps->maintain_const_fps)) {
  4276. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4277. true);
  4278. }
  4279. }
  4280. rc = dsi_display_dfps_update(display, mode);
  4281. if (rc) {
  4282. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4283. display->name, rc);
  4284. goto error;
  4285. }
  4286. display_for_each_ctrl(i, display) {
  4287. ctrl = &display->ctrl[i];
  4288. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4289. &display->config, mode, mode->dsi_mode_flags,
  4290. display->dsi_clk_handle);
  4291. if (rc) {
  4292. DSI_ERR("failed to update ctrl config\n");
  4293. goto error;
  4294. }
  4295. }
  4296. if (priv_info->phy_timing_len) {
  4297. display_for_each_ctrl(i, display) {
  4298. ctrl = &display->ctrl[i];
  4299. rc = dsi_phy_set_timing_params(ctrl->phy,
  4300. priv_info->phy_timing_val,
  4301. priv_info->phy_timing_len,
  4302. commit_phy_timing);
  4303. if (rc)
  4304. DSI_ERR("Fail to add timing params\n");
  4305. }
  4306. }
  4307. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4308. return rc;
  4309. }
  4310. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4311. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4312. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4313. if (rc)
  4314. DSI_ERR("dynamic clk change failed %d\n", rc);
  4315. /*
  4316. * skip rest of the opearations since
  4317. * dsi_display_dynamic_clk_switch_vid() already takes
  4318. * care of them.
  4319. */
  4320. return rc;
  4321. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4322. clk_rate = mode->timing.clk_rate_hz;
  4323. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4324. clk_rate);
  4325. if (rc) {
  4326. DSI_ERR("Failed to configure dynamic clk\n");
  4327. return rc;
  4328. }
  4329. }
  4330. }
  4331. display_for_each_ctrl(i, display) {
  4332. ctrl = &display->ctrl[i];
  4333. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4334. mode, mode->dsi_mode_flags,
  4335. display->dsi_clk_handle);
  4336. if (rc) {
  4337. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4338. display->name, rc);
  4339. goto error;
  4340. }
  4341. }
  4342. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4343. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4344. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4345. u64 to_bitclk = mode->timing.clk_rate_hz;
  4346. commit_phy_timing = true;
  4347. /* No need to set clkrate pending flag if clocks are same */
  4348. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4349. atomic_set(&display->clkrate_change_pending, 1);
  4350. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4351. }
  4352. if (priv_info->phy_timing_len) {
  4353. display_for_each_ctrl(i, display) {
  4354. ctrl = &display->ctrl[i];
  4355. rc = dsi_phy_set_timing_params(ctrl->phy,
  4356. priv_info->phy_timing_val,
  4357. priv_info->phy_timing_len,
  4358. commit_phy_timing);
  4359. if (rc)
  4360. DSI_ERR("failed to add DSI PHY timing params\n");
  4361. }
  4362. }
  4363. error:
  4364. return rc;
  4365. }
  4366. /**
  4367. * _dsi_display_dev_init - initializes the display device
  4368. * Initialization will acquire references to the resources required for the
  4369. * display hardware to function.
  4370. * @display: Handle to the display
  4371. * Returns: Zero on success
  4372. */
  4373. static int _dsi_display_dev_init(struct dsi_display *display)
  4374. {
  4375. int rc = 0;
  4376. if (!display) {
  4377. DSI_ERR("invalid display\n");
  4378. return -EINVAL;
  4379. }
  4380. if (!display->panel_node && !display->fw)
  4381. return 0;
  4382. mutex_lock(&display->display_lock);
  4383. display->parser = dsi_parser_get(&display->pdev->dev);
  4384. if (display->fw && display->parser)
  4385. display->parser_node = dsi_parser_get_head_node(
  4386. display->parser, display->fw->data,
  4387. display->fw->size);
  4388. rc = dsi_display_parse_dt(display);
  4389. if (rc) {
  4390. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4391. goto error;
  4392. }
  4393. rc = dsi_display_res_init(display);
  4394. if (rc) {
  4395. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4396. display->name, rc);
  4397. goto error;
  4398. }
  4399. error:
  4400. mutex_unlock(&display->display_lock);
  4401. return rc;
  4402. }
  4403. /**
  4404. * _dsi_display_dev_deinit - deinitializes the display device
  4405. * All the resources acquired during device init will be released.
  4406. * @display: Handle to the display
  4407. * Returns: Zero on success
  4408. */
  4409. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4410. {
  4411. int rc = 0;
  4412. if (!display) {
  4413. DSI_ERR("invalid display\n");
  4414. return -EINVAL;
  4415. }
  4416. mutex_lock(&display->display_lock);
  4417. rc = dsi_display_res_deinit(display);
  4418. if (rc)
  4419. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4420. display->name, rc);
  4421. mutex_unlock(&display->display_lock);
  4422. return rc;
  4423. }
  4424. /**
  4425. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4426. * @dsi_display: Pointer to dsi display
  4427. * Returns: Zero on success
  4428. */
  4429. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4430. {
  4431. struct dsi_display *display = dsi_display;
  4432. int rc = 0;
  4433. /* Remove the panel vote that was added during dsi display probe */
  4434. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4435. if (rc)
  4436. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4437. display->panel->name, rc);
  4438. return rc;
  4439. }
  4440. /**
  4441. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4442. * @dsi_display: Pointer to dsi display
  4443. * Returns: Zero on success
  4444. */
  4445. int dsi_display_cont_splash_config(void *dsi_display)
  4446. {
  4447. struct dsi_display *display = dsi_display;
  4448. int rc = 0;
  4449. /* Vote for gdsc required to read register address space */
  4450. if (!display) {
  4451. DSI_ERR("invalid input display param\n");
  4452. return -EINVAL;
  4453. }
  4454. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4455. if (rc < 0) {
  4456. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4457. rc);
  4458. return rc;
  4459. }
  4460. mutex_lock(&display->display_lock);
  4461. display->is_cont_splash_enabled = true;
  4462. /* Update splash status for clock manager */
  4463. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4464. display->is_cont_splash_enabled);
  4465. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
  4466. /* Set up ctrl isr before enabling core clk */
  4467. dsi_display_ctrl_isr_configure(display, true);
  4468. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4469. * regulator are inplicit from pre clk on callback
  4470. */
  4471. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4472. DSI_ALL_CLKS, DSI_CLK_ON);
  4473. if (rc) {
  4474. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4475. display->name, rc);
  4476. goto clk_manager_update;
  4477. }
  4478. mutex_unlock(&display->display_lock);
  4479. /* Set the current brightness level */
  4480. dsi_panel_bl_handoff(display->panel);
  4481. return rc;
  4482. clk_manager_update:
  4483. dsi_display_ctrl_isr_configure(display, false);
  4484. /* Update splash status for clock manager */
  4485. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4486. false);
  4487. pm_runtime_put_sync(display->drm_dev->dev);
  4488. display->is_cont_splash_enabled = false;
  4489. mutex_unlock(&display->display_lock);
  4490. return rc;
  4491. }
  4492. /**
  4493. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4494. * @display: Pointer to dsi display
  4495. * Returns: Zero on success
  4496. */
  4497. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4498. {
  4499. int rc = 0;
  4500. if (!display->is_cont_splash_enabled)
  4501. return 0;
  4502. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4503. DSI_ALL_CLKS, DSI_CLK_OFF);
  4504. if (rc)
  4505. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4506. display->name, rc);
  4507. pm_runtime_put_sync(display->drm_dev->dev);
  4508. display->is_cont_splash_enabled = false;
  4509. /* Update splash status for clock manager */
  4510. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4511. display->is_cont_splash_enabled);
  4512. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
  4513. return rc;
  4514. }
  4515. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4516. {
  4517. int rc = 0;
  4518. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4519. if (!rc) {
  4520. DSI_DEBUG("dsi bit clk has been configured to %d\n",
  4521. display->cached_clk_rate);
  4522. atomic_set(&display->clkrate_change_pending, 0);
  4523. } else {
  4524. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4525. display->cached_clk_rate, rc);
  4526. }
  4527. return rc;
  4528. }
  4529. static int dsi_display_validate_split_link(struct dsi_display *display)
  4530. {
  4531. int i, rc = 0;
  4532. struct dsi_display_ctrl *ctrl;
  4533. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4534. if (!host->split_link.enabled)
  4535. return 0;
  4536. display_for_each_ctrl(i, display) {
  4537. ctrl = &display->ctrl[i];
  4538. if (!ctrl->ctrl->split_link_supported) {
  4539. DSI_ERR("[%s] split link is not supported by hw\n",
  4540. display->name);
  4541. rc = -ENOTSUPP;
  4542. goto error;
  4543. }
  4544. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4545. host->split_link.panel_mode = display->panel->panel_mode;
  4546. }
  4547. DSI_DEBUG("Split link is enabled\n");
  4548. return 0;
  4549. error:
  4550. host->split_link.enabled = false;
  4551. return rc;
  4552. }
  4553. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4554. {
  4555. int rc = 0;
  4556. struct dsi_display *display;
  4557. if (!data)
  4558. return -EINVAL;
  4559. rc = dsi_ctrl_get_io_resources(io_res);
  4560. if (rc)
  4561. goto end;
  4562. rc = dsi_phy_get_io_resources(io_res);
  4563. if (rc)
  4564. goto end;
  4565. display = (struct dsi_display *)data;
  4566. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4567. end:
  4568. return rc;
  4569. }
  4570. static int dsi_display_pre_release(void *data)
  4571. {
  4572. struct dsi_display *display;
  4573. if (!data)
  4574. return -EINVAL;
  4575. display = (struct dsi_display *)data;
  4576. mutex_lock(&display->display_lock);
  4577. display->hw_ownership = false;
  4578. mutex_unlock(&display->display_lock);
  4579. dsi_display_ctrl_irq_update(display, false);
  4580. return 0;
  4581. }
  4582. static int dsi_display_pre_acquire(void *data)
  4583. {
  4584. struct dsi_display *display;
  4585. if (!data)
  4586. return -EINVAL;
  4587. display = (struct dsi_display *)data;
  4588. mutex_lock(&display->display_lock);
  4589. display->hw_ownership = true;
  4590. mutex_unlock(&display->display_lock);
  4591. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4592. return 0;
  4593. }
  4594. /**
  4595. * dsi_display_bind - bind dsi device with controlling device
  4596. * @dev: Pointer to base of platform device
  4597. * @master: Pointer to container of drm device
  4598. * @data: Pointer to private data
  4599. * Returns: Zero on success
  4600. */
  4601. static int dsi_display_bind(struct device *dev,
  4602. struct device *master,
  4603. void *data)
  4604. {
  4605. struct dsi_display_ctrl *display_ctrl;
  4606. struct drm_device *drm;
  4607. struct dsi_display *display;
  4608. struct dsi_clk_info info;
  4609. struct clk_ctrl_cb clk_cb;
  4610. void *handle = NULL;
  4611. struct platform_device *pdev = to_platform_device(dev);
  4612. char *client1 = "dsi_clk_client";
  4613. char *client2 = "mdp_event_client";
  4614. struct msm_vm_ops vm_event_ops = {
  4615. .vm_get_io_resources = dsi_display_get_io_resources,
  4616. .vm_pre_hw_release = dsi_display_pre_release,
  4617. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4618. };
  4619. int i, rc = 0;
  4620. if (!dev || !pdev || !master) {
  4621. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4622. dev, pdev, master);
  4623. return -EINVAL;
  4624. }
  4625. drm = dev_get_drvdata(master);
  4626. display = platform_get_drvdata(pdev);
  4627. if (!drm || !display) {
  4628. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4629. drm, display);
  4630. return -EINVAL;
  4631. }
  4632. if (!display->panel_node && !display->fw)
  4633. return 0;
  4634. if (!display->fw)
  4635. display->name = display->panel_node->name;
  4636. /* defer bind if ext bridge driver is not loaded */
  4637. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4638. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4639. if (!of_drm_find_bridge(
  4640. display->ext_bridge[i].node_of)) {
  4641. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4642. display->ext_bridge[i].node_of->full_name);
  4643. return -EPROBE_DEFER;
  4644. }
  4645. }
  4646. }
  4647. mutex_lock(&display->display_lock);
  4648. rc = dsi_display_validate_split_link(display);
  4649. if (rc) {
  4650. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4651. display->name, rc);
  4652. goto error;
  4653. }
  4654. rc = dsi_display_debugfs_init(display);
  4655. if (rc) {
  4656. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4657. goto error;
  4658. }
  4659. atomic_set(&display->clkrate_change_pending, 0);
  4660. display->cached_clk_rate = 0;
  4661. memset(&info, 0x0, sizeof(info));
  4662. display_for_each_ctrl(i, display) {
  4663. display_ctrl = &display->ctrl[i];
  4664. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4665. if (rc) {
  4666. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4667. display->name, i, rc);
  4668. goto error_ctrl_deinit;
  4669. }
  4670. display_ctrl->ctrl->horiz_index = i;
  4671. rc = dsi_phy_drv_init(display_ctrl->phy);
  4672. if (rc) {
  4673. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4674. display->name, i, rc);
  4675. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4676. goto error_ctrl_deinit;
  4677. }
  4678. display_ctrl->ctrl->dma_cmd_workq = display->dma_cmd_workq;
  4679. memcpy(&info.c_clks[i],
  4680. (&display_ctrl->ctrl->clk_info.core_clks),
  4681. sizeof(struct dsi_core_clk_info));
  4682. memcpy(&info.l_hs_clks[i],
  4683. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4684. sizeof(struct dsi_link_hs_clk_info));
  4685. memcpy(&info.l_lp_clks[i],
  4686. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4687. sizeof(struct dsi_link_lp_clk_info));
  4688. info.c_clks[i].drm = drm;
  4689. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4690. }
  4691. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4692. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4693. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4694. info.post_clkon_cb = dsi_post_clkon_cb;
  4695. info.phy_config_cb = dsi_display_phy_configure;
  4696. info.phy_pll_toggle_cb = dsi_display_phy_pll_toggle;
  4697. info.priv_data = display;
  4698. info.master_ndx = display->clk_master_idx;
  4699. info.dsi_ctrl_count = display->ctrl_count;
  4700. snprintf(info.name, MAX_STRING_LEN,
  4701. "DSI_MNGR-%s", display->name);
  4702. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4703. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4704. rc = PTR_ERR(display->clk_mngr);
  4705. display->clk_mngr = NULL;
  4706. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4707. goto error_ctrl_deinit;
  4708. }
  4709. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4710. if (IS_ERR_OR_NULL(handle)) {
  4711. rc = PTR_ERR(handle);
  4712. DSI_ERR("failed to register %s client, rc = %d\n",
  4713. client1, rc);
  4714. goto error_clk_deinit;
  4715. } else {
  4716. display->dsi_clk_handle = handle;
  4717. }
  4718. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4719. if (IS_ERR_OR_NULL(handle)) {
  4720. rc = PTR_ERR(handle);
  4721. DSI_ERR("failed to register %s client, rc = %d\n",
  4722. client2, rc);
  4723. goto error_clk_client_deinit;
  4724. } else {
  4725. display->mdp_clk_handle = handle;
  4726. }
  4727. clk_cb.priv = display;
  4728. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4729. display_for_each_ctrl(i, display) {
  4730. display_ctrl = &display->ctrl[i];
  4731. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4732. if (rc) {
  4733. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4734. display->name, i, rc);
  4735. goto error_ctrl_deinit;
  4736. }
  4737. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4738. if (rc) {
  4739. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4740. display->name, i, rc);
  4741. goto error_ctrl_deinit;
  4742. }
  4743. }
  4744. dsi_display_update_byte_intf_div(display);
  4745. rc = dsi_display_mipi_host_init(display);
  4746. if (rc) {
  4747. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4748. display->name, rc);
  4749. goto error_ctrl_deinit;
  4750. }
  4751. rc = dsi_panel_drv_init(display->panel, &display->host);
  4752. if (rc) {
  4753. if (rc != -EPROBE_DEFER)
  4754. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4755. display->name, rc);
  4756. goto error_host_deinit;
  4757. }
  4758. DSI_INFO("Successfully bind display panel '%s'\n", display->name);
  4759. display->drm_dev = drm;
  4760. display_for_each_ctrl(i, display) {
  4761. display_ctrl = &display->ctrl[i];
  4762. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4763. continue;
  4764. display_ctrl->ctrl->drm_dev = drm;
  4765. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4766. &display_ctrl->ctrl->clk_freq);
  4767. if (rc) {
  4768. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4769. display->name, rc);
  4770. goto error;
  4771. }
  4772. }
  4773. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4774. goto error;
  4775. error_host_deinit:
  4776. (void)dsi_display_mipi_host_deinit(display);
  4777. error_clk_client_deinit:
  4778. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4779. error_clk_deinit:
  4780. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4781. error_ctrl_deinit:
  4782. for (i = i - 1; i >= 0; i--) {
  4783. display_ctrl = &display->ctrl[i];
  4784. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4785. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4786. dsi_ctrl_put(display_ctrl->ctrl);
  4787. dsi_phy_put(display_ctrl->phy);
  4788. }
  4789. (void)dsi_display_debugfs_deinit(display);
  4790. error:
  4791. mutex_unlock(&display->display_lock);
  4792. return rc;
  4793. }
  4794. /**
  4795. * dsi_display_unbind - unbind dsi from controlling device
  4796. * @dev: Pointer to base of platform device
  4797. * @master: Pointer to container of drm device
  4798. * @data: Pointer to private data
  4799. */
  4800. static void dsi_display_unbind(struct device *dev,
  4801. struct device *master, void *data)
  4802. {
  4803. struct dsi_display_ctrl *display_ctrl;
  4804. struct dsi_display *display;
  4805. struct platform_device *pdev = to_platform_device(dev);
  4806. int i, rc = 0;
  4807. if (!dev || !pdev || !master) {
  4808. DSI_ERR("invalid param(s)\n");
  4809. return;
  4810. }
  4811. display = platform_get_drvdata(pdev);
  4812. if (!display || !display->panel_node) {
  4813. DSI_ERR("invalid display\n");
  4814. return;
  4815. }
  4816. mutex_lock(&display->display_lock);
  4817. rc = dsi_display_mipi_host_deinit(display);
  4818. if (rc)
  4819. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4820. display->name,
  4821. rc);
  4822. display_for_each_ctrl(i, display) {
  4823. display_ctrl = &display->ctrl[i];
  4824. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4825. if (rc)
  4826. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4827. display->name, i, rc);
  4828. display->ctrl->ctrl->dma_cmd_workq = NULL;
  4829. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4830. if (rc)
  4831. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4832. display->name, i, rc);
  4833. }
  4834. atomic_set(&display->clkrate_change_pending, 0);
  4835. (void)dsi_display_debugfs_deinit(display);
  4836. mutex_unlock(&display->display_lock);
  4837. }
  4838. static const struct component_ops dsi_display_comp_ops = {
  4839. .bind = dsi_display_bind,
  4840. .unbind = dsi_display_unbind,
  4841. };
  4842. static struct platform_driver dsi_display_driver = {
  4843. .probe = dsi_display_dev_probe,
  4844. .remove = dsi_display_dev_remove,
  4845. .driver = {
  4846. .name = "msm-dsi-display",
  4847. .of_match_table = dsi_display_dt_match,
  4848. .suppress_bind_attrs = true,
  4849. },
  4850. };
  4851. static int dsi_display_init(struct dsi_display *display)
  4852. {
  4853. int rc = 0;
  4854. struct platform_device *pdev = display->pdev;
  4855. mutex_init(&display->display_lock);
  4856. rc = _dsi_display_dev_init(display);
  4857. if (rc) {
  4858. DSI_ERR("device init failed, rc=%d\n", rc);
  4859. goto end;
  4860. }
  4861. /*
  4862. * Vote on panel regulator is added to make sure panel regulators
  4863. * are ON for cont-splash enabled usecase.
  4864. * This panel regulator vote will be removed only in:
  4865. * 1) device suspend when cont-splash is enabled.
  4866. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4867. * For GKI, adding this vote will make sure that sync_state
  4868. * kernel driver doesn't disable the panel regulators after
  4869. * dsi probe is complete.
  4870. */
  4871. if (display->panel) {
  4872. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4873. true);
  4874. if (rc) {
  4875. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4876. display->panel->name, rc);
  4877. return rc;
  4878. }
  4879. }
  4880. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4881. if (rc)
  4882. DSI_ERR("component add failed, rc=%d\n", rc);
  4883. DSI_DEBUG("component add success: %s\n", display->name);
  4884. end:
  4885. return rc;
  4886. }
  4887. static void dsi_display_firmware_display(const struct firmware *fw,
  4888. void *context)
  4889. {
  4890. struct dsi_display *display = context;
  4891. if (fw) {
  4892. DSI_INFO("reading data from firmware, size=%zd\n",
  4893. fw->size);
  4894. display->fw = fw;
  4895. if (!strcmp(display->display_type, "primary"))
  4896. display->name = "dsi_firmware_display";
  4897. else if (!strcmp(display->display_type, "secondary"))
  4898. display->name = "dsi_firmware_display_secondary";
  4899. } else {
  4900. DSI_INFO("no firmware available, fallback to device node\n");
  4901. }
  4902. if (dsi_display_init(display))
  4903. return;
  4904. DSI_DEBUG("success\n");
  4905. }
  4906. int dsi_display_dev_probe(struct platform_device *pdev)
  4907. {
  4908. struct dsi_display *display = NULL;
  4909. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4910. int rc = 0, index = DSI_PRIMARY;
  4911. bool firm_req = false;
  4912. struct dsi_display_boot_param *boot_disp;
  4913. if (!pdev || !pdev->dev.of_node) {
  4914. DSI_ERR("pdev not found\n");
  4915. rc = -ENODEV;
  4916. goto end;
  4917. }
  4918. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4919. if (!display) {
  4920. rc = -ENOMEM;
  4921. goto end;
  4922. }
  4923. display->dma_cmd_workq = create_singlethread_workqueue(
  4924. "dsi_dma_cmd_workq");
  4925. if (!display->dma_cmd_workq) {
  4926. DSI_ERR("failed to create work queue\n");
  4927. rc = -EINVAL;
  4928. goto end;
  4929. }
  4930. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  4931. if (!mdp_node) {
  4932. DSI_ERR("mdp_node not found\n");
  4933. rc = -ENODEV;
  4934. goto end;
  4935. }
  4936. display->trusted_vm_env = of_property_read_bool(mdp_node,
  4937. "qcom,sde-trusted-vm-env");
  4938. if (display->trusted_vm_env)
  4939. DSI_INFO("Display enabled with trusted vm path\n");
  4940. /* initialize panel id to UINT64_MAX */
  4941. display->panel_id = ~0x0;
  4942. display->display_type = of_get_property(pdev->dev.of_node,
  4943. "label", NULL);
  4944. if (!display->display_type)
  4945. display->display_type = "primary";
  4946. if (!strcmp(display->display_type, "secondary"))
  4947. index = DSI_SECONDARY;
  4948. boot_disp = &boot_displays[index];
  4949. node = pdev->dev.of_node;
  4950. if (boot_disp->boot_disp_en) {
  4951. /* The panel name should be same as UEFI name index */
  4952. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4953. if (!panel_node)
  4954. DSI_WARN("panel_node %s not found\n", boot_disp->name);
  4955. } else {
  4956. panel_node = of_parse_phandle(node,
  4957. "qcom,dsi-default-panel", 0);
  4958. if (!panel_node)
  4959. DSI_WARN("default panel not found\n");
  4960. }
  4961. boot_disp->node = pdev->dev.of_node;
  4962. boot_disp->disp = display;
  4963. display->panel_node = panel_node;
  4964. display->pdev = pdev;
  4965. display->boot_disp = boot_disp;
  4966. dsi_display_parse_cmdline_topology(display, index);
  4967. platform_set_drvdata(pdev, display);
  4968. if (!dsi_display_validate_res(display)) {
  4969. rc = -EPROBE_DEFER;
  4970. DSI_ERR("resources required for display probe not present: rc=%d\n", rc);
  4971. goto end;
  4972. }
  4973. /* initialize display in firmware callback */
  4974. if (!(boot_displays[DSI_PRIMARY].boot_disp_en ||
  4975. boot_displays[DSI_SECONDARY].boot_disp_en) &&
  4976. IS_ENABLED(CONFIG_DSI_PARSER)) {
  4977. if (!strcmp(display->display_type, "primary"))
  4978. firm_req = !request_firmware_nowait(
  4979. THIS_MODULE, 1, "dsi_prop",
  4980. &pdev->dev, GFP_KERNEL, display,
  4981. dsi_display_firmware_display);
  4982. else if (!strcmp(display->display_type, "secondary"))
  4983. firm_req = !request_firmware_nowait(
  4984. THIS_MODULE, 1, "dsi_prop_sec",
  4985. &pdev->dev, GFP_KERNEL, display,
  4986. dsi_display_firmware_display);
  4987. }
  4988. if (!firm_req) {
  4989. rc = dsi_display_init(display);
  4990. if (rc)
  4991. goto end;
  4992. }
  4993. return 0;
  4994. end:
  4995. if (display)
  4996. devm_kfree(&pdev->dev, display);
  4997. return rc;
  4998. }
  4999. int dsi_display_dev_remove(struct platform_device *pdev)
  5000. {
  5001. int rc = 0, i = 0;
  5002. struct dsi_display *display;
  5003. struct dsi_display_ctrl *ctrl;
  5004. if (!pdev) {
  5005. DSI_ERR("Invalid device\n");
  5006. return -EINVAL;
  5007. }
  5008. display = platform_get_drvdata(pdev);
  5009. /* decrement ref count */
  5010. of_node_put(display->panel_node);
  5011. if (display->dma_cmd_workq) {
  5012. flush_workqueue(display->dma_cmd_workq);
  5013. destroy_workqueue(display->dma_cmd_workq);
  5014. display->dma_cmd_workq = NULL;
  5015. display_for_each_ctrl(i, display) {
  5016. ctrl = &display->ctrl[i];
  5017. if (!ctrl->ctrl)
  5018. continue;
  5019. ctrl->ctrl->dma_cmd_workq = NULL;
  5020. }
  5021. }
  5022. (void)_dsi_display_dev_deinit(display);
  5023. platform_set_drvdata(pdev, NULL);
  5024. devm_kfree(&pdev->dev, display);
  5025. return rc;
  5026. }
  5027. int dsi_display_get_num_of_displays(void)
  5028. {
  5029. int i, count = 0;
  5030. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  5031. struct dsi_display *display = boot_displays[i].disp;
  5032. if ((display && display->panel_node) ||
  5033. (display && display->fw))
  5034. count++;
  5035. }
  5036. return count;
  5037. }
  5038. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  5039. {
  5040. int index = 0, count = 0;
  5041. if (!display_array || !max_display_count) {
  5042. DSI_ERR("invalid params\n");
  5043. return 0;
  5044. }
  5045. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  5046. struct dsi_display *display = boot_displays[index].disp;
  5047. if ((display && display->panel_node) ||
  5048. (display && display->fw))
  5049. display_array[count++] = display;
  5050. }
  5051. return count;
  5052. }
  5053. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  5054. {
  5055. if (!display)
  5056. return;
  5057. mutex_lock(&display->display_lock);
  5058. display->is_active = is_active;
  5059. mutex_unlock(&display->display_lock);
  5060. }
  5061. int dsi_display_drm_bridge_init(struct dsi_display *display,
  5062. struct drm_encoder *enc)
  5063. {
  5064. int rc = 0;
  5065. struct dsi_bridge *bridge;
  5066. struct msm_drm_private *priv = NULL;
  5067. if (!display || !display->drm_dev || !enc) {
  5068. DSI_ERR("invalid param(s)\n");
  5069. return -EINVAL;
  5070. }
  5071. mutex_lock(&display->display_lock);
  5072. priv = display->drm_dev->dev_private;
  5073. if (!priv) {
  5074. DSI_ERR("Private data is not present\n");
  5075. rc = -EINVAL;
  5076. goto error;
  5077. }
  5078. if (display->bridge) {
  5079. DSI_ERR("display is already initialize\n");
  5080. goto error;
  5081. }
  5082. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  5083. if (IS_ERR_OR_NULL(bridge)) {
  5084. rc = PTR_ERR(bridge);
  5085. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  5086. goto error;
  5087. }
  5088. display->bridge = bridge;
  5089. priv->bridges[priv->num_bridges++] = &bridge->base;
  5090. if (display->tx_cmd_buf == NULL) {
  5091. rc = dsi_host_alloc_cmd_tx_buffer(display);
  5092. if (rc)
  5093. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  5094. }
  5095. error:
  5096. mutex_unlock(&display->display_lock);
  5097. return rc;
  5098. }
  5099. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  5100. {
  5101. int rc = 0;
  5102. if (!display) {
  5103. DSI_ERR("Invalid params\n");
  5104. return -EINVAL;
  5105. }
  5106. mutex_lock(&display->display_lock);
  5107. dsi_drm_bridge_cleanup(display->bridge);
  5108. display->bridge = NULL;
  5109. mutex_unlock(&display->display_lock);
  5110. return rc;
  5111. }
  5112. /* Hook functions to call external connector, pointer validation is
  5113. * done in dsi_display_drm_ext_bridge_init.
  5114. */
  5115. static enum drm_connector_status dsi_display_drm_ext_detect(
  5116. struct drm_connector *connector,
  5117. bool force,
  5118. void *disp)
  5119. {
  5120. struct dsi_display *display = disp;
  5121. return display->ext_conn->funcs->detect(display->ext_conn, force);
  5122. }
  5123. static int dsi_display_drm_ext_get_modes(
  5124. struct drm_connector *connector, void *disp,
  5125. const struct msm_resource_caps_info *avail_res)
  5126. {
  5127. struct dsi_display *display = disp;
  5128. struct drm_display_mode *pmode, *pt;
  5129. int count;
  5130. /* if there are modes defined in panel, ignore external modes */
  5131. if (display->panel->num_timing_nodes)
  5132. return dsi_connector_get_modes(connector, disp, avail_res);
  5133. count = display->ext_conn->helper_private->get_modes(
  5134. display->ext_conn);
  5135. list_for_each_entry_safe(pmode, pt,
  5136. &display->ext_conn->probed_modes, head) {
  5137. list_move_tail(&pmode->head, &connector->probed_modes);
  5138. }
  5139. connector->display_info = display->ext_conn->display_info;
  5140. return count;
  5141. }
  5142. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  5143. struct drm_connector *connector,
  5144. struct drm_display_mode *mode,
  5145. void *disp, const struct msm_resource_caps_info *avail_res)
  5146. {
  5147. struct dsi_display *display = disp;
  5148. enum drm_mode_status status;
  5149. /* always do internal mode_valid check */
  5150. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  5151. if (status != MODE_OK)
  5152. return status;
  5153. return display->ext_conn->helper_private->mode_valid(
  5154. display->ext_conn, mode);
  5155. }
  5156. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  5157. void *disp,
  5158. struct drm_atomic_state *state)
  5159. {
  5160. struct dsi_display *display = disp;
  5161. struct drm_connector_state *c_state;
  5162. c_state = drm_atomic_get_new_connector_state(state, connector);
  5163. return display->ext_conn->helper_private->atomic_check(
  5164. display->ext_conn, state);
  5165. }
  5166. static int dsi_display_ext_get_info(struct drm_connector *connector,
  5167. struct msm_display_info *info, void *disp)
  5168. {
  5169. struct dsi_display *display;
  5170. int i;
  5171. if (!info || !disp) {
  5172. DSI_ERR("invalid params\n");
  5173. return -EINVAL;
  5174. }
  5175. display = disp;
  5176. if (!display->panel) {
  5177. DSI_ERR("invalid display panel\n");
  5178. return -EINVAL;
  5179. }
  5180. mutex_lock(&display->display_lock);
  5181. memset(info, 0, sizeof(struct msm_display_info));
  5182. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5183. info->num_of_h_tiles = display->ctrl_count;
  5184. for (i = 0; i < info->num_of_h_tiles; i++)
  5185. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5186. info->is_connected = connector->status != connector_status_disconnected;
  5187. if (!strcmp(display->display_type, "primary"))
  5188. info->display_type = SDE_CONNECTOR_PRIMARY;
  5189. else if (!strcmp(display->display_type, "secondary"))
  5190. info->display_type = SDE_CONNECTOR_SECONDARY;
  5191. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5192. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5193. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5194. mutex_unlock(&display->display_lock);
  5195. return 0;
  5196. }
  5197. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5198. const struct drm_display_mode *drm_mode,
  5199. struct msm_mode_info *mode_info,
  5200. void *display, const struct msm_resource_caps_info *avail_res)
  5201. {
  5202. struct msm_display_topology *topology;
  5203. if (!drm_mode || !mode_info ||
  5204. !avail_res || !avail_res->max_mixer_width)
  5205. return -EINVAL;
  5206. memset(mode_info, 0, sizeof(*mode_info));
  5207. mode_info->frame_rate = drm_mode_vrefresh(drm_mode);
  5208. mode_info->vtotal = drm_mode->vtotal;
  5209. topology = &mode_info->topology;
  5210. topology->num_lm = (avail_res->max_mixer_width
  5211. <= drm_mode->hdisplay) ? 2 : 1;
  5212. topology->num_enc = 0;
  5213. topology->num_intf = topology->num_lm;
  5214. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5215. return 0;
  5216. }
  5217. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5218. struct drm_bridge *bridge)
  5219. {
  5220. struct msm_drm_private *priv;
  5221. struct sde_kms *sde_kms;
  5222. struct drm_connector *conn;
  5223. struct drm_connector_list_iter conn_iter;
  5224. struct sde_connector *sde_conn;
  5225. struct dsi_display *display;
  5226. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5227. int i;
  5228. if (!bridge || !bridge->encoder) {
  5229. SDE_ERROR("invalid argument\n");
  5230. return NULL;
  5231. }
  5232. priv = bridge->dev->dev_private;
  5233. sde_kms = to_sde_kms(priv->kms);
  5234. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5235. drm_for_each_connector_iter(conn, &conn_iter) {
  5236. sde_conn = to_sde_connector(conn);
  5237. if (sde_conn->encoder == bridge->encoder) {
  5238. display = sde_conn->display;
  5239. display_for_each_ctrl(i, display) {
  5240. if (display->ext_bridge[i].bridge == bridge) {
  5241. dsi_bridge = &display->ext_bridge[i];
  5242. break;
  5243. }
  5244. }
  5245. }
  5246. }
  5247. drm_connector_list_iter_end(&conn_iter);
  5248. return dsi_bridge;
  5249. }
  5250. static void dsi_display_drm_ext_adjust_timing(
  5251. const struct dsi_display *display,
  5252. struct drm_display_mode *mode)
  5253. {
  5254. mode->hdisplay /= display->ctrl_count;
  5255. mode->hsync_start /= display->ctrl_count;
  5256. mode->hsync_end /= display->ctrl_count;
  5257. mode->htotal /= display->ctrl_count;
  5258. mode->hskew /= display->ctrl_count;
  5259. mode->clock /= display->ctrl_count;
  5260. }
  5261. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5262. struct drm_bridge *bridge,
  5263. const struct drm_display_info *info,
  5264. const struct drm_display_mode *mode)
  5265. {
  5266. struct dsi_display_ext_bridge *ext_bridge;
  5267. struct drm_display_mode tmp;
  5268. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5269. if (!ext_bridge)
  5270. return MODE_ERROR;
  5271. tmp = *mode;
  5272. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5273. return ext_bridge->orig_funcs->mode_valid(bridge, info, &tmp);
  5274. }
  5275. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5276. struct drm_bridge *bridge,
  5277. const struct drm_display_mode *mode,
  5278. struct drm_display_mode *adjusted_mode)
  5279. {
  5280. struct dsi_display_ext_bridge *ext_bridge;
  5281. struct drm_display_mode tmp;
  5282. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5283. if (!ext_bridge)
  5284. return false;
  5285. tmp = *mode;
  5286. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5287. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5288. }
  5289. static void dsi_display_drm_ext_bridge_mode_set(
  5290. struct drm_bridge *bridge,
  5291. const struct drm_display_mode *mode,
  5292. const struct drm_display_mode *adjusted_mode)
  5293. {
  5294. struct dsi_display_ext_bridge *ext_bridge;
  5295. struct drm_display_mode tmp;
  5296. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5297. if (!ext_bridge)
  5298. return;
  5299. tmp = *mode;
  5300. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5301. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5302. }
  5303. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5304. struct mipi_dsi_device *dsi)
  5305. {
  5306. struct dsi_display *display = to_dsi_display(host);
  5307. struct dsi_panel *panel;
  5308. if (!host || !dsi || !display->panel) {
  5309. DSI_ERR("Invalid param\n");
  5310. return -EINVAL;
  5311. }
  5312. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5313. dsi->name, dsi->channel, dsi->lanes,
  5314. dsi->format, dsi->mode_flags);
  5315. panel = display->panel;
  5316. panel->host_config.data_lanes = 0;
  5317. if (dsi->lanes > 0)
  5318. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5319. if (dsi->lanes > 1)
  5320. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5321. if (dsi->lanes > 2)
  5322. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5323. if (dsi->lanes > 3)
  5324. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5325. switch (dsi->format) {
  5326. case MIPI_DSI_FMT_RGB888:
  5327. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5328. break;
  5329. case MIPI_DSI_FMT_RGB666:
  5330. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5331. break;
  5332. case MIPI_DSI_FMT_RGB666_PACKED:
  5333. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5334. break;
  5335. case MIPI_DSI_FMT_RGB565:
  5336. default:
  5337. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5338. break;
  5339. }
  5340. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5341. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5342. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5343. panel->video_config.traffic_mode =
  5344. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5345. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5346. panel->video_config.traffic_mode =
  5347. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5348. else
  5349. panel->video_config.traffic_mode =
  5350. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5351. panel->video_config.hsa_lp11_en =
  5352. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5353. panel->video_config.hbp_lp11_en =
  5354. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5355. panel->video_config.hfp_lp11_en =
  5356. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5357. panel->video_config.pulse_mode_hsa_he =
  5358. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5359. } else {
  5360. panel->panel_mode = DSI_OP_CMD_MODE;
  5361. DSI_ERR("command mode not supported by ext bridge\n");
  5362. return -ENOTSUPP;
  5363. }
  5364. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5365. return 0;
  5366. }
  5367. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5368. .attach = dsi_host_ext_attach,
  5369. .detach = dsi_host_detach,
  5370. .transfer = dsi_host_transfer,
  5371. };
  5372. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5373. {
  5374. if (!display || !display->panel) {
  5375. pr_err("invalid param(s)\n");
  5376. return NULL;
  5377. }
  5378. return &display->panel->drm_panel;
  5379. }
  5380. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5381. struct drm_encoder *encoder, struct drm_connector *connector)
  5382. {
  5383. struct drm_device *drm;
  5384. struct drm_bridge *bridge;
  5385. struct drm_bridge *ext_bridge;
  5386. struct drm_connector *ext_conn;
  5387. struct sde_connector *sde_conn;
  5388. struct drm_bridge *prev_bridge;
  5389. int rc = 0, i;
  5390. if (!display || !encoder || !connector)
  5391. return -EINVAL;
  5392. drm = encoder->dev;
  5393. bridge = drm_bridge_chain_get_first_bridge(encoder);
  5394. sde_conn = to_sde_connector(connector);
  5395. prev_bridge = bridge;
  5396. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5397. return 0;
  5398. if (!bridge)
  5399. return -EINVAL;
  5400. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5401. struct dsi_display_ext_bridge *ext_bridge_info =
  5402. &display->ext_bridge[i];
  5403. struct drm_encoder *c_encoder;
  5404. /* return if ext bridge is already initialized */
  5405. if (ext_bridge_info->bridge)
  5406. return 0;
  5407. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5408. if (IS_ERR_OR_NULL(ext_bridge)) {
  5409. rc = PTR_ERR(ext_bridge);
  5410. DSI_ERR("failed to find ext bridge\n");
  5411. goto error;
  5412. }
  5413. /* override functions for mode adjustment */
  5414. if (display->ext_bridge_cnt > 1) {
  5415. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5416. if (ext_bridge->funcs->mode_fixup)
  5417. ext_bridge_info->bridge_funcs.mode_fixup =
  5418. dsi_display_drm_ext_bridge_mode_fixup;
  5419. if (ext_bridge->funcs->mode_valid)
  5420. ext_bridge_info->bridge_funcs.mode_valid =
  5421. dsi_display_drm_ext_bridge_mode_valid;
  5422. if (ext_bridge->funcs->mode_set)
  5423. ext_bridge_info->bridge_funcs.mode_set =
  5424. dsi_display_drm_ext_bridge_mode_set;
  5425. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5426. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5427. }
  5428. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge, 0);
  5429. if (rc) {
  5430. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5431. display->name, rc);
  5432. goto error;
  5433. }
  5434. ext_bridge_info->display = display;
  5435. ext_bridge_info->bridge = ext_bridge;
  5436. prev_bridge = ext_bridge;
  5437. /* ext bridge will init its own connector during attach,
  5438. * we need to extract it out of the connector list
  5439. */
  5440. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5441. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5442. struct drm_connector, head);
  5443. if (!ext_conn) {
  5444. DSI_ERR("failed to get external connector\n");
  5445. rc = PTR_ERR(ext_conn);
  5446. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5447. goto error;
  5448. }
  5449. drm_connector_for_each_possible_encoder(ext_conn, c_encoder)
  5450. break;
  5451. if (!c_encoder) {
  5452. DSI_ERR("failed to get encoder\n");
  5453. rc = PTR_ERR(c_encoder);
  5454. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5455. goto error;
  5456. }
  5457. if (ext_conn && ext_conn != connector &&
  5458. c_encoder->base.id == bridge->encoder->base.id) {
  5459. list_del_init(&ext_conn->head);
  5460. display->ext_conn = ext_conn;
  5461. }
  5462. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5463. /* if there is no valid external connector created, or in split
  5464. * mode, default setting is used from panel defined in DT file.
  5465. */
  5466. if (!display->ext_conn ||
  5467. !display->ext_conn->funcs ||
  5468. !display->ext_conn->helper_private ||
  5469. display->ext_bridge_cnt > 1) {
  5470. display->ext_conn = NULL;
  5471. continue;
  5472. }
  5473. /* otherwise, hook up the functions to use external connector */
  5474. if (display->ext_conn->funcs->detect)
  5475. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5476. if (display->ext_conn->helper_private->get_modes)
  5477. sde_conn->ops.get_modes =
  5478. dsi_display_drm_ext_get_modes;
  5479. if (display->ext_conn->helper_private->mode_valid)
  5480. sde_conn->ops.mode_valid =
  5481. dsi_display_drm_ext_mode_valid;
  5482. if (display->ext_conn->helper_private->atomic_check)
  5483. sde_conn->ops.atomic_check =
  5484. dsi_display_drm_ext_atomic_check;
  5485. sde_conn->ops.get_info =
  5486. dsi_display_ext_get_info;
  5487. sde_conn->ops.get_mode_info =
  5488. dsi_display_ext_get_mode_info;
  5489. /* add support to attach/detach */
  5490. display->host.ops = &dsi_host_ext_ops;
  5491. }
  5492. return 0;
  5493. error:
  5494. return rc;
  5495. }
  5496. int dsi_display_get_info(struct drm_connector *connector,
  5497. struct msm_display_info *info, void *disp)
  5498. {
  5499. struct dsi_display *display;
  5500. struct dsi_panel_phy_props phy_props;
  5501. struct dsi_host_common_cfg *host;
  5502. int i, rc;
  5503. if (!info || !disp) {
  5504. DSI_ERR("invalid params\n");
  5505. return -EINVAL;
  5506. }
  5507. display = disp;
  5508. if (!display->panel) {
  5509. DSI_ERR("invalid display panel\n");
  5510. return -EINVAL;
  5511. }
  5512. mutex_lock(&display->display_lock);
  5513. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5514. if (rc) {
  5515. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5516. display->name, rc);
  5517. goto error;
  5518. }
  5519. memset(info, 0, sizeof(struct msm_display_info));
  5520. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5521. info->num_of_h_tiles = display->ctrl_count;
  5522. for (i = 0; i < info->num_of_h_tiles; i++)
  5523. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5524. info->is_connected = display->is_active;
  5525. if (!strcmp(display->display_type, "primary"))
  5526. info->display_type = SDE_CONNECTOR_PRIMARY;
  5527. else if (!strcmp(display->display_type, "secondary"))
  5528. info->display_type = SDE_CONNECTOR_SECONDARY;
  5529. info->width_mm = phy_props.panel_width_mm;
  5530. info->height_mm = phy_props.panel_height_mm;
  5531. info->max_width = 1920;
  5532. info->max_height = 1080;
  5533. info->qsync_min_fps = display->panel->qsync_caps.qsync_min_fps;
  5534. info->has_qsync_min_fps_list = (display->panel->qsync_caps.qsync_min_fps_list_len > 0);
  5535. info->has_avr_step_req = (display->panel->avr_caps.avr_step_fps_list_len > 0);
  5536. info->poms_align_vsync = display->panel->poms_align_vsync;
  5537. switch (display->panel->panel_mode) {
  5538. case DSI_OP_VIDEO_MODE:
  5539. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5540. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5541. if (display->panel->panel_mode_switch_enabled)
  5542. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5543. break;
  5544. case DSI_OP_CMD_MODE:
  5545. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5546. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5547. if (display->panel->panel_mode_switch_enabled)
  5548. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5549. info->is_te_using_watchdog_timer =
  5550. display->panel->te_using_watchdog_timer |
  5551. display->sw_te_using_wd;
  5552. break;
  5553. default:
  5554. DSI_ERR("unknwown dsi panel mode %d\n",
  5555. display->panel->panel_mode);
  5556. break;
  5557. }
  5558. if (display->panel->esd_config.esd_enabled &&
  5559. !display->sw_te_using_wd)
  5560. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5561. info->te_source = display->te_source;
  5562. host = &display->panel->host_config;
  5563. if (host->split_link.enabled)
  5564. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5565. info->dsc_count = display->panel->dsc_count;
  5566. info->lm_count = display->panel->lm_count;
  5567. error:
  5568. mutex_unlock(&display->display_lock);
  5569. return rc;
  5570. }
  5571. int dsi_display_get_mode_count(struct dsi_display *display,
  5572. u32 *count)
  5573. {
  5574. if (!display || !display->panel) {
  5575. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5576. display ? display->panel != NULL : 0);
  5577. return -EINVAL;
  5578. }
  5579. mutex_lock(&display->display_lock);
  5580. *count = display->panel->num_display_modes;
  5581. mutex_unlock(&display->display_lock);
  5582. return 0;
  5583. }
  5584. void dsi_display_adjust_mode_timing(struct dsi_display *display,
  5585. struct dsi_display_mode *dsi_mode,
  5586. int lanes, int bpp)
  5587. {
  5588. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5589. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5590. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  5591. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5592. /* Constant FPS is not supported on command mode */
  5593. if (!(dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE))
  5594. return;
  5595. if (!dyn_clk_caps->maintain_const_fps)
  5596. return;
  5597. /*
  5598. * When there is a dynamic clock switch, there is small change
  5599. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5600. * is adjusted. It has been assumed that the refined porch values
  5601. * are supported by the panel. This logic can be enhanced further
  5602. * in future by taking min/max porches supported by the panel.
  5603. */
  5604. switch (dyn_clk_caps->type) {
  5605. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5606. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5607. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5608. do_div(old_htotal, display->ctrl_count);
  5609. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5610. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5611. if (dsi_display_is_type_cphy(display)) {
  5612. new_htotal = new_htotal * bits_per_symbol;
  5613. div = div * num_of_symbols;
  5614. }
  5615. do_div(new_htotal, div);
  5616. if (old_htotal > new_htotal)
  5617. dsi_mode->timing.h_front_porch -=
  5618. ((old_htotal - new_htotal) * display->ctrl_count);
  5619. else
  5620. dsi_mode->timing.h_front_porch +=
  5621. ((new_htotal - old_htotal) * display->ctrl_count);
  5622. break;
  5623. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5624. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5625. do_div(htotal, display->ctrl_count);
  5626. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5627. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5628. if (dsi_display_is_type_cphy(display)) {
  5629. new_vtotal = new_vtotal * bits_per_symbol;
  5630. div = div * num_of_symbols;
  5631. }
  5632. do_div(new_vtotal, div);
  5633. dsi_mode->timing.v_front_porch = new_vtotal -
  5634. dsi_mode->timing.v_back_porch -
  5635. dsi_mode->timing.v_sync_width -
  5636. dsi_mode->timing.v_active;
  5637. break;
  5638. default:
  5639. break;
  5640. }
  5641. }
  5642. static void _dsi_display_populate_bit_clks(struct dsi_display *display, int start, int end)
  5643. {
  5644. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5645. struct dsi_display_mode *src;
  5646. struct dsi_host_common_cfg *cfg;
  5647. int i, bpp, lanes = 0;
  5648. if (!display)
  5649. return;
  5650. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5651. if (!dyn_clk_caps->dyn_clk_support)
  5652. return;
  5653. cfg = &(display->panel->host_config);
  5654. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5655. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5656. lanes++;
  5657. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5658. lanes++;
  5659. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5660. lanes++;
  5661. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5662. lanes++;
  5663. for (i = start; i < end; i++) {
  5664. src = &display->modes[i];
  5665. if (!src)
  5666. return;
  5667. if (!src->priv_info->bit_clk_list.count)
  5668. continue;
  5669. src->timing.clk_rate_hz = src->priv_info->bit_clk_list.rates[0];
  5670. dsi_display_adjust_mode_timing(display, src, lanes, bpp);
  5671. src->pixel_clk_khz = div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5672. src->pixel_clk_khz /= 1000;
  5673. src->pixel_clk_khz *= display->ctrl_count;
  5674. }
  5675. }
  5676. int dsi_display_restore_bit_clk(struct dsi_display *display, struct dsi_display_mode *mode)
  5677. {
  5678. int i;
  5679. u32 clk_rate_hz = 0;
  5680. if (!display || !mode || !mode->priv_info) {
  5681. DSI_ERR("invalid arguments\n");
  5682. return -EINVAL;
  5683. }
  5684. clk_rate_hz = display->cached_clk_rate;
  5685. if (mode->priv_info->bit_clk_list.count) {
  5686. /* use first entry as the default bit clk rate */
  5687. clk_rate_hz = mode->priv_info->bit_clk_list.rates[0];
  5688. for (i = 0; i < mode->priv_info->bit_clk_list.count; i++) {
  5689. if (display->dyn_bit_clk == mode->priv_info->bit_clk_list.rates[i])
  5690. clk_rate_hz = display->dyn_bit_clk;
  5691. }
  5692. }
  5693. mode->timing.clk_rate_hz = clk_rate_hz;
  5694. mode->priv_info->clk_rate_hz = clk_rate_hz;
  5695. SDE_EVT32(clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5696. DSI_DEBUG("clk_rate_hz:%u, cached_clk_rate:%u, dyn_bit_clk:%u\n",
  5697. clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5698. return 0;
  5699. }
  5700. void dsi_display_put_mode(struct dsi_display *display,
  5701. struct dsi_display_mode *mode)
  5702. {
  5703. dsi_panel_put_mode(mode);
  5704. }
  5705. int dsi_display_get_modes(struct dsi_display *display,
  5706. struct dsi_display_mode **out_modes)
  5707. {
  5708. struct dsi_dfps_capabilities dfps_caps;
  5709. struct dsi_display_ctrl *ctrl;
  5710. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5711. bool is_split_link, support_cmd_mode, support_video_mode;
  5712. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5713. u32 sublinks_count, mode_idx, array_idx = 0;
  5714. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5715. int i, start, end, rc = -EINVAL;
  5716. if (!display || !out_modes) {
  5717. DSI_ERR("Invalid params\n");
  5718. return -EINVAL;
  5719. }
  5720. *out_modes = NULL;
  5721. ctrl = &display->ctrl[0];
  5722. mutex_lock(&display->display_lock);
  5723. if (display->modes)
  5724. goto exit;
  5725. display_mode_count = display->panel->num_display_modes;
  5726. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5727. GFP_KERNEL);
  5728. if (!display->modes) {
  5729. rc = -ENOMEM;
  5730. goto error;
  5731. }
  5732. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5733. if (rc) {
  5734. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5735. display->name);
  5736. goto error;
  5737. }
  5738. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5739. timing_mode_count = display->panel->num_timing_nodes;
  5740. /* Validate command line timing */
  5741. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5742. (display->cmdline_timing >= timing_mode_count))
  5743. display->cmdline_timing = NO_OVERRIDE;
  5744. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5745. struct dsi_display_mode display_mode;
  5746. int topology_override = NO_OVERRIDE;
  5747. bool is_preferred = false;
  5748. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5749. memset(&display_mode, 0, sizeof(display_mode));
  5750. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5751. &display_mode,
  5752. topology_override);
  5753. if (rc) {
  5754. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5755. display->name, mode_idx);
  5756. goto error;
  5757. }
  5758. if (display->cmdline_timing == display_mode.mode_idx) {
  5759. topology_override = display->cmdline_topology;
  5760. is_preferred = true;
  5761. }
  5762. support_cmd_mode = display_mode.panel_mode_caps & DSI_OP_CMD_MODE;
  5763. support_video_mode = display_mode.panel_mode_caps & DSI_OP_VIDEO_MODE;
  5764. /* Setup widebus support */
  5765. display_mode.priv_info->widebus_support =
  5766. ctrl->ctrl->hw.widebus_support;
  5767. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5768. !support_video_mode) ? 1 : dfps_caps.dfps_list_len);
  5769. /* Calculate dsi frame transfer time */
  5770. if (support_cmd_mode) {
  5771. dsi_panel_calc_dsi_transfer_time(
  5772. &display->panel->host_config,
  5773. &display_mode, frame_threshold_us);
  5774. display_mode.priv_info->dsi_transfer_time_us =
  5775. display_mode.timing.dsi_transfer_time_us;
  5776. display_mode.priv_info->min_dsi_clk_hz =
  5777. display_mode.timing.min_dsi_clk_hz;
  5778. display_mode.priv_info->mdp_transfer_time_us =
  5779. display_mode.timing.mdp_transfer_time_us;
  5780. }
  5781. is_split_link = host->split_link.enabled;
  5782. sublinks_count = host->split_link.num_sublinks;
  5783. if (is_split_link && sublinks_count > 1) {
  5784. display_mode.timing.h_active *= sublinks_count;
  5785. display_mode.timing.h_front_porch *= sublinks_count;
  5786. display_mode.timing.h_sync_width *= sublinks_count;
  5787. display_mode.timing.h_back_porch *= sublinks_count;
  5788. display_mode.timing.h_skew *= sublinks_count;
  5789. display_mode.pixel_clk_khz *= sublinks_count;
  5790. } else {
  5791. display_mode.timing.h_active *= display->ctrl_count;
  5792. display_mode.timing.h_front_porch *=
  5793. display->ctrl_count;
  5794. display_mode.timing.h_sync_width *=
  5795. display->ctrl_count;
  5796. display_mode.timing.h_back_porch *=
  5797. display->ctrl_count;
  5798. display_mode.timing.h_skew *= display->ctrl_count;
  5799. display_mode.pixel_clk_khz *= display->ctrl_count;
  5800. }
  5801. start = array_idx;
  5802. for (i = 0; i < num_dfps_rates; i++) {
  5803. struct dsi_display_mode *sub_mode =
  5804. &display->modes[array_idx];
  5805. u32 curr_refresh_rate;
  5806. if (!sub_mode) {
  5807. DSI_ERR("invalid mode data\n");
  5808. rc = -EFAULT;
  5809. goto error;
  5810. }
  5811. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5812. array_idx++;
  5813. if (!dfps_caps.dfps_support || !support_video_mode)
  5814. continue;
  5815. sub_mode->mode_idx += (array_idx - 1);
  5816. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5817. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5818. dsi_display_get_dfps_timing(display, sub_mode,
  5819. curr_refresh_rate);
  5820. sub_mode->panel_mode_caps = DSI_OP_VIDEO_MODE;
  5821. }
  5822. end = array_idx;
  5823. _dsi_display_populate_bit_clks(display, start, end);
  5824. if (is_preferred) {
  5825. /* Set first timing sub mode as preferred mode */
  5826. display->modes[start].is_preferred = true;
  5827. }
  5828. }
  5829. exit:
  5830. *out_modes = display->modes;
  5831. rc = 0;
  5832. error:
  5833. if (rc)
  5834. kfree(display->modes);
  5835. mutex_unlock(&display->display_lock);
  5836. return rc;
  5837. }
  5838. int dsi_display_get_panel_vfp(void *dsi_display,
  5839. int h_active, int v_active)
  5840. {
  5841. int i, rc = 0;
  5842. u32 count, refresh_rate = 0;
  5843. struct dsi_dfps_capabilities dfps_caps;
  5844. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5845. struct dsi_host_common_cfg *host;
  5846. if (!display || !display->panel)
  5847. return -EINVAL;
  5848. mutex_lock(&display->display_lock);
  5849. count = display->panel->num_display_modes;
  5850. if (display->panel->cur_mode)
  5851. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5852. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5853. if (dfps_caps.dfps_support)
  5854. refresh_rate = dfps_caps.max_refresh_rate;
  5855. if (!refresh_rate) {
  5856. mutex_unlock(&display->display_lock);
  5857. DSI_ERR("Null Refresh Rate\n");
  5858. return -EINVAL;
  5859. }
  5860. host = &display->panel->host_config;
  5861. if (host->split_link.enabled)
  5862. h_active *= host->split_link.num_sublinks;
  5863. else
  5864. h_active *= display->ctrl_count;
  5865. for (i = 0; i < count; i++) {
  5866. struct dsi_display_mode *m = &display->modes[i];
  5867. if (m && v_active == m->timing.v_active &&
  5868. h_active == m->timing.h_active &&
  5869. refresh_rate == m->timing.refresh_rate) {
  5870. rc = m->timing.v_front_porch;
  5871. break;
  5872. }
  5873. }
  5874. mutex_unlock(&display->display_lock);
  5875. return rc;
  5876. }
  5877. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5878. {
  5879. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5880. u32 count, i;
  5881. int rc = 0;
  5882. *num_lm = 0;
  5883. mutex_lock(&display->display_lock);
  5884. count = display->panel->num_display_modes;
  5885. mutex_unlock(&display->display_lock);
  5886. if (!display->modes) {
  5887. struct dsi_display_mode *m;
  5888. rc = dsi_display_get_modes(display, &m);
  5889. if (rc)
  5890. return rc;
  5891. }
  5892. mutex_lock(&display->display_lock);
  5893. for (i = 0; i < count; i++) {
  5894. struct dsi_display_mode *m = &display->modes[i];
  5895. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5896. }
  5897. mutex_unlock(&display->display_lock);
  5898. return rc;
  5899. }
  5900. int dsi_display_get_qsync_min_fps(void *display_dsi, u32 mode_fps)
  5901. {
  5902. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5903. struct dsi_panel *panel;
  5904. u32 i;
  5905. if (display == NULL || display->panel == NULL)
  5906. return -EINVAL;
  5907. panel = display->panel;
  5908. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5909. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5910. return panel->qsync_caps.qsync_min_fps_list[i];
  5911. }
  5912. SDE_EVT32(mode_fps);
  5913. DSI_DEBUG("Invalid mode_fps %d\n", mode_fps);
  5914. return -EINVAL;
  5915. }
  5916. int dsi_display_get_avr_step_req_fps(void *display_dsi, u32 mode_fps)
  5917. {
  5918. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5919. struct dsi_panel *panel;
  5920. u32 i, step = 0;
  5921. if (!display || !display->panel)
  5922. return -EINVAL;
  5923. panel = display->panel;
  5924. /* support a single fixed rate, or rate corresponding to dfps list entry */
  5925. if (panel->avr_caps.avr_step_fps_list_len == 1) {
  5926. step = panel->avr_caps.avr_step_fps_list[0];
  5927. } else if (panel->avr_caps.avr_step_fps_list_len > 1) {
  5928. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5929. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5930. step = panel->avr_caps.avr_step_fps_list[i];
  5931. }
  5932. }
  5933. DSI_DEBUG("mode_fps %u, avr_step fps %u\n", mode_fps, step);
  5934. return step;
  5935. }
  5936. static bool dsi_display_match_timings(const struct dsi_display_mode *mode1,
  5937. struct dsi_display_mode *mode2, unsigned int match_flags)
  5938. {
  5939. bool is_matching = false;
  5940. if (match_flags & DSI_MODE_MATCH_ACTIVE_TIMINGS) {
  5941. is_matching = mode1->timing.h_active == mode2->timing.h_active &&
  5942. mode1->timing.v_active == mode2->timing.v_active &&
  5943. mode1->timing.refresh_rate == mode2->timing.refresh_rate;
  5944. if (!is_matching)
  5945. goto end;
  5946. }
  5947. if (match_flags & DSI_MODE_MATCH_PORCH_TIMINGS)
  5948. is_matching = mode1->timing.h_back_porch == mode2->timing.h_back_porch &&
  5949. mode1->timing.h_front_porch == mode2->timing.h_front_porch &&
  5950. mode1->timing.h_sync_width == mode2->timing.h_sync_width &&
  5951. mode1->timing.h_skew == mode2->timing.h_skew &&
  5952. mode1->timing.v_back_porch == mode2->timing.v_back_porch &&
  5953. mode1->timing.v_front_porch == mode2->timing.v_front_porch &&
  5954. mode1->timing.v_sync_width == mode2->timing.v_sync_width;
  5955. end:
  5956. return is_matching;
  5957. }
  5958. static bool dsi_display_mode_match(const struct dsi_display_mode *mode1,
  5959. struct dsi_display_mode *mode2, unsigned int match_flags)
  5960. {
  5961. if (!mode1 && !mode2)
  5962. return true;
  5963. if (!mode1 || !mode2)
  5964. return false;
  5965. if ((match_flags & DSI_MODE_MATCH_FULL_TIMINGS) &&
  5966. !dsi_display_match_timings(mode1, mode2, match_flags))
  5967. return false;
  5968. return true;
  5969. }
  5970. int dsi_display_find_mode(struct dsi_display *display,
  5971. const struct dsi_display_mode *cmp,
  5972. struct dsi_display_mode **out_mode)
  5973. {
  5974. u32 count, i;
  5975. int rc;
  5976. struct dsi_display_mode *m;
  5977. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5978. unsigned int match_flags = DSI_MODE_MATCH_FULL_TIMINGS;
  5979. if (!display || !out_mode)
  5980. return -EINVAL;
  5981. *out_mode = NULL;
  5982. mutex_lock(&display->display_lock);
  5983. count = display->panel->num_display_modes;
  5984. mutex_unlock(&display->display_lock);
  5985. if (!display->modes) {
  5986. rc = dsi_display_get_modes(display, &m);
  5987. if (rc)
  5988. return rc;
  5989. }
  5990. mutex_lock(&display->display_lock);
  5991. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5992. for (i = 0; i < count; i++) {
  5993. m = &display->modes[i];
  5994. /**
  5995. * When dynamic bit clock is enabled with contants FPS,
  5996. * the adjusted mode porches value may not match the panel
  5997. * default mode porches and panel mode lookup will fail.
  5998. * In that case we omit porches in mode matching function.
  5999. */
  6000. if (dyn_clk_caps->maintain_const_fps)
  6001. match_flags = DSI_MODE_MATCH_ACTIVE_TIMINGS;
  6002. if (dsi_display_mode_match(cmp, m, match_flags)) {
  6003. *out_mode = m;
  6004. rc = 0;
  6005. break;
  6006. }
  6007. }
  6008. mutex_unlock(&display->display_lock);
  6009. if (!*out_mode) {
  6010. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  6011. display->name, cmp->timing.v_active,
  6012. cmp->timing.h_active, cmp->timing.refresh_rate,
  6013. cmp->pixel_clk_khz);
  6014. rc = -ENOENT;
  6015. }
  6016. return rc;
  6017. }
  6018. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  6019. struct dsi_display_mode *adj)
  6020. {
  6021. /*
  6022. * If there is a change in the hfp or vfp of the current and adjoining
  6023. * mode,then either it is a dfps mode switch or dynamic clk change with
  6024. * constant fps.
  6025. */
  6026. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  6027. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  6028. return true;
  6029. else
  6030. return false;
  6031. }
  6032. /**
  6033. * dsi_display_validate_mode_change() - Validate mode change case.
  6034. * @display: DSI display handle.
  6035. * @cur_mode: Current mode.
  6036. * @adj_mode: Mode to be set.
  6037. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  6038. * is change in hfp or vfp but vactive and hactive are same.
  6039. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  6040. * is change in clk but vactive and hactive are same.
  6041. * Return: error code.
  6042. */
  6043. int dsi_display_validate_mode_change(struct dsi_display *display,
  6044. struct dsi_display_mode *cur_mode,
  6045. struct dsi_display_mode *adj_mode)
  6046. {
  6047. int rc = 0;
  6048. struct dsi_dfps_capabilities dfps_caps;
  6049. struct dsi_dyn_clk_caps *dyn_clk_caps;
  6050. struct sde_connector *sde_conn;
  6051. if (!display || !adj_mode || !display->drm_conn) {
  6052. DSI_ERR("Invalid params\n");
  6053. return -EINVAL;
  6054. }
  6055. if (!display->panel || !display->panel->cur_mode) {
  6056. DSI_DEBUG("Current panel mode not set\n");
  6057. return rc;
  6058. }
  6059. if ((cur_mode->timing.v_active != adj_mode->timing.v_active) ||
  6060. (cur_mode->timing.h_active != adj_mode->timing.h_active)) {
  6061. DSI_DEBUG("Avoid VRR and POMS when resolution is changed\n");
  6062. return rc;
  6063. }
  6064. sde_conn = to_sde_connector(display->drm_conn);
  6065. mutex_lock(&display->display_lock);
  6066. if (sde_conn->expected_panel_mode == MSM_DISPLAY_VIDEO_MODE &&
  6067. display->config.panel_mode == DSI_OP_CMD_MODE) {
  6068. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  6069. DSI_DEBUG("Panel operating mode change to video detected\n");
  6070. } else if (sde_conn->expected_panel_mode == MSM_DISPLAY_CMD_MODE &&
  6071. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6072. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  6073. DSI_DEBUG("Panel operating mode change to command detected\n");
  6074. } else {
  6075. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  6076. /* dfps and dynamic clock with const fps use case */
  6077. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  6078. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  6079. if (dfps_caps.dfps_support ||
  6080. dyn_clk_caps->maintain_const_fps) {
  6081. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  6082. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  6083. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1,
  6084. cur_mode->timing.refresh_rate,
  6085. adj_mode->timing.refresh_rate,
  6086. cur_mode->timing.h_front_porch,
  6087. adj_mode->timing.h_front_porch,
  6088. cur_mode->timing.v_front_porch,
  6089. adj_mode->timing.v_front_porch);
  6090. }
  6091. }
  6092. /* dynamic clk change use case */
  6093. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  6094. if (dyn_clk_caps->dyn_clk_support) {
  6095. DSI_DEBUG("dynamic clk change detected\n");
  6096. if ((adj_mode->dsi_mode_flags &
  6097. DSI_MODE_FLAG_VRR) &&
  6098. (!dyn_clk_caps->maintain_const_fps)) {
  6099. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  6100. rc = -ENOTSUPP;
  6101. goto error;
  6102. }
  6103. /**
  6104. * Set VRR flag whenever there is a dynamic clock
  6105. * change on video mode panel as dynamic refresh is
  6106. * always required when fps compensation is enabled.
  6107. */
  6108. if ((display->config.panel_mode == DSI_OP_VIDEO_MODE) &&
  6109. dyn_clk_caps->maintain_const_fps)
  6110. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  6111. adj_mode->dsi_mode_flags |=
  6112. DSI_MODE_FLAG_DYN_CLK;
  6113. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  6114. cur_mode->pixel_clk_khz,
  6115. adj_mode->pixel_clk_khz);
  6116. }
  6117. }
  6118. }
  6119. error:
  6120. mutex_unlock(&display->display_lock);
  6121. return rc;
  6122. }
  6123. int dsi_display_validate_mode(struct dsi_display *display,
  6124. struct dsi_display_mode *mode,
  6125. u32 flags)
  6126. {
  6127. int rc = 0;
  6128. int i;
  6129. struct dsi_display_ctrl *ctrl;
  6130. struct dsi_display_mode adj_mode;
  6131. if (!display || !mode) {
  6132. DSI_ERR("Invalid params\n");
  6133. return -EINVAL;
  6134. }
  6135. mutex_lock(&display->display_lock);
  6136. adj_mode = *mode;
  6137. adjust_timing_by_ctrl_count(display, &adj_mode);
  6138. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  6139. if (rc) {
  6140. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  6141. display->name, rc);
  6142. goto error;
  6143. }
  6144. display_for_each_ctrl(i, display) {
  6145. ctrl = &display->ctrl[i];
  6146. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  6147. if (rc) {
  6148. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  6149. display->name, rc);
  6150. goto error;
  6151. }
  6152. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  6153. if (rc) {
  6154. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  6155. display->name, rc);
  6156. goto error;
  6157. }
  6158. }
  6159. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  6160. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  6161. rc = dsi_display_validate_mode_seamless(display, mode);
  6162. if (rc) {
  6163. DSI_ERR("[%s] seamless not possible rc=%d\n",
  6164. display->name, rc);
  6165. goto error;
  6166. }
  6167. }
  6168. error:
  6169. mutex_unlock(&display->display_lock);
  6170. return rc;
  6171. }
  6172. int dsi_display_set_mode(struct dsi_display *display,
  6173. struct dsi_display_mode *mode,
  6174. u32 flags)
  6175. {
  6176. int rc = 0;
  6177. struct dsi_display_mode adj_mode;
  6178. struct dsi_mode_info timing;
  6179. if (!display || !mode || !display->panel) {
  6180. DSI_ERR("Invalid params\n");
  6181. return -EINVAL;
  6182. }
  6183. mutex_lock(&display->display_lock);
  6184. adj_mode = *mode;
  6185. timing = adj_mode.timing;
  6186. adjust_timing_by_ctrl_count(display, &adj_mode);
  6187. if (!display->panel->cur_mode) {
  6188. display->panel->cur_mode =
  6189. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  6190. if (!display->panel->cur_mode) {
  6191. rc = -ENOMEM;
  6192. goto error;
  6193. }
  6194. }
  6195. rc = dsi_display_restore_bit_clk(display, &adj_mode);
  6196. if (rc) {
  6197. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  6198. goto error;
  6199. }
  6200. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  6201. if (rc) {
  6202. DSI_ERR("[%s] mode cannot be set\n", display->name);
  6203. goto error;
  6204. }
  6205. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  6206. if (rc) {
  6207. DSI_ERR("[%s] failed to set mode\n", display->name);
  6208. goto error;
  6209. }
  6210. DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d, clk_rate=%llu\n",
  6211. adj_mode.priv_info->mdp_transfer_time_us,
  6212. timing.h_active, timing.v_active, timing.refresh_rate,
  6213. adj_mode.priv_info->clk_rate_hz);
  6214. SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
  6215. timing.h_active, timing.v_active, timing.refresh_rate,
  6216. adj_mode.priv_info->clk_rate_hz);
  6217. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  6218. error:
  6219. mutex_unlock(&display->display_lock);
  6220. return rc;
  6221. }
  6222. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  6223. {
  6224. int rc = 0;
  6225. int i;
  6226. struct dsi_display_ctrl *ctrl;
  6227. if (!display) {
  6228. DSI_ERR("Invalid params\n");
  6229. return -EINVAL;
  6230. }
  6231. display_for_each_ctrl(i, display) {
  6232. ctrl = &display->ctrl[i];
  6233. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  6234. if (rc) {
  6235. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  6236. display->name, i);
  6237. goto error;
  6238. }
  6239. }
  6240. display->is_tpg_enabled = enable;
  6241. error:
  6242. return rc;
  6243. }
  6244. static int dsi_display_pre_switch(struct dsi_display *display)
  6245. {
  6246. int rc = 0;
  6247. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6248. DSI_CORE_CLK, DSI_CLK_ON);
  6249. if (rc) {
  6250. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6251. display->name, rc);
  6252. goto error;
  6253. }
  6254. rc = dsi_display_ctrl_update(display);
  6255. if (rc) {
  6256. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  6257. display->name, rc);
  6258. goto error_ctrl_clk_off;
  6259. }
  6260. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6261. DSI_LINK_CLK, DSI_CLK_ON);
  6262. if (rc) {
  6263. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6264. display->name, rc);
  6265. goto error_ctrl_deinit;
  6266. }
  6267. goto error;
  6268. error_ctrl_deinit:
  6269. (void)dsi_display_ctrl_deinit(display);
  6270. error_ctrl_clk_off:
  6271. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6272. DSI_CORE_CLK, DSI_CLK_OFF);
  6273. error:
  6274. return rc;
  6275. }
  6276. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  6277. {
  6278. int i;
  6279. struct dsi_display_ctrl *ctrl;
  6280. display_for_each_ctrl(i, display) {
  6281. ctrl = &display->ctrl[i];
  6282. if (!ctrl->ctrl)
  6283. continue;
  6284. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  6285. return false;
  6286. }
  6287. return true;
  6288. }
  6289. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  6290. {
  6291. struct dsi_display *display = NULL;
  6292. display = container_of(work, struct dsi_display, fifo_underflow_work);
  6293. if (!display || !display->panel ||
  6294. atomic_read(&display->panel->esd_recovery_pending)) {
  6295. DSI_DEBUG("Invalid recovery use case\n");
  6296. return;
  6297. }
  6298. mutex_lock(&display->display_lock);
  6299. if (!_dsi_display_validate_host_state(display)) {
  6300. mutex_unlock(&display->display_lock);
  6301. return;
  6302. }
  6303. DSI_INFO("handle DSI FIFO underflow error\n");
  6304. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6305. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6306. DSI_ALL_CLKS, DSI_CLK_ON);
  6307. dsi_display_soft_reset(display);
  6308. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6309. DSI_ALL_CLKS, DSI_CLK_OFF);
  6310. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6311. mutex_unlock(&display->display_lock);
  6312. }
  6313. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6314. {
  6315. struct dsi_display *display = NULL;
  6316. struct dsi_display_ctrl *ctrl;
  6317. int i, rc;
  6318. int mask = BIT(20); /* clock lane */
  6319. int (*cb_func)(void *event_usr_ptr,
  6320. uint32_t event_idx, uint32_t instance_idx,
  6321. uint32_t data0, uint32_t data1,
  6322. uint32_t data2, uint32_t data3);
  6323. void *data;
  6324. u32 version = 0;
  6325. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6326. if (!display || !display->panel ||
  6327. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6328. atomic_read(&display->panel->esd_recovery_pending)) {
  6329. DSI_DEBUG("Invalid recovery use case\n");
  6330. return;
  6331. }
  6332. mutex_lock(&display->display_lock);
  6333. if (!_dsi_display_validate_host_state(display)) {
  6334. mutex_unlock(&display->display_lock);
  6335. return;
  6336. }
  6337. DSI_INFO("handle DSI FIFO overflow error\n");
  6338. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6339. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6340. DSI_ALL_CLKS, DSI_CLK_ON);
  6341. /*
  6342. * below recovery sequence is not applicable to
  6343. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6344. */
  6345. ctrl = &display->ctrl[display->clk_master_idx];
  6346. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6347. if (!version || (version < 0x20020001))
  6348. goto end;
  6349. /* reset ctrl and lanes */
  6350. display_for_each_ctrl(i, display) {
  6351. ctrl = &display->ctrl[i];
  6352. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6353. rc = dsi_phy_lane_reset(ctrl->phy);
  6354. }
  6355. /* wait for display line count to be in active area */
  6356. ctrl = &display->ctrl[display->clk_master_idx];
  6357. if (ctrl->ctrl->recovery_cb.event_cb) {
  6358. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6359. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6360. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6361. display->clk_master_idx, 0, 0, 0, 0);
  6362. if (rc < 0) {
  6363. DSI_DEBUG("sde callback failed\n");
  6364. goto end;
  6365. }
  6366. }
  6367. /* Enable Video mode for DSI controller */
  6368. display_for_each_ctrl(i, display) {
  6369. ctrl = &display->ctrl[i];
  6370. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6371. }
  6372. /*
  6373. * Add sufficient delay to make sure
  6374. * pixel transmission has started
  6375. */
  6376. udelay(200);
  6377. end:
  6378. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6379. DSI_ALL_CLKS, DSI_CLK_OFF);
  6380. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6381. mutex_unlock(&display->display_lock);
  6382. }
  6383. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6384. {
  6385. struct dsi_display *display = NULL;
  6386. struct dsi_display_ctrl *ctrl;
  6387. int i, rc;
  6388. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6389. int (*cb_func)(void *event_usr_ptr,
  6390. uint32_t event_idx, uint32_t instance_idx,
  6391. uint32_t data0, uint32_t data1,
  6392. uint32_t data2, uint32_t data3);
  6393. void *data;
  6394. u32 version = 0;
  6395. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6396. if (!display || !display->panel ||
  6397. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6398. atomic_read(&display->panel->esd_recovery_pending)) {
  6399. DSI_DEBUG("Invalid recovery use case\n");
  6400. return;
  6401. }
  6402. mutex_lock(&display->display_lock);
  6403. if (!_dsi_display_validate_host_state(display)) {
  6404. mutex_unlock(&display->display_lock);
  6405. return;
  6406. }
  6407. DSI_INFO("handle DSI LP RX Timeout error\n");
  6408. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6409. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6410. DSI_ALL_CLKS, DSI_CLK_ON);
  6411. /*
  6412. * below recovery sequence is not applicable to
  6413. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6414. */
  6415. ctrl = &display->ctrl[display->clk_master_idx];
  6416. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6417. if (!version || (version < 0x20020001))
  6418. goto end;
  6419. /* reset ctrl and lanes */
  6420. display_for_each_ctrl(i, display) {
  6421. ctrl = &display->ctrl[i];
  6422. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6423. rc = dsi_phy_lane_reset(ctrl->phy);
  6424. }
  6425. ctrl = &display->ctrl[display->clk_master_idx];
  6426. if (ctrl->ctrl->recovery_cb.event_cb) {
  6427. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6428. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6429. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6430. display->clk_master_idx, 0, 0, 0, 0);
  6431. if (rc < 0) {
  6432. DSI_DEBUG("Target is in suspend/shutdown\n");
  6433. goto end;
  6434. }
  6435. }
  6436. /* Enable Video mode for DSI controller */
  6437. display_for_each_ctrl(i, display) {
  6438. ctrl = &display->ctrl[i];
  6439. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6440. }
  6441. /*
  6442. * Add sufficient delay to make sure
  6443. * pixel transmission as started
  6444. */
  6445. udelay(200);
  6446. end:
  6447. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6448. DSI_ALL_CLKS, DSI_CLK_OFF);
  6449. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6450. mutex_unlock(&display->display_lock);
  6451. }
  6452. static int dsi_display_cb_error_handler(void *data,
  6453. uint32_t event_idx, uint32_t instance_idx,
  6454. uint32_t data0, uint32_t data1,
  6455. uint32_t data2, uint32_t data3)
  6456. {
  6457. struct dsi_display *display = data;
  6458. if (!display || !(display->err_workq))
  6459. return -EINVAL;
  6460. switch (event_idx) {
  6461. case DSI_FIFO_UNDERFLOW:
  6462. queue_work(display->err_workq, &display->fifo_underflow_work);
  6463. break;
  6464. case DSI_FIFO_OVERFLOW:
  6465. queue_work(display->err_workq, &display->fifo_overflow_work);
  6466. break;
  6467. case DSI_LP_Rx_TIMEOUT:
  6468. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6469. break;
  6470. default:
  6471. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6472. break;
  6473. }
  6474. return 0;
  6475. }
  6476. static void dsi_display_register_error_handler(struct dsi_display *display)
  6477. {
  6478. int i = 0;
  6479. struct dsi_display_ctrl *ctrl;
  6480. struct dsi_event_cb_info event_info;
  6481. if (!display)
  6482. return;
  6483. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6484. if (!display->err_workq) {
  6485. DSI_ERR("failed to create dsi workq!\n");
  6486. return;
  6487. }
  6488. INIT_WORK(&display->fifo_underflow_work,
  6489. dsi_display_handle_fifo_underflow);
  6490. INIT_WORK(&display->fifo_overflow_work,
  6491. dsi_display_handle_fifo_overflow);
  6492. INIT_WORK(&display->lp_rx_timeout_work,
  6493. dsi_display_handle_lp_rx_timeout);
  6494. memset(&event_info, 0, sizeof(event_info));
  6495. event_info.event_cb = dsi_display_cb_error_handler;
  6496. event_info.event_usr_ptr = display;
  6497. display_for_each_ctrl(i, display) {
  6498. ctrl = &display->ctrl[i];
  6499. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6500. }
  6501. }
  6502. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6503. {
  6504. int i = 0;
  6505. struct dsi_display_ctrl *ctrl;
  6506. if (!display)
  6507. return;
  6508. display_for_each_ctrl(i, display) {
  6509. ctrl = &display->ctrl[i];
  6510. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6511. 0, sizeof(struct dsi_event_cb_info));
  6512. }
  6513. if (display->err_workq) {
  6514. destroy_workqueue(display->err_workq);
  6515. display->err_workq = NULL;
  6516. }
  6517. }
  6518. int dsi_display_prepare(struct dsi_display *display)
  6519. {
  6520. int rc = 0;
  6521. struct dsi_display_mode *mode;
  6522. if (!display) {
  6523. DSI_ERR("Invalid params\n");
  6524. return -EINVAL;
  6525. }
  6526. if (!display->panel->cur_mode) {
  6527. DSI_ERR("no valid mode set for the display\n");
  6528. return -EINVAL;
  6529. }
  6530. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6531. mutex_lock(&display->display_lock);
  6532. display->hw_ownership = true;
  6533. mode = display->panel->cur_mode;
  6534. dsi_display_set_ctrl_esd_check_flag(display, false);
  6535. /* Set up ctrl isr before enabling core clk */
  6536. if (!display->trusted_vm_env)
  6537. dsi_display_ctrl_isr_configure(display, true);
  6538. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6539. if (display->is_cont_splash_enabled &&
  6540. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6541. DSI_ERR("DMS not supported on first frame\n");
  6542. rc = -EINVAL;
  6543. goto error;
  6544. }
  6545. if (!is_skip_op_required(display)) {
  6546. /* update dsi ctrl for new mode */
  6547. rc = dsi_display_pre_switch(display);
  6548. if (rc)
  6549. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6550. display->name, rc);
  6551. goto error;
  6552. }
  6553. }
  6554. if (!display->poms_pending &&
  6555. (!is_skip_op_required(display))) {
  6556. /*
  6557. * For continuous splash/trusted vm, we skip panel
  6558. * pre prepare since the regulator vote is already
  6559. * taken care in splash resource init
  6560. */
  6561. rc = dsi_panel_pre_prepare(display->panel);
  6562. if (rc) {
  6563. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6564. display->name, rc);
  6565. goto error;
  6566. }
  6567. }
  6568. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6569. DSI_CORE_CLK, DSI_CLK_ON);
  6570. if (rc) {
  6571. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6572. display->name, rc);
  6573. goto error_panel_post_unprep;
  6574. }
  6575. /*
  6576. * If ULPS during suspend feature is enabled, then DSI PHY was
  6577. * left on during suspend. In this case, we do not need to reset/init
  6578. * PHY. This would have already been done when the CORE clocks are
  6579. * turned on. However, if cont splash is disabled, the first time DSI
  6580. * is powered on, phy init needs to be done unconditionally.
  6581. */
  6582. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6583. rc = dsi_display_phy_sw_reset(display);
  6584. if (rc) {
  6585. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6586. display->name, rc);
  6587. goto error_ctrl_clk_off;
  6588. }
  6589. rc = dsi_display_phy_enable(display);
  6590. if (rc) {
  6591. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6592. display->name, rc);
  6593. goto error_ctrl_clk_off;
  6594. }
  6595. }
  6596. rc = dsi_display_ctrl_init(display);
  6597. if (rc) {
  6598. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6599. display->name, rc);
  6600. goto error_phy_disable;
  6601. }
  6602. /* Set up DSI ERROR event callback */
  6603. dsi_display_register_error_handler(display);
  6604. rc = dsi_display_ctrl_host_enable(display);
  6605. if (rc) {
  6606. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6607. display->name, rc);
  6608. goto error_ctrl_deinit;
  6609. }
  6610. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6611. DSI_LINK_CLK, DSI_CLK_ON);
  6612. if (rc) {
  6613. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6614. display->name, rc);
  6615. goto error_host_engine_off;
  6616. }
  6617. if (!is_skip_op_required(display)) {
  6618. /*
  6619. * For continuous splash/trusted vm, skip panel prepare and
  6620. * ctl reset since the pnael and ctrl is already in active
  6621. * state and panel on commands are not needed
  6622. */
  6623. rc = dsi_display_soft_reset(display);
  6624. if (rc) {
  6625. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6626. display->name, rc);
  6627. goto error_ctrl_link_off;
  6628. }
  6629. if (!display->poms_pending) {
  6630. rc = dsi_panel_prepare(display->panel);
  6631. if (rc) {
  6632. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6633. display->name, rc);
  6634. goto error_ctrl_link_off;
  6635. }
  6636. }
  6637. }
  6638. goto error;
  6639. error_ctrl_link_off:
  6640. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6641. DSI_LINK_CLK, DSI_CLK_OFF);
  6642. error_host_engine_off:
  6643. (void)dsi_display_ctrl_host_disable(display);
  6644. error_ctrl_deinit:
  6645. (void)dsi_display_ctrl_deinit(display);
  6646. error_phy_disable:
  6647. (void)dsi_display_phy_disable(display);
  6648. error_ctrl_clk_off:
  6649. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6650. DSI_CORE_CLK, DSI_CLK_OFF);
  6651. error_panel_post_unprep:
  6652. (void)dsi_panel_post_unprepare(display->panel);
  6653. error:
  6654. mutex_unlock(&display->display_lock);
  6655. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6656. return rc;
  6657. }
  6658. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6659. const struct dsi_display_ctrl *ctrl,
  6660. const struct msm_roi_list *req_rois,
  6661. struct dsi_rect *out_roi)
  6662. {
  6663. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6664. struct dsi_display_mode *cur_mode;
  6665. struct msm_roi_caps *roi_caps;
  6666. struct dsi_rect req_roi = { 0 };
  6667. int rc = 0;
  6668. cur_mode = display->panel->cur_mode;
  6669. if (!cur_mode)
  6670. return 0;
  6671. roi_caps = &cur_mode->priv_info->roi_caps;
  6672. if (req_rois->num_rects > roi_caps->num_roi) {
  6673. DSI_ERR("request for %d rois greater than max %d\n",
  6674. req_rois->num_rects,
  6675. roi_caps->num_roi);
  6676. rc = -EINVAL;
  6677. goto exit;
  6678. }
  6679. /**
  6680. * if no rois, user wants to reset back to full resolution
  6681. * note: h_active is already divided by ctrl_count
  6682. */
  6683. if (!req_rois->num_rects) {
  6684. *out_roi = *bounds;
  6685. goto exit;
  6686. }
  6687. /* intersect with the bounds */
  6688. req_roi.x = req_rois->roi[0].x1;
  6689. req_roi.y = req_rois->roi[0].y1;
  6690. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6691. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6692. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6693. exit:
  6694. /* adjust the ctrl origin to be top left within the ctrl */
  6695. out_roi->x = out_roi->x - bounds->x;
  6696. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6697. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6698. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6699. bounds->x, bounds->y, bounds->w, bounds->h,
  6700. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6701. return rc;
  6702. }
  6703. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6704. {
  6705. int i;
  6706. int rc = 0;
  6707. if (!display->panel->qsync_caps.qsync_min_fps) {
  6708. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6709. return 0;
  6710. }
  6711. mutex_lock(&display->display_lock);
  6712. display_for_each_ctrl(i, display) {
  6713. if (enable) {
  6714. /* send the commands to enable qsync */
  6715. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6716. if (rc) {
  6717. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6718. goto exit;
  6719. }
  6720. } else {
  6721. /* send the commands to enable qsync */
  6722. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6723. if (rc) {
  6724. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6725. goto exit;
  6726. }
  6727. }
  6728. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6729. }
  6730. exit:
  6731. SDE_EVT32(enable, display->panel->qsync_caps.qsync_min_fps, rc);
  6732. mutex_unlock(&display->display_lock);
  6733. return rc;
  6734. }
  6735. static int dsi_display_set_roi(struct dsi_display *display,
  6736. struct msm_roi_list *rois)
  6737. {
  6738. struct dsi_display_mode *cur_mode;
  6739. struct msm_roi_caps *roi_caps;
  6740. int rc = 0;
  6741. int i;
  6742. if (!display || !rois || !display->panel)
  6743. return -EINVAL;
  6744. cur_mode = display->panel->cur_mode;
  6745. if (!cur_mode)
  6746. return 0;
  6747. roi_caps = &cur_mode->priv_info->roi_caps;
  6748. if (!roi_caps->enabled)
  6749. return 0;
  6750. display_for_each_ctrl(i, display) {
  6751. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6752. struct dsi_rect ctrl_roi;
  6753. bool changed = false;
  6754. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6755. if (rc) {
  6756. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6757. return rc;
  6758. }
  6759. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6760. if (rc) {
  6761. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6762. return rc;
  6763. }
  6764. if (!changed)
  6765. continue;
  6766. /* send the new roi to the panel via dcs commands */
  6767. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6768. if (rc) {
  6769. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6770. return rc;
  6771. }
  6772. /* re-program the ctrl with the timing based on the new roi */
  6773. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6774. if (rc) {
  6775. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6776. return rc;
  6777. }
  6778. }
  6779. return rc;
  6780. }
  6781. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6782. struct dsi_display *display,
  6783. struct msm_display_kickoff_params *params)
  6784. {
  6785. int rc = 0, ret = 0;
  6786. int i;
  6787. /* check and setup MISR */
  6788. if (display->misr_enable)
  6789. _dsi_display_setup_misr(display);
  6790. /* dynamic DSI clock setting */
  6791. if (atomic_read(&display->clkrate_change_pending)) {
  6792. mutex_lock(&display->display_lock);
  6793. /*
  6794. * acquire panel_lock to make sure no commands are in progress
  6795. */
  6796. dsi_panel_acquire_panel_lock(display->panel);
  6797. /*
  6798. * Wait for DSI command engine not to be busy sending data
  6799. * from display engine.
  6800. * If waiting fails, return "rc" instead of below "ret" so as
  6801. * not to impact DRM commit. The clock updating would be
  6802. * deferred to the next DRM commit.
  6803. */
  6804. display_for_each_ctrl(i, display) {
  6805. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6806. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6807. if (ret)
  6808. goto wait_failure;
  6809. }
  6810. /*
  6811. * Don't check the return value so as not to impact DRM commit
  6812. * when error occurs.
  6813. */
  6814. (void)dsi_display_force_update_dsi_clk(display);
  6815. wait_failure:
  6816. /* release panel_lock */
  6817. dsi_panel_release_panel_lock(display->panel);
  6818. mutex_unlock(&display->display_lock);
  6819. }
  6820. if (!ret)
  6821. rc = dsi_display_set_roi(display, params->rois);
  6822. return rc;
  6823. }
  6824. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6825. {
  6826. int rc = 0;
  6827. if (!display || !display->panel) {
  6828. DSI_ERR("Invalid params\n");
  6829. return -EINVAL;
  6830. }
  6831. if (!display->panel->cur_mode) {
  6832. DSI_ERR("no valid mode set for the display\n");
  6833. return -EINVAL;
  6834. }
  6835. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6836. rc = dsi_display_vid_engine_enable(display);
  6837. if (rc) {
  6838. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6839. display->name, rc);
  6840. goto error_out;
  6841. }
  6842. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6843. rc = dsi_display_cmd_engine_enable(display);
  6844. if (rc) {
  6845. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6846. display->name, rc);
  6847. goto error_out;
  6848. }
  6849. } else {
  6850. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6851. rc = -EINVAL;
  6852. }
  6853. error_out:
  6854. return rc;
  6855. }
  6856. int dsi_display_pre_commit(void *display,
  6857. struct msm_display_conn_params *params)
  6858. {
  6859. bool enable = false;
  6860. int rc = 0;
  6861. if (!display || !params) {
  6862. pr_err("Invalid params\n");
  6863. return -EINVAL;
  6864. }
  6865. if (params->qsync_update) {
  6866. enable = (params->qsync_mode > 0) ? true : false;
  6867. rc = dsi_display_qsync(display, enable);
  6868. if (rc)
  6869. pr_err("%s failed to send qsync commands\n",
  6870. __func__);
  6871. SDE_EVT32(params->qsync_mode, rc);
  6872. }
  6873. return rc;
  6874. }
  6875. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6876. {
  6877. if (display->panel_id != ~0x0 &&
  6878. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6879. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6880. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6881. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6882. 0, ((display->panel_id & 0xffffffff00000000) >> 32),
  6883. (display->panel_id & 0xffffffff), 0, 0);
  6884. }
  6885. }
  6886. int dsi_display_enable(struct dsi_display *display)
  6887. {
  6888. int rc = 0;
  6889. struct dsi_display_mode *mode;
  6890. if (!display || !display->panel) {
  6891. DSI_ERR("Invalid params\n");
  6892. return -EINVAL;
  6893. }
  6894. if (!display->panel->cur_mode) {
  6895. DSI_ERR("no valid mode set for the display\n");
  6896. return -EINVAL;
  6897. }
  6898. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6899. /*
  6900. * Engine states and panel states are populated during splash
  6901. * resource/trusted vm and hence we return early
  6902. */
  6903. if (is_skip_op_required(display)) {
  6904. dsi_display_config_ctrl_for_cont_splash(display);
  6905. rc = dsi_display_splash_res_cleanup(display);
  6906. if (rc) {
  6907. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6908. rc);
  6909. return -EINVAL;
  6910. }
  6911. display->panel->panel_initialized = true;
  6912. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6913. dsi_display_panel_id_notification(display);
  6914. return 0;
  6915. }
  6916. mutex_lock(&display->display_lock);
  6917. mode = display->panel->cur_mode;
  6918. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6919. rc = dsi_panel_post_switch(display->panel);
  6920. if (rc) {
  6921. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6922. display->name, rc);
  6923. goto error;
  6924. }
  6925. } else if (!display->poms_pending) {
  6926. rc = dsi_panel_enable(display->panel);
  6927. if (rc) {
  6928. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6929. display->name, rc);
  6930. goto error;
  6931. }
  6932. }
  6933. dsi_display_panel_id_notification(display);
  6934. /* Block sending pps command if modeset is due to fps difference */
  6935. if ((mode->priv_info->dsc_enabled ||
  6936. mode->priv_info->vdc_enabled) &&
  6937. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6938. rc = dsi_panel_update_pps(display->panel);
  6939. if (rc) {
  6940. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6941. display->name, rc);
  6942. goto error;
  6943. }
  6944. }
  6945. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6946. rc = dsi_panel_switch(display->panel);
  6947. if (rc)
  6948. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6949. display->name, rc);
  6950. goto error;
  6951. }
  6952. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6953. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6954. rc = dsi_display_vid_engine_enable(display);
  6955. if (rc) {
  6956. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6957. display->name, rc);
  6958. goto error_disable_panel;
  6959. }
  6960. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6961. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6962. rc = dsi_display_cmd_engine_enable(display);
  6963. if (rc) {
  6964. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6965. display->name, rc);
  6966. goto error_disable_panel;
  6967. }
  6968. } else {
  6969. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6970. rc = -EINVAL;
  6971. goto error_disable_panel;
  6972. }
  6973. goto error;
  6974. error_disable_panel:
  6975. (void)dsi_panel_disable(display->panel);
  6976. error:
  6977. mutex_unlock(&display->display_lock);
  6978. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6979. return rc;
  6980. }
  6981. int dsi_display_post_enable(struct dsi_display *display)
  6982. {
  6983. int rc = 0;
  6984. if (!display) {
  6985. DSI_ERR("Invalid params\n");
  6986. return -EINVAL;
  6987. }
  6988. mutex_lock(&display->display_lock);
  6989. if (display->panel->cur_mode->dsi_mode_flags &
  6990. DSI_MODE_FLAG_POMS_TO_CMD) {
  6991. dsi_panel_switch_cmd_mode_in(display->panel);
  6992. } else if (display->panel->cur_mode->dsi_mode_flags &
  6993. DSI_MODE_FLAG_POMS_TO_VID)
  6994. dsi_panel_switch_video_mode_in(display->panel);
  6995. else {
  6996. rc = dsi_panel_post_enable(display->panel);
  6997. if (rc)
  6998. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  6999. display->name, rc);
  7000. }
  7001. /* remove the clk vote for CMD mode panels */
  7002. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7003. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7004. DSI_ALL_CLKS, DSI_CLK_OFF);
  7005. mutex_unlock(&display->display_lock);
  7006. return rc;
  7007. }
  7008. int dsi_display_pre_disable(struct dsi_display *display)
  7009. {
  7010. int rc = 0;
  7011. if (!display) {
  7012. DSI_ERR("Invalid params\n");
  7013. return -EINVAL;
  7014. }
  7015. mutex_lock(&display->display_lock);
  7016. /* enable the clk vote for CMD mode panels */
  7017. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7018. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7019. DSI_ALL_CLKS, DSI_CLK_ON);
  7020. if (display->poms_pending) {
  7021. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7022. dsi_panel_switch_cmd_mode_out(display->panel);
  7023. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7024. /*
  7025. * Add unbalanced vote for clock & cmd engine to enable
  7026. * async trigger of pre video to cmd mode switch.
  7027. */
  7028. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7029. DSI_ALL_CLKS, DSI_CLK_ON);
  7030. if (rc) {
  7031. DSI_ERR("[%s]failed to enable all clocks,rc=%d",
  7032. display->name, rc);
  7033. goto exit;
  7034. }
  7035. rc = dsi_display_cmd_engine_enable(display);
  7036. if (rc) {
  7037. DSI_ERR("[%s]failed to enable cmd engine,rc=%d",
  7038. display->name, rc);
  7039. goto error_disable_clks;
  7040. }
  7041. dsi_panel_switch_video_mode_out(display->panel);
  7042. }
  7043. } else {
  7044. rc = dsi_panel_pre_disable(display->panel);
  7045. if (rc)
  7046. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  7047. display->name, rc);
  7048. }
  7049. goto exit;
  7050. error_disable_clks:
  7051. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7052. DSI_ALL_CLKS, DSI_CLK_OFF);
  7053. if (rc)
  7054. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  7055. display->name, rc);
  7056. exit:
  7057. mutex_unlock(&display->display_lock);
  7058. return rc;
  7059. }
  7060. static void dsi_display_handle_poms_te(struct work_struct *work)
  7061. {
  7062. struct dsi_display *display = NULL;
  7063. struct delayed_work *dw = to_delayed_work(work);
  7064. struct mipi_dsi_device *dsi = NULL;
  7065. struct dsi_panel *panel = NULL;
  7066. int rc = 0;
  7067. display = container_of(dw, struct dsi_display, poms_te_work);
  7068. if (!display || !display->panel) {
  7069. DSI_ERR("Invalid params\n");
  7070. return;
  7071. }
  7072. panel = display->panel;
  7073. mutex_lock(&panel->panel_lock);
  7074. if (!dsi_panel_initialized(panel)) {
  7075. rc = -EINVAL;
  7076. goto error;
  7077. }
  7078. dsi = &panel->mipi_device;
  7079. rc = mipi_dsi_dcs_set_tear_off(dsi);
  7080. error:
  7081. mutex_unlock(&panel->panel_lock);
  7082. if (rc < 0)
  7083. DSI_ERR("failed to set tear off\n");
  7084. }
  7085. int dsi_display_disable(struct dsi_display *display)
  7086. {
  7087. int rc = 0;
  7088. if (!display) {
  7089. DSI_ERR("Invalid params\n");
  7090. return -EINVAL;
  7091. }
  7092. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7093. mutex_lock(&display->display_lock);
  7094. /* cancel delayed work */
  7095. if (display->poms_pending &&
  7096. display->panel->poms_align_vsync)
  7097. cancel_delayed_work_sync(&display->poms_te_work);
  7098. rc = dsi_display_wake_up(display);
  7099. if (rc)
  7100. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7101. display->name, rc);
  7102. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7103. rc = dsi_display_vid_engine_disable(display);
  7104. if (rc)
  7105. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  7106. display->name, rc);
  7107. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  7108. /**
  7109. * On POMS request , disable panel TE through
  7110. * delayed work queue.
  7111. */
  7112. if (display->poms_pending &&
  7113. display->panel->poms_align_vsync) {
  7114. INIT_DELAYED_WORK(&display->poms_te_work,
  7115. dsi_display_handle_poms_te);
  7116. queue_delayed_work(system_wq,
  7117. &display->poms_te_work,
  7118. msecs_to_jiffies(100));
  7119. }
  7120. rc = dsi_display_cmd_engine_disable(display);
  7121. if (rc)
  7122. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  7123. display->name, rc);
  7124. } else {
  7125. DSI_ERR("[%s] Invalid configuration\n", display->name);
  7126. rc = -EINVAL;
  7127. }
  7128. if (!display->poms_pending && !is_skip_op_required(display)) {
  7129. rc = dsi_panel_disable(display->panel);
  7130. if (rc)
  7131. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  7132. display->name, rc);
  7133. }
  7134. if (is_skip_op_required(display)) {
  7135. /* applicable only for trusted vm */
  7136. display->panel->panel_initialized = false;
  7137. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  7138. }
  7139. mutex_unlock(&display->display_lock);
  7140. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7141. return rc;
  7142. }
  7143. int dsi_display_update_pps(char *pps_cmd, void *disp)
  7144. {
  7145. struct dsi_display *display;
  7146. if (pps_cmd == NULL || disp == NULL) {
  7147. DSI_ERR("Invalid parameter\n");
  7148. return -EINVAL;
  7149. }
  7150. display = disp;
  7151. mutex_lock(&display->display_lock);
  7152. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  7153. mutex_unlock(&display->display_lock);
  7154. return 0;
  7155. }
  7156. int dsi_display_update_dyn_bit_clk(struct dsi_display *display,
  7157. struct dsi_display_mode *mode)
  7158. {
  7159. struct dsi_dyn_clk_caps *dyn_clk_caps;
  7160. struct dsi_host_common_cfg *host_cfg;
  7161. int bpp, lanes = 0;
  7162. if (!display || !mode) {
  7163. DSI_ERR("invalid arguments\n");
  7164. return -EINVAL;
  7165. }
  7166. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  7167. if (!dyn_clk_caps->dyn_clk_support) {
  7168. DSI_DEBUG("dynamic bit clock support not enabled\n");
  7169. return 0;
  7170. } else if (!display->dyn_bit_clk_pending) {
  7171. DSI_DEBUG("dynamic bit clock rate not updated\n");
  7172. return 0;
  7173. } else if (!display->dyn_bit_clk) {
  7174. DSI_DEBUG("dynamic bit clock rate cleared\n");
  7175. return 0;
  7176. } else if (display->dyn_bit_clk < mode->priv_info->min_dsi_clk_hz) {
  7177. DSI_ERR("dynamic bit clock rate %llu smaller than minimum value:%llu\n",
  7178. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz);
  7179. return -EINVAL;
  7180. }
  7181. /* update mode clk rate with user value */
  7182. mode->timing.clk_rate_hz = display->dyn_bit_clk;
  7183. mode->priv_info->clk_rate_hz = display->dyn_bit_clk;
  7184. host_cfg = &(display->panel->host_config);
  7185. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  7186. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  7187. lanes++;
  7188. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  7189. lanes++;
  7190. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  7191. lanes++;
  7192. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  7193. lanes++;
  7194. dsi_display_adjust_mode_timing(display, mode, lanes, bpp);
  7195. /* adjust pixel clock based on dynamic bit clock */
  7196. mode->pixel_clk_khz = div_u64(mode->timing.clk_rate_hz * lanes, bpp);
  7197. do_div(mode->pixel_clk_khz, 1000);
  7198. mode->pixel_clk_khz *= display->ctrl_count;
  7199. SDE_EVT32(display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, mode->pixel_clk_khz);
  7200. DSI_DEBUG("dynamic bit clk:%u, min dsi clk:%llu, lanes:%d, bpp:%d, pck:%d Khz\n",
  7201. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, lanes, bpp,
  7202. mode->pixel_clk_khz);
  7203. display->dyn_bit_clk_pending = false;
  7204. return 0;
  7205. }
  7206. int dsi_display_dump_clks_state(struct dsi_display *display)
  7207. {
  7208. int rc = 0;
  7209. if (!display) {
  7210. DSI_ERR("invalid display argument\n");
  7211. return -EINVAL;
  7212. }
  7213. if (!display->clk_mngr) {
  7214. DSI_ERR("invalid clk manager\n");
  7215. return -EINVAL;
  7216. }
  7217. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  7218. DSI_ERR("invalid clk handles\n");
  7219. return -EINVAL;
  7220. }
  7221. mutex_lock(&display->display_lock);
  7222. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  7223. if (rc) {
  7224. DSI_ERR("failed to dump dsi clock state\n");
  7225. goto end;
  7226. }
  7227. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  7228. if (rc) {
  7229. DSI_ERR("failed to dump mdp clock state\n");
  7230. goto end;
  7231. }
  7232. end:
  7233. mutex_unlock(&display->display_lock);
  7234. return rc;
  7235. }
  7236. int dsi_display_unprepare(struct dsi_display *display)
  7237. {
  7238. int rc = 0, i;
  7239. struct dsi_display_ctrl *ctrl;
  7240. if (!display) {
  7241. DSI_ERR("Invalid params\n");
  7242. return -EINVAL;
  7243. }
  7244. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7245. mutex_lock(&display->display_lock);
  7246. rc = dsi_display_wake_up(display);
  7247. if (rc)
  7248. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7249. display->name, rc);
  7250. if (!display->poms_pending && !is_skip_op_required(display)) {
  7251. rc = dsi_panel_unprepare(display->panel);
  7252. if (rc)
  7253. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  7254. display->name, rc);
  7255. }
  7256. /* Remove additional vote added for pre_mode_switch_to_cmd */
  7257. if (display->poms_pending &&
  7258. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7259. display_for_each_ctrl(i, display) {
  7260. ctrl = &display->ctrl[i];
  7261. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  7262. continue;
  7263. flush_workqueue(display->dma_cmd_workq);
  7264. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  7265. ctrl->ctrl->dma_wait_queued = false;
  7266. }
  7267. dsi_display_cmd_engine_disable(display);
  7268. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7269. DSI_ALL_CLKS, DSI_CLK_OFF);
  7270. }
  7271. rc = dsi_display_ctrl_host_disable(display);
  7272. if (rc)
  7273. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  7274. display->name, rc);
  7275. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7276. DSI_LINK_CLK, DSI_CLK_OFF);
  7277. if (rc)
  7278. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  7279. display->name, rc);
  7280. rc = dsi_display_ctrl_deinit(display);
  7281. if (rc)
  7282. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  7283. display->name, rc);
  7284. if (!display->panel->ulps_suspend_enabled) {
  7285. rc = dsi_display_phy_disable(display);
  7286. if (rc)
  7287. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  7288. display->name, rc);
  7289. }
  7290. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7291. DSI_CORE_CLK, DSI_CLK_OFF);
  7292. if (rc)
  7293. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  7294. display->name, rc);
  7295. /* destrory dsi isr set up */
  7296. dsi_display_ctrl_isr_configure(display, false);
  7297. if (!display->poms_pending && !is_skip_op_required(display)) {
  7298. rc = dsi_panel_post_unprepare(display->panel);
  7299. if (rc)
  7300. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  7301. display->name, rc);
  7302. }
  7303. display->hw_ownership = false;
  7304. mutex_unlock(&display->display_lock);
  7305. /* Free up DSI ERROR event callback */
  7306. dsi_display_unregister_error_handler(display);
  7307. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7308. return rc;
  7309. }
  7310. void __init dsi_display_register(void)
  7311. {
  7312. dsi_phy_drv_register();
  7313. dsi_ctrl_drv_register();
  7314. dsi_display_parse_boot_display_selection();
  7315. platform_driver_register(&dsi_display_driver);
  7316. }
  7317. void __exit dsi_display_unregister(void)
  7318. {
  7319. platform_driver_unregister(&dsi_display_driver);
  7320. dsi_ctrl_drv_unregister();
  7321. dsi_phy_drv_unregister();
  7322. }
  7323. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  7324. 0600);
  7325. MODULE_PARM_DESC(dsi_display0,
  7326. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  7327. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  7328. 0600);
  7329. MODULE_PARM_DESC(dsi_display1,
  7330. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");