304e2cf9c0
For FW to hold debug info. Simplify driver structure for easy dump in T32. Change-Id: Ib310a3d9fe3437d5ce49783eb813fbb2d8bd3216 Signed-off-by: George Shen <quic_sqiao@quicinc.com>
550 行
15 KiB
C
550 行
15 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*/
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#include "msm_cvp.h"
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#include "cvp_power.h"
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static inline int find_max(unsigned long *array, unsigned int num)
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{
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int i, max = 0;
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for (i = 0; i < num; i++)
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max = array[i] > max ? array[i] : max;
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return max;
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}
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static bool is_subblock_profile_existed(struct msm_cvp_inst *inst)
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{
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return (inst->prop.cycles[HFI_HW_OD] ||
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inst->prop.cycles[HFI_HW_MPU] ||
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inst->prop.cycles[HFI_HW_FDU] ||
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inst->prop.cycles[HFI_HW_ICA] ||
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inst->prop.cycles[HFI_HW_VADL] ||
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inst->prop.cycles[HFI_HW_TOF] ||
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inst->prop.cycles[HFI_HW_RGE] ||
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inst->prop.cycles[HFI_HW_XRA] ||
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inst->prop.cycles[HFI_HW_LSR]);
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}
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static char hw_names[HFI_MAX_HW_THREADS][8] = {{"FDU"}, {"OD"}, {"MPU"}, {"ICA"},
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{"VADL"}, {"TOF"}, {"RGE"}, {"XRA"},
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{"LSR"}};
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static void aggregate_power_update(struct msm_cvp_core *core,
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struct cvp_power_level *nrt_pwr,
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struct cvp_power_level *rt_pwr,
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unsigned int max_clk_rate)
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{
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struct msm_cvp_inst *inst;
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int i, j;
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unsigned long blocks_sum[2][HFI_MAX_HW_THREADS] = {0};
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unsigned long fw_sum[2] = {0}, max_cycle[2] = {0}, op_max_cycle[2] = {0};
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unsigned long op_blocks_max[2][HFI_MAX_HW_THREADS] = {0};
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unsigned long op_fw_max[2] = {0}, bw_sum[2] = {0}, op_bw_max[2] = {0};
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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core->dyn_clk.sum_fps[j] = 0;
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list_for_each_entry(inst, &core->instances, list) {
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if (inst->state == MSM_CVP_CORE_INVALID ||
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inst->state == MSM_CVP_CORE_UNINIT ||
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!is_subblock_profile_existed(inst))
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continue;
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if (inst->prop.priority <= CVP_RT_PRIO_THRESHOLD) {
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/* Non-realtime session use index 0 */
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i = 0;
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} else {
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i = 1;
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}
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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if (inst->prop.cycles[j])
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dprintk(CVP_PWR, "pwrUpdate %s %u\n",
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hw_names[j], inst->prop.cycles[j]);
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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if (inst->prop.op_cycles[j])
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dprintk(CVP_PWR, "pwrUpdate_OP %s %u\n",
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hw_names[j], inst->prop.op_cycles[j]);
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dprintk(CVP_PWR, " fw %u fw_o %u\n", inst->prop.fw_cycles,
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inst->prop.fw_op_cycles);
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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blocks_sum[i][j] += inst->prop.cycles[j];
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fw_sum[i] += inst->prop.fw_cycles;
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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op_blocks_max[i][j] =
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(op_blocks_max[i][j] >= inst->prop.op_cycles[j]) ?
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op_blocks_max[i][j] : inst->prop.op_cycles[j];
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op_fw_max[i] =
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(op_fw_max[i] >= inst->prop.fw_op_cycles) ?
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op_fw_max[i] : inst->prop.fw_op_cycles;
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bw_sum[i] += inst->prop.ddr_bw;
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op_bw_max[i] =
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(op_bw_max[i] >= inst->prop.ddr_op_bw) ?
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op_bw_max[i] : inst->prop.ddr_op_bw;
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for (j = 0; j < HFI_MAX_HW_THREADS; j++) {
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if (inst->prop.fps[j])
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dprintk(CVP_PWR, "fps %s %d ", hw_names[j],
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inst->prop.fps[j]);
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core->dyn_clk.sum_fps[j] += inst->prop.fps[j];
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}
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for (j = 0; j < HFI_MAX_HW_THREADS; j++)
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if (core->dyn_clk.sum_fps[j])
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dprintk(CVP_PWR, "sum_fps %s %d ", hw_names[j],
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core->dyn_clk.sum_fps[j]);
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}
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for (i = 0; i < 2; i++) {
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max_cycle[i] = find_max(&blocks_sum[i][0], HFI_MAX_HW_THREADS);
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op_max_cycle[i] = find_max(&op_blocks_max[i][0], HFI_MAX_HW_THREADS);
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op_max_cycle[i] =
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(op_max_cycle[i] > max_clk_rate) ?
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max_clk_rate : op_max_cycle[i];
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bw_sum[i] = (bw_sum[i] >= op_bw_max[i]) ?
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bw_sum[i] : op_bw_max[i];
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}
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nrt_pwr->core_sum += max_cycle[0];
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nrt_pwr->op_core_sum = (nrt_pwr->op_core_sum >= op_max_cycle[0]) ?
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nrt_pwr->op_core_sum : op_max_cycle[0];
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nrt_pwr->bw_sum += bw_sum[0];
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rt_pwr->core_sum += max_cycle[1];
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rt_pwr->op_core_sum = (rt_pwr->op_core_sum >= op_max_cycle[1]) ?
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rt_pwr->op_core_sum : op_max_cycle[1];
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rt_pwr->bw_sum += bw_sum[1];
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}
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/**
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* adjust_bw_freqs(): calculate CVP clock freq and bw required to sustain
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* required use case.
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* Bandwidth vote will be best-effort, not returning error if the request
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* b/w exceeds max limit.
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* Clock vote from non-realtime sessions will be best effort, not returning
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* error if the aggreated session clock request exceeds max limit.
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* Clock vote from realtime session will be hard request. If aggregated
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* session clock request exceeds max limit, the function will return
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* error.
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*
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* Ensure caller acquires clk_lock!
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*/
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static int adjust_bw_freqs(void)
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{
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struct msm_cvp_core *core;
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struct iris_hfi_device *hdev;
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struct bus_info *bus = NULL;
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struct clock_set *clocks;
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struct clock_info *cl;
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struct allowed_clock_rates_table *tbl = NULL;
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unsigned int tbl_size;
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unsigned int cvp_min_rate, cvp_max_rate, max_bw = 0, min_bw = 0;
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struct cvp_power_level rt_pwr = {0}, nrt_pwr = {0};
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unsigned long tmp, core_sum, op_core_sum, bw_sum;
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int i, rc = 0, bus_count = 0;
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unsigned long ctrl_freq;
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core = cvp_driver->cvp_core;
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hdev = core->device->hfi_device_data;
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clocks = &core->resources.clock_set;
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cl = &clocks->clock_tbl[clocks->count - 1];
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tbl = core->resources.allowed_clks_tbl;
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tbl_size = core->resources.allowed_clks_tbl_size;
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cvp_min_rate = tbl[0].clock_rate;
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cvp_max_rate = tbl[tbl_size - 1].clock_rate;
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for (bus_count = 0; bus_count < core->resources.bus_set.count; bus_count++) {
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if (!strcmp(core->resources.bus_set.bus_tbl[bus_count].name, "cvp-ddr")) {
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bus = &core->resources.bus_set.bus_tbl[bus_count];
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max_bw = bus->range[1];
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min_bw = max_bw/10;
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}
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}
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if (!bus) {
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dprintk(CVP_ERR, "bus node is NULL for cvp-ddr\n");
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return -EINVAL;
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}
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aggregate_power_update(core, &nrt_pwr, &rt_pwr, cvp_max_rate);
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dprintk(CVP_PWR, "PwrUpdate nrt %u %u rt %u %u\n",
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nrt_pwr.core_sum, nrt_pwr.op_core_sum,
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rt_pwr.core_sum, rt_pwr.op_core_sum);
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if (rt_pwr.core_sum > cvp_max_rate) {
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dprintk(CVP_WARN, "%s clk vote out of range %lld\n",
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__func__, rt_pwr.core_sum);
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return -ENOTSUPP;
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}
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core_sum = rt_pwr.core_sum + nrt_pwr.core_sum;
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op_core_sum = (rt_pwr.op_core_sum >= nrt_pwr.op_core_sum) ?
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rt_pwr.op_core_sum : nrt_pwr.op_core_sum;
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core_sum = (core_sum >= op_core_sum) ?
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core_sum : op_core_sum;
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if (core_sum > cvp_max_rate) {
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core_sum = cvp_max_rate;
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} else if (core_sum <= cvp_min_rate) {
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core_sum = cvp_min_rate;
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} else {
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for (i = 1; i < tbl_size; i++)
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if (core_sum <= tbl[i].clock_rate)
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break;
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core_sum = tbl[i].clock_rate;
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}
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bw_sum = rt_pwr.bw_sum + nrt_pwr.bw_sum;
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bw_sum = bw_sum >> 10;
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bw_sum = (bw_sum > max_bw) ? max_bw : bw_sum;
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bw_sum = (bw_sum < min_bw) ? min_bw : bw_sum;
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dprintk(CVP_PWR, "%s %lld %lld\n", __func__,
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core_sum, bw_sum);
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if (!cl->has_scaling) {
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dprintk(CVP_ERR, "Cannot scale CVP clock\n");
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return -EINVAL;
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}
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tmp = core->curr_freq;
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core->curr_freq = core_sum;
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core->orig_core_sum = core_sum;
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rc = msm_cvp_set_clocks(core);
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if (rc) {
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dprintk(CVP_ERR,
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"Failed to set clock rate %u %s: %d %s\n",
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core_sum, cl->name, rc, __func__);
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core->curr_freq = tmp;
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return rc;
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}
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ctrl_freq = (core->curr_freq*3)>>1;
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core->dyn_clk.conf_freq = core->curr_freq;
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for (i = 0; i < HFI_MAX_HW_THREADS; ++i) {
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core->dyn_clk.hi_ctrl_lim[i] = core->dyn_clk.sum_fps[i] ?
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ctrl_freq/core->dyn_clk.sum_fps[i] : 0;
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core->dyn_clk.lo_ctrl_lim[i] =
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core->dyn_clk.hi_ctrl_lim[i];
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}
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hdev->clk_freq = core->curr_freq;
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rc = msm_cvp_set_bw(bus, bw_sum);
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return rc;
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}
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int msm_cvp_update_power(struct msm_cvp_inst *inst)
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{
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int rc = 0;
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struct msm_cvp_core *core;
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struct msm_cvp_inst *s;
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if (!inst) {
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dprintk(CVP_ERR, "%s: invalid params\n", __func__);
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return -EINVAL;
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}
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s = cvp_get_inst_validate(inst->core, inst);
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if (!s)
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return -ECONNRESET;
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core = inst->core;
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mutex_lock(&core->clk_lock);
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rc = adjust_bw_freqs();
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mutex_unlock(&core->clk_lock);
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cvp_put_inst(s);
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return rc;
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}
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static int cvp_readjust_clock(struct msm_cvp_core *core,
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u32 avg_cycles, enum hfi_hw_thread i)
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{
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int rc = 0;
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struct allowed_clock_rates_table *tbl = NULL;
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unsigned int tbl_size = 0;
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unsigned int cvp_min_rate = 0, cvp_max_rate = 0;
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unsigned long tmp = core->curr_freq;
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unsigned long lo_freq = 0;
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u32 j;
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tbl = core->resources.allowed_clks_tbl;
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tbl_size = core->resources.allowed_clks_tbl_size;
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cvp_min_rate = tbl[0].clock_rate;
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cvp_max_rate = tbl[tbl_size - 1].clock_rate;
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if (!((avg_cycles > core->dyn_clk.hi_ctrl_lim[i] &&
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core->curr_freq != cvp_max_rate) ||
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(avg_cycles <= core->dyn_clk.lo_ctrl_lim[i] &&
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core->curr_freq != cvp_min_rate))) {
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return rc;
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}
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core->curr_freq = ((avg_cycles * core->dyn_clk.sum_fps[i]) << 1)/3;
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dprintk(CVP_PWR,
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"%s - cycles tot %u, avg %u. sum_fps %u, cur_freq %u\n",
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__func__,
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core->dyn_clk.cycle[i].total,
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avg_cycles,
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core->dyn_clk.sum_fps[i],
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core->curr_freq);
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if (core->curr_freq > cvp_max_rate) {
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core->curr_freq = cvp_max_rate;
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lo_freq = (tbl_size > 1) ?
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tbl[tbl_size - 2].clock_rate :
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cvp_min_rate;
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} else if (core->curr_freq <= cvp_min_rate) {
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core->curr_freq = cvp_min_rate;
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lo_freq = cvp_min_rate;
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} else {
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for (j = 1; j < tbl_size; j++)
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if (core->curr_freq <= tbl[j].clock_rate)
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break;
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core->curr_freq = tbl[j].clock_rate;
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lo_freq = tbl[j-1].clock_rate;
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}
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if (core->orig_core_sum > core->curr_freq) {
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dprintk(CVP_PWR,
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"%s - %d - Cancel readjust, core %u, freq %u\n",
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__func__, i, core->orig_core_sum, core->curr_freq);
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core->curr_freq = tmp;
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return rc;
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}
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dprintk(CVP_PWR,
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"%s:%d - %d - Readjust to %u\n",
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__func__, __LINE__, i, core->curr_freq);
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rc = msm_cvp_set_clocks(core);
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if (rc) {
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dprintk(CVP_ERR,
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"Failed to set clock rate %u: %d %s\n",
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core->curr_freq, rc, __func__);
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core->curr_freq = tmp;
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} else {
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lo_freq = (lo_freq < core->dyn_clk.conf_freq) ?
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core->dyn_clk.conf_freq : lo_freq;
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core->dyn_clk.hi_ctrl_lim[i] = core->dyn_clk.sum_fps[i] ?
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((core->curr_freq*3)>>1)/core->dyn_clk.sum_fps[i] : 0;
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core->dyn_clk.lo_ctrl_lim[i] =
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core->dyn_clk.sum_fps[i] ?
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((lo_freq*3)>>1)/core->dyn_clk.sum_fps[i] : 0;
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dprintk(CVP_PWR,
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"%s - Readjust clk to %u. New lim [%d] hi %u lo %u\n",
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__func__, core->curr_freq, i,
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core->dyn_clk.hi_ctrl_lim[i],
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core->dyn_clk.lo_ctrl_lim[i]);
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}
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return rc;
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}
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int cvp_check_clock(struct msm_cvp_inst *inst,
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struct cvp_hfi_msg_session_hdr_ext *hdr)
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{
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int rc = 0;
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u32 i, j;
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u32 hw_cycles[HFI_MAX_HW_THREADS] = {0};
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u32 fw_cycles = 0;
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struct msm_cvp_core *core = inst->core;
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for (i = 0; i < HFI_MAX_HW_ACTIVATIONS_PER_FRAME; ++i)
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fw_cycles += hdr->fw_cycles[i];
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for (i = 0; i < HFI_MAX_HW_THREADS; ++i)
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for (j = 0; j < HFI_MAX_HW_ACTIVATIONS_PER_FRAME; ++j)
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hw_cycles[i] += hdr->hw_cycles[i][j];
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dprintk(CVP_PWR, "%s - cycles fw %u. FDU %d MPU %d ODU %d ICA %d\n",
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__func__, fw_cycles, hw_cycles[0],
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hw_cycles[1], hw_cycles[2], hw_cycles[3]);
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mutex_lock(&core->clk_lock);
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for (i = 0; i < HFI_MAX_HW_THREADS; ++i) {
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dprintk(CVP_PWR, "%s - %d: hw_cycles %u, tens_thresh %u\n",
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__func__, i, hw_cycles[i],
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core->dyn_clk.hi_ctrl_lim[i]);
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if (core->dyn_clk.hi_ctrl_lim[i]) {
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if (core->dyn_clk.cycle[i].size < CVP_CYCLE_STAT_SIZE)
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core->dyn_clk.cycle[i].size++;
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else
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core->dyn_clk.cycle[i].total -=
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core->dyn_clk.cycle[i].busy[
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core->dyn_clk.cycle[i].idx];
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if (hw_cycles[i]) {
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core->dyn_clk.cycle[i].busy[
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core->dyn_clk.cycle[i].idx]
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= hw_cycles[i] + fw_cycles;
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core->dyn_clk.cycle[i].total
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+= hw_cycles[i] + fw_cycles;
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dprintk(CVP_PWR,
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"%s: busy (hw + fw) cycles = %u\n",
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__func__,
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core->dyn_clk.cycle[i].busy[
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core->dyn_clk.cycle[i].idx]);
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dprintk(CVP_PWR, "total cycles %u\n",
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core->dyn_clk.cycle[i].total);
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} else {
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core->dyn_clk.cycle[i].busy[
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core->dyn_clk.cycle[i].idx] =
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hdr->busy_cycles;
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core->dyn_clk.cycle[i].total +=
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hdr->busy_cycles;
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dprintk(CVP_PWR,
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"%s - busy cycles = %u total %u\n",
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__func__,
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core->dyn_clk.cycle[i].busy[
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core->dyn_clk.cycle[i].idx],
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core->dyn_clk.cycle[i].total);
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}
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core->dyn_clk.cycle[i].idx =
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(core->dyn_clk.cycle[i].idx ==
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CVP_CYCLE_STAT_SIZE-1) ?
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0 : core->dyn_clk.cycle[i].idx+1;
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dprintk(CVP_PWR, "%s - %d: size %u, tens_thresh %u\n",
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__func__, i, core->dyn_clk.cycle[i].size,
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core->dyn_clk.hi_ctrl_lim[i]);
|
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if (core->dyn_clk.cycle[i].size == CVP_CYCLE_STAT_SIZE
|
|
&& core->dyn_clk.hi_ctrl_lim[i] != 0) {
|
|
u32 avg_cycles =
|
|
core->dyn_clk.cycle[i].total>>3;
|
|
|
|
rc = cvp_readjust_clock(core,
|
|
avg_cycles,
|
|
i);
|
|
}
|
|
}
|
|
}
|
|
mutex_unlock(&core->clk_lock);
|
|
|
|
return rc;
|
|
}
|
|
|
|
unsigned int msm_cvp_get_hw_aggregate_cycles(enum hfi_hw_thread hwblk)
|
|
{
|
|
struct msm_cvp_core *core;
|
|
struct msm_cvp_inst *inst;
|
|
unsigned long cycles_sum = 0;
|
|
|
|
core = cvp_driver->cvp_core;
|
|
|
|
if (!core) {
|
|
dprintk(CVP_ERR, "%s: invalid core\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
mutex_lock(&core->clk_lock);
|
|
list_for_each_entry(inst, &core->instances, list) {
|
|
if (inst->state == MSM_CVP_CORE_INVALID ||
|
|
inst->state == MSM_CVP_CORE_UNINIT ||
|
|
!is_subblock_profile_existed(inst))
|
|
continue;
|
|
switch (hwblk) {
|
|
case HFI_HW_FDU:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_FDU];
|
|
break;
|
|
}
|
|
case HFI_HW_ICA:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_ICA];
|
|
break;
|
|
}
|
|
case HFI_HW_MPU:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_MPU];
|
|
break;
|
|
}
|
|
case HFI_HW_OD:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_OD];
|
|
break;
|
|
}
|
|
case HFI_HW_VADL:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_VADL];
|
|
break;
|
|
}
|
|
case HFI_HW_TOF:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_TOF];
|
|
break;
|
|
}
|
|
case HFI_HW_RGE:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_RGE];
|
|
break;
|
|
}
|
|
case HFI_HW_XRA:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_XRA];
|
|
break;
|
|
}
|
|
case HFI_HW_LSR:
|
|
{
|
|
cycles_sum += inst->prop.cycles[HFI_HW_LSR];
|
|
break;
|
|
}
|
|
default:
|
|
dprintk(CVP_ERR, "unrecognized hw block %d\n",
|
|
hwblk);
|
|
break;
|
|
}
|
|
}
|
|
mutex_unlock(&core->clk_lock);
|
|
cycles_sum = cycles_sum&0xFFFFFFFF;
|
|
return (unsigned int)cycles_sum;
|
|
}
|
|
|
|
bool check_clock_required(struct msm_cvp_inst *inst,
|
|
struct eva_kmd_hfi_packet *hdr)
|
|
{
|
|
struct cvp_hfi_msg_session_hdr_ext *ehdr =
|
|
(struct cvp_hfi_msg_session_hdr_ext *)hdr;
|
|
bool clock_check = false;
|
|
|
|
if (!msm_cvp_dcvs_disable &&
|
|
ehdr->packet_type == HFI_MSG_SESSION_CVP_FD) {
|
|
if (ehdr->size == sizeof(struct cvp_hfi_msg_session_hdr_ext)
|
|
+ sizeof(struct cvp_hfi_buf_type)) {
|
|
struct msm_cvp_core *core = inst->core;
|
|
|
|
dprintk(CVP_PWR, "busy cycle %d, total %d\n",
|
|
ehdr->busy_cycles, ehdr->total_cycles);
|
|
|
|
if (core->dyn_clk.sum_fps[HFI_HW_FDU] ||
|
|
core->dyn_clk.sum_fps[HFI_HW_MPU] ||
|
|
core->dyn_clk.sum_fps[HFI_HW_OD] ||
|
|
core->dyn_clk.sum_fps[HFI_HW_ICA]) {
|
|
clock_check = true;
|
|
}
|
|
} else {
|
|
dprintk(CVP_WARN, "dcvs is disabled, %d != %d + %d\n",
|
|
ehdr->size, sizeof(struct cvp_hfi_msg_session_hdr_ext),
|
|
sizeof(struct cvp_hfi_buf_type));
|
|
}
|
|
}
|
|
|
|
return clock_check;
|
|
}
|
|
|
|
|