main.c 111 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/version.h>
  20. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  21. #include <linux/panic_notifier.h>
  22. #endif
  23. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  24. #include <soc/qcom/minidump.h>
  25. #endif
  26. #include "cnss_plat_ipc_qmi.h"
  27. #include "cnss_utils.h"
  28. #include "main.h"
  29. #include "bus.h"
  30. #include "debug.h"
  31. #include "genl.h"
  32. #include "reg.h"
  33. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  34. #include "smcinvoke.h"
  35. #include "smcinvoke_object.h"
  36. #include "IClientEnv.h"
  37. #define HW_STATE_UID 0x108
  38. #define HW_OP_GET_STATE 1
  39. #define HW_WIFI_UID 0x508
  40. #define FEATURE_NOT_SUPPORTED 12
  41. #define PERIPHERAL_NOT_FOUND 10
  42. #endif
  43. #define CNSS_DUMP_FORMAT_VER 0x11
  44. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  45. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  46. #define CNSS_DUMP_NAME "CNSS_WLAN"
  47. #define CNSS_DUMP_DESC_SIZE 0x1000
  48. #define CNSS_DUMP_SEG_VER 0x1
  49. #define FILE_SYSTEM_READY 1
  50. #define FW_READY_TIMEOUT 20000
  51. #define FW_ASSERT_TIMEOUT 5000
  52. #define CNSS_EVENT_PENDING 2989
  53. #define POWER_RESET_MIN_DELAY_MS 100
  54. #define CNSS_QUIRKS_DEFAULT 0
  55. #ifdef CONFIG_CNSS_EMULATION
  56. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  57. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  58. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  59. #else
  60. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  61. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  62. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  63. #endif
  64. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  65. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  66. #define CNSS_MIN_TIME_SYNC_PERIOD 2000
  67. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  68. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  69. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  70. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  71. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  72. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  73. enum cnss_cal_db_op {
  74. CNSS_CAL_DB_UPLOAD,
  75. CNSS_CAL_DB_DOWNLOAD,
  76. CNSS_CAL_DB_INVALID_OP,
  77. };
  78. enum cnss_recovery_type {
  79. CNSS_WLAN_RECOVERY = 0x1,
  80. CNSS_PCSS_RECOVERY = 0x2,
  81. };
  82. static struct cnss_plat_data *plat_env;
  83. static bool cnss_allow_driver_loading;
  84. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  85. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  86. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  87. };
  88. static struct cnss_fw_files FW_FILES_DEFAULT = {
  89. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  90. "utfbd.bin", "epping.bin", "evicted.bin"
  91. };
  92. struct cnss_driver_event {
  93. struct list_head list;
  94. enum cnss_driver_event_type type;
  95. bool sync;
  96. struct completion complete;
  97. int ret;
  98. void *data;
  99. };
  100. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  101. struct cnss_plat_data *plat_priv)
  102. {
  103. plat_env = plat_priv;
  104. }
  105. bool cnss_check_driver_loading_allowed(void)
  106. {
  107. return cnss_allow_driver_loading;
  108. }
  109. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  110. {
  111. return plat_env;
  112. }
  113. /**
  114. * cnss_get_mem_seg_count - Get segment count of memory
  115. * @type: memory type
  116. * @seg: segment count
  117. *
  118. * Return: 0 on success, negative value on failure
  119. */
  120. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  121. {
  122. struct cnss_plat_data *plat_priv;
  123. plat_priv = cnss_get_plat_priv(NULL);
  124. if (!plat_priv)
  125. return -ENODEV;
  126. switch (type) {
  127. case CNSS_REMOTE_MEM_TYPE_FW:
  128. *seg = plat_priv->fw_mem_seg_len;
  129. break;
  130. case CNSS_REMOTE_MEM_TYPE_QDSS:
  131. *seg = plat_priv->qdss_mem_seg_len;
  132. break;
  133. default:
  134. return -EINVAL;
  135. }
  136. return 0;
  137. }
  138. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  139. /**
  140. * cnss_get_wifi_kobject -return wifi kobject
  141. * Return: Null, to maintain driver comnpatibilty
  142. */
  143. struct kobject *cnss_get_wifi_kobj(struct device *dev)
  144. {
  145. struct cnss_plat_data *plat_priv;
  146. plat_priv = cnss_get_plat_priv(NULL);
  147. if (!plat_priv)
  148. return NULL;
  149. return plat_priv->wifi_kobj;
  150. }
  151. EXPORT_SYMBOL(cnss_get_wifi_kobj);
  152. /**
  153. * cnss_get_mem_segment_info - Get memory info of different type
  154. * @type: memory type
  155. * @segment: array to save the segment info
  156. * @seg: segment count
  157. *
  158. * Return: 0 on success, negative value on failure
  159. */
  160. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  161. struct cnss_mem_segment segment[],
  162. u32 segment_count)
  163. {
  164. struct cnss_plat_data *plat_priv;
  165. u32 i;
  166. plat_priv = cnss_get_plat_priv(NULL);
  167. if (!plat_priv)
  168. return -ENODEV;
  169. switch (type) {
  170. case CNSS_REMOTE_MEM_TYPE_FW:
  171. if (segment_count > plat_priv->fw_mem_seg_len)
  172. segment_count = plat_priv->fw_mem_seg_len;
  173. for (i = 0; i < segment_count; i++) {
  174. segment[i].size = plat_priv->fw_mem[i].size;
  175. segment[i].va = plat_priv->fw_mem[i].va;
  176. segment[i].pa = plat_priv->fw_mem[i].pa;
  177. }
  178. break;
  179. case CNSS_REMOTE_MEM_TYPE_QDSS:
  180. if (segment_count > plat_priv->qdss_mem_seg_len)
  181. segment_count = plat_priv->qdss_mem_seg_len;
  182. for (i = 0; i < segment_count; i++) {
  183. segment[i].size = plat_priv->qdss_mem[i].size;
  184. segment[i].va = plat_priv->qdss_mem[i].va;
  185. segment[i].pa = plat_priv->qdss_mem[i].pa;
  186. }
  187. break;
  188. default:
  189. return -EINVAL;
  190. }
  191. return 0;
  192. }
  193. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  194. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  195. enum cnss_feature_v01 feature)
  196. {
  197. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  198. return -EINVAL;
  199. plat_priv->feature_list |= 1 << feature;
  200. return 0;
  201. }
  202. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  203. enum cnss_feature_v01 feature)
  204. {
  205. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  206. return -EINVAL;
  207. plat_priv->feature_list &= ~(1 << feature);
  208. return 0;
  209. }
  210. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  211. u64 *feature_list)
  212. {
  213. if (unlikely(!plat_priv))
  214. return -EINVAL;
  215. *feature_list = plat_priv->feature_list;
  216. return 0;
  217. }
  218. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  219. {
  220. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  221. return;
  222. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  223. plat_priv->driver_state,
  224. atomic_read(&plat_priv->pm_count));
  225. pm_stay_awake(&plat_priv->plat_dev->dev);
  226. }
  227. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  228. {
  229. int r = atomic_dec_return(&plat_priv->pm_count);
  230. WARN_ON(r < 0);
  231. if (r != 0)
  232. return;
  233. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  234. plat_priv->driver_state,
  235. atomic_read(&plat_priv->pm_count));
  236. pm_relax(&plat_priv->plat_dev->dev);
  237. }
  238. int cnss_get_fw_files_for_target(struct device *dev,
  239. struct cnss_fw_files *pfw_files,
  240. u32 target_type, u32 target_version)
  241. {
  242. if (!pfw_files)
  243. return -ENODEV;
  244. switch (target_version) {
  245. case QCA6174_REV3_VERSION:
  246. case QCA6174_REV3_2_VERSION:
  247. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  248. break;
  249. default:
  250. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  251. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  252. target_type, target_version);
  253. break;
  254. }
  255. return 0;
  256. }
  257. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  258. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  259. {
  260. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  261. if (!plat_priv)
  262. return -ENODEV;
  263. if (!cap)
  264. return -EINVAL;
  265. *cap = plat_priv->cap;
  266. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  267. return 0;
  268. }
  269. EXPORT_SYMBOL(cnss_get_platform_cap);
  270. /**
  271. * cnss_get_fw_cap - Check whether FW supports specific capability or not
  272. * @dev: Device
  273. * @fw_cap: FW Capability which needs to be checked
  274. *
  275. * Return: TRUE if supported, FALSE on failure or if not supported
  276. */
  277. bool cnss_get_fw_cap(struct device *dev, enum cnss_fw_caps fw_cap)
  278. {
  279. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  280. bool ret = false;
  281. if (!plat_priv)
  282. return ret;
  283. if (!plat_priv->fw_caps)
  284. return ret;
  285. switch (fw_cap) {
  286. case CNSS_FW_CAP_DIRECT_LINK_SUPPORT:
  287. ret = !!(plat_priv->fw_caps &
  288. QMI_WLFW_DIRECT_LINK_SUPPORT_V01);
  289. break;
  290. default:
  291. cnss_pr_err("Invalid FW Capability: 0x%x\n", fw_cap);
  292. }
  293. cnss_pr_dbg("FW Capability 0x%x is %s\n", fw_cap,
  294. ret ? "supported" : "not supported");
  295. return ret;
  296. }
  297. EXPORT_SYMBOL(cnss_get_fw_cap);
  298. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  299. {
  300. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  301. if (!plat_priv)
  302. return;
  303. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  304. }
  305. EXPORT_SYMBOL(cnss_request_pm_qos);
  306. void cnss_remove_pm_qos(struct device *dev)
  307. {
  308. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  309. if (!plat_priv)
  310. return;
  311. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  312. }
  313. EXPORT_SYMBOL(cnss_remove_pm_qos);
  314. int cnss_wlan_enable(struct device *dev,
  315. struct cnss_wlan_enable_cfg *config,
  316. enum cnss_driver_mode mode,
  317. const char *host_version)
  318. {
  319. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  320. int ret = 0;
  321. if (!plat_priv)
  322. return -ENODEV;
  323. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  324. return 0;
  325. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  326. return 0;
  327. if (!config || !host_version) {
  328. cnss_pr_err("Invalid config or host_version pointer\n");
  329. return -EINVAL;
  330. }
  331. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  332. mode, config, host_version);
  333. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  334. goto skip_cfg;
  335. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  336. if (ret)
  337. goto out;
  338. skip_cfg:
  339. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  340. out:
  341. return ret;
  342. }
  343. EXPORT_SYMBOL(cnss_wlan_enable);
  344. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  345. {
  346. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  347. int ret = 0;
  348. if (!plat_priv)
  349. return -ENODEV;
  350. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  351. return 0;
  352. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  353. return 0;
  354. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  355. cnss_bus_free_qdss_mem(plat_priv);
  356. return ret;
  357. }
  358. EXPORT_SYMBOL(cnss_wlan_disable);
  359. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  360. u32 data_len, u8 *output)
  361. {
  362. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  363. int ret = 0;
  364. if (!plat_priv) {
  365. cnss_pr_err("plat_priv is NULL!\n");
  366. return -EINVAL;
  367. }
  368. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  369. return 0;
  370. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  371. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  372. plat_priv->driver_state);
  373. ret = -EINVAL;
  374. goto out;
  375. }
  376. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  377. data_len, output);
  378. out:
  379. return ret;
  380. }
  381. EXPORT_SYMBOL(cnss_athdiag_read);
  382. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  383. u32 data_len, u8 *input)
  384. {
  385. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  386. int ret = 0;
  387. if (!plat_priv) {
  388. cnss_pr_err("plat_priv is NULL!\n");
  389. return -EINVAL;
  390. }
  391. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  392. return 0;
  393. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  394. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  395. plat_priv->driver_state);
  396. ret = -EINVAL;
  397. goto out;
  398. }
  399. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  400. data_len, input);
  401. out:
  402. return ret;
  403. }
  404. EXPORT_SYMBOL(cnss_athdiag_write);
  405. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  406. {
  407. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  408. if (!plat_priv)
  409. return -ENODEV;
  410. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  411. return 0;
  412. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  413. }
  414. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  415. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  416. {
  417. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  418. if (!plat_priv)
  419. return -EINVAL;
  420. if (!plat_priv->fw_pcie_gen_switch) {
  421. cnss_pr_err("Firmware does not support PCIe gen switch\n");
  422. return -EOPNOTSUPP;
  423. }
  424. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  425. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  426. return -EINVAL;
  427. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  428. plat_priv->pcie_gen_speed = pcie_gen_speed;
  429. return 0;
  430. }
  431. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  432. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  433. {
  434. int ret = 0;
  435. if (!plat_priv)
  436. return -ENODEV;
  437. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  438. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  439. if (ret)
  440. goto out;
  441. if (plat_priv->hds_enabled)
  442. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  443. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  444. cnss_wlfw_ini_file_send_sync(plat_priv, WLFW_CONN_ROAM_INI_V01);
  445. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  446. plat_priv->ctrl_params.bdf_type);
  447. if (ret)
  448. goto out;
  449. ret = cnss_bus_load_m3(plat_priv);
  450. if (ret)
  451. goto out;
  452. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  453. if (ret)
  454. goto out;
  455. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  456. return 0;
  457. out:
  458. return ret;
  459. }
  460. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  461. {
  462. int ret = 0;
  463. if (!plat_priv->antenna) {
  464. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  465. if (ret)
  466. goto out;
  467. }
  468. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  469. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  470. if (ret)
  471. goto out;
  472. }
  473. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  474. if (ret)
  475. goto out;
  476. return 0;
  477. out:
  478. return ret;
  479. }
  480. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  481. {
  482. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  483. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  484. }
  485. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  486. {
  487. u32 i;
  488. int ret = 0;
  489. struct cnss_plat_ipc_daemon_config *cfg;
  490. ret = cnss_qmi_get_dms_mac(plat_priv);
  491. if (ret == 0 && plat_priv->dms.mac_valid)
  492. goto qmi_send;
  493. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  494. * Thus assert on failure to get MAC from DMS even after retries
  495. */
  496. if (plat_priv->use_nv_mac) {
  497. /* Check if Daemon says platform support DMS MAC provisioning */
  498. cfg = cnss_plat_ipc_qmi_daemon_config();
  499. if (cfg) {
  500. if (!cfg->dms_mac_addr_supported) {
  501. cnss_pr_err("DMS MAC address not supported\n");
  502. CNSS_ASSERT(0);
  503. return -EINVAL;
  504. }
  505. }
  506. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  507. if (plat_priv->dms.mac_valid)
  508. break;
  509. ret = cnss_qmi_get_dms_mac(plat_priv);
  510. if (ret == 0)
  511. break;
  512. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  513. }
  514. if (!plat_priv->dms.mac_valid) {
  515. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  516. CNSS_ASSERT(0);
  517. return -EINVAL;
  518. }
  519. }
  520. qmi_send:
  521. if (plat_priv->dms.mac_valid)
  522. ret =
  523. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  524. ARRAY_SIZE(plat_priv->dms.mac));
  525. return ret;
  526. }
  527. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  528. enum cnss_cal_db_op op, u32 *size)
  529. {
  530. int ret = 0;
  531. u32 timeout = cnss_get_timeout(plat_priv,
  532. CNSS_TIMEOUT_DAEMON_CONNECTION);
  533. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  534. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  535. if (op >= CNSS_CAL_DB_INVALID_OP)
  536. return -EINVAL;
  537. if (!plat_priv->cbc_file_download) {
  538. cnss_pr_info("CAL DB file not required as per BDF\n");
  539. return 0;
  540. }
  541. if (*size == 0) {
  542. cnss_pr_err("Invalid cal file size\n");
  543. return -EINVAL;
  544. }
  545. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  546. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  547. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  548. msecs_to_jiffies(timeout));
  549. if (!ret) {
  550. cnss_pr_err("Daemon not yet connected\n");
  551. CNSS_ASSERT(0);
  552. return ret;
  553. }
  554. }
  555. if (!plat_priv->cal_mem->va) {
  556. cnss_pr_err("CAL DB Memory not setup for FW\n");
  557. return -EINVAL;
  558. }
  559. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  560. if (op == CNSS_CAL_DB_DOWNLOAD) {
  561. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  562. ret = cnss_plat_ipc_qmi_file_download(client_id,
  563. CNSS_CAL_DB_FILE_NAME,
  564. plat_priv->cal_mem->va,
  565. size);
  566. } else {
  567. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  568. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  569. CNSS_CAL_DB_FILE_NAME,
  570. plat_priv->cal_mem->va,
  571. *size);
  572. }
  573. if (ret)
  574. cnss_pr_err("Cal DB file %s %s failure\n",
  575. CNSS_CAL_DB_FILE_NAME,
  576. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  577. else
  578. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  579. CNSS_CAL_DB_FILE_NAME,
  580. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  581. *size);
  582. return ret;
  583. }
  584. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  585. {
  586. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  587. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  588. return -EINVAL;
  589. }
  590. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  591. &plat_priv->cal_file_size);
  592. }
  593. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  594. u32 *cal_file_size)
  595. {
  596. /* To download pass the total size of cal DB mem allocated.
  597. * After cal file is download to mem, its size is updated in
  598. * return pointer
  599. */
  600. *cal_file_size = plat_priv->cal_mem->size;
  601. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  602. cal_file_size);
  603. }
  604. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  605. {
  606. int ret = 0;
  607. u32 cal_file_size = 0;
  608. if (!plat_priv)
  609. return -ENODEV;
  610. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  611. cnss_pr_err("Reboot is in progress, ignore FW ready\n");
  612. return -EINVAL;
  613. }
  614. cnss_pr_dbg("Processing FW Init Done..\n");
  615. del_timer(&plat_priv->fw_boot_timer);
  616. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  617. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  618. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  619. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  620. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  621. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  622. }
  623. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  624. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  625. CNSS_WALTEST);
  626. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  627. cnss_request_antenna_sharing(plat_priv);
  628. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  629. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  630. plat_priv->cal_time = jiffies;
  631. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  632. CNSS_CALIBRATION);
  633. } else {
  634. ret = cnss_setup_dms_mac(plat_priv);
  635. ret = cnss_bus_call_driver_probe(plat_priv);
  636. }
  637. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  638. goto out;
  639. else if (ret)
  640. goto shutdown;
  641. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  642. return 0;
  643. shutdown:
  644. cnss_bus_dev_shutdown(plat_priv);
  645. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  646. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  647. out:
  648. return ret;
  649. }
  650. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  651. {
  652. switch (type) {
  653. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  654. return "SERVER_ARRIVE";
  655. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  656. return "SERVER_EXIT";
  657. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  658. return "REQUEST_MEM";
  659. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  660. return "FW_MEM_READY";
  661. case CNSS_DRIVER_EVENT_FW_READY:
  662. return "FW_READY";
  663. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  664. return "COLD_BOOT_CAL_START";
  665. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  666. return "COLD_BOOT_CAL_DONE";
  667. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  668. return "REGISTER_DRIVER";
  669. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  670. return "UNREGISTER_DRIVER";
  671. case CNSS_DRIVER_EVENT_RECOVERY:
  672. return "RECOVERY";
  673. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  674. return "FORCE_FW_ASSERT";
  675. case CNSS_DRIVER_EVENT_POWER_UP:
  676. return "POWER_UP";
  677. case CNSS_DRIVER_EVENT_POWER_DOWN:
  678. return "POWER_DOWN";
  679. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  680. return "IDLE_RESTART";
  681. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  682. return "IDLE_SHUTDOWN";
  683. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  684. return "IMS_WFC_CALL_IND";
  685. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  686. return "WLFW_TWC_CFG_IND";
  687. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  688. return "QDSS_TRACE_REQ_MEM";
  689. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  690. return "FW_MEM_FILE_SAVE";
  691. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  692. return "QDSS_TRACE_FREE";
  693. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  694. return "QDSS_TRACE_REQ_DATA";
  695. case CNSS_DRIVER_EVENT_MAX:
  696. return "EVENT_MAX";
  697. }
  698. return "UNKNOWN";
  699. };
  700. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  701. enum cnss_driver_event_type type,
  702. u32 flags, void *data)
  703. {
  704. struct cnss_driver_event *event;
  705. unsigned long irq_flags;
  706. int gfp = GFP_KERNEL;
  707. int ret = 0;
  708. if (!plat_priv)
  709. return -ENODEV;
  710. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  711. cnss_driver_event_to_str(type), type,
  712. flags ? "-sync" : "", plat_priv->driver_state, flags);
  713. if (type >= CNSS_DRIVER_EVENT_MAX) {
  714. cnss_pr_err("Invalid Event type: %d, can't post", type);
  715. return -EINVAL;
  716. }
  717. if (in_interrupt() || irqs_disabled())
  718. gfp = GFP_ATOMIC;
  719. event = kzalloc(sizeof(*event), gfp);
  720. if (!event)
  721. return -ENOMEM;
  722. cnss_pm_stay_awake(plat_priv);
  723. event->type = type;
  724. event->data = data;
  725. init_completion(&event->complete);
  726. event->ret = CNSS_EVENT_PENDING;
  727. event->sync = !!(flags & CNSS_EVENT_SYNC);
  728. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  729. list_add_tail(&event->list, &plat_priv->event_list);
  730. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  731. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  732. if (!(flags & CNSS_EVENT_SYNC))
  733. goto out;
  734. if (flags & CNSS_EVENT_UNKILLABLE)
  735. wait_for_completion(&event->complete);
  736. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  737. ret = wait_for_completion_killable(&event->complete);
  738. else
  739. ret = wait_for_completion_interruptible(&event->complete);
  740. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  741. cnss_driver_event_to_str(type), type,
  742. plat_priv->driver_state, ret, event->ret);
  743. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  744. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  745. event->sync = false;
  746. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  747. ret = -EINTR;
  748. goto out;
  749. }
  750. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  751. ret = event->ret;
  752. kfree(event);
  753. out:
  754. cnss_pm_relax(plat_priv);
  755. return ret;
  756. }
  757. /**
  758. * cnss_get_timeout - Get timeout for corresponding type.
  759. * @plat_priv: Pointer to platform driver context.
  760. * @cnss_timeout_type: Timeout type.
  761. *
  762. * Return: Timeout in milliseconds.
  763. */
  764. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  765. enum cnss_timeout_type timeout_type)
  766. {
  767. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  768. switch (timeout_type) {
  769. case CNSS_TIMEOUT_QMI:
  770. return qmi_timeout;
  771. case CNSS_TIMEOUT_POWER_UP:
  772. return (qmi_timeout << 2);
  773. case CNSS_TIMEOUT_IDLE_RESTART:
  774. /* In idle restart power up sequence, we have fw_boot_timer to
  775. * handle FW initialization failure.
  776. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  777. * account for FW dump collection and FW re-initialization on
  778. * retry.
  779. */
  780. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  781. case CNSS_TIMEOUT_CALIBRATION:
  782. /* Similar to mission mode, in CBC if FW init fails
  783. * fw recovery is tried. Thus return 2x the CBC timeout.
  784. */
  785. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  786. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  787. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  788. case CNSS_TIMEOUT_RDDM:
  789. return CNSS_RDDM_TIMEOUT_MS;
  790. case CNSS_TIMEOUT_RECOVERY:
  791. return RECOVERY_TIMEOUT;
  792. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  793. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  794. default:
  795. return qmi_timeout;
  796. }
  797. }
  798. unsigned int cnss_get_boot_timeout(struct device *dev)
  799. {
  800. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  801. if (!plat_priv) {
  802. cnss_pr_err("plat_priv is NULL\n");
  803. return 0;
  804. }
  805. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  806. }
  807. EXPORT_SYMBOL(cnss_get_boot_timeout);
  808. int cnss_power_up(struct device *dev)
  809. {
  810. int ret = 0;
  811. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  812. unsigned int timeout;
  813. if (!plat_priv) {
  814. cnss_pr_err("plat_priv is NULL\n");
  815. return -ENODEV;
  816. }
  817. cnss_pr_dbg("Powering up device\n");
  818. ret = cnss_driver_event_post(plat_priv,
  819. CNSS_DRIVER_EVENT_POWER_UP,
  820. CNSS_EVENT_SYNC, NULL);
  821. if (ret)
  822. goto out;
  823. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  824. goto out;
  825. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  826. reinit_completion(&plat_priv->power_up_complete);
  827. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  828. msecs_to_jiffies(timeout));
  829. if (!ret) {
  830. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  831. timeout);
  832. ret = -EAGAIN;
  833. goto out;
  834. }
  835. return 0;
  836. out:
  837. return ret;
  838. }
  839. EXPORT_SYMBOL(cnss_power_up);
  840. int cnss_power_down(struct device *dev)
  841. {
  842. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  843. if (!plat_priv) {
  844. cnss_pr_err("plat_priv is NULL\n");
  845. return -ENODEV;
  846. }
  847. cnss_pr_dbg("Powering down device\n");
  848. return cnss_driver_event_post(plat_priv,
  849. CNSS_DRIVER_EVENT_POWER_DOWN,
  850. CNSS_EVENT_SYNC, NULL);
  851. }
  852. EXPORT_SYMBOL(cnss_power_down);
  853. int cnss_idle_restart(struct device *dev)
  854. {
  855. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  856. unsigned int timeout;
  857. int ret = 0;
  858. if (!plat_priv) {
  859. cnss_pr_err("plat_priv is NULL\n");
  860. return -ENODEV;
  861. }
  862. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  863. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  864. return -EBUSY;
  865. }
  866. cnss_pr_dbg("Doing idle restart\n");
  867. reinit_completion(&plat_priv->power_up_complete);
  868. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  869. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  870. ret = -EINVAL;
  871. goto out;
  872. }
  873. ret = cnss_driver_event_post(plat_priv,
  874. CNSS_DRIVER_EVENT_IDLE_RESTART,
  875. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  876. if (ret)
  877. goto out;
  878. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  879. ret = cnss_bus_call_driver_probe(plat_priv);
  880. goto out;
  881. }
  882. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  883. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  884. msecs_to_jiffies(timeout));
  885. if (plat_priv->power_up_error) {
  886. ret = plat_priv->power_up_error;
  887. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  888. cnss_pr_dbg("Power up error:%d, exiting\n",
  889. plat_priv->power_up_error);
  890. goto out;
  891. }
  892. if (!ret) {
  893. /* This exception occurs after attempting retry of FW recovery.
  894. * Thus we can safely power off the device.
  895. */
  896. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  897. timeout);
  898. ret = -ETIMEDOUT;
  899. cnss_power_down(dev);
  900. CNSS_ASSERT(0);
  901. goto out;
  902. }
  903. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  904. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  905. del_timer(&plat_priv->fw_boot_timer);
  906. ret = -EINVAL;
  907. goto out;
  908. }
  909. /* In non-DRV mode, remove MHI satellite configuration. Switching to
  910. * non-DRV is supported only once after device reboots and before wifi
  911. * is turned on. We do not allow switching back to DRV.
  912. * To bring device back into DRV, user needs to reboot device.
  913. */
  914. if (test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) {
  915. cnss_pr_dbg("DRV is disabled\n");
  916. cnss_bus_disable_mhi_satellite_cfg(plat_priv);
  917. }
  918. mutex_unlock(&plat_priv->driver_ops_lock);
  919. return 0;
  920. out:
  921. mutex_unlock(&plat_priv->driver_ops_lock);
  922. return ret;
  923. }
  924. EXPORT_SYMBOL(cnss_idle_restart);
  925. int cnss_idle_shutdown(struct device *dev)
  926. {
  927. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  928. unsigned int timeout;
  929. int ret;
  930. if (!plat_priv) {
  931. cnss_pr_err("plat_priv is NULL\n");
  932. return -ENODEV;
  933. }
  934. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  935. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  936. return -EAGAIN;
  937. }
  938. cnss_pr_dbg("Doing idle shutdown\n");
  939. if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
  940. !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  941. goto skip_wait;
  942. reinit_completion(&plat_priv->recovery_complete);
  943. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY);
  944. ret = wait_for_completion_timeout(&plat_priv->recovery_complete,
  945. msecs_to_jiffies(timeout));
  946. if (!ret) {
  947. cnss_pr_err("Timeout (%ums) waiting for recovery to complete\n",
  948. timeout);
  949. CNSS_ASSERT(0);
  950. }
  951. skip_wait:
  952. return cnss_driver_event_post(plat_priv,
  953. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  954. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  955. }
  956. EXPORT_SYMBOL(cnss_idle_shutdown);
  957. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  958. {
  959. int ret = 0;
  960. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  961. if (ret) {
  962. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  963. goto out;
  964. }
  965. ret = cnss_get_clk(plat_priv);
  966. if (ret) {
  967. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  968. goto put_vreg;
  969. }
  970. ret = cnss_get_pinctrl(plat_priv);
  971. if (ret) {
  972. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  973. goto put_clk;
  974. }
  975. return 0;
  976. put_clk:
  977. cnss_put_clk(plat_priv);
  978. put_vreg:
  979. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  980. out:
  981. return ret;
  982. }
  983. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  984. {
  985. cnss_put_clk(plat_priv);
  986. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  987. }
  988. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  989. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  990. unsigned long code,
  991. void *ss_handle)
  992. {
  993. struct cnss_plat_data *plat_priv =
  994. container_of(nb, struct cnss_plat_data, modem_nb);
  995. struct cnss_esoc_info *esoc_info;
  996. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  997. if (!plat_priv)
  998. return NOTIFY_DONE;
  999. esoc_info = &plat_priv->esoc_info;
  1000. if (code == SUBSYS_AFTER_POWERUP)
  1001. esoc_info->modem_current_status = 1;
  1002. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  1003. esoc_info->modem_current_status = 0;
  1004. else
  1005. return NOTIFY_DONE;
  1006. if (!cnss_bus_call_driver_modem_status(plat_priv,
  1007. esoc_info->modem_current_status))
  1008. return NOTIFY_DONE;
  1009. return NOTIFY_OK;
  1010. }
  1011. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1012. {
  1013. int ret = 0;
  1014. struct device *dev;
  1015. struct cnss_esoc_info *esoc_info;
  1016. struct esoc_desc *esoc_desc;
  1017. const char *client_desc;
  1018. dev = &plat_priv->plat_dev->dev;
  1019. esoc_info = &plat_priv->esoc_info;
  1020. esoc_info->notify_modem_status =
  1021. of_property_read_bool(dev->of_node,
  1022. "qcom,notify-modem-status");
  1023. if (!esoc_info->notify_modem_status)
  1024. goto out;
  1025. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  1026. &client_desc);
  1027. if (ret) {
  1028. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  1029. } else {
  1030. esoc_desc = devm_register_esoc_client(dev, client_desc);
  1031. if (IS_ERR_OR_NULL(esoc_desc)) {
  1032. ret = PTR_RET(esoc_desc);
  1033. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  1034. ret);
  1035. goto out;
  1036. }
  1037. esoc_info->esoc_desc = esoc_desc;
  1038. }
  1039. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  1040. esoc_info->modem_current_status = 0;
  1041. esoc_info->modem_notify_handler =
  1042. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  1043. esoc_info->esoc_desc->name :
  1044. "modem", &plat_priv->modem_nb);
  1045. if (IS_ERR(esoc_info->modem_notify_handler)) {
  1046. ret = PTR_ERR(esoc_info->modem_notify_handler);
  1047. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  1048. ret);
  1049. goto unreg_esoc;
  1050. }
  1051. return 0;
  1052. unreg_esoc:
  1053. if (esoc_info->esoc_desc)
  1054. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1055. out:
  1056. return ret;
  1057. }
  1058. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1059. {
  1060. struct device *dev;
  1061. struct cnss_esoc_info *esoc_info;
  1062. dev = &plat_priv->plat_dev->dev;
  1063. esoc_info = &plat_priv->esoc_info;
  1064. if (esoc_info->notify_modem_status)
  1065. subsys_notif_unregister_notifier
  1066. (esoc_info->modem_notify_handler,
  1067. &plat_priv->modem_nb);
  1068. if (esoc_info->esoc_desc)
  1069. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1070. }
  1071. #else
  1072. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1073. {
  1074. return 0;
  1075. }
  1076. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1077. #endif
  1078. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1079. {
  1080. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1081. int ret = 0;
  1082. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1083. return 0;
  1084. enable_irq(sol_gpio->dev_sol_irq);
  1085. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1086. if (ret)
  1087. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1088. ret);
  1089. return ret;
  1090. }
  1091. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1092. {
  1093. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1094. int ret = 0;
  1095. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1096. return 0;
  1097. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1098. if (ret)
  1099. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1100. ret);
  1101. disable_irq(sol_gpio->dev_sol_irq);
  1102. return ret;
  1103. }
  1104. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1105. {
  1106. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1107. if (sol_gpio->dev_sol_gpio < 0)
  1108. return -EINVAL;
  1109. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1110. }
  1111. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1112. {
  1113. struct cnss_plat_data *plat_priv = data;
  1114. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1115. sol_gpio->dev_sol_counter++;
  1116. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1117. irq, sol_gpio->dev_sol_counter);
  1118. /* Make sure abort current suspend */
  1119. cnss_pm_stay_awake(plat_priv);
  1120. cnss_pm_relax(plat_priv);
  1121. pm_system_wakeup();
  1122. cnss_bus_handle_dev_sol_irq(plat_priv);
  1123. return IRQ_HANDLED;
  1124. }
  1125. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1126. {
  1127. struct device *dev = &plat_priv->plat_dev->dev;
  1128. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1129. int ret = 0;
  1130. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1131. "wlan-dev-sol-gpio", 0);
  1132. if (sol_gpio->dev_sol_gpio < 0)
  1133. goto out;
  1134. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1135. sol_gpio->dev_sol_gpio);
  1136. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1137. if (ret) {
  1138. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1139. ret);
  1140. goto out;
  1141. }
  1142. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1143. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1144. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1145. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1146. if (ret) {
  1147. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1148. goto free_gpio;
  1149. }
  1150. return 0;
  1151. free_gpio:
  1152. gpio_free(sol_gpio->dev_sol_gpio);
  1153. out:
  1154. return ret;
  1155. }
  1156. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1157. {
  1158. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1159. if (sol_gpio->dev_sol_gpio < 0)
  1160. return;
  1161. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1162. gpio_free(sol_gpio->dev_sol_gpio);
  1163. }
  1164. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1165. {
  1166. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1167. if (sol_gpio->host_sol_gpio < 0)
  1168. return -EINVAL;
  1169. if (value)
  1170. cnss_pr_dbg("Assert host SOL GPIO\n");
  1171. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1172. return 0;
  1173. }
  1174. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1175. {
  1176. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1177. if (sol_gpio->host_sol_gpio < 0)
  1178. return -EINVAL;
  1179. return gpio_get_value(sol_gpio->host_sol_gpio);
  1180. }
  1181. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1182. {
  1183. struct device *dev = &plat_priv->plat_dev->dev;
  1184. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1185. int ret = 0;
  1186. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1187. "wlan-host-sol-gpio", 0);
  1188. if (sol_gpio->host_sol_gpio < 0)
  1189. goto out;
  1190. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1191. sol_gpio->host_sol_gpio);
  1192. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1193. if (ret) {
  1194. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1195. ret);
  1196. goto out;
  1197. }
  1198. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1199. return 0;
  1200. out:
  1201. return ret;
  1202. }
  1203. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1204. {
  1205. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1206. if (sol_gpio->host_sol_gpio < 0)
  1207. return;
  1208. gpio_free(sol_gpio->host_sol_gpio);
  1209. }
  1210. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1211. {
  1212. int ret;
  1213. ret = cnss_init_dev_sol_gpio(plat_priv);
  1214. if (ret)
  1215. goto out;
  1216. ret = cnss_init_host_sol_gpio(plat_priv);
  1217. if (ret)
  1218. goto deinit_dev_sol;
  1219. return 0;
  1220. deinit_dev_sol:
  1221. cnss_deinit_dev_sol_gpio(plat_priv);
  1222. out:
  1223. return ret;
  1224. }
  1225. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1226. {
  1227. cnss_deinit_host_sol_gpio(plat_priv);
  1228. cnss_deinit_dev_sol_gpio(plat_priv);
  1229. }
  1230. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1231. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1232. {
  1233. struct cnss_plat_data *plat_priv;
  1234. int ret = 0;
  1235. if (!subsys_desc->dev) {
  1236. cnss_pr_err("dev from subsys_desc is NULL\n");
  1237. return -ENODEV;
  1238. }
  1239. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1240. if (!plat_priv) {
  1241. cnss_pr_err("plat_priv is NULL\n");
  1242. return -ENODEV;
  1243. }
  1244. if (!plat_priv->driver_state) {
  1245. cnss_pr_dbg("subsys powerup is ignored\n");
  1246. return 0;
  1247. }
  1248. ret = cnss_bus_dev_powerup(plat_priv);
  1249. if (ret)
  1250. __pm_relax(plat_priv->recovery_ws);
  1251. return ret;
  1252. }
  1253. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1254. bool force_stop)
  1255. {
  1256. struct cnss_plat_data *plat_priv;
  1257. if (!subsys_desc->dev) {
  1258. cnss_pr_err("dev from subsys_desc is NULL\n");
  1259. return -ENODEV;
  1260. }
  1261. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1262. if (!plat_priv) {
  1263. cnss_pr_err("plat_priv is NULL\n");
  1264. return -ENODEV;
  1265. }
  1266. if (!plat_priv->driver_state) {
  1267. cnss_pr_dbg("subsys shutdown is ignored\n");
  1268. return 0;
  1269. }
  1270. return cnss_bus_dev_shutdown(plat_priv);
  1271. }
  1272. void cnss_device_crashed(struct device *dev)
  1273. {
  1274. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1275. struct cnss_subsys_info *subsys_info;
  1276. if (!plat_priv)
  1277. return;
  1278. subsys_info = &plat_priv->subsys_info;
  1279. if (subsys_info->subsys_device) {
  1280. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1281. subsys_set_crash_status(subsys_info->subsys_device, true);
  1282. subsystem_restart_dev(subsys_info->subsys_device);
  1283. }
  1284. }
  1285. EXPORT_SYMBOL(cnss_device_crashed);
  1286. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1287. {
  1288. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1289. if (!plat_priv) {
  1290. cnss_pr_err("plat_priv is NULL\n");
  1291. return;
  1292. }
  1293. cnss_bus_dev_crash_shutdown(plat_priv);
  1294. }
  1295. static int cnss_subsys_ramdump(int enable,
  1296. const struct subsys_desc *subsys_desc)
  1297. {
  1298. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1299. if (!plat_priv) {
  1300. cnss_pr_err("plat_priv is NULL\n");
  1301. return -ENODEV;
  1302. }
  1303. if (!enable)
  1304. return 0;
  1305. return cnss_bus_dev_ramdump(plat_priv);
  1306. }
  1307. static void cnss_recovery_work_handler(struct work_struct *work)
  1308. {
  1309. }
  1310. #else
  1311. static void cnss_recovery_work_handler(struct work_struct *work)
  1312. {
  1313. int ret;
  1314. struct cnss_plat_data *plat_priv =
  1315. container_of(work, struct cnss_plat_data, recovery_work);
  1316. if (!plat_priv->recovery_enabled)
  1317. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1318. cnss_bus_dev_shutdown(plat_priv);
  1319. cnss_bus_dev_ramdump(plat_priv);
  1320. msleep(POWER_RESET_MIN_DELAY_MS);
  1321. ret = cnss_bus_dev_powerup(plat_priv);
  1322. if (ret)
  1323. __pm_relax(plat_priv->recovery_ws);
  1324. return;
  1325. }
  1326. void cnss_device_crashed(struct device *dev)
  1327. {
  1328. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1329. if (!plat_priv)
  1330. return;
  1331. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1332. schedule_work(&plat_priv->recovery_work);
  1333. }
  1334. EXPORT_SYMBOL(cnss_device_crashed);
  1335. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1336. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1337. {
  1338. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1339. struct cnss_ramdump_info *ramdump_info;
  1340. if (!plat_priv)
  1341. return NULL;
  1342. ramdump_info = &plat_priv->ramdump_info;
  1343. *size = ramdump_info->ramdump_size;
  1344. return ramdump_info->ramdump_va;
  1345. }
  1346. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1347. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1348. {
  1349. switch (reason) {
  1350. case CNSS_REASON_DEFAULT:
  1351. return "DEFAULT";
  1352. case CNSS_REASON_LINK_DOWN:
  1353. return "LINK_DOWN";
  1354. case CNSS_REASON_RDDM:
  1355. return "RDDM";
  1356. case CNSS_REASON_TIMEOUT:
  1357. return "TIMEOUT";
  1358. }
  1359. return "UNKNOWN";
  1360. };
  1361. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1362. enum cnss_recovery_reason reason)
  1363. {
  1364. plat_priv->recovery_count++;
  1365. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1366. goto self_recovery;
  1367. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1368. cnss_pr_dbg("Skip device recovery\n");
  1369. return 0;
  1370. }
  1371. /* FW recovery sequence has multiple steps and firmware load requires
  1372. * linux PM in awake state. Thus hold the cnss wake source until
  1373. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1374. * time taken in this process.
  1375. */
  1376. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1377. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1378. true);
  1379. switch (reason) {
  1380. case CNSS_REASON_LINK_DOWN:
  1381. if (!cnss_bus_check_link_status(plat_priv)) {
  1382. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1383. return 0;
  1384. }
  1385. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1386. &plat_priv->ctrl_params.quirks))
  1387. goto self_recovery;
  1388. if (!cnss_bus_recover_link_down(plat_priv)) {
  1389. /* clear recovery bit here to avoid skipping
  1390. * the recovery work for RDDM later
  1391. */
  1392. clear_bit(CNSS_DRIVER_RECOVERY,
  1393. &plat_priv->driver_state);
  1394. return 0;
  1395. }
  1396. break;
  1397. case CNSS_REASON_RDDM:
  1398. cnss_bus_collect_dump_info(plat_priv, false);
  1399. break;
  1400. case CNSS_REASON_DEFAULT:
  1401. case CNSS_REASON_TIMEOUT:
  1402. break;
  1403. default:
  1404. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1405. cnss_recovery_reason_to_str(reason), reason);
  1406. break;
  1407. }
  1408. cnss_bus_device_crashed(plat_priv);
  1409. return 0;
  1410. self_recovery:
  1411. cnss_pr_dbg("Going for self recovery\n");
  1412. cnss_bus_dev_shutdown(plat_priv);
  1413. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1414. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1415. &plat_priv->ctrl_params.quirks);
  1416. cnss_bus_dev_powerup(plat_priv);
  1417. return 0;
  1418. }
  1419. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1420. void *data)
  1421. {
  1422. struct cnss_recovery_data *recovery_data = data;
  1423. int ret = 0;
  1424. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1425. cnss_recovery_reason_to_str(recovery_data->reason),
  1426. recovery_data->reason);
  1427. if (!plat_priv->driver_state) {
  1428. cnss_pr_err("Improper driver state, ignore recovery\n");
  1429. ret = -EINVAL;
  1430. goto out;
  1431. }
  1432. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1433. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1434. ret = -EINVAL;
  1435. goto out;
  1436. }
  1437. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1438. cnss_pr_err("Recovery is already in progress\n");
  1439. CNSS_ASSERT(0);
  1440. ret = -EINVAL;
  1441. goto out;
  1442. }
  1443. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1444. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1445. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1446. ret = -EINVAL;
  1447. goto out;
  1448. }
  1449. switch (plat_priv->device_id) {
  1450. case QCA6174_DEVICE_ID:
  1451. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1452. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1453. &plat_priv->driver_state)) {
  1454. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1455. ret = -EINVAL;
  1456. goto out;
  1457. }
  1458. break;
  1459. default:
  1460. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1461. set_bit(CNSS_FW_BOOT_RECOVERY,
  1462. &plat_priv->driver_state);
  1463. }
  1464. break;
  1465. }
  1466. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1467. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1468. out:
  1469. kfree(data);
  1470. return ret;
  1471. }
  1472. int cnss_self_recovery(struct device *dev,
  1473. enum cnss_recovery_reason reason)
  1474. {
  1475. cnss_schedule_recovery(dev, reason);
  1476. return 0;
  1477. }
  1478. EXPORT_SYMBOL(cnss_self_recovery);
  1479. void cnss_schedule_recovery(struct device *dev,
  1480. enum cnss_recovery_reason reason)
  1481. {
  1482. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1483. struct cnss_recovery_data *data;
  1484. int gfp = GFP_KERNEL;
  1485. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1486. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1487. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1488. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1489. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1490. return;
  1491. }
  1492. if (in_interrupt() || irqs_disabled())
  1493. gfp = GFP_ATOMIC;
  1494. data = kzalloc(sizeof(*data), gfp);
  1495. if (!data)
  1496. return;
  1497. data->reason = reason;
  1498. cnss_driver_event_post(plat_priv,
  1499. CNSS_DRIVER_EVENT_RECOVERY,
  1500. 0, data);
  1501. }
  1502. EXPORT_SYMBOL(cnss_schedule_recovery);
  1503. int cnss_force_fw_assert(struct device *dev)
  1504. {
  1505. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1506. if (!plat_priv) {
  1507. cnss_pr_err("plat_priv is NULL\n");
  1508. return -ENODEV;
  1509. }
  1510. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1511. cnss_pr_info("Forced FW assert is not supported\n");
  1512. return -EOPNOTSUPP;
  1513. }
  1514. if (cnss_bus_is_device_down(plat_priv)) {
  1515. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1516. return 0;
  1517. }
  1518. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1519. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1520. return 0;
  1521. }
  1522. if (in_interrupt() || irqs_disabled())
  1523. cnss_driver_event_post(plat_priv,
  1524. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1525. 0, NULL);
  1526. else
  1527. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1528. return 0;
  1529. }
  1530. EXPORT_SYMBOL(cnss_force_fw_assert);
  1531. int cnss_force_collect_rddm(struct device *dev)
  1532. {
  1533. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1534. unsigned int timeout;
  1535. int ret = 0;
  1536. if (!plat_priv) {
  1537. cnss_pr_err("plat_priv is NULL\n");
  1538. return -ENODEV;
  1539. }
  1540. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1541. cnss_pr_info("Force collect rddm is not supported\n");
  1542. return -EOPNOTSUPP;
  1543. }
  1544. if (cnss_bus_is_device_down(plat_priv)) {
  1545. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1546. goto wait_rddm;
  1547. }
  1548. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1549. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1550. goto wait_rddm;
  1551. }
  1552. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1553. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1554. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1555. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1556. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1557. return 0;
  1558. }
  1559. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1560. if (ret)
  1561. return ret;
  1562. wait_rddm:
  1563. reinit_completion(&plat_priv->rddm_complete);
  1564. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1565. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1566. msecs_to_jiffies(timeout));
  1567. if (!ret) {
  1568. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1569. timeout);
  1570. ret = -ETIMEDOUT;
  1571. } else if (ret > 0) {
  1572. ret = 0;
  1573. }
  1574. return ret;
  1575. }
  1576. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1577. int cnss_qmi_send_get(struct device *dev)
  1578. {
  1579. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1580. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1581. return 0;
  1582. return cnss_bus_qmi_send_get(plat_priv);
  1583. }
  1584. EXPORT_SYMBOL(cnss_qmi_send_get);
  1585. int cnss_qmi_send_put(struct device *dev)
  1586. {
  1587. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1588. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1589. return 0;
  1590. return cnss_bus_qmi_send_put(plat_priv);
  1591. }
  1592. EXPORT_SYMBOL(cnss_qmi_send_put);
  1593. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1594. int cmd_len, void *cb_ctx,
  1595. int (*cb)(void *ctx, void *event, int event_len))
  1596. {
  1597. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1598. int ret;
  1599. if (!plat_priv)
  1600. return -ENODEV;
  1601. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1602. return -EINVAL;
  1603. plat_priv->get_info_cb = cb;
  1604. plat_priv->get_info_cb_ctx = cb_ctx;
  1605. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1606. if (ret) {
  1607. plat_priv->get_info_cb = NULL;
  1608. plat_priv->get_info_cb_ctx = NULL;
  1609. }
  1610. return ret;
  1611. }
  1612. EXPORT_SYMBOL(cnss_qmi_send);
  1613. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1614. {
  1615. int ret = 0;
  1616. u32 retry = 0, timeout;
  1617. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1618. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1619. goto out;
  1620. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1621. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1622. goto out;
  1623. } else if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  1624. cnss_pr_dbg("Calibration deferred as WLAN device disabled\n");
  1625. goto out;
  1626. }
  1627. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1628. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1629. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1630. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1631. CNSS_ASSERT(0);
  1632. return -EINVAL;
  1633. }
  1634. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1635. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1636. break;
  1637. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1638. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1639. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1640. CNSS_ASSERT(0);
  1641. ret = -EINVAL;
  1642. goto mark_cal_fail;
  1643. }
  1644. }
  1645. switch (plat_priv->device_id) {
  1646. case QCA6290_DEVICE_ID:
  1647. case QCA6390_DEVICE_ID:
  1648. case QCA6490_DEVICE_ID:
  1649. case KIWI_DEVICE_ID:
  1650. case MANGO_DEVICE_ID:
  1651. break;
  1652. default:
  1653. cnss_pr_err("Not supported for device ID 0x%lx\n",
  1654. plat_priv->device_id);
  1655. ret = -EINVAL;
  1656. goto mark_cal_fail;
  1657. }
  1658. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1659. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  1660. timeout = cnss_get_timeout(plat_priv,
  1661. CNSS_TIMEOUT_CALIBRATION);
  1662. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  1663. timeout / 1000);
  1664. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1665. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1666. msecs_to_jiffies(timeout));
  1667. }
  1668. reinit_completion(&plat_priv->cal_complete);
  1669. ret = cnss_bus_dev_powerup(plat_priv);
  1670. mark_cal_fail:
  1671. if (ret) {
  1672. complete(&plat_priv->cal_complete);
  1673. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1674. /* Set CBC done in driver state to mark attempt and note error
  1675. * since calibration cannot be retried at boot.
  1676. */
  1677. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1678. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1679. }
  1680. out:
  1681. return ret;
  1682. }
  1683. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1684. void *data)
  1685. {
  1686. struct cnss_cal_info *cal_info = data;
  1687. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1688. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1689. goto out;
  1690. switch (cal_info->cal_status) {
  1691. case CNSS_CAL_DONE:
  1692. cnss_pr_dbg("Calibration completed successfully\n");
  1693. plat_priv->cal_done = true;
  1694. break;
  1695. case CNSS_CAL_TIMEOUT:
  1696. case CNSS_CAL_FAILURE:
  1697. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1698. cal_info->cal_status);
  1699. break;
  1700. default:
  1701. cnss_pr_err("Unknown calibration status: %u\n",
  1702. cal_info->cal_status);
  1703. break;
  1704. }
  1705. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1706. cnss_bus_free_qdss_mem(plat_priv);
  1707. cnss_release_antenna_sharing(plat_priv);
  1708. cnss_bus_dev_shutdown(plat_priv);
  1709. msleep(POWER_RESET_MIN_DELAY_MS);
  1710. complete(&plat_priv->cal_complete);
  1711. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1712. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1713. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1714. cnss_cal_mem_upload_to_file(plat_priv);
  1715. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1716. goto out;
  1717. cnss_pr_dbg("Schedule WLAN driver load\n");
  1718. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1719. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1720. 0);
  1721. }
  1722. out:
  1723. kfree(data);
  1724. return 0;
  1725. }
  1726. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1727. {
  1728. int ret;
  1729. ret = cnss_bus_dev_powerup(plat_priv);
  1730. if (ret)
  1731. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1732. return ret;
  1733. }
  1734. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1735. {
  1736. cnss_bus_dev_shutdown(plat_priv);
  1737. return 0;
  1738. }
  1739. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1740. {
  1741. int ret = 0;
  1742. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1743. if (ret < 0)
  1744. return ret;
  1745. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1746. }
  1747. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1748. u32 mem_seg_len, u64 pa, u32 size)
  1749. {
  1750. int i = 0;
  1751. u64 offset = 0;
  1752. void *va = NULL;
  1753. u64 local_pa;
  1754. u32 local_size;
  1755. for (i = 0; i < mem_seg_len; i++) {
  1756. local_pa = (u64)fw_mem[i].pa;
  1757. local_size = (u32)fw_mem[i].size;
  1758. if (pa == local_pa && size <= local_size) {
  1759. va = fw_mem[i].va;
  1760. break;
  1761. }
  1762. if (pa > local_pa &&
  1763. pa < local_pa + local_size &&
  1764. pa + size <= local_pa + local_size) {
  1765. offset = pa - local_pa;
  1766. va = fw_mem[i].va + offset;
  1767. break;
  1768. }
  1769. }
  1770. return va;
  1771. }
  1772. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  1773. void *data)
  1774. {
  1775. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1776. struct cnss_fw_mem *fw_mem_seg;
  1777. int ret = 0L;
  1778. void *va = NULL;
  1779. u32 i, fw_mem_seg_len;
  1780. switch (event_data->mem_type) {
  1781. case QMI_WLFW_MEM_TYPE_DDR_V01:
  1782. if (!plat_priv->fw_mem_seg_len)
  1783. goto invalid_mem_save;
  1784. fw_mem_seg = plat_priv->fw_mem;
  1785. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  1786. break;
  1787. case QMI_WLFW_MEM_QDSS_V01:
  1788. if (!plat_priv->qdss_mem_seg_len)
  1789. goto invalid_mem_save;
  1790. fw_mem_seg = plat_priv->qdss_mem;
  1791. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  1792. break;
  1793. default:
  1794. goto invalid_mem_save;
  1795. }
  1796. for (i = 0; i < event_data->mem_seg_len; i++) {
  1797. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  1798. event_data->mem_seg[i].addr,
  1799. event_data->mem_seg[i].size);
  1800. if (!va) {
  1801. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  1802. &event_data->mem_seg[i].addr,
  1803. event_data->mem_type);
  1804. ret = -EINVAL;
  1805. break;
  1806. }
  1807. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  1808. event_data->file_name,
  1809. event_data->mem_seg[i].size);
  1810. if (ret < 0) {
  1811. cnss_pr_err("Fail to save fw mem data: %d\n",
  1812. ret);
  1813. break;
  1814. }
  1815. }
  1816. kfree(data);
  1817. return ret;
  1818. invalid_mem_save:
  1819. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  1820. event_data->mem_type);
  1821. kfree(data);
  1822. return -EINVAL;
  1823. }
  1824. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  1825. {
  1826. cnss_bus_free_qdss_mem(plat_priv);
  1827. return 0;
  1828. }
  1829. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  1830. void *data)
  1831. {
  1832. int ret = 0;
  1833. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1834. if (!plat_priv)
  1835. return -ENODEV;
  1836. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  1837. event_data->total_size);
  1838. kfree(data);
  1839. return ret;
  1840. }
  1841. static void cnss_driver_event_work(struct work_struct *work)
  1842. {
  1843. struct cnss_plat_data *plat_priv =
  1844. container_of(work, struct cnss_plat_data, event_work);
  1845. struct cnss_driver_event *event;
  1846. unsigned long flags;
  1847. int ret = 0;
  1848. if (!plat_priv) {
  1849. cnss_pr_err("plat_priv is NULL!\n");
  1850. return;
  1851. }
  1852. cnss_pm_stay_awake(plat_priv);
  1853. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1854. while (!list_empty(&plat_priv->event_list)) {
  1855. event = list_first_entry(&plat_priv->event_list,
  1856. struct cnss_driver_event, list);
  1857. list_del(&event->list);
  1858. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1859. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  1860. cnss_driver_event_to_str(event->type),
  1861. event->sync ? "-sync" : "", event->type,
  1862. plat_priv->driver_state);
  1863. switch (event->type) {
  1864. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1865. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  1866. break;
  1867. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1868. ret = cnss_wlfw_server_exit(plat_priv);
  1869. break;
  1870. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1871. ret = cnss_bus_alloc_fw_mem(plat_priv);
  1872. if (ret)
  1873. break;
  1874. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  1875. break;
  1876. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1877. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  1878. break;
  1879. case CNSS_DRIVER_EVENT_FW_READY:
  1880. ret = cnss_fw_ready_hdlr(plat_priv);
  1881. break;
  1882. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1883. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  1884. break;
  1885. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1886. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  1887. event->data);
  1888. break;
  1889. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1890. ret = cnss_bus_register_driver_hdlr(plat_priv,
  1891. event->data);
  1892. break;
  1893. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1894. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  1895. break;
  1896. case CNSS_DRIVER_EVENT_RECOVERY:
  1897. ret = cnss_driver_recovery_hdlr(plat_priv,
  1898. event->data);
  1899. break;
  1900. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1901. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1902. break;
  1903. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1904. set_bit(CNSS_DRIVER_IDLE_RESTART,
  1905. &plat_priv->driver_state);
  1906. fallthrough;
  1907. case CNSS_DRIVER_EVENT_POWER_UP:
  1908. ret = cnss_power_up_hdlr(plat_priv);
  1909. break;
  1910. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1911. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  1912. &plat_priv->driver_state);
  1913. fallthrough;
  1914. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1915. ret = cnss_power_down_hdlr(plat_priv);
  1916. break;
  1917. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1918. ret = cnss_process_wfc_call_ind_event(plat_priv,
  1919. event->data);
  1920. break;
  1921. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1922. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  1923. event->data);
  1924. break;
  1925. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1926. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  1927. break;
  1928. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1929. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  1930. event->data);
  1931. break;
  1932. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1933. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  1934. break;
  1935. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1936. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  1937. event->data);
  1938. break;
  1939. default:
  1940. cnss_pr_err("Invalid driver event type: %d",
  1941. event->type);
  1942. kfree(event);
  1943. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1944. continue;
  1945. }
  1946. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1947. if (event->sync) {
  1948. event->ret = ret;
  1949. complete(&event->complete);
  1950. continue;
  1951. }
  1952. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1953. kfree(event);
  1954. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1955. }
  1956. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1957. cnss_pm_relax(plat_priv);
  1958. }
  1959. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1960. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1961. {
  1962. int ret = 0;
  1963. struct cnss_subsys_info *subsys_info;
  1964. subsys_info = &plat_priv->subsys_info;
  1965. subsys_info->subsys_desc.name = "wlan";
  1966. subsys_info->subsys_desc.owner = THIS_MODULE;
  1967. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  1968. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  1969. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  1970. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  1971. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  1972. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  1973. if (IS_ERR(subsys_info->subsys_device)) {
  1974. ret = PTR_ERR(subsys_info->subsys_device);
  1975. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  1976. goto out;
  1977. }
  1978. subsys_info->subsys_handle =
  1979. subsystem_get(subsys_info->subsys_desc.name);
  1980. if (!subsys_info->subsys_handle) {
  1981. cnss_pr_err("Failed to get subsys_handle!\n");
  1982. ret = -EINVAL;
  1983. goto unregister_subsys;
  1984. } else if (IS_ERR(subsys_info->subsys_handle)) {
  1985. ret = PTR_ERR(subsys_info->subsys_handle);
  1986. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  1987. goto unregister_subsys;
  1988. }
  1989. return 0;
  1990. unregister_subsys:
  1991. subsys_unregister(subsys_info->subsys_device);
  1992. out:
  1993. return ret;
  1994. }
  1995. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  1996. {
  1997. struct cnss_subsys_info *subsys_info;
  1998. subsys_info = &plat_priv->subsys_info;
  1999. subsystem_put(subsys_info->subsys_handle);
  2000. subsys_unregister(subsys_info->subsys_device);
  2001. }
  2002. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2003. {
  2004. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  2005. return create_ramdump_device(subsys_info->subsys_desc.name,
  2006. subsys_info->subsys_desc.dev);
  2007. }
  2008. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2009. void *ramdump_dev)
  2010. {
  2011. destroy_ramdump_device(ramdump_dev);
  2012. }
  2013. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2014. {
  2015. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2016. struct ramdump_segment segment;
  2017. memset(&segment, 0, sizeof(segment));
  2018. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  2019. segment.size = ramdump_info->ramdump_size;
  2020. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  2021. }
  2022. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2023. {
  2024. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2025. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2026. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2027. struct ramdump_segment *ramdump_segs, *s;
  2028. struct cnss_dump_meta_info meta_info = {0};
  2029. int i, ret = 0;
  2030. ramdump_segs = kcalloc(dump_data->nentries + 1,
  2031. sizeof(*ramdump_segs),
  2032. GFP_KERNEL);
  2033. if (!ramdump_segs)
  2034. return -ENOMEM;
  2035. s = ramdump_segs + 1;
  2036. for (i = 0; i < dump_data->nentries; i++) {
  2037. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2038. cnss_pr_err("Unsupported dump type: %d",
  2039. dump_seg->type);
  2040. continue;
  2041. }
  2042. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2043. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2044. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2045. }
  2046. meta_info.entry[dump_seg->type].entry_num++;
  2047. s->address = dump_seg->address;
  2048. s->v_address = (void __iomem *)dump_seg->v_address;
  2049. s->size = dump_seg->size;
  2050. s++;
  2051. dump_seg++;
  2052. }
  2053. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2054. meta_info.version = CNSS_RAMDUMP_VERSION;
  2055. meta_info.chipset = plat_priv->device_id;
  2056. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2057. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  2058. ramdump_segs->size = sizeof(meta_info);
  2059. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  2060. dump_data->nentries + 1);
  2061. kfree(ramdump_segs);
  2062. return ret;
  2063. }
  2064. #else
  2065. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2066. void *data)
  2067. {
  2068. struct cnss_plat_data *plat_priv =
  2069. container_of(nb, struct cnss_plat_data, panic_nb);
  2070. cnss_bus_dev_crash_shutdown(plat_priv);
  2071. return NOTIFY_DONE;
  2072. }
  2073. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2074. {
  2075. int ret;
  2076. if (!plat_priv)
  2077. return -ENODEV;
  2078. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2079. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2080. &plat_priv->panic_nb);
  2081. if (ret) {
  2082. cnss_pr_err("Failed to register panic handler\n");
  2083. return -EINVAL;
  2084. }
  2085. return 0;
  2086. }
  2087. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2088. {
  2089. int ret;
  2090. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2091. &plat_priv->panic_nb);
  2092. if (ret)
  2093. cnss_pr_err("Failed to unregister panic handler\n");
  2094. }
  2095. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2096. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2097. {
  2098. return &plat_priv->plat_dev->dev;
  2099. }
  2100. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2101. void *ramdump_dev)
  2102. {
  2103. }
  2104. #endif
  2105. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2106. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2107. {
  2108. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2109. struct qcom_dump_segment segment;
  2110. struct list_head head;
  2111. INIT_LIST_HEAD(&head);
  2112. memset(&segment, 0, sizeof(segment));
  2113. segment.va = ramdump_info->ramdump_va;
  2114. segment.size = ramdump_info->ramdump_size;
  2115. list_add(&segment.node, &head);
  2116. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2117. }
  2118. #else
  2119. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2120. {
  2121. return 0;
  2122. }
  2123. /* Using completion event inside dynamically allocated ramdump_desc
  2124. * may result a race between freeing the event after setting it to
  2125. * complete inside dev coredump free callback and the thread that is
  2126. * waiting for completion.
  2127. */
  2128. DECLARE_COMPLETION(dump_done);
  2129. #define TIMEOUT_SAVE_DUMP_MS 30000
  2130. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2131. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2132. { \
  2133. if (class == ELFCLASS32) \
  2134. return sizeof(struct elf32_##__xhdr); \
  2135. else \
  2136. return sizeof(struct elf64_##__xhdr); \
  2137. }
  2138. SIZEOF_ELF_STRUCT(phdr)
  2139. SIZEOF_ELF_STRUCT(hdr)
  2140. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2141. do { \
  2142. if (class == ELFCLASS32) \
  2143. ((struct elf32_##__xhdr *)arg)->member = value; \
  2144. else \
  2145. ((struct elf64_##__xhdr *)arg)->member = value; \
  2146. } while (0)
  2147. #define set_ehdr_property(arg, class, member, value) \
  2148. set_xhdr_property(hdr, arg, class, member, value)
  2149. #define set_phdr_property(arg, class, member, value) \
  2150. set_xhdr_property(phdr, arg, class, member, value)
  2151. /* These replace qcom_ramdump driver APIs called from common API
  2152. * cnss_do_elf_dump() by the ones defined here.
  2153. */
  2154. #define qcom_dump_segment cnss_qcom_dump_segment
  2155. #define qcom_elf_dump cnss_qcom_elf_dump
  2156. #define dump_enabled cnss_dump_enabled
  2157. struct cnss_qcom_dump_segment {
  2158. struct list_head node;
  2159. dma_addr_t da;
  2160. void *va;
  2161. size_t size;
  2162. };
  2163. struct cnss_qcom_ramdump_desc {
  2164. void *data;
  2165. struct completion dump_done;
  2166. };
  2167. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2168. void *data, size_t datalen)
  2169. {
  2170. struct cnss_qcom_ramdump_desc *desc = data;
  2171. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2172. datalen);
  2173. }
  2174. static void cnss_qcom_devcd_freev(void *data)
  2175. {
  2176. struct cnss_qcom_ramdump_desc *desc = data;
  2177. cnss_pr_dbg("Free dump data for dev coredump\n");
  2178. complete(&dump_done);
  2179. vfree(desc->data);
  2180. kfree(desc);
  2181. }
  2182. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2183. gfp_t gfp)
  2184. {
  2185. struct cnss_qcom_ramdump_desc *desc;
  2186. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2187. int ret;
  2188. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2189. if (!desc)
  2190. return -ENOMEM;
  2191. desc->data = data;
  2192. reinit_completion(&dump_done);
  2193. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2194. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2195. ret = wait_for_completion_timeout(&dump_done,
  2196. msecs_to_jiffies(timeout));
  2197. if (!ret)
  2198. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2199. timeout);
  2200. return ret ? 0 : -ETIMEDOUT;
  2201. }
  2202. /* Since the elf32 and elf64 identification is identical apart from
  2203. * the class, use elf32 by default.
  2204. */
  2205. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2206. {
  2207. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2208. ehdr->e_ident[EI_CLASS] = class;
  2209. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2210. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2211. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2212. }
  2213. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2214. unsigned char class)
  2215. {
  2216. struct cnss_qcom_dump_segment *segment;
  2217. void *phdr, *ehdr;
  2218. size_t data_size, offset;
  2219. int phnum = 0;
  2220. void *data;
  2221. void __iomem *ptr;
  2222. if (!segs || list_empty(segs))
  2223. return -EINVAL;
  2224. data_size = sizeof_elf_hdr(class);
  2225. list_for_each_entry(segment, segs, node) {
  2226. data_size += sizeof_elf_phdr(class) + segment->size;
  2227. phnum++;
  2228. }
  2229. data = vmalloc(data_size);
  2230. if (!data)
  2231. return -ENOMEM;
  2232. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2233. ehdr = data;
  2234. memset(ehdr, 0, sizeof_elf_hdr(class));
  2235. init_elf_identification(ehdr, class);
  2236. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2237. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2238. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2239. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2240. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2241. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2242. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2243. phdr = data + sizeof_elf_hdr(class);
  2244. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2245. list_for_each_entry(segment, segs, node) {
  2246. memset(phdr, 0, sizeof_elf_phdr(class));
  2247. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2248. set_phdr_property(phdr, class, p_offset, offset);
  2249. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2250. set_phdr_property(phdr, class, p_paddr, segment->da);
  2251. set_phdr_property(phdr, class, p_filesz, segment->size);
  2252. set_phdr_property(phdr, class, p_memsz, segment->size);
  2253. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2254. set_phdr_property(phdr, class, p_align, 0);
  2255. if (segment->va) {
  2256. memcpy(data + offset, segment->va, segment->size);
  2257. } else {
  2258. ptr = devm_ioremap(dev, segment->da, segment->size);
  2259. if (!ptr) {
  2260. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2261. &segment->da, segment->size);
  2262. memset(data + offset, 0xff, segment->size);
  2263. } else {
  2264. memcpy_fromio(data + offset, ptr,
  2265. segment->size);
  2266. }
  2267. }
  2268. offset += segment->size;
  2269. phdr += sizeof_elf_phdr(class);
  2270. }
  2271. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2272. }
  2273. /* Saving dump to file system is always needed in this case. */
  2274. static bool cnss_dump_enabled(void)
  2275. {
  2276. return true;
  2277. }
  2278. #endif /* CONFIG_QCOM_RAMDUMP */
  2279. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2280. {
  2281. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2282. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2283. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2284. struct qcom_dump_segment *seg;
  2285. struct cnss_dump_meta_info meta_info = {0};
  2286. struct list_head head;
  2287. int i, ret = 0;
  2288. if (!dump_enabled()) {
  2289. cnss_pr_info("Dump collection is not enabled\n");
  2290. return ret;
  2291. }
  2292. INIT_LIST_HEAD(&head);
  2293. for (i = 0; i < dump_data->nentries; i++) {
  2294. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2295. cnss_pr_err("Unsupported dump type: %d",
  2296. dump_seg->type);
  2297. continue;
  2298. }
  2299. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2300. if (!seg)
  2301. continue;
  2302. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2303. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2304. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2305. }
  2306. meta_info.entry[dump_seg->type].entry_num++;
  2307. seg->da = dump_seg->address;
  2308. seg->va = dump_seg->v_address;
  2309. seg->size = dump_seg->size;
  2310. list_add_tail(&seg->node, &head);
  2311. dump_seg++;
  2312. }
  2313. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2314. if (!seg)
  2315. goto do_elf_dump;
  2316. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2317. meta_info.version = CNSS_RAMDUMP_VERSION;
  2318. meta_info.chipset = plat_priv->device_id;
  2319. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2320. seg->va = &meta_info;
  2321. seg->size = sizeof(meta_info);
  2322. list_add(&seg->node, &head);
  2323. do_elf_dump:
  2324. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2325. while (!list_empty(&head)) {
  2326. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2327. list_del(&seg->node);
  2328. kfree(seg);
  2329. }
  2330. return ret;
  2331. }
  2332. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2333. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2334. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2335. {
  2336. struct cnss_ramdump_info *ramdump_info;
  2337. struct msm_dump_entry dump_entry;
  2338. ramdump_info = &plat_priv->ramdump_info;
  2339. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2340. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2341. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2342. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2343. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2344. sizeof(ramdump_info->dump_data.name));
  2345. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2346. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2347. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2348. &dump_entry);
  2349. }
  2350. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2351. {
  2352. int ret = 0;
  2353. struct device *dev;
  2354. struct cnss_ramdump_info *ramdump_info;
  2355. u32 ramdump_size = 0;
  2356. dev = &plat_priv->plat_dev->dev;
  2357. ramdump_info = &plat_priv->ramdump_info;
  2358. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  2359. /* dt type: legacy or converged */
  2360. ret = of_property_read_u32(dev->of_node,
  2361. "qcom,wlan-ramdump-dynamic",
  2362. &ramdump_size);
  2363. } else {
  2364. ret = of_property_read_u32(plat_priv->dev_node,
  2365. "qcom,wlan-ramdump-dynamic",
  2366. &ramdump_size);
  2367. }
  2368. if (ret == 0) {
  2369. ramdump_info->ramdump_va =
  2370. dma_alloc_coherent(dev, ramdump_size,
  2371. &ramdump_info->ramdump_pa,
  2372. GFP_KERNEL);
  2373. if (ramdump_info->ramdump_va)
  2374. ramdump_info->ramdump_size = ramdump_size;
  2375. }
  2376. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2377. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2378. if (ramdump_info->ramdump_size == 0) {
  2379. cnss_pr_info("Ramdump will not be collected");
  2380. goto out;
  2381. }
  2382. ret = cnss_init_dump_entry(plat_priv);
  2383. if (ret) {
  2384. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2385. goto free_ramdump;
  2386. }
  2387. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2388. if (!ramdump_info->ramdump_dev) {
  2389. cnss_pr_err("Failed to create ramdump device!");
  2390. ret = -ENOMEM;
  2391. goto free_ramdump;
  2392. }
  2393. return 0;
  2394. free_ramdump:
  2395. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2396. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2397. out:
  2398. return ret;
  2399. }
  2400. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2401. {
  2402. struct device *dev;
  2403. struct cnss_ramdump_info *ramdump_info;
  2404. dev = &plat_priv->plat_dev->dev;
  2405. ramdump_info = &plat_priv->ramdump_info;
  2406. if (ramdump_info->ramdump_dev)
  2407. cnss_destroy_ramdump_device(plat_priv,
  2408. ramdump_info->ramdump_dev);
  2409. if (ramdump_info->ramdump_va)
  2410. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2411. ramdump_info->ramdump_va,
  2412. ramdump_info->ramdump_pa);
  2413. }
  2414. /**
  2415. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2416. * @ret: Error returned by msm_dump_data_register_nominidump
  2417. *
  2418. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2419. * ignore failure.
  2420. *
  2421. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2422. */
  2423. static int cnss_ignore_dump_data_reg_fail(int ret)
  2424. {
  2425. return ret;
  2426. }
  2427. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2428. {
  2429. int ret = 0;
  2430. struct cnss_ramdump_info_v2 *info_v2;
  2431. struct cnss_dump_data *dump_data;
  2432. struct msm_dump_entry dump_entry;
  2433. struct device *dev = &plat_priv->plat_dev->dev;
  2434. u32 ramdump_size = 0;
  2435. info_v2 = &plat_priv->ramdump_info_v2;
  2436. dump_data = &info_v2->dump_data;
  2437. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  2438. /* dt type: legacy or converged */
  2439. ret = of_property_read_u32(dev->of_node,
  2440. "qcom,wlan-ramdump-dynamic",
  2441. &ramdump_size);
  2442. } else {
  2443. ret = of_property_read_u32(plat_priv->dev_node,
  2444. "qcom,wlan-ramdump-dynamic",
  2445. &ramdump_size);
  2446. }
  2447. if (ret == 0)
  2448. info_v2->ramdump_size = ramdump_size;
  2449. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2450. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2451. if (!info_v2->dump_data_vaddr)
  2452. return -ENOMEM;
  2453. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2454. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2455. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2456. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2457. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2458. sizeof(dump_data->name));
  2459. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2460. dump_entry.addr = virt_to_phys(dump_data);
  2461. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2462. &dump_entry);
  2463. if (ret) {
  2464. ret = cnss_ignore_dump_data_reg_fail(ret);
  2465. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2466. ret ? "Error" : "Ignoring", ret);
  2467. goto free_ramdump;
  2468. }
  2469. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2470. if (!info_v2->ramdump_dev) {
  2471. cnss_pr_err("Failed to create ramdump device!\n");
  2472. ret = -ENOMEM;
  2473. goto free_ramdump;
  2474. }
  2475. return 0;
  2476. free_ramdump:
  2477. kfree(info_v2->dump_data_vaddr);
  2478. info_v2->dump_data_vaddr = NULL;
  2479. return ret;
  2480. }
  2481. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2482. {
  2483. struct cnss_ramdump_info_v2 *info_v2;
  2484. info_v2 = &plat_priv->ramdump_info_v2;
  2485. if (info_v2->ramdump_dev)
  2486. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2487. kfree(info_v2->dump_data_vaddr);
  2488. info_v2->dump_data_vaddr = NULL;
  2489. info_v2->dump_data_valid = false;
  2490. }
  2491. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2492. {
  2493. int ret = 0;
  2494. switch (plat_priv->device_id) {
  2495. case QCA6174_DEVICE_ID:
  2496. ret = cnss_register_ramdump_v1(plat_priv);
  2497. break;
  2498. case QCA6290_DEVICE_ID:
  2499. case QCA6390_DEVICE_ID:
  2500. case QCA6490_DEVICE_ID:
  2501. case KIWI_DEVICE_ID:
  2502. case MANGO_DEVICE_ID:
  2503. ret = cnss_register_ramdump_v2(plat_priv);
  2504. break;
  2505. default:
  2506. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2507. ret = -ENODEV;
  2508. break;
  2509. }
  2510. return ret;
  2511. }
  2512. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2513. {
  2514. switch (plat_priv->device_id) {
  2515. case QCA6174_DEVICE_ID:
  2516. cnss_unregister_ramdump_v1(plat_priv);
  2517. break;
  2518. case QCA6290_DEVICE_ID:
  2519. case QCA6390_DEVICE_ID:
  2520. case QCA6490_DEVICE_ID:
  2521. case KIWI_DEVICE_ID:
  2522. case MANGO_DEVICE_ID:
  2523. cnss_unregister_ramdump_v2(plat_priv);
  2524. break;
  2525. default:
  2526. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2527. break;
  2528. }
  2529. }
  2530. #else
  2531. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2532. {
  2533. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2534. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2535. struct device *dev = &plat_priv->plat_dev->dev;
  2536. u32 ramdump_size = 0;
  2537. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2538. &ramdump_size) == 0)
  2539. info_v2->ramdump_size = ramdump_size;
  2540. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2541. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2542. if (!info_v2->dump_data_vaddr)
  2543. return -ENOMEM;
  2544. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2545. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2546. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2547. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2548. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2549. sizeof(dump_data->name));
  2550. info_v2->ramdump_dev = dev;
  2551. return 0;
  2552. }
  2553. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2554. {
  2555. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2556. info_v2->ramdump_dev = NULL;
  2557. kfree(info_v2->dump_data_vaddr);
  2558. info_v2->dump_data_vaddr = NULL;
  2559. info_v2->dump_data_valid = false;
  2560. }
  2561. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2562. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2563. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2564. phys_addr_t *pa, unsigned long attrs)
  2565. {
  2566. struct sg_table sgt;
  2567. int ret;
  2568. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2569. if (ret) {
  2570. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2571. va, &dma, size, attrs);
  2572. return -EINVAL;
  2573. }
  2574. *pa = page_to_phys(sg_page(sgt.sgl));
  2575. sg_free_table(&sgt);
  2576. return 0;
  2577. }
  2578. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2579. enum cnss_fw_dump_type type, int seg_no,
  2580. void *va, phys_addr_t pa, size_t size)
  2581. {
  2582. struct md_region md_entry;
  2583. int ret;
  2584. switch (type) {
  2585. case CNSS_FW_IMAGE:
  2586. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2587. seg_no);
  2588. break;
  2589. case CNSS_FW_RDDM:
  2590. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2591. seg_no);
  2592. break;
  2593. case CNSS_FW_REMOTE_HEAP:
  2594. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2595. seg_no);
  2596. break;
  2597. default:
  2598. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2599. return -EINVAL;
  2600. }
  2601. md_entry.phys_addr = pa;
  2602. md_entry.virt_addr = (uintptr_t)va;
  2603. md_entry.size = size;
  2604. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2605. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2606. md_entry.name, va, &pa, size);
  2607. ret = msm_minidump_add_region(&md_entry);
  2608. if (ret < 0)
  2609. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2610. return ret;
  2611. }
  2612. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2613. enum cnss_fw_dump_type type, int seg_no,
  2614. void *va, phys_addr_t pa, size_t size)
  2615. {
  2616. struct md_region md_entry;
  2617. int ret;
  2618. switch (type) {
  2619. case CNSS_FW_IMAGE:
  2620. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2621. seg_no);
  2622. break;
  2623. case CNSS_FW_RDDM:
  2624. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2625. seg_no);
  2626. break;
  2627. case CNSS_FW_REMOTE_HEAP:
  2628. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2629. seg_no);
  2630. break;
  2631. default:
  2632. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2633. return -EINVAL;
  2634. }
  2635. md_entry.phys_addr = pa;
  2636. md_entry.virt_addr = (uintptr_t)va;
  2637. md_entry.size = size;
  2638. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2639. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2640. md_entry.name, va, &pa, size);
  2641. ret = msm_minidump_remove_region(&md_entry);
  2642. if (ret)
  2643. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2644. ret);
  2645. return ret;
  2646. }
  2647. #else
  2648. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2649. phys_addr_t *pa, unsigned long attrs)
  2650. {
  2651. return 0;
  2652. }
  2653. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2654. enum cnss_fw_dump_type type, int seg_no,
  2655. void *va, phys_addr_t pa, size_t size)
  2656. {
  2657. return 0;
  2658. }
  2659. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2660. enum cnss_fw_dump_type type, int seg_no,
  2661. void *va, phys_addr_t pa, size_t size)
  2662. {
  2663. return 0;
  2664. }
  2665. #endif /* CONFIG_QCOM_MINIDUMP */
  2666. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  2667. const struct firmware **fw_entry,
  2668. const char *filename)
  2669. {
  2670. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  2671. return request_firmware_direct(fw_entry, filename,
  2672. &plat_priv->plat_dev->dev);
  2673. else
  2674. return firmware_request_nowarn(fw_entry, filename,
  2675. &plat_priv->plat_dev->dev);
  2676. }
  2677. #if IS_ENABLED(CONFIG_INTERCONNECT)
  2678. /**
  2679. * cnss_register_bus_scale() - Setup interconnect voting data
  2680. * @plat_priv: Platform data structure
  2681. *
  2682. * For different interconnect path configured in device tree setup voting data
  2683. * for list of bandwidth requirements.
  2684. *
  2685. * Result: 0 for success. -EINVAL if not configured
  2686. */
  2687. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2688. {
  2689. int ret = -EINVAL;
  2690. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  2691. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2692. struct device *dev = &plat_priv->plat_dev->dev;
  2693. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  2694. ret = of_property_read_u32(dev->of_node,
  2695. "qcom,icc-path-count",
  2696. &plat_priv->icc.path_count);
  2697. if (ret) {
  2698. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  2699. return 0;
  2700. }
  2701. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  2702. "qcom,bus-bw-cfg-count",
  2703. &plat_priv->icc.bus_bw_cfg_count);
  2704. if (ret) {
  2705. cnss_pr_err("Failed to get Bus BW Config table size\n");
  2706. goto cleanup;
  2707. }
  2708. cfg_arr_size = plat_priv->icc.path_count *
  2709. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  2710. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  2711. if (!cfg_arr) {
  2712. cnss_pr_err("Failed to alloc cfg table mem\n");
  2713. ret = -ENOMEM;
  2714. goto cleanup;
  2715. }
  2716. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  2717. "qcom,bus-bw-cfg", cfg_arr,
  2718. cfg_arr_size);
  2719. if (ret) {
  2720. cnss_pr_err("Invalid Bus BW Config Table\n");
  2721. goto cleanup;
  2722. }
  2723. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  2724. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  2725. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  2726. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  2727. GFP_KERNEL);
  2728. if (!bus_bw_info) {
  2729. ret = -ENOMEM;
  2730. goto out;
  2731. }
  2732. ret = of_property_read_string_index(dev->of_node,
  2733. "interconnect-names", idx,
  2734. &bus_bw_info->icc_name);
  2735. if (ret)
  2736. goto out;
  2737. bus_bw_info->icc_path =
  2738. of_icc_get(&plat_priv->plat_dev->dev,
  2739. bus_bw_info->icc_name);
  2740. if (IS_ERR(bus_bw_info->icc_path)) {
  2741. ret = PTR_ERR(bus_bw_info->icc_path);
  2742. if (ret != -EPROBE_DEFER) {
  2743. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  2744. bus_bw_info->icc_name, ret);
  2745. goto out;
  2746. }
  2747. }
  2748. bus_bw_info->cfg_table =
  2749. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  2750. sizeof(*bus_bw_info->cfg_table),
  2751. GFP_KERNEL);
  2752. if (!bus_bw_info->cfg_table) {
  2753. ret = -ENOMEM;
  2754. goto out;
  2755. }
  2756. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  2757. bus_bw_info->icc_name);
  2758. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  2759. CNSS_ICC_VOTE_MAX);
  2760. i < plat_priv->icc.bus_bw_cfg_count;
  2761. i++, j += 2) {
  2762. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  2763. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  2764. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  2765. i, bus_bw_info->cfg_table[i].avg_bw,
  2766. bus_bw_info->cfg_table[i].peak_bw);
  2767. }
  2768. list_add_tail(&bus_bw_info->list,
  2769. &plat_priv->icc.list_head);
  2770. }
  2771. kfree(cfg_arr);
  2772. return 0;
  2773. out:
  2774. list_for_each_entry_safe(bus_bw_info, tmp,
  2775. &plat_priv->icc.list_head, list) {
  2776. list_del(&bus_bw_info->list);
  2777. }
  2778. cleanup:
  2779. kfree(cfg_arr);
  2780. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2781. return ret;
  2782. }
  2783. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  2784. {
  2785. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2786. list_for_each_entry_safe(bus_bw_info, tmp,
  2787. &plat_priv->icc.list_head, list) {
  2788. list_del(&bus_bw_info->list);
  2789. if (bus_bw_info->icc_path)
  2790. icc_put(bus_bw_info->icc_path);
  2791. }
  2792. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2793. }
  2794. #else
  2795. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2796. {
  2797. return 0;
  2798. }
  2799. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  2800. #endif /* CONFIG_INTERCONNECT */
  2801. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  2802. {
  2803. struct cnss_plat_data *plat_priv = cb_ctx;
  2804. if (!plat_priv) {
  2805. cnss_pr_err("%s: Invalid context\n", __func__);
  2806. return;
  2807. }
  2808. if (status) {
  2809. cnss_pr_info("CNSS Daemon connected\n");
  2810. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2811. complete(&plat_priv->daemon_connected);
  2812. } else {
  2813. cnss_pr_info("CNSS Daemon disconnected\n");
  2814. reinit_completion(&plat_priv->daemon_connected);
  2815. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2816. }
  2817. }
  2818. static ssize_t enable_hds_store(struct device *dev,
  2819. struct device_attribute *attr,
  2820. const char *buf, size_t count)
  2821. {
  2822. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2823. unsigned int enable_hds = 0;
  2824. if (!plat_priv)
  2825. return -ENODEV;
  2826. if (sscanf(buf, "%du", &enable_hds) != 1) {
  2827. cnss_pr_err("Invalid enable_hds sysfs command\n");
  2828. return -EINVAL;
  2829. }
  2830. if (enable_hds)
  2831. plat_priv->hds_enabled = true;
  2832. else
  2833. plat_priv->hds_enabled = false;
  2834. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  2835. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  2836. return count;
  2837. }
  2838. static ssize_t recovery_show(struct device *dev,
  2839. struct device_attribute *attr,
  2840. char *buf)
  2841. {
  2842. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2843. u32 buf_size = PAGE_SIZE;
  2844. u32 curr_len = 0;
  2845. u32 buf_written = 0;
  2846. if (!plat_priv)
  2847. return -ENODEV;
  2848. buf_written = scnprintf(buf, buf_size,
  2849. "Usage: echo [recovery_bitmap] > /sys/kernel/cnss/recovery\n"
  2850. "BIT0 -- wlan fw recovery\n"
  2851. "BIT1 -- wlan pcss recovery\n"
  2852. "---------------------------------\n");
  2853. curr_len += buf_written;
  2854. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  2855. "WLAN recovery %s[%d]\n",
  2856. plat_priv->recovery_enabled ? "Enabled" : "Disabled",
  2857. plat_priv->recovery_enabled);
  2858. curr_len += buf_written;
  2859. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  2860. "WLAN PCSS recovery %s[%d]\n",
  2861. plat_priv->recovery_pcss_enabled ? "Enabled" : "Disabled",
  2862. plat_priv->recovery_pcss_enabled);
  2863. curr_len += buf_written;
  2864. /*
  2865. * Now size of curr_len is not over page size for sure,
  2866. * later if new item or none-fixed size item added, need
  2867. * add check to make sure curr_len is not over page size.
  2868. */
  2869. return curr_len;
  2870. }
  2871. static ssize_t time_sync_period_show(struct device *dev,
  2872. struct device_attribute *attr,
  2873. char *buf)
  2874. {
  2875. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2876. return scnprintf(buf, PAGE_SIZE, "%u ms\n",
  2877. plat_priv->ctrl_params.time_sync_period);
  2878. }
  2879. static ssize_t time_sync_period_store(struct device *dev,
  2880. struct device_attribute *attr,
  2881. const char *buf, size_t count)
  2882. {
  2883. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2884. unsigned int time_sync_period = 0;
  2885. if (!plat_priv)
  2886. return -ENODEV;
  2887. if (sscanf(buf, "%du", &time_sync_period) != 1) {
  2888. cnss_pr_err("Invalid time sync sysfs command\n");
  2889. return -EINVAL;
  2890. }
  2891. if (time_sync_period >= CNSS_MIN_TIME_SYNC_PERIOD)
  2892. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  2893. return count;
  2894. }
  2895. static ssize_t recovery_store(struct device *dev,
  2896. struct device_attribute *attr,
  2897. const char *buf, size_t count)
  2898. {
  2899. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2900. unsigned int recovery = 0;
  2901. int ret;
  2902. if (!plat_priv)
  2903. return -ENODEV;
  2904. if (sscanf(buf, "%du", &recovery) != 1) {
  2905. cnss_pr_err("Invalid recovery sysfs command\n");
  2906. return -EINVAL;
  2907. }
  2908. plat_priv->recovery_enabled = !!(recovery & CNSS_WLAN_RECOVERY);
  2909. plat_priv->recovery_pcss_enabled = !!(recovery & CNSS_PCSS_RECOVERY);
  2910. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  2911. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  2912. cnss_pr_dbg("%s PCSS recovery, count is %zu\n",
  2913. plat_priv->recovery_pcss_enabled ? "Enable" : "Disable", count);
  2914. ret = cnss_send_subsys_restart_level_msg(plat_priv);
  2915. if (ret < 0) {
  2916. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  2917. plat_priv->recovery_pcss_enabled = false;
  2918. return -EINVAL;
  2919. }
  2920. return count;
  2921. }
  2922. static ssize_t shutdown_store(struct device *dev,
  2923. struct device_attribute *attr,
  2924. const char *buf, size_t count)
  2925. {
  2926. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2927. if (plat_priv) {
  2928. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2929. del_timer(&plat_priv->fw_boot_timer);
  2930. complete_all(&plat_priv->power_up_complete);
  2931. complete_all(&plat_priv->cal_complete);
  2932. }
  2933. cnss_pr_dbg("Received shutdown notification\n");
  2934. return count;
  2935. }
  2936. static ssize_t fs_ready_store(struct device *dev,
  2937. struct device_attribute *attr,
  2938. const char *buf, size_t count)
  2939. {
  2940. int fs_ready = 0;
  2941. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2942. if (sscanf(buf, "%du", &fs_ready) != 1)
  2943. return -EINVAL;
  2944. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  2945. fs_ready, count);
  2946. if (!plat_priv) {
  2947. cnss_pr_err("plat_priv is NULL\n");
  2948. return count;
  2949. }
  2950. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  2951. cnss_pr_dbg("QMI is bypassed\n");
  2952. return count;
  2953. }
  2954. set_bit(CNSS_FS_READY, &plat_priv->driver_state);
  2955. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  2956. cnss_driver_event_post(plat_priv,
  2957. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  2958. 0, NULL);
  2959. }
  2960. return count;
  2961. }
  2962. static ssize_t qdss_trace_start_store(struct device *dev,
  2963. struct device_attribute *attr,
  2964. const char *buf, size_t count)
  2965. {
  2966. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2967. wlfw_qdss_trace_start(plat_priv);
  2968. cnss_pr_dbg("Received QDSS start command\n");
  2969. return count;
  2970. }
  2971. static ssize_t qdss_trace_stop_store(struct device *dev,
  2972. struct device_attribute *attr,
  2973. const char *buf, size_t count)
  2974. {
  2975. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2976. u32 option = 0;
  2977. if (sscanf(buf, "%du", &option) != 1)
  2978. return -EINVAL;
  2979. wlfw_qdss_trace_stop(plat_priv, option);
  2980. cnss_pr_dbg("Received QDSS stop command\n");
  2981. return count;
  2982. }
  2983. static ssize_t qdss_conf_download_store(struct device *dev,
  2984. struct device_attribute *attr,
  2985. const char *buf, size_t count)
  2986. {
  2987. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2988. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  2989. cnss_pr_dbg("Received QDSS download config command\n");
  2990. return count;
  2991. }
  2992. static ssize_t hw_trace_override_store(struct device *dev,
  2993. struct device_attribute *attr,
  2994. const char *buf, size_t count)
  2995. {
  2996. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2997. int tmp = 0;
  2998. if (sscanf(buf, "%du", &tmp) != 1)
  2999. return -EINVAL;
  3000. plat_priv->hw_trc_override = tmp;
  3001. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  3002. return count;
  3003. }
  3004. static ssize_t charger_mode_store(struct device *dev,
  3005. struct device_attribute *attr,
  3006. const char *buf, size_t count)
  3007. {
  3008. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3009. int tmp = 0;
  3010. if (sscanf(buf, "%du", &tmp) != 1)
  3011. return -EINVAL;
  3012. plat_priv->charger_mode = tmp;
  3013. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  3014. return count;
  3015. }
  3016. static DEVICE_ATTR_WO(fs_ready);
  3017. static DEVICE_ATTR_WO(shutdown);
  3018. static DEVICE_ATTR_RW(recovery);
  3019. static DEVICE_ATTR_WO(enable_hds);
  3020. static DEVICE_ATTR_WO(qdss_trace_start);
  3021. static DEVICE_ATTR_WO(qdss_trace_stop);
  3022. static DEVICE_ATTR_WO(qdss_conf_download);
  3023. static DEVICE_ATTR_WO(hw_trace_override);
  3024. static DEVICE_ATTR_WO(charger_mode);
  3025. static DEVICE_ATTR_RW(time_sync_period);
  3026. static struct attribute *cnss_attrs[] = {
  3027. &dev_attr_fs_ready.attr,
  3028. &dev_attr_shutdown.attr,
  3029. &dev_attr_recovery.attr,
  3030. &dev_attr_enable_hds.attr,
  3031. &dev_attr_qdss_trace_start.attr,
  3032. &dev_attr_qdss_trace_stop.attr,
  3033. &dev_attr_qdss_conf_download.attr,
  3034. &dev_attr_hw_trace_override.attr,
  3035. &dev_attr_charger_mode.attr,
  3036. &dev_attr_time_sync_period.attr,
  3037. NULL,
  3038. };
  3039. static struct attribute_group cnss_attr_group = {
  3040. .attrs = cnss_attrs,
  3041. };
  3042. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  3043. {
  3044. struct device *dev = &plat_priv->plat_dev->dev;
  3045. int ret;
  3046. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "cnss");
  3047. if (ret) {
  3048. cnss_pr_err("Failed to create cnss link, err = %d\n",
  3049. ret);
  3050. goto out;
  3051. }
  3052. /* This is only for backward compatibility. */
  3053. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "shutdown_wlan");
  3054. if (ret) {
  3055. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  3056. ret);
  3057. goto rm_cnss_link;
  3058. }
  3059. return 0;
  3060. rm_cnss_link:
  3061. sysfs_remove_link(kernel_kobj, "cnss");
  3062. out:
  3063. return ret;
  3064. }
  3065. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  3066. {
  3067. sysfs_remove_link(kernel_kobj, "shutdown_wlan");
  3068. sysfs_remove_link(kernel_kobj, "cnss");
  3069. }
  3070. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  3071. {
  3072. int ret = 0;
  3073. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  3074. &cnss_attr_group);
  3075. if (ret) {
  3076. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  3077. ret);
  3078. goto out;
  3079. }
  3080. cnss_create_sysfs_link(plat_priv);
  3081. return 0;
  3082. out:
  3083. return ret;
  3084. }
  3085. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  3086. {
  3087. cnss_remove_sysfs_link(plat_priv);
  3088. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  3089. }
  3090. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  3091. {
  3092. spin_lock_init(&plat_priv->event_lock);
  3093. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  3094. WQ_UNBOUND, 1);
  3095. if (!plat_priv->event_wq) {
  3096. cnss_pr_err("Failed to create event workqueue!\n");
  3097. return -EFAULT;
  3098. }
  3099. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  3100. INIT_LIST_HEAD(&plat_priv->event_list);
  3101. return 0;
  3102. }
  3103. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  3104. {
  3105. destroy_workqueue(plat_priv->event_wq);
  3106. }
  3107. static int cnss_reboot_notifier(struct notifier_block *nb,
  3108. unsigned long action,
  3109. void *data)
  3110. {
  3111. struct cnss_plat_data *plat_priv =
  3112. container_of(nb, struct cnss_plat_data, reboot_nb);
  3113. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3114. del_timer(&plat_priv->fw_boot_timer);
  3115. complete_all(&plat_priv->power_up_complete);
  3116. complete_all(&plat_priv->cal_complete);
  3117. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  3118. return NOTIFY_DONE;
  3119. }
  3120. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  3121. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3122. {
  3123. struct Object client_env;
  3124. struct Object app_object;
  3125. u32 wifi_uid = HW_WIFI_UID;
  3126. union ObjectArg obj_arg[2] = {{{0, 0}}};
  3127. int ret;
  3128. u8 state = 0;
  3129. /* Once this flag is set, secure peripheral feature
  3130. * will not be supported till next reboot
  3131. */
  3132. if (plat_priv->sec_peri_feature_disable)
  3133. return 0;
  3134. /* get rootObj */
  3135. ret = get_client_env_object(&client_env);
  3136. if (ret) {
  3137. cnss_pr_dbg("Failed to get client_env_object, ret: %d\n", ret);
  3138. goto end;
  3139. }
  3140. ret = IClientEnv_open(client_env, HW_STATE_UID, &app_object);
  3141. if (ret) {
  3142. cnss_pr_dbg("Failed to get app_object, ret: %d\n", ret);
  3143. if (ret == FEATURE_NOT_SUPPORTED) {
  3144. ret = 0; /* Do not Assert */
  3145. plat_priv->sec_peri_feature_disable = true;
  3146. cnss_pr_dbg("Secure HW feature not supported\n");
  3147. }
  3148. goto exit_release_clientenv;
  3149. }
  3150. obj_arg[0].b = (struct ObjectBuf) {&wifi_uid, sizeof(u32)};
  3151. obj_arg[1].b = (struct ObjectBuf) {&state, sizeof(u8)};
  3152. ret = Object_invoke(app_object, HW_OP_GET_STATE, obj_arg,
  3153. ObjectCounts_pack(1, 1, 0, 0));
  3154. cnss_pr_dbg("SMC invoke ret: %d state: %d\n", ret, state);
  3155. if (ret) {
  3156. if (ret == PERIPHERAL_NOT_FOUND) {
  3157. ret = 0; /* Do not Assert */
  3158. plat_priv->sec_peri_feature_disable = true;
  3159. cnss_pr_dbg("Secure HW mode is not updated. Peripheral not found\n");
  3160. }
  3161. goto exit_release_app_obj;
  3162. }
  3163. if (state == 1)
  3164. set_bit(CNSS_WLAN_HW_DISABLED,
  3165. &plat_priv->driver_state);
  3166. else
  3167. clear_bit(CNSS_WLAN_HW_DISABLED,
  3168. &plat_priv->driver_state);
  3169. exit_release_app_obj:
  3170. Object_release(app_object);
  3171. exit_release_clientenv:
  3172. Object_release(client_env);
  3173. end:
  3174. if (ret) {
  3175. cnss_pr_err("Unable to get HW disable status\n");
  3176. CNSS_ASSERT(0);
  3177. }
  3178. return ret;
  3179. }
  3180. #else
  3181. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3182. {
  3183. return 0;
  3184. }
  3185. #endif
  3186. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  3187. {
  3188. int ret;
  3189. ret = cnss_init_sol_gpio(plat_priv);
  3190. if (ret)
  3191. return ret;
  3192. timer_setup(&plat_priv->fw_boot_timer,
  3193. cnss_bus_fw_boot_timeout_hdlr, 0);
  3194. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  3195. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  3196. if (ret)
  3197. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  3198. ret);
  3199. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  3200. if (ret)
  3201. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  3202. ret);
  3203. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  3204. init_completion(&plat_priv->power_up_complete);
  3205. init_completion(&plat_priv->cal_complete);
  3206. init_completion(&plat_priv->rddm_complete);
  3207. init_completion(&plat_priv->recovery_complete);
  3208. init_completion(&plat_priv->daemon_connected);
  3209. mutex_init(&plat_priv->dev_lock);
  3210. mutex_init(&plat_priv->driver_ops_lock);
  3211. plat_priv->recovery_ws =
  3212. wakeup_source_register(&plat_priv->plat_dev->dev,
  3213. "CNSS_FW_RECOVERY");
  3214. if (!plat_priv->recovery_ws)
  3215. cnss_pr_err("Failed to setup FW recovery wake source\n");
  3216. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3217. cnss_daemon_connection_update_cb,
  3218. plat_priv);
  3219. if (ret)
  3220. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  3221. ret);
  3222. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  3223. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  3224. plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL);
  3225. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3226. "qcom,rc-ep-short-channel"))
  3227. cnss_set_feature_list(plat_priv, CNSS_RC_EP_ULTRASHORT_CHANNEL_V01);
  3228. return 0;
  3229. }
  3230. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  3231. {
  3232. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3233. plat_priv);
  3234. complete_all(&plat_priv->recovery_complete);
  3235. complete_all(&plat_priv->rddm_complete);
  3236. complete_all(&plat_priv->cal_complete);
  3237. complete_all(&plat_priv->power_up_complete);
  3238. complete_all(&plat_priv->daemon_connected);
  3239. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  3240. unregister_reboot_notifier(&plat_priv->reboot_nb);
  3241. del_timer(&plat_priv->fw_boot_timer);
  3242. wakeup_source_unregister(plat_priv->recovery_ws);
  3243. cnss_deinit_sol_gpio(plat_priv);
  3244. kfree(plat_priv->sram_dump);
  3245. }
  3246. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3247. {
  3248. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3249. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3250. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3251. "qcom,wlan-cbc-enabled");
  3252. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3253. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3254. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3255. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3256. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3257. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3258. * enabled by default
  3259. */
  3260. plat_priv->adsp_pc_enabled = true;
  3261. }
  3262. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3263. {
  3264. struct device *dev = &plat_priv->plat_dev->dev;
  3265. plat_priv->use_pm_domain =
  3266. of_property_read_bool(dev->of_node, "use-pm-domain");
  3267. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3268. }
  3269. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3270. {
  3271. struct device *dev = &plat_priv->plat_dev->dev;
  3272. plat_priv->set_wlaon_pwr_ctrl =
  3273. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3274. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3275. plat_priv->set_wlaon_pwr_ctrl);
  3276. }
  3277. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3278. {
  3279. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3280. "qcom,converged-dt") ||
  3281. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3282. "qcom,same-dt-multi-dev") ||
  3283. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3284. "qcom,multi-wlan-exchg"));
  3285. }
  3286. static const struct platform_device_id cnss_platform_id_table[] = {
  3287. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3288. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3289. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3290. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3291. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3292. { .name = "mango", .driver_data = MANGO_DEVICE_ID, },
  3293. { .name = "qcaconv", .driver_data = 0, },
  3294. { },
  3295. };
  3296. static const struct of_device_id cnss_of_match_table[] = {
  3297. {
  3298. .compatible = "qcom,cnss",
  3299. .data = (void *)&cnss_platform_id_table[0]},
  3300. {
  3301. .compatible = "qcom,cnss-qca6290",
  3302. .data = (void *)&cnss_platform_id_table[1]},
  3303. {
  3304. .compatible = "qcom,cnss-qca6390",
  3305. .data = (void *)&cnss_platform_id_table[2]},
  3306. {
  3307. .compatible = "qcom,cnss-qca6490",
  3308. .data = (void *)&cnss_platform_id_table[3]},
  3309. {
  3310. .compatible = "qcom,cnss-kiwi",
  3311. .data = (void *)&cnss_platform_id_table[4]},
  3312. {
  3313. .compatible = "qcom,cnss-mango",
  3314. .data = (void *)&cnss_platform_id_table[5]},
  3315. {
  3316. .compatible = "qcom,cnss-qca-converged",
  3317. .data = (void *)&cnss_platform_id_table[6]},
  3318. { },
  3319. };
  3320. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3321. static inline bool
  3322. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3323. {
  3324. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3325. "use-nv-mac");
  3326. }
  3327. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  3328. {
  3329. struct device_node *child;
  3330. u32 id, i;
  3331. int id_n, device_identifier_gpio, ret;
  3332. u8 gpio_value;
  3333. if (plat_priv->dt_type != CNSS_DTT_CONVERGED)
  3334. return 0;
  3335. /* Parses the wlan_sw_ctrl gpio which is used to identify device */
  3336. ret = cnss_get_wlan_sw_ctrl(plat_priv);
  3337. if (ret) {
  3338. cnss_pr_dbg("Failed to parse wlan_sw_ctrl gpio, error:%d", ret);
  3339. return ret;
  3340. }
  3341. device_identifier_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  3342. gpio_value = gpio_get_value(device_identifier_gpio);
  3343. cnss_pr_dbg("Value of Device Identifier GPIO: %d\n", gpio_value);
  3344. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  3345. child) {
  3346. if (strcmp(child->name, "chip_cfg"))
  3347. continue;
  3348. id_n = of_property_count_u32_elems(child, "supported-ids");
  3349. if (id_n <= 0) {
  3350. cnss_pr_err("Device id is NOT set\n");
  3351. return -EINVAL;
  3352. }
  3353. for (i = 0; i < id_n; i++) {
  3354. ret = of_property_read_u32_index(child,
  3355. "supported-ids",
  3356. i, &id);
  3357. if (ret) {
  3358. cnss_pr_err("Failed to read supported ids\n");
  3359. return -EINVAL;
  3360. }
  3361. if (gpio_value && id == QCA6490_DEVICE_ID) {
  3362. plat_priv->plat_dev->dev.of_node = child;
  3363. plat_priv->device_id = QCA6490_DEVICE_ID;
  3364. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  3365. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3366. child->name, i, id);
  3367. return 0;
  3368. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  3369. plat_priv->plat_dev->dev.of_node = child;
  3370. plat_priv->device_id = KIWI_DEVICE_ID;
  3371. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  3372. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3373. child->name, i, id);
  3374. return 0;
  3375. }
  3376. }
  3377. }
  3378. return -EINVAL;
  3379. }
  3380. static inline u32
  3381. cnss_dt_type(struct cnss_plat_data *plat_priv)
  3382. {
  3383. bool is_converged_dt = of_property_read_bool(
  3384. plat_priv->plat_dev->dev.of_node, "qcom,converged-dt");
  3385. bool is_multi_wlan_xchg;
  3386. if (is_converged_dt)
  3387. return CNSS_DTT_CONVERGED;
  3388. is_multi_wlan_xchg = of_property_read_bool(
  3389. plat_priv->plat_dev->dev.of_node, "qcom,multi-wlan-exchg");
  3390. if (is_multi_wlan_xchg)
  3391. return CNSS_DTT_MULTIEXCHG;
  3392. return CNSS_DTT_LEGACY;
  3393. }
  3394. static int cnss_wlan_device_init(struct cnss_plat_data *plat_priv)
  3395. {
  3396. int ret = 0;
  3397. int retry = 0;
  3398. if (test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3399. return 0;
  3400. retry:
  3401. ret = cnss_power_on_device(plat_priv);
  3402. if (ret)
  3403. goto end;
  3404. ret = cnss_bus_init(plat_priv);
  3405. if (ret) {
  3406. if ((ret != -EPROBE_DEFER) &&
  3407. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3408. cnss_power_off_device(plat_priv);
  3409. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3410. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3411. goto retry;
  3412. }
  3413. goto power_off;
  3414. }
  3415. return 0;
  3416. power_off:
  3417. cnss_power_off_device(plat_priv);
  3418. end:
  3419. return ret;
  3420. }
  3421. int cnss_wlan_hw_enable(void)
  3422. {
  3423. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3424. int ret = 0;
  3425. clear_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state);
  3426. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  3427. goto register_driver;
  3428. ret = cnss_wlan_device_init(plat_priv);
  3429. if (ret) {
  3430. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state))
  3431. CNSS_ASSERT(0);
  3432. return ret;
  3433. }
  3434. if (test_bit(CNSS_FS_READY, &plat_priv->driver_state))
  3435. cnss_driver_event_post(plat_priv,
  3436. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3437. 0, NULL);
  3438. register_driver:
  3439. if (plat_priv->driver_ops)
  3440. ret = cnss_wlan_register_driver(plat_priv->driver_ops);
  3441. return ret;
  3442. }
  3443. EXPORT_SYMBOL(cnss_wlan_hw_enable);
  3444. static int cnss_probe(struct platform_device *plat_dev)
  3445. {
  3446. int ret = 0;
  3447. struct cnss_plat_data *plat_priv;
  3448. const struct of_device_id *of_id;
  3449. const struct platform_device_id *device_id;
  3450. if (cnss_get_plat_priv(plat_dev)) {
  3451. cnss_pr_err("Driver is already initialized!\n");
  3452. ret = -EEXIST;
  3453. goto out;
  3454. }
  3455. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  3456. if (!of_id || !of_id->data) {
  3457. cnss_pr_err("Failed to find of match device!\n");
  3458. ret = -ENODEV;
  3459. goto out;
  3460. }
  3461. device_id = of_id->data;
  3462. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  3463. GFP_KERNEL);
  3464. if (!plat_priv) {
  3465. ret = -ENOMEM;
  3466. goto out;
  3467. }
  3468. plat_priv->plat_dev = plat_dev;
  3469. plat_priv->dev_node = NULL;
  3470. plat_priv->device_id = device_id->driver_data;
  3471. plat_priv->dt_type = cnss_dt_type(plat_priv);
  3472. cnss_pr_dbg("Probing platform driver from dt type: %d\n",
  3473. plat_priv->dt_type);
  3474. plat_priv->use_fw_path_with_prefix =
  3475. cnss_use_fw_path_with_prefix(plat_priv);
  3476. ret = cnss_get_dev_cfg_node(plat_priv);
  3477. if (ret) {
  3478. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  3479. goto reset_plat_dev;
  3480. }
  3481. plat_priv->bus_type = cnss_get_bus_type(plat_priv);
  3482. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  3483. plat_priv->driver_mode = CNSS_DRIVER_MODE_MAX;
  3484. cnss_set_plat_priv(plat_dev, plat_priv);
  3485. platform_set_drvdata(plat_dev, plat_priv);
  3486. INIT_LIST_HEAD(&plat_priv->vreg_list);
  3487. INIT_LIST_HEAD(&plat_priv->clk_list);
  3488. cnss_get_pm_domain_info(plat_priv);
  3489. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  3490. cnss_power_misc_params_init(plat_priv);
  3491. cnss_get_tcs_info(plat_priv);
  3492. cnss_get_cpr_info(plat_priv);
  3493. cnss_aop_mbox_init(plat_priv);
  3494. cnss_init_control_params(plat_priv);
  3495. ret = cnss_get_resources(plat_priv);
  3496. if (ret)
  3497. goto reset_ctx;
  3498. ret = cnss_register_esoc(plat_priv);
  3499. if (ret)
  3500. goto free_res;
  3501. ret = cnss_register_bus_scale(plat_priv);
  3502. if (ret)
  3503. goto unreg_esoc;
  3504. ret = cnss_create_sysfs(plat_priv);
  3505. if (ret)
  3506. goto unreg_bus_scale;
  3507. ret = cnss_event_work_init(plat_priv);
  3508. if (ret)
  3509. goto remove_sysfs;
  3510. ret = cnss_qmi_init(plat_priv);
  3511. if (ret)
  3512. goto deinit_event_work;
  3513. ret = cnss_dms_init(plat_priv);
  3514. if (ret)
  3515. goto deinit_qmi;
  3516. ret = cnss_debugfs_create(plat_priv);
  3517. if (ret)
  3518. goto deinit_dms;
  3519. ret = cnss_misc_init(plat_priv);
  3520. if (ret)
  3521. goto destroy_debugfs;
  3522. ret = cnss_wlan_hw_disable_check(plat_priv);
  3523. if (ret)
  3524. goto deinit_misc;
  3525. /* Make sure all platform related init are done before
  3526. * device power on and bus init.
  3527. */
  3528. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  3529. ret = cnss_wlan_device_init(plat_priv);
  3530. if (ret)
  3531. goto deinit_misc;
  3532. } else {
  3533. cnss_pr_info("WLAN HW Disabled. Defer PCI enumeration\n");
  3534. }
  3535. cnss_register_coex_service(plat_priv);
  3536. cnss_register_ims_service(plat_priv);
  3537. ret = cnss_genl_init();
  3538. if (ret < 0)
  3539. cnss_pr_err("CNSS genl init failed %d\n", ret);
  3540. cnss_pr_info("Platform driver probed successfully.\n");
  3541. return 0;
  3542. deinit_misc:
  3543. cnss_misc_deinit(plat_priv);
  3544. destroy_debugfs:
  3545. cnss_debugfs_destroy(plat_priv);
  3546. deinit_dms:
  3547. cnss_dms_deinit(plat_priv);
  3548. deinit_qmi:
  3549. cnss_qmi_deinit(plat_priv);
  3550. deinit_event_work:
  3551. cnss_event_work_deinit(plat_priv);
  3552. remove_sysfs:
  3553. cnss_remove_sysfs(plat_priv);
  3554. unreg_bus_scale:
  3555. cnss_unregister_bus_scale(plat_priv);
  3556. unreg_esoc:
  3557. cnss_unregister_esoc(plat_priv);
  3558. free_res:
  3559. cnss_put_resources(plat_priv);
  3560. reset_ctx:
  3561. platform_set_drvdata(plat_dev, NULL);
  3562. reset_plat_dev:
  3563. cnss_set_plat_priv(plat_dev, NULL);
  3564. out:
  3565. return ret;
  3566. }
  3567. static int cnss_remove(struct platform_device *plat_dev)
  3568. {
  3569. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  3570. cnss_genl_exit();
  3571. cnss_unregister_ims_service(plat_priv);
  3572. cnss_unregister_coex_service(plat_priv);
  3573. cnss_bus_deinit(plat_priv);
  3574. cnss_misc_deinit(plat_priv);
  3575. cnss_debugfs_destroy(plat_priv);
  3576. cnss_dms_deinit(plat_priv);
  3577. cnss_qmi_deinit(plat_priv);
  3578. cnss_event_work_deinit(plat_priv);
  3579. cnss_cancel_dms_work();
  3580. cnss_remove_sysfs(plat_priv);
  3581. cnss_unregister_bus_scale(plat_priv);
  3582. cnss_unregister_esoc(plat_priv);
  3583. cnss_put_resources(plat_priv);
  3584. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  3585. mbox_free_channel(plat_priv->mbox_chan);
  3586. platform_set_drvdata(plat_dev, NULL);
  3587. plat_env = NULL;
  3588. return 0;
  3589. }
  3590. static struct platform_driver cnss_platform_driver = {
  3591. .probe = cnss_probe,
  3592. .remove = cnss_remove,
  3593. .driver = {
  3594. .name = "cnss2",
  3595. .of_match_table = cnss_of_match_table,
  3596. #ifdef CONFIG_CNSS_ASYNC
  3597. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  3598. #endif
  3599. },
  3600. };
  3601. static bool cnss_check_compatible_node(void)
  3602. {
  3603. struct device_node *dn = NULL;
  3604. for_each_matching_node(dn, cnss_of_match_table) {
  3605. if (of_device_is_available(dn)) {
  3606. cnss_allow_driver_loading = true;
  3607. return true;
  3608. }
  3609. }
  3610. return false;
  3611. }
  3612. /**
  3613. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  3614. *
  3615. * Valid device tree node means a node with "compatible" property from the
  3616. * device match table and "status" property is not disabled.
  3617. *
  3618. * Return: true if valid device tree node found, false if not found
  3619. */
  3620. static bool cnss_is_valid_dt_node_found(void)
  3621. {
  3622. struct device_node *dn = NULL;
  3623. for_each_matching_node(dn, cnss_of_match_table) {
  3624. if (of_device_is_available(dn))
  3625. break;
  3626. }
  3627. if (dn)
  3628. return true;
  3629. return false;
  3630. }
  3631. static int __init cnss_initialize(void)
  3632. {
  3633. int ret = 0;
  3634. if (!cnss_is_valid_dt_node_found())
  3635. return -ENODEV;
  3636. if (!cnss_check_compatible_node())
  3637. return ret;
  3638. cnss_debug_init();
  3639. ret = platform_driver_register(&cnss_platform_driver);
  3640. if (ret)
  3641. cnss_debug_deinit();
  3642. return ret;
  3643. }
  3644. static void __exit cnss_exit(void)
  3645. {
  3646. platform_driver_unregister(&cnss_platform_driver);
  3647. cnss_debug_deinit();
  3648. }
  3649. module_init(cnss_initialize);
  3650. module_exit(cnss_exit);
  3651. MODULE_LICENSE("GPL v2");
  3652. MODULE_DESCRIPTION("CNSS2 Platform Driver");