dp_be.c 27 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <wlan_utility.h>
  19. #include <dp_internal.h>
  20. #include <dp_htt.h>
  21. #include "dp_be.h"
  22. #include "dp_be_tx.h"
  23. #include "dp_be_rx.h"
  24. #include <hal_be_api.h>
  25. /* Generic AST entry aging timer value */
  26. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  27. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  28. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  29. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  30. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  31. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  32. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  33. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  34. };
  35. #else
  36. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  37. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  38. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  39. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  40. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  41. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  42. };
  43. #endif
  44. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  45. {
  46. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  47. }
  48. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  49. {
  50. switch (context_type) {
  51. case DP_CONTEXT_TYPE_SOC:
  52. return sizeof(struct dp_soc_be);
  53. case DP_CONTEXT_TYPE_PDEV:
  54. return sizeof(struct dp_pdev_be);
  55. case DP_CONTEXT_TYPE_VDEV:
  56. return sizeof(struct dp_vdev_be);
  57. case DP_CONTEXT_TYPE_PEER:
  58. return sizeof(struct dp_peer_be);
  59. default:
  60. return 0;
  61. }
  62. }
  63. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  64. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  65. /**
  66. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  67. per wbm2sw ring
  68. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  69. *
  70. * Return: None
  71. */
  72. static inline
  73. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  74. {
  75. cc_cfg->wbm2sw6_cc_en = 1;
  76. cc_cfg->wbm2sw5_cc_en = 1;
  77. cc_cfg->wbm2sw4_cc_en = 1;
  78. cc_cfg->wbm2sw3_cc_en = 1;
  79. cc_cfg->wbm2sw2_cc_en = 1;
  80. /* disable wbm2sw1 hw cc as it's for FW */
  81. cc_cfg->wbm2sw1_cc_en = 0;
  82. cc_cfg->wbm2sw0_cc_en = 1;
  83. cc_cfg->wbm2fw_cc_en = 0;
  84. }
  85. #else
  86. static inline
  87. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  88. {
  89. cc_cfg->wbm2sw6_cc_en = 1;
  90. cc_cfg->wbm2sw5_cc_en = 1;
  91. cc_cfg->wbm2sw4_cc_en = 1;
  92. cc_cfg->wbm2sw3_cc_en = 1;
  93. cc_cfg->wbm2sw2_cc_en = 1;
  94. cc_cfg->wbm2sw1_cc_en = 1;
  95. cc_cfg->wbm2sw0_cc_en = 1;
  96. cc_cfg->wbm2fw_cc_en = 0;
  97. }
  98. #endif
  99. /**
  100. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  101. conversion register
  102. * @soc: SOC handle
  103. * @cc_ctx: cookie conversion context pointer
  104. * @is_4k_align: page address 4k alignd
  105. *
  106. * Return: None
  107. */
  108. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  109. struct dp_hw_cookie_conversion_t *cc_ctx,
  110. bool is_4k_align)
  111. {
  112. struct hal_hw_cc_config cc_cfg = { 0 };
  113. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  114. dp_info("INI skip HW CC register setting");
  115. return;
  116. }
  117. cc_cfg.lut_base_addr_31_0 = cc_ctx->cmem_base;
  118. cc_cfg.cc_global_en = true;
  119. cc_cfg.page_4k_align = is_4k_align;
  120. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  121. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  122. /* 36th bit should be 1 then HW know this is CMEM address */
  123. cc_cfg.lut_base_addr_39_32 = 0x10;
  124. cc_cfg.error_path_cookie_conv_en = true;
  125. cc_cfg.release_path_cookie_conv_en = true;
  126. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  127. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  128. }
  129. /**
  130. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  131. * @hal_soc_hdl: HAL SOC handle
  132. * @offset: CMEM address
  133. * @value: value to write
  134. *
  135. * Return: None.
  136. */
  137. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  138. uint32_t offset,
  139. uint32_t value)
  140. {
  141. hal_cmem_write(hal_soc_hdl, offset, value);
  142. }
  143. /**
  144. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  145. HW cookie conversion
  146. * @soc: SOC handle
  147. * @cc_ctx: cookie conversion context pointer
  148. *
  149. * Return: 0 in case of success, else error value
  150. */
  151. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(
  152. struct dp_soc *soc,
  153. struct dp_hw_cookie_conversion_t *cc_ctx)
  154. {
  155. dp_info("cmem base 0x%llx, size 0x%llx",
  156. soc->cmem_base, soc->cmem_size);
  157. /* get CMEM for cookie conversion */
  158. if (soc->cmem_size < DP_CC_PPT_MEM_SIZE) {
  159. dp_err("cmem_size %llu bytes < 4K", soc->cmem_size);
  160. return QDF_STATUS_E_RESOURCES;
  161. }
  162. cc_ctx->cmem_base = (uint32_t)(soc->cmem_base +
  163. DP_CC_MEM_OFFSET_IN_CMEM);
  164. return QDF_STATUS_SUCCESS;
  165. }
  166. #else
  167. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  168. struct dp_hw_cookie_conversion_t *cc_ctx,
  169. bool is_4k_align) {}
  170. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  171. uint32_t offset,
  172. uint32_t value)
  173. { }
  174. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(
  175. struct dp_soc *soc,
  176. struct dp_hw_cookie_conversion_t *cc_ctx)
  177. {
  178. return QDF_STATUS_SUCCESS;
  179. }
  180. #endif
  181. static QDF_STATUS dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc)
  182. {
  183. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  184. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  185. uint32_t max_tx_rx_desc_num, num_spt_pages, i = 0;
  186. struct dp_spt_page_desc *spt_desc;
  187. struct qdf_mem_dma_page_t *dma_page;
  188. QDF_STATUS qdf_status;
  189. if (soc->cdp_soc.ol_ops->get_con_mode &&
  190. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  191. return QDF_STATUS_SUCCESS;
  192. qdf_status = dp_hw_cc_cmem_addr_init(soc, cc_ctx);
  193. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  194. return qdf_status;
  195. /* estimate how many SPT DDR pages needed */
  196. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  197. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  198. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  199. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  200. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  201. dp_info("num_spt_pages needed %d", num_spt_pages);
  202. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  203. &cc_ctx->page_pool, qdf_page_size,
  204. num_spt_pages, 0, false);
  205. if (!cc_ctx->page_pool.dma_pages) {
  206. dp_err("spt ddr pages allocation failed");
  207. return QDF_STATUS_E_RESOURCES;
  208. }
  209. cc_ctx->page_desc_base = qdf_mem_malloc(
  210. num_spt_pages * sizeof(struct dp_spt_page_desc));
  211. if (!cc_ctx->page_desc_base) {
  212. dp_err("spt page descs allocation failed");
  213. goto fail_0;
  214. }
  215. /* initial page desc */
  216. spt_desc = cc_ctx->page_desc_base;
  217. dma_page = cc_ctx->page_pool.dma_pages;
  218. while (i < num_spt_pages) {
  219. /* check if page address 4K aligned */
  220. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  221. dp_err("non-4k aligned pages addr %pK",
  222. (void *)dma_page[i].page_p_addr);
  223. goto fail_1;
  224. }
  225. spt_desc[i].page_v_addr =
  226. dma_page[i].page_v_addr_start;
  227. spt_desc[i].page_p_addr =
  228. dma_page[i].page_p_addr;
  229. i++;
  230. }
  231. cc_ctx->total_page_num = num_spt_pages;
  232. qdf_spinlock_create(&cc_ctx->cc_lock);
  233. return QDF_STATUS_SUCCESS;
  234. fail_1:
  235. qdf_mem_free(cc_ctx->page_desc_base);
  236. fail_0:
  237. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  238. &cc_ctx->page_pool, 0, false);
  239. return QDF_STATUS_E_FAILURE;
  240. }
  241. static QDF_STATUS dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc)
  242. {
  243. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  244. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  245. if (soc->cdp_soc.ol_ops->get_con_mode &&
  246. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  247. return QDF_STATUS_SUCCESS;
  248. qdf_mem_free(cc_ctx->page_desc_base);
  249. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  250. &cc_ctx->page_pool, 0, false);
  251. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  252. return QDF_STATUS_SUCCESS;
  253. }
  254. static QDF_STATUS dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc)
  255. {
  256. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  257. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  258. uint32_t i = 0;
  259. struct dp_spt_page_desc *spt_desc;
  260. if (soc->cdp_soc.ol_ops->get_con_mode &&
  261. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  262. return QDF_STATUS_SUCCESS;
  263. if (!cc_ctx->total_page_num) {
  264. dp_err("total page num is 0");
  265. return QDF_STATUS_E_INVAL;
  266. }
  267. spt_desc = cc_ctx->page_desc_base;
  268. while (i < cc_ctx->total_page_num) {
  269. /* write page PA to CMEM */
  270. dp_hw_cc_cmem_write(soc->hal_soc,
  271. (cc_ctx->cmem_base +
  272. i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED),
  273. (spt_desc[i].page_p_addr >>
  274. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  275. spt_desc[i].ppt_index = i;
  276. spt_desc[i].avail_entry_index = 0;
  277. /* link page desc */
  278. if ((i + 1) != cc_ctx->total_page_num)
  279. spt_desc[i].next = &spt_desc[i + 1];
  280. else
  281. spt_desc[i].next = NULL;
  282. i++;
  283. }
  284. cc_ctx->page_desc_freelist = cc_ctx->page_desc_base;
  285. cc_ctx->free_page_num = cc_ctx->total_page_num;
  286. /* write WBM/REO cookie conversion CFG register */
  287. dp_cc_reg_cfg_init(soc, cc_ctx, true);
  288. return QDF_STATUS_SUCCESS;
  289. }
  290. static QDF_STATUS dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc)
  291. {
  292. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  293. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  294. if (soc->cdp_soc.ol_ops->get_con_mode &&
  295. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  296. return QDF_STATUS_SUCCESS;
  297. cc_ctx->page_desc_freelist = NULL;
  298. cc_ctx->free_page_num = 0;
  299. return QDF_STATUS_SUCCESS;
  300. }
  301. uint16_t dp_cc_spt_page_desc_alloc(struct dp_soc_be *be_soc,
  302. struct dp_spt_page_desc **list_head,
  303. struct dp_spt_page_desc **list_tail,
  304. uint16_t num_desc)
  305. {
  306. uint16_t num_pages, count;
  307. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  308. num_pages = (num_desc / DP_CC_SPT_PAGE_MAX_ENTRIES) +
  309. (num_desc % DP_CC_SPT_PAGE_MAX_ENTRIES ? 1 : 0);
  310. if (num_pages > cc_ctx->free_page_num) {
  311. dp_err("fail: num_pages required %d > free_page_num %d",
  312. num_pages,
  313. cc_ctx->free_page_num);
  314. return 0;
  315. }
  316. qdf_spin_lock_bh(&cc_ctx->cc_lock);
  317. *list_head = *list_tail = cc_ctx->page_desc_freelist;
  318. for (count = 0; count < num_pages; count++) {
  319. if (qdf_unlikely(!cc_ctx->page_desc_freelist)) {
  320. cc_ctx->page_desc_freelist = *list_head;
  321. *list_head = *list_tail = NULL;
  322. qdf_spin_unlock_bh(&cc_ctx->cc_lock);
  323. return 0;
  324. }
  325. *list_tail = cc_ctx->page_desc_freelist;
  326. cc_ctx->page_desc_freelist = cc_ctx->page_desc_freelist->next;
  327. }
  328. (*list_tail)->next = NULL;
  329. cc_ctx->free_page_num -= count;
  330. qdf_spin_unlock_bh(&cc_ctx->cc_lock);
  331. return count;
  332. }
  333. void dp_cc_spt_page_desc_free(struct dp_soc_be *be_soc,
  334. struct dp_spt_page_desc **list_head,
  335. struct dp_spt_page_desc **list_tail,
  336. uint16_t page_nums)
  337. {
  338. struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
  339. struct dp_spt_page_desc *temp_list = NULL;
  340. qdf_spin_lock_bh(&cc_ctx->cc_lock);
  341. temp_list = cc_ctx->page_desc_freelist;
  342. cc_ctx->page_desc_freelist = *list_head;
  343. (*list_tail)->next = temp_list;
  344. cc_ctx->free_page_num += page_nums;
  345. *list_tail = NULL;
  346. *list_head = NULL;
  347. qdf_spin_unlock_bh(&cc_ctx->cc_lock);
  348. }
  349. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc)
  350. {
  351. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  352. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  353. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  354. qdf_status = dp_tx_init_bank_profiles(be_soc);
  355. /* cookie conversion */
  356. qdf_status = dp_hw_cookie_conversion_attach(be_soc);
  357. return qdf_status;
  358. }
  359. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  360. {
  361. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  362. dp_tx_deinit_bank_profiles(be_soc);
  363. dp_hw_cookie_conversion_detach(be_soc);
  364. return QDF_STATUS_SUCCESS;
  365. }
  366. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  367. {
  368. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  369. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  370. qdf_status = dp_hw_cookie_conversion_init(be_soc);
  371. return qdf_status;
  372. }
  373. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  374. {
  375. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  376. dp_hw_cookie_conversion_deinit(be_soc);
  377. return QDF_STATUS_SUCCESS;
  378. }
  379. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev)
  380. {
  381. return QDF_STATUS_SUCCESS;
  382. }
  383. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  384. {
  385. return QDF_STATUS_SUCCESS;
  386. }
  387. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  388. {
  389. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  390. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  391. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  392. /* Needs to be enabled after bring-up*/
  393. be_vdev->vdev_id_check_en = false;
  394. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  395. QDF_BUG(0);
  396. return QDF_STATUS_E_FAULT;
  397. }
  398. if (vdev->opmode == wlan_op_mode_sta) {
  399. if (soc->cdp_soc.ol_ops->set_mec_timer)
  400. soc->cdp_soc.ol_ops->set_mec_timer(
  401. soc->ctrl_psoc,
  402. vdev->vdev_id,
  403. DP_AST_AGING_TIMER_DEFAULT_MS);
  404. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  405. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  406. }
  407. return QDF_STATUS_SUCCESS;
  408. }
  409. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  410. {
  411. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  412. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  413. dp_tx_put_bank_profile(be_soc, be_vdev);
  414. return QDF_STATUS_SUCCESS;
  415. }
  416. qdf_size_t dp_get_soc_context_size_be(void)
  417. {
  418. return sizeof(struct dp_soc_be);
  419. }
  420. /**
  421. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  422. * @soc: Common DP soc handle
  423. *
  424. * Return: QDF_STATUS
  425. */
  426. static QDF_STATUS
  427. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  428. {
  429. int i;
  430. int mac_id;
  431. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  432. struct dp_srng *rx_mac_srng;
  433. QDF_STATUS status = QDF_STATUS_SUCCESS;
  434. /*
  435. * In Beryllium chipset msdu_start, mpdu_end
  436. * and rx_attn are part of msdu_end/mpdu_start
  437. */
  438. htt_tlv_filter.msdu_start = 0;
  439. htt_tlv_filter.mpdu_end = 0;
  440. htt_tlv_filter.attention = 0;
  441. htt_tlv_filter.mpdu_start = 1;
  442. htt_tlv_filter.msdu_end = 1;
  443. htt_tlv_filter.packet = 1;
  444. htt_tlv_filter.packet_header = 1;
  445. htt_tlv_filter.ppdu_start = 0;
  446. htt_tlv_filter.ppdu_end = 0;
  447. htt_tlv_filter.ppdu_end_user_stats = 0;
  448. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  449. htt_tlv_filter.ppdu_end_status_done = 0;
  450. htt_tlv_filter.enable_fp = 1;
  451. htt_tlv_filter.enable_md = 0;
  452. htt_tlv_filter.enable_md = 0;
  453. htt_tlv_filter.enable_mo = 0;
  454. htt_tlv_filter.fp_mgmt_filter = 0;
  455. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  456. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  457. FILTER_DATA_MCAST |
  458. FILTER_DATA_DATA);
  459. htt_tlv_filter.mo_mgmt_filter = 0;
  460. htt_tlv_filter.mo_ctrl_filter = 0;
  461. htt_tlv_filter.mo_data_filter = 0;
  462. htt_tlv_filter.md_data_filter = 0;
  463. htt_tlv_filter.offset_valid = true;
  464. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  465. htt_tlv_filter.rx_mpdu_end_offset = 0;
  466. htt_tlv_filter.rx_msdu_start_offset = 0;
  467. htt_tlv_filter.rx_attn_offset = 0;
  468. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  469. htt_tlv_filter.rx_header_offset =
  470. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  471. htt_tlv_filter.rx_mpdu_start_offset =
  472. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  473. htt_tlv_filter.rx_msdu_end_offset =
  474. hal_rx_msdu_end_offset_get(soc->hal_soc);
  475. dp_info("TLV subscription\n"
  476. "msdu_start %d, mpdu_end %d, attention %d"
  477. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  478. "TLV offsets\n"
  479. "msdu_start %d, mpdu_end %d, attention %d"
  480. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  481. htt_tlv_filter.msdu_start,
  482. htt_tlv_filter.mpdu_end,
  483. htt_tlv_filter.attention,
  484. htt_tlv_filter.mpdu_start,
  485. htt_tlv_filter.msdu_end,
  486. htt_tlv_filter.packet_header,
  487. htt_tlv_filter.packet,
  488. htt_tlv_filter.rx_msdu_start_offset,
  489. htt_tlv_filter.rx_mpdu_end_offset,
  490. htt_tlv_filter.rx_attn_offset,
  491. htt_tlv_filter.rx_mpdu_start_offset,
  492. htt_tlv_filter.rx_msdu_end_offset,
  493. htt_tlv_filter.rx_header_offset,
  494. htt_tlv_filter.rx_packet_offset);
  495. for (i = 0; i < MAX_PDEV_CNT; i++) {
  496. struct dp_pdev *pdev = soc->pdev_list[i];
  497. if (!pdev)
  498. continue;
  499. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  500. int mac_for_pdev =
  501. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  502. /*
  503. * Obtain lmac id from pdev to access the LMAC ring
  504. * in soc context
  505. */
  506. int lmac_id =
  507. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  508. pdev->pdev_id);
  509. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  510. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  511. rx_mac_srng->hal_srng,
  512. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  513. &htt_tlv_filter);
  514. }
  515. }
  516. return status;
  517. }
  518. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  519. /**
  520. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  521. * near-full IRQs.
  522. * @soc: Datapath SoC handle
  523. * @int_ctx: Interrupt context
  524. * @dp_budget: Budget of the work that can be done in the bottom half
  525. *
  526. * Return: work done in the handler
  527. */
  528. static uint32_t
  529. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  530. uint32_t dp_budget)
  531. {
  532. int ring = 0;
  533. int budget = dp_budget;
  534. uint32_t work_done = 0;
  535. uint32_t remaining_quota = dp_budget;
  536. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  537. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  538. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  539. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  540. int rx_near_full_mask = rx_near_full_grp_1_mask |
  541. rx_near_full_grp_2_mask;
  542. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  543. rx_near_full_mask,
  544. tx_ring_near_full_mask);
  545. if (rx_near_full_mask) {
  546. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  547. if (!(rx_near_full_mask & (1 << ring)))
  548. continue;
  549. work_done = dp_rx_nf_process(int_ctx,
  550. soc->reo_dest_ring[ring].hal_srng,
  551. ring, remaining_quota);
  552. if (work_done) {
  553. intr_stats->num_rx_ring_near_full_masks[ring]++;
  554. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  555. rx_near_full_mask, ring,
  556. work_done,
  557. budget);
  558. budget -= work_done;
  559. if (budget <= 0)
  560. goto budget_done;
  561. remaining_quota = budget;
  562. }
  563. }
  564. }
  565. if (tx_ring_near_full_mask) {
  566. for (ring = 0; ring < MAX_TCL_DATA_RINGS; ring++) {
  567. if (!(tx_ring_near_full_mask & (1 << ring)))
  568. continue;
  569. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  570. soc->tx_comp_ring[ring].hal_srng,
  571. ring, remaining_quota);
  572. if (work_done) {
  573. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  574. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  575. tx_ring_near_full_mask, ring,
  576. work_done, budget);
  577. budget -= work_done;
  578. if (budget <= 0)
  579. break;
  580. remaining_quota = budget;
  581. }
  582. }
  583. }
  584. intr_stats->num_near_full_masks++;
  585. budget_done:
  586. return dp_budget - budget;
  587. }
  588. /**
  589. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  590. * state and set the reap_limit appropriately
  591. * as per the near full state
  592. * @soc: Datapath soc handle
  593. * @dp_srng: Datapath handle for SRNG
  594. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  595. * the srng near-full state
  596. *
  597. * Return: 1, if the srng is in near-full state
  598. * 0, if the srng is not in near-full state
  599. */
  600. static int
  601. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  602. struct dp_srng *dp_srng,
  603. int *max_reap_limit)
  604. {
  605. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  606. }
  607. /**
  608. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  609. * near full IRQ handling operations.
  610. * @arch_ops: arch ops handle
  611. *
  612. * Return: none
  613. */
  614. static inline void
  615. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  616. {
  617. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  618. arch_ops->dp_srng_test_and_update_nf_params =
  619. dp_srng_test_and_update_nf_params_be;
  620. }
  621. #else
  622. static inline void
  623. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  624. {
  625. }
  626. #endif
  627. #ifdef WLAN_SUPPORT_PPEDS
  628. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  629. {
  630. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  631. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  632. soc_cfg_ctx = soc->wlan_cfg_ctx;
  633. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  634. return;
  635. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  636. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  637. be_soc->ppe_release_ring.alloc_size,
  638. soc->ctrl_psoc,
  639. WLAN_MD_DP_SRNG_PPE_RELEASE,
  640. "ppe_release_ring");
  641. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  642. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  643. be_soc->ppe2tcl_ring.alloc_size,
  644. soc->ctrl_psoc,
  645. WLAN_MD_DP_SRNG_PPE2TCL,
  646. "ppe2tcl_ring");
  647. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  648. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  649. be_soc->reo2ppe_ring.alloc_size,
  650. soc->ctrl_psoc,
  651. WLAN_MD_DP_SRNG_REO2PPE,
  652. "reo2ppe_ring");
  653. }
  654. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  655. {
  656. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  657. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  658. soc_cfg_ctx = soc->wlan_cfg_ctx;
  659. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  660. return;
  661. dp_srng_free(soc, &be_soc->ppe_release_ring);
  662. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  663. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  664. }
  665. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  666. {
  667. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  668. uint32_t entries;
  669. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  670. soc_cfg_ctx = soc->wlan_cfg_ctx;
  671. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  672. return QDF_STATUS_SUCCESS;
  673. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  674. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  675. entries, 0)) {
  676. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  677. goto fail;
  678. }
  679. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  680. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  681. entries, 0)) {
  682. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  683. goto fail;
  684. }
  685. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  686. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  687. entries, 0)) {
  688. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  689. goto fail;
  690. }
  691. return QDF_STATUS_SUCCESS;
  692. fail:
  693. dp_soc_ppe_srng_free(soc);
  694. return QDF_STATUS_E_NOMEM;
  695. }
  696. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  697. {
  698. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  699. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  700. soc_cfg_ctx = soc->wlan_cfg_ctx;
  701. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  702. return QDF_STATUS_SUCCESS;
  703. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  704. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  705. goto fail;
  706. }
  707. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  708. be_soc->reo2ppe_ring.alloc_size,
  709. soc->ctrl_psoc,
  710. WLAN_MD_DP_SRNG_REO2PPE,
  711. "reo2ppe_ring");
  712. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  713. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  714. goto fail;
  715. }
  716. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  717. be_soc->ppe2tcl_ring.alloc_size,
  718. soc->ctrl_psoc,
  719. WLAN_MD_DP_SRNG_PPE2TCL,
  720. "ppe2tcl_ring");
  721. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  722. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  723. goto fail;
  724. }
  725. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  726. be_soc->ppe_release_ring.alloc_size,
  727. soc->ctrl_psoc,
  728. WLAN_MD_DP_SRNG_PPE_RELEASE,
  729. "ppe_release_ring");
  730. return QDF_STATUS_SUCCESS;
  731. fail:
  732. dp_soc_ppe_srng_deinit(soc);
  733. return QDF_STATUS_E_NOMEM;
  734. }
  735. #else
  736. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  737. {
  738. }
  739. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  740. {
  741. }
  742. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  743. {
  744. return QDF_STATUS_SUCCESS;
  745. }
  746. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  747. {
  748. return QDF_STATUS_SUCCESS;
  749. }
  750. #endif
  751. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  752. {
  753. dp_soc_ppe_srng_deinit(soc);
  754. }
  755. static void dp_soc_srng_free_be(struct dp_soc *soc)
  756. {
  757. dp_soc_ppe_srng_free(soc);
  758. }
  759. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  760. {
  761. return dp_soc_ppe_srng_alloc(soc);
  762. }
  763. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  764. {
  765. return dp_soc_ppe_srng_init(soc);
  766. }
  767. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  768. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  769. uint8_t tx_ring_id,
  770. uint8_t bm_id)
  771. {
  772. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  773. soc->tcl_data_ring[tx_ring_id].hal_srng,
  774. bm_id);
  775. }
  776. #else
  777. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  778. uint8_t tx_ring_id,
  779. uint8_t bm_id)
  780. {
  781. }
  782. #endif
  783. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  784. {
  785. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  786. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  787. arch_ops->dp_rx_process = dp_rx_process_be;
  788. arch_ops->tx_comp_get_params_from_hal_desc =
  789. dp_tx_comp_get_params_from_hal_desc_be;
  790. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  791. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  792. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  793. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  794. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  795. dp_wbm_get_rx_desc_from_hal_desc_be;
  796. #endif
  797. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  798. arch_ops->dp_rx_desc_cookie_2_va =
  799. dp_rx_desc_cookie_2_va_be;
  800. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  801. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  802. arch_ops->txrx_soc_init = dp_soc_init_be;
  803. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  804. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  805. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  806. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  807. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  808. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  809. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  810. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  811. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  812. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  813. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  814. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  815. dp_init_near_full_arch_ops_be(arch_ops);
  816. }