dp_be.c 40 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #include <hal_be_api.h>
  26. /* Generic AST entry aging timer value */
  27. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  28. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  29. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  30. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  31. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  32. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  33. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  34. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  35. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  36. };
  37. #else
  38. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  39. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  40. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  41. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  42. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  43. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  44. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  45. };
  46. #endif
  47. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  48. {
  49. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  50. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  51. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  52. /* this is used only when dmac mode is enabled */
  53. soc->num_rx_refill_buf_rings = 1;
  54. }
  55. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  56. {
  57. switch (context_type) {
  58. case DP_CONTEXT_TYPE_SOC:
  59. return sizeof(struct dp_soc_be);
  60. case DP_CONTEXT_TYPE_PDEV:
  61. return sizeof(struct dp_pdev_be);
  62. case DP_CONTEXT_TYPE_VDEV:
  63. return sizeof(struct dp_vdev_be);
  64. case DP_CONTEXT_TYPE_PEER:
  65. return sizeof(struct dp_peer_be);
  66. default:
  67. return 0;
  68. }
  69. }
  70. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  71. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  72. /**
  73. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  74. per wbm2sw ring
  75. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  76. *
  77. * Return: None
  78. */
  79. static inline
  80. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  81. {
  82. cc_cfg->wbm2sw6_cc_en = 1;
  83. cc_cfg->wbm2sw5_cc_en = 1;
  84. cc_cfg->wbm2sw4_cc_en = 1;
  85. cc_cfg->wbm2sw3_cc_en = 1;
  86. cc_cfg->wbm2sw2_cc_en = 1;
  87. /* disable wbm2sw1 hw cc as it's for FW */
  88. cc_cfg->wbm2sw1_cc_en = 0;
  89. cc_cfg->wbm2sw0_cc_en = 1;
  90. cc_cfg->wbm2fw_cc_en = 0;
  91. }
  92. #else
  93. static inline
  94. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  95. {
  96. cc_cfg->wbm2sw6_cc_en = 1;
  97. cc_cfg->wbm2sw5_cc_en = 1;
  98. cc_cfg->wbm2sw4_cc_en = 1;
  99. cc_cfg->wbm2sw3_cc_en = 1;
  100. cc_cfg->wbm2sw2_cc_en = 1;
  101. cc_cfg->wbm2sw1_cc_en = 1;
  102. cc_cfg->wbm2sw0_cc_en = 1;
  103. cc_cfg->wbm2fw_cc_en = 0;
  104. }
  105. #endif
  106. /**
  107. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  108. conversion register
  109. * @soc: SOC handle
  110. * @is_4k_align: page address 4k alignd
  111. *
  112. * Return: None
  113. */
  114. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  115. bool is_4k_align)
  116. {
  117. struct hal_hw_cc_config cc_cfg = { 0 };
  118. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  119. if (soc->cdp_soc.ol_ops->get_con_mode &&
  120. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  121. return;
  122. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  123. dp_info("INI skip HW CC register setting");
  124. return;
  125. }
  126. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  127. cc_cfg.cc_global_en = true;
  128. cc_cfg.page_4k_align = is_4k_align;
  129. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  130. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  131. /* 36th bit should be 1 then HW know this is CMEM address */
  132. cc_cfg.lut_base_addr_39_32 = 0x10;
  133. cc_cfg.error_path_cookie_conv_en = true;
  134. cc_cfg.release_path_cookie_conv_en = true;
  135. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  136. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  137. }
  138. /**
  139. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  140. * @hal_soc_hdl: HAL SOC handle
  141. * @offset: CMEM address
  142. * @value: value to write
  143. *
  144. * Return: None.
  145. */
  146. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  147. uint32_t offset,
  148. uint32_t value)
  149. {
  150. hal_cmem_write(hal_soc_hdl, offset, value);
  151. }
  152. /**
  153. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  154. HW cookie conversion
  155. * @soc: SOC handle
  156. * @cc_ctx: cookie conversion context pointer
  157. *
  158. * Return: 0 in case of success, else error value
  159. */
  160. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  161. {
  162. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  163. dp_info("cmem base 0x%llx, size 0x%llx",
  164. soc->cmem_base, soc->cmem_size);
  165. /* get CMEM for cookie conversion */
  166. if (soc->cmem_size < DP_CC_PPT_MEM_SIZE) {
  167. dp_err("cmem_size %llu bytes < 4K", soc->cmem_size);
  168. return QDF_STATUS_E_RESOURCES;
  169. }
  170. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  171. DP_CC_MEM_OFFSET_IN_CMEM);
  172. return QDF_STATUS_SUCCESS;
  173. }
  174. #else
  175. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  176. bool is_4k_align) {}
  177. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  178. uint32_t offset,
  179. uint32_t value)
  180. { }
  181. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  182. {
  183. return QDF_STATUS_SUCCESS;
  184. }
  185. #endif
  186. QDF_STATUS
  187. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  188. struct dp_hw_cookie_conversion_t *cc_ctx,
  189. uint32_t num_descs,
  190. enum dp_desc_type desc_type,
  191. uint8_t desc_pool_id)
  192. {
  193. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  194. uint32_t num_spt_pages, i = 0;
  195. struct dp_spt_page_desc *spt_desc;
  196. struct qdf_mem_dma_page_t *dma_page;
  197. uint8_t chip_id;
  198. /* estimate how many SPT DDR pages needed */
  199. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  200. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  201. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  202. dp_info("num_spt_pages needed %d", num_spt_pages);
  203. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  204. &cc_ctx->page_pool, qdf_page_size,
  205. num_spt_pages, 0, false);
  206. if (!cc_ctx->page_pool.dma_pages) {
  207. dp_err("spt ddr pages allocation failed");
  208. return QDF_STATUS_E_RESOURCES;
  209. }
  210. cc_ctx->page_desc_base = qdf_mem_malloc(
  211. num_spt_pages * sizeof(struct dp_spt_page_desc));
  212. if (!cc_ctx->page_desc_base) {
  213. dp_err("spt page descs allocation failed");
  214. goto fail_0;
  215. }
  216. chip_id = dp_mlo_get_chip_id(soc);
  217. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  218. desc_type);
  219. /* initial page desc */
  220. spt_desc = cc_ctx->page_desc_base;
  221. dma_page = cc_ctx->page_pool.dma_pages;
  222. while (i < num_spt_pages) {
  223. /* check if page address 4K aligned */
  224. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  225. dp_err("non-4k aligned pages addr %pK",
  226. (void *)dma_page[i].page_p_addr);
  227. goto fail_1;
  228. }
  229. spt_desc[i].page_v_addr =
  230. dma_page[i].page_v_addr_start;
  231. spt_desc[i].page_p_addr =
  232. dma_page[i].page_p_addr;
  233. i++;
  234. }
  235. cc_ctx->total_page_num = num_spt_pages;
  236. qdf_spinlock_create(&cc_ctx->cc_lock);
  237. return QDF_STATUS_SUCCESS;
  238. fail_1:
  239. qdf_mem_free(cc_ctx->page_desc_base);
  240. fail_0:
  241. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  242. &cc_ctx->page_pool, 0, false);
  243. return QDF_STATUS_E_FAILURE;
  244. }
  245. QDF_STATUS
  246. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  247. struct dp_hw_cookie_conversion_t *cc_ctx)
  248. {
  249. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  250. qdf_mem_free(cc_ctx->page_desc_base);
  251. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  252. &cc_ctx->page_pool, 0, false);
  253. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  254. return QDF_STATUS_SUCCESS;
  255. }
  256. QDF_STATUS
  257. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  258. struct dp_hw_cookie_conversion_t *cc_ctx)
  259. {
  260. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  261. uint32_t i = 0;
  262. struct dp_spt_page_desc *spt_desc;
  263. uint32_t ppt_index;
  264. uint32_t ppt_id_start;
  265. if (!cc_ctx->total_page_num) {
  266. dp_err("total page num is 0");
  267. return QDF_STATUS_E_INVAL;
  268. }
  269. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  270. spt_desc = cc_ctx->page_desc_base;
  271. while (i < cc_ctx->total_page_num) {
  272. /* write page PA to CMEM */
  273. dp_hw_cc_cmem_write(soc->hal_soc,
  274. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  275. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  276. (spt_desc[i].page_p_addr >>
  277. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  278. ppt_index = ppt_id_start + i;
  279. spt_desc[i].ppt_index = ppt_index;
  280. be_soc->page_desc_base[ppt_index].page_v_addr =
  281. spt_desc[i].page_v_addr;
  282. i++;
  283. }
  284. return QDF_STATUS_SUCCESS;
  285. }
  286. QDF_STATUS
  287. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  288. struct dp_hw_cookie_conversion_t *cc_ctx)
  289. {
  290. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  291. uint32_t ppt_index;
  292. struct dp_spt_page_desc *spt_desc;
  293. int i = 0;
  294. spt_desc = cc_ctx->page_desc_base;
  295. while (i < cc_ctx->total_page_num) {
  296. /* reset PA in CMEM to NULL */
  297. dp_hw_cc_cmem_write(soc->hal_soc,
  298. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  299. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  300. 0);
  301. ppt_index = spt_desc[i].ppt_index;
  302. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  303. i++;
  304. }
  305. return QDF_STATUS_SUCCESS;
  306. }
  307. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  308. {
  309. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  310. int i = 0;
  311. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  312. dp_hw_cookie_conversion_detach(be_soc,
  313. &be_soc->tx_cc_ctx[i]);
  314. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  315. dp_hw_cookie_conversion_detach(be_soc,
  316. &be_soc->rx_cc_ctx[i]);
  317. qdf_mem_free(be_soc->page_desc_base);
  318. be_soc->page_desc_base = NULL;
  319. return QDF_STATUS_SUCCESS;
  320. }
  321. #ifdef WLAN_MLO_MULTI_CHIP
  322. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  323. {
  324. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  325. qdf_mem_set(be_vdev->partner_vdev_list,
  326. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  327. CDP_INVALID_VDEV_ID);
  328. }
  329. #else
  330. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  331. {
  332. }
  333. #endif
  334. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  335. struct cdp_soc_attach_params *params)
  336. {
  337. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  338. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  339. uint32_t max_tx_rx_desc_num, num_spt_pages;
  340. uint32_t num_entries;
  341. int i = 0;
  342. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  343. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  344. /* estimate how many SPT DDR pages needed */
  345. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  346. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  347. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  348. be_soc->page_desc_base = qdf_mem_malloc(
  349. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  350. if (!be_soc->page_desc_base) {
  351. dp_err("spt page descs allocation failed");
  352. return QDF_STATUS_E_NOMEM;
  353. }
  354. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  355. qdf_status = dp_hw_cc_cmem_addr_init(soc);
  356. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  357. goto fail;
  358. dp_soc_mlo_fill_params(soc, params);
  359. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  360. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  361. qdf_status =
  362. dp_hw_cookie_conversion_attach(be_soc,
  363. &be_soc->tx_cc_ctx[i],
  364. num_entries,
  365. DP_TX_DESC_TYPE, i);
  366. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  367. goto fail;
  368. }
  369. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  370. num_entries =
  371. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  372. qdf_status =
  373. dp_hw_cookie_conversion_attach(be_soc,
  374. &be_soc->rx_cc_ctx[i],
  375. num_entries,
  376. DP_RX_DESC_BUF_TYPE, i);
  377. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  378. goto fail;
  379. }
  380. return qdf_status;
  381. fail:
  382. dp_soc_detach_be(soc);
  383. return qdf_status;
  384. }
  385. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  386. {
  387. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  388. int i = 0;
  389. dp_tx_deinit_bank_profiles(be_soc);
  390. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  391. dp_hw_cookie_conversion_deinit(be_soc,
  392. &be_soc->tx_cc_ctx[i]);
  393. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  394. dp_hw_cookie_conversion_deinit(be_soc,
  395. &be_soc->rx_cc_ctx[i]);
  396. return QDF_STATUS_SUCCESS;
  397. }
  398. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  399. {
  400. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  401. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  402. int i = 0;
  403. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  404. qdf_status =
  405. dp_hw_cookie_conversion_init(be_soc,
  406. &be_soc->tx_cc_ctx[i]);
  407. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  408. goto fail;
  409. }
  410. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  411. qdf_status =
  412. dp_hw_cookie_conversion_init(be_soc,
  413. &be_soc->rx_cc_ctx[i]);
  414. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  415. goto fail;
  416. }
  417. /* route vdev_id mismatch notification via FW completion */
  418. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  419. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  420. qdf_status = dp_tx_init_bank_profiles(be_soc);
  421. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  422. goto fail;
  423. /* write WBM/REO cookie conversion CFG register */
  424. dp_cc_reg_cfg_init(soc, true);
  425. return qdf_status;
  426. fail:
  427. dp_soc_deinit_be(soc);
  428. return qdf_status;
  429. }
  430. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  431. struct cdp_pdev_attach_params *params)
  432. {
  433. dp_pdev_mlo_fill_params(pdev, params);
  434. return QDF_STATUS_SUCCESS;
  435. }
  436. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  437. {
  438. return QDF_STATUS_SUCCESS;
  439. }
  440. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  441. {
  442. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  443. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  444. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  445. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  446. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  447. QDF_BUG(0);
  448. return QDF_STATUS_E_FAULT;
  449. }
  450. if (vdev->opmode == wlan_op_mode_sta) {
  451. if (soc->cdp_soc.ol_ops->set_mec_timer)
  452. soc->cdp_soc.ol_ops->set_mec_timer(
  453. soc->ctrl_psoc,
  454. vdev->vdev_id,
  455. DP_AST_AGING_TIMER_DEFAULT_MS);
  456. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  457. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  458. }
  459. dp_mlo_init_ptnr_list(vdev);
  460. return QDF_STATUS_SUCCESS;
  461. }
  462. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  463. {
  464. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  465. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  466. dp_tx_put_bank_profile(be_soc, be_vdev);
  467. dp_clr_mlo_ptnr_list(soc, vdev);
  468. return QDF_STATUS_SUCCESS;
  469. }
  470. qdf_size_t dp_get_soc_context_size_be(void)
  471. {
  472. return sizeof(struct dp_soc_be);
  473. }
  474. /**
  475. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  476. * @soc: Common DP soc handle
  477. *
  478. * Return: QDF_STATUS
  479. */
  480. static QDF_STATUS
  481. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  482. {
  483. int i;
  484. int mac_id;
  485. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  486. struct dp_srng *rx_mac_srng;
  487. QDF_STATUS status = QDF_STATUS_SUCCESS;
  488. /*
  489. * In Beryllium chipset msdu_start, mpdu_end
  490. * and rx_attn are part of msdu_end/mpdu_start
  491. */
  492. htt_tlv_filter.msdu_start = 0;
  493. htt_tlv_filter.mpdu_end = 0;
  494. htt_tlv_filter.attention = 0;
  495. htt_tlv_filter.mpdu_start = 1;
  496. htt_tlv_filter.msdu_end = 1;
  497. htt_tlv_filter.packet = 1;
  498. htt_tlv_filter.packet_header = 1;
  499. htt_tlv_filter.ppdu_start = 0;
  500. htt_tlv_filter.ppdu_end = 0;
  501. htt_tlv_filter.ppdu_end_user_stats = 0;
  502. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  503. htt_tlv_filter.ppdu_end_status_done = 0;
  504. htt_tlv_filter.enable_fp = 1;
  505. htt_tlv_filter.enable_md = 0;
  506. htt_tlv_filter.enable_md = 0;
  507. htt_tlv_filter.enable_mo = 0;
  508. htt_tlv_filter.fp_mgmt_filter = 0;
  509. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  510. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  511. FILTER_DATA_MCAST |
  512. FILTER_DATA_DATA);
  513. htt_tlv_filter.mo_mgmt_filter = 0;
  514. htt_tlv_filter.mo_ctrl_filter = 0;
  515. htt_tlv_filter.mo_data_filter = 0;
  516. htt_tlv_filter.md_data_filter = 0;
  517. htt_tlv_filter.offset_valid = true;
  518. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  519. htt_tlv_filter.rx_mpdu_end_offset = 0;
  520. htt_tlv_filter.rx_msdu_start_offset = 0;
  521. htt_tlv_filter.rx_attn_offset = 0;
  522. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  523. htt_tlv_filter.rx_header_offset =
  524. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  525. htt_tlv_filter.rx_mpdu_start_offset =
  526. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  527. htt_tlv_filter.rx_msdu_end_offset =
  528. hal_rx_msdu_end_offset_get(soc->hal_soc);
  529. dp_info("TLV subscription\n"
  530. "msdu_start %d, mpdu_end %d, attention %d"
  531. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  532. "TLV offsets\n"
  533. "msdu_start %d, mpdu_end %d, attention %d"
  534. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  535. htt_tlv_filter.msdu_start,
  536. htt_tlv_filter.mpdu_end,
  537. htt_tlv_filter.attention,
  538. htt_tlv_filter.mpdu_start,
  539. htt_tlv_filter.msdu_end,
  540. htt_tlv_filter.packet_header,
  541. htt_tlv_filter.packet,
  542. htt_tlv_filter.rx_msdu_start_offset,
  543. htt_tlv_filter.rx_mpdu_end_offset,
  544. htt_tlv_filter.rx_attn_offset,
  545. htt_tlv_filter.rx_mpdu_start_offset,
  546. htt_tlv_filter.rx_msdu_end_offset,
  547. htt_tlv_filter.rx_header_offset,
  548. htt_tlv_filter.rx_packet_offset);
  549. for (i = 0; i < MAX_PDEV_CNT; i++) {
  550. struct dp_pdev *pdev = soc->pdev_list[i];
  551. if (!pdev)
  552. continue;
  553. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  554. int mac_for_pdev =
  555. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  556. /*
  557. * Obtain lmac id from pdev to access the LMAC ring
  558. * in soc context
  559. */
  560. int lmac_id =
  561. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  562. pdev->pdev_id);
  563. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  564. if (!rx_mac_srng->hal_srng)
  565. continue;
  566. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  567. rx_mac_srng->hal_srng,
  568. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  569. &htt_tlv_filter);
  570. }
  571. }
  572. return status;
  573. }
  574. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  575. /**
  576. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  577. * near-full IRQs.
  578. * @soc: Datapath SoC handle
  579. * @int_ctx: Interrupt context
  580. * @dp_budget: Budget of the work that can be done in the bottom half
  581. *
  582. * Return: work done in the handler
  583. */
  584. static uint32_t
  585. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  586. uint32_t dp_budget)
  587. {
  588. int ring = 0;
  589. int budget = dp_budget;
  590. uint32_t work_done = 0;
  591. uint32_t remaining_quota = dp_budget;
  592. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  593. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  594. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  595. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  596. int rx_near_full_mask = rx_near_full_grp_1_mask |
  597. rx_near_full_grp_2_mask;
  598. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  599. rx_near_full_mask,
  600. tx_ring_near_full_mask);
  601. if (rx_near_full_mask) {
  602. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  603. if (!(rx_near_full_mask & (1 << ring)))
  604. continue;
  605. work_done = dp_rx_nf_process(int_ctx,
  606. soc->reo_dest_ring[ring].hal_srng,
  607. ring, remaining_quota);
  608. if (work_done) {
  609. intr_stats->num_rx_ring_near_full_masks[ring]++;
  610. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  611. rx_near_full_mask, ring,
  612. work_done,
  613. budget);
  614. budget -= work_done;
  615. if (budget <= 0)
  616. goto budget_done;
  617. remaining_quota = budget;
  618. }
  619. }
  620. }
  621. if (tx_ring_near_full_mask) {
  622. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  623. if (!(tx_ring_near_full_mask & (1 << ring)))
  624. continue;
  625. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  626. soc->tx_comp_ring[ring].hal_srng,
  627. ring, remaining_quota);
  628. if (work_done) {
  629. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  630. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  631. tx_ring_near_full_mask, ring,
  632. work_done, budget);
  633. budget -= work_done;
  634. if (budget <= 0)
  635. break;
  636. remaining_quota = budget;
  637. }
  638. }
  639. }
  640. intr_stats->num_near_full_masks++;
  641. budget_done:
  642. return dp_budget - budget;
  643. }
  644. /**
  645. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  646. * state and set the reap_limit appropriately
  647. * as per the near full state
  648. * @soc: Datapath soc handle
  649. * @dp_srng: Datapath handle for SRNG
  650. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  651. * the srng near-full state
  652. *
  653. * Return: 1, if the srng is in near-full state
  654. * 0, if the srng is not in near-full state
  655. */
  656. static int
  657. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  658. struct dp_srng *dp_srng,
  659. int *max_reap_limit)
  660. {
  661. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  662. }
  663. /**
  664. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  665. * near full IRQ handling operations.
  666. * @arch_ops: arch ops handle
  667. *
  668. * Return: none
  669. */
  670. static inline void
  671. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  672. {
  673. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  674. arch_ops->dp_srng_test_and_update_nf_params =
  675. dp_srng_test_and_update_nf_params_be;
  676. }
  677. #else
  678. static inline void
  679. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  680. {
  681. }
  682. #endif
  683. #ifdef WLAN_SUPPORT_PPEDS
  684. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  685. {
  686. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  687. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  688. soc_cfg_ctx = soc->wlan_cfg_ctx;
  689. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  690. return;
  691. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  692. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  693. be_soc->ppe_release_ring.alloc_size,
  694. soc->ctrl_psoc,
  695. WLAN_MD_DP_SRNG_PPE_RELEASE,
  696. "ppe_release_ring");
  697. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  698. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  699. be_soc->ppe2tcl_ring.alloc_size,
  700. soc->ctrl_psoc,
  701. WLAN_MD_DP_SRNG_PPE2TCL,
  702. "ppe2tcl_ring");
  703. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  704. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  705. be_soc->reo2ppe_ring.alloc_size,
  706. soc->ctrl_psoc,
  707. WLAN_MD_DP_SRNG_REO2PPE,
  708. "reo2ppe_ring");
  709. }
  710. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  711. {
  712. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  713. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  714. soc_cfg_ctx = soc->wlan_cfg_ctx;
  715. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  716. return;
  717. dp_srng_free(soc, &be_soc->ppe_release_ring);
  718. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  719. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  720. }
  721. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  722. {
  723. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  724. uint32_t entries;
  725. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  726. soc_cfg_ctx = soc->wlan_cfg_ctx;
  727. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  728. return QDF_STATUS_SUCCESS;
  729. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  730. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  731. entries, 0)) {
  732. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  733. goto fail;
  734. }
  735. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  736. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  737. entries, 0)) {
  738. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  739. goto fail;
  740. }
  741. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  742. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  743. entries, 0)) {
  744. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  745. goto fail;
  746. }
  747. return QDF_STATUS_SUCCESS;
  748. fail:
  749. dp_soc_ppe_srng_free(soc);
  750. return QDF_STATUS_E_NOMEM;
  751. }
  752. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  753. {
  754. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  755. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  756. soc_cfg_ctx = soc->wlan_cfg_ctx;
  757. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  758. return QDF_STATUS_SUCCESS;
  759. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  760. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  761. goto fail;
  762. }
  763. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  764. be_soc->reo2ppe_ring.alloc_size,
  765. soc->ctrl_psoc,
  766. WLAN_MD_DP_SRNG_REO2PPE,
  767. "reo2ppe_ring");
  768. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  769. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  770. goto fail;
  771. }
  772. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  773. be_soc->ppe2tcl_ring.alloc_size,
  774. soc->ctrl_psoc,
  775. WLAN_MD_DP_SRNG_PPE2TCL,
  776. "ppe2tcl_ring");
  777. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  778. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  779. goto fail;
  780. }
  781. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  782. be_soc->ppe_release_ring.alloc_size,
  783. soc->ctrl_psoc,
  784. WLAN_MD_DP_SRNG_PPE_RELEASE,
  785. "ppe_release_ring");
  786. return QDF_STATUS_SUCCESS;
  787. fail:
  788. dp_soc_ppe_srng_deinit(soc);
  789. return QDF_STATUS_E_NOMEM;
  790. }
  791. #else
  792. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  793. {
  794. }
  795. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  796. {
  797. }
  798. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  799. {
  800. return QDF_STATUS_SUCCESS;
  801. }
  802. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  803. {
  804. return QDF_STATUS_SUCCESS;
  805. }
  806. #endif
  807. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  808. {
  809. uint32_t i;
  810. dp_soc_ppe_srng_deinit(soc);
  811. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  812. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  813. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  814. RXDMA_BUF, 0);
  815. }
  816. }
  817. }
  818. static void dp_soc_srng_free_be(struct dp_soc *soc)
  819. {
  820. uint32_t i;
  821. dp_soc_ppe_srng_free(soc);
  822. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  823. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  824. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  825. }
  826. }
  827. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  828. {
  829. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  830. uint32_t ring_size;
  831. uint32_t i;
  832. soc_cfg_ctx = soc->wlan_cfg_ctx;
  833. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  834. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  835. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  836. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  837. RXDMA_BUF, ring_size, 0)) {
  838. dp_err("%pK: dp_srng_alloc failed refill ring",
  839. soc);
  840. goto fail;
  841. }
  842. }
  843. }
  844. if (dp_soc_ppe_srng_alloc(soc)) {
  845. dp_err("%pK: ppe rings alloc failed",
  846. soc);
  847. goto fail;
  848. }
  849. return QDF_STATUS_SUCCESS;
  850. fail:
  851. dp_soc_srng_free_be(soc);
  852. return QDF_STATUS_E_NOMEM;
  853. }
  854. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  855. {
  856. int i = 0;
  857. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  858. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  859. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  860. RXDMA_BUF, 0, 0)) {
  861. dp_err("%pK: dp_srng_init failed refill ring",
  862. soc);
  863. goto fail;
  864. }
  865. }
  866. }
  867. if (dp_soc_ppe_srng_init(soc)) {
  868. dp_err("%pK: ppe rings init failed",
  869. soc);
  870. goto fail;
  871. }
  872. return QDF_STATUS_SUCCESS;
  873. fail:
  874. dp_soc_srng_deinit_be(soc);
  875. return QDF_STATUS_E_NOMEM;
  876. }
  877. #ifdef WLAN_FEATURE_11BE_MLO
  878. static inline unsigned
  879. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  880. union dp_align_mac_addr *mac_addr)
  881. {
  882. uint32_t index;
  883. index =
  884. mac_addr->align2.bytes_ab ^
  885. mac_addr->align2.bytes_cd ^
  886. mac_addr->align2.bytes_ef;
  887. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  888. index &= mld_hash_obj->mld_peer_hash.mask;
  889. return index;
  890. }
  891. QDF_STATUS
  892. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  893. int hash_elems)
  894. {
  895. int i, log2;
  896. if (!mld_hash_obj)
  897. return QDF_STATUS_E_FAILURE;
  898. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  899. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  900. log2 = dp_log2_ceil(hash_elems);
  901. hash_elems = 1 << log2;
  902. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  903. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  904. /* allocate an array of TAILQ peer object lists */
  905. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  906. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  907. if (!mld_hash_obj->mld_peer_hash.bins)
  908. return QDF_STATUS_E_NOMEM;
  909. for (i = 0; i < hash_elems; i++)
  910. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  911. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  912. return QDF_STATUS_SUCCESS;
  913. }
  914. void
  915. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  916. {
  917. if (!mld_hash_obj)
  918. return;
  919. if (mld_hash_obj->mld_peer_hash.bins) {
  920. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  921. mld_hash_obj->mld_peer_hash.bins = NULL;
  922. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  923. }
  924. }
  925. #ifdef WLAN_MLO_MULTI_CHIP
  926. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  927. {
  928. /* In case of MULTI chip MLO peer hash table when MLO global object
  929. * is created, avoid from SOC attach path
  930. */
  931. return QDF_STATUS_SUCCESS;
  932. }
  933. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  934. {
  935. }
  936. #else
  937. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  938. {
  939. dp_mld_peer_hash_obj_t mld_hash_obj;
  940. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  941. if (!mld_hash_obj)
  942. return QDF_STATUS_E_FAILURE;
  943. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  944. }
  945. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  946. {
  947. dp_mld_peer_hash_obj_t mld_hash_obj;
  948. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  949. if (!mld_hash_obj)
  950. return;
  951. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  952. }
  953. #endif
  954. static struct dp_peer *
  955. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  956. uint8_t *peer_mac_addr,
  957. int mac_addr_is_aligned,
  958. enum dp_mod_id mod_id)
  959. {
  960. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  961. uint32_t index;
  962. struct dp_peer *peer;
  963. dp_mld_peer_hash_obj_t mld_hash_obj;
  964. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  965. if (!mld_hash_obj)
  966. return NULL;
  967. if (!mld_hash_obj->mld_peer_hash.bins)
  968. return NULL;
  969. if (mac_addr_is_aligned) {
  970. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  971. } else {
  972. qdf_mem_copy(
  973. &local_mac_addr_aligned.raw[0],
  974. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  975. mac_addr = &local_mac_addr_aligned;
  976. }
  977. /* search mld peer table if no link peer for given mac address */
  978. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  979. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  980. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  981. hash_list_elem) {
  982. /* do not check vdev ID for MLD peer */
  983. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  984. /* take peer reference before returning */
  985. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  986. QDF_STATUS_SUCCESS)
  987. peer = NULL;
  988. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  989. return peer;
  990. }
  991. }
  992. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  993. return NULL; /* failure */
  994. }
  995. static void
  996. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  997. {
  998. uint32_t index;
  999. struct dp_peer *tmppeer = NULL;
  1000. int found = 0;
  1001. dp_mld_peer_hash_obj_t mld_hash_obj;
  1002. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1003. if (!mld_hash_obj)
  1004. return;
  1005. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1006. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1007. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1008. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1009. hash_list_elem) {
  1010. if (tmppeer == peer) {
  1011. found = 1;
  1012. break;
  1013. }
  1014. }
  1015. QDF_ASSERT(found);
  1016. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1017. hash_list_elem);
  1018. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1019. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1020. }
  1021. static void
  1022. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1023. {
  1024. uint32_t index;
  1025. dp_mld_peer_hash_obj_t mld_hash_obj;
  1026. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1027. if (!mld_hash_obj)
  1028. return;
  1029. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1030. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1031. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1032. DP_MOD_ID_CONFIG))) {
  1033. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1034. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1035. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1036. return;
  1037. }
  1038. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1039. hash_list_elem);
  1040. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1041. }
  1042. #endif
  1043. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1044. defined(WLAN_MCAST_MLO)
  1045. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1046. struct dp_vdev_be *be_vdev,
  1047. cdp_config_param_type val)
  1048. {
  1049. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1050. }
  1051. #else
  1052. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1053. struct dp_vdev_be *be_vdev,
  1054. cdp_config_param_type val)
  1055. {
  1056. }
  1057. #endif
  1058. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1059. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1060. uint8_t tx_ring_id,
  1061. uint8_t bm_id)
  1062. {
  1063. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1064. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1065. bm_id);
  1066. }
  1067. #else
  1068. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1069. uint8_t tx_ring_id,
  1070. uint8_t bm_id)
  1071. {
  1072. }
  1073. #endif
  1074. #ifdef WLAN_MLO_MULTI_CHIP
  1075. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1076. struct cdp_peer_setup_info *setup_info,
  1077. enum cdp_host_reo_dest_ring *reo_dest,
  1078. bool *hash_based,
  1079. uint8_t *lmac_peer_id_msb)
  1080. {
  1081. struct dp_soc *soc = vdev->pdev->soc;
  1082. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1083. uint8_t default_rx_ring_id;
  1084. uint8_t chip_id;
  1085. if (!be_soc->mlo_enabled)
  1086. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1087. hash_based);
  1088. chip_id = be_soc->mlo_chip_id;
  1089. default_rx_ring_id =
  1090. wlan_cfg_mlo_default_rx_ring_get_by_chip_id(soc->wlan_cfg_ctx,
  1091. chip_id);
  1092. *reo_dest = hal_reo_ring_remap_value_get_be(default_rx_ring_id);
  1093. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1094. *lmac_peer_id_msb =
  1095. wlan_cfg_mlo_lmac_peer_id_msb_get_by_chip_id(soc->wlan_cfg_ctx,
  1096. chip_id);
  1097. }
  1098. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1099. uint32_t *remap0,
  1100. uint32_t *remap1,
  1101. uint32_t *remap2)
  1102. {
  1103. uint8_t rx_ring_mask;
  1104. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1105. if (!be_soc->mlo_enabled)
  1106. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1107. rx_ring_mask =
  1108. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 0);
  1109. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1110. rx_ring_mask =
  1111. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 1);
  1112. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1113. rx_ring_mask =
  1114. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 2);
  1115. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1116. return true;
  1117. }
  1118. #else
  1119. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1120. struct cdp_peer_setup_info *setup_info,
  1121. enum cdp_host_reo_dest_ring *reo_dest,
  1122. bool *hash_based,
  1123. uint8_t *lmac_peer_id_msb)
  1124. {
  1125. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  1126. }
  1127. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1128. uint32_t *remap0,
  1129. uint32_t *remap1,
  1130. uint32_t *remap2)
  1131. {
  1132. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1133. }
  1134. #endif
  1135. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1136. struct dp_vdev *vdev,
  1137. enum cdp_vdev_param_type param,
  1138. cdp_config_param_type val)
  1139. {
  1140. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1141. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1142. switch (param) {
  1143. case CDP_TX_ENCAP_TYPE:
  1144. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1145. dp_tx_update_bank_profile(be_soc, be_vdev);
  1146. break;
  1147. case CDP_ENABLE_CIPHER:
  1148. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1149. dp_tx_update_bank_profile(be_soc, be_vdev);
  1150. break;
  1151. case CDP_SET_MCAST_VDEV:
  1152. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1153. break;
  1154. default:
  1155. dp_warn("invalid param %d", param);
  1156. break;
  1157. }
  1158. return QDF_STATUS_SUCCESS;
  1159. }
  1160. #ifdef WLAN_FEATURE_11BE_MLO
  1161. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1162. static inline void
  1163. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1164. {
  1165. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1166. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1167. /*
  1168. * Double the peers since we use ML indication bit
  1169. * alongwith peer_id to find peers.
  1170. */
  1171. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1172. }
  1173. #else
  1174. static inline void
  1175. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1176. {
  1177. soc->max_peer_id =
  1178. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1179. }
  1180. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1181. #else
  1182. static inline void
  1183. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1184. {
  1185. soc->max_peer_id = soc->max_peers;
  1186. }
  1187. #endif /* WLAN_FEATURE_11BE_MLO */
  1188. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1189. {
  1190. }
  1191. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1192. {
  1193. dp_soc_max_peer_id_set(soc);
  1194. return QDF_STATUS_SUCCESS;
  1195. }
  1196. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1197. {
  1198. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1199. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1200. arch_ops->dp_rx_process = dp_rx_process_be;
  1201. arch_ops->tx_comp_get_params_from_hal_desc =
  1202. dp_tx_comp_get_params_from_hal_desc_be;
  1203. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1204. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1205. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1206. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1207. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1208. dp_wbm_get_rx_desc_from_hal_desc_be;
  1209. #endif
  1210. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1211. arch_ops->dp_rx_desc_cookie_2_va =
  1212. dp_rx_desc_cookie_2_va_be;
  1213. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1214. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1215. arch_ops->txrx_soc_init = dp_soc_init_be;
  1216. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1217. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1218. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1219. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1220. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1221. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1222. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1223. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1224. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1225. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1226. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1227. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1228. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1229. dp_rx_peer_metadata_peer_id_get_be;
  1230. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1231. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1232. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  1233. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  1234. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1235. #ifdef WLAN_FEATURE_11BE_MLO
  1236. #ifdef WLAN_MCAST_MLO
  1237. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1238. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1239. #endif
  1240. arch_ops->mlo_peer_find_hash_detach =
  1241. dp_mlo_peer_find_hash_detach_wrapper;
  1242. arch_ops->mlo_peer_find_hash_attach =
  1243. dp_mlo_peer_find_hash_attach_wrapper;
  1244. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1245. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1246. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1247. #endif
  1248. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1249. dp_init_near_full_arch_ops_be(arch_ops);
  1250. }