dp_be_rx.c 29 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "cdp_txrx_cmn_struct.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_types.h"
  21. #include "dp_rx.h"
  22. #include "dp_be_rx.h"
  23. #include "dp_peer.h"
  24. #include "hal_rx.h"
  25. #include "hal_be_rx.h"
  26. #include "hal_api.h"
  27. #include "hal_be_api.h"
  28. #include "qdf_nbuf.h"
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "dp_internal.h"
  33. #include "dp_ipa.h"
  34. #ifdef FEATURE_WDS
  35. #include "dp_txrx_wds.h"
  36. #endif
  37. #include "dp_hist.h"
  38. #include "dp_rx_buffer_pool.h"
  39. /**
  40. * dp_rx_process_be() - Brain of the Rx processing functionality
  41. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  42. * @int_ctx: per interrupt context
  43. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  44. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  45. * @quota: No. of units (packets) that can be serviced in one shot.
  46. *
  47. * This function implements the core of Rx functionality. This is
  48. * expected to handle only non-error frames.
  49. *
  50. * Return: uint32_t: No. of elements processed
  51. */
  52. uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
  53. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  54. uint32_t quota)
  55. {
  56. hal_ring_desc_t ring_desc;
  57. hal_soc_handle_t hal_soc;
  58. struct dp_rx_desc *rx_desc = NULL;
  59. qdf_nbuf_t nbuf, next;
  60. bool near_full;
  61. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  62. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  63. uint32_t num_pending;
  64. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  65. uint16_t msdu_len = 0;
  66. uint16_t peer_id;
  67. uint8_t vdev_id;
  68. struct dp_peer *peer;
  69. struct dp_vdev *vdev;
  70. uint32_t pkt_len = 0;
  71. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  72. struct hal_rx_msdu_desc_info msdu_desc_info;
  73. enum hal_reo_error_status error;
  74. uint32_t peer_mdata;
  75. uint8_t *rx_tlv_hdr;
  76. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  77. uint8_t mac_id = 0;
  78. struct dp_pdev *rx_pdev;
  79. struct dp_srng *dp_rxdma_srng;
  80. struct rx_desc_pool *rx_desc_pool;
  81. struct dp_soc *soc = int_ctx->soc;
  82. uint8_t core_id = 0;
  83. struct cdp_tid_rx_stats *tid_stats;
  84. qdf_nbuf_t nbuf_head;
  85. qdf_nbuf_t nbuf_tail;
  86. qdf_nbuf_t deliver_list_head;
  87. qdf_nbuf_t deliver_list_tail;
  88. uint32_t num_rx_bufs_reaped = 0;
  89. uint32_t intr_id;
  90. struct hif_opaque_softc *scn;
  91. int32_t tid = 0;
  92. bool is_prev_msdu_last = true;
  93. uint32_t num_entries_avail = 0;
  94. uint32_t rx_ol_pkt_cnt = 0;
  95. uint32_t num_entries = 0;
  96. struct hal_rx_msdu_metadata msdu_metadata;
  97. QDF_STATUS status;
  98. qdf_nbuf_t ebuf_head;
  99. qdf_nbuf_t ebuf_tail;
  100. uint8_t pkt_capture_offload = 0;
  101. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  102. int max_reap_limit, ring_near_full;
  103. DP_HIST_INIT();
  104. qdf_assert_always(soc && hal_ring_hdl);
  105. hal_soc = soc->hal_soc;
  106. qdf_assert_always(hal_soc);
  107. scn = soc->hif_handle;
  108. hif_pm_runtime_mark_dp_rx_busy(scn);
  109. intr_id = int_ctx->dp_intr_id;
  110. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  111. more_data:
  112. /* reset local variables here to be re-used in the function */
  113. nbuf_head = NULL;
  114. nbuf_tail = NULL;
  115. deliver_list_head = NULL;
  116. deliver_list_tail = NULL;
  117. peer = NULL;
  118. vdev = NULL;
  119. num_rx_bufs_reaped = 0;
  120. ebuf_head = NULL;
  121. ebuf_tail = NULL;
  122. ring_near_full = 0;
  123. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  124. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  125. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  126. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  127. qdf_mem_zero(head, sizeof(head));
  128. qdf_mem_zero(tail, sizeof(tail));
  129. ring_near_full = _dp_srng_test_and_update_nf_params(soc, rx_ring,
  130. &max_reap_limit);
  131. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  132. /*
  133. * Need API to convert from hal_ring pointer to
  134. * Ring Type / Ring Id combo
  135. */
  136. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  137. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  138. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  139. goto done;
  140. }
  141. /*
  142. * start reaping the buffers from reo ring and queue
  143. * them in per vdev queue.
  144. * Process the received pkts in a different per vdev loop.
  145. */
  146. while (qdf_likely(quota &&
  147. (ring_desc = hal_srng_dst_peek(hal_soc,
  148. hal_ring_hdl)))) {
  149. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  150. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  151. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  152. soc, hal_ring_hdl, error);
  153. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  154. 1);
  155. /* Don't know how to deal with this -- assert */
  156. qdf_assert(0);
  157. }
  158. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  159. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  160. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  161. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  162. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  163. break;
  164. }
  165. rx_desc = (struct dp_rx_desc *)
  166. hal_rx_get_reo_desc_va(ring_desc);
  167. dp_rx_desc_sw_cc_check(soc, rx_buf_cookie, &rx_desc);
  168. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  169. ring_desc, rx_desc);
  170. if (QDF_IS_STATUS_ERROR(status)) {
  171. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  172. qdf_assert_always(!rx_desc->unmapped);
  173. dp_ipa_reo_ctx_buf_mapping_lock(
  174. soc,
  175. reo_ring_num);
  176. dp_ipa_handle_rx_buf_smmu_mapping(
  177. soc,
  178. rx_desc->nbuf,
  179. RX_DATA_BUFFER_SIZE,
  180. false);
  181. qdf_nbuf_unmap_nbytes_single(
  182. soc->osdev,
  183. rx_desc->nbuf,
  184. QDF_DMA_FROM_DEVICE,
  185. RX_DATA_BUFFER_SIZE);
  186. rx_desc->unmapped = 1;
  187. dp_ipa_reo_ctx_buf_mapping_unlock(
  188. soc,
  189. reo_ring_num);
  190. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  191. rx_desc->pool_id);
  192. dp_rx_add_to_free_desc_list(
  193. &head[rx_desc->pool_id],
  194. &tail[rx_desc->pool_id],
  195. rx_desc);
  196. }
  197. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  198. continue;
  199. }
  200. /*
  201. * this is a unlikely scenario where the host is reaping
  202. * a descriptor which it already reaped just a while ago
  203. * but is yet to replenish it back to HW.
  204. * In this case host will dump the last 128 descriptors
  205. * including the software descriptor rx_desc and assert.
  206. */
  207. if (qdf_unlikely(!rx_desc->in_use)) {
  208. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  209. dp_info_rl("Reaping rx_desc not in use!");
  210. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  211. ring_desc, rx_desc);
  212. /* ignore duplicate RX desc and continue to process */
  213. /* Pop out the descriptor */
  214. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  215. continue;
  216. }
  217. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  218. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  219. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  220. dp_info_rl("Nbuf sanity check failure!");
  221. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  222. ring_desc, rx_desc);
  223. rx_desc->in_err_state = 1;
  224. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  225. continue;
  226. }
  227. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  228. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  229. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  230. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  231. ring_desc, rx_desc);
  232. }
  233. /* Get MPDU DESC info */
  234. hal_rx_mpdu_desc_info_get_be(ring_desc, &mpdu_desc_info);
  235. /* Get MSDU DESC info */
  236. hal_rx_msdu_desc_info_get_be(ring_desc, &msdu_desc_info);
  237. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  238. HAL_MSDU_F_MSDU_CONTINUATION)) {
  239. /* previous msdu has end bit set, so current one is
  240. * the new MPDU
  241. */
  242. if (is_prev_msdu_last) {
  243. /* Get number of entries available in HW ring */
  244. num_entries_avail =
  245. hal_srng_dst_num_valid(hal_soc,
  246. hal_ring_hdl, 1);
  247. /* For new MPDU check if we can read complete
  248. * MPDU by comparing the number of buffers
  249. * available and number of buffers needed to
  250. * reap this MPDU
  251. */
  252. if ((msdu_desc_info.msdu_len /
  253. (RX_DATA_BUFFER_SIZE -
  254. soc->rx_pkt_tlv_size) + 1) >
  255. num_entries_avail) {
  256. DP_STATS_INC(soc,
  257. rx.msdu_scatter_wait_break,
  258. 1);
  259. dp_rx_cookie_reset_invalid_bit(
  260. ring_desc);
  261. break;
  262. }
  263. is_prev_msdu_last = false;
  264. }
  265. }
  266. core_id = smp_processor_id();
  267. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  268. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  269. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  270. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  271. HAL_MPDU_F_RAW_AMPDU))
  272. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  273. if (!is_prev_msdu_last &&
  274. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  275. is_prev_msdu_last = true;
  276. /* Pop out the descriptor*/
  277. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  278. rx_bufs_reaped[rx_desc->pool_id]++;
  279. peer_mdata = mpdu_desc_info.peer_meta_data;
  280. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  281. DP_PEER_METADATA_PEER_ID_GET(peer_mdata);
  282. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  283. DP_PEER_METADATA_VDEV_ID_GET(peer_mdata);
  284. /* to indicate whether this msdu is rx offload */
  285. pkt_capture_offload =
  286. DP_PEER_METADATA_OFFLOAD_GET(peer_mdata);
  287. /*
  288. * save msdu flags first, last and continuation msdu in
  289. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  290. * length to nbuf->cb. This ensures the info required for
  291. * per pkt processing is always in the same cache line.
  292. * This helps in improving throughput for smaller pkt
  293. * sizes.
  294. */
  295. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  296. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  297. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  298. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  299. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  300. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  301. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  302. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  303. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  304. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  305. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  306. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  307. qdf_nbuf_set_tid_val(rx_desc->nbuf,
  308. HAL_RX_REO_QUEUE_NUMBER_GET(ring_desc));
  309. #ifdef CONFIG_LITHIUM
  310. qdf_nbuf_set_rx_reo_dest_ind(
  311. rx_desc->nbuf,
  312. HAL_RX_REO_MSDU_REO_DST_IND_GET(ring_desc));
  313. #endif
  314. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  315. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  316. /*
  317. * move unmap after scattered msdu waiting break logic
  318. * in case double skb unmap happened.
  319. */
  320. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  321. dp_ipa_reo_ctx_buf_mapping_lock(soc, reo_ring_num);
  322. dp_ipa_handle_rx_buf_smmu_mapping(soc, rx_desc->nbuf,
  323. rx_desc_pool->buf_size,
  324. false);
  325. qdf_nbuf_unmap_nbytes_single(soc->osdev, rx_desc->nbuf,
  326. QDF_DMA_FROM_DEVICE,
  327. rx_desc_pool->buf_size);
  328. rx_desc->unmapped = 1;
  329. dp_ipa_reo_ctx_buf_mapping_unlock(soc, reo_ring_num);
  330. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  331. ebuf_tail, rx_desc);
  332. /*
  333. * if continuation bit is set then we have MSDU spread
  334. * across multiple buffers, let us not decrement quota
  335. * till we reap all buffers of that MSDU.
  336. */
  337. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  338. quota -= 1;
  339. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  340. &tail[rx_desc->pool_id], rx_desc);
  341. num_rx_bufs_reaped++;
  342. /*
  343. * only if complete msdu is received for scatter case,
  344. * then allow break.
  345. */
  346. if (is_prev_msdu_last &&
  347. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  348. max_reap_limit))
  349. break;
  350. }
  351. done:
  352. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  353. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  354. /*
  355. * continue with next mac_id if no pkts were reaped
  356. * from that pool
  357. */
  358. if (!rx_bufs_reaped[mac_id])
  359. continue;
  360. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_id];
  361. rx_desc_pool = &soc->rx_desc_buf[mac_id];
  362. dp_rx_buffers_replenish(soc, mac_id, dp_rxdma_srng,
  363. rx_desc_pool, rx_bufs_reaped[mac_id],
  364. &head[mac_id], &tail[mac_id]);
  365. }
  366. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  367. /* Peer can be NULL is case of LFR */
  368. if (qdf_likely(peer))
  369. vdev = NULL;
  370. /*
  371. * BIG loop where each nbuf is dequeued from global queue,
  372. * processed and queued back on a per vdev basis. These nbufs
  373. * are sent to stack as and when we run out of nbufs
  374. * or a new nbuf dequeued from global queue has a different
  375. * vdev when compared to previous nbuf.
  376. */
  377. nbuf = nbuf_head;
  378. while (nbuf) {
  379. next = nbuf->next;
  380. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  381. nbuf = next;
  382. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  383. continue;
  384. }
  385. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  386. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  387. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  388. if (dp_rx_is_list_ready(deliver_list_head, vdev, peer,
  389. peer_id, vdev_id)) {
  390. dp_rx_deliver_to_stack(soc, vdev, peer,
  391. deliver_list_head,
  392. deliver_list_tail);
  393. deliver_list_head = NULL;
  394. deliver_list_tail = NULL;
  395. }
  396. /* Get TID from struct cb->tid_val, save to tid */
  397. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  398. tid = qdf_nbuf_get_tid_val(nbuf);
  399. if (qdf_unlikely(!peer)) {
  400. peer = dp_peer_get_ref_by_id(soc, peer_id,
  401. DP_MOD_ID_RX);
  402. } else if (peer && peer->peer_id != peer_id) {
  403. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  404. peer = dp_peer_get_ref_by_id(soc, peer_id,
  405. DP_MOD_ID_RX);
  406. }
  407. if (peer) {
  408. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  409. qdf_dp_trace_set_track(nbuf, QDF_RX);
  410. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  411. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  412. QDF_NBUF_RX_PKT_DATA_TRACK;
  413. }
  414. rx_bufs_used++;
  415. if (qdf_likely(peer)) {
  416. vdev = peer->vdev;
  417. } else {
  418. nbuf->next = NULL;
  419. dp_rx_deliver_to_pkt_capture_no_peer(
  420. soc, nbuf, pkt_capture_offload);
  421. if (!pkt_capture_offload)
  422. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  423. nbuf = next;
  424. continue;
  425. }
  426. if (qdf_unlikely(!vdev)) {
  427. qdf_nbuf_free(nbuf);
  428. nbuf = next;
  429. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  430. continue;
  431. }
  432. /* when hlos tid override is enabled, save tid in
  433. * skb->priority
  434. */
  435. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  436. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  437. qdf_nbuf_set_priority(nbuf, tid);
  438. rx_pdev = vdev->pdev;
  439. DP_RX_TID_SAVE(nbuf, tid);
  440. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  441. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  442. soc->wlan_cfg_ctx)))
  443. qdf_nbuf_set_timestamp(nbuf);
  444. tid_stats =
  445. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  446. /*
  447. * Check if DMA completed -- msdu_done is the last bit
  448. * to be written
  449. */
  450. if (qdf_unlikely(!qdf_nbuf_is_rx_chfrag_cont(nbuf) &&
  451. !hal_rx_attn_msdu_done_get(hal_soc,
  452. rx_tlv_hdr))) {
  453. dp_err("MSDU DONE failure");
  454. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  455. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  456. QDF_TRACE_LEVEL_INFO);
  457. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  458. qdf_nbuf_free(nbuf);
  459. qdf_assert(0);
  460. nbuf = next;
  461. continue;
  462. }
  463. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  464. /*
  465. * First IF condition:
  466. * 802.11 Fragmented pkts are reinjected to REO
  467. * HW block as SG pkts and for these pkts we only
  468. * need to pull the RX TLVS header length.
  469. * Second IF condition:
  470. * The below condition happens when an MSDU is spread
  471. * across multiple buffers. This can happen in two cases
  472. * 1. The nbuf size is smaller then the received msdu.
  473. * ex: we have set the nbuf size to 2048 during
  474. * nbuf_alloc. but we received an msdu which is
  475. * 2304 bytes in size then this msdu is spread
  476. * across 2 nbufs.
  477. *
  478. * 2. AMSDUs when RAW mode is enabled.
  479. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  480. * across 1st nbuf and 2nd nbuf and last MSDU is
  481. * spread across 2nd nbuf and 3rd nbuf.
  482. *
  483. * for these scenarios let us create a skb frag_list and
  484. * append these buffers till the last MSDU of the AMSDU
  485. * Third condition:
  486. * This is the most likely case, we receive 802.3 pkts
  487. * decapsulated by HW, here we need to set the pkt length.
  488. */
  489. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  490. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  491. bool is_mcbc, is_sa_vld, is_da_vld;
  492. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  493. rx_tlv_hdr);
  494. is_sa_vld =
  495. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  496. rx_tlv_hdr);
  497. is_da_vld =
  498. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  499. rx_tlv_hdr);
  500. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  501. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  502. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  503. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  504. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  505. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  506. nbuf = dp_rx_sg_create(soc, nbuf);
  507. next = nbuf->next;
  508. if (qdf_nbuf_is_raw_frame(nbuf)) {
  509. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  510. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  511. } else {
  512. qdf_nbuf_free(nbuf);
  513. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  514. dp_info_rl("scatter msdu len %d, dropped",
  515. msdu_len);
  516. nbuf = next;
  517. continue;
  518. }
  519. } else {
  520. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  521. pkt_len = msdu_len +
  522. msdu_metadata.l3_hdr_pad +
  523. soc->rx_pkt_tlv_size;
  524. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  525. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  526. }
  527. /*
  528. * process frame for mulitpass phrase processing
  529. */
  530. if (qdf_unlikely(vdev->multipass_en)) {
  531. if (dp_rx_multipass_process(peer, nbuf, tid) == false) {
  532. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  533. qdf_nbuf_free(nbuf);
  534. nbuf = next;
  535. continue;
  536. }
  537. }
  538. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, peer)) {
  539. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  540. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  541. /* Drop & free packet */
  542. qdf_nbuf_free(nbuf);
  543. /* Statistics */
  544. nbuf = next;
  545. continue;
  546. }
  547. if (qdf_unlikely(peer && (peer->nawds_enabled) &&
  548. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  549. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  550. rx_tlv_hdr) ==
  551. false))) {
  552. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  553. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  554. qdf_nbuf_free(nbuf);
  555. nbuf = next;
  556. continue;
  557. }
  558. /*
  559. * Drop non-EAPOL frames from unauthorized peer.
  560. */
  561. if (qdf_likely(peer) && qdf_unlikely(!peer->authorize)) {
  562. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  563. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  564. if (!is_eapol) {
  565. DP_STATS_INC(soc,
  566. rx.err.peer_unauth_rx_pkt_drop,
  567. 1);
  568. qdf_nbuf_free(nbuf);
  569. nbuf = next;
  570. continue;
  571. }
  572. }
  573. if (soc->process_rx_status)
  574. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  575. /* Update the protocol tag in SKB based on CCE metadata */
  576. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  577. reo_ring_num, false, true);
  578. /* Update the flow tag in SKB based on FSE metadata */
  579. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  580. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  581. reo_ring_num, tid_stats);
  582. if (qdf_unlikely(vdev->mesh_vdev)) {
  583. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  584. == QDF_STATUS_SUCCESS) {
  585. dp_rx_info("%pK: mesh pkt filtered", soc);
  586. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  587. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  588. 1);
  589. qdf_nbuf_free(nbuf);
  590. nbuf = next;
  591. continue;
  592. }
  593. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  594. }
  595. if (qdf_likely(vdev->rx_decap_type ==
  596. htt_cmn_pkt_type_ethernet) &&
  597. qdf_likely(!vdev->mesh_vdev)) {
  598. /* WDS Destination Address Learning */
  599. dp_rx_da_learn(soc, rx_tlv_hdr, peer, nbuf);
  600. /* WDS Source Port Learning */
  601. if (qdf_likely(vdev->wds_enabled))
  602. dp_rx_wds_srcport_learn(soc,
  603. rx_tlv_hdr,
  604. peer,
  605. nbuf,
  606. msdu_metadata);
  607. /* Intrabss-fwd */
  608. if (dp_rx_check_ap_bridge(vdev))
  609. if (DP_RX_INTRABSS_FWD(soc, peer, rx_tlv_hdr,
  610. nbuf, msdu_metadata)) {
  611. nbuf = next;
  612. tid_stats->intrabss_cnt++;
  613. continue; /* Get next desc */
  614. }
  615. }
  616. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  617. dp_rx_update_stats(soc, nbuf);
  618. DP_RX_LIST_APPEND(deliver_list_head,
  619. deliver_list_tail,
  620. nbuf);
  621. DP_STATS_INC_PKT(peer, rx.to_stack, 1,
  622. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  623. if (qdf_unlikely(peer->in_twt))
  624. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  625. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  626. tid_stats->delivered_to_stack++;
  627. nbuf = next;
  628. }
  629. if (qdf_likely(deliver_list_head)) {
  630. if (qdf_likely(peer)) {
  631. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  632. pkt_capture_offload,
  633. deliver_list_head);
  634. if (!pkt_capture_offload)
  635. dp_rx_deliver_to_stack(soc, vdev, peer,
  636. deliver_list_head,
  637. deliver_list_tail);
  638. } else {
  639. nbuf = deliver_list_head;
  640. while (nbuf) {
  641. next = nbuf->next;
  642. nbuf->next = NULL;
  643. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  644. nbuf = next;
  645. }
  646. }
  647. }
  648. if (qdf_likely(peer))
  649. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  650. /*
  651. * If we are processing in near-full condition, there are 3 scenario
  652. * 1) Ring entries has reached critical state
  653. * 2) Ring entries are still near high threshold
  654. * 3) Ring entries are below the safe level
  655. *
  656. * One more loop will move the state to normal processing and yield
  657. */
  658. if (ring_near_full)
  659. goto more_data;
  660. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  661. if (quota) {
  662. num_pending =
  663. dp_rx_srng_get_num_pending(hal_soc,
  664. hal_ring_hdl,
  665. num_entries,
  666. &near_full);
  667. if (num_pending) {
  668. DP_STATS_INC(soc, rx.hp_oos2, 1);
  669. if (!hif_exec_should_yield(scn, intr_id))
  670. goto more_data;
  671. if (qdf_unlikely(near_full)) {
  672. DP_STATS_INC(soc, rx.near_full, 1);
  673. goto more_data;
  674. }
  675. }
  676. }
  677. if (vdev && vdev->osif_fisa_flush)
  678. vdev->osif_fisa_flush(soc, reo_ring_num);
  679. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  680. vdev->osif_gro_flush(vdev->osif_vdev,
  681. reo_ring_num);
  682. }
  683. }
  684. /* Update histogram statistics by looping through pdev's */
  685. DP_RX_HIST_STATS_PER_PDEV();
  686. return rx_bufs_used; /* Assume no scale factor for now */
  687. }
  688. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  689. /**
  690. * dp_rx_desc_pool_init_be_cc() - initial RX desc pool for cookie conversion
  691. * @soc: Handle to DP Soc structure
  692. * @rx_desc_pool: Rx descriptor pool handler
  693. * @pool_id: Rx descriptor pool ID
  694. *
  695. * Return: QDF_STATUS_SUCCESS - succeeded, others - failed
  696. */
  697. static QDF_STATUS
  698. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  699. struct rx_desc_pool *rx_desc_pool,
  700. uint32_t pool_id)
  701. {
  702. struct dp_soc_be *be_soc;
  703. union dp_rx_desc_list_elem_t *rx_desc_elem;
  704. struct dp_spt_page_desc *page_desc;
  705. struct dp_spt_page_desc_list *page_desc_list;
  706. be_soc = dp_get_be_soc_from_dp_soc(soc);
  707. page_desc_list = &be_soc->rx_spt_page_desc[pool_id];
  708. /* allocate SPT pages from page desc pool */
  709. page_desc_list->num_spt_pages =
  710. dp_cc_spt_page_desc_alloc(be_soc,
  711. &page_desc_list->spt_page_list_head,
  712. &page_desc_list->spt_page_list_tail,
  713. rx_desc_pool->pool_size);
  714. if (!page_desc_list->num_spt_pages) {
  715. dp_err("fail to allocate cookie conversion spt pages");
  716. return QDF_STATUS_E_FAILURE;
  717. }
  718. /* put each RX Desc VA to SPT pages and get corresponding ID */
  719. page_desc = page_desc_list->spt_page_list_head;
  720. rx_desc_elem = rx_desc_pool->freelist;
  721. while (rx_desc_elem) {
  722. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  723. page_desc->avail_entry_index,
  724. &rx_desc_elem->rx_desc);
  725. rx_desc_elem->rx_desc.cookie =
  726. dp_cc_desc_id_generate(page_desc->ppt_index,
  727. page_desc->avail_entry_index);
  728. rx_desc_elem->rx_desc.pool_id = pool_id;
  729. rx_desc_elem->rx_desc.in_use = 0;
  730. rx_desc_elem = rx_desc_elem->next;
  731. page_desc->avail_entry_index++;
  732. if (page_desc->avail_entry_index >=
  733. DP_CC_SPT_PAGE_MAX_ENTRIES)
  734. page_desc = page_desc->next;
  735. }
  736. return QDF_STATUS_SUCCESS;
  737. }
  738. #else
  739. static QDF_STATUS
  740. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  741. struct rx_desc_pool *rx_desc_pool,
  742. uint32_t pool_id)
  743. {
  744. struct dp_soc_be *be_soc;
  745. struct dp_spt_page_desc *page_desc;
  746. struct dp_spt_page_desc_list *page_desc_list;
  747. int i;
  748. be_soc = dp_get_be_soc_from_dp_soc(soc);
  749. page_desc_list = &be_soc->rx_spt_page_desc[pool_id];
  750. /* allocate SPT pages from page desc pool */
  751. page_desc_list->num_spt_pages =
  752. dp_cc_spt_page_desc_alloc(
  753. be_soc,
  754. &page_desc_list->spt_page_list_head,
  755. &page_desc_list->spt_page_list_tail,
  756. rx_desc_pool->pool_size);
  757. if (!page_desc_list->num_spt_pages) {
  758. dp_err("fail to allocate cookie conversion spt pages");
  759. return QDF_STATUS_E_FAILURE;
  760. }
  761. /* put each RX Desc VA to SPT pages and get corresponding ID */
  762. page_desc = page_desc_list->spt_page_list_head;
  763. for (i = 0; i <= rx_desc_pool->pool_size - 1; i++) {
  764. if (i == rx_desc_pool->pool_size - 1)
  765. rx_desc_pool->array[i].next = NULL;
  766. else
  767. rx_desc_pool->array[i].next =
  768. &rx_desc_pool->array[i + 1];
  769. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  770. page_desc->avail_entry_index,
  771. &rx_desc_pool->array[i].rx_desc);
  772. rx_desc_pool->array[i].rx_desc.cookie =
  773. dp_cc_desc_id_generate(page_desc->ppt_index,
  774. page_desc->avail_entry_index);
  775. rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
  776. rx_desc_pool->array[i].rx_desc.in_use = 0;
  777. page_desc->avail_entry_index++;
  778. if (page_desc->avail_entry_index >=
  779. DP_CC_SPT_PAGE_MAX_ENTRIES)
  780. page_desc = page_desc->next;
  781. }
  782. return QDF_STATUS_SUCCESS;
  783. }
  784. #endif
  785. static void
  786. dp_rx_desc_pool_deinit_be_cc(struct dp_soc *soc,
  787. struct rx_desc_pool *rx_desc_pool,
  788. uint32_t pool_id)
  789. {
  790. struct dp_soc_be *be_soc;
  791. struct dp_spt_page_desc *page_desc;
  792. struct dp_spt_page_desc_list *page_desc_list;
  793. be_soc = dp_get_be_soc_from_dp_soc(soc);
  794. page_desc_list = &be_soc->rx_spt_page_desc[pool_id];
  795. if (!page_desc_list->num_spt_pages) {
  796. dp_warn("page_desc_list is empty for pool_id %d", pool_id);
  797. return;
  798. }
  799. /* cleanup for each page */
  800. page_desc = page_desc_list->spt_page_list_head;
  801. while (page_desc) {
  802. page_desc->avail_entry_index = 0;
  803. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  804. page_desc = page_desc->next;
  805. }
  806. /* free pages desc back to pool */
  807. dp_cc_spt_page_desc_free(be_soc,
  808. &page_desc_list->spt_page_list_head,
  809. &page_desc_list->spt_page_list_tail,
  810. page_desc_list->num_spt_pages);
  811. page_desc_list->num_spt_pages = 0;
  812. }
  813. QDF_STATUS dp_rx_desc_pool_init_be(struct dp_soc *soc,
  814. struct rx_desc_pool *rx_desc_pool,
  815. uint32_t pool_id)
  816. {
  817. QDF_STATUS status = QDF_STATUS_SUCCESS;
  818. /* Only regular RX buffer desc pool use HW cookie conversion */
  819. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE) {
  820. dp_info("rx_desc_buf pool init");
  821. status = dp_rx_desc_pool_init_be_cc(soc,
  822. rx_desc_pool,
  823. pool_id);
  824. } else {
  825. dp_info("non_rx_desc_buf_pool init");
  826. status = dp_rx_desc_pool_init_generic(soc, rx_desc_pool, pool_id);
  827. }
  828. return status;
  829. }
  830. void dp_rx_desc_pool_deinit_be(struct dp_soc *soc,
  831. struct rx_desc_pool *rx_desc_pool,
  832. uint32_t pool_id)
  833. {
  834. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE)
  835. dp_rx_desc_pool_deinit_be_cc(soc, rx_desc_pool, pool_id);
  836. }
  837. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  838. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  839. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  840. void *ring_desc,
  841. struct dp_rx_desc **r_rx_desc)
  842. {
  843. if (hal_rx_wbm_get_cookie_convert_done(ring_desc)) {
  844. /* HW cookie conversion done */
  845. *r_rx_desc = (struct dp_rx_desc *)
  846. hal_rx_wbm_get_desc_va(ring_desc);
  847. } else {
  848. /* SW do cookie conversion */
  849. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  850. *r_rx_desc = (struct dp_rx_desc *)
  851. dp_cc_desc_find(soc, cookie);
  852. }
  853. return QDF_STATUS_SUCCESS;
  854. }
  855. #else
  856. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  857. void *ring_desc,
  858. struct dp_rx_desc **r_rx_desc)
  859. {
  860. *r_rx_desc = (struct dp_rx_desc *)
  861. hal_rx_wbm_get_desc_va(ring_desc);
  862. return QDF_STATUS_SUCCESS;
  863. }
  864. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  865. #else
  866. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  867. void *ring_desc,
  868. struct dp_rx_desc **r_rx_desc)
  869. {
  870. /* SW do cookie conversion */
  871. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  872. *r_rx_desc = (struct dp_rx_desc *)
  873. dp_cc_desc_find(soc, cookie);
  874. return QDF_STATUS_SUCCESS;
  875. }
  876. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  877. struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
  878. uint32_t cookie)
  879. {
  880. return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
  881. }
  882. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  883. uint32_t dp_rx_nf_process(struct dp_intr *int_ctx,
  884. hal_ring_handle_t hal_ring_hdl,
  885. uint8_t reo_ring_num,
  886. uint32_t quota)
  887. {
  888. struct dp_soc *soc = int_ctx->soc;
  889. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  890. uint32_t work_done = 0;
  891. if (dp_srng_get_near_full_level(soc, rx_ring) <
  892. DP_SRNG_THRESH_NEAR_FULL)
  893. return 0;
  894. qdf_atomic_set(&rx_ring->near_full, 1);
  895. work_done++;
  896. return work_done;
  897. }
  898. #endif