dp_tx.c 110 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #define DP_TX_QUEUE_MASK 0x3
  34. /* TODO Add support in TSO */
  35. #define DP_DESC_NUM_FRAG(x) 0
  36. /* disable TQM_BYPASS */
  37. #define TQM_BYPASS_WAR 0
  38. /* invalid peer id for reinject*/
  39. #define DP_INVALID_PEER 0XFFFE
  40. /*mapping between hal encrypt type and cdp_sec_type*/
  41. #define MAX_CDP_SEC_TYPE 12
  42. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  43. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  44. HAL_TX_ENCRYPT_TYPE_WEP_128,
  45. HAL_TX_ENCRYPT_TYPE_WEP_104,
  46. HAL_TX_ENCRYPT_TYPE_WEP_40,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  48. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  49. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  50. HAL_TX_ENCRYPT_TYPE_WAPI,
  51. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  53. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  54. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  55. /**
  56. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  57. * @vdev: DP Virtual device handle
  58. * @nbuf: Buffer pointer
  59. * @queue: queue ids container for nbuf
  60. *
  61. * TX packet queue has 2 instances, software descriptors id and dma ring id
  62. * Based on tx feature and hardware configuration queue id combination could be
  63. * different.
  64. * For example -
  65. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  66. * With no XPS,lock based resource protection, Descriptor pool ids are different
  67. * for each vdev, dma ring id will be same as single pdev id
  68. *
  69. * Return: None
  70. */
  71. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  72. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  73. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  74. {
  75. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  76. queue->desc_pool_id = queue_offset;
  77. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  79. "%s, pool_id:%d ring_id: %d",
  80. __func__, queue->desc_pool_id, queue->ring_id);
  81. return;
  82. }
  83. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  84. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  85. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  86. {
  87. /* get flow id */
  88. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  89. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  91. "%s, pool_id:%d ring_id: %d",
  92. __func__, queue->desc_pool_id, queue->ring_id);
  93. return;
  94. }
  95. #endif
  96. #if defined(FEATURE_TSO)
  97. /**
  98. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  99. *
  100. * @soc - core txrx main context
  101. * @seg_desc - tso segment descriptor
  102. * @num_seg_desc - tso number segment descriptor
  103. */
  104. static void dp_tx_tso_unmap_segment(
  105. struct dp_soc *soc,
  106. struct qdf_tso_seg_elem_t *seg_desc,
  107. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  108. {
  109. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  110. if (qdf_unlikely(!seg_desc)) {
  111. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  112. __func__, __LINE__);
  113. qdf_assert(0);
  114. } else if (qdf_unlikely(!num_seg_desc)) {
  115. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  116. __func__, __LINE__);
  117. qdf_assert(0);
  118. } else {
  119. bool is_last_seg;
  120. /* no tso segment left to do dma unmap */
  121. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  122. return;
  123. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  124. true : false;
  125. qdf_nbuf_unmap_tso_segment(soc->osdev,
  126. seg_desc, is_last_seg);
  127. num_seg_desc->num_seg.tso_cmn_num_seg--;
  128. }
  129. }
  130. /**
  131. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  132. * back to the freelist
  133. *
  134. * @soc - soc device handle
  135. * @tx_desc - Tx software descriptor
  136. */
  137. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  138. struct dp_tx_desc_s *tx_desc)
  139. {
  140. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  141. if (qdf_unlikely(!tx_desc->tso_desc)) {
  142. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  143. "%s %d TSO desc is NULL!",
  144. __func__, __LINE__);
  145. qdf_assert(0);
  146. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  147. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  148. "%s %d TSO num desc is NULL!",
  149. __func__, __LINE__);
  150. qdf_assert(0);
  151. } else {
  152. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  153. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  154. /* Add the tso num segment into the free list */
  155. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  156. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  157. tx_desc->tso_num_desc);
  158. tx_desc->tso_num_desc = NULL;
  159. }
  160. /* Add the tso segment into the free list*/
  161. dp_tx_tso_desc_free(soc,
  162. tx_desc->pool_id, tx_desc->tso_desc);
  163. tx_desc->tso_desc = NULL;
  164. }
  165. }
  166. #else
  167. static void dp_tx_tso_unmap_segment(
  168. struct dp_soc *soc,
  169. struct qdf_tso_seg_elem_t *seg_desc,
  170. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  171. {
  172. }
  173. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  174. struct dp_tx_desc_s *tx_desc)
  175. {
  176. }
  177. #endif
  178. /**
  179. * dp_tx_desc_release() - Release Tx Descriptor
  180. * @tx_desc : Tx Descriptor
  181. * @desc_pool_id: Descriptor Pool ID
  182. *
  183. * Deallocate all resources attached to Tx descriptor and free the Tx
  184. * descriptor.
  185. *
  186. * Return:
  187. */
  188. static void
  189. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  190. {
  191. struct dp_pdev *pdev = tx_desc->pdev;
  192. struct dp_soc *soc;
  193. uint8_t comp_status = 0;
  194. qdf_assert(pdev);
  195. soc = pdev->soc;
  196. if (tx_desc->frm_type == dp_tx_frm_tso)
  197. dp_tx_tso_desc_release(soc, tx_desc);
  198. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  199. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  200. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  201. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  202. qdf_atomic_dec(&pdev->num_tx_outstanding);
  203. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  204. qdf_atomic_dec(&pdev->num_tx_exception);
  205. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  206. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  207. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  208. soc->hal_soc);
  209. else
  210. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  212. "Tx Completion Release desc %d status %d outstanding %d",
  213. tx_desc->id, comp_status,
  214. qdf_atomic_read(&pdev->num_tx_outstanding));
  215. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  216. return;
  217. }
  218. /**
  219. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  220. * @vdev: DP vdev Handle
  221. * @nbuf: skb
  222. *
  223. * Prepares and fills HTT metadata in the frame pre-header for special frames
  224. * that should be transmitted using varying transmit parameters.
  225. * There are 2 VDEV modes that currently needs this special metadata -
  226. * 1) Mesh Mode
  227. * 2) DSRC Mode
  228. *
  229. * Return: HTT metadata size
  230. *
  231. */
  232. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  233. uint32_t *meta_data)
  234. {
  235. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  236. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  237. uint8_t htt_desc_size;
  238. /* Size rounded of multiple of 8 bytes */
  239. uint8_t htt_desc_size_aligned;
  240. uint8_t *hdr = NULL;
  241. /*
  242. * Metadata - HTT MSDU Extension header
  243. */
  244. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  245. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  246. if (vdev->mesh_vdev) {
  247. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  248. htt_desc_size_aligned)) {
  249. DP_STATS_INC(vdev,
  250. tx_i.dropped.headroom_insufficient, 1);
  251. return 0;
  252. }
  253. /* Fill and add HTT metaheader */
  254. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  255. if (hdr == NULL) {
  256. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  257. "Error in filling HTT metadata");
  258. return 0;
  259. }
  260. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  261. } else if (vdev->opmode == wlan_op_mode_ocb) {
  262. /* Todo - Add support for DSRC */
  263. }
  264. return htt_desc_size_aligned;
  265. }
  266. /**
  267. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  268. * @tso_seg: TSO segment to process
  269. * @ext_desc: Pointer to MSDU extension descriptor
  270. *
  271. * Return: void
  272. */
  273. #if defined(FEATURE_TSO)
  274. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  275. void *ext_desc)
  276. {
  277. uint8_t num_frag;
  278. uint32_t tso_flags;
  279. /*
  280. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  281. * tcp_flag_mask
  282. *
  283. * Checksum enable flags are set in TCL descriptor and not in Extension
  284. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  285. */
  286. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  287. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  288. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  289. tso_seg->tso_flags.ip_len);
  290. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  291. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  292. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  293. uint32_t lo = 0;
  294. uint32_t hi = 0;
  295. qdf_dmaaddr_to_32s(
  296. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  297. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  298. tso_seg->tso_frags[num_frag].length);
  299. }
  300. return;
  301. }
  302. #else
  303. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  304. void *ext_desc)
  305. {
  306. return;
  307. }
  308. #endif
  309. #if defined(FEATURE_TSO)
  310. /**
  311. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  312. * allocated and free them
  313. *
  314. * @soc: soc handle
  315. * @free_seg: list of tso segments
  316. * @msdu_info: msdu descriptor
  317. *
  318. * Return - void
  319. */
  320. static void dp_tx_free_tso_seg_list(
  321. struct dp_soc *soc,
  322. struct qdf_tso_seg_elem_t *free_seg,
  323. struct dp_tx_msdu_info_s *msdu_info)
  324. {
  325. struct qdf_tso_seg_elem_t *next_seg;
  326. while (free_seg) {
  327. next_seg = free_seg->next;
  328. dp_tx_tso_desc_free(soc,
  329. msdu_info->tx_queue.desc_pool_id,
  330. free_seg);
  331. free_seg = next_seg;
  332. }
  333. }
  334. /**
  335. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  336. * allocated and free them
  337. *
  338. * @soc: soc handle
  339. * @free_num_seg: list of tso number segments
  340. * @msdu_info: msdu descriptor
  341. * Return - void
  342. */
  343. static void dp_tx_free_tso_num_seg_list(
  344. struct dp_soc *soc,
  345. struct qdf_tso_num_seg_elem_t *free_num_seg,
  346. struct dp_tx_msdu_info_s *msdu_info)
  347. {
  348. struct qdf_tso_num_seg_elem_t *next_num_seg;
  349. while (free_num_seg) {
  350. next_num_seg = free_num_seg->next;
  351. dp_tso_num_seg_free(soc,
  352. msdu_info->tx_queue.desc_pool_id,
  353. free_num_seg);
  354. free_num_seg = next_num_seg;
  355. }
  356. }
  357. /**
  358. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  359. * do dma unmap for each segment
  360. *
  361. * @soc: soc handle
  362. * @free_seg: list of tso segments
  363. * @num_seg_desc: tso number segment descriptor
  364. *
  365. * Return - void
  366. */
  367. static void dp_tx_unmap_tso_seg_list(
  368. struct dp_soc *soc,
  369. struct qdf_tso_seg_elem_t *free_seg,
  370. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  371. {
  372. struct qdf_tso_seg_elem_t *next_seg;
  373. if (qdf_unlikely(!num_seg_desc)) {
  374. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  375. return;
  376. }
  377. while (free_seg) {
  378. next_seg = free_seg->next;
  379. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  380. free_seg = next_seg;
  381. }
  382. }
  383. /**
  384. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  385. * free the tso segments descriptor and
  386. * tso num segments descriptor
  387. *
  388. * @soc: soc handle
  389. * @msdu_info: msdu descriptor
  390. * @tso_seg_unmap: flag to show if dma unmap is necessary
  391. *
  392. * Return - void
  393. */
  394. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  395. struct dp_tx_msdu_info_s *msdu_info,
  396. bool tso_seg_unmap)
  397. {
  398. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  399. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  400. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  401. tso_info->tso_num_seg_list;
  402. /* do dma unmap for each segment */
  403. if (tso_seg_unmap)
  404. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  405. /* free all tso number segment descriptor though looks only have 1 */
  406. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  407. /* free all tso segment descriptor */
  408. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  409. }
  410. /**
  411. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  412. * @vdev: virtual device handle
  413. * @msdu: network buffer
  414. * @msdu_info: meta data associated with the msdu
  415. *
  416. * Return: QDF_STATUS_SUCCESS success
  417. */
  418. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  419. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  420. {
  421. struct qdf_tso_seg_elem_t *tso_seg;
  422. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  423. struct dp_soc *soc = vdev->pdev->soc;
  424. struct qdf_tso_info_t *tso_info;
  425. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  426. tso_info = &msdu_info->u.tso_info;
  427. tso_info->curr_seg = NULL;
  428. tso_info->tso_seg_list = NULL;
  429. tso_info->num_segs = num_seg;
  430. msdu_info->frm_type = dp_tx_frm_tso;
  431. tso_info->tso_num_seg_list = NULL;
  432. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  433. while (num_seg) {
  434. tso_seg = dp_tx_tso_desc_alloc(
  435. soc, msdu_info->tx_queue.desc_pool_id);
  436. if (tso_seg) {
  437. tso_seg->next = tso_info->tso_seg_list;
  438. tso_info->tso_seg_list = tso_seg;
  439. num_seg--;
  440. } else {
  441. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  442. __func__);
  443. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  444. return QDF_STATUS_E_NOMEM;
  445. }
  446. }
  447. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  448. tso_num_seg = dp_tso_num_seg_alloc(soc,
  449. msdu_info->tx_queue.desc_pool_id);
  450. if (tso_num_seg) {
  451. tso_num_seg->next = tso_info->tso_num_seg_list;
  452. tso_info->tso_num_seg_list = tso_num_seg;
  453. } else {
  454. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  455. __func__);
  456. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  457. return QDF_STATUS_E_NOMEM;
  458. }
  459. msdu_info->num_seg =
  460. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  461. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  462. msdu_info->num_seg);
  463. if (!(msdu_info->num_seg)) {
  464. /*
  465. * Free allocated TSO seg desc and number seg desc,
  466. * do unmap for segments if dma map has done.
  467. */
  468. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  469. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  470. return QDF_STATUS_E_INVAL;
  471. }
  472. tso_info->curr_seg = tso_info->tso_seg_list;
  473. return QDF_STATUS_SUCCESS;
  474. }
  475. #else
  476. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  477. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  478. {
  479. return QDF_STATUS_E_NOMEM;
  480. }
  481. #endif
  482. /**
  483. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  484. * @vdev: DP Vdev handle
  485. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  486. * @desc_pool_id: Descriptor Pool ID
  487. *
  488. * Return:
  489. */
  490. static
  491. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  492. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  493. {
  494. uint8_t i;
  495. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  496. struct dp_tx_seg_info_s *seg_info;
  497. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  498. struct dp_soc *soc = vdev->pdev->soc;
  499. /* Allocate an extension descriptor */
  500. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  501. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  502. if (!msdu_ext_desc) {
  503. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  504. return NULL;
  505. }
  506. if (msdu_info->exception_fw &&
  507. qdf_unlikely(vdev->mesh_vdev)) {
  508. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  509. &msdu_info->meta_data[0],
  510. sizeof(struct htt_tx_msdu_desc_ext2_t));
  511. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  512. }
  513. switch (msdu_info->frm_type) {
  514. case dp_tx_frm_sg:
  515. case dp_tx_frm_me:
  516. case dp_tx_frm_raw:
  517. seg_info = msdu_info->u.sg_info.curr_seg;
  518. /* Update the buffer pointers in MSDU Extension Descriptor */
  519. for (i = 0; i < seg_info->frag_cnt; i++) {
  520. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  521. seg_info->frags[i].paddr_lo,
  522. seg_info->frags[i].paddr_hi,
  523. seg_info->frags[i].len);
  524. }
  525. break;
  526. case dp_tx_frm_tso:
  527. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  528. &cached_ext_desc[0]);
  529. break;
  530. default:
  531. break;
  532. }
  533. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  534. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  535. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  536. msdu_ext_desc->vaddr);
  537. return msdu_ext_desc;
  538. }
  539. /**
  540. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  541. *
  542. * @skb: skb to be traced
  543. * @msdu_id: msdu_id of the packet
  544. * @vdev_id: vdev_id of the packet
  545. *
  546. * Return: None
  547. */
  548. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  549. uint8_t vdev_id)
  550. {
  551. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  552. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  553. DPTRACE(qdf_dp_trace_ptr(skb,
  554. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  555. QDF_TRACE_DEFAULT_PDEV_ID,
  556. qdf_nbuf_data_addr(skb),
  557. sizeof(qdf_nbuf_data(skb)),
  558. msdu_id, vdev_id));
  559. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  560. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  561. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  562. msdu_id, QDF_TX));
  563. }
  564. /**
  565. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  566. * @vdev: DP vdev handle
  567. * @nbuf: skb
  568. * @desc_pool_id: Descriptor pool ID
  569. * @meta_data: Metadata to the fw
  570. * @tx_exc_metadata: Handle that holds exception path metadata
  571. * Allocate and prepare Tx descriptor with msdu information.
  572. *
  573. * Return: Pointer to Tx Descriptor on success,
  574. * NULL on failure
  575. */
  576. static
  577. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  578. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  579. struct dp_tx_msdu_info_s *msdu_info,
  580. struct cdp_tx_exception_metadata *tx_exc_metadata)
  581. {
  582. uint8_t align_pad;
  583. uint8_t is_exception = 0;
  584. uint8_t htt_hdr_size;
  585. qdf_ether_header_t *eh;
  586. struct dp_tx_desc_s *tx_desc;
  587. struct dp_pdev *pdev = vdev->pdev;
  588. struct dp_soc *soc = pdev->soc;
  589. /* Allocate software Tx descriptor */
  590. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  591. if (qdf_unlikely(!tx_desc)) {
  592. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  593. return NULL;
  594. }
  595. /* Flow control/Congestion Control counters */
  596. qdf_atomic_inc(&pdev->num_tx_outstanding);
  597. /* Initialize the SW tx descriptor */
  598. tx_desc->nbuf = nbuf;
  599. tx_desc->frm_type = dp_tx_frm_std;
  600. tx_desc->tx_encap_type = (tx_exc_metadata ?
  601. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  602. tx_desc->vdev = vdev;
  603. tx_desc->pdev = pdev;
  604. tx_desc->msdu_ext_desc = NULL;
  605. tx_desc->pkt_offset = 0;
  606. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  607. /*
  608. * For special modes (vdev_type == ocb or mesh), data frames should be
  609. * transmitted using varying transmit parameters (tx spec) which include
  610. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  611. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  612. * These frames are sent as exception packets to firmware.
  613. *
  614. * HW requirement is that metadata should always point to a
  615. * 8-byte aligned address. So we add alignment pad to start of buffer.
  616. * HTT Metadata should be ensured to be multiple of 8-bytes,
  617. * to get 8-byte aligned start address along with align_pad added
  618. *
  619. * |-----------------------------|
  620. * | |
  621. * |-----------------------------| <-----Buffer Pointer Address given
  622. * | | ^ in HW descriptor (aligned)
  623. * | HTT Metadata | |
  624. * | | |
  625. * | | | Packet Offset given in descriptor
  626. * | | |
  627. * |-----------------------------| |
  628. * | Alignment Pad | v
  629. * |-----------------------------| <----- Actual buffer start address
  630. * | SKB Data | (Unaligned)
  631. * | |
  632. * | |
  633. * | |
  634. * | |
  635. * | |
  636. * |-----------------------------|
  637. */
  638. if (qdf_unlikely((msdu_info->exception_fw)) ||
  639. (vdev->opmode == wlan_op_mode_ocb)) {
  640. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  641. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  642. DP_STATS_INC(vdev,
  643. tx_i.dropped.headroom_insufficient, 1);
  644. goto failure;
  645. }
  646. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  647. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  648. "qdf_nbuf_push_head failed");
  649. goto failure;
  650. }
  651. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  652. msdu_info->meta_data);
  653. if (htt_hdr_size == 0)
  654. goto failure;
  655. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  656. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  657. is_exception = 1;
  658. }
  659. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  660. qdf_nbuf_map(soc->osdev, nbuf,
  661. QDF_DMA_TO_DEVICE))) {
  662. /* Handle failure */
  663. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  664. "qdf_nbuf_map failed");
  665. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  666. goto failure;
  667. }
  668. if (qdf_unlikely(vdev->nawds_enabled)) {
  669. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  670. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  671. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  672. is_exception = 1;
  673. }
  674. }
  675. #if !TQM_BYPASS_WAR
  676. if (is_exception || tx_exc_metadata)
  677. #endif
  678. {
  679. /* Temporary WAR due to TQM VP issues */
  680. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  681. qdf_atomic_inc(&pdev->num_tx_exception);
  682. }
  683. return tx_desc;
  684. failure:
  685. dp_tx_desc_release(tx_desc, desc_pool_id);
  686. return NULL;
  687. }
  688. /**
  689. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  690. * @vdev: DP vdev handle
  691. * @nbuf: skb
  692. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  693. * @desc_pool_id : Descriptor Pool ID
  694. *
  695. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  696. * information. For frames wth fragments, allocate and prepare
  697. * an MSDU extension descriptor
  698. *
  699. * Return: Pointer to Tx Descriptor on success,
  700. * NULL on failure
  701. */
  702. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  703. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  704. uint8_t desc_pool_id)
  705. {
  706. struct dp_tx_desc_s *tx_desc;
  707. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  708. struct dp_pdev *pdev = vdev->pdev;
  709. struct dp_soc *soc = pdev->soc;
  710. /* Allocate software Tx descriptor */
  711. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  712. if (!tx_desc) {
  713. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  714. return NULL;
  715. }
  716. /* Flow control/Congestion Control counters */
  717. qdf_atomic_inc(&pdev->num_tx_outstanding);
  718. /* Initialize the SW tx descriptor */
  719. tx_desc->nbuf = nbuf;
  720. tx_desc->frm_type = msdu_info->frm_type;
  721. tx_desc->tx_encap_type = vdev->tx_encap_type;
  722. tx_desc->vdev = vdev;
  723. tx_desc->pdev = pdev;
  724. tx_desc->pkt_offset = 0;
  725. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  726. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  727. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  728. /* Handle scattered frames - TSO/SG/ME */
  729. /* Allocate and prepare an extension descriptor for scattered frames */
  730. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  731. if (!msdu_ext_desc) {
  732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  733. "%s Tx Extension Descriptor Alloc Fail",
  734. __func__);
  735. goto failure;
  736. }
  737. #if TQM_BYPASS_WAR
  738. /* Temporary WAR due to TQM VP issues */
  739. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  740. qdf_atomic_inc(&pdev->num_tx_exception);
  741. #endif
  742. if (qdf_unlikely(msdu_info->exception_fw))
  743. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  744. tx_desc->msdu_ext_desc = msdu_ext_desc;
  745. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  746. return tx_desc;
  747. failure:
  748. dp_tx_desc_release(tx_desc, desc_pool_id);
  749. return NULL;
  750. }
  751. /**
  752. * dp_tx_prepare_raw() - Prepare RAW packet TX
  753. * @vdev: DP vdev handle
  754. * @nbuf: buffer pointer
  755. * @seg_info: Pointer to Segment info Descriptor to be prepared
  756. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  757. * descriptor
  758. *
  759. * Return:
  760. */
  761. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  762. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  763. {
  764. qdf_nbuf_t curr_nbuf = NULL;
  765. uint16_t total_len = 0;
  766. qdf_dma_addr_t paddr;
  767. int32_t i;
  768. int32_t mapped_buf_num = 0;
  769. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  770. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  771. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  772. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  773. if (vdev->raw_mode_war &&
  774. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS))
  775. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  776. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  777. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  778. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  779. QDF_DMA_TO_DEVICE)) {
  780. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  781. "%s dma map error ", __func__);
  782. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  783. mapped_buf_num = i;
  784. goto error;
  785. }
  786. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  787. seg_info->frags[i].paddr_lo = paddr;
  788. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  789. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  790. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  791. total_len += qdf_nbuf_len(curr_nbuf);
  792. }
  793. seg_info->frag_cnt = i;
  794. seg_info->total_len = total_len;
  795. seg_info->next = NULL;
  796. sg_info->curr_seg = seg_info;
  797. msdu_info->frm_type = dp_tx_frm_raw;
  798. msdu_info->num_seg = 1;
  799. return nbuf;
  800. error:
  801. i = 0;
  802. while (nbuf) {
  803. curr_nbuf = nbuf;
  804. if (i < mapped_buf_num) {
  805. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  806. i++;
  807. }
  808. nbuf = qdf_nbuf_next(nbuf);
  809. qdf_nbuf_free(curr_nbuf);
  810. }
  811. return NULL;
  812. }
  813. /**
  814. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  815. * @soc: DP Soc Handle
  816. * @vdev: DP vdev handle
  817. * @tx_desc: Tx Descriptor Handle
  818. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  819. * @fw_metadata: Metadata to send to Target Firmware along with frame
  820. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  821. * @tx_exc_metadata: Handle that holds exception path meta data
  822. *
  823. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  824. * from software Tx descriptor
  825. *
  826. * Return:
  827. */
  828. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  829. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  830. uint16_t fw_metadata, uint8_t ring_id,
  831. struct cdp_tx_exception_metadata
  832. *tx_exc_metadata)
  833. {
  834. uint8_t type;
  835. uint16_t length;
  836. void *hal_tx_desc, *hal_tx_desc_cached;
  837. qdf_dma_addr_t dma_addr;
  838. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  839. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  840. tx_exc_metadata->sec_type : vdev->sec_type);
  841. /* Return Buffer Manager ID */
  842. uint8_t bm_id = ring_id;
  843. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  844. hal_tx_desc_cached = (void *) cached_desc;
  845. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  846. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  847. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  848. type = HAL_TX_BUF_TYPE_EXT_DESC;
  849. dma_addr = tx_desc->msdu_ext_desc->paddr;
  850. } else {
  851. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  852. type = HAL_TX_BUF_TYPE_BUFFER;
  853. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  854. }
  855. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  856. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  857. dma_addr, bm_id, tx_desc->id,
  858. type, soc->hal_soc);
  859. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  860. return QDF_STATUS_E_RESOURCES;
  861. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  862. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  863. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  864. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  865. vdev->pdev->lmac_id);
  866. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  867. vdev->search_type);
  868. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  869. vdev->bss_ast_hash);
  870. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  871. vdev->dscp_tid_map_id);
  872. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  873. sec_type_map[sec_type]);
  874. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  875. length, type, (uint64_t)dma_addr,
  876. tx_desc->pkt_offset, tx_desc->id);
  877. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  878. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  879. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  880. vdev->hal_desc_addr_search_flags);
  881. /* verify checksum offload configuration*/
  882. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  883. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  884. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  885. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  886. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  887. }
  888. if (tid != HTT_TX_EXT_TID_INVALID)
  889. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  890. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  891. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  892. /* Sync cached descriptor with HW */
  893. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  894. if (!hal_tx_desc) {
  895. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  896. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  897. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  898. return QDF_STATUS_E_RESOURCES;
  899. }
  900. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  901. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  902. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  903. return QDF_STATUS_SUCCESS;
  904. }
  905. /**
  906. * dp_cce_classify() - Classify the frame based on CCE rules
  907. * @vdev: DP vdev handle
  908. * @nbuf: skb
  909. *
  910. * Classify frames based on CCE rules
  911. * Return: bool( true if classified,
  912. * else false)
  913. */
  914. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  915. {
  916. qdf_ether_header_t *eh = NULL;
  917. uint16_t ether_type;
  918. qdf_llc_t *llcHdr;
  919. qdf_nbuf_t nbuf_clone = NULL;
  920. qdf_dot3_qosframe_t *qos_wh = NULL;
  921. /* for mesh packets don't do any classification */
  922. if (qdf_unlikely(vdev->mesh_vdev))
  923. return false;
  924. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  925. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  926. ether_type = eh->ether_type;
  927. llcHdr = (qdf_llc_t *)(nbuf->data +
  928. sizeof(qdf_ether_header_t));
  929. } else {
  930. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  931. /* For encrypted packets don't do any classification */
  932. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  933. return false;
  934. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  935. if (qdf_unlikely(
  936. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  937. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  938. ether_type = *(uint16_t *)(nbuf->data
  939. + QDF_IEEE80211_4ADDR_HDR_LEN
  940. + sizeof(qdf_llc_t)
  941. - sizeof(ether_type));
  942. llcHdr = (qdf_llc_t *)(nbuf->data +
  943. QDF_IEEE80211_4ADDR_HDR_LEN);
  944. } else {
  945. ether_type = *(uint16_t *)(nbuf->data
  946. + QDF_IEEE80211_3ADDR_HDR_LEN
  947. + sizeof(qdf_llc_t)
  948. - sizeof(ether_type));
  949. llcHdr = (qdf_llc_t *)(nbuf->data +
  950. QDF_IEEE80211_3ADDR_HDR_LEN);
  951. }
  952. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  953. && (ether_type ==
  954. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  955. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  956. return true;
  957. }
  958. }
  959. return false;
  960. }
  961. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  962. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  963. sizeof(*llcHdr));
  964. nbuf_clone = qdf_nbuf_clone(nbuf);
  965. if (qdf_unlikely(nbuf_clone)) {
  966. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  967. if (ether_type == htons(ETHERTYPE_VLAN)) {
  968. qdf_nbuf_pull_head(nbuf_clone,
  969. sizeof(qdf_net_vlanhdr_t));
  970. }
  971. }
  972. } else {
  973. if (ether_type == htons(ETHERTYPE_VLAN)) {
  974. nbuf_clone = qdf_nbuf_clone(nbuf);
  975. if (qdf_unlikely(nbuf_clone)) {
  976. qdf_nbuf_pull_head(nbuf_clone,
  977. sizeof(qdf_net_vlanhdr_t));
  978. }
  979. }
  980. }
  981. if (qdf_unlikely(nbuf_clone))
  982. nbuf = nbuf_clone;
  983. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  984. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  985. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  986. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  987. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  988. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  989. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  990. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  991. if (qdf_unlikely(nbuf_clone != NULL))
  992. qdf_nbuf_free(nbuf_clone);
  993. return true;
  994. }
  995. if (qdf_unlikely(nbuf_clone != NULL))
  996. qdf_nbuf_free(nbuf_clone);
  997. return false;
  998. }
  999. /**
  1000. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1001. * @vdev: DP vdev handle
  1002. * @nbuf: skb
  1003. *
  1004. * Extract the DSCP or PCP information from frame and map into TID value.
  1005. *
  1006. * Return: void
  1007. */
  1008. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1009. struct dp_tx_msdu_info_s *msdu_info)
  1010. {
  1011. uint8_t tos = 0, dscp_tid_override = 0;
  1012. uint8_t *hdr_ptr, *L3datap;
  1013. uint8_t is_mcast = 0;
  1014. qdf_ether_header_t *eh = NULL;
  1015. qdf_ethervlan_header_t *evh = NULL;
  1016. uint16_t ether_type;
  1017. qdf_llc_t *llcHdr;
  1018. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1019. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1020. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1021. eh = (qdf_ether_header_t *)nbuf->data;
  1022. hdr_ptr = eh->ether_dhost;
  1023. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1024. } else {
  1025. qdf_dot3_qosframe_t *qos_wh =
  1026. (qdf_dot3_qosframe_t *) nbuf->data;
  1027. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1028. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1029. return;
  1030. }
  1031. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1032. ether_type = eh->ether_type;
  1033. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1034. /*
  1035. * Check if packet is dot3 or eth2 type.
  1036. */
  1037. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1038. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  1039. sizeof(*llcHdr));
  1040. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1041. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1042. sizeof(*llcHdr);
  1043. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  1044. + sizeof(*llcHdr) +
  1045. sizeof(qdf_net_vlanhdr_t));
  1046. } else {
  1047. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1048. sizeof(*llcHdr);
  1049. }
  1050. } else {
  1051. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1052. evh = (qdf_ethervlan_header_t *) eh;
  1053. ether_type = evh->ether_type;
  1054. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1055. }
  1056. }
  1057. /*
  1058. * Find priority from IP TOS DSCP field
  1059. */
  1060. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1061. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1062. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1063. /* Only for unicast frames */
  1064. if (!is_mcast) {
  1065. /* send it on VO queue */
  1066. msdu_info->tid = DP_VO_TID;
  1067. }
  1068. } else {
  1069. /*
  1070. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1071. * from TOS byte.
  1072. */
  1073. tos = ip->ip_tos;
  1074. dscp_tid_override = 1;
  1075. }
  1076. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1077. /* TODO
  1078. * use flowlabel
  1079. *igmpmld cases to be handled in phase 2
  1080. */
  1081. unsigned long ver_pri_flowlabel;
  1082. unsigned long pri;
  1083. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1084. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1085. DP_IPV6_PRIORITY_SHIFT;
  1086. tos = pri;
  1087. dscp_tid_override = 1;
  1088. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1089. msdu_info->tid = DP_VO_TID;
  1090. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1091. /* Only for unicast frames */
  1092. if (!is_mcast) {
  1093. /* send ucast arp on VO queue */
  1094. msdu_info->tid = DP_VO_TID;
  1095. }
  1096. }
  1097. /*
  1098. * Assign all MCAST packets to BE
  1099. */
  1100. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1101. if (is_mcast) {
  1102. tos = 0;
  1103. dscp_tid_override = 1;
  1104. }
  1105. }
  1106. if (dscp_tid_override == 1) {
  1107. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1108. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1109. }
  1110. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1111. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1112. return;
  1113. }
  1114. /**
  1115. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1116. * @vdev: DP vdev handle
  1117. * @nbuf: skb
  1118. *
  1119. * Software based TID classification is required when more than 2 DSCP-TID
  1120. * mapping tables are needed.
  1121. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1122. *
  1123. * Return: void
  1124. */
  1125. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1126. struct dp_tx_msdu_info_s *msdu_info)
  1127. {
  1128. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1129. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1130. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1131. return;
  1132. /* for mesh packets don't do any classification */
  1133. if (qdf_unlikely(vdev->mesh_vdev))
  1134. return;
  1135. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1136. }
  1137. #ifdef FEATURE_WLAN_TDLS
  1138. /**
  1139. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1140. * @tx_desc: TX descriptor
  1141. *
  1142. * Return: None
  1143. */
  1144. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1145. {
  1146. if (tx_desc->vdev) {
  1147. if (tx_desc->vdev->is_tdls_frame) {
  1148. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1149. tx_desc->vdev->is_tdls_frame = false;
  1150. }
  1151. }
  1152. }
  1153. /**
  1154. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1155. * @tx_desc: TX descriptor
  1156. * @vdev: datapath vdev handle
  1157. *
  1158. * Return: None
  1159. */
  1160. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1161. struct dp_vdev *vdev)
  1162. {
  1163. struct hal_tx_completion_status ts = {0};
  1164. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1165. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1166. if (vdev->tx_non_std_data_callback.func) {
  1167. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1168. vdev->tx_non_std_data_callback.func(
  1169. vdev->tx_non_std_data_callback.ctxt,
  1170. nbuf, ts.status);
  1171. return;
  1172. }
  1173. }
  1174. #else
  1175. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1176. {
  1177. }
  1178. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1179. struct dp_vdev *vdev)
  1180. {
  1181. }
  1182. #endif
  1183. /**
  1184. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1185. * @vdev: DP vdev handle
  1186. * @nbuf: skb
  1187. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1188. * @meta_data: Metadata to the fw
  1189. * @tx_q: Tx queue to be used for this Tx frame
  1190. * @peer_id: peer_id of the peer in case of NAWDS frames
  1191. * @tx_exc_metadata: Handle that holds exception path metadata
  1192. *
  1193. * Return: NULL on success,
  1194. * nbuf when it fails to send
  1195. */
  1196. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1197. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1198. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1199. {
  1200. struct dp_pdev *pdev = vdev->pdev;
  1201. struct dp_soc *soc = pdev->soc;
  1202. struct dp_tx_desc_s *tx_desc;
  1203. QDF_STATUS status;
  1204. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1205. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1206. uint16_t htt_tcl_metadata = 0;
  1207. uint8_t tid = msdu_info->tid;
  1208. struct cdp_tid_tx_stats *tid_stats = NULL;
  1209. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1210. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1211. msdu_info, tx_exc_metadata);
  1212. if (!tx_desc) {
  1213. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1214. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1215. __func__, vdev, tx_q->desc_pool_id);
  1216. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1217. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1218. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1219. return nbuf;
  1220. }
  1221. if (qdf_unlikely(soc->cce_disable)) {
  1222. if (dp_cce_classify(vdev, nbuf) == true) {
  1223. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1224. tid = DP_VO_TID;
  1225. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1226. }
  1227. }
  1228. dp_tx_update_tdls_flags(tx_desc);
  1229. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1230. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1231. "%s %d : HAL RING Access Failed -- %pK",
  1232. __func__, __LINE__, hal_srng);
  1233. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1234. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1235. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1236. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1237. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1238. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1239. goto fail_return;
  1240. }
  1241. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1242. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1243. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1244. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1245. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1246. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1247. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1248. peer_id);
  1249. } else
  1250. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1251. if (msdu_info->exception_fw) {
  1252. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1253. }
  1254. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1255. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1256. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1257. if (status != QDF_STATUS_SUCCESS) {
  1258. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1259. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1260. __func__, tx_desc, tx_q->ring_id);
  1261. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1262. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1263. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1264. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1265. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1266. goto fail_return;
  1267. }
  1268. nbuf = NULL;
  1269. fail_return:
  1270. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1271. hal_srng_access_end(soc->hal_soc, hal_srng);
  1272. hif_pm_runtime_put(soc->hif_handle);
  1273. } else {
  1274. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1275. }
  1276. return nbuf;
  1277. }
  1278. /**
  1279. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1280. * @vdev: DP vdev handle
  1281. * @nbuf: skb
  1282. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1283. *
  1284. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1285. *
  1286. * Return: NULL on success,
  1287. * nbuf when it fails to send
  1288. */
  1289. #if QDF_LOCK_STATS
  1290. static noinline
  1291. #else
  1292. static
  1293. #endif
  1294. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1295. struct dp_tx_msdu_info_s *msdu_info)
  1296. {
  1297. uint8_t i;
  1298. struct dp_pdev *pdev = vdev->pdev;
  1299. struct dp_soc *soc = pdev->soc;
  1300. struct dp_tx_desc_s *tx_desc;
  1301. bool is_cce_classified = false;
  1302. QDF_STATUS status;
  1303. uint16_t htt_tcl_metadata = 0;
  1304. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1305. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1306. struct cdp_tid_tx_stats *tid_stats = NULL;
  1307. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1308. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1309. "%s %d : HAL RING Access Failed -- %pK",
  1310. __func__, __LINE__, hal_srng);
  1311. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1312. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1313. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1314. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1315. return nbuf;
  1316. }
  1317. if (qdf_unlikely(soc->cce_disable)) {
  1318. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1319. if (is_cce_classified) {
  1320. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1321. msdu_info->tid = DP_VO_TID;
  1322. }
  1323. }
  1324. if (msdu_info->frm_type == dp_tx_frm_me)
  1325. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1326. i = 0;
  1327. /* Print statement to track i and num_seg */
  1328. /*
  1329. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1330. * descriptors using information in msdu_info
  1331. */
  1332. while (i < msdu_info->num_seg) {
  1333. /*
  1334. * Setup Tx descriptor for an MSDU, and MSDU extension
  1335. * descriptor
  1336. */
  1337. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1338. tx_q->desc_pool_id);
  1339. if (!tx_desc) {
  1340. if (msdu_info->frm_type == dp_tx_frm_me) {
  1341. dp_tx_me_free_buf(pdev,
  1342. (void *)(msdu_info->u.sg_info
  1343. .curr_seg->frags[0].vaddr));
  1344. }
  1345. goto done;
  1346. }
  1347. if (msdu_info->frm_type == dp_tx_frm_me) {
  1348. tx_desc->me_buffer =
  1349. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1350. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1351. }
  1352. if (is_cce_classified)
  1353. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1354. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1355. if (msdu_info->exception_fw) {
  1356. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1357. }
  1358. /*
  1359. * Enqueue the Tx MSDU descriptor to HW for transmit
  1360. */
  1361. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1362. htt_tcl_metadata, tx_q->ring_id, NULL);
  1363. if (status != QDF_STATUS_SUCCESS) {
  1364. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1365. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1366. __func__, tx_desc, tx_q->ring_id);
  1367. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1368. tid_stats = &pdev->stats.tid_stats.
  1369. tid_tx_stats[msdu_info->tid];
  1370. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1371. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1372. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1373. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1374. goto done;
  1375. }
  1376. /*
  1377. * TODO
  1378. * if tso_info structure can be modified to have curr_seg
  1379. * as first element, following 2 blocks of code (for TSO and SG)
  1380. * can be combined into 1
  1381. */
  1382. /*
  1383. * For frames with multiple segments (TSO, ME), jump to next
  1384. * segment.
  1385. */
  1386. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1387. if (msdu_info->u.tso_info.curr_seg->next) {
  1388. msdu_info->u.tso_info.curr_seg =
  1389. msdu_info->u.tso_info.curr_seg->next;
  1390. /*
  1391. * If this is a jumbo nbuf, then increment the number of
  1392. * nbuf users for each additional segment of the msdu.
  1393. * This will ensure that the skb is freed only after
  1394. * receiving tx completion for all segments of an nbuf
  1395. */
  1396. qdf_nbuf_inc_users(nbuf);
  1397. /* Check with MCL if this is needed */
  1398. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1399. }
  1400. }
  1401. /*
  1402. * For Multicast-Unicast converted packets,
  1403. * each converted frame (for a client) is represented as
  1404. * 1 segment
  1405. */
  1406. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1407. (msdu_info->frm_type == dp_tx_frm_me)) {
  1408. if (msdu_info->u.sg_info.curr_seg->next) {
  1409. msdu_info->u.sg_info.curr_seg =
  1410. msdu_info->u.sg_info.curr_seg->next;
  1411. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1412. }
  1413. }
  1414. i++;
  1415. }
  1416. nbuf = NULL;
  1417. done:
  1418. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1419. hal_srng_access_end(soc->hal_soc, hal_srng);
  1420. hif_pm_runtime_put(soc->hif_handle);
  1421. } else {
  1422. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1423. }
  1424. return nbuf;
  1425. }
  1426. /**
  1427. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1428. * for SG frames
  1429. * @vdev: DP vdev handle
  1430. * @nbuf: skb
  1431. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1432. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1433. *
  1434. * Return: NULL on success,
  1435. * nbuf when it fails to send
  1436. */
  1437. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1438. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1439. {
  1440. uint32_t cur_frag, nr_frags;
  1441. qdf_dma_addr_t paddr;
  1442. struct dp_tx_sg_info_s *sg_info;
  1443. sg_info = &msdu_info->u.sg_info;
  1444. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1445. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1446. QDF_DMA_TO_DEVICE)) {
  1447. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1448. "dma map error");
  1449. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1450. qdf_nbuf_free(nbuf);
  1451. return NULL;
  1452. }
  1453. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1454. seg_info->frags[0].paddr_lo = paddr;
  1455. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1456. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1457. seg_info->frags[0].vaddr = (void *) nbuf;
  1458. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1459. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1460. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1461. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1462. "frag dma map error");
  1463. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1464. qdf_nbuf_free(nbuf);
  1465. return NULL;
  1466. }
  1467. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1468. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1469. seg_info->frags[cur_frag + 1].paddr_hi =
  1470. ((uint64_t) paddr) >> 32;
  1471. seg_info->frags[cur_frag + 1].len =
  1472. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1473. }
  1474. seg_info->frag_cnt = (cur_frag + 1);
  1475. seg_info->total_len = qdf_nbuf_len(nbuf);
  1476. seg_info->next = NULL;
  1477. sg_info->curr_seg = seg_info;
  1478. msdu_info->frm_type = dp_tx_frm_sg;
  1479. msdu_info->num_seg = 1;
  1480. return nbuf;
  1481. }
  1482. #ifdef MESH_MODE_SUPPORT
  1483. /**
  1484. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1485. and prepare msdu_info for mesh frames.
  1486. * @vdev: DP vdev handle
  1487. * @nbuf: skb
  1488. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1489. *
  1490. * Return: NULL on failure,
  1491. * nbuf when extracted successfully
  1492. */
  1493. static
  1494. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1495. struct dp_tx_msdu_info_s *msdu_info)
  1496. {
  1497. struct meta_hdr_s *mhdr;
  1498. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1499. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1500. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1501. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1502. msdu_info->exception_fw = 0;
  1503. goto remove_meta_hdr;
  1504. }
  1505. msdu_info->exception_fw = 1;
  1506. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1507. meta_data->host_tx_desc_pool = 1;
  1508. meta_data->update_peer_cache = 1;
  1509. meta_data->learning_frame = 1;
  1510. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1511. meta_data->power = mhdr->power;
  1512. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1513. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1514. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1515. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1516. meta_data->dyn_bw = 1;
  1517. meta_data->valid_pwr = 1;
  1518. meta_data->valid_mcs_mask = 1;
  1519. meta_data->valid_nss_mask = 1;
  1520. meta_data->valid_preamble_type = 1;
  1521. meta_data->valid_retries = 1;
  1522. meta_data->valid_bw_info = 1;
  1523. }
  1524. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1525. meta_data->encrypt_type = 0;
  1526. meta_data->valid_encrypt_type = 1;
  1527. meta_data->learning_frame = 0;
  1528. }
  1529. meta_data->valid_key_flags = 1;
  1530. meta_data->key_flags = (mhdr->keyix & 0x3);
  1531. remove_meta_hdr:
  1532. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1533. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1534. "qdf_nbuf_pull_head failed");
  1535. qdf_nbuf_free(nbuf);
  1536. return NULL;
  1537. }
  1538. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1540. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1541. " tid %d to_fw %d",
  1542. __func__, msdu_info->meta_data[0],
  1543. msdu_info->meta_data[1],
  1544. msdu_info->meta_data[2],
  1545. msdu_info->meta_data[3],
  1546. msdu_info->meta_data[4],
  1547. msdu_info->meta_data[5],
  1548. msdu_info->tid, msdu_info->exception_fw);
  1549. return nbuf;
  1550. }
  1551. #else
  1552. static
  1553. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1554. struct dp_tx_msdu_info_s *msdu_info)
  1555. {
  1556. return nbuf;
  1557. }
  1558. #endif
  1559. #ifdef DP_FEATURE_NAWDS_TX
  1560. /**
  1561. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1562. * @vdev: dp_vdev handle
  1563. * @nbuf: skb
  1564. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1565. * @tx_q: Tx queue to be used for this Tx frame
  1566. * @meta_data: Meta date for mesh
  1567. * @peer_id: peer_id of the peer in case of NAWDS frames
  1568. *
  1569. * return: NULL on success nbuf on failure
  1570. */
  1571. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1572. struct dp_tx_msdu_info_s *msdu_info)
  1573. {
  1574. struct dp_peer *peer = NULL;
  1575. struct dp_soc *soc = vdev->pdev->soc;
  1576. struct dp_ast_entry *ast_entry = NULL;
  1577. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1578. uint16_t peer_id = HTT_INVALID_PEER;
  1579. struct dp_peer *sa_peer = NULL;
  1580. qdf_nbuf_t nbuf_copy;
  1581. qdf_spin_lock_bh(&(soc->ast_lock));
  1582. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1583. (soc,
  1584. (uint8_t *)(eh->ether_shost),
  1585. vdev->pdev->pdev_id);
  1586. if (ast_entry)
  1587. sa_peer = ast_entry->peer;
  1588. qdf_spin_unlock_bh(&(soc->ast_lock));
  1589. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1590. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1591. (peer->nawds_enabled)) {
  1592. if (sa_peer == peer) {
  1593. QDF_TRACE(QDF_MODULE_ID_DP,
  1594. QDF_TRACE_LEVEL_DEBUG,
  1595. " %s: broadcast multicast packet",
  1596. __func__);
  1597. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1598. continue;
  1599. }
  1600. nbuf_copy = qdf_nbuf_copy(nbuf);
  1601. if (!nbuf_copy) {
  1602. QDF_TRACE(QDF_MODULE_ID_DP,
  1603. QDF_TRACE_LEVEL_ERROR,
  1604. "nbuf copy failed");
  1605. }
  1606. peer_id = peer->peer_ids[0];
  1607. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1608. msdu_info, peer_id, NULL);
  1609. if (nbuf_copy != NULL) {
  1610. qdf_nbuf_free(nbuf_copy);
  1611. continue;
  1612. }
  1613. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1614. 1, qdf_nbuf_len(nbuf));
  1615. }
  1616. }
  1617. if (peer_id == HTT_INVALID_PEER)
  1618. return nbuf;
  1619. return NULL;
  1620. }
  1621. #endif
  1622. /**
  1623. * dp_check_exc_metadata() - Checks if parameters are valid
  1624. * @tx_exc - holds all exception path parameters
  1625. *
  1626. * Returns true when all the parameters are valid else false
  1627. *
  1628. */
  1629. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1630. {
  1631. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1632. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1633. tx_exc->sec_type > cdp_num_sec_types) {
  1634. return false;
  1635. }
  1636. return true;
  1637. }
  1638. /**
  1639. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1640. * @vap_dev: DP vdev handle
  1641. * @nbuf: skb
  1642. * @tx_exc_metadata: Handle that holds exception path meta data
  1643. *
  1644. * Entry point for Core Tx layer (DP_TX) invoked from
  1645. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1646. *
  1647. * Return: NULL on success,
  1648. * nbuf when it fails to send
  1649. */
  1650. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1651. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1652. {
  1653. qdf_ether_header_t *eh = NULL;
  1654. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1655. struct dp_tx_msdu_info_s msdu_info;
  1656. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1657. msdu_info.tid = tx_exc_metadata->tid;
  1658. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1659. dp_verbose_debug("skb %pM", nbuf->data);
  1660. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1661. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1663. "Invalid parameters in exception path");
  1664. goto fail;
  1665. }
  1666. /* Basic sanity checks for unsupported packets */
  1667. /* MESH mode */
  1668. if (qdf_unlikely(vdev->mesh_vdev)) {
  1669. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1670. "Mesh mode is not supported in exception path");
  1671. goto fail;
  1672. }
  1673. /* TSO or SG */
  1674. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1675. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1676. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1677. "TSO and SG are not supported in exception path");
  1678. goto fail;
  1679. }
  1680. /* RAW */
  1681. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1682. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1683. "Raw frame is not supported in exception path");
  1684. goto fail;
  1685. }
  1686. /* Mcast enhancement*/
  1687. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1688. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1689. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1690. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1691. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1692. }
  1693. }
  1694. /*
  1695. * Get HW Queue to use for this frame.
  1696. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1697. * dedicated for data and 1 for command.
  1698. * "queue_id" maps to one hardware ring.
  1699. * With each ring, we also associate a unique Tx descriptor pool
  1700. * to minimize lock contention for these resources.
  1701. */
  1702. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1703. /* Single linear frame */
  1704. /*
  1705. * If nbuf is a simple linear frame, use send_single function to
  1706. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1707. * SRNG. There is no need to setup a MSDU extension descriptor.
  1708. */
  1709. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1710. tx_exc_metadata->peer_id, tx_exc_metadata);
  1711. return nbuf;
  1712. fail:
  1713. dp_verbose_debug("pkt send failed");
  1714. return nbuf;
  1715. }
  1716. /**
  1717. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1718. * @vap_dev: DP vdev handle
  1719. * @nbuf: skb
  1720. *
  1721. * Entry point for Core Tx layer (DP_TX) invoked from
  1722. * hard_start_xmit in OSIF/HDD
  1723. *
  1724. * Return: NULL on success,
  1725. * nbuf when it fails to send
  1726. */
  1727. #ifdef MESH_MODE_SUPPORT
  1728. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1729. {
  1730. struct meta_hdr_s *mhdr;
  1731. qdf_nbuf_t nbuf_mesh = NULL;
  1732. qdf_nbuf_t nbuf_clone = NULL;
  1733. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1734. uint8_t no_enc_frame = 0;
  1735. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1736. if (nbuf_mesh == NULL) {
  1737. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1738. "qdf_nbuf_unshare failed");
  1739. return nbuf;
  1740. }
  1741. nbuf = nbuf_mesh;
  1742. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1743. if ((vdev->sec_type != cdp_sec_type_none) &&
  1744. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1745. no_enc_frame = 1;
  1746. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1747. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1748. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1749. !no_enc_frame) {
  1750. nbuf_clone = qdf_nbuf_clone(nbuf);
  1751. if (nbuf_clone == NULL) {
  1752. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1753. "qdf_nbuf_clone failed");
  1754. return nbuf;
  1755. }
  1756. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1757. }
  1758. if (nbuf_clone) {
  1759. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1760. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1761. } else {
  1762. qdf_nbuf_free(nbuf_clone);
  1763. }
  1764. }
  1765. if (no_enc_frame)
  1766. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1767. else
  1768. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1769. nbuf = dp_tx_send(vap_dev, nbuf);
  1770. if ((nbuf == NULL) && no_enc_frame) {
  1771. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1772. }
  1773. return nbuf;
  1774. }
  1775. #else
  1776. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1777. {
  1778. return dp_tx_send(vap_dev, nbuf);
  1779. }
  1780. #endif
  1781. /**
  1782. * dp_tx_send() - Transmit a frame on a given VAP
  1783. * @vap_dev: DP vdev handle
  1784. * @nbuf: skb
  1785. *
  1786. * Entry point for Core Tx layer (DP_TX) invoked from
  1787. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1788. * cases
  1789. *
  1790. * Return: NULL on success,
  1791. * nbuf when it fails to send
  1792. */
  1793. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1794. {
  1795. qdf_ether_header_t *eh = NULL;
  1796. struct dp_tx_msdu_info_s msdu_info;
  1797. struct dp_tx_seg_info_s seg_info;
  1798. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1799. uint16_t peer_id = HTT_INVALID_PEER;
  1800. qdf_nbuf_t nbuf_mesh = NULL;
  1801. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1802. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1803. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1804. dp_verbose_debug("skb %pM", nbuf->data);
  1805. /*
  1806. * Set Default Host TID value to invalid TID
  1807. * (TID override disabled)
  1808. */
  1809. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1810. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1811. if (qdf_unlikely(vdev->mesh_vdev)) {
  1812. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1813. &msdu_info);
  1814. if (nbuf_mesh == NULL) {
  1815. dp_verbose_debug("Extracting mesh metadata failed");
  1816. return nbuf;
  1817. }
  1818. nbuf = nbuf_mesh;
  1819. }
  1820. /*
  1821. * Get HW Queue to use for this frame.
  1822. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1823. * dedicated for data and 1 for command.
  1824. * "queue_id" maps to one hardware ring.
  1825. * With each ring, we also associate a unique Tx descriptor pool
  1826. * to minimize lock contention for these resources.
  1827. */
  1828. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1829. /*
  1830. * TCL H/W supports 2 DSCP-TID mapping tables.
  1831. * Table 1 - Default DSCP-TID mapping table
  1832. * Table 2 - 1 DSCP-TID override table
  1833. *
  1834. * If we need a different DSCP-TID mapping for this vap,
  1835. * call tid_classify to extract DSCP/ToS from frame and
  1836. * map to a TID and store in msdu_info. This is later used
  1837. * to fill in TCL Input descriptor (per-packet TID override).
  1838. */
  1839. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1840. /*
  1841. * Classify the frame and call corresponding
  1842. * "prepare" function which extracts the segment (TSO)
  1843. * and fragmentation information (for TSO , SG, ME, or Raw)
  1844. * into MSDU_INFO structure which is later used to fill
  1845. * SW and HW descriptors.
  1846. */
  1847. if (qdf_nbuf_is_tso(nbuf)) {
  1848. dp_verbose_debug("TSO frame %pK", vdev);
  1849. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1850. qdf_nbuf_len(nbuf));
  1851. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1852. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1853. qdf_nbuf_len(nbuf));
  1854. return nbuf;
  1855. }
  1856. goto send_multiple;
  1857. }
  1858. /* SG */
  1859. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1860. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1861. if (!nbuf)
  1862. return NULL;
  1863. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1864. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1865. qdf_nbuf_len(nbuf));
  1866. goto send_multiple;
  1867. }
  1868. #ifdef ATH_SUPPORT_IQUE
  1869. /* Mcast to Ucast Conversion*/
  1870. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1871. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1872. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1873. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1874. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1875. DP_STATS_INC_PKT(vdev,
  1876. tx_i.mcast_en.mcast_pkt, 1,
  1877. qdf_nbuf_len(nbuf));
  1878. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1879. QDF_STATUS_SUCCESS) {
  1880. return NULL;
  1881. }
  1882. }
  1883. }
  1884. #endif
  1885. /* RAW */
  1886. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1887. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1888. if (nbuf == NULL)
  1889. return NULL;
  1890. dp_verbose_debug("Raw frame %pK", vdev);
  1891. goto send_multiple;
  1892. }
  1893. /* Single linear frame */
  1894. /*
  1895. * If nbuf is a simple linear frame, use send_single function to
  1896. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1897. * SRNG. There is no need to setup a MSDU extension descriptor.
  1898. */
  1899. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1900. return nbuf;
  1901. send_multiple:
  1902. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1903. return nbuf;
  1904. }
  1905. /**
  1906. * dp_tx_reinject_handler() - Tx Reinject Handler
  1907. * @tx_desc: software descriptor head pointer
  1908. * @status : Tx completion status from HTT descriptor
  1909. *
  1910. * This function reinjects frames back to Target.
  1911. * Todo - Host queue needs to be added
  1912. *
  1913. * Return: none
  1914. */
  1915. static
  1916. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1917. {
  1918. struct dp_vdev *vdev;
  1919. struct dp_peer *peer = NULL;
  1920. uint32_t peer_id = HTT_INVALID_PEER;
  1921. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1922. qdf_nbuf_t nbuf_copy = NULL;
  1923. struct dp_tx_msdu_info_s msdu_info;
  1924. struct dp_peer *sa_peer = NULL;
  1925. struct dp_ast_entry *ast_entry = NULL;
  1926. struct dp_soc *soc = NULL;
  1927. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1928. #ifdef WDS_VENDOR_EXTENSION
  1929. int is_mcast = 0, is_ucast = 0;
  1930. int num_peers_3addr = 0;
  1931. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1932. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1933. #endif
  1934. vdev = tx_desc->vdev;
  1935. soc = vdev->pdev->soc;
  1936. qdf_assert(vdev);
  1937. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1938. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1939. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1940. "%s Tx reinject path", __func__);
  1941. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1942. qdf_nbuf_len(tx_desc->nbuf));
  1943. qdf_spin_lock_bh(&(soc->ast_lock));
  1944. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1945. (soc,
  1946. (uint8_t *)(eh->ether_shost),
  1947. vdev->pdev->pdev_id);
  1948. if (ast_entry)
  1949. sa_peer = ast_entry->peer;
  1950. qdf_spin_unlock_bh(&(soc->ast_lock));
  1951. #ifdef WDS_VENDOR_EXTENSION
  1952. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1953. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1954. } else {
  1955. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1956. }
  1957. is_ucast = !is_mcast;
  1958. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1959. if (peer->bss_peer)
  1960. continue;
  1961. /* Detect wds peers that use 3-addr framing for mcast.
  1962. * if there are any, the bss_peer is used to send the
  1963. * the mcast frame using 3-addr format. all wds enabled
  1964. * peers that use 4-addr framing for mcast frames will
  1965. * be duplicated and sent as 4-addr frames below.
  1966. */
  1967. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1968. num_peers_3addr = 1;
  1969. break;
  1970. }
  1971. }
  1972. #endif
  1973. if (qdf_unlikely(vdev->mesh_vdev)) {
  1974. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1975. } else {
  1976. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1977. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1978. #ifdef WDS_VENDOR_EXTENSION
  1979. /*
  1980. * . if 3-addr STA, then send on BSS Peer
  1981. * . if Peer WDS enabled and accept 4-addr mcast,
  1982. * send mcast on that peer only
  1983. * . if Peer WDS enabled and accept 4-addr ucast,
  1984. * send ucast on that peer only
  1985. */
  1986. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1987. (peer->wds_enabled &&
  1988. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1989. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1990. #else
  1991. ((peer->bss_peer &&
  1992. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1993. peer->nawds_enabled)) {
  1994. #endif
  1995. peer_id = DP_INVALID_PEER;
  1996. if (peer->nawds_enabled) {
  1997. peer_id = peer->peer_ids[0];
  1998. if (sa_peer == peer) {
  1999. QDF_TRACE(
  2000. QDF_MODULE_ID_DP,
  2001. QDF_TRACE_LEVEL_DEBUG,
  2002. " %s: multicast packet",
  2003. __func__);
  2004. DP_STATS_INC(peer,
  2005. tx.nawds_mcast_drop, 1);
  2006. continue;
  2007. }
  2008. }
  2009. nbuf_copy = qdf_nbuf_copy(nbuf);
  2010. if (!nbuf_copy) {
  2011. QDF_TRACE(QDF_MODULE_ID_DP,
  2012. QDF_TRACE_LEVEL_DEBUG,
  2013. FL("nbuf copy failed"));
  2014. break;
  2015. }
  2016. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2017. nbuf_copy,
  2018. &msdu_info,
  2019. peer_id,
  2020. NULL);
  2021. if (nbuf_copy) {
  2022. QDF_TRACE(QDF_MODULE_ID_DP,
  2023. QDF_TRACE_LEVEL_DEBUG,
  2024. FL("pkt send failed"));
  2025. qdf_nbuf_free(nbuf_copy);
  2026. } else {
  2027. if (peer_id != DP_INVALID_PEER)
  2028. DP_STATS_INC_PKT(peer,
  2029. tx.nawds_mcast,
  2030. 1, qdf_nbuf_len(nbuf));
  2031. }
  2032. }
  2033. }
  2034. }
  2035. if (vdev->nawds_enabled) {
  2036. peer_id = DP_INVALID_PEER;
  2037. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2038. 1, qdf_nbuf_len(nbuf));
  2039. nbuf = dp_tx_send_msdu_single(vdev,
  2040. nbuf,
  2041. &msdu_info,
  2042. peer_id, NULL);
  2043. if (nbuf) {
  2044. QDF_TRACE(QDF_MODULE_ID_DP,
  2045. QDF_TRACE_LEVEL_DEBUG,
  2046. FL("pkt send failed"));
  2047. qdf_nbuf_free(nbuf);
  2048. }
  2049. } else
  2050. qdf_nbuf_free(nbuf);
  2051. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2052. }
  2053. /**
  2054. * dp_tx_inspect_handler() - Tx Inspect Handler
  2055. * @tx_desc: software descriptor head pointer
  2056. * @status : Tx completion status from HTT descriptor
  2057. *
  2058. * Handles Tx frames sent back to Host for inspection
  2059. * (ProxyARP)
  2060. *
  2061. * Return: none
  2062. */
  2063. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2064. {
  2065. struct dp_soc *soc;
  2066. struct dp_pdev *pdev = tx_desc->pdev;
  2067. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2068. "%s Tx inspect path",
  2069. __func__);
  2070. qdf_assert(pdev);
  2071. soc = pdev->soc;
  2072. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2073. qdf_nbuf_len(tx_desc->nbuf));
  2074. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2075. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2076. }
  2077. #ifdef FEATURE_PERPKT_INFO
  2078. /**
  2079. * dp_get_completion_indication_for_stack() - send completion to stack
  2080. * @soc : dp_soc handle
  2081. * @pdev: dp_pdev handle
  2082. * @peer: dp peer handle
  2083. * @ts: transmit completion status structure
  2084. * @netbuf: Buffer pointer for free
  2085. *
  2086. * This function is used for indication whether buffer needs to be
  2087. * sent to stack for freeing or not
  2088. */
  2089. QDF_STATUS
  2090. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2091. struct dp_pdev *pdev,
  2092. struct dp_peer *peer,
  2093. struct hal_tx_completion_status *ts,
  2094. qdf_nbuf_t netbuf,
  2095. uint64_t time_latency)
  2096. {
  2097. struct tx_capture_hdr *ppdu_hdr;
  2098. uint16_t peer_id = ts->peer_id;
  2099. uint32_t ppdu_id = ts->ppdu_id;
  2100. uint8_t first_msdu = ts->first_msdu;
  2101. uint8_t last_msdu = ts->last_msdu;
  2102. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2103. !pdev->latency_capture_enable))
  2104. return QDF_STATUS_E_NOSUPPORT;
  2105. if (!peer) {
  2106. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2107. FL("Peer Invalid"));
  2108. return QDF_STATUS_E_INVAL;
  2109. }
  2110. if (pdev->mcopy_mode) {
  2111. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2112. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2113. return QDF_STATUS_E_INVAL;
  2114. }
  2115. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2116. pdev->m_copy_id.tx_peer_id = peer_id;
  2117. }
  2118. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2120. FL("No headroom"));
  2121. return QDF_STATUS_E_NOMEM;
  2122. }
  2123. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2124. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2125. IEEE80211_ADDR_LEN);
  2126. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2127. IEEE80211_ADDR_LEN);
  2128. ppdu_hdr->ppdu_id = ppdu_id;
  2129. ppdu_hdr->peer_id = peer_id;
  2130. ppdu_hdr->first_msdu = first_msdu;
  2131. ppdu_hdr->last_msdu = last_msdu;
  2132. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2133. ppdu_hdr->tsf = ts->tsf;
  2134. ppdu_hdr->time_latency = time_latency;
  2135. }
  2136. return QDF_STATUS_SUCCESS;
  2137. }
  2138. /**
  2139. * dp_send_completion_to_stack() - send completion to stack
  2140. * @soc : dp_soc handle
  2141. * @pdev: dp_pdev handle
  2142. * @peer_id: peer_id of the peer for which completion came
  2143. * @ppdu_id: ppdu_id
  2144. * @netbuf: Buffer pointer for free
  2145. *
  2146. * This function is used to send completion to stack
  2147. * to free buffer
  2148. */
  2149. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2150. uint16_t peer_id, uint32_t ppdu_id,
  2151. qdf_nbuf_t netbuf)
  2152. {
  2153. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2154. netbuf, peer_id,
  2155. WDI_NO_VAL, pdev->pdev_id);
  2156. }
  2157. #else
  2158. static QDF_STATUS
  2159. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2160. struct dp_pdev *pdev,
  2161. struct dp_peer *peer,
  2162. struct hal_tx_completion_status *ts,
  2163. qdf_nbuf_t netbuf,
  2164. uint64_t time_latency)
  2165. {
  2166. return QDF_STATUS_E_NOSUPPORT;
  2167. }
  2168. static void
  2169. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2170. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2171. {
  2172. }
  2173. #endif
  2174. /**
  2175. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2176. * @soc: Soc handle
  2177. * @desc: software Tx descriptor to be processed
  2178. *
  2179. * Return: none
  2180. */
  2181. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2182. struct dp_tx_desc_s *desc)
  2183. {
  2184. struct dp_vdev *vdev = desc->vdev;
  2185. qdf_nbuf_t nbuf = desc->nbuf;
  2186. /* If it is TDLS mgmt, don't unmap or free the frame */
  2187. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2188. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2189. /* 0 : MSDU buffer, 1 : MLE */
  2190. if (desc->msdu_ext_desc) {
  2191. /* TSO free */
  2192. if (hal_tx_ext_desc_get_tso_enable(
  2193. desc->msdu_ext_desc->vaddr)) {
  2194. /* unmap eash TSO seg before free the nbuf */
  2195. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2196. desc->tso_num_desc);
  2197. qdf_nbuf_free(nbuf);
  2198. return;
  2199. }
  2200. }
  2201. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2202. if (qdf_likely(!vdev->mesh_vdev))
  2203. qdf_nbuf_free(nbuf);
  2204. else {
  2205. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2206. qdf_nbuf_free(nbuf);
  2207. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2208. } else
  2209. vdev->osif_tx_free_ext((nbuf));
  2210. }
  2211. }
  2212. /**
  2213. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2214. * @vdev: pointer to dp dev handler
  2215. * @status : Tx completion status from HTT descriptor
  2216. *
  2217. * Handles MEC notify event sent from fw to Host
  2218. *
  2219. * Return: none
  2220. */
  2221. #ifdef FEATURE_WDS
  2222. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2223. {
  2224. struct dp_soc *soc;
  2225. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2226. struct dp_peer *peer;
  2227. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2228. if (!vdev->mec_enabled)
  2229. return;
  2230. /* MEC required only in STA mode */
  2231. if (vdev->opmode != wlan_op_mode_sta)
  2232. return;
  2233. soc = vdev->pdev->soc;
  2234. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2235. peer = TAILQ_FIRST(&vdev->peer_list);
  2236. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2237. if (!peer) {
  2238. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2239. FL("peer is NULL"));
  2240. return;
  2241. }
  2242. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2243. "%s Tx MEC Handler",
  2244. __func__);
  2245. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2246. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2247. status[(DP_MAC_ADDR_LEN - 2) + i];
  2248. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2249. dp_peer_add_ast(soc,
  2250. peer,
  2251. mac_addr,
  2252. CDP_TXRX_AST_TYPE_MEC,
  2253. flags);
  2254. }
  2255. #endif
  2256. #ifdef MESH_MODE_SUPPORT
  2257. /**
  2258. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2259. * in mesh meta header
  2260. * @tx_desc: software descriptor head pointer
  2261. * @ts: pointer to tx completion stats
  2262. * Return: none
  2263. */
  2264. static
  2265. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2266. struct hal_tx_completion_status *ts)
  2267. {
  2268. struct meta_hdr_s *mhdr;
  2269. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2270. if (!tx_desc->msdu_ext_desc) {
  2271. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2272. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2273. "netbuf %pK offset %d",
  2274. netbuf, tx_desc->pkt_offset);
  2275. return;
  2276. }
  2277. }
  2278. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2279. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2280. "netbuf %pK offset %lu", netbuf,
  2281. sizeof(struct meta_hdr_s));
  2282. return;
  2283. }
  2284. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2285. mhdr->rssi = ts->ack_frame_rssi;
  2286. mhdr->channel = tx_desc->pdev->operating_channel;
  2287. }
  2288. #else
  2289. static
  2290. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2291. struct hal_tx_completion_status *ts)
  2292. {
  2293. }
  2294. #endif
  2295. /**
  2296. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2297. * @peer: Handle to DP peer
  2298. * @ts: pointer to HAL Tx completion stats
  2299. *
  2300. * Return: None
  2301. */
  2302. static inline void
  2303. dp_tx_update_peer_stats(struct dp_peer *peer,
  2304. struct hal_tx_completion_status *ts, uint32_t length)
  2305. {
  2306. struct dp_pdev *pdev = peer->vdev->pdev;
  2307. struct dp_soc *soc = NULL;
  2308. uint8_t mcs, pkt_type;
  2309. uint8_t tid = ts->tid;
  2310. struct cdp_tid_tx_stats *tid_stats;
  2311. if (!pdev)
  2312. return;
  2313. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2314. tid = CDP_MAX_DATA_TIDS - 1;
  2315. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2316. soc = pdev->soc;
  2317. mcs = ts->mcs;
  2318. pkt_type = ts->pkt_type;
  2319. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2320. dp_err("Release source is not from TQM");
  2321. return;
  2322. }
  2323. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2324. tid_stats->complete_cnt++;
  2325. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2326. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2327. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2328. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2329. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2330. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2331. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2332. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2333. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2334. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2335. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2336. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2337. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2338. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2339. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2340. tid_stats->comp_fail_cnt++;
  2341. return;
  2342. }
  2343. tid_stats->success_cnt++;
  2344. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2345. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2346. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2347. /*
  2348. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2349. * Return from here if HTT PPDU events are enabled.
  2350. */
  2351. if (!(soc->process_tx_status))
  2352. return;
  2353. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2354. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2355. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2356. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2357. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2358. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2359. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2360. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2361. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2362. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2363. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2364. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2365. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2366. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2367. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2368. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2369. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2370. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2371. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2372. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2373. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2374. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2375. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2376. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2377. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2378. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2379. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2380. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2381. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2382. &peer->stats, ts->peer_id,
  2383. UPDATE_PEER_STATS, pdev->pdev_id);
  2384. #endif
  2385. }
  2386. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2387. /**
  2388. * dp_tx_flow_pool_lock() - take flow pool lock
  2389. * @soc: core txrx main context
  2390. * @tx_desc: tx desc
  2391. *
  2392. * Return: None
  2393. */
  2394. static inline
  2395. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2396. struct dp_tx_desc_s *tx_desc)
  2397. {
  2398. struct dp_tx_desc_pool_s *pool;
  2399. uint8_t desc_pool_id;
  2400. desc_pool_id = tx_desc->pool_id;
  2401. pool = &soc->tx_desc[desc_pool_id];
  2402. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2403. }
  2404. /**
  2405. * dp_tx_flow_pool_unlock() - release flow pool lock
  2406. * @soc: core txrx main context
  2407. * @tx_desc: tx desc
  2408. *
  2409. * Return: None
  2410. */
  2411. static inline
  2412. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2413. struct dp_tx_desc_s *tx_desc)
  2414. {
  2415. struct dp_tx_desc_pool_s *pool;
  2416. uint8_t desc_pool_id;
  2417. desc_pool_id = tx_desc->pool_id;
  2418. pool = &soc->tx_desc[desc_pool_id];
  2419. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2420. }
  2421. #else
  2422. static inline
  2423. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2424. {
  2425. }
  2426. static inline
  2427. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2428. {
  2429. }
  2430. #endif
  2431. /**
  2432. * dp_tx_notify_completion() - Notify tx completion for this desc
  2433. * @soc: core txrx main context
  2434. * @tx_desc: tx desc
  2435. * @netbuf: buffer
  2436. *
  2437. * Return: none
  2438. */
  2439. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2440. struct dp_tx_desc_s *tx_desc,
  2441. qdf_nbuf_t netbuf)
  2442. {
  2443. void *osif_dev;
  2444. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2445. qdf_assert(tx_desc);
  2446. dp_tx_flow_pool_lock(soc, tx_desc);
  2447. if (!tx_desc->vdev ||
  2448. !tx_desc->vdev->osif_vdev) {
  2449. dp_tx_flow_pool_unlock(soc, tx_desc);
  2450. return;
  2451. }
  2452. osif_dev = tx_desc->vdev->osif_vdev;
  2453. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2454. dp_tx_flow_pool_unlock(soc, tx_desc);
  2455. if (tx_compl_cbk)
  2456. tx_compl_cbk(netbuf, osif_dev);
  2457. }
  2458. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2459. * @pdev: pdev handle
  2460. * @tid: tid value
  2461. * @txdesc_ts: timestamp from txdesc
  2462. * @ppdu_id: ppdu id
  2463. *
  2464. * Return: none
  2465. */
  2466. #ifdef FEATURE_PERPKT_INFO
  2467. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2468. uint8_t tid,
  2469. uint64_t txdesc_ts,
  2470. uint32_t ppdu_id)
  2471. {
  2472. uint64_t delta_ms;
  2473. struct cdp_tx_sojourn_stats *sojourn_stats;
  2474. if (pdev->enhanced_stats_en == 0)
  2475. return;
  2476. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2477. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2478. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2479. if (!pdev->sojourn_buf)
  2480. return;
  2481. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2482. qdf_nbuf_data(pdev->sojourn_buf);
  2483. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2484. sizeof(struct cdp_tx_sojourn_stats));
  2485. qdf_mem_zero(&pdev->sojourn_stats,
  2486. sizeof(struct cdp_tx_sojourn_stats));
  2487. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2488. pdev->sojourn_buf, HTT_INVALID_PEER,
  2489. WDI_NO_VAL, pdev->pdev_id);
  2490. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2491. }
  2492. if (tid == HTT_INVALID_TID)
  2493. return;
  2494. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2495. txdesc_ts;
  2496. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2497. delta_ms);
  2498. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2499. pdev->sojourn_stats.num_msdus[tid]++;
  2500. }
  2501. #else
  2502. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2503. uint8_t tid,
  2504. uint64_t txdesc_ts,
  2505. uint32_t ppdu_id)
  2506. {
  2507. }
  2508. #endif
  2509. /**
  2510. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2511. * @soc: DP Soc handle
  2512. * @tx_desc: software Tx descriptor
  2513. * @ts : Tx completion status from HAL/HTT descriptor
  2514. *
  2515. * Return: none
  2516. */
  2517. static inline void
  2518. dp_tx_comp_process_desc(struct dp_soc *soc,
  2519. struct dp_tx_desc_s *desc,
  2520. struct hal_tx_completion_status *ts,
  2521. struct dp_peer *peer)
  2522. {
  2523. uint64_t time_latency = 0;
  2524. /*
  2525. * m_copy/tx_capture modes are not supported for
  2526. * scatter gather packets
  2527. */
  2528. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2529. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2530. desc->timestamp);
  2531. }
  2532. if (!(desc->msdu_ext_desc) &&
  2533. (dp_get_completion_indication_for_stack(soc, desc->pdev,
  2534. peer, ts, desc->nbuf,
  2535. time_latency)
  2536. == QDF_STATUS_SUCCESS)) {
  2537. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2538. QDF_DMA_TO_DEVICE);
  2539. dp_send_completion_to_stack(soc, desc->pdev, ts->peer_id,
  2540. ts->ppdu_id, desc->nbuf);
  2541. } else {
  2542. dp_tx_comp_free_buf(soc, desc);
  2543. }
  2544. }
  2545. /**
  2546. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2547. * @tx_desc: software descriptor head pointer
  2548. * @ts: Tx completion status
  2549. * @peer: peer handle
  2550. *
  2551. * Return: none
  2552. */
  2553. static inline
  2554. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2555. struct hal_tx_completion_status *ts,
  2556. struct dp_peer *peer)
  2557. {
  2558. uint32_t length;
  2559. struct dp_soc *soc = NULL;
  2560. struct dp_vdev *vdev = tx_desc->vdev;
  2561. qdf_ether_header_t *eh =
  2562. (qdf_ether_header_t *)qdf_nbuf_data(tx_desc->nbuf);
  2563. if (!vdev) {
  2564. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2565. "invalid vdev");
  2566. goto out;
  2567. }
  2568. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2569. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2570. QDF_TRACE_DEFAULT_PDEV_ID,
  2571. qdf_nbuf_data_addr(tx_desc->nbuf),
  2572. sizeof(qdf_nbuf_data(tx_desc->nbuf)),
  2573. tx_desc->id,
  2574. ts->status));
  2575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2576. "-------------------- \n"
  2577. "Tx Completion Stats: \n"
  2578. "-------------------- \n"
  2579. "ack_frame_rssi = %d \n"
  2580. "first_msdu = %d \n"
  2581. "last_msdu = %d \n"
  2582. "msdu_part_of_amsdu = %d \n"
  2583. "rate_stats valid = %d \n"
  2584. "bw = %d \n"
  2585. "pkt_type = %d \n"
  2586. "stbc = %d \n"
  2587. "ldpc = %d \n"
  2588. "sgi = %d \n"
  2589. "mcs = %d \n"
  2590. "ofdma = %d \n"
  2591. "tones_in_ru = %d \n"
  2592. "tsf = %d \n"
  2593. "ppdu_id = %d \n"
  2594. "transmit_cnt = %d \n"
  2595. "tid = %d \n"
  2596. "peer_id = %d\n",
  2597. ts->ack_frame_rssi, ts->first_msdu,
  2598. ts->last_msdu, ts->msdu_part_of_amsdu,
  2599. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2600. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2601. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2602. ts->transmit_cnt, ts->tid, ts->peer_id);
  2603. soc = vdev->pdev->soc;
  2604. /* Update SoC level stats */
  2605. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2606. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2607. /* Update per-packet stats for mesh mode */
  2608. if (qdf_unlikely(vdev->mesh_vdev) &&
  2609. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2610. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2611. length = qdf_nbuf_len(tx_desc->nbuf);
  2612. /* Update peer level stats */
  2613. if (!peer) {
  2614. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2615. "peer is null or deletion in progress");
  2616. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2617. goto out;
  2618. }
  2619. if (qdf_likely(!peer->bss_peer)) {
  2620. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2621. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2622. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2623. } else {
  2624. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2625. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2626. if ((peer->vdev->tx_encap_type ==
  2627. htt_cmn_pkt_type_ethernet) &&
  2628. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2629. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2630. }
  2631. }
  2632. }
  2633. dp_tx_update_peer_stats(peer, ts, length);
  2634. out:
  2635. return;
  2636. }
  2637. /**
  2638. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2639. * @soc: core txrx main context
  2640. * @comp_head: software descriptor head pointer
  2641. *
  2642. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2643. * and release the software descriptors after processing is complete
  2644. *
  2645. * Return: none
  2646. */
  2647. static void
  2648. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2649. struct dp_tx_desc_s *comp_head)
  2650. {
  2651. struct dp_tx_desc_s *desc;
  2652. struct dp_tx_desc_s *next;
  2653. struct hal_tx_completion_status ts = {0};
  2654. struct dp_peer *peer;
  2655. DP_HIST_INIT();
  2656. desc = comp_head;
  2657. while (desc) {
  2658. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2659. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2660. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2661. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2662. if (peer)
  2663. dp_peer_unref_del_find_by_id(peer);
  2664. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2665. next = desc->next;
  2666. dp_tx_desc_release(desc, desc->pool_id);
  2667. desc = next;
  2668. }
  2669. DP_TX_HIST_STATS_PER_PDEV();
  2670. }
  2671. /**
  2672. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2673. * @tx_desc: software descriptor head pointer
  2674. * @status : Tx completion status from HTT descriptor
  2675. *
  2676. * This function will process HTT Tx indication messages from Target
  2677. *
  2678. * Return: none
  2679. */
  2680. static
  2681. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2682. {
  2683. uint8_t tx_status;
  2684. struct dp_pdev *pdev;
  2685. struct dp_vdev *vdev;
  2686. struct dp_soc *soc;
  2687. struct hal_tx_completion_status ts = {0};
  2688. uint32_t *htt_desc = (uint32_t *)status;
  2689. struct dp_peer *peer;
  2690. struct cdp_tid_tx_stats *tid_stats = NULL;
  2691. qdf_assert(tx_desc->pdev);
  2692. pdev = tx_desc->pdev;
  2693. vdev = tx_desc->vdev;
  2694. soc = pdev->soc;
  2695. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2696. switch (tx_status) {
  2697. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2698. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2699. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2700. {
  2701. uint8_t tid;
  2702. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2703. ts.peer_id =
  2704. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2705. htt_desc[2]);
  2706. ts.tid =
  2707. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2708. htt_desc[2]);
  2709. } else {
  2710. ts.peer_id = HTT_INVALID_PEER;
  2711. ts.tid = HTT_INVALID_TID;
  2712. }
  2713. ts.ppdu_id =
  2714. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2715. htt_desc[1]);
  2716. ts.ack_frame_rssi =
  2717. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2718. htt_desc[1]);
  2719. ts.first_msdu = 1;
  2720. ts.last_msdu = 1;
  2721. tid = ts.tid;
  2722. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2723. tid = CDP_MAX_DATA_TIDS - 1;
  2724. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2725. tid_stats->complete_cnt++;
  2726. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2727. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2728. tid_stats->comp_fail_cnt++;
  2729. } else {
  2730. tid_stats->success_cnt++;
  2731. }
  2732. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2733. if (qdf_likely(peer))
  2734. dp_peer_unref_del_find_by_id(peer);
  2735. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2736. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2737. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2738. break;
  2739. }
  2740. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2741. {
  2742. dp_tx_reinject_handler(tx_desc, status);
  2743. break;
  2744. }
  2745. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2746. {
  2747. dp_tx_inspect_handler(tx_desc, status);
  2748. break;
  2749. }
  2750. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2751. {
  2752. dp_tx_mec_handler(vdev, status);
  2753. break;
  2754. }
  2755. default:
  2756. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2757. "%s Invalid HTT tx_status %d\n",
  2758. __func__, tx_status);
  2759. break;
  2760. }
  2761. }
  2762. /**
  2763. * dp_tx_comp_handler() - Tx completion handler
  2764. * @soc: core txrx main context
  2765. * @ring_id: completion ring id
  2766. * @quota: No. of packets/descriptors that can be serviced in one loop
  2767. *
  2768. * This function will collect hardware release ring element contents and
  2769. * handle descriptor contents. Based on contents, free packet or handle error
  2770. * conditions
  2771. *
  2772. * Return: none
  2773. */
  2774. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2775. {
  2776. void *tx_comp_hal_desc;
  2777. uint8_t buffer_src;
  2778. uint8_t pool_id;
  2779. uint32_t tx_desc_id;
  2780. struct dp_tx_desc_s *tx_desc = NULL;
  2781. struct dp_tx_desc_s *head_desc = NULL;
  2782. struct dp_tx_desc_s *tail_desc = NULL;
  2783. uint32_t num_processed;
  2784. uint32_t count;
  2785. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2786. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2787. "%s %d : HAL RING Access Failed -- %pK",
  2788. __func__, __LINE__, hal_srng);
  2789. return 0;
  2790. }
  2791. num_processed = 0;
  2792. count = 0;
  2793. /* Find head descriptor from completion ring */
  2794. while (qdf_likely(tx_comp_hal_desc =
  2795. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2796. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2797. /* If this buffer was not released by TQM or FW, then it is not
  2798. * Tx completion indication, assert */
  2799. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2800. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2801. QDF_TRACE(QDF_MODULE_ID_DP,
  2802. QDF_TRACE_LEVEL_FATAL,
  2803. "Tx comp release_src != TQM | FW");
  2804. qdf_assert_always(0);
  2805. }
  2806. /* Get descriptor id */
  2807. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2808. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2809. DP_TX_DESC_ID_POOL_OS;
  2810. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2811. continue;
  2812. /* Find Tx descriptor */
  2813. tx_desc = dp_tx_desc_find(soc, pool_id,
  2814. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2815. DP_TX_DESC_ID_PAGE_OS,
  2816. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2817. DP_TX_DESC_ID_OFFSET_OS);
  2818. /*
  2819. * If the descriptor is already freed in vdev_detach,
  2820. * continue to next descriptor
  2821. */
  2822. if (!tx_desc->vdev) {
  2823. QDF_TRACE(QDF_MODULE_ID_DP,
  2824. QDF_TRACE_LEVEL_INFO,
  2825. "Descriptor freed in vdev_detach %d",
  2826. tx_desc_id);
  2827. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2828. count++;
  2829. continue;
  2830. }
  2831. /*
  2832. * If the release source is FW, process the HTT status
  2833. */
  2834. if (qdf_unlikely(buffer_src ==
  2835. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2836. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2837. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2838. htt_tx_status);
  2839. dp_tx_process_htt_completion(tx_desc,
  2840. htt_tx_status);
  2841. } else {
  2842. /* Pool id is not matching. Error */
  2843. if (tx_desc->pool_id != pool_id) {
  2844. QDF_TRACE(QDF_MODULE_ID_DP,
  2845. QDF_TRACE_LEVEL_FATAL,
  2846. "Tx Comp pool id %d not matched %d",
  2847. pool_id, tx_desc->pool_id);
  2848. qdf_assert_always(0);
  2849. }
  2850. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2851. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2852. QDF_TRACE(QDF_MODULE_ID_DP,
  2853. QDF_TRACE_LEVEL_FATAL,
  2854. "Txdesc invalid, flgs = %x,id = %d",
  2855. tx_desc->flags, tx_desc_id);
  2856. qdf_assert_always(0);
  2857. }
  2858. /* First ring descriptor on the cycle */
  2859. if (!head_desc) {
  2860. head_desc = tx_desc;
  2861. tail_desc = tx_desc;
  2862. }
  2863. tail_desc->next = tx_desc;
  2864. tx_desc->next = NULL;
  2865. tail_desc = tx_desc;
  2866. /* Collect hw completion contents */
  2867. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2868. &tx_desc->comp, 1);
  2869. }
  2870. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2871. /*
  2872. * Processed packet count is more than given quota
  2873. * stop to processing
  2874. */
  2875. if ((num_processed >= quota))
  2876. break;
  2877. count++;
  2878. }
  2879. hal_srng_access_end(soc->hal_soc, hal_srng);
  2880. /* Process the reaped descriptors */
  2881. if (head_desc)
  2882. dp_tx_comp_process_desc_list(soc, head_desc);
  2883. return num_processed;
  2884. }
  2885. #ifdef FEATURE_WLAN_TDLS
  2886. /**
  2887. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2888. *
  2889. * @data_vdev - which vdev should transmit the tx data frames
  2890. * @tx_spec - what non-standard handling to apply to the tx data frames
  2891. * @msdu_list - NULL-terminated list of tx MSDUs
  2892. *
  2893. * Return: NULL on success,
  2894. * nbuf when it fails to send
  2895. */
  2896. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2897. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2898. {
  2899. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2900. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2901. vdev->is_tdls_frame = true;
  2902. return dp_tx_send(vdev_handle, msdu_list);
  2903. }
  2904. #endif
  2905. /**
  2906. * dp_tx_vdev_attach() - attach vdev to dp tx
  2907. * @vdev: virtual device instance
  2908. *
  2909. * Return: QDF_STATUS_SUCCESS: success
  2910. * QDF_STATUS_E_RESOURCES: Error return
  2911. */
  2912. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2913. {
  2914. /*
  2915. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2916. */
  2917. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2918. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2919. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2920. vdev->vdev_id);
  2921. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2922. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2923. /*
  2924. * Set HTT Extension Valid bit to 0 by default
  2925. */
  2926. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2927. dp_tx_vdev_update_search_flags(vdev);
  2928. return QDF_STATUS_SUCCESS;
  2929. }
  2930. #ifdef FEATURE_WDS
  2931. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2932. {
  2933. struct dp_soc *soc = vdev->pdev->soc;
  2934. /*
  2935. * If AST index override support is available (HKv2 etc),
  2936. * DA search flag be enabled always
  2937. *
  2938. * If AST index override support is not available (HKv1),
  2939. * DA search flag should be used for all modes except QWRAP
  2940. */
  2941. if (soc->ast_override_support || !vdev->proxysta_vdev)
  2942. return true;
  2943. return false;
  2944. }
  2945. #else
  2946. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2947. {
  2948. return false;
  2949. }
  2950. #endif
  2951. /**
  2952. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2953. * @vdev: virtual device instance
  2954. *
  2955. * Return: void
  2956. *
  2957. */
  2958. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2959. {
  2960. struct dp_soc *soc = vdev->pdev->soc;
  2961. /*
  2962. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2963. * for TDLS link
  2964. *
  2965. * Enable AddrY (SA based search) only for non-WDS STA and
  2966. * ProxySTA VAP (in HKv1) modes.
  2967. *
  2968. * In all other VAP modes, only DA based search should be
  2969. * enabled
  2970. */
  2971. if (vdev->opmode == wlan_op_mode_sta &&
  2972. vdev->tdls_link_connected)
  2973. vdev->hal_desc_addr_search_flags =
  2974. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2975. else if ((vdev->opmode == wlan_op_mode_sta) &&
  2976. !dp_tx_da_search_override(vdev))
  2977. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2978. else
  2979. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2980. /* Set search type only when peer map v2 messaging is enabled
  2981. * as we will have the search index (AST hash) only when v2 is
  2982. * enabled
  2983. */
  2984. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  2985. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  2986. else
  2987. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  2988. }
  2989. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2990. /* dp_tx_desc_flush() - release resources associated
  2991. * to tx_desc
  2992. * @vdev: virtual device instance
  2993. *
  2994. * This function will free all outstanding Tx buffers,
  2995. * including ME buffer for which either free during
  2996. * completion didn't happened or completion is not
  2997. * received.
  2998. */
  2999. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  3000. {
  3001. uint8_t i;
  3002. uint32_t j;
  3003. uint32_t num_desc, page_id, offset;
  3004. uint16_t num_desc_per_page;
  3005. struct dp_soc *soc = vdev->pdev->soc;
  3006. struct dp_tx_desc_s *tx_desc = NULL;
  3007. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3008. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3009. tx_desc_pool = &soc->tx_desc[i];
  3010. if (!(tx_desc_pool->pool_size) ||
  3011. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3012. !(tx_desc_pool->desc_pages.cacheable_pages))
  3013. continue;
  3014. num_desc = tx_desc_pool->pool_size;
  3015. num_desc_per_page =
  3016. tx_desc_pool->desc_pages.num_element_per_page;
  3017. for (j = 0; j < num_desc; j++) {
  3018. page_id = j / num_desc_per_page;
  3019. offset = j % num_desc_per_page;
  3020. if (qdf_unlikely(!(tx_desc_pool->
  3021. desc_pages.cacheable_pages)))
  3022. break;
  3023. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3024. if (tx_desc && (tx_desc->vdev == vdev) &&
  3025. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  3026. dp_tx_comp_free_buf(soc, tx_desc);
  3027. dp_tx_desc_release(tx_desc, i);
  3028. }
  3029. }
  3030. }
  3031. }
  3032. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3033. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  3034. {
  3035. uint8_t i, num_pool;
  3036. uint32_t j;
  3037. uint32_t num_desc, page_id, offset;
  3038. uint16_t num_desc_per_page;
  3039. struct dp_soc *soc = vdev->pdev->soc;
  3040. struct dp_tx_desc_s *tx_desc = NULL;
  3041. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3042. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3043. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3044. for (i = 0; i < num_pool; i++) {
  3045. tx_desc_pool = &soc->tx_desc[i];
  3046. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3047. continue;
  3048. num_desc_per_page =
  3049. tx_desc_pool->desc_pages.num_element_per_page;
  3050. for (j = 0; j < num_desc; j++) {
  3051. page_id = j / num_desc_per_page;
  3052. offset = j % num_desc_per_page;
  3053. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3054. if (tx_desc && (tx_desc->vdev == vdev) &&
  3055. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  3056. dp_tx_comp_free_buf(soc, tx_desc);
  3057. dp_tx_desc_release(tx_desc, i);
  3058. }
  3059. }
  3060. }
  3061. }
  3062. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3063. /**
  3064. * dp_tx_vdev_detach() - detach vdev from dp tx
  3065. * @vdev: virtual device instance
  3066. *
  3067. * Return: QDF_STATUS_SUCCESS: success
  3068. * QDF_STATUS_E_RESOURCES: Error return
  3069. */
  3070. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3071. {
  3072. dp_tx_desc_flush(vdev);
  3073. return QDF_STATUS_SUCCESS;
  3074. }
  3075. /**
  3076. * dp_tx_pdev_attach() - attach pdev to dp tx
  3077. * @pdev: physical device instance
  3078. *
  3079. * Return: QDF_STATUS_SUCCESS: success
  3080. * QDF_STATUS_E_RESOURCES: Error return
  3081. */
  3082. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3083. {
  3084. struct dp_soc *soc = pdev->soc;
  3085. /* Initialize Flow control counters */
  3086. qdf_atomic_init(&pdev->num_tx_exception);
  3087. qdf_atomic_init(&pdev->num_tx_outstanding);
  3088. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3089. /* Initialize descriptors in TCL Ring */
  3090. hal_tx_init_data_ring(soc->hal_soc,
  3091. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3092. }
  3093. return QDF_STATUS_SUCCESS;
  3094. }
  3095. /**
  3096. * dp_tx_pdev_detach() - detach pdev from dp tx
  3097. * @pdev: physical device instance
  3098. *
  3099. * Return: QDF_STATUS_SUCCESS: success
  3100. * QDF_STATUS_E_RESOURCES: Error return
  3101. */
  3102. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3103. {
  3104. dp_tx_me_exit(pdev);
  3105. return QDF_STATUS_SUCCESS;
  3106. }
  3107. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3108. /* Pools will be allocated dynamically */
  3109. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3110. int num_desc)
  3111. {
  3112. uint8_t i;
  3113. for (i = 0; i < num_pool; i++) {
  3114. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3115. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3116. }
  3117. return 0;
  3118. }
  3119. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3120. {
  3121. uint8_t i;
  3122. for (i = 0; i < num_pool; i++)
  3123. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3124. }
  3125. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3126. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3127. int num_desc)
  3128. {
  3129. uint8_t i;
  3130. /* Allocate software Tx descriptor pools */
  3131. for (i = 0; i < num_pool; i++) {
  3132. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3133. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3134. "%s Tx Desc Pool alloc %d failed %pK",
  3135. __func__, i, soc);
  3136. return ENOMEM;
  3137. }
  3138. }
  3139. return 0;
  3140. }
  3141. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3142. {
  3143. uint8_t i;
  3144. for (i = 0; i < num_pool; i++) {
  3145. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3146. if (dp_tx_desc_pool_free(soc, i)) {
  3147. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3148. "%s Tx Desc Pool Free failed", __func__);
  3149. }
  3150. }
  3151. }
  3152. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3153. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3154. /**
  3155. * dp_tso_attach_wifi3() - TSO attach handler
  3156. * @txrx_soc: Opaque Dp handle
  3157. *
  3158. * Reserve TSO descriptor buffers
  3159. *
  3160. * Return: QDF_STATUS_E_FAILURE on failure or
  3161. * QDF_STATUS_SUCCESS on success
  3162. */
  3163. static
  3164. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3165. {
  3166. return dp_tso_soc_attach(txrx_soc);
  3167. }
  3168. /**
  3169. * dp_tso_detach_wifi3() - TSO Detach handler
  3170. * @txrx_soc: Opaque Dp handle
  3171. *
  3172. * Deallocate TSO descriptor buffers
  3173. *
  3174. * Return: QDF_STATUS_E_FAILURE on failure or
  3175. * QDF_STATUS_SUCCESS on success
  3176. */
  3177. static
  3178. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3179. {
  3180. return dp_tso_soc_detach(txrx_soc);
  3181. }
  3182. #else
  3183. static
  3184. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3185. {
  3186. return QDF_STATUS_SUCCESS;
  3187. }
  3188. static
  3189. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3190. {
  3191. return QDF_STATUS_SUCCESS;
  3192. }
  3193. #endif
  3194. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3195. {
  3196. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3197. uint8_t i;
  3198. uint8_t num_pool;
  3199. uint32_t num_desc;
  3200. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3201. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3202. for (i = 0; i < num_pool; i++)
  3203. dp_tx_tso_desc_pool_free(soc, i);
  3204. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3205. __func__, num_pool, num_desc);
  3206. for (i = 0; i < num_pool; i++)
  3207. dp_tx_tso_num_seg_pool_free(soc, i);
  3208. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3209. __func__, num_pool, num_desc);
  3210. return QDF_STATUS_SUCCESS;
  3211. }
  3212. /**
  3213. * dp_tso_attach() - TSO attach handler
  3214. * @txrx_soc: Opaque Dp handle
  3215. *
  3216. * Reserve TSO descriptor buffers
  3217. *
  3218. * Return: QDF_STATUS_E_FAILURE on failure or
  3219. * QDF_STATUS_SUCCESS on success
  3220. */
  3221. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3222. {
  3223. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3224. uint8_t i;
  3225. uint8_t num_pool;
  3226. uint32_t num_desc;
  3227. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3228. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3229. for (i = 0; i < num_pool; i++) {
  3230. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3231. dp_err("TSO Desc Pool alloc %d failed %pK",
  3232. i, soc);
  3233. return QDF_STATUS_E_FAILURE;
  3234. }
  3235. }
  3236. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3237. __func__, num_pool, num_desc);
  3238. for (i = 0; i < num_pool; i++) {
  3239. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3240. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3241. i, soc);
  3242. return QDF_STATUS_E_FAILURE;
  3243. }
  3244. }
  3245. return QDF_STATUS_SUCCESS;
  3246. }
  3247. /**
  3248. * dp_tx_soc_detach() - detach soc from dp tx
  3249. * @soc: core txrx main context
  3250. *
  3251. * This function will detach dp tx into main device context
  3252. * will free dp tx resource and initialize resources
  3253. *
  3254. * Return: QDF_STATUS_SUCCESS: success
  3255. * QDF_STATUS_E_RESOURCES: Error return
  3256. */
  3257. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3258. {
  3259. uint8_t num_pool;
  3260. uint16_t num_desc;
  3261. uint16_t num_ext_desc;
  3262. uint8_t i;
  3263. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3264. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3265. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3266. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3267. dp_tx_flow_control_deinit(soc);
  3268. dp_tx_delete_static_pools(soc, num_pool);
  3269. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3270. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3271. __func__, num_pool, num_desc);
  3272. for (i = 0; i < num_pool; i++) {
  3273. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3274. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3275. "%s Tx Ext Desc Pool Free failed",
  3276. __func__);
  3277. return QDF_STATUS_E_RESOURCES;
  3278. }
  3279. }
  3280. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3281. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3282. __func__, num_pool, num_ext_desc);
  3283. status = dp_tso_detach_wifi3(soc);
  3284. if (status != QDF_STATUS_SUCCESS)
  3285. return status;
  3286. return QDF_STATUS_SUCCESS;
  3287. }
  3288. /**
  3289. * dp_tx_soc_attach() - attach soc to dp tx
  3290. * @soc: core txrx main context
  3291. *
  3292. * This function will attach dp tx into main device context
  3293. * will allocate dp tx resource and initialize resources
  3294. *
  3295. * Return: QDF_STATUS_SUCCESS: success
  3296. * QDF_STATUS_E_RESOURCES: Error return
  3297. */
  3298. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3299. {
  3300. uint8_t i;
  3301. uint8_t num_pool;
  3302. uint32_t num_desc;
  3303. uint32_t num_ext_desc;
  3304. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3305. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3306. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3307. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3308. if (num_pool > MAX_TXDESC_POOLS)
  3309. goto fail;
  3310. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3311. goto fail;
  3312. dp_tx_flow_control_init(soc);
  3313. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3314. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3315. __func__, num_pool, num_desc);
  3316. /* Allocate extension tx descriptor pools */
  3317. for (i = 0; i < num_pool; i++) {
  3318. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3319. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3320. "MSDU Ext Desc Pool alloc %d failed %pK",
  3321. i, soc);
  3322. goto fail;
  3323. }
  3324. }
  3325. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3326. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3327. __func__, num_pool, num_ext_desc);
  3328. status = dp_tso_attach_wifi3((void *)soc);
  3329. if (status != QDF_STATUS_SUCCESS)
  3330. goto fail;
  3331. /* Initialize descriptors in TCL Rings */
  3332. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3333. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3334. hal_tx_init_data_ring(soc->hal_soc,
  3335. soc->tcl_data_ring[i].hal_srng);
  3336. }
  3337. }
  3338. /*
  3339. * todo - Add a runtime config option to enable this.
  3340. */
  3341. /*
  3342. * Due to multiple issues on NPR EMU, enable it selectively
  3343. * only for NPR EMU, should be removed, once NPR platforms
  3344. * are stable.
  3345. */
  3346. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3347. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3348. "%s HAL Tx init Success", __func__);
  3349. return QDF_STATUS_SUCCESS;
  3350. fail:
  3351. /* Detach will take care of freeing only allocated resources */
  3352. dp_tx_soc_detach(soc);
  3353. return QDF_STATUS_E_RESOURCES;
  3354. }
  3355. /*
  3356. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3357. * pdev: pointer to DP PDEV structure
  3358. * seg_info_head: Pointer to the head of list
  3359. *
  3360. * return: void
  3361. */
  3362. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3363. struct dp_tx_seg_info_s *seg_info_head)
  3364. {
  3365. struct dp_tx_me_buf_t *mc_uc_buf;
  3366. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3367. qdf_nbuf_t nbuf = NULL;
  3368. uint64_t phy_addr;
  3369. while (seg_info_head) {
  3370. nbuf = seg_info_head->nbuf;
  3371. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3372. seg_info_head->frags[0].vaddr;
  3373. phy_addr = seg_info_head->frags[0].paddr_hi;
  3374. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3375. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3376. phy_addr,
  3377. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  3378. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3379. qdf_nbuf_free(nbuf);
  3380. seg_info_new = seg_info_head;
  3381. seg_info_head = seg_info_head->next;
  3382. qdf_mem_free(seg_info_new);
  3383. }
  3384. }
  3385. /**
  3386. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3387. * @vdev: DP VDEV handle
  3388. * @nbuf: Multicast nbuf
  3389. * @newmac: Table of the clients to which packets have to be sent
  3390. * @new_mac_cnt: No of clients
  3391. *
  3392. * return: no of converted packets
  3393. */
  3394. uint16_t
  3395. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3396. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3397. {
  3398. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3399. struct dp_pdev *pdev = vdev->pdev;
  3400. qdf_ether_header_t *eh;
  3401. uint8_t *data;
  3402. uint16_t len;
  3403. /* reference to frame dst addr */
  3404. uint8_t *dstmac;
  3405. /* copy of original frame src addr */
  3406. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3407. /* local index into newmac */
  3408. uint8_t new_mac_idx = 0;
  3409. struct dp_tx_me_buf_t *mc_uc_buf;
  3410. qdf_nbuf_t nbuf_clone;
  3411. struct dp_tx_msdu_info_s msdu_info;
  3412. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3413. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3414. struct dp_tx_seg_info_s *seg_info_new;
  3415. struct dp_tx_frag_info_s data_frag;
  3416. qdf_dma_addr_t paddr_data;
  3417. qdf_dma_addr_t paddr_mcbuf = 0;
  3418. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3419. QDF_STATUS status;
  3420. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3421. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3422. eh = (qdf_ether_header_t *)nbuf;
  3423. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3424. len = qdf_nbuf_len(nbuf);
  3425. data = qdf_nbuf_data(nbuf);
  3426. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3427. QDF_DMA_TO_DEVICE);
  3428. if (status) {
  3429. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3430. "Mapping failure Error:%d", status);
  3431. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3432. qdf_nbuf_free(nbuf);
  3433. return 1;
  3434. }
  3435. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3436. /*preparing data fragment*/
  3437. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3438. data_frag.paddr_lo = (uint32_t)paddr_data;
  3439. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3440. data_frag.len = len - DP_MAC_ADDR_LEN;
  3441. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3442. dstmac = newmac[new_mac_idx];
  3443. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3444. "added mac addr (%pM)", dstmac);
  3445. /* Check for NULL Mac Address */
  3446. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3447. continue;
  3448. /* frame to self mac. skip */
  3449. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3450. continue;
  3451. /*
  3452. * TODO: optimize to avoid malloc in per-packet path
  3453. * For eg. seg_pool can be made part of vdev structure
  3454. */
  3455. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3456. if (!seg_info_new) {
  3457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3458. "alloc failed");
  3459. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3460. goto fail_seg_alloc;
  3461. }
  3462. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3463. if (mc_uc_buf == NULL)
  3464. goto fail_buf_alloc;
  3465. /*
  3466. * TODO: Check if we need to clone the nbuf
  3467. * Or can we just use the reference for all cases
  3468. */
  3469. if (new_mac_idx < (new_mac_cnt - 1)) {
  3470. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3471. if (nbuf_clone == NULL) {
  3472. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3473. goto fail_clone;
  3474. }
  3475. } else {
  3476. /*
  3477. * Update the ref
  3478. * to account for frame sent without cloning
  3479. */
  3480. qdf_nbuf_ref(nbuf);
  3481. nbuf_clone = nbuf;
  3482. }
  3483. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3484. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3485. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3486. &paddr_mcbuf);
  3487. if (status) {
  3488. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3489. "Mapping failure Error:%d", status);
  3490. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3491. goto fail_map;
  3492. }
  3493. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3494. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3495. seg_info_new->frags[0].paddr_hi =
  3496. ((uint64_t) paddr_mcbuf >> 32);
  3497. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3498. seg_info_new->frags[1] = data_frag;
  3499. seg_info_new->nbuf = nbuf_clone;
  3500. seg_info_new->frag_cnt = 2;
  3501. seg_info_new->total_len = len;
  3502. seg_info_new->next = NULL;
  3503. if (seg_info_head == NULL)
  3504. seg_info_head = seg_info_new;
  3505. else
  3506. seg_info_tail->next = seg_info_new;
  3507. seg_info_tail = seg_info_new;
  3508. }
  3509. if (!seg_info_head) {
  3510. goto free_return;
  3511. }
  3512. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3513. msdu_info.num_seg = new_mac_cnt;
  3514. msdu_info.frm_type = dp_tx_frm_me;
  3515. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3516. qdf_unlikely(pdev->hmmc_tid_override_en))
  3517. msdu_info.tid = pdev->hmmc_tid;
  3518. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3519. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3520. while (seg_info_head->next) {
  3521. seg_info_new = seg_info_head;
  3522. seg_info_head = seg_info_head->next;
  3523. qdf_mem_free(seg_info_new);
  3524. }
  3525. qdf_mem_free(seg_info_head);
  3526. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3527. qdf_nbuf_free(nbuf);
  3528. return new_mac_cnt;
  3529. fail_map:
  3530. qdf_nbuf_free(nbuf_clone);
  3531. fail_clone:
  3532. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3533. fail_buf_alloc:
  3534. qdf_mem_free(seg_info_new);
  3535. fail_seg_alloc:
  3536. dp_tx_me_mem_free(pdev, seg_info_head);
  3537. free_return:
  3538. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3539. qdf_nbuf_free(nbuf);
  3540. return 1;
  3541. }