dsi_display.c 227 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/list.h>
  7. #include <linux/of.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/err.h>
  10. #include <linux/version.h>
  11. #include <linux/ktime.h>
  12. #include "msm_drv.h"
  13. #include "sde_connector.h"
  14. #include "msm_mmu.h"
  15. #include "dsi_display.h"
  16. #include "dsi_panel.h"
  17. #include "dsi_ctrl.h"
  18. #include "dsi_ctrl_hw.h"
  19. #include "dsi_drm.h"
  20. #include "dsi_clk.h"
  21. #include "dsi_pwr.h"
  22. #include "sde_dbg.h"
  23. #include "dsi_parser.h"
  24. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  25. #define INT_BASE_10 10
  26. #define MISR_BUFF_SIZE 256
  27. #define ESD_MODE_STRING_MAX_LEN 256
  28. #define ESD_TRIGGER_STRING_MAX_LEN 10
  29. #define MAX_NAME_SIZE 64
  30. #define MAX_TE_RECHECKS 5
  31. #define DSI_CLOCK_BITRATE_RADIX 10
  32. #define MAX_TE_SOURCE_ID 2
  33. #define SEC_PANEL_NAME_MAX_LEN 256
  34. u8 dbgfs_tx_cmd_buf[SZ_4K];
  35. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  36. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  37. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  38. {.boot_param = dsi_display_primary},
  39. {.boot_param = dsi_display_secondary},
  40. };
  41. static void dsi_display_panel_id_notification(struct dsi_display *display);
  42. static const struct of_device_id dsi_display_dt_match[] = {
  43. {.compatible = "qcom,dsi-display"},
  44. {}
  45. };
  46. bool is_skip_op_required(struct dsi_display *display)
  47. {
  48. if (!display)
  49. return false;
  50. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  51. }
  52. static bool is_sim_panel(struct dsi_display *display)
  53. {
  54. if (!display || !display->panel)
  55. return false;
  56. return (display->panel->te_using_watchdog_timer ||
  57. display->panel->panel_ack_disabled);
  58. }
  59. static bool phy_pll_bypass(struct dsi_display *display)
  60. {
  61. return display->ctrl[display->cmd_master_idx].phy->hw.phy_pll_bypass;
  62. }
  63. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  64. u32 mask, bool enable)
  65. {
  66. int i;
  67. struct dsi_display_ctrl *ctrl;
  68. if (!display)
  69. return;
  70. display_for_each_ctrl(i, display) {
  71. ctrl = &display->ctrl[i];
  72. if ((!ctrl) || (!ctrl->ctrl))
  73. continue;
  74. mutex_lock(&ctrl->ctrl->ctrl_lock);
  75. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  76. mutex_unlock(&ctrl->ctrl->ctrl_lock);
  77. }
  78. }
  79. static int dsi_display_config_clk_gating(struct dsi_display *display,
  80. bool enable)
  81. {
  82. int rc = 0, i = 0;
  83. struct dsi_display_ctrl *mctrl, *ctrl;
  84. enum dsi_clk_gate_type clk_selection;
  85. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  86. if (!display) {
  87. DSI_ERR("Invalid params\n");
  88. return -EINVAL;
  89. }
  90. if (display->panel->host_config.force_hs_clk_lane) {
  91. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  92. return 0;
  93. }
  94. mctrl = &display->ctrl[display->clk_master_idx];
  95. if (!mctrl) {
  96. DSI_ERR("Invalid controller\n");
  97. return -EINVAL;
  98. }
  99. clk_selection = display->clk_gating_config;
  100. if (!enable) {
  101. /* for disable path, make sure to disable all clk gating */
  102. clk_selection = DSI_CLK_ALL;
  103. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  104. /* Default selection, no overrides */
  105. clk_selection = default_clk_select;
  106. } else if (clk_selection == DSI_CLK_NONE) {
  107. clk_selection = 0;
  108. }
  109. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  110. enable ? "Enabling" : "Disabling",
  111. clk_selection & BYTE_CLK ? "yes" : "no",
  112. clk_selection & PIXEL_CLK ? "yes" : "no",
  113. clk_selection & DSI_PHY ? "yes" : "no");
  114. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  115. if (rc) {
  116. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  117. display->name, enable ? "enable" : "disable",
  118. clk_selection, rc);
  119. return rc;
  120. }
  121. display_for_each_ctrl(i, display) {
  122. ctrl = &display->ctrl[i];
  123. if (!ctrl->ctrl || (ctrl == mctrl))
  124. continue;
  125. /**
  126. * In Split DSI usecase we should not enable clock gating on
  127. * DSI PHY1 to ensure no display atrifacts are seen.
  128. */
  129. clk_selection &= ~DSI_PHY;
  130. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  131. clk_selection);
  132. if (rc) {
  133. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  134. display->name, enable ? "enable" : "disable",
  135. clk_selection, rc);
  136. return rc;
  137. }
  138. }
  139. return 0;
  140. }
  141. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  142. bool enable)
  143. {
  144. int i;
  145. struct dsi_display_ctrl *ctrl;
  146. if (!display)
  147. return;
  148. display_for_each_ctrl(i, display) {
  149. ctrl = &display->ctrl[i];
  150. if (!ctrl)
  151. continue;
  152. ctrl->ctrl->esd_check_underway = enable;
  153. }
  154. }
  155. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  156. {
  157. int i;
  158. struct dsi_display_ctrl *ctrl;
  159. if (!display)
  160. return;
  161. display_for_each_ctrl(i, display) {
  162. ctrl = &display->ctrl[i];
  163. if (!ctrl)
  164. continue;
  165. dsi_ctrl_irq_update(ctrl->ctrl, en);
  166. }
  167. }
  168. void dsi_rect_intersect(const struct dsi_rect *r1,
  169. const struct dsi_rect *r2,
  170. struct dsi_rect *result)
  171. {
  172. int l, t, r, b;
  173. if (!r1 || !r2 || !result)
  174. return;
  175. l = max(r1->x, r2->x);
  176. t = max(r1->y, r2->y);
  177. r = min((r1->x + r1->w), (r2->x + r2->w));
  178. b = min((r1->y + r1->h), (r2->y + r2->h));
  179. if (r <= l || b <= t) {
  180. memset(result, 0, sizeof(*result));
  181. } else {
  182. result->x = l;
  183. result->y = t;
  184. result->w = r - l;
  185. result->h = b - t;
  186. }
  187. }
  188. int dsi_display_set_backlight(struct drm_connector *connector,
  189. void *display, u32 bl_lvl)
  190. {
  191. struct dsi_display *dsi_display = display;
  192. struct dsi_panel *panel;
  193. u32 bl_scale, bl_scale_sv;
  194. u64 bl_temp;
  195. int rc = 0;
  196. if (dsi_display == NULL || dsi_display->panel == NULL)
  197. return -EINVAL;
  198. panel = dsi_display->panel;
  199. mutex_lock(&panel->panel_lock);
  200. if (!dsi_panel_initialized(panel)) {
  201. rc = -EINVAL;
  202. goto error;
  203. }
  204. panel->bl_config.bl_level = bl_lvl;
  205. /* scale backlight */
  206. bl_scale = panel->bl_config.bl_scale;
  207. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  208. bl_scale_sv = panel->bl_config.bl_scale_sv;
  209. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  210. /* use bl_temp as index of dimming bl lut to find the dimming panel backlight */
  211. if (bl_temp != 0 && panel->bl_config.dimming_bl_lut &&
  212. bl_temp < panel->bl_config.dimming_bl_lut->length) {
  213. DSI_DEBUG("before dimming bl_temp = %u, after dimming bl_temp = %lu\n",
  214. bl_temp, panel->bl_config.dimming_bl_lut->mapped_bl[bl_temp]);
  215. bl_temp = panel->bl_config.dimming_bl_lut->mapped_bl[bl_temp];
  216. }
  217. if (bl_temp > panel->bl_config.bl_max_level)
  218. bl_temp = panel->bl_config.bl_max_level;
  219. if (bl_temp && (bl_temp < panel->bl_config.bl_min_level))
  220. bl_temp = panel->bl_config.bl_min_level;
  221. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  222. bl_scale, bl_scale_sv, (u32)bl_temp);
  223. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  224. if (rc)
  225. DSI_ERR("unable to set backlight\n");
  226. error:
  227. mutex_unlock(&panel->panel_lock);
  228. return rc;
  229. }
  230. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  231. {
  232. int rc = 0;
  233. int i;
  234. struct dsi_display_ctrl *m_ctrl, *ctrl;
  235. bool skip_op = display->trusted_vm_env;
  236. m_ctrl = &display->ctrl[display->cmd_master_idx];
  237. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  238. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  239. DSI_CTRL_ENGINE_ON, skip_op);
  240. if (rc) {
  241. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  242. display->name, skip_op, rc);
  243. goto done;
  244. }
  245. display_for_each_ctrl(i, display) {
  246. ctrl = &display->ctrl[i];
  247. if (!ctrl->ctrl || (ctrl == m_ctrl))
  248. continue;
  249. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  250. DSI_CTRL_ENGINE_ON, skip_op);
  251. if (rc) {
  252. DSI_ERR(
  253. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  254. display->name, skip_op, rc);
  255. goto error_disable_master;
  256. }
  257. }
  258. goto done;
  259. error_disable_master:
  260. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  261. DSI_CTRL_ENGINE_OFF, skip_op);
  262. done:
  263. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  264. return rc;
  265. }
  266. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  267. {
  268. int rc = 0;
  269. int i;
  270. struct dsi_display_ctrl *m_ctrl, *ctrl;
  271. bool skip_op = display->trusted_vm_env;
  272. m_ctrl = &display->ctrl[display->cmd_master_idx];
  273. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  274. display_for_each_ctrl(i, display) {
  275. ctrl = &display->ctrl[i];
  276. if (!ctrl->ctrl || (ctrl == m_ctrl))
  277. continue;
  278. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  279. DSI_CTRL_ENGINE_OFF, skip_op);
  280. if (rc)
  281. DSI_ERR(
  282. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  283. display->name, skip_op, rc);
  284. }
  285. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  286. DSI_CTRL_ENGINE_OFF, skip_op);
  287. if (rc)
  288. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  289. display->name, skip_op, rc);
  290. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  291. return rc;
  292. }
  293. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  294. {
  295. struct dsi_display *display;
  296. struct dsi_display_ctrl *display_ctrl;
  297. int rc, cnt;
  298. if (!cb_data) {
  299. DSI_ERR("aspace cb called with invalid cb_data\n");
  300. return;
  301. }
  302. display = (struct dsi_display *)cb_data;
  303. /*
  304. * acquire panel_lock to make sure no commands are in-progress
  305. * while detaching the non-secure context banks
  306. */
  307. dsi_panel_acquire_panel_lock(display->panel);
  308. if (is_detach) {
  309. /* invalidate the stored iova */
  310. display->cmd_buffer_iova = 0;
  311. /* return the virtual address mapping */
  312. msm_gem_put_vaddr(display->tx_cmd_buf);
  313. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  314. } else {
  315. rc = msm_gem_get_iova(display->tx_cmd_buf,
  316. display->aspace, &(display->cmd_buffer_iova));
  317. if (rc) {
  318. DSI_ERR("failed to get the iova rc %d\n", rc);
  319. goto end;
  320. }
  321. display->vaddr =
  322. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  323. if (IS_ERR_OR_NULL(display->vaddr)) {
  324. DSI_ERR("failed to get va rc %d\n", rc);
  325. goto end;
  326. }
  327. }
  328. display_for_each_ctrl(cnt, display) {
  329. display_ctrl = &display->ctrl[cnt];
  330. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  331. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  332. display_ctrl->ctrl->vaddr = display->vaddr;
  333. display_ctrl->ctrl->secure_mode = is_detach;
  334. }
  335. end:
  336. /* release panel_lock */
  337. dsi_panel_release_panel_lock(display->panel);
  338. }
  339. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  340. {
  341. struct dsi_display *display = (struct dsi_display *)data;
  342. /*
  343. * This irq handler is used for sole purpose of identifying
  344. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  345. * in case of display not being initialized yet
  346. */
  347. if (!display)
  348. return IRQ_HANDLED;
  349. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  350. complete_all(&display->esd_te_gate);
  351. return IRQ_HANDLED;
  352. }
  353. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  354. bool enable)
  355. {
  356. if (!display) {
  357. DSI_ERR("Invalid params\n");
  358. return;
  359. }
  360. /* Handle unbalanced irq enable/disable calls */
  361. if (enable && !display->is_te_irq_enabled) {
  362. enable_irq(gpio_to_irq(display->disp_te_gpio));
  363. display->is_te_irq_enabled = true;
  364. } else if (!enable && display->is_te_irq_enabled) {
  365. disable_irq(gpio_to_irq(display->disp_te_gpio));
  366. display->is_te_irq_enabled = false;
  367. }
  368. }
  369. static void dsi_display_register_te_irq(struct dsi_display *display)
  370. {
  371. int rc = 0;
  372. struct platform_device *pdev;
  373. struct device *dev;
  374. unsigned int te_irq;
  375. pdev = display->pdev;
  376. if (!pdev) {
  377. DSI_ERR("invalid platform device\n");
  378. return;
  379. }
  380. dev = &pdev->dev;
  381. if (!dev) {
  382. DSI_ERR("invalid device\n");
  383. return;
  384. }
  385. if (display->trusted_vm_env) {
  386. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  387. return;
  388. }
  389. if (!gpio_is_valid(display->disp_te_gpio)) {
  390. rc = -EINVAL;
  391. goto error;
  392. }
  393. init_completion(&display->esd_te_gate);
  394. te_irq = gpio_to_irq(display->disp_te_gpio);
  395. /* Avoid deferred spurious irqs with disable_irq() */
  396. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  397. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  398. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  399. "TE_GPIO", display);
  400. if (rc) {
  401. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  402. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  403. goto error;
  404. }
  405. disable_irq(te_irq);
  406. display->is_te_irq_enabled = false;
  407. return;
  408. error:
  409. /* disable the TE based ESD check */
  410. DSI_WARN("Unable to register for TE IRQ\n");
  411. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  412. display->panel->esd_config.esd_enabled = false;
  413. }
  414. /* Allocate memory for cmd dma tx buffer */
  415. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  416. {
  417. int rc = 0, cnt = 0;
  418. struct dsi_display_ctrl *display_ctrl;
  419. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  420. SZ_4K,
  421. MSM_BO_UNCACHED);
  422. if ((display->tx_cmd_buf) == NULL) {
  423. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  424. rc = -ENOMEM;
  425. goto error;
  426. }
  427. display->cmd_buffer_size = SZ_4K;
  428. display->aspace = msm_gem_smmu_address_space_get(
  429. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  430. if (PTR_ERR(display->aspace) == -ENODEV) {
  431. display->aspace = NULL;
  432. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  433. } else if (IS_ERR_OR_NULL(display->aspace)) {
  434. rc = PTR_ERR(display->aspace);
  435. display->aspace = NULL;
  436. DSI_ERR("failed to get aspace %d\n", rc);
  437. goto free_gem;
  438. } else if (display->aspace) {
  439. /* register to aspace */
  440. rc = msm_gem_address_space_register_cb(display->aspace,
  441. dsi_display_aspace_cb_locked, (void *)display);
  442. if (rc) {
  443. DSI_ERR("failed to register callback %d\n", rc);
  444. goto free_gem;
  445. }
  446. }
  447. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  448. &(display->cmd_buffer_iova));
  449. if (rc) {
  450. DSI_ERR("failed to get the iova rc %d\n", rc);
  451. goto free_aspace_cb;
  452. }
  453. display->vaddr =
  454. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  455. if (IS_ERR_OR_NULL(display->vaddr)) {
  456. DSI_ERR("failed to get va rc %d\n", rc);
  457. rc = -EINVAL;
  458. goto put_iova;
  459. }
  460. display_for_each_ctrl(cnt, display) {
  461. display_ctrl = &display->ctrl[cnt];
  462. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  463. display_ctrl->ctrl->cmd_buffer_iova =
  464. display->cmd_buffer_iova;
  465. display_ctrl->ctrl->vaddr = display->vaddr;
  466. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  467. }
  468. return rc;
  469. put_iova:
  470. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  471. free_aspace_cb:
  472. msm_gem_address_space_unregister_cb(display->aspace,
  473. dsi_display_aspace_cb_locked, display);
  474. free_gem:
  475. mutex_lock(&display->drm_dev->struct_mutex);
  476. msm_gem_free_object(display->tx_cmd_buf);
  477. mutex_unlock(&display->drm_dev->struct_mutex);
  478. error:
  479. return rc;
  480. }
  481. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  482. {
  483. int i, j = 0;
  484. int len = 0, *lenp;
  485. int group = 0, count = 0;
  486. struct drm_panel_esd_config *config;
  487. if (!panel)
  488. return false;
  489. config = &(panel->esd_config);
  490. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  491. count = config->status_cmd.count;
  492. for (i = 0; i < count; i++)
  493. len += lenp[i];
  494. for (j = 0; j < config->groups; ++j) {
  495. for (i = 0; i < len; ++i) {
  496. if (config->return_buf[i] !=
  497. config->status_value[group + i]) {
  498. DRM_ERROR("mismatch: 0x%x\n",
  499. config->return_buf[i]);
  500. break;
  501. }
  502. }
  503. if (i == len)
  504. return true;
  505. group += len;
  506. }
  507. return false;
  508. }
  509. static void dsi_display_parse_demura_data(struct dsi_display *display)
  510. {
  511. int rc = 0;
  512. display->panel_id = ~0x0;
  513. if (display->fw) {
  514. DSI_DEBUG("FW definition unsupported for Demura panel data\n");
  515. return;
  516. }
  517. rc = of_property_read_u64(display->pdev->dev.of_node,
  518. "qcom,demura-panel-id", &display->panel_id);
  519. if (rc) {
  520. DSI_DEBUG("No panel ID is present for this display\n");
  521. } else if (!display->panel_id) {
  522. DSI_DEBUG("Dummy panel ID node present for this display\n");
  523. display->panel_id = ~0x0;
  524. } else {
  525. DSI_DEBUG("panel id found: %lx\n", display->panel_id);
  526. }
  527. }
  528. static void dsi_display_parse_te_data(struct dsi_display *display)
  529. {
  530. struct platform_device *pdev;
  531. struct device *dev;
  532. int rc = 0;
  533. u32 val = 0;
  534. pdev = display->pdev;
  535. if (!pdev) {
  536. DSI_ERR("Invalid platform device\n");
  537. return;
  538. }
  539. dev = &pdev->dev;
  540. if (!dev) {
  541. DSI_ERR("Invalid platform device\n");
  542. return;
  543. }
  544. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  545. "qcom,platform-te-gpio", 0);
  546. if (display->fw)
  547. rc = dsi_parser_read_u32(display->parser_node,
  548. "qcom,panel-te-source", &val);
  549. else
  550. rc = of_property_read_u32(dev->of_node,
  551. "qcom,panel-te-source", &val);
  552. if (rc || (val > MAX_TE_SOURCE_ID)) {
  553. DSI_ERR("invalid vsync source selection\n");
  554. val = 0;
  555. }
  556. display->te_source = val;
  557. }
  558. static void dsi_display_set_cmd_tx_ctrl_flags(struct dsi_display *display,
  559. struct dsi_cmd_desc *cmd)
  560. {
  561. struct dsi_display_ctrl *ctrl, *m_ctrl;
  562. struct mipi_dsi_msg *msg = &cmd->msg;
  563. u32 flags = 0;
  564. int i = 0;
  565. m_ctrl = &display->ctrl[display->clk_master_idx];
  566. display_for_each_ctrl(i, display) {
  567. ctrl = &display->ctrl[i];
  568. if (!ctrl->ctrl)
  569. continue;
  570. /*
  571. * Set cmd transfer mode flags.
  572. * 1) Default selection is CMD fetch from memory.
  573. * 2) In secure session override and use FIFO rather than
  574. * memory.
  575. * 3) If cmd_len is greater than FIFO size non embedded mode of
  576. * tx is used.
  577. */
  578. flags = DSI_CTRL_CMD_FETCH_MEMORY;
  579. if (ctrl->ctrl->secure_mode) {
  580. flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
  581. flags |= DSI_CTRL_CMD_FIFO_STORE;
  582. } else if (msg->tx_len > DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES) {
  583. flags |= DSI_CTRL_CMD_NON_EMBEDDED_MODE;
  584. }
  585. /* Set flags needed for broadcast. Read commands are always unicast */
  586. if (!(msg->flags & MIPI_DSI_MSG_UNICAST_COMMAND) && (display->ctrl_count > 1))
  587. flags |= DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER;
  588. /*
  589. * Set flags for command scheduling.
  590. * 1) In video mode command DMA scheduling is default.
  591. * 2) In command mode unicast command DMA scheduling depends on message
  592. * flag and TE needs to be running.
  593. * 3) In command mode broadcast command DMA scheduling is default and
  594. * TE needs to be running.
  595. */
  596. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  597. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  598. } else {
  599. if (msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED)
  600. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  601. if (flags & DSI_CTRL_CMD_BROADCAST)
  602. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  603. if (!display->enabled)
  604. flags &= ~DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  605. }
  606. /* Set flags for last command */
  607. if (!(msg->flags & MIPI_DSI_MSG_BATCH_COMMAND) || (flags & DSI_CTRL_CMD_FIFO_STORE)
  608. || (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE))
  609. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  610. /*
  611. * Set flags for asynchronous wait.
  612. * Asynchronous wait is supported in the following scenarios
  613. * 1) queue_cmd_waits is set by connector and
  614. * - commands are not sent using DSI FIFO memory
  615. * - commands are not sent in non-embedded mode
  616. * - no explicit msg post_wait_ms is specified
  617. * - not a read command
  618. * 2) if async override msg flag is present
  619. */
  620. if (display->queue_cmd_waits)
  621. if (!(flags & DSI_CTRL_CMD_FIFO_STORE) &&
  622. !(flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) &&
  623. (cmd->post_wait_ms == 0) &&
  624. !(cmd->ctrl_flags & DSI_CTRL_CMD_READ))
  625. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  626. if (msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  627. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  628. }
  629. cmd->ctrl_flags |= flags;
  630. }
  631. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  632. struct dsi_display *display)
  633. {
  634. int i, rc = 0, count = 0, start = 0, *lenp;
  635. struct drm_panel_esd_config *config;
  636. struct dsi_cmd_desc *cmds;
  637. struct dsi_panel *panel;
  638. u32 flags = 0;
  639. if (!display->panel || !ctrl || !ctrl->ctrl)
  640. return -EINVAL;
  641. panel = display->panel;
  642. /*
  643. * When DSI controller is not in initialized state, we do not want to
  644. * report a false ESD failure and hence we defer until next read
  645. * happen.
  646. */
  647. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  648. return 1;
  649. if (phy_pll_bypass(display))
  650. return 0;
  651. config = &(panel->esd_config);
  652. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  653. count = config->status_cmd.count;
  654. cmds = config->status_cmd.cmds;
  655. flags = DSI_CTRL_CMD_READ;
  656. for (i = 0; i < count; ++i) {
  657. memset(config->status_buf, 0x0, SZ_4K);
  658. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  659. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  660. cmds[i].msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  661. cmds[i].msg.rx_buf = config->status_buf;
  662. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  663. cmds[i].ctrl_flags = flags;
  664. dsi_display_set_cmd_tx_ctrl_flags(display,&cmds[i]);
  665. rc = dsi_ctrl_transfer_prepare(ctrl->ctrl, cmds[i].ctrl_flags);
  666. if (rc) {
  667. DSI_ERR("prepare for rx cmd transfer failed rc=%d\n", rc);
  668. return rc;
  669. }
  670. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i]);
  671. if (rc <= 0) {
  672. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  673. } else {
  674. memcpy(config->return_buf + start,
  675. config->status_buf, lenp[i]);
  676. start += lenp[i];
  677. }
  678. dsi_ctrl_transfer_unprepare(ctrl->ctrl, cmds[i].ctrl_flags);
  679. }
  680. return rc;
  681. }
  682. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  683. struct dsi_display *display)
  684. {
  685. int rc = 0;
  686. rc = dsi_display_read_status(ctrl, display);
  687. if (rc <= 0) {
  688. goto exit;
  689. } else {
  690. /*
  691. * panel status read successfully.
  692. * check for validity of the data read back.
  693. */
  694. rc = dsi_display_validate_reg_read(display->panel);
  695. if (!rc) {
  696. rc = -EINVAL;
  697. goto exit;
  698. }
  699. }
  700. exit:
  701. return rc;
  702. }
  703. static int dsi_display_status_reg_read(struct dsi_display *display)
  704. {
  705. int rc = 0, i;
  706. struct dsi_display_ctrl *m_ctrl, *ctrl;
  707. DSI_DEBUG(" ++\n");
  708. m_ctrl = &display->ctrl[display->cmd_master_idx];
  709. if (display->tx_cmd_buf == NULL) {
  710. rc = dsi_host_alloc_cmd_tx_buffer(display);
  711. if (rc) {
  712. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  713. goto done;
  714. }
  715. }
  716. rc = dsi_display_validate_status(m_ctrl, display);
  717. if (rc <= 0) {
  718. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  719. display->name, rc);
  720. goto done;
  721. }
  722. if (!display->panel->sync_broadcast_en)
  723. goto done;
  724. display_for_each_ctrl(i, display) {
  725. ctrl = &display->ctrl[i];
  726. if (ctrl == m_ctrl)
  727. continue;
  728. rc = dsi_display_validate_status(ctrl, display);
  729. if (rc <= 0) {
  730. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  731. display->name, rc);
  732. goto done;
  733. }
  734. }
  735. done:
  736. return rc;
  737. }
  738. static int dsi_display_status_bta_request(struct dsi_display *display)
  739. {
  740. int rc = 0;
  741. DSI_DEBUG(" ++\n");
  742. /* TODO: trigger SW BTA and wait for acknowledgment */
  743. return rc;
  744. }
  745. static void dsi_display_release_te_irq(struct dsi_display *display)
  746. {
  747. int te_irq = 0;
  748. te_irq = gpio_to_irq(display->disp_te_gpio);
  749. if (te_irq)
  750. free_irq(te_irq, display);
  751. }
  752. static int dsi_display_status_check_te(struct dsi_display *display,
  753. int rechecks)
  754. {
  755. int rc = 1, i = 0;
  756. int const esd_te_timeout = msecs_to_jiffies(3*20);
  757. if (!rechecks)
  758. return rc;
  759. /* register te irq handler */
  760. dsi_display_register_te_irq(display);
  761. dsi_display_change_te_irq_status(display, true);
  762. for (i = 0; i < rechecks; i++) {
  763. reinit_completion(&display->esd_te_gate);
  764. if (!wait_for_completion_timeout(&display->esd_te_gate,
  765. esd_te_timeout)) {
  766. DSI_ERR("TE check failed\n");
  767. dsi_display_change_te_irq_status(display, false);
  768. return -EINVAL;
  769. }
  770. }
  771. dsi_display_change_te_irq_status(display, false);
  772. dsi_display_release_te_irq(display);
  773. return rc;
  774. }
  775. void dsi_display_toggle_error_interrupt_status(struct dsi_display * display, bool enable)
  776. {
  777. int i = 0;
  778. struct dsi_display_ctrl *ctrl;
  779. display_for_each_ctrl(i, display) {
  780. ctrl = &display->ctrl[i];
  781. if (!ctrl->ctrl)
  782. continue;
  783. dsi_ctrl_toggle_error_interrupt_status(ctrl->ctrl, enable);
  784. }
  785. }
  786. int dsi_display_check_status(struct drm_connector *connector, void *display,
  787. bool te_check_override)
  788. {
  789. struct dsi_display *dsi_display = display;
  790. struct dsi_panel *panel;
  791. u32 status_mode;
  792. int rc = 0x1;
  793. int te_rechecks = 1;
  794. if (!dsi_display || !dsi_display->panel)
  795. return -EINVAL;
  796. panel = dsi_display->panel;
  797. dsi_panel_acquire_panel_lock(panel);
  798. if (!panel->panel_initialized) {
  799. DSI_DEBUG("Panel not initialized\n");
  800. goto release_panel_lock;
  801. }
  802. /* Prevent another ESD check,when ESD recovery is underway */
  803. if (atomic_read(&panel->esd_recovery_pending))
  804. goto release_panel_lock;
  805. status_mode = panel->esd_config.status_mode;
  806. if ((status_mode == ESD_MODE_SW_SIM_SUCCESS) || is_sim_panel(display))
  807. goto release_panel_lock;
  808. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  809. rc = -EINVAL;
  810. goto release_panel_lock;
  811. }
  812. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
  813. if (te_check_override)
  814. te_rechecks = MAX_TE_RECHECKS;
  815. if ((dsi_display->trusted_vm_env) ||
  816. (panel->panel_mode == DSI_OP_VIDEO_MODE))
  817. te_rechecks = 0;
  818. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  819. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  820. /* Disable error interrupts while doing an ESD check */
  821. dsi_display_toggle_error_interrupt_status(dsi_display, false);
  822. if (status_mode == ESD_MODE_REG_READ) {
  823. rc = dsi_display_status_reg_read(dsi_display);
  824. } else if (status_mode == ESD_MODE_SW_BTA) {
  825. rc = dsi_display_status_bta_request(dsi_display);
  826. } else if (status_mode == ESD_MODE_PANEL_TE) {
  827. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  828. te_check_override = false;
  829. } else {
  830. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  831. panel->esd_config.esd_enabled = false;
  832. }
  833. if (rc <= 0 && te_check_override)
  834. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  835. if (rc > 0) {
  836. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  837. if (te_check_override && panel->esd_config.esd_enabled == false)
  838. rc = dsi_display_status_check_te(dsi_display,
  839. te_rechecks);
  840. }
  841. /* Handle Panel failures during display disable sequence */
  842. if (rc <=0)
  843. atomic_set(&panel->esd_recovery_pending, 1);
  844. else
  845. /* Enable error interrupts post an ESD success */
  846. dsi_display_toggle_error_interrupt_status(dsi_display, true);
  847. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_OFF);
  848. release_panel_lock:
  849. dsi_panel_release_panel_lock(panel);
  850. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
  851. return rc;
  852. }
  853. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  854. bool *state)
  855. {
  856. struct dsi_display_ctrl *ctrl;
  857. int i, rc = -EINVAL;
  858. bool final_state = true;
  859. display_for_each_ctrl(i, dsi_display) {
  860. bool ctrl_state = false;
  861. ctrl = &dsi_display->ctrl[i];
  862. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, &ctrl_state);
  863. final_state &= ctrl_state;
  864. if ((rc) || !(final_state))
  865. break;
  866. }
  867. *state = final_state;
  868. return rc;
  869. }
  870. static int dsi_display_cmd_rx(struct dsi_display *display,
  871. struct dsi_cmd_desc *cmd)
  872. {
  873. struct dsi_display_ctrl *m_ctrl = NULL;
  874. u32 flags = 0;
  875. int rc = 0;
  876. if (!display || !display->panel)
  877. return -EINVAL;
  878. m_ctrl = &display->ctrl[display->cmd_master_idx];
  879. if (!m_ctrl || !m_ctrl->ctrl)
  880. return -EINVAL;
  881. /* acquire panel_lock to make sure no commands are in progress */
  882. dsi_panel_acquire_panel_lock(display->panel);
  883. if (!display->panel->panel_initialized) {
  884. DSI_DEBUG("panel not initialized\n");
  885. goto release_panel_lock;
  886. }
  887. if (phy_pll_bypass(display))
  888. goto release_panel_lock;
  889. flags = DSI_CTRL_CMD_READ;
  890. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  891. dsi_display_toggle_error_interrupt_status(display, false);
  892. cmd->ctrl_flags = flags;
  893. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  894. rc = dsi_ctrl_transfer_prepare(m_ctrl->ctrl, cmd->ctrl_flags);
  895. if (rc) {
  896. DSI_ERR("prepare for rx cmd transfer failed rc = %d\n", rc);
  897. goto enable_error_interrupts;
  898. }
  899. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  900. if (rc <= 0)
  901. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  902. dsi_ctrl_transfer_unprepare(m_ctrl->ctrl, cmd->ctrl_flags);
  903. enable_error_interrupts:
  904. dsi_display_toggle_error_interrupt_status(display, true);
  905. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_OFF);
  906. release_panel_lock:
  907. dsi_panel_release_panel_lock(display->panel);
  908. return rc;
  909. }
  910. int dsi_display_cmd_transfer(struct drm_connector *connector,
  911. void *display, const char *cmd_buf,
  912. u32 cmd_buf_len)
  913. {
  914. struct dsi_display *dsi_display = display;
  915. int rc = 0, cnt = 0, i = 0;
  916. bool state = false, transfer = false;
  917. struct dsi_panel_cmd_set *set;
  918. if (!dsi_display || !cmd_buf) {
  919. DSI_ERR("[DSI] invalid params\n");
  920. return -EINVAL;
  921. }
  922. DSI_DEBUG("[DSI] Display command transfer\n");
  923. if (!(cmd_buf[3] & MIPI_DSI_MSG_BATCH_COMMAND))
  924. transfer = true;
  925. mutex_lock(&dsi_display->display_lock);
  926. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  927. /**
  928. * Handle scenario where a command transfer is initiated through
  929. * sysfs interface when device is in suepnd state.
  930. */
  931. if (!rc && !state) {
  932. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  933. );
  934. rc = -EPERM;
  935. goto end;
  936. }
  937. if (rc || !state) {
  938. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  939. state, rc);
  940. rc = -EPERM;
  941. goto end;
  942. }
  943. SDE_EVT32(dsi_display->tx_cmd_buf_ndx, cmd_buf_len);
  944. /*
  945. * Reset the dbgfs buffer if the commands sent exceed the available
  946. * buffer size. For video mode, limiting the buffer size to 2K to
  947. * ensure no performance issues.
  948. */
  949. if (dsi_display->panel->panel_mode == DSI_OP_CMD_MODE) {
  950. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_4K) {
  951. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  952. dsi_display->tx_cmd_buf_ndx = 0;
  953. }
  954. } else {
  955. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_2K) {
  956. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  957. dsi_display->tx_cmd_buf_ndx = 0;
  958. }
  959. }
  960. memcpy(&dbgfs_tx_cmd_buf[dsi_display->tx_cmd_buf_ndx], cmd_buf,
  961. cmd_buf_len);
  962. dsi_display->tx_cmd_buf_ndx += cmd_buf_len;
  963. if (transfer) {
  964. struct dsi_cmd_desc *cmds;
  965. set = &dsi_display->cmd_set;
  966. set->count = 0;
  967. dsi_panel_get_cmd_pkt_count(dbgfs_tx_cmd_buf,
  968. dsi_display->tx_cmd_buf_ndx, &cnt);
  969. dsi_panel_alloc_cmd_packets(set, cnt);
  970. dsi_panel_create_cmd_packets(dbgfs_tx_cmd_buf,
  971. dsi_display->tx_cmd_buf_ndx, cnt, set->cmds);
  972. cmds = set->cmds;
  973. dsi_display->tx_cmd_buf_ndx = 0;
  974. dsi_panel_acquire_panel_lock(dsi_display->panel);
  975. for (i = 0; i < cnt; i++) {
  976. rc = dsi_host_transfer_sub(&dsi_display->host, cmds);
  977. if (rc < 0) {
  978. DSI_ERR("failed to send command, rc=%d\n", rc);
  979. break;
  980. }
  981. if (cmds->post_wait_ms)
  982. usleep_range(cmds->post_wait_ms*1000,
  983. ((cmds->post_wait_ms*1000)+10));
  984. cmds++;
  985. }
  986. dsi_panel_release_panel_lock(dsi_display->panel);
  987. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  988. dsi_panel_destroy_cmd_packets(set);
  989. dsi_panel_dealloc_cmd_packets(set);
  990. }
  991. end:
  992. mutex_unlock(&dsi_display->display_lock);
  993. return rc;
  994. }
  995. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  996. bool enable)
  997. {
  998. int i;
  999. struct dsi_display_ctrl *ctrl;
  1000. if (!display || !display->panel->host_config.force_hs_clk_lane)
  1001. return;
  1002. display_for_each_ctrl(i, display) {
  1003. ctrl = &display->ctrl[i];
  1004. /*
  1005. * For phy ver 4.0 chipsets, configure DSI controller and
  1006. * DSI PHY to force clk lane to HS mode always whereas
  1007. * for other phy ver chipsets, configure DSI controller only.
  1008. */
  1009. if (ctrl->phy->hw.ops.set_continuous_clk) {
  1010. dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
  1011. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  1012. dsi_phy_set_continuous_clk(ctrl->phy, enable);
  1013. } else {
  1014. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  1015. }
  1016. }
  1017. }
  1018. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  1019. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len, ktime_t *ts)
  1020. {
  1021. struct dsi_display *dsi_display = display;
  1022. struct dsi_cmd_desc cmd = {};
  1023. bool state = false;
  1024. int rc = -1;
  1025. if (!dsi_display || !cmd_buf || !recv_buf) {
  1026. DSI_ERR("[DSI] invalid params\n");
  1027. return -EINVAL;
  1028. }
  1029. rc = dsi_panel_create_cmd_packets(cmd_buf, cmd_buf_len, 1, &cmd);
  1030. if (rc) {
  1031. DSI_ERR("[DSI] command packet create failed, rc = %d\n", rc);
  1032. return rc;
  1033. }
  1034. cmd.msg.rx_buf = recv_buf;
  1035. cmd.msg.rx_len = recv_buf_len;
  1036. cmd.msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  1037. mutex_lock(&dsi_display->display_lock);
  1038. if (is_sim_panel(display)) {
  1039. DSI_DEBUG("Simulation panel doesn't support read commands\n");
  1040. goto end;
  1041. }
  1042. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  1043. /**
  1044. * Handle scenario where a command transfer is initiated through
  1045. * sysfs interface when device is in suspend state.
  1046. */
  1047. if (!rc && !state) {
  1048. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n");
  1049. rc = -EPERM;
  1050. goto end;
  1051. }
  1052. if (rc || !state) {
  1053. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  1054. state, rc);
  1055. rc = -EPERM;
  1056. goto end;
  1057. }
  1058. SDE_EVT32(cmd_buf_len, recv_buf_len);
  1059. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  1060. if (rc <= 0)
  1061. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  1062. if (ts)
  1063. *ts = cmd.ts;
  1064. end:
  1065. mutex_unlock(&dsi_display->display_lock);
  1066. return rc;
  1067. }
  1068. int dsi_display_soft_reset(void *display)
  1069. {
  1070. struct dsi_display *dsi_display;
  1071. struct dsi_display_ctrl *ctrl;
  1072. int rc = 0;
  1073. int i;
  1074. if (!display)
  1075. return -EINVAL;
  1076. dsi_display = display;
  1077. display_for_each_ctrl(i, dsi_display) {
  1078. ctrl = &dsi_display->ctrl[i];
  1079. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  1080. if (rc) {
  1081. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  1082. dsi_display->name, i, rc);
  1083. break;
  1084. }
  1085. }
  1086. return rc;
  1087. }
  1088. enum dsi_pixel_format dsi_display_get_dst_format(
  1089. struct drm_connector *connector,
  1090. void *display)
  1091. {
  1092. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  1093. struct dsi_display *dsi_display = (struct dsi_display *)display;
  1094. if (!dsi_display || !dsi_display->panel) {
  1095. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  1096. dsi_display,
  1097. ((dsi_display) ? dsi_display->panel : NULL));
  1098. return format;
  1099. }
  1100. format = dsi_display->panel->host_config.dst_format;
  1101. return format;
  1102. }
  1103. static void _dsi_display_setup_misr(struct dsi_display *display)
  1104. {
  1105. int i;
  1106. display_for_each_ctrl(i, display) {
  1107. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  1108. display->misr_enable,
  1109. display->misr_frame_count);
  1110. }
  1111. }
  1112. int dsi_display_set_power(struct drm_connector *connector,
  1113. int power_mode, void *disp)
  1114. {
  1115. struct dsi_display *display = disp;
  1116. int rc = 0;
  1117. if (!display || !display->panel) {
  1118. DSI_ERR("invalid display/panel\n");
  1119. return -EINVAL;
  1120. }
  1121. switch (power_mode) {
  1122. case SDE_MODE_DPMS_LP1:
  1123. rc = dsi_panel_set_lp1(display->panel);
  1124. break;
  1125. case SDE_MODE_DPMS_LP2:
  1126. rc = dsi_panel_set_lp2(display->panel);
  1127. break;
  1128. case SDE_MODE_DPMS_ON:
  1129. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  1130. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  1131. rc = dsi_panel_set_nolp(display->panel);
  1132. break;
  1133. case SDE_MODE_DPMS_OFF:
  1134. default:
  1135. return rc;
  1136. }
  1137. SDE_EVT32(display->panel->power_mode, power_mode, rc);
  1138. DSI_DEBUG("Power mode transition from %d to %d %s",
  1139. display->panel->power_mode, power_mode,
  1140. rc ? "failed" : "successful");
  1141. if (!rc)
  1142. display->panel->power_mode = power_mode;
  1143. return rc;
  1144. }
  1145. #if IS_ENABLED(CONFIG_DEBUG_FS)
  1146. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  1147. {
  1148. u32 status_mode = 0;
  1149. if (!display->panel) {
  1150. DSI_ERR("Invalid panel data\n");
  1151. return false;
  1152. }
  1153. status_mode = display->panel->esd_config.status_mode;
  1154. if (status_mode == ESD_MODE_PANEL_TE &&
  1155. gpio_is_valid(display->disp_te_gpio))
  1156. return true;
  1157. return false;
  1158. }
  1159. static ssize_t debugfs_dump_info_read(struct file *file,
  1160. char __user *user_buf,
  1161. size_t user_len,
  1162. loff_t *ppos)
  1163. {
  1164. struct dsi_display *display = file->private_data;
  1165. struct dsi_mode_info *m;
  1166. char *buf;
  1167. u32 len = 0;
  1168. int i;
  1169. if (!display)
  1170. return -ENODEV;
  1171. if (*ppos)
  1172. return 0;
  1173. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1174. if (!buf)
  1175. return -ENOMEM;
  1176. m = &display->config.video_timing;
  1177. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1178. len += snprintf(buf + len, (SZ_4K - len),
  1179. "\tResolution = %d(%d|%d|%d|%d)x%d(%d|%d|%d|%d)@%dfps %llu Hz\n",
  1180. m->h_active, m->h_back_porch, m->h_front_porch, m->h_sync_width,
  1181. m->h_sync_polarity, m->v_active, m->v_back_porch, m->v_front_porch,
  1182. m->v_sync_width, m->v_sync_polarity, m->refresh_rate, m->clk_rate_hz);
  1183. display_for_each_ctrl(i, display) {
  1184. len += snprintf(buf + len, (SZ_4K - len),
  1185. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1186. i, display->ctrl[i].ctrl->name,
  1187. display->ctrl[i].phy->name);
  1188. }
  1189. len += snprintf(buf + len, (SZ_4K - len),
  1190. "\tPanel = %s\n", display->panel->name);
  1191. len += snprintf(buf + len, (SZ_4K - len),
  1192. "\tClock master = %s\n",
  1193. display->ctrl[display->clk_master_idx].ctrl->name);
  1194. if (len > user_len)
  1195. len = user_len;
  1196. if (copy_to_user(user_buf, buf, len)) {
  1197. kfree(buf);
  1198. return -EFAULT;
  1199. }
  1200. *ppos += len;
  1201. kfree(buf);
  1202. return len;
  1203. }
  1204. static ssize_t debugfs_misr_setup(struct file *file,
  1205. const char __user *user_buf,
  1206. size_t user_len,
  1207. loff_t *ppos)
  1208. {
  1209. struct dsi_display *display = file->private_data;
  1210. char *buf;
  1211. int rc = 0;
  1212. size_t len;
  1213. u32 enable, frame_count;
  1214. if (!display)
  1215. return -ENODEV;
  1216. if (*ppos)
  1217. return 0;
  1218. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1219. if (!buf)
  1220. return -ENOMEM;
  1221. /* leave room for termination char */
  1222. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1223. if (copy_from_user(buf, user_buf, len)) {
  1224. rc = -EINVAL;
  1225. goto error;
  1226. }
  1227. buf[len] = '\0'; /* terminate the string */
  1228. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1229. rc = -EINVAL;
  1230. goto error;
  1231. }
  1232. display->misr_enable = enable;
  1233. display->misr_frame_count = frame_count;
  1234. mutex_lock(&display->display_lock);
  1235. if (!display->hw_ownership) {
  1236. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1237. display->name);
  1238. rc = -EOPNOTSUPP;
  1239. goto unlock;
  1240. }
  1241. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1242. DSI_CORE_CLK, DSI_CLK_ON);
  1243. if (rc) {
  1244. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1245. display->name, rc);
  1246. goto unlock;
  1247. }
  1248. _dsi_display_setup_misr(display);
  1249. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1250. DSI_CORE_CLK, DSI_CLK_OFF);
  1251. if (rc) {
  1252. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1253. display->name, rc);
  1254. goto unlock;
  1255. }
  1256. rc = user_len;
  1257. unlock:
  1258. mutex_unlock(&display->display_lock);
  1259. error:
  1260. kfree(buf);
  1261. return rc;
  1262. }
  1263. static ssize_t debugfs_misr_read(struct file *file,
  1264. char __user *user_buf,
  1265. size_t user_len,
  1266. loff_t *ppos)
  1267. {
  1268. struct dsi_display *display = file->private_data;
  1269. char *buf;
  1270. u32 len = 0;
  1271. int rc = 0;
  1272. struct dsi_ctrl *dsi_ctrl;
  1273. int i;
  1274. u32 misr;
  1275. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1276. if (!display)
  1277. return -ENODEV;
  1278. if (*ppos)
  1279. return 0;
  1280. buf = kzalloc(max_len, GFP_KERNEL);
  1281. if (ZERO_OR_NULL_PTR(buf))
  1282. return -ENOMEM;
  1283. mutex_lock(&display->display_lock);
  1284. if (!display->hw_ownership) {
  1285. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1286. display->name);
  1287. rc = -EOPNOTSUPP;
  1288. goto error;
  1289. }
  1290. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1291. DSI_CORE_CLK, DSI_CLK_ON);
  1292. if (rc) {
  1293. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1294. display->name, rc);
  1295. goto error;
  1296. }
  1297. display_for_each_ctrl(i, display) {
  1298. dsi_ctrl = display->ctrl[i].ctrl;
  1299. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1300. len += snprintf((buf + len), max_len - len,
  1301. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1302. if (len >= max_len)
  1303. break;
  1304. }
  1305. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1306. DSI_CORE_CLK, DSI_CLK_OFF);
  1307. if (rc) {
  1308. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1309. display->name, rc);
  1310. goto error;
  1311. }
  1312. if (copy_to_user(user_buf, buf, max_len)) {
  1313. rc = -EFAULT;
  1314. goto error;
  1315. }
  1316. *ppos += len;
  1317. error:
  1318. mutex_unlock(&display->display_lock);
  1319. kfree(buf);
  1320. return len;
  1321. }
  1322. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1323. const char __user *user_buf,
  1324. size_t user_len,
  1325. loff_t *ppos)
  1326. {
  1327. struct dsi_display *display = file->private_data;
  1328. char *buf;
  1329. int rc = 0;
  1330. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1331. u32 esd_trigger;
  1332. size_t len;
  1333. if (!display)
  1334. return -ENODEV;
  1335. if (*ppos)
  1336. return 0;
  1337. if (user_len > sizeof(u32))
  1338. return -EINVAL;
  1339. if (!user_len || !user_buf)
  1340. return -EINVAL;
  1341. if (!display->panel ||
  1342. atomic_read(&display->panel->esd_recovery_pending))
  1343. return user_len;
  1344. if (!esd_config->esd_enabled) {
  1345. DSI_ERR("ESD feature is not enabled\n");
  1346. return -EINVAL;
  1347. }
  1348. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1349. if (!buf)
  1350. return -ENOMEM;
  1351. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1352. if (copy_from_user(buf, user_buf, len)) {
  1353. rc = -EINVAL;
  1354. goto error;
  1355. }
  1356. buf[len] = '\0'; /* terminate the string */
  1357. if (kstrtouint(buf, 10, &esd_trigger)) {
  1358. rc = -EINVAL;
  1359. goto error;
  1360. }
  1361. if (esd_trigger != 1) {
  1362. rc = -EINVAL;
  1363. goto error;
  1364. }
  1365. display->esd_trigger = esd_trigger;
  1366. mutex_lock(&display->display_lock);
  1367. if (!display->hw_ownership) {
  1368. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1369. display->name);
  1370. rc = -EOPNOTSUPP;
  1371. goto unlock;
  1372. }
  1373. if (display->esd_trigger) {
  1374. struct dsi_panel *panel = display->panel;
  1375. DSI_INFO("ESD attack triggered by user\n");
  1376. rc = panel->panel_ops.trigger_esd_attack(panel);
  1377. if (rc) {
  1378. DSI_ERR("Failed to trigger ESD attack\n");
  1379. goto error;
  1380. }
  1381. }
  1382. rc = len;
  1383. unlock:
  1384. mutex_unlock(&display->display_lock);
  1385. error:
  1386. kfree(buf);
  1387. return rc;
  1388. }
  1389. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1390. const char __user *user_buf,
  1391. size_t user_len,
  1392. loff_t *ppos)
  1393. {
  1394. struct dsi_display *display = file->private_data;
  1395. struct drm_panel_esd_config *esd_config;
  1396. char *buf;
  1397. int rc = 0;
  1398. size_t len;
  1399. if (!display)
  1400. return -ENODEV;
  1401. if (*ppos)
  1402. return 0;
  1403. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1404. if (ZERO_OR_NULL_PTR(buf))
  1405. return -ENOMEM;
  1406. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1407. if (copy_from_user(buf, user_buf, len)) {
  1408. rc = -EINVAL;
  1409. goto error;
  1410. }
  1411. buf[len] = '\0'; /* terminate the string */
  1412. if (!display->panel) {
  1413. rc = -EINVAL;
  1414. goto error;
  1415. }
  1416. esd_config = &display->panel->esd_config;
  1417. if (!esd_config) {
  1418. DSI_ERR("Invalid panel esd config\n");
  1419. rc = -EINVAL;
  1420. goto error;
  1421. }
  1422. if (!esd_config->esd_enabled) {
  1423. rc = -EINVAL;
  1424. goto error;
  1425. }
  1426. if (!strcmp(buf, "te_signal_check\n")) {
  1427. DSI_INFO("TE based ESD check for panels is not allowed\n");
  1428. rc = -EINVAL;
  1429. goto error;
  1430. }
  1431. if (!strcmp(buf, "reg_read\n")) {
  1432. DSI_INFO("ESD check is switched to reg read by user\n");
  1433. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1434. if (rc) {
  1435. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1436. rc);
  1437. rc = user_len;
  1438. goto error;
  1439. }
  1440. esd_config->status_mode = ESD_MODE_REG_READ;
  1441. if (dsi_display_is_te_based_esd(display))
  1442. dsi_display_change_te_irq_status(display, false);
  1443. }
  1444. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1445. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1446. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1447. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1448. rc = len;
  1449. error:
  1450. kfree(buf);
  1451. return rc;
  1452. }
  1453. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1454. char __user *user_buf,
  1455. size_t user_len,
  1456. loff_t *ppos)
  1457. {
  1458. struct dsi_display *display = file->private_data;
  1459. struct drm_panel_esd_config *esd_config;
  1460. char *buf;
  1461. int rc = 0;
  1462. size_t len = 0;
  1463. if (!display)
  1464. return -ENODEV;
  1465. if (*ppos)
  1466. return 0;
  1467. if (!display->panel) {
  1468. DSI_ERR("invalid panel data\n");
  1469. return -EINVAL;
  1470. }
  1471. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1472. if (ZERO_OR_NULL_PTR(buf))
  1473. return -ENOMEM;
  1474. esd_config = &display->panel->esd_config;
  1475. if (!esd_config) {
  1476. DSI_ERR("Invalid panel esd config\n");
  1477. rc = -EINVAL;
  1478. goto error;
  1479. }
  1480. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1481. if (!esd_config->esd_enabled) {
  1482. rc = snprintf(buf, len, "ESD feature not enabled");
  1483. goto output_mode;
  1484. }
  1485. switch (esd_config->status_mode) {
  1486. case ESD_MODE_REG_READ:
  1487. rc = snprintf(buf, len, "reg_read");
  1488. break;
  1489. case ESD_MODE_PANEL_TE:
  1490. rc = snprintf(buf, len, "te_signal_check");
  1491. break;
  1492. case ESD_MODE_SW_SIM_FAILURE:
  1493. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1494. break;
  1495. case ESD_MODE_SW_SIM_SUCCESS:
  1496. rc = snprintf(buf, len, "esd_sw_sim_success");
  1497. break;
  1498. default:
  1499. rc = snprintf(buf, len, "invalid");
  1500. break;
  1501. }
  1502. output_mode:
  1503. if (!rc) {
  1504. rc = -EINVAL;
  1505. goto error;
  1506. }
  1507. if (copy_to_user(user_buf, buf, len)) {
  1508. rc = -EFAULT;
  1509. goto error;
  1510. }
  1511. *ppos += len;
  1512. error:
  1513. kfree(buf);
  1514. return len;
  1515. }
  1516. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1517. const char __user *user_buf,
  1518. size_t user_len,
  1519. loff_t *ppos)
  1520. {
  1521. struct dsi_display *display = file->private_data;
  1522. struct dsi_display_ctrl *display_ctrl;
  1523. char *buf;
  1524. int rc = 0;
  1525. u32 line = 0, window = 0;
  1526. size_t len;
  1527. int i;
  1528. if (!display)
  1529. return -ENODEV;
  1530. if (*ppos)
  1531. return 0;
  1532. buf = kzalloc(256, GFP_KERNEL);
  1533. if (ZERO_OR_NULL_PTR(buf))
  1534. return -ENOMEM;
  1535. len = min_t(size_t, user_len, 255);
  1536. if (copy_from_user(buf, user_buf, len)) {
  1537. rc = -EINVAL;
  1538. goto error;
  1539. }
  1540. buf[len] = '\0'; /* terminate the string */
  1541. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1542. return -EFAULT;
  1543. display_for_each_ctrl(i, display) {
  1544. struct dsi_ctrl *ctrl;
  1545. display_ctrl = &display->ctrl[i];
  1546. if (!display_ctrl->ctrl)
  1547. continue;
  1548. ctrl = display_ctrl->ctrl;
  1549. ctrl->host_config.common_config.dma_sched_line = line;
  1550. ctrl->host_config.common_config.dma_sched_window = window;
  1551. }
  1552. rc = len;
  1553. error:
  1554. kfree(buf);
  1555. return rc;
  1556. }
  1557. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1558. char __user *user_buf,
  1559. size_t user_len,
  1560. loff_t *ppos)
  1561. {
  1562. struct dsi_display *display = file->private_data;
  1563. struct dsi_display_ctrl *m_ctrl;
  1564. struct dsi_ctrl *ctrl;
  1565. char *buf;
  1566. u32 len = 0;
  1567. int rc = 0;
  1568. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1569. if (!display)
  1570. return -ENODEV;
  1571. if (*ppos)
  1572. return 0;
  1573. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1574. ctrl = m_ctrl->ctrl;
  1575. buf = kzalloc(max_len, GFP_KERNEL);
  1576. if (ZERO_OR_NULL_PTR(buf))
  1577. return -ENOMEM;
  1578. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1579. ctrl->host_config.common_config.dma_sched_line);
  1580. len += scnprintf((buf + len), max_len - len,
  1581. "Schedule command window width: %d\n",
  1582. ctrl->host_config.common_config.dma_sched_window);
  1583. if (len > max_len)
  1584. len = max_len;
  1585. if (copy_to_user(user_buf, buf, len)) {
  1586. rc = -EFAULT;
  1587. goto error;
  1588. }
  1589. *ppos += len;
  1590. error:
  1591. kfree(buf);
  1592. return len;
  1593. }
  1594. static const struct file_operations dump_info_fops = {
  1595. .open = simple_open,
  1596. .read = debugfs_dump_info_read,
  1597. };
  1598. static const struct file_operations misr_data_fops = {
  1599. .open = simple_open,
  1600. .read = debugfs_misr_read,
  1601. .write = debugfs_misr_setup,
  1602. };
  1603. static const struct file_operations esd_trigger_fops = {
  1604. .open = simple_open,
  1605. .write = debugfs_esd_trigger_check,
  1606. };
  1607. static const struct file_operations esd_check_mode_fops = {
  1608. .open = simple_open,
  1609. .write = debugfs_alter_esd_check_mode,
  1610. .read = debugfs_read_esd_check_mode,
  1611. };
  1612. static const struct file_operations dsi_command_scheduling_fops = {
  1613. .open = simple_open,
  1614. .write = debugfs_update_cmd_scheduling_params,
  1615. .read = debugfs_read_cmd_scheduling_params,
  1616. };
  1617. static int dsi_display_debugfs_init(struct dsi_display *display)
  1618. {
  1619. int rc = 0;
  1620. struct dentry *dir, *dump_file, *misr_data;
  1621. char name[MAX_NAME_SIZE];
  1622. char panel_name[SEC_PANEL_NAME_MAX_LEN];
  1623. char secondary_panel_str[] = "_secondary";
  1624. int i;
  1625. strlcpy(panel_name, display->name, SEC_PANEL_NAME_MAX_LEN);
  1626. if (strcmp(display->display_type, "secondary") == 0)
  1627. strlcat(panel_name, secondary_panel_str, SEC_PANEL_NAME_MAX_LEN);
  1628. dir = debugfs_create_dir(panel_name, NULL);
  1629. if (IS_ERR_OR_NULL(dir)) {
  1630. rc = PTR_ERR(dir);
  1631. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1632. display->name, rc);
  1633. goto error;
  1634. }
  1635. dump_file = debugfs_create_file("dump_info",
  1636. 0400,
  1637. dir,
  1638. display,
  1639. &dump_info_fops);
  1640. if (IS_ERR_OR_NULL(dump_file)) {
  1641. rc = PTR_ERR(dump_file);
  1642. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1643. display->name, rc);
  1644. goto error_remove_dir;
  1645. }
  1646. dump_file = debugfs_create_file("esd_trigger",
  1647. 0644,
  1648. dir,
  1649. display,
  1650. &esd_trigger_fops);
  1651. if (IS_ERR_OR_NULL(dump_file)) {
  1652. rc = PTR_ERR(dump_file);
  1653. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1654. display->name, rc);
  1655. goto error_remove_dir;
  1656. }
  1657. dump_file = debugfs_create_file("esd_check_mode",
  1658. 0644,
  1659. dir,
  1660. display,
  1661. &esd_check_mode_fops);
  1662. if (IS_ERR_OR_NULL(dump_file)) {
  1663. rc = PTR_ERR(dump_file);
  1664. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1665. display->name, rc);
  1666. goto error_remove_dir;
  1667. }
  1668. dump_file = debugfs_create_file("cmd_sched_params",
  1669. 0644,
  1670. dir,
  1671. display,
  1672. &dsi_command_scheduling_fops);
  1673. if (IS_ERR_OR_NULL(dump_file)) {
  1674. rc = PTR_ERR(dump_file);
  1675. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1676. display->name, rc);
  1677. goto error_remove_dir;
  1678. }
  1679. misr_data = debugfs_create_file("misr_data",
  1680. 0600,
  1681. dir,
  1682. display,
  1683. &misr_data_fops);
  1684. if (IS_ERR_OR_NULL(misr_data)) {
  1685. rc = PTR_ERR(misr_data);
  1686. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1687. display->name, rc);
  1688. goto error_remove_dir;
  1689. }
  1690. display_for_each_ctrl(i, display) {
  1691. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1692. if (!phy || !phy->name)
  1693. continue;
  1694. snprintf(name, ARRAY_SIZE(name),
  1695. "%s_allow_phy_power_off", phy->name);
  1696. debugfs_create_bool(name, 0600, dir, &phy->allow_phy_power_off);
  1697. snprintf(name, ARRAY_SIZE(name),
  1698. "%s_regulator_min_datarate_bps", phy->name);
  1699. debugfs_create_u32(name, 0600, dir, &phy->regulator_min_datarate_bps);
  1700. }
  1701. debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1702. &display->panel->ulps_feature_enabled);
  1703. debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1704. &display->panel->ulps_suspend_enabled);
  1705. debugfs_create_bool("ulps_status", 0400, dir, &display->ulps_enabled);
  1706. debugfs_create_u32("clk_gating_config", 0600, dir, &display->clk_gating_config);
  1707. display->root = dir;
  1708. dsi_parser_dbg_init(display->parser, dir);
  1709. return rc;
  1710. error_remove_dir:
  1711. debugfs_remove(dir);
  1712. error:
  1713. return rc;
  1714. }
  1715. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1716. {
  1717. if (display->root) {
  1718. debugfs_remove_recursive(display->root);
  1719. display->root = NULL;
  1720. }
  1721. return 0;
  1722. }
  1723. #else
  1724. static int dsi_display_debugfs_init(struct dsi_display *display)
  1725. {
  1726. return 0;
  1727. }
  1728. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1729. {
  1730. return 0;
  1731. }
  1732. #endif /* CONFIG_DEBUG_FS */
  1733. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1734. struct dsi_display_mode *mode)
  1735. {
  1736. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1737. bool is_split_link = host->split_link.enabled;
  1738. u32 sublinks_count = host->split_link.num_sublinks;
  1739. if (is_split_link && sublinks_count > 1) {
  1740. mode->timing.h_active /= sublinks_count;
  1741. mode->timing.h_front_porch /= sublinks_count;
  1742. mode->timing.h_sync_width /= sublinks_count;
  1743. mode->timing.h_back_porch /= sublinks_count;
  1744. mode->timing.h_skew /= sublinks_count;
  1745. mode->pixel_clk_khz /= sublinks_count;
  1746. } else {
  1747. if (mode->priv_info->dsc_enabled)
  1748. mode->priv_info->dsc.config.pic_width =
  1749. mode->timing.h_active;
  1750. mode->timing.h_active /= display->ctrl_count;
  1751. mode->timing.h_front_porch /= display->ctrl_count;
  1752. mode->timing.h_sync_width /= display->ctrl_count;
  1753. mode->timing.h_back_porch /= display->ctrl_count;
  1754. mode->timing.h_skew /= display->ctrl_count;
  1755. mode->pixel_clk_khz /= display->ctrl_count;
  1756. }
  1757. }
  1758. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1759. bool enable)
  1760. {
  1761. /* TODO: make checks based on cont. splash */
  1762. DSI_DEBUG("checking ulps req validity\n");
  1763. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1764. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1765. return false;
  1766. }
  1767. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1768. !display->panel->ulps_suspend_enabled) {
  1769. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1770. return false;
  1771. }
  1772. if (!dsi_panel_initialized(display->panel) &&
  1773. !display->panel->ulps_suspend_enabled) {
  1774. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1775. return false;
  1776. }
  1777. if (enable && display->ulps_enabled) {
  1778. DSI_DEBUG("ULPS already enabled\n");
  1779. return false;
  1780. } else if (!enable && !display->ulps_enabled) {
  1781. DSI_DEBUG("ULPS already disabled\n");
  1782. return false;
  1783. }
  1784. /*
  1785. * No need to enter ULPS when transitioning from splash screen to
  1786. * boot animation or trusted vm environments since it is expected
  1787. * that the clocks would be turned right back on.
  1788. */
  1789. if (enable && is_skip_op_required(display))
  1790. return false;
  1791. return true;
  1792. }
  1793. /**
  1794. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1795. * @dsi_display: DSI display handle.
  1796. * @enable: enable/disable ULPS.
  1797. *
  1798. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1799. *
  1800. * Return: error code.
  1801. */
  1802. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1803. {
  1804. int rc = 0;
  1805. int i = 0;
  1806. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1807. if (!display) {
  1808. DSI_ERR("Invalid params\n");
  1809. return -EINVAL;
  1810. }
  1811. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1812. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1813. __func__, enable);
  1814. return 0;
  1815. }
  1816. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1817. /*
  1818. * ULPS entry-exit can be either through the DSI controller or
  1819. * the DSI PHY depending on hardware variation. For some chipsets,
  1820. * both controller version and phy version ulps entry-exit ops can
  1821. * be present. To handle such cases, send ulps request through PHY,
  1822. * if ulps request is handled in PHY, then no need to send request
  1823. * through controller.
  1824. */
  1825. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1826. display->clamp_enabled);
  1827. if (rc == DSI_PHY_ULPS_ERROR) {
  1828. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1829. return -EINVAL;
  1830. }
  1831. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1832. display_for_each_ctrl(i, display) {
  1833. ctrl = &display->ctrl[i];
  1834. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1835. continue;
  1836. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1837. enable, display->clamp_enabled);
  1838. if (rc == DSI_PHY_ULPS_ERROR) {
  1839. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1840. enable);
  1841. return -EINVAL;
  1842. }
  1843. }
  1844. }
  1845. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1846. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1847. if (rc) {
  1848. DSI_ERR("Ulps controller state change(%d) failed\n",
  1849. enable);
  1850. return rc;
  1851. }
  1852. display_for_each_ctrl(i, display) {
  1853. ctrl = &display->ctrl[i];
  1854. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1855. continue;
  1856. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1857. if (rc) {
  1858. DSI_ERR("Ulps controller state change(%d) failed\n",
  1859. enable);
  1860. return rc;
  1861. }
  1862. }
  1863. }
  1864. display->ulps_enabled = enable;
  1865. return 0;
  1866. }
  1867. /**
  1868. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1869. * @dsi_display: DSI display handle.
  1870. * @enable: enable/disable clamping.
  1871. *
  1872. * Return: error code.
  1873. */
  1874. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1875. {
  1876. int rc = 0;
  1877. int i = 0;
  1878. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1879. bool ulps_enabled = false;
  1880. if (!display) {
  1881. DSI_ERR("Invalid params\n");
  1882. return -EINVAL;
  1883. }
  1884. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1885. ulps_enabled = display->ulps_enabled;
  1886. /*
  1887. * Clamp control can be either through the DSI controller or
  1888. * the DSI PHY depending on hardware variation
  1889. */
  1890. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1891. if (rc) {
  1892. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1893. return rc;
  1894. }
  1895. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1896. if (rc) {
  1897. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1898. return rc;
  1899. }
  1900. display_for_each_ctrl(i, display) {
  1901. ctrl = &display->ctrl[i];
  1902. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1903. continue;
  1904. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1905. if (rc) {
  1906. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1907. return rc;
  1908. }
  1909. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1910. if (rc) {
  1911. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1912. enable);
  1913. return rc;
  1914. }
  1915. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1916. enable ? "enabled" : "disabled", i);
  1917. }
  1918. display->clamp_enabled = enable;
  1919. return 0;
  1920. }
  1921. /**
  1922. * dsi_display_setup_ctrl() - setup DSI controller.
  1923. * @dsi_display: DSI display handle.
  1924. *
  1925. * Return: error code.
  1926. */
  1927. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1928. {
  1929. int rc = 0;
  1930. int i = 0;
  1931. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1932. if (!display) {
  1933. DSI_ERR("Invalid params\n");
  1934. return -EINVAL;
  1935. }
  1936. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1937. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1938. if (rc) {
  1939. DSI_ERR("DSI controller setup failed\n");
  1940. return rc;
  1941. }
  1942. display_for_each_ctrl(i, display) {
  1943. ctrl = &display->ctrl[i];
  1944. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1945. continue;
  1946. rc = dsi_ctrl_setup(ctrl->ctrl);
  1947. if (rc) {
  1948. DSI_ERR("DSI controller setup failed\n");
  1949. return rc;
  1950. }
  1951. }
  1952. return 0;
  1953. }
  1954. static int dsi_display_phy_enable(struct dsi_display *display);
  1955. /**
  1956. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1957. * @dsi_display: DSI display handle.
  1958. * @mmss_clamp: True if clamp is enabled.
  1959. *
  1960. * Return: error code.
  1961. */
  1962. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1963. bool mmss_clamp)
  1964. {
  1965. int rc = 0;
  1966. int i = 0;
  1967. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1968. if (!display) {
  1969. DSI_ERR("Invalid params\n");
  1970. return -EINVAL;
  1971. }
  1972. if (mmss_clamp && !display->phy_idle_power_off) {
  1973. dsi_display_phy_enable(display);
  1974. return 0;
  1975. }
  1976. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1977. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1978. if (rc) {
  1979. DSI_ERR("DSI controller setup failed\n");
  1980. return rc;
  1981. }
  1982. display_for_each_ctrl(i, display) {
  1983. ctrl = &display->ctrl[i];
  1984. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1985. continue;
  1986. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1987. if (rc) {
  1988. DSI_ERR("DSI controller setup failed\n");
  1989. return rc;
  1990. }
  1991. }
  1992. display->phy_idle_power_off = false;
  1993. return 0;
  1994. }
  1995. /**
  1996. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  1997. * @dsi_display: DSI display handle.
  1998. *
  1999. * Return: error code.
  2000. */
  2001. static int dsi_display_phy_idle_off(struct dsi_display *display)
  2002. {
  2003. int rc = 0;
  2004. int i = 0;
  2005. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2006. if (!display) {
  2007. DSI_ERR("Invalid params\n");
  2008. return -EINVAL;
  2009. }
  2010. display_for_each_ctrl(i, display) {
  2011. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  2012. if (!phy)
  2013. continue;
  2014. if (!phy->allow_phy_power_off) {
  2015. DSI_DEBUG("phy doesn't support this feature\n");
  2016. return 0;
  2017. }
  2018. }
  2019. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2020. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  2021. if (rc) {
  2022. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2023. display->name, rc);
  2024. return rc;
  2025. }
  2026. display_for_each_ctrl(i, display) {
  2027. ctrl = &display->ctrl[i];
  2028. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2029. continue;
  2030. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  2031. if (rc) {
  2032. DSI_ERR("DSI controller setup failed\n");
  2033. return rc;
  2034. }
  2035. }
  2036. display->phy_idle_power_off = true;
  2037. return 0;
  2038. }
  2039. void dsi_display_enable_event(struct drm_connector *connector,
  2040. struct dsi_display *display,
  2041. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  2042. bool enable)
  2043. {
  2044. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  2045. int i;
  2046. if (!display) {
  2047. DSI_ERR("invalid display\n");
  2048. return;
  2049. }
  2050. if (event_info)
  2051. event_info->event_idx = event_idx;
  2052. switch (event_idx) {
  2053. case SDE_CONN_EVENT_VID_DONE:
  2054. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  2055. break;
  2056. case SDE_CONN_EVENT_CMD_DONE:
  2057. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  2058. break;
  2059. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  2060. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  2061. if (event_info) {
  2062. display_for_each_ctrl(i, display)
  2063. display->ctrl[i].ctrl->recovery_cb =
  2064. *event_info;
  2065. }
  2066. break;
  2067. case SDE_CONN_EVENT_PANEL_ID:
  2068. if (event_info)
  2069. display_for_each_ctrl(i, display)
  2070. display->ctrl[i].ctrl->panel_id_cb
  2071. = *event_info;
  2072. dsi_display_panel_id_notification(display);
  2073. break;
  2074. default:
  2075. /* nothing to do */
  2076. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  2077. return;
  2078. }
  2079. if (enable) {
  2080. display_for_each_ctrl(i, display)
  2081. dsi_ctrl_enable_status_interrupt(
  2082. display->ctrl[i].ctrl, irq_status_idx,
  2083. event_info);
  2084. } else {
  2085. display_for_each_ctrl(i, display)
  2086. dsi_ctrl_disable_status_interrupt(
  2087. display->ctrl[i].ctrl, irq_status_idx);
  2088. }
  2089. }
  2090. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  2091. {
  2092. int rc = 0;
  2093. int i;
  2094. struct dsi_display_ctrl *ctrl;
  2095. /* Sequence does not matter for split dsi usecases */
  2096. display_for_each_ctrl(i, display) {
  2097. ctrl = &display->ctrl[i];
  2098. if (!ctrl->ctrl)
  2099. continue;
  2100. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2101. DSI_CTRL_POWER_VREG_ON);
  2102. if (rc) {
  2103. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2104. ctrl->ctrl->name, rc);
  2105. goto error;
  2106. }
  2107. }
  2108. return rc;
  2109. error:
  2110. for (i = i - 1; i >= 0; i--) {
  2111. ctrl = &display->ctrl[i];
  2112. if (!ctrl->ctrl)
  2113. continue;
  2114. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  2115. DSI_CTRL_POWER_VREG_OFF);
  2116. }
  2117. return rc;
  2118. }
  2119. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  2120. {
  2121. int rc = 0;
  2122. int i;
  2123. struct dsi_display_ctrl *ctrl;
  2124. /* Sequence does not matter for split dsi usecases */
  2125. display_for_each_ctrl(i, display) {
  2126. ctrl = &display->ctrl[i];
  2127. if (!ctrl->ctrl)
  2128. continue;
  2129. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2130. DSI_CTRL_POWER_VREG_OFF);
  2131. if (rc) {
  2132. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2133. ctrl->ctrl->name, rc);
  2134. goto error;
  2135. }
  2136. }
  2137. error:
  2138. return rc;
  2139. }
  2140. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  2141. unsigned int display_type)
  2142. {
  2143. char *boot_str = NULL;
  2144. char *str = NULL;
  2145. char *sw_te = NULL;
  2146. unsigned long cmdline_topology = NO_OVERRIDE;
  2147. unsigned long cmdline_timing = NO_OVERRIDE;
  2148. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2149. DSI_ERR("display_type=%d not supported\n", display_type);
  2150. goto end;
  2151. }
  2152. if (display_type == DSI_PRIMARY)
  2153. boot_str = dsi_display_primary;
  2154. else
  2155. boot_str = dsi_display_secondary;
  2156. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2157. if (sw_te)
  2158. display->sw_te_using_wd = true;
  2159. str = strnstr(boot_str, ":config", strlen(boot_str));
  2160. if (str) {
  2161. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2162. DSI_ERR("invalid config index override: %s\n",
  2163. boot_str);
  2164. goto end;
  2165. }
  2166. }
  2167. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2168. if (str) {
  2169. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2170. DSI_ERR("invalid timing index override: %s\n",
  2171. boot_str);
  2172. cmdline_topology = NO_OVERRIDE;
  2173. goto end;
  2174. }
  2175. }
  2176. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2177. end:
  2178. display->cmdline_topology = cmdline_topology;
  2179. display->cmdline_timing = cmdline_timing;
  2180. }
  2181. /**
  2182. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2183. *
  2184. * Return: returns error status
  2185. */
  2186. static int dsi_display_parse_boot_display_selection(void)
  2187. {
  2188. char *pos = NULL;
  2189. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2190. int i, j;
  2191. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2192. strlcpy(disp_buf, boot_displays[i].boot_param,
  2193. MAX_CMDLINE_PARAM_LEN);
  2194. pos = strnstr(disp_buf, ":", strlen(disp_buf));
  2195. /* Use ':' as a delimiter to retrieve the display name */
  2196. if (!pos) {
  2197. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2198. continue;
  2199. }
  2200. for (j = 0; (disp_buf + j) < pos; j++)
  2201. boot_displays[i].name[j] = *(disp_buf + j);
  2202. boot_displays[i].name[j] = '\0';
  2203. boot_displays[i].boot_disp_en = true;
  2204. }
  2205. return 0;
  2206. }
  2207. static int dsi_display_phy_power_on(struct dsi_display *display)
  2208. {
  2209. int rc = 0;
  2210. int i;
  2211. struct dsi_display_ctrl *ctrl;
  2212. /* Sequence does not matter for split dsi usecases */
  2213. display_for_each_ctrl(i, display) {
  2214. ctrl = &display->ctrl[i];
  2215. if (!ctrl->ctrl)
  2216. continue;
  2217. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2218. if (rc) {
  2219. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2220. ctrl->phy->name, rc);
  2221. goto error;
  2222. }
  2223. }
  2224. return rc;
  2225. error:
  2226. for (i = i - 1; i >= 0; i--) {
  2227. ctrl = &display->ctrl[i];
  2228. if (!ctrl->phy)
  2229. continue;
  2230. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2231. }
  2232. return rc;
  2233. }
  2234. static int dsi_display_phy_power_off(struct dsi_display *display)
  2235. {
  2236. int rc = 0;
  2237. int i;
  2238. struct dsi_display_ctrl *ctrl;
  2239. /* Sequence does not matter for split dsi usecases */
  2240. display_for_each_ctrl(i, display) {
  2241. ctrl = &display->ctrl[i];
  2242. if (!ctrl->phy)
  2243. continue;
  2244. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2245. if (rc) {
  2246. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2247. ctrl->ctrl->name, rc);
  2248. goto error;
  2249. }
  2250. }
  2251. error:
  2252. return rc;
  2253. }
  2254. static int dsi_display_set_clk_src(struct dsi_display *display, bool set_xo)
  2255. {
  2256. int rc = 0;
  2257. int i;
  2258. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2259. struct dsi_ctrl_clk_info *info;
  2260. if (display->trusted_vm_env)
  2261. return 0;
  2262. /*
  2263. * In case of split DSI usecases, the clock for master controller should
  2264. * be enabled before the other controller. Master controller in the
  2265. * clock context refers to the controller that sources the clock. While turning off the
  2266. * clocks, the source is set to xo.
  2267. */
  2268. m_ctrl = &display->ctrl[display->clk_master_idx];
  2269. info = &m_ctrl->ctrl->clk_info;
  2270. if (!set_xo)
  2271. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.pll_clks);
  2272. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2273. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &info->xo_clk);
  2274. if (rc) {
  2275. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n", display->name, rc);
  2276. return rc;
  2277. }
  2278. /* Set source for the rest of the controllers */
  2279. display_for_each_ctrl(i, display) {
  2280. ctrl = &display->ctrl[i];
  2281. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2282. continue;
  2283. info = &ctrl->ctrl->clk_info;
  2284. if (!set_xo)
  2285. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &display->clock_info.pll_clks);
  2286. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2287. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &info->xo_clk);
  2288. if (rc) {
  2289. DSI_ERR("[%s] failed to set source clocks, rc=%d\n", display->name, rc);
  2290. return rc;
  2291. }
  2292. }
  2293. return 0;
  2294. }
  2295. static int dsi_display_phy_pll_enable(struct dsi_display *display)
  2296. {
  2297. int rc = 0;
  2298. struct dsi_display_ctrl *m_ctrl;
  2299. m_ctrl = &display->ctrl[display->clk_master_idx];
  2300. if (!m_ctrl->phy) {
  2301. DSI_ERR("[%s] PHY not found\n", display->name);
  2302. return -EINVAL;
  2303. }
  2304. /*
  2305. * It is recommended to turn on the PLL before switching parent
  2306. * of RCG to PLL because when RCG is on, both the old and new
  2307. * sources should be on while switching the RCG parent.
  2308. *
  2309. * Note: Branch clocks and in turn RCG might not get turned off
  2310. * during clock disable sequence if there is a vote from dispcc
  2311. * or any of its other consumers.
  2312. */
  2313. rc = dsi_phy_pll_toggle(m_ctrl->phy, true);
  2314. if (rc)
  2315. return rc;
  2316. return dsi_display_set_clk_src(display, false);
  2317. }
  2318. static int dsi_display_phy_pll_disable(struct dsi_display *display)
  2319. {
  2320. int rc = 0;
  2321. struct dsi_display_ctrl *m_ctrl;
  2322. /*
  2323. * It is recommended to turn off the PLL after switching parent
  2324. * of RCG to PLL because when RCG is on, both the old and new
  2325. * sources should be on while switching the RCG parent.
  2326. */
  2327. rc = dsi_display_set_clk_src(display, true);
  2328. if (rc)
  2329. return rc;
  2330. m_ctrl = &display->ctrl[display->clk_master_idx];
  2331. if (!m_ctrl->phy) {
  2332. DSI_ERR("[%s] PHY not found\n", display->name);
  2333. return -EINVAL;
  2334. }
  2335. return dsi_phy_pll_toggle(m_ctrl->phy, false);
  2336. }
  2337. int dsi_display_phy_pll_toggle(void *priv, bool prepare)
  2338. {
  2339. struct dsi_display *display = priv;
  2340. if (!display) {
  2341. DSI_ERR("invalid arguments\n");
  2342. return -EINVAL;
  2343. }
  2344. if (is_skip_op_required(display) || phy_pll_bypass(display))
  2345. return 0;
  2346. if (prepare)
  2347. return dsi_display_phy_pll_enable(display);
  2348. else
  2349. return dsi_display_phy_pll_disable(display);
  2350. }
  2351. int dsi_display_phy_configure(void *priv, bool commit)
  2352. {
  2353. int rc = 0;
  2354. struct dsi_display *display = priv;
  2355. struct dsi_display_ctrl *m_ctrl;
  2356. struct dsi_pll_resource *pll_res;
  2357. struct dsi_ctrl *ctrl;
  2358. if (!display) {
  2359. DSI_ERR("invalid arguments\n");
  2360. return -EINVAL;
  2361. }
  2362. if (is_skip_op_required(display))
  2363. return 0;
  2364. m_ctrl = &display->ctrl[display->clk_master_idx];
  2365. if ((!m_ctrl->phy) || (!m_ctrl->ctrl)) {
  2366. DSI_ERR("[%s] PHY not found\n", display->name);
  2367. return -EINVAL;
  2368. }
  2369. pll_res = m_ctrl->phy->pll;
  2370. if (!pll_res) {
  2371. DSI_ERR("[%s] PLL res not found\n", display->name);
  2372. return -EINVAL;
  2373. }
  2374. ctrl = m_ctrl->ctrl;
  2375. pll_res->byteclk_rate = ctrl->clk_freq.byte_clk_rate;
  2376. pll_res->pclk_rate = ctrl->clk_freq.pix_clk_rate;
  2377. rc = dsi_phy_configure(m_ctrl->phy, commit);
  2378. return rc;
  2379. }
  2380. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2381. bool enable)
  2382. {
  2383. int rc = 0;
  2384. int i;
  2385. struct dsi_display_ctrl *ctrl;
  2386. display_for_each_ctrl(i, display) {
  2387. ctrl = &display->ctrl[i];
  2388. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2389. if (rc) {
  2390. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2391. display->name, enable ? "mask" : "unmask", rc);
  2392. return rc;
  2393. }
  2394. }
  2395. return 0;
  2396. }
  2397. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2398. {
  2399. struct dsi_display_ctrl *ctrl;
  2400. int i;
  2401. if (!display)
  2402. return;
  2403. display_for_each_ctrl(i, display) {
  2404. ctrl = &display->ctrl[i];
  2405. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2406. }
  2407. /*
  2408. * After retime buffer synchronization we need to turn of clk_en_sel
  2409. * bit on each phy. Avoid this for Cphy.
  2410. */
  2411. if (dsi_is_type_cphy(&display->panel->host_config))
  2412. return;
  2413. display_for_each_ctrl(i, display) {
  2414. ctrl = &display->ctrl[i];
  2415. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2416. }
  2417. }
  2418. static int dsi_display_ctrl_update(struct dsi_display *display)
  2419. {
  2420. int rc = 0;
  2421. int i;
  2422. struct dsi_display_ctrl *ctrl;
  2423. display_for_each_ctrl(i, display) {
  2424. ctrl = &display->ctrl[i];
  2425. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2426. if (rc) {
  2427. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2428. display->name, i, rc);
  2429. goto error_host_deinit;
  2430. }
  2431. }
  2432. return 0;
  2433. error_host_deinit:
  2434. for (i = i - 1; i >= 0; i--) {
  2435. ctrl = &display->ctrl[i];
  2436. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2437. }
  2438. return rc;
  2439. }
  2440. static int dsi_display_ctrl_init(struct dsi_display *display)
  2441. {
  2442. int rc = 0;
  2443. int i;
  2444. struct dsi_display_ctrl *ctrl;
  2445. bool skip_op = is_skip_op_required(display);
  2446. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2447. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2448. * we will programe DSI controller as part of core clock enable.
  2449. * After that we should not re-configure DSI controller again here for
  2450. * usecases where we are resuming from ulps suspend as it might put
  2451. * the HW in bad state.
  2452. */
  2453. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2454. display_for_each_ctrl(i, display) {
  2455. ctrl = &display->ctrl[i];
  2456. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2457. if (rc) {
  2458. DSI_ERR(
  2459. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2460. display->name, i, skip_op, rc);
  2461. goto error_host_deinit;
  2462. }
  2463. }
  2464. } else {
  2465. display_for_each_ctrl(i, display) {
  2466. ctrl = &display->ctrl[i];
  2467. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2468. DSI_CTRL_OP_HOST_INIT,
  2469. true);
  2470. if (rc)
  2471. DSI_DEBUG("host init update failed rc=%d\n",
  2472. rc);
  2473. }
  2474. }
  2475. return rc;
  2476. error_host_deinit:
  2477. for (i = i - 1; i >= 0; i--) {
  2478. ctrl = &display->ctrl[i];
  2479. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2480. }
  2481. return rc;
  2482. }
  2483. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2484. {
  2485. int rc = 0;
  2486. int i;
  2487. struct dsi_display_ctrl *ctrl;
  2488. display_for_each_ctrl(i, display) {
  2489. ctrl = &display->ctrl[i];
  2490. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2491. if (rc) {
  2492. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2493. display->name, i, rc);
  2494. }
  2495. }
  2496. return rc;
  2497. }
  2498. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2499. {
  2500. int rc = 0;
  2501. int i;
  2502. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2503. bool skip_op = is_skip_op_required(display);
  2504. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2505. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2506. DSI_CTRL_ENGINE_ON, skip_op);
  2507. if (rc) {
  2508. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2509. display->name, skip_op, rc);
  2510. goto error;
  2511. }
  2512. display_for_each_ctrl(i, display) {
  2513. ctrl = &display->ctrl[i];
  2514. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2515. continue;
  2516. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2517. DSI_CTRL_ENGINE_ON, skip_op);
  2518. if (rc) {
  2519. DSI_ERR(
  2520. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2521. display->name, skip_op, rc);
  2522. goto error_disable_master;
  2523. }
  2524. }
  2525. return rc;
  2526. error_disable_master:
  2527. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2528. DSI_CTRL_ENGINE_OFF, skip_op);
  2529. error:
  2530. return rc;
  2531. }
  2532. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2533. {
  2534. int rc = 0;
  2535. int i;
  2536. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2537. bool skip_op = is_skip_op_required(display);
  2538. /*
  2539. * This is a defensive check. In reality as this is called after panel OFF commands, which
  2540. * can never be ASYNC, the controller post_tx_queued flag will never be set when this API
  2541. * is called.
  2542. */
  2543. display_for_each_ctrl(i, display) {
  2544. ctrl = &display->ctrl[i];
  2545. if (!ctrl->ctrl || !(ctrl->ctrl->post_tx_queued))
  2546. continue;
  2547. flush_workqueue(display->post_cmd_tx_workq);
  2548. cancel_work_sync(&ctrl->ctrl->post_cmd_tx_work);
  2549. ctrl->ctrl->post_tx_queued = false;
  2550. }
  2551. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2552. /*
  2553. * For platforms where ULPS is controlled by DSI controller block,
  2554. * do not disable dsi controller block if lanes are to be
  2555. * kept in ULPS during suspend. So just update the SW state
  2556. * and return early.
  2557. */
  2558. if (display->panel->ulps_suspend_enabled &&
  2559. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2560. display_for_each_ctrl(i, display) {
  2561. ctrl = &display->ctrl[i];
  2562. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2563. DSI_CTRL_OP_HOST_ENGINE,
  2564. false);
  2565. if (rc)
  2566. DSI_DEBUG("host state update failed %d\n", rc);
  2567. }
  2568. return rc;
  2569. }
  2570. display_for_each_ctrl(i, display) {
  2571. ctrl = &display->ctrl[i];
  2572. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2573. continue;
  2574. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2575. DSI_CTRL_ENGINE_OFF, skip_op);
  2576. if (rc)
  2577. DSI_ERR(
  2578. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2579. display->name, skip_op, rc);
  2580. }
  2581. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2582. DSI_CTRL_ENGINE_OFF, skip_op);
  2583. if (rc) {
  2584. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2585. display->name, skip_op, rc);
  2586. goto error;
  2587. }
  2588. error:
  2589. return rc;
  2590. }
  2591. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2592. {
  2593. int rc = 0;
  2594. int i;
  2595. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2596. bool skip_op = is_skip_op_required(display);
  2597. m_ctrl = &display->ctrl[display->video_master_idx];
  2598. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2599. DSI_CTRL_ENGINE_ON, skip_op);
  2600. if (rc) {
  2601. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2602. display->name, skip_op, rc);
  2603. goto error;
  2604. }
  2605. display_for_each_ctrl(i, display) {
  2606. ctrl = &display->ctrl[i];
  2607. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2608. continue;
  2609. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2610. DSI_CTRL_ENGINE_ON, skip_op);
  2611. if (rc) {
  2612. DSI_ERR(
  2613. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2614. display->name, skip_op, rc);
  2615. goto error_disable_master;
  2616. }
  2617. }
  2618. return rc;
  2619. error_disable_master:
  2620. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2621. DSI_CTRL_ENGINE_OFF, skip_op);
  2622. error:
  2623. return rc;
  2624. }
  2625. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2626. {
  2627. int rc = 0;
  2628. int i;
  2629. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2630. bool skip_op = is_skip_op_required(display);
  2631. m_ctrl = &display->ctrl[display->video_master_idx];
  2632. display_for_each_ctrl(i, display) {
  2633. ctrl = &display->ctrl[i];
  2634. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2635. continue;
  2636. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2637. DSI_CTRL_ENGINE_OFF, skip_op);
  2638. if (rc)
  2639. DSI_ERR(
  2640. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2641. display->name, skip_op, rc);
  2642. }
  2643. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2644. DSI_CTRL_ENGINE_OFF, skip_op);
  2645. if (rc)
  2646. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2647. display->name, skip_op, rc);
  2648. return rc;
  2649. }
  2650. static int dsi_display_phy_enable(struct dsi_display *display)
  2651. {
  2652. int rc = 0;
  2653. int i;
  2654. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2655. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2656. bool skip_op = is_skip_op_required(display);
  2657. m_ctrl = &display->ctrl[display->clk_master_idx];
  2658. if (display->ctrl_count > 1)
  2659. m_src = DSI_PLL_SOURCE_NATIVE;
  2660. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2661. m_src, true, skip_op);
  2662. if (rc) {
  2663. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2664. display->name, skip_op, rc);
  2665. goto error;
  2666. }
  2667. display_for_each_ctrl(i, display) {
  2668. ctrl = &display->ctrl[i];
  2669. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2670. continue;
  2671. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2672. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2673. if (rc) {
  2674. DSI_ERR(
  2675. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2676. display->name, skip_op, rc);
  2677. goto error_disable_master;
  2678. }
  2679. }
  2680. return rc;
  2681. error_disable_master:
  2682. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2683. error:
  2684. return rc;
  2685. }
  2686. static int dsi_display_phy_disable(struct dsi_display *display)
  2687. {
  2688. int rc = 0;
  2689. int i;
  2690. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2691. bool skip_op = is_skip_op_required(display);
  2692. m_ctrl = &display->ctrl[display->clk_master_idx];
  2693. display_for_each_ctrl(i, display) {
  2694. ctrl = &display->ctrl[i];
  2695. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2696. continue;
  2697. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2698. if (rc)
  2699. DSI_ERR(
  2700. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2701. display->name, skip_op, rc);
  2702. }
  2703. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2704. if (rc)
  2705. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2706. display->name, skip_op, rc);
  2707. return rc;
  2708. }
  2709. static int dsi_display_wake_up(struct dsi_display *display)
  2710. {
  2711. return 0;
  2712. }
  2713. static int dsi_display_broadcast_cmd(struct dsi_display *display, struct dsi_cmd_desc *cmd)
  2714. {
  2715. int rc = 0;
  2716. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2717. int i;
  2718. u32 flags = 0;
  2719. if (phy_pll_bypass(display))
  2720. return 0;
  2721. /*
  2722. * 1. Setup commands in FIFO
  2723. * 2. Trigger commands
  2724. */
  2725. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2726. display_for_each_ctrl(i, display) {
  2727. ctrl = &display->ctrl[i];
  2728. flags = cmd->ctrl_flags;
  2729. if (ctrl == m_ctrl)
  2730. flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2731. rc = dsi_ctrl_transfer_prepare(ctrl->ctrl, flags);
  2732. if (rc) {
  2733. DSI_ERR("[%s] prepare for cmd transfer failed,rc=%d\n",
  2734. display->name, rc);
  2735. if (ctrl != m_ctrl)
  2736. dsi_ctrl_transfer_unprepare(m_ctrl->ctrl, flags |
  2737. DSI_CTRL_CMD_BROADCAST_MASTER);
  2738. return rc;
  2739. }
  2740. }
  2741. cmd->ctrl_flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2742. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  2743. if (rc) {
  2744. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2745. display->name, rc);
  2746. goto error;
  2747. }
  2748. cmd->ctrl_flags &= ~DSI_CTRL_CMD_BROADCAST_MASTER;
  2749. display_for_each_ctrl(i, display) {
  2750. ctrl = &display->ctrl[i];
  2751. if (ctrl == m_ctrl)
  2752. continue;
  2753. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, cmd);
  2754. if (rc) {
  2755. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2756. display->name, rc);
  2757. goto error;
  2758. }
  2759. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, cmd->ctrl_flags);
  2760. if (rc) {
  2761. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2762. display->name, rc);
  2763. goto error;
  2764. }
  2765. }
  2766. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, cmd->ctrl_flags | DSI_CTRL_CMD_BROADCAST_MASTER);
  2767. if (rc) {
  2768. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2769. display->name, rc);
  2770. goto error;
  2771. }
  2772. error:
  2773. display_for_each_ctrl(i, display) {
  2774. ctrl = &display->ctrl[i];
  2775. flags = cmd->ctrl_flags;
  2776. if (ctrl == m_ctrl)
  2777. flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2778. dsi_ctrl_transfer_unprepare(ctrl->ctrl, flags);
  2779. }
  2780. return rc;
  2781. }
  2782. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2783. {
  2784. int rc = 0;
  2785. int i;
  2786. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2787. /*
  2788. * For continuous splash and trusted vm environment,
  2789. * ctrl states are updated separately and hence we do
  2790. * an early return
  2791. */
  2792. if (is_skip_op_required(display) || phy_pll_bypass(display)) {
  2793. DSI_DEBUG(
  2794. "cont splash/trusted vm use case, phy sw reset not required\n");
  2795. return 0;
  2796. }
  2797. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2798. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2799. if (rc) {
  2800. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2801. goto error;
  2802. }
  2803. display_for_each_ctrl(i, display) {
  2804. ctrl = &display->ctrl[i];
  2805. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2806. continue;
  2807. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2808. if (rc) {
  2809. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2810. display->name, rc);
  2811. goto error;
  2812. }
  2813. }
  2814. error:
  2815. return rc;
  2816. }
  2817. static int dsi_host_attach(struct mipi_dsi_host *host,
  2818. struct mipi_dsi_device *dsi)
  2819. {
  2820. return 0;
  2821. }
  2822. static int dsi_host_detach(struct mipi_dsi_host *host,
  2823. struct mipi_dsi_device *dsi)
  2824. {
  2825. return 0;
  2826. }
  2827. int dsi_host_transfer_sub(struct mipi_dsi_host *host, struct dsi_cmd_desc *cmd)
  2828. {
  2829. struct dsi_display *display;
  2830. int rc = 0;
  2831. if (!host || !cmd) {
  2832. DSI_ERR("Invalid params\n");
  2833. return 0;
  2834. }
  2835. display = to_dsi_display(host);
  2836. if (phy_pll_bypass(display))
  2837. return 0;
  2838. /* Avoid sending DCS commands when ESD recovery is pending */
  2839. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2840. DSI_DEBUG("ESD recovery pending\n");
  2841. return 0;
  2842. }
  2843. rc = dsi_display_wake_up(display);
  2844. if (rc) {
  2845. DSI_ERR("[%s] failed to wake up display, rc=%d\n", display->name, rc);
  2846. goto error;
  2847. }
  2848. if (display->tx_cmd_buf == NULL) {
  2849. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2850. if (rc) {
  2851. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2852. goto error;
  2853. }
  2854. }
  2855. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  2856. if (cmd->ctrl_flags & DSI_CTRL_CMD_BROADCAST) {
  2857. rc = dsi_display_broadcast_cmd(display, cmd);
  2858. if (rc) {
  2859. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n", display->name, rc);
  2860. goto error;
  2861. }
  2862. } else {
  2863. int idx = cmd->ctrl;
  2864. rc = dsi_ctrl_transfer_prepare(display->ctrl[idx].ctrl, cmd->ctrl_flags);
  2865. if (rc) {
  2866. DSI_ERR("failed to prepare for command transfer: %d\n", rc);
  2867. goto error;
  2868. }
  2869. rc = dsi_ctrl_cmd_transfer(display->ctrl[idx].ctrl, cmd);
  2870. if (rc)
  2871. DSI_ERR("[%s] cmd transfer failed, rc=%d\n", display->name, rc);
  2872. dsi_ctrl_transfer_unprepare(display->ctrl[idx].ctrl, cmd->ctrl_flags);
  2873. }
  2874. error:
  2875. return rc;
  2876. }
  2877. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg)
  2878. {
  2879. int rc = 0;
  2880. struct dsi_cmd_desc cmd;
  2881. if (!msg) {
  2882. DSI_ERR("Invalid params\n");
  2883. return 0;
  2884. }
  2885. memcpy(&cmd.msg, msg, sizeof(*msg));
  2886. cmd.ctrl = 0;
  2887. cmd.post_wait_ms = 0;
  2888. cmd.ctrl_flags = 0;
  2889. rc = dsi_host_transfer_sub(host, &cmd);
  2890. return rc;
  2891. }
  2892. static struct mipi_dsi_host_ops dsi_host_ops = {
  2893. .attach = dsi_host_attach,
  2894. .detach = dsi_host_detach,
  2895. .transfer = dsi_host_transfer,
  2896. };
  2897. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2898. {
  2899. int rc = 0;
  2900. struct mipi_dsi_host *host = &display->host;
  2901. host->dev = &display->pdev->dev;
  2902. host->ops = &dsi_host_ops;
  2903. rc = mipi_dsi_host_register(host);
  2904. if (rc) {
  2905. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2906. display->name, rc);
  2907. goto error;
  2908. }
  2909. error:
  2910. return rc;
  2911. }
  2912. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2913. {
  2914. int rc = 0;
  2915. struct mipi_dsi_host *host = &display->host;
  2916. mipi_dsi_host_unregister(host);
  2917. host->dev = NULL;
  2918. host->ops = NULL;
  2919. return rc;
  2920. }
  2921. static bool dsi_display_check_prefix(const char *clk_prefix,
  2922. const char *clk_name)
  2923. {
  2924. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2925. }
  2926. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2927. char *dsi_clk_name)
  2928. {
  2929. if (display->fw)
  2930. return dsi_parser_count_strings(display->parser_node,
  2931. dsi_clk_name);
  2932. else
  2933. return of_property_count_strings(display->panel_node,
  2934. dsi_clk_name);
  2935. }
  2936. static void dsi_display_get_clock_name(struct dsi_display *display,
  2937. char *dsi_clk_name, int index,
  2938. const char **clk_name)
  2939. {
  2940. if (display->fw)
  2941. dsi_parser_read_string_index(display->parser_node,
  2942. dsi_clk_name, index, clk_name);
  2943. else
  2944. of_property_read_string_index(display->panel_node,
  2945. dsi_clk_name, index, clk_name);
  2946. }
  2947. static int dsi_display_clocks_init(struct dsi_display *display)
  2948. {
  2949. int i, rc = 0, num_clk = 0;
  2950. const char *clk_name;
  2951. const char *pll_byte = "pll_byte", *pll_dsi = "pll_dsi";
  2952. struct clk *dsi_clk;
  2953. struct dsi_clk_link_set *pll = &display->clock_info.pll_clks;
  2954. char *dsi_clock_name;
  2955. if (!strcmp(display->display_type, "primary"))
  2956. dsi_clock_name = "qcom,dsi-select-clocks";
  2957. else
  2958. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2959. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2960. for (i = 0; i < num_clk; i++) {
  2961. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2962. &clk_name);
  2963. DSI_DEBUG("clock name:%s\n", clk_name);
  2964. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2965. if (IS_ERR_OR_NULL(dsi_clk)) {
  2966. rc = PTR_ERR(dsi_clk);
  2967. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2968. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2969. pll->byte_clk = NULL;
  2970. goto error;
  2971. }
  2972. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2973. pll->pixel_clk = NULL;
  2974. goto error;
  2975. }
  2976. }
  2977. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2978. pll->byte_clk = dsi_clk;
  2979. continue;
  2980. }
  2981. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2982. pll->pixel_clk = dsi_clk;
  2983. continue;
  2984. }
  2985. }
  2986. return 0;
  2987. error:
  2988. return rc;
  2989. }
  2990. static int dsi_display_clk_ctrl_cb(void *priv,
  2991. struct dsi_clk_ctrl_info clk_state_info)
  2992. {
  2993. int rc = 0;
  2994. struct dsi_display *display = NULL;
  2995. void *clk_handle = NULL;
  2996. if (!priv) {
  2997. DSI_ERR("Invalid params\n");
  2998. return -EINVAL;
  2999. }
  3000. display = priv;
  3001. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  3002. clk_handle = display->mdp_clk_handle;
  3003. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  3004. clk_handle = display->dsi_clk_handle;
  3005. } else {
  3006. DSI_ERR("invalid clk handle, return error\n");
  3007. return -EINVAL;
  3008. }
  3009. /*
  3010. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  3011. * to turn off DSI clocks.
  3012. */
  3013. rc = dsi_display_clk_ctrl(clk_handle,
  3014. clk_state_info.clk_type, clk_state_info.clk_state);
  3015. if (rc) {
  3016. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  3017. display->name, clk_state_info.clk_state,
  3018. clk_state_info.clk_type, rc);
  3019. return rc;
  3020. }
  3021. return 0;
  3022. }
  3023. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  3024. {
  3025. int i;
  3026. struct dsi_display_ctrl *ctrl;
  3027. if (!display)
  3028. return;
  3029. display_for_each_ctrl(i, display) {
  3030. ctrl = &display->ctrl[i];
  3031. if (!ctrl)
  3032. continue;
  3033. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  3034. }
  3035. }
  3036. static void dsi_display_cleanup_post_esd_failure(struct dsi_display *display)
  3037. {
  3038. int i = 0;
  3039. struct dsi_display_ctrl *ctrl;
  3040. display_for_each_ctrl(i, display) {
  3041. ctrl = &display->ctrl[i];
  3042. if (!ctrl->ctrl)
  3043. continue;
  3044. dsi_phy_lane_reset(ctrl->phy);
  3045. dsi_ctrl_soft_reset(ctrl->ctrl);
  3046. }
  3047. }
  3048. int dsi_pre_clkoff_cb(void *priv,
  3049. enum dsi_clk_type clk,
  3050. enum dsi_lclk_type l_type,
  3051. enum dsi_clk_state new_state)
  3052. {
  3053. int rc = 0, i;
  3054. struct dsi_display *display = priv;
  3055. struct dsi_display_ctrl *ctrl;
  3056. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3057. (l_type & DSI_LINK_LP_CLK)) {
  3058. /*
  3059. * Clean up the DSI controller on a previous ESD failure. This requires a DSI
  3060. * controller soft reset. Also reset PHY lanes before resetting controller.
  3061. */
  3062. if (atomic_read(&display->panel->esd_recovery_pending))
  3063. dsi_display_cleanup_post_esd_failure(display);
  3064. /*
  3065. * If continuous clock is enabled then disable it
  3066. * before entering into ULPS Mode.
  3067. */
  3068. if (display->panel->host_config.force_hs_clk_lane)
  3069. _dsi_display_continuous_clk_ctrl(display, false);
  3070. /*
  3071. * If ULPS feature is enabled, enter ULPS first.
  3072. * However, when blanking the panel, we should enter ULPS
  3073. * only if ULPS during suspend feature is enabled.
  3074. */
  3075. if (!dsi_panel_initialized(display->panel)) {
  3076. if (display->panel->ulps_suspend_enabled)
  3077. rc = dsi_display_set_ulps(display, true);
  3078. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  3079. rc = dsi_display_set_ulps(display, true);
  3080. }
  3081. if (rc)
  3082. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  3083. __func__, rc);
  3084. }
  3085. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3086. (l_type & DSI_LINK_HS_CLK)) {
  3087. /*
  3088. * PHY clock gating should be disabled before the PLL and the
  3089. * branch clocks are turned off. Otherwise, it is possible that
  3090. * the clock RCGs may not be turned off correctly resulting
  3091. * in clock warnings.
  3092. */
  3093. rc = dsi_display_config_clk_gating(display, false);
  3094. if (rc)
  3095. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  3096. display->name, rc);
  3097. }
  3098. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  3099. /*
  3100. * Enable DSI clamps only if entering idle power collapse or
  3101. * when ULPS during suspend is enabled..
  3102. */
  3103. if (dsi_panel_initialized(display->panel) ||
  3104. display->panel->ulps_suspend_enabled) {
  3105. dsi_display_phy_idle_off(display);
  3106. rc = dsi_display_set_clamp(display, true);
  3107. if (rc)
  3108. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  3109. __func__, rc);
  3110. rc = dsi_display_phy_reset_config(display, false);
  3111. if (rc)
  3112. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3113. __func__, rc);
  3114. } else {
  3115. /* Make sure that controller is not in ULPS state when
  3116. * the DSI link is not active.
  3117. */
  3118. rc = dsi_display_set_ulps(display, false);
  3119. if (rc)
  3120. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  3121. __func__, rc);
  3122. }
  3123. /* dsi will not be able to serve irqs from here on */
  3124. dsi_display_ctrl_irq_update(display, false);
  3125. /* cache the MISR values */
  3126. display_for_each_ctrl(i, display) {
  3127. ctrl = &display->ctrl[i];
  3128. if (!ctrl->ctrl)
  3129. continue;
  3130. dsi_ctrl_cache_misr(ctrl->ctrl);
  3131. }
  3132. }
  3133. return rc;
  3134. }
  3135. int dsi_post_clkon_cb(void *priv,
  3136. enum dsi_clk_type clk,
  3137. enum dsi_lclk_type l_type,
  3138. enum dsi_clk_state curr_state)
  3139. {
  3140. int rc = 0;
  3141. struct dsi_display *display = priv;
  3142. bool mmss_clamp = false;
  3143. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3144. mmss_clamp = display->clamp_enabled;
  3145. /*
  3146. * controller setup is needed if coming out of idle
  3147. * power collapse with clamps enabled.
  3148. */
  3149. if (mmss_clamp)
  3150. dsi_display_ctrl_setup(display);
  3151. /*
  3152. * Phy setup is needed if coming out of idle
  3153. * power collapse with clamps enabled.
  3154. */
  3155. if (display->phy_idle_power_off || mmss_clamp)
  3156. dsi_display_phy_idle_on(display, mmss_clamp);
  3157. if (display->ulps_enabled && mmss_clamp) {
  3158. /*
  3159. * ULPS Entry Request. This is needed if the lanes were
  3160. * in ULPS prior to power collapse, since after
  3161. * power collapse and reset, the DSI controller resets
  3162. * back to idle state and not ULPS. This ulps entry
  3163. * request will transition the state of the DSI
  3164. * controller to ULPS which will match the state of the
  3165. * DSI phy. This needs to be done prior to disabling
  3166. * the DSI clamps.
  3167. *
  3168. * Also, reset the ulps flag so that ulps_config
  3169. * function would reconfigure the controller state to
  3170. * ULPS.
  3171. */
  3172. display->ulps_enabled = false;
  3173. rc = dsi_display_set_ulps(display, true);
  3174. if (rc) {
  3175. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3176. __func__, rc);
  3177. goto error;
  3178. }
  3179. }
  3180. rc = dsi_display_phy_reset_config(display, true);
  3181. if (rc) {
  3182. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3183. __func__, rc);
  3184. goto error;
  3185. }
  3186. rc = dsi_display_set_clamp(display, false);
  3187. if (rc) {
  3188. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3189. __func__, rc);
  3190. goto error;
  3191. }
  3192. }
  3193. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3194. /*
  3195. * Toggle the resync FIFO everytime clock changes, except
  3196. * when cont-splash screen transition is going on.
  3197. * Toggling resync FIFO during cont splash transition
  3198. * can lead to blinks on the display.
  3199. */
  3200. if (!display->is_cont_splash_enabled)
  3201. dsi_display_toggle_resync_fifo(display);
  3202. if (display->ulps_enabled) {
  3203. rc = dsi_display_set_ulps(display, false);
  3204. if (rc) {
  3205. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3206. __func__, rc);
  3207. goto error;
  3208. }
  3209. }
  3210. if (display->panel->host_config.force_hs_clk_lane)
  3211. _dsi_display_continuous_clk_ctrl(display, true);
  3212. rc = dsi_display_config_clk_gating(display, true);
  3213. if (rc) {
  3214. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3215. display->name, rc);
  3216. goto error;
  3217. }
  3218. }
  3219. /* enable dsi to serve irqs */
  3220. if (clk & DSI_CORE_CLK)
  3221. dsi_display_ctrl_irq_update(display, true);
  3222. error:
  3223. return rc;
  3224. }
  3225. int dsi_post_clkoff_cb(void *priv,
  3226. enum dsi_clk_type clk_type,
  3227. enum dsi_lclk_type l_type,
  3228. enum dsi_clk_state curr_state)
  3229. {
  3230. int rc = 0;
  3231. struct dsi_display *display = priv;
  3232. if (!display) {
  3233. DSI_ERR("%s: Invalid arg\n", __func__);
  3234. return -EINVAL;
  3235. }
  3236. /* Reset PHY to clear the PHY status once the HS clocks are turned off */
  3237. if ((clk_type & DSI_LINK_CLK) && (curr_state == DSI_CLK_OFF)
  3238. && (l_type == DSI_LINK_HS_CLK)) {
  3239. if (atomic_read(&display->panel->esd_recovery_pending))
  3240. dsi_display_phy_sw_reset(display);
  3241. }
  3242. if ((clk_type & DSI_CORE_CLK) &&
  3243. (curr_state == DSI_CLK_OFF)) {
  3244. rc = dsi_display_phy_power_off(display);
  3245. if (rc)
  3246. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3247. display->name, rc);
  3248. rc = dsi_display_ctrl_power_off(display);
  3249. if (rc)
  3250. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3251. display->name, rc);
  3252. }
  3253. return rc;
  3254. }
  3255. int dsi_pre_clkon_cb(void *priv,
  3256. enum dsi_clk_type clk_type,
  3257. enum dsi_lclk_type l_type,
  3258. enum dsi_clk_state new_state)
  3259. {
  3260. int rc = 0;
  3261. struct dsi_display *display = priv;
  3262. if (!display) {
  3263. DSI_ERR("%s: invalid input\n", __func__);
  3264. return -EINVAL;
  3265. }
  3266. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3267. /*
  3268. * Enable DSI core power
  3269. * 1.> PANEL_PM are controlled as part of
  3270. * panel_power_ctrl. Needed not be handled here.
  3271. * 2.> CTRL_PM need to be enabled/disabled
  3272. * only during unblank/blank. Their state should
  3273. * not be changed during static screen.
  3274. */
  3275. DSI_DEBUG("updating power states for ctrl and phy\n");
  3276. rc = dsi_display_ctrl_power_on(display);
  3277. if (rc) {
  3278. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3279. display->name, rc);
  3280. return rc;
  3281. }
  3282. rc = dsi_display_phy_power_on(display);
  3283. if (rc) {
  3284. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3285. display->name, rc);
  3286. return rc;
  3287. }
  3288. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3289. }
  3290. return rc;
  3291. }
  3292. static void __set_lane_map_v2(u8 *lane_map_v2,
  3293. enum dsi_phy_data_lanes lane0,
  3294. enum dsi_phy_data_lanes lane1,
  3295. enum dsi_phy_data_lanes lane2,
  3296. enum dsi_phy_data_lanes lane3)
  3297. {
  3298. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3299. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3300. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3301. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3302. }
  3303. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3304. {
  3305. int rc = 0, i = 0;
  3306. const char *data;
  3307. u8 temp[DSI_LANE_MAX - 1];
  3308. if (!display) {
  3309. DSI_ERR("invalid params\n");
  3310. return -EINVAL;
  3311. }
  3312. /* lane-map-v2 supersedes lane-map-v1 setting */
  3313. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3314. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3315. if (!rc) {
  3316. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3317. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3318. return 0;
  3319. } else if (rc != EINVAL) {
  3320. DSI_DEBUG("Incorrect mapping, configure default\n");
  3321. goto set_default;
  3322. }
  3323. /* lane-map older version, for DSI controller version < 2.0 */
  3324. data = of_get_property(display->pdev->dev.of_node,
  3325. "qcom,lane-map", NULL);
  3326. if (!data)
  3327. goto set_default;
  3328. if (!strcmp(data, "lane_map_3012")) {
  3329. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3330. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3331. DSI_PHYSICAL_LANE_1,
  3332. DSI_PHYSICAL_LANE_2,
  3333. DSI_PHYSICAL_LANE_3,
  3334. DSI_PHYSICAL_LANE_0);
  3335. } else if (!strcmp(data, "lane_map_2301")) {
  3336. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3337. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3338. DSI_PHYSICAL_LANE_2,
  3339. DSI_PHYSICAL_LANE_3,
  3340. DSI_PHYSICAL_LANE_0,
  3341. DSI_PHYSICAL_LANE_1);
  3342. } else if (!strcmp(data, "lane_map_1230")) {
  3343. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3344. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3345. DSI_PHYSICAL_LANE_3,
  3346. DSI_PHYSICAL_LANE_0,
  3347. DSI_PHYSICAL_LANE_1,
  3348. DSI_PHYSICAL_LANE_2);
  3349. } else if (!strcmp(data, "lane_map_0321")) {
  3350. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3351. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3352. DSI_PHYSICAL_LANE_0,
  3353. DSI_PHYSICAL_LANE_3,
  3354. DSI_PHYSICAL_LANE_2,
  3355. DSI_PHYSICAL_LANE_1);
  3356. } else if (!strcmp(data, "lane_map_1032")) {
  3357. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3358. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3359. DSI_PHYSICAL_LANE_1,
  3360. DSI_PHYSICAL_LANE_0,
  3361. DSI_PHYSICAL_LANE_3,
  3362. DSI_PHYSICAL_LANE_2);
  3363. } else if (!strcmp(data, "lane_map_2103")) {
  3364. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3365. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3366. DSI_PHYSICAL_LANE_2,
  3367. DSI_PHYSICAL_LANE_1,
  3368. DSI_PHYSICAL_LANE_0,
  3369. DSI_PHYSICAL_LANE_3);
  3370. } else if (!strcmp(data, "lane_map_3210")) {
  3371. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3372. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3373. DSI_PHYSICAL_LANE_3,
  3374. DSI_PHYSICAL_LANE_2,
  3375. DSI_PHYSICAL_LANE_1,
  3376. DSI_PHYSICAL_LANE_0);
  3377. } else {
  3378. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3379. __func__, data);
  3380. goto set_default;
  3381. }
  3382. return 0;
  3383. set_default:
  3384. /* default lane mapping */
  3385. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3386. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3387. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3388. return 0;
  3389. }
  3390. static int dsi_display_get_phandle_index(
  3391. struct dsi_display *display,
  3392. const char *propname, int count, int index)
  3393. {
  3394. struct device_node *disp_node = display->panel_node;
  3395. u32 *val = NULL;
  3396. int rc = 0;
  3397. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3398. if (ZERO_OR_NULL_PTR(val)) {
  3399. rc = -ENOMEM;
  3400. goto end;
  3401. }
  3402. if (index >= count)
  3403. goto end;
  3404. if (display->fw)
  3405. rc = dsi_parser_read_u32_array(display->parser_node,
  3406. propname, val, count);
  3407. else
  3408. rc = of_property_read_u32_array(disp_node, propname,
  3409. val, count);
  3410. if (rc)
  3411. goto end;
  3412. rc = val[index];
  3413. DSI_DEBUG("%s index=%d\n", propname, rc);
  3414. end:
  3415. kfree(val);
  3416. return rc;
  3417. }
  3418. static bool dsi_display_validate_res(struct dsi_display *display)
  3419. {
  3420. struct device_node *of_node = display->pdev->dev.of_node;
  3421. struct of_phandle_iterator it;
  3422. bool ctrl_avail = false;
  3423. bool phy_avail = false;
  3424. /*
  3425. * At least if one of the controller or PHY is present or has been probed, the
  3426. * dsi_display_dev_probe can pass this check. Exact ctrl and PHY match will be
  3427. * done after the DT is parsed.
  3428. */
  3429. of_phandle_iterator_init(&it, of_node, "qcom,dsi-ctrl", NULL, 0);
  3430. while (of_phandle_iterator_next(&it) == 0)
  3431. ctrl_avail |= dsi_ctrl_check_resource(it.node);
  3432. of_phandle_iterator_init(&it, of_node, "qcom,dsi-phy", NULL, 0);
  3433. while (of_phandle_iterator_next(&it) == 0)
  3434. phy_avail |= dsi_phy_check_resource(it.node);
  3435. return (ctrl_avail & phy_avail);
  3436. }
  3437. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3438. const char *propname)
  3439. {
  3440. if (display->fw)
  3441. return dsi_parser_count_u32_elems(display->parser_node,
  3442. propname);
  3443. else
  3444. return of_property_count_u32_elems(display->panel_node,
  3445. propname);
  3446. }
  3447. static int dsi_display_parse_dt(struct dsi_display *display)
  3448. {
  3449. int i, rc = 0;
  3450. u32 phy_count = 0;
  3451. struct device_node *of_node = display->pdev->dev.of_node;
  3452. char *dsi_ctrl_name, *dsi_phy_name;
  3453. if (!strcmp(display->display_type, "primary")) {
  3454. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3455. dsi_phy_name = "qcom,dsi-phy-num";
  3456. } else {
  3457. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3458. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3459. }
  3460. display->ctrl_count = dsi_display_get_phandle_count(display,
  3461. dsi_ctrl_name);
  3462. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3463. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3464. display->ctrl_count, phy_count);
  3465. if (!phy_count || !display->ctrl_count) {
  3466. DSI_ERR("no ctrl/phys found\n");
  3467. rc = -ENODEV;
  3468. goto error;
  3469. }
  3470. if (phy_count != display->ctrl_count) {
  3471. DSI_ERR("different ctrl and phy counts\n");
  3472. rc = -ENODEV;
  3473. goto error;
  3474. }
  3475. display_for_each_ctrl(i, display) {
  3476. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3477. int index;
  3478. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3479. display->ctrl_count, i);
  3480. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3481. "qcom,dsi-ctrl", index);
  3482. of_node_put(ctrl->ctrl_of_node);
  3483. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3484. display->ctrl_count, i);
  3485. ctrl->phy_of_node = of_parse_phandle(of_node,
  3486. "qcom,dsi-phy", index);
  3487. of_node_put(ctrl->phy_of_node);
  3488. }
  3489. /* Parse TE data */
  3490. dsi_display_parse_te_data(display);
  3491. /* Parse all external bridges from port 0 */
  3492. display_for_each_ctrl(i, display) {
  3493. display->ext_bridge[i].node_of =
  3494. of_graph_get_remote_node(of_node, 0, i);
  3495. if (display->ext_bridge[i].node_of)
  3496. display->ext_bridge_cnt++;
  3497. else
  3498. break;
  3499. }
  3500. /* Parse Demura data */
  3501. dsi_display_parse_demura_data(display);
  3502. DSI_DEBUG("success\n");
  3503. error:
  3504. return rc;
  3505. }
  3506. static bool dsi_display_validate_panel_resources(struct dsi_display *display)
  3507. {
  3508. if (!is_sim_panel(display)) {
  3509. if (!display->panel->host_config.ext_bridge_mode &&
  3510. !gpio_is_valid(display->panel->reset_config.reset_gpio)) {
  3511. DSI_ERR("invalid reset gpio for the panel\n");
  3512. return false;
  3513. }
  3514. }
  3515. return true;
  3516. }
  3517. static int dsi_display_res_init(struct dsi_display *display)
  3518. {
  3519. int rc = 0;
  3520. int i;
  3521. struct dsi_display_ctrl *ctrl;
  3522. display_for_each_ctrl(i, display) {
  3523. ctrl = &display->ctrl[i];
  3524. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3525. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3526. rc = PTR_ERR(ctrl->ctrl);
  3527. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3528. ctrl->ctrl = NULL;
  3529. goto error_ctrl_put;
  3530. }
  3531. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3532. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3533. rc = PTR_ERR(ctrl->phy);
  3534. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3535. dsi_ctrl_put(ctrl->ctrl);
  3536. ctrl->phy = NULL;
  3537. goto error_ctrl_put;
  3538. }
  3539. }
  3540. display->panel = dsi_panel_get(&display->pdev->dev,
  3541. display->panel_node,
  3542. display->parser_node,
  3543. display->display_type,
  3544. display->cmdline_topology,
  3545. display->trusted_vm_env);
  3546. if (IS_ERR_OR_NULL(display->panel)) {
  3547. rc = PTR_ERR(display->panel);
  3548. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3549. display->panel = NULL;
  3550. goto error_ctrl_put;
  3551. }
  3552. display->panel->te_using_watchdog_timer |= display->sw_te_using_wd;
  3553. if (!dsi_display_validate_panel_resources(display)) {
  3554. rc = -EINVAL;
  3555. goto error_panel_put;
  3556. }
  3557. display_for_each_ctrl(i, display) {
  3558. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3559. struct dsi_host_common_cfg *host = &display->panel->host_config;
  3560. phy->cfg.force_clk_lane_hs =
  3561. display->panel->host_config.force_hs_clk_lane;
  3562. phy->cfg.phy_type =
  3563. display->panel->host_config.phy_type;
  3564. /*
  3565. * Parse the dynamic clock trim codes for PLL, for video mode panels that have
  3566. * dynamic clock property set.
  3567. */
  3568. if ((display->panel->dyn_clk_caps.dyn_clk_support) &&
  3569. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  3570. dsi_phy_pll_parse_dfps_data(phy);
  3571. phy->cfg.split_link.enabled = host->split_link.enabled;
  3572. phy->cfg.split_link.num_sublinks = host->split_link.num_sublinks;
  3573. phy->cfg.split_link.lanes_per_sublink = host->split_link.lanes_per_sublink;
  3574. }
  3575. rc = dsi_display_parse_lane_map(display);
  3576. if (rc) {
  3577. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3578. goto error_panel_put;
  3579. }
  3580. rc = dsi_display_clocks_init(display);
  3581. if (rc) {
  3582. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3583. goto error_panel_put;
  3584. }
  3585. /**
  3586. * In trusted vm, the connectors will not be enabled
  3587. * until the HW resources are assigned and accepted.
  3588. */
  3589. if (display->trusted_vm_env) {
  3590. display->is_active = false;
  3591. display->hw_ownership = false;
  3592. } else {
  3593. display->is_active = true;
  3594. display->hw_ownership = true;
  3595. }
  3596. return 0;
  3597. error_panel_put:
  3598. dsi_panel_put(display->panel);
  3599. error_ctrl_put:
  3600. for (i = i - 1; i >= 0; i--) {
  3601. ctrl = &display->ctrl[i];
  3602. dsi_ctrl_put(ctrl->ctrl);
  3603. dsi_phy_put(ctrl->phy);
  3604. }
  3605. return rc;
  3606. }
  3607. static int dsi_display_res_deinit(struct dsi_display *display)
  3608. {
  3609. int rc = 0;
  3610. int i;
  3611. struct dsi_display_ctrl *ctrl;
  3612. display_for_each_ctrl(i, display) {
  3613. ctrl = &display->ctrl[i];
  3614. dsi_phy_put(ctrl->phy);
  3615. dsi_ctrl_put(ctrl->ctrl);
  3616. }
  3617. if (display->panel)
  3618. dsi_panel_put(display->panel);
  3619. return rc;
  3620. }
  3621. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3622. struct dsi_display_mode *mode,
  3623. u32 flags)
  3624. {
  3625. int rc = 0;
  3626. int i;
  3627. struct dsi_display_ctrl *ctrl;
  3628. /*
  3629. * To set a mode:
  3630. * 1. Controllers should be turned off.
  3631. * 2. Link clocks should be off.
  3632. * 3. Phy should be disabled.
  3633. */
  3634. display_for_each_ctrl(i, display) {
  3635. ctrl = &display->ctrl[i];
  3636. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3637. (ctrl->phy_enabled)) {
  3638. rc = -EINVAL;
  3639. goto error;
  3640. }
  3641. }
  3642. error:
  3643. return rc;
  3644. }
  3645. static bool dsi_display_is_seamless_dfps_possible(
  3646. const struct dsi_display *display,
  3647. const struct dsi_display_mode *tgt,
  3648. const enum dsi_dfps_type dfps_type)
  3649. {
  3650. struct dsi_display_mode *cur;
  3651. if (!display || !tgt || !display->panel) {
  3652. DSI_ERR("Invalid params\n");
  3653. return false;
  3654. }
  3655. cur = display->panel->cur_mode;
  3656. if (cur->timing.h_active != tgt->timing.h_active) {
  3657. DSI_DEBUG("timing.h_active differs %d %d\n",
  3658. cur->timing.h_active, tgt->timing.h_active);
  3659. return false;
  3660. }
  3661. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3662. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3663. cur->timing.h_back_porch,
  3664. tgt->timing.h_back_porch);
  3665. return false;
  3666. }
  3667. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3668. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3669. cur->timing.h_sync_width,
  3670. tgt->timing.h_sync_width);
  3671. return false;
  3672. }
  3673. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3674. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3675. cur->timing.h_front_porch,
  3676. tgt->timing.h_front_porch);
  3677. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3678. return false;
  3679. }
  3680. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3681. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3682. cur->timing.h_skew,
  3683. tgt->timing.h_skew);
  3684. return false;
  3685. }
  3686. /* skip polarity comparison */
  3687. if (cur->timing.v_active != tgt->timing.v_active) {
  3688. DSI_DEBUG("timing.v_active differs %d %d\n",
  3689. cur->timing.v_active,
  3690. tgt->timing.v_active);
  3691. return false;
  3692. }
  3693. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3694. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3695. cur->timing.v_back_porch,
  3696. tgt->timing.v_back_porch);
  3697. return false;
  3698. }
  3699. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3700. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3701. cur->timing.v_sync_width,
  3702. tgt->timing.v_sync_width);
  3703. return false;
  3704. }
  3705. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3706. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3707. cur->timing.v_front_porch,
  3708. tgt->timing.v_front_porch);
  3709. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3710. return false;
  3711. }
  3712. /* skip polarity comparison */
  3713. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3714. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3715. cur->timing.refresh_rate,
  3716. tgt->timing.refresh_rate);
  3717. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3718. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3719. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3720. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3721. DSI_DEBUG("flags differs %d %d\n",
  3722. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3723. return true;
  3724. }
  3725. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3726. {
  3727. struct dsi_host_common_cfg *config;
  3728. struct dsi_display_ctrl *m_ctrl;
  3729. int phy_ver;
  3730. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3731. config = &display->panel->host_config;
  3732. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3733. config->byte_intf_clk_div = 2;
  3734. }
  3735. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3736. u32 bit_clk_rate)
  3737. {
  3738. int rc = 0;
  3739. int i;
  3740. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3741. if (!display->panel) {
  3742. DSI_ERR("Invalid params\n");
  3743. return -EINVAL;
  3744. }
  3745. if (bit_clk_rate == 0) {
  3746. DSI_ERR("Invalid bit clock rate\n");
  3747. return -EINVAL;
  3748. }
  3749. display->config.bit_clk_rate_hz = bit_clk_rate;
  3750. display_for_each_ctrl(i, display) {
  3751. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3752. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3753. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3754. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3755. byte_intf_clk_rate;
  3756. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3757. struct dsi_host_common_cfg *host_cfg;
  3758. mutex_lock(&ctrl->ctrl_lock);
  3759. host_cfg = &display->panel->host_config;
  3760. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3761. num_of_lanes++;
  3762. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3763. num_of_lanes++;
  3764. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3765. num_of_lanes++;
  3766. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3767. num_of_lanes++;
  3768. if (num_of_lanes == 0) {
  3769. DSI_ERR("Invalid lane count\n");
  3770. rc = -EINVAL;
  3771. goto error;
  3772. }
  3773. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3774. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3775. bit_rate_per_lane = bit_rate;
  3776. do_div(bit_rate_per_lane, num_of_lanes);
  3777. pclk_rate = bit_rate;
  3778. do_div(pclk_rate, bpp);
  3779. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3780. bit_rate_per_lane = bit_rate;
  3781. do_div(bit_rate_per_lane, num_of_lanes);
  3782. byte_clk_rate = bit_rate_per_lane;
  3783. do_div(byte_clk_rate, 8);
  3784. byte_intf_clk_rate = byte_clk_rate;
  3785. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3786. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3787. } else {
  3788. bit_rate_per_lane = bit_clk_rate;
  3789. pclk_rate *= bits_per_symbol;
  3790. do_div(pclk_rate, num_of_symbols);
  3791. byte_clk_rate = bit_clk_rate;
  3792. do_div(byte_clk_rate, num_of_symbols);
  3793. /* For CPHY, byte_intf_clk is same as byte_clk */
  3794. byte_intf_clk_rate = byte_clk_rate;
  3795. }
  3796. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3797. bit_rate, bit_rate_per_lane);
  3798. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3799. byte_clk_rate, byte_intf_clk_rate);
  3800. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3801. SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
  3802. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3803. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3804. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3805. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3806. ctrl->clk_freq, ctrl->cell_index);
  3807. if (rc) {
  3808. DSI_ERR("Failed to update link frequencies\n");
  3809. goto error;
  3810. }
  3811. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3812. error:
  3813. mutex_unlock(&ctrl->ctrl_lock);
  3814. /* TODO: recover ctrl->clk_freq in case of failure */
  3815. if (rc)
  3816. return rc;
  3817. }
  3818. return 0;
  3819. }
  3820. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3821. struct dsi_dyn_clk_delay *delay,
  3822. struct dsi_display_mode *mode)
  3823. {
  3824. u32 esc_clk_rate_hz;
  3825. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3826. u32 hsync_period = 0;
  3827. struct dsi_display_ctrl *m_ctrl;
  3828. struct dsi_ctrl *dsi_ctrl;
  3829. struct dsi_phy_cfg *cfg;
  3830. int phy_ver;
  3831. m_ctrl = &display->ctrl[display->clk_master_idx];
  3832. dsi_ctrl = m_ctrl->ctrl;
  3833. cfg = &(m_ctrl->phy->cfg);
  3834. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3835. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3836. esc_clk_rate_hz);
  3837. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3838. esc_clk_rate_hz);
  3839. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3840. esc_clk_rate_hz);
  3841. hsync_period = dsi_h_total_dce(&mode->timing);
  3842. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3843. if (!display->panel->video_config.eof_bllp_lp11_en)
  3844. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3845. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3846. (display->config.common_config.t_clk_post + 1)) /
  3847. byte_to_esc_ratio) +
  3848. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3849. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3850. ((cfg->timing.lane_v3[3] * 4) +
  3851. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3852. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3853. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3854. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3855. hr_bit_to_esc_ratio);
  3856. delay->pipe_delay2 = 0;
  3857. if (display->panel->host_config.force_hs_clk_lane)
  3858. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3859. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3860. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3861. hr_bit_to_esc_ratio);
  3862. /*
  3863. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3864. * 25us pll delay recommended for phy ver 4.0
  3865. */
  3866. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3867. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3868. delay->pll_delay = 100;
  3869. else
  3870. delay->pll_delay = 25;
  3871. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3872. }
  3873. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3874. struct link_clk_freq *bkp_freq)
  3875. {
  3876. int rc = 0, i;
  3877. u8 ctrl_version;
  3878. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3879. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3880. struct dsi_clk_link_set *enable_clk;
  3881. m_ctrl = &display->ctrl[display->clk_master_idx];
  3882. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3883. ctrl_version = m_ctrl->ctrl->version;
  3884. enable_clk = &display->clock_info.pll_clks;
  3885. dsi_clk_prepare_enable(enable_clk);
  3886. dsi_display_phy_configure(display, false);
  3887. display_for_each_ctrl(i, display) {
  3888. ctrl = &display->ctrl[i];
  3889. if (!ctrl->ctrl)
  3890. continue;
  3891. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3892. ctrl->ctrl->clk_freq.byte_clk_rate,
  3893. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3894. if (rc) {
  3895. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3896. goto recover_byte_clk;
  3897. }
  3898. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3899. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3900. if (rc) {
  3901. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3902. goto recover_pix_clk;
  3903. }
  3904. }
  3905. display_for_each_ctrl(i, display) {
  3906. ctrl = &display->ctrl[i];
  3907. if (ctrl == m_ctrl)
  3908. continue;
  3909. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3910. }
  3911. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3912. /*
  3913. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3914. * and with constant fps, as dynamic refresh will applied with
  3915. * next mdp intf ctrl flush.
  3916. */
  3917. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3918. (dyn_clk_caps->maintain_const_fps))
  3919. return 0;
  3920. /* wait for dynamic refresh done */
  3921. display_for_each_ctrl(i, display) {
  3922. ctrl = &display->ctrl[i];
  3923. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3924. if (rc) {
  3925. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3926. goto recover_pix_clk;
  3927. } else {
  3928. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3929. i ? "slave" : "master");
  3930. }
  3931. }
  3932. display_for_each_ctrl(i, display) {
  3933. ctrl = &display->ctrl[i];
  3934. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3935. }
  3936. if (rc)
  3937. DSI_ERR("could not switch back to src clks %d\n", rc);
  3938. dsi_clk_disable_unprepare(enable_clk);
  3939. return rc;
  3940. recover_pix_clk:
  3941. display_for_each_ctrl(i, display) {
  3942. ctrl = &display->ctrl[i];
  3943. if (!ctrl->ctrl)
  3944. continue;
  3945. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3946. bkp_freq->pix_clk_rate, i);
  3947. }
  3948. recover_byte_clk:
  3949. display_for_each_ctrl(i, display) {
  3950. ctrl = &display->ctrl[i];
  3951. if (!ctrl->ctrl)
  3952. continue;
  3953. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3954. bkp_freq->byte_clk_rate,
  3955. bkp_freq->byte_intf_clk_rate, i);
  3956. }
  3957. return rc;
  3958. }
  3959. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3960. struct dsi_display_mode *mode)
  3961. {
  3962. int rc = 0, mask, i;
  3963. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3964. struct dsi_dyn_clk_delay delay;
  3965. struct link_clk_freq bkp_freq;
  3966. dsi_panel_acquire_panel_lock(display->panel);
  3967. m_ctrl = &display->ctrl[display->clk_master_idx];
  3968. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3969. /* mask PLL unlock, FIFO overflow and underflow errors */
  3970. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3971. BIT(DSI_FIFO_OVERFLOW);
  3972. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3973. /* update the phy timings based on new mode */
  3974. display_for_each_ctrl(i, display) {
  3975. ctrl = &display->ctrl[i];
  3976. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3977. }
  3978. /* back up existing rates to handle failure case */
  3979. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3980. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3981. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3982. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3983. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3984. if (rc) {
  3985. DSI_ERR("failed set link frequencies %d\n", rc);
  3986. goto exit;
  3987. }
  3988. /* calculate pipe delays */
  3989. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3990. /* configure dynamic refresh ctrl registers */
  3991. display_for_each_ctrl(i, display) {
  3992. ctrl = &display->ctrl[i];
  3993. if (!ctrl->phy)
  3994. continue;
  3995. if (ctrl == m_ctrl)
  3996. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3997. else
  3998. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3999. false);
  4000. }
  4001. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  4002. exit:
  4003. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  4004. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  4005. DSI_CLK_OFF);
  4006. /* store newly calculated phy timings in mode private info */
  4007. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  4008. mode->priv_info->phy_timing_val,
  4009. mode->priv_info->phy_timing_len);
  4010. dsi_panel_release_panel_lock(display->panel);
  4011. return rc;
  4012. }
  4013. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  4014. int clk_rate)
  4015. {
  4016. int rc = 0;
  4017. if (clk_rate <= 0) {
  4018. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  4019. return -EINVAL;
  4020. }
  4021. if (clk_rate == display->cached_clk_rate) {
  4022. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  4023. return rc;
  4024. }
  4025. display->cached_clk_rate = clk_rate;
  4026. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  4027. if (!rc) {
  4028. DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
  4029. __func__, clk_rate);
  4030. atomic_set(&display->clkrate_change_pending, 1);
  4031. } else {
  4032. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  4033. __func__, clk_rate, rc);
  4034. /* Caching clock failed, so don't go on doing so. */
  4035. atomic_set(&display->clkrate_change_pending, 0);
  4036. display->cached_clk_rate = 0;
  4037. }
  4038. return rc;
  4039. }
  4040. static int dsi_display_dfps_update(struct dsi_display *display,
  4041. struct dsi_display_mode *dsi_mode)
  4042. {
  4043. struct dsi_mode_info *timing;
  4044. struct dsi_display_ctrl *m_ctrl, *ctrl;
  4045. struct dsi_display_mode *panel_mode;
  4046. struct dsi_dfps_capabilities dfps_caps;
  4047. int rc = 0;
  4048. int i = 0;
  4049. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4050. if (!display || !dsi_mode || !display->panel) {
  4051. DSI_ERR("Invalid params\n");
  4052. return -EINVAL;
  4053. }
  4054. timing = &dsi_mode->timing;
  4055. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4056. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4057. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  4058. DSI_ERR("dfps or constant fps not supported\n");
  4059. return -ENOTSUPP;
  4060. }
  4061. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  4062. DSI_ERR("dfps clock method not supported\n");
  4063. return -ENOTSUPP;
  4064. }
  4065. /* For split DSI, update the clock master first */
  4066. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  4067. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  4068. m_ctrl = &display->ctrl[display->clk_master_idx];
  4069. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  4070. if (rc) {
  4071. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  4072. display->name, i, rc);
  4073. goto error;
  4074. }
  4075. /* Update the rest of the controllers */
  4076. display_for_each_ctrl(i, display) {
  4077. ctrl = &display->ctrl[i];
  4078. if (!ctrl->ctrl || (ctrl == m_ctrl))
  4079. continue;
  4080. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  4081. if (rc) {
  4082. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  4083. display->name, i, rc);
  4084. goto error;
  4085. }
  4086. }
  4087. panel_mode = display->panel->cur_mode;
  4088. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  4089. /*
  4090. * dsi_mode_flags flags are used to communicate with other drm driver
  4091. * components, and are transient. They aren't inherently part of the
  4092. * display panel's mode and shouldn't be saved into the cached currently
  4093. * active mode.
  4094. */
  4095. panel_mode->dsi_mode_flags = 0;
  4096. error:
  4097. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  4098. return rc;
  4099. }
  4100. static int dsi_display_dfps_calc_front_porch(
  4101. u32 old_fps,
  4102. u32 new_fps,
  4103. u32 a_total,
  4104. u32 b_total,
  4105. u32 b_fp,
  4106. u32 *b_fp_out)
  4107. {
  4108. s32 b_fp_new;
  4109. int add_porches, diff;
  4110. if (!b_fp_out) {
  4111. DSI_ERR("Invalid params\n");
  4112. return -EINVAL;
  4113. }
  4114. if (!a_total || !new_fps) {
  4115. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  4116. return -EINVAL;
  4117. }
  4118. /*
  4119. * Keep clock, other porches constant, use new fps, calc front porch
  4120. * new_vtotal = old_vtotal * (old_fps / new_fps )
  4121. * new_vfp - old_vfp = new_vtotal - old_vtotal
  4122. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  4123. */
  4124. diff = abs(old_fps - new_fps);
  4125. add_porches = mult_frac(b_total, diff, new_fps);
  4126. if (old_fps > new_fps)
  4127. b_fp_new = b_fp + add_porches;
  4128. else
  4129. b_fp_new = b_fp - add_porches;
  4130. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  4131. new_fps, a_total, b_total, b_fp, b_fp_new);
  4132. if (b_fp_new < 0) {
  4133. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  4134. return -EINVAL;
  4135. }
  4136. /**
  4137. * TODO: To differentiate from clock method when communicating to the
  4138. * other components, perhaps we should set clk here to original value
  4139. */
  4140. *b_fp_out = b_fp_new;
  4141. return 0;
  4142. }
  4143. /**
  4144. * dsi_display_get_dfps_timing() - Get the new dfps values.
  4145. * @display: DSI display handle.
  4146. * @adj_mode: Mode value structure to be changed.
  4147. * It contains old timing values and latest fps value.
  4148. * New timing values are updated based on new fps.
  4149. * @curr_refresh_rate: Current fps rate.
  4150. * If zero , current fps rate is taken from
  4151. * display->panel->cur_mode.
  4152. * Return: error code.
  4153. */
  4154. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  4155. struct dsi_display_mode *adj_mode,
  4156. u32 curr_refresh_rate)
  4157. {
  4158. struct dsi_dfps_capabilities dfps_caps;
  4159. struct dsi_display_mode per_ctrl_mode;
  4160. struct dsi_mode_info *timing;
  4161. struct dsi_ctrl *m_ctrl;
  4162. int rc = 0;
  4163. if (!display || !adj_mode) {
  4164. DSI_ERR("Invalid params\n");
  4165. return -EINVAL;
  4166. }
  4167. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  4168. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4169. if (!dfps_caps.dfps_support) {
  4170. DSI_ERR("dfps not supported by panel\n");
  4171. return -EINVAL;
  4172. }
  4173. per_ctrl_mode = *adj_mode;
  4174. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  4175. if (!curr_refresh_rate) {
  4176. if (!dsi_display_is_seamless_dfps_possible(display,
  4177. &per_ctrl_mode, dfps_caps.type)) {
  4178. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4179. return -EINVAL;
  4180. }
  4181. if (display->panel->cur_mode) {
  4182. curr_refresh_rate =
  4183. display->panel->cur_mode->timing.refresh_rate;
  4184. } else {
  4185. DSI_ERR("cur_mode is not initialized\n");
  4186. return -EINVAL;
  4187. }
  4188. }
  4189. /* TODO: Remove this direct reference to the dsi_ctrl */
  4190. timing = &per_ctrl_mode.timing;
  4191. switch (dfps_caps.type) {
  4192. case DSI_DFPS_IMMEDIATE_VFP:
  4193. rc = dsi_display_dfps_calc_front_porch(
  4194. curr_refresh_rate,
  4195. timing->refresh_rate,
  4196. dsi_h_total_dce(timing),
  4197. DSI_V_TOTAL(timing),
  4198. timing->v_front_porch,
  4199. &adj_mode->timing.v_front_porch);
  4200. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
  4201. curr_refresh_rate, timing->refresh_rate,
  4202. timing->v_front_porch, adj_mode->timing.v_front_porch);
  4203. break;
  4204. case DSI_DFPS_IMMEDIATE_HFP:
  4205. rc = dsi_display_dfps_calc_front_porch(
  4206. curr_refresh_rate,
  4207. timing->refresh_rate,
  4208. DSI_V_TOTAL(timing),
  4209. dsi_h_total_dce(timing),
  4210. timing->h_front_porch,
  4211. &adj_mode->timing.h_front_porch);
  4212. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
  4213. curr_refresh_rate, timing->refresh_rate,
  4214. timing->h_front_porch, adj_mode->timing.h_front_porch);
  4215. if (!rc)
  4216. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4217. break;
  4218. default:
  4219. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4220. rc = -ENOTSUPP;
  4221. }
  4222. return rc;
  4223. }
  4224. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4225. struct dsi_display_mode *adj_mode)
  4226. {
  4227. int rc = 0;
  4228. if (!display || !adj_mode) {
  4229. DSI_ERR("Invalid params\n");
  4230. return false;
  4231. }
  4232. /* Currently the only seamless transition is dynamic fps */
  4233. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4234. if (rc) {
  4235. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4236. } else {
  4237. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4238. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4239. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4240. }
  4241. return rc;
  4242. }
  4243. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4244. struct dsi_display_mode *to_mode)
  4245. {
  4246. u32 cur_fps, to_fps;
  4247. u32 cur_h_active, to_h_active;
  4248. u32 cur_v_active, to_v_active;
  4249. cur_fps = cur_mode->timing.refresh_rate;
  4250. to_fps = to_mode->timing.refresh_rate;
  4251. cur_h_active = cur_mode->timing.h_active;
  4252. cur_v_active = cur_mode->timing.v_active;
  4253. to_h_active = to_mode->timing.h_active;
  4254. to_v_active = to_mode->timing.v_active;
  4255. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4256. (cur_fps != to_fps)) {
  4257. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4258. DSI_DEBUG("DMS Modeset with FPS change\n");
  4259. } else {
  4260. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4261. }
  4262. }
  4263. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4264. struct dsi_display_mode *mode,
  4265. u32 flags)
  4266. {
  4267. int rc = 0, clk_rate = 0;
  4268. int i;
  4269. struct dsi_display_ctrl *ctrl;
  4270. struct dsi_display_ctrl *mctrl;
  4271. struct dsi_display_mode_priv_info *priv_info;
  4272. bool commit_phy_timing = false;
  4273. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4274. priv_info = mode->priv_info;
  4275. if (!priv_info) {
  4276. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4277. display->name);
  4278. return -EINVAL;
  4279. }
  4280. SDE_EVT32(mode->dsi_mode_flags, display->panel->panel_mode);
  4281. if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  4282. display->panel->panel_mode = DSI_OP_VIDEO_MODE;
  4283. else if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  4284. display->panel->panel_mode = DSI_OP_CMD_MODE;
  4285. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4286. mode,
  4287. &display->config);
  4288. if (rc) {
  4289. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4290. display->name, rc);
  4291. goto error;
  4292. }
  4293. memcpy(&display->config.lane_map, &display->lane_map,
  4294. sizeof(display->lane_map));
  4295. mctrl = &display->ctrl[display->clk_master_idx];
  4296. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4297. if (mode->dsi_mode_flags &
  4298. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4299. display_for_each_ctrl(i, display) {
  4300. ctrl = &display->ctrl[i];
  4301. if (!ctrl->ctrl || (ctrl != mctrl))
  4302. continue;
  4303. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4304. true);
  4305. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4306. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4307. (dyn_clk_caps->maintain_const_fps)) {
  4308. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4309. true);
  4310. }
  4311. }
  4312. rc = dsi_display_dfps_update(display, mode);
  4313. if (rc) {
  4314. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4315. display->name, rc);
  4316. goto error;
  4317. }
  4318. display_for_each_ctrl(i, display) {
  4319. ctrl = &display->ctrl[i];
  4320. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4321. &display->config, mode, mode->dsi_mode_flags,
  4322. display->dsi_clk_handle);
  4323. if (rc) {
  4324. DSI_ERR("failed to update ctrl config\n");
  4325. goto error;
  4326. }
  4327. }
  4328. if (priv_info->phy_timing_len) {
  4329. display_for_each_ctrl(i, display) {
  4330. ctrl = &display->ctrl[i];
  4331. rc = dsi_phy_set_timing_params(ctrl->phy,
  4332. priv_info->phy_timing_val,
  4333. priv_info->phy_timing_len,
  4334. commit_phy_timing);
  4335. if (rc)
  4336. DSI_ERR("Fail to add timing params\n");
  4337. }
  4338. }
  4339. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4340. return rc;
  4341. }
  4342. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4343. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4344. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4345. if (rc)
  4346. DSI_ERR("dynamic clk change failed %d\n", rc);
  4347. /*
  4348. * skip rest of the opearations since
  4349. * dsi_display_dynamic_clk_switch_vid() already takes
  4350. * care of them.
  4351. */
  4352. return rc;
  4353. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4354. clk_rate = mode->timing.clk_rate_hz;
  4355. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4356. clk_rate);
  4357. if (rc) {
  4358. DSI_ERR("Failed to configure dynamic clk\n");
  4359. return rc;
  4360. }
  4361. }
  4362. }
  4363. display_for_each_ctrl(i, display) {
  4364. ctrl = &display->ctrl[i];
  4365. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4366. mode, mode->dsi_mode_flags,
  4367. display->dsi_clk_handle);
  4368. if (rc) {
  4369. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4370. display->name, rc);
  4371. goto error;
  4372. }
  4373. }
  4374. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4375. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4376. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4377. u64 to_bitclk = mode->timing.clk_rate_hz;
  4378. commit_phy_timing = true;
  4379. /* No need to set clkrate pending flag if clocks are same */
  4380. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4381. atomic_set(&display->clkrate_change_pending, 1);
  4382. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4383. }
  4384. if (priv_info->phy_timing_len) {
  4385. display_for_each_ctrl(i, display) {
  4386. ctrl = &display->ctrl[i];
  4387. rc = dsi_phy_set_timing_params(ctrl->phy,
  4388. priv_info->phy_timing_val,
  4389. priv_info->phy_timing_len,
  4390. commit_phy_timing);
  4391. if (rc)
  4392. DSI_ERR("failed to add DSI PHY timing params\n");
  4393. }
  4394. }
  4395. error:
  4396. return rc;
  4397. }
  4398. /**
  4399. * _dsi_display_dev_init - initializes the display device
  4400. * Initialization will acquire references to the resources required for the
  4401. * display hardware to function.
  4402. * @display: Handle to the display
  4403. * Returns: Zero on success
  4404. */
  4405. static int _dsi_display_dev_init(struct dsi_display *display)
  4406. {
  4407. int rc = 0;
  4408. if (!display) {
  4409. DSI_ERR("invalid display\n");
  4410. return -EINVAL;
  4411. }
  4412. if (!display->panel_node && !display->fw)
  4413. return 0;
  4414. mutex_lock(&display->display_lock);
  4415. display->parser = dsi_parser_get(&display->pdev->dev);
  4416. if (display->fw && display->parser)
  4417. display->parser_node = dsi_parser_get_head_node(
  4418. display->parser, display->fw->data,
  4419. display->fw->size);
  4420. rc = dsi_display_parse_dt(display);
  4421. if (rc) {
  4422. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4423. goto error;
  4424. }
  4425. rc = dsi_display_res_init(display);
  4426. if (rc) {
  4427. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4428. display->name, rc);
  4429. goto error;
  4430. }
  4431. error:
  4432. mutex_unlock(&display->display_lock);
  4433. return rc;
  4434. }
  4435. /**
  4436. * _dsi_display_dev_deinit - deinitializes the display device
  4437. * All the resources acquired during device init will be released.
  4438. * @display: Handle to the display
  4439. * Returns: Zero on success
  4440. */
  4441. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4442. {
  4443. int rc = 0;
  4444. if (!display) {
  4445. DSI_ERR("invalid display\n");
  4446. return -EINVAL;
  4447. }
  4448. mutex_lock(&display->display_lock);
  4449. rc = dsi_display_res_deinit(display);
  4450. if (rc)
  4451. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4452. display->name, rc);
  4453. mutex_unlock(&display->display_lock);
  4454. return rc;
  4455. }
  4456. /**
  4457. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4458. * @dsi_display: Pointer to dsi display
  4459. * Returns: Zero on success
  4460. */
  4461. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4462. {
  4463. struct dsi_display *display = dsi_display;
  4464. int rc = 0;
  4465. /* Remove the panel vote that was added during dsi display probe */
  4466. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4467. if (rc)
  4468. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4469. display->panel->name, rc);
  4470. return rc;
  4471. }
  4472. /**
  4473. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4474. * @dsi_display: Pointer to dsi display
  4475. * Returns: Zero on success
  4476. */
  4477. int dsi_display_cont_splash_config(void *dsi_display)
  4478. {
  4479. struct dsi_display *display = dsi_display;
  4480. int rc = 0;
  4481. /* Vote for gdsc required to read register address space */
  4482. if (!display) {
  4483. DSI_ERR("invalid input display param\n");
  4484. return -EINVAL;
  4485. }
  4486. rc = pm_runtime_resume_and_get(display->drm_dev->dev);
  4487. if (rc < 0) {
  4488. DSI_ERR("failed to enable power resource %d\n", rc);
  4489. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  4490. return rc;
  4491. }
  4492. mutex_lock(&display->display_lock);
  4493. display->is_cont_splash_enabled = true;
  4494. /* Update splash status for clock manager */
  4495. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4496. display->is_cont_splash_enabled);
  4497. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
  4498. /* Set up ctrl isr before enabling core clk */
  4499. dsi_display_ctrl_isr_configure(display, true);
  4500. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4501. * regulator are inplicit from pre clk on callback
  4502. */
  4503. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4504. DSI_ALL_CLKS, DSI_CLK_ON);
  4505. if (rc) {
  4506. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4507. display->name, rc);
  4508. goto clk_manager_update;
  4509. }
  4510. mutex_unlock(&display->display_lock);
  4511. /* Set the current brightness level */
  4512. dsi_panel_bl_handoff(display->panel);
  4513. return rc;
  4514. clk_manager_update:
  4515. dsi_display_ctrl_isr_configure(display, false);
  4516. /* Update splash status for clock manager */
  4517. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4518. false);
  4519. pm_runtime_put_sync(display->drm_dev->dev);
  4520. display->is_cont_splash_enabled = false;
  4521. mutex_unlock(&display->display_lock);
  4522. return rc;
  4523. }
  4524. /**
  4525. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4526. * @display: Pointer to dsi display
  4527. * Returns: Zero on success
  4528. */
  4529. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4530. {
  4531. int rc = 0;
  4532. if (!display->is_cont_splash_enabled)
  4533. return 0;
  4534. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4535. DSI_ALL_CLKS, DSI_CLK_OFF);
  4536. if (rc)
  4537. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4538. display->name, rc);
  4539. pm_runtime_put_sync(display->drm_dev->dev);
  4540. display->is_cont_splash_enabled = false;
  4541. /* Update splash status for clock manager */
  4542. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4543. display->is_cont_splash_enabled);
  4544. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
  4545. return rc;
  4546. }
  4547. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4548. {
  4549. int rc = 0, i = 0;
  4550. struct dsi_display_ctrl *ctrl;
  4551. /*
  4552. * The force update dsi clock, is the only clock update function that toggles the state of
  4553. * DSI clocks without any ref count protection. With the addition of ASYNC command wait,
  4554. * there is a need for adding a check for any queued waits before updating these clocks.
  4555. */
  4556. display_for_each_ctrl(i, display) {
  4557. ctrl = &display->ctrl[i];
  4558. if (!ctrl->ctrl || !(ctrl->ctrl->post_tx_queued))
  4559. continue;
  4560. flush_workqueue(display->post_cmd_tx_workq);
  4561. cancel_work_sync(&ctrl->ctrl->post_cmd_tx_work);
  4562. ctrl->ctrl->post_tx_queued = false;
  4563. }
  4564. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4565. if (!rc) {
  4566. DSI_DEBUG("dsi bit clk has been configured to %d\n",
  4567. display->cached_clk_rate);
  4568. atomic_set(&display->clkrate_change_pending, 0);
  4569. } else {
  4570. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4571. display->cached_clk_rate, rc);
  4572. }
  4573. return rc;
  4574. }
  4575. static int dsi_display_validate_split_link(struct dsi_display *display)
  4576. {
  4577. int i, rc = 0;
  4578. struct dsi_display_ctrl *ctrl;
  4579. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4580. if (!host->split_link.enabled)
  4581. return 0;
  4582. display_for_each_ctrl(i, display) {
  4583. ctrl = &display->ctrl[i];
  4584. if (!ctrl->ctrl->split_link_supported) {
  4585. DSI_ERR("[%s] split link is not supported by hw\n",
  4586. display->name);
  4587. rc = -ENOTSUPP;
  4588. goto error;
  4589. }
  4590. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4591. host->split_link.panel_mode = display->panel->panel_mode;
  4592. }
  4593. DSI_DEBUG("Split link is enabled\n");
  4594. return 0;
  4595. error:
  4596. host->split_link.enabled = false;
  4597. return rc;
  4598. }
  4599. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4600. {
  4601. int rc = 0;
  4602. struct dsi_display *display;
  4603. struct platform_device *pdev;
  4604. int te_gpio, avdd_gpio;
  4605. if (!data)
  4606. return -EINVAL;
  4607. display = (struct dsi_display *)data;
  4608. pdev = display->pdev;
  4609. if (!pdev)
  4610. return -EINVAL;
  4611. rc = dsi_ctrl_get_io_resources(io_res);
  4612. if (rc)
  4613. return rc;
  4614. rc = dsi_phy_get_io_resources(io_res);
  4615. if (rc)
  4616. return rc;
  4617. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4618. if (rc)
  4619. return rc;
  4620. te_gpio = of_get_named_gpio(pdev->dev.of_node, "qcom,platform-te-gpio", 0);
  4621. if (gpio_is_valid(te_gpio)) {
  4622. rc = msm_dss_get_gpio_io_mem(te_gpio, &io_res->mem);
  4623. if (rc) {
  4624. DSI_ERR("[%s] failed to retrieve the te gpio address\n",
  4625. display->panel->name);
  4626. return rc;
  4627. }
  4628. }
  4629. avdd_gpio = of_get_named_gpio(pdev->dev.of_node,
  4630. "qcom,avdd-regulator-gpio", 0);
  4631. if (gpio_is_valid(avdd_gpio)) {
  4632. rc = msm_dss_get_gpio_io_mem(avdd_gpio, &io_res->mem);
  4633. if (rc)
  4634. DSI_ERR("[%s] failed to retrieve the avdd gpio address\n",
  4635. display->panel->name);
  4636. }
  4637. return rc;
  4638. }
  4639. static int dsi_display_pre_release(void *data)
  4640. {
  4641. struct dsi_display *display;
  4642. int i;
  4643. if (!data)
  4644. return -EINVAL;
  4645. display = (struct dsi_display *)data;
  4646. mutex_lock(&display->display_lock);
  4647. display->hw_ownership = false;
  4648. mutex_unlock(&display->display_lock);
  4649. /* flush work queues */
  4650. display_for_each_ctrl(i, display) {
  4651. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  4652. if (!ctrl->ctrl || !(ctrl->ctrl->post_tx_queued))
  4653. continue;
  4654. flush_workqueue(display->post_cmd_tx_workq);
  4655. cancel_work_sync(&ctrl->ctrl->post_cmd_tx_work);
  4656. ctrl->ctrl->post_tx_queued = false;
  4657. }
  4658. dsi_display_ctrl_irq_update(display, false);
  4659. return 0;
  4660. }
  4661. static int dsi_display_pre_acquire(void *data)
  4662. {
  4663. struct dsi_display *display;
  4664. if (!data)
  4665. return -EINVAL;
  4666. display = (struct dsi_display *)data;
  4667. mutex_lock(&display->display_lock);
  4668. display->hw_ownership = true;
  4669. mutex_unlock(&display->display_lock);
  4670. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4671. return 0;
  4672. }
  4673. /**
  4674. * dsi_display_bind - bind dsi device with controlling device
  4675. * @dev: Pointer to base of platform device
  4676. * @master: Pointer to container of drm device
  4677. * @data: Pointer to private data
  4678. * Returns: Zero on success
  4679. */
  4680. static int dsi_display_bind(struct device *dev,
  4681. struct device *master,
  4682. void *data)
  4683. {
  4684. struct dsi_display_ctrl *display_ctrl;
  4685. struct drm_device *drm;
  4686. struct dsi_display *display;
  4687. struct dsi_clk_info info;
  4688. struct clk_ctrl_cb clk_cb;
  4689. void *handle = NULL;
  4690. struct platform_device *pdev = to_platform_device(dev);
  4691. char *client1 = "dsi_clk_client";
  4692. char *client2 = "mdp_event_client";
  4693. struct msm_vm_ops vm_event_ops = {
  4694. .vm_get_io_resources = dsi_display_get_io_resources,
  4695. .vm_pre_hw_release = dsi_display_pre_release,
  4696. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4697. };
  4698. int i, rc = 0;
  4699. if (!dev || !pdev || !master) {
  4700. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4701. dev, pdev, master);
  4702. return -EINVAL;
  4703. }
  4704. drm = dev_get_drvdata(master);
  4705. display = platform_get_drvdata(pdev);
  4706. if (!drm || !display) {
  4707. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4708. drm, display);
  4709. return -EINVAL;
  4710. }
  4711. if (!display->panel_node && !display->fw)
  4712. return 0;
  4713. if (!display->fw)
  4714. display->name = display->panel_node->name;
  4715. /* defer bind if ext bridge driver is not loaded */
  4716. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4717. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4718. if (!of_drm_find_bridge(
  4719. display->ext_bridge[i].node_of)) {
  4720. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4721. display->ext_bridge[i].node_of->full_name);
  4722. return -EPROBE_DEFER;
  4723. }
  4724. }
  4725. }
  4726. mutex_lock(&display->display_lock);
  4727. rc = dsi_display_validate_split_link(display);
  4728. if (rc) {
  4729. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4730. display->name, rc);
  4731. goto error;
  4732. }
  4733. rc = dsi_display_debugfs_init(display);
  4734. if (rc) {
  4735. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4736. goto error;
  4737. }
  4738. atomic_set(&display->clkrate_change_pending, 0);
  4739. display->cached_clk_rate = 0;
  4740. memset(&info, 0x0, sizeof(info));
  4741. display_for_each_ctrl(i, display) {
  4742. display_ctrl = &display->ctrl[i];
  4743. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4744. if (rc) {
  4745. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4746. display->name, i, rc);
  4747. goto error_ctrl_deinit;
  4748. }
  4749. display_ctrl->ctrl->horiz_index = i;
  4750. rc = dsi_phy_drv_init(display_ctrl->phy);
  4751. if (rc) {
  4752. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4753. display->name, i, rc);
  4754. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4755. goto error_ctrl_deinit;
  4756. }
  4757. display_ctrl->ctrl->post_cmd_tx_workq = display->post_cmd_tx_workq;
  4758. memcpy(&info.c_clks[i],
  4759. (&display_ctrl->ctrl->clk_info.core_clks),
  4760. sizeof(struct dsi_core_clk_info));
  4761. memcpy(&info.l_hs_clks[i],
  4762. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4763. sizeof(struct dsi_link_hs_clk_info));
  4764. memcpy(&info.l_lp_clks[i],
  4765. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4766. sizeof(struct dsi_link_lp_clk_info));
  4767. info.c_clks[i].drm = drm;
  4768. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4769. }
  4770. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4771. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4772. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4773. info.post_clkon_cb = dsi_post_clkon_cb;
  4774. info.phy_config_cb = dsi_display_phy_configure;
  4775. info.phy_pll_toggle_cb = dsi_display_phy_pll_toggle;
  4776. info.priv_data = display;
  4777. info.master_ndx = display->clk_master_idx;
  4778. info.dsi_ctrl_count = display->ctrl_count;
  4779. info.phy_pll_bypass = phy_pll_bypass(display);
  4780. snprintf(info.name, MAX_STRING_LEN,
  4781. "DSI_MNGR-%s", display->name);
  4782. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4783. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4784. rc = PTR_ERR(display->clk_mngr);
  4785. display->clk_mngr = NULL;
  4786. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4787. goto error_ctrl_deinit;
  4788. }
  4789. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4790. if (IS_ERR_OR_NULL(handle)) {
  4791. rc = PTR_ERR(handle);
  4792. DSI_ERR("failed to register %s client, rc = %d\n",
  4793. client1, rc);
  4794. goto error_clk_deinit;
  4795. } else {
  4796. display->dsi_clk_handle = handle;
  4797. }
  4798. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4799. if (IS_ERR_OR_NULL(handle)) {
  4800. rc = PTR_ERR(handle);
  4801. DSI_ERR("failed to register %s client, rc = %d\n",
  4802. client2, rc);
  4803. goto error_clk_client_deinit;
  4804. } else {
  4805. display->mdp_clk_handle = handle;
  4806. }
  4807. clk_cb.priv = display;
  4808. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4809. display_for_each_ctrl(i, display) {
  4810. display_ctrl = &display->ctrl[i];
  4811. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4812. if (rc) {
  4813. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4814. display->name, i, rc);
  4815. goto error_ctrl_deinit;
  4816. }
  4817. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4818. if (rc) {
  4819. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4820. display->name, i, rc);
  4821. goto error_ctrl_deinit;
  4822. }
  4823. }
  4824. dsi_display_update_byte_intf_div(display);
  4825. rc = dsi_display_mipi_host_init(display);
  4826. if (rc) {
  4827. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4828. display->name, rc);
  4829. goto error_ctrl_deinit;
  4830. }
  4831. rc = dsi_panel_drv_init(display->panel, &display->host);
  4832. if (rc) {
  4833. if (rc != -EPROBE_DEFER)
  4834. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4835. display->name, rc);
  4836. goto error_host_deinit;
  4837. }
  4838. DSI_INFO("Successfully bind display panel '%s %s'\n", display->name,
  4839. display->panel->te_using_watchdog_timer ? "as sim panel" : "");
  4840. display->drm_dev = drm;
  4841. display_for_each_ctrl(i, display) {
  4842. display_ctrl = &display->ctrl[i];
  4843. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4844. continue;
  4845. display_ctrl->ctrl->drm_dev = drm;
  4846. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4847. &display_ctrl->ctrl->clk_freq);
  4848. if (rc) {
  4849. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4850. display->name, rc);
  4851. goto error;
  4852. }
  4853. }
  4854. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4855. goto error;
  4856. error_host_deinit:
  4857. (void)dsi_display_mipi_host_deinit(display);
  4858. error_clk_client_deinit:
  4859. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4860. error_clk_deinit:
  4861. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4862. error_ctrl_deinit:
  4863. for (i = i - 1; i >= 0; i--) {
  4864. display_ctrl = &display->ctrl[i];
  4865. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4866. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4867. dsi_ctrl_put(display_ctrl->ctrl);
  4868. dsi_phy_put(display_ctrl->phy);
  4869. }
  4870. (void)dsi_display_debugfs_deinit(display);
  4871. error:
  4872. mutex_unlock(&display->display_lock);
  4873. return rc;
  4874. }
  4875. /**
  4876. * dsi_display_unbind - unbind dsi from controlling device
  4877. * @dev: Pointer to base of platform device
  4878. * @master: Pointer to container of drm device
  4879. * @data: Pointer to private data
  4880. */
  4881. static void dsi_display_unbind(struct device *dev,
  4882. struct device *master, void *data)
  4883. {
  4884. struct dsi_display_ctrl *display_ctrl;
  4885. struct dsi_display *display;
  4886. struct platform_device *pdev = to_platform_device(dev);
  4887. int i, rc = 0;
  4888. if (!dev || !pdev || !master) {
  4889. DSI_ERR("invalid param(s)\n");
  4890. return;
  4891. }
  4892. display = platform_get_drvdata(pdev);
  4893. if (!display || !display->panel_node) {
  4894. DSI_ERR("invalid display\n");
  4895. return;
  4896. }
  4897. mutex_lock(&display->display_lock);
  4898. rc = dsi_display_mipi_host_deinit(display);
  4899. if (rc)
  4900. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4901. display->name,
  4902. rc);
  4903. display_for_each_ctrl(i, display) {
  4904. display_ctrl = &display->ctrl[i];
  4905. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4906. if (rc)
  4907. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4908. display->name, i, rc);
  4909. display->ctrl->ctrl->post_cmd_tx_workq = NULL;
  4910. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4911. if (rc)
  4912. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4913. display->name, i, rc);
  4914. }
  4915. atomic_set(&display->clkrate_change_pending, 0);
  4916. (void)dsi_display_debugfs_deinit(display);
  4917. mutex_unlock(&display->display_lock);
  4918. }
  4919. static const struct component_ops dsi_display_comp_ops = {
  4920. .bind = dsi_display_bind,
  4921. .unbind = dsi_display_unbind,
  4922. };
  4923. static struct platform_driver dsi_display_driver = {
  4924. .probe = dsi_display_dev_probe,
  4925. .remove = dsi_display_dev_remove,
  4926. .driver = {
  4927. .name = "msm-dsi-display",
  4928. .of_match_table = dsi_display_dt_match,
  4929. .suppress_bind_attrs = true,
  4930. },
  4931. };
  4932. static int dsi_display_init(struct dsi_display *display)
  4933. {
  4934. int rc = 0;
  4935. struct platform_device *pdev = display->pdev;
  4936. mutex_init(&display->display_lock);
  4937. rc = _dsi_display_dev_init(display);
  4938. if (rc) {
  4939. DSI_ERR("device init failed, rc=%d\n", rc);
  4940. goto end;
  4941. }
  4942. /*
  4943. * Vote on panel regulator is added to make sure panel regulators
  4944. * are ON for cont-splash enabled usecase.
  4945. * This panel regulator vote will be removed only in:
  4946. * 1) device suspend when cont-splash is enabled.
  4947. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4948. * For GKI, adding this vote will make sure that sync_state
  4949. * kernel driver doesn't disable the panel regulators after
  4950. * dsi probe is complete.
  4951. */
  4952. if (display->panel) {
  4953. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4954. true);
  4955. if (rc) {
  4956. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4957. display->panel->name, rc);
  4958. return rc;
  4959. }
  4960. }
  4961. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4962. if (rc)
  4963. DSI_ERR("component add failed, rc=%d\n", rc);
  4964. DSI_DEBUG("component add success: %s\n", display->name);
  4965. end:
  4966. return rc;
  4967. }
  4968. static void dsi_display_firmware_display(const struct firmware *fw,
  4969. void *context)
  4970. {
  4971. struct dsi_display *display = context;
  4972. if (fw) {
  4973. DSI_INFO("reading data from firmware, size=%zd\n",
  4974. fw->size);
  4975. display->fw = fw;
  4976. if (!strcmp(display->display_type, "primary"))
  4977. display->name = "dsi_firmware_display";
  4978. else if (!strcmp(display->display_type, "secondary"))
  4979. display->name = "dsi_firmware_display_secondary";
  4980. } else {
  4981. DSI_INFO("no firmware available, fallback to device node\n");
  4982. }
  4983. if (dsi_display_init(display))
  4984. return;
  4985. DSI_DEBUG("success\n");
  4986. }
  4987. int dsi_display_dev_probe(struct platform_device *pdev)
  4988. {
  4989. struct dsi_display *display = NULL;
  4990. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4991. int rc = 0, index = DSI_PRIMARY;
  4992. bool firm_req = false;
  4993. struct dsi_display_boot_param *boot_disp;
  4994. if (!pdev || !pdev->dev.of_node) {
  4995. DSI_ERR("pdev not found\n");
  4996. rc = -ENODEV;
  4997. goto end;
  4998. }
  4999. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  5000. if (!display) {
  5001. rc = -ENOMEM;
  5002. goto end;
  5003. }
  5004. display->post_cmd_tx_workq = create_singlethread_workqueue(
  5005. "dsi_post_cmd_tx_workq");
  5006. if (!display->post_cmd_tx_workq) {
  5007. DSI_ERR("failed to create work queue\n");
  5008. rc = -EINVAL;
  5009. goto end;
  5010. }
  5011. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  5012. if (!mdp_node) {
  5013. DSI_ERR("mdp_node not found\n");
  5014. rc = -ENODEV;
  5015. goto end;
  5016. }
  5017. display->trusted_vm_env = of_property_read_bool(mdp_node,
  5018. "qcom,sde-trusted-vm-env");
  5019. if (display->trusted_vm_env)
  5020. DSI_INFO("Display enabled with trusted vm path\n");
  5021. /* initialize panel id to UINT64_MAX */
  5022. display->panel_id = ~0x0;
  5023. display->display_type = of_get_property(pdev->dev.of_node,
  5024. "label", NULL);
  5025. if (!display->display_type)
  5026. display->display_type = "primary";
  5027. if (!strcmp(display->display_type, "secondary"))
  5028. index = DSI_SECONDARY;
  5029. boot_disp = &boot_displays[index];
  5030. node = pdev->dev.of_node;
  5031. if (boot_disp->boot_disp_en) {
  5032. /* The panel name should be same as UEFI name index */
  5033. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  5034. if (!panel_node)
  5035. DSI_WARN("%s panel_node %s not found\n", display->display_type,
  5036. boot_disp->name);
  5037. } else {
  5038. panel_node = of_parse_phandle(node,
  5039. "qcom,dsi-default-panel", 0);
  5040. if (!panel_node)
  5041. DSI_INFO("%s default panel not found\n", display->display_type);
  5042. }
  5043. boot_disp->node = pdev->dev.of_node;
  5044. boot_disp->disp = display;
  5045. display->panel_node = panel_node;
  5046. display->pdev = pdev;
  5047. display->boot_disp = boot_disp;
  5048. dsi_display_parse_cmdline_topology(display, index);
  5049. platform_set_drvdata(pdev, display);
  5050. if (!dsi_display_validate_res(display)) {
  5051. rc = -EPROBE_DEFER;
  5052. DSI_ERR("resources required for display probe not present: rc=%d\n", rc);
  5053. goto end;
  5054. }
  5055. /* initialize display in firmware callback */
  5056. if (!(boot_displays[DSI_PRIMARY].boot_disp_en ||
  5057. boot_displays[DSI_SECONDARY].boot_disp_en) &&
  5058. IS_ENABLED(CONFIG_DSI_PARSER)) {
  5059. if (!strcmp(display->display_type, "primary"))
  5060. firm_req = !request_firmware_nowait(
  5061. THIS_MODULE, 1, "dsi_prop",
  5062. &pdev->dev, GFP_KERNEL, display,
  5063. dsi_display_firmware_display);
  5064. else if (!strcmp(display->display_type, "secondary"))
  5065. firm_req = !request_firmware_nowait(
  5066. THIS_MODULE, 1, "dsi_prop_sec",
  5067. &pdev->dev, GFP_KERNEL, display,
  5068. dsi_display_firmware_display);
  5069. }
  5070. if (!firm_req) {
  5071. rc = dsi_display_init(display);
  5072. if (rc)
  5073. goto end;
  5074. }
  5075. return 0;
  5076. end:
  5077. if (display)
  5078. devm_kfree(&pdev->dev, display);
  5079. return rc;
  5080. }
  5081. int dsi_display_dev_remove(struct platform_device *pdev)
  5082. {
  5083. int rc = 0, i = 0;
  5084. struct dsi_display *display;
  5085. struct dsi_display_ctrl *ctrl;
  5086. if (!pdev) {
  5087. DSI_ERR("Invalid device\n");
  5088. return -EINVAL;
  5089. }
  5090. display = platform_get_drvdata(pdev);
  5091. /* decrement ref count */
  5092. of_node_put(display->panel_node);
  5093. if (display->post_cmd_tx_workq) {
  5094. flush_workqueue(display->post_cmd_tx_workq);
  5095. destroy_workqueue(display->post_cmd_tx_workq);
  5096. display->post_cmd_tx_workq = NULL;
  5097. display_for_each_ctrl(i, display) {
  5098. ctrl = &display->ctrl[i];
  5099. if (!ctrl->ctrl)
  5100. continue;
  5101. ctrl->ctrl->post_cmd_tx_workq = NULL;
  5102. }
  5103. }
  5104. (void)_dsi_display_dev_deinit(display);
  5105. platform_set_drvdata(pdev, NULL);
  5106. devm_kfree(&pdev->dev, display);
  5107. return rc;
  5108. }
  5109. int dsi_display_get_num_of_displays(void)
  5110. {
  5111. int i, count = 0;
  5112. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  5113. struct dsi_display *display = boot_displays[i].disp;
  5114. if ((display && display->panel_node) ||
  5115. (display && display->fw))
  5116. count++;
  5117. }
  5118. return count;
  5119. }
  5120. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  5121. {
  5122. int index = 0, count = 0;
  5123. if (!display_array || !max_display_count) {
  5124. DSI_ERR("invalid params\n");
  5125. return 0;
  5126. }
  5127. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  5128. struct dsi_display *display = boot_displays[index].disp;
  5129. if ((display && display->panel_node) ||
  5130. (display && display->fw))
  5131. display_array[count++] = display;
  5132. }
  5133. return count;
  5134. }
  5135. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  5136. {
  5137. if (!display)
  5138. return;
  5139. mutex_lock(&display->display_lock);
  5140. display->is_active = is_active;
  5141. mutex_unlock(&display->display_lock);
  5142. }
  5143. int dsi_display_drm_bridge_init(struct dsi_display *display,
  5144. struct drm_encoder *enc)
  5145. {
  5146. int rc = 0;
  5147. struct dsi_bridge *bridge;
  5148. struct msm_drm_private *priv = NULL;
  5149. if (!display || !display->drm_dev || !enc) {
  5150. DSI_ERR("invalid param(s)\n");
  5151. return -EINVAL;
  5152. }
  5153. mutex_lock(&display->display_lock);
  5154. priv = display->drm_dev->dev_private;
  5155. if (!priv) {
  5156. DSI_ERR("Private data is not present\n");
  5157. rc = -EINVAL;
  5158. goto error;
  5159. }
  5160. if (display->bridge) {
  5161. DSI_ERR("display is already initialize\n");
  5162. goto error;
  5163. }
  5164. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  5165. if (IS_ERR_OR_NULL(bridge)) {
  5166. rc = PTR_ERR(bridge);
  5167. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  5168. goto error;
  5169. }
  5170. display->bridge = bridge;
  5171. priv->bridges[priv->num_bridges++] = &bridge->base;
  5172. if (display->tx_cmd_buf == NULL) {
  5173. rc = dsi_host_alloc_cmd_tx_buffer(display);
  5174. if (rc)
  5175. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  5176. }
  5177. error:
  5178. mutex_unlock(&display->display_lock);
  5179. return rc;
  5180. }
  5181. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  5182. {
  5183. int rc = 0;
  5184. if (!display) {
  5185. DSI_ERR("Invalid params\n");
  5186. return -EINVAL;
  5187. }
  5188. mutex_lock(&display->display_lock);
  5189. dsi_drm_bridge_cleanup(display->bridge);
  5190. display->bridge = NULL;
  5191. mutex_unlock(&display->display_lock);
  5192. return rc;
  5193. }
  5194. /* Hook functions to call external connector, pointer validation is
  5195. * done in dsi_display_drm_ext_bridge_init.
  5196. */
  5197. static enum drm_connector_status dsi_display_drm_ext_detect(
  5198. struct drm_connector *connector,
  5199. bool force,
  5200. void *disp)
  5201. {
  5202. struct dsi_display *display = disp;
  5203. return display->ext_conn->funcs->detect(display->ext_conn, force);
  5204. }
  5205. static int dsi_display_drm_ext_get_modes(
  5206. struct drm_connector *connector, void *disp,
  5207. const struct msm_resource_caps_info *avail_res)
  5208. {
  5209. struct dsi_display *display = disp;
  5210. struct drm_display_mode *pmode, *pt;
  5211. int count;
  5212. /* if there are modes defined in panel, ignore external modes */
  5213. if (display->panel->num_timing_nodes)
  5214. return dsi_connector_get_modes(connector, disp, avail_res);
  5215. count = display->ext_conn->helper_private->get_modes(
  5216. display->ext_conn);
  5217. list_for_each_entry_safe(pmode, pt,
  5218. &display->ext_conn->probed_modes, head) {
  5219. list_move_tail(&pmode->head, &connector->probed_modes);
  5220. }
  5221. connector->display_info = display->ext_conn->display_info;
  5222. return count;
  5223. }
  5224. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  5225. struct drm_connector *connector,
  5226. struct drm_display_mode *mode,
  5227. void *disp, const struct msm_resource_caps_info *avail_res)
  5228. {
  5229. struct dsi_display *display = disp;
  5230. enum drm_mode_status status;
  5231. /* always do internal mode_valid check */
  5232. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  5233. if (status != MODE_OK)
  5234. return status;
  5235. return display->ext_conn->helper_private->mode_valid(
  5236. display->ext_conn, mode);
  5237. }
  5238. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  5239. void *disp,
  5240. struct drm_atomic_state *state)
  5241. {
  5242. struct dsi_display *display = disp;
  5243. struct drm_connector_state *c_state;
  5244. c_state = drm_atomic_get_new_connector_state(state, connector);
  5245. return display->ext_conn->helper_private->atomic_check(
  5246. display->ext_conn, state);
  5247. }
  5248. static int dsi_display_ext_get_info(struct drm_connector *connector,
  5249. struct msm_display_info *info, void *disp)
  5250. {
  5251. struct dsi_display *display;
  5252. int i;
  5253. if (!info || !disp) {
  5254. DSI_ERR("invalid params\n");
  5255. return -EINVAL;
  5256. }
  5257. display = disp;
  5258. if (!display->panel) {
  5259. DSI_ERR("invalid display panel\n");
  5260. return -EINVAL;
  5261. }
  5262. mutex_lock(&display->display_lock);
  5263. memset(info, 0, sizeof(struct msm_display_info));
  5264. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5265. info->num_of_h_tiles = display->ctrl_count;
  5266. for (i = 0; i < info->num_of_h_tiles; i++)
  5267. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5268. info->is_connected = connector->status != connector_status_disconnected;
  5269. if (!strcmp(display->display_type, "primary"))
  5270. info->display_type = SDE_CONNECTOR_PRIMARY;
  5271. else if (!strcmp(display->display_type, "secondary"))
  5272. info->display_type = SDE_CONNECTOR_SECONDARY;
  5273. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5274. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5275. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5276. mutex_unlock(&display->display_lock);
  5277. return 0;
  5278. }
  5279. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5280. const struct drm_display_mode *drm_mode, struct msm_sub_mode *sub_mode,
  5281. struct msm_mode_info *mode_info,
  5282. void *display, const struct msm_resource_caps_info *avail_res)
  5283. {
  5284. struct msm_display_topology *topology;
  5285. if (!drm_mode || !mode_info ||
  5286. !avail_res || !avail_res->max_mixer_width)
  5287. return -EINVAL;
  5288. memset(mode_info, 0, sizeof(*mode_info));
  5289. mode_info->frame_rate = drm_mode_vrefresh(drm_mode);
  5290. mode_info->vtotal = drm_mode->vtotal;
  5291. topology = &mode_info->topology;
  5292. topology->num_lm = (avail_res->max_mixer_width
  5293. <= drm_mode->hdisplay) ? 2 : 1;
  5294. topology->num_enc = 0;
  5295. topology->num_intf = topology->num_lm;
  5296. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5297. return 0;
  5298. }
  5299. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5300. struct drm_bridge *bridge)
  5301. {
  5302. struct msm_drm_private *priv;
  5303. struct sde_kms *sde_kms;
  5304. struct drm_connector *conn;
  5305. struct drm_connector_list_iter conn_iter;
  5306. struct sde_connector *sde_conn;
  5307. struct dsi_display *display;
  5308. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5309. int i;
  5310. if (!bridge || !bridge->encoder) {
  5311. SDE_ERROR("invalid argument\n");
  5312. return NULL;
  5313. }
  5314. priv = bridge->dev->dev_private;
  5315. sde_kms = to_sde_kms(priv->kms);
  5316. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5317. drm_for_each_connector_iter(conn, &conn_iter) {
  5318. sde_conn = to_sde_connector(conn);
  5319. if (sde_conn->encoder == bridge->encoder) {
  5320. display = sde_conn->display;
  5321. display_for_each_ctrl(i, display) {
  5322. if (display->ext_bridge[i].bridge == bridge) {
  5323. dsi_bridge = &display->ext_bridge[i];
  5324. break;
  5325. }
  5326. }
  5327. }
  5328. }
  5329. drm_connector_list_iter_end(&conn_iter);
  5330. return dsi_bridge;
  5331. }
  5332. static void dsi_display_drm_ext_adjust_timing(
  5333. const struct dsi_display *display,
  5334. struct drm_display_mode *mode)
  5335. {
  5336. mode->hdisplay /= display->ctrl_count;
  5337. mode->hsync_start /= display->ctrl_count;
  5338. mode->hsync_end /= display->ctrl_count;
  5339. mode->htotal /= display->ctrl_count;
  5340. mode->hskew /= display->ctrl_count;
  5341. mode->clock /= display->ctrl_count;
  5342. }
  5343. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5344. struct drm_bridge *bridge,
  5345. const struct drm_display_info *info,
  5346. const struct drm_display_mode *mode)
  5347. {
  5348. struct dsi_display_ext_bridge *ext_bridge;
  5349. struct drm_display_mode tmp;
  5350. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5351. if (!ext_bridge)
  5352. return MODE_ERROR;
  5353. tmp = *mode;
  5354. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5355. return ext_bridge->orig_funcs->mode_valid(bridge, info, &tmp);
  5356. }
  5357. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5358. struct drm_bridge *bridge,
  5359. const struct drm_display_mode *mode,
  5360. struct drm_display_mode *adjusted_mode)
  5361. {
  5362. struct dsi_display_ext_bridge *ext_bridge;
  5363. struct drm_display_mode tmp;
  5364. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5365. if (!ext_bridge)
  5366. return false;
  5367. tmp = *mode;
  5368. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5369. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5370. }
  5371. static void dsi_display_drm_ext_bridge_mode_set(
  5372. struct drm_bridge *bridge,
  5373. const struct drm_display_mode *mode,
  5374. const struct drm_display_mode *adjusted_mode)
  5375. {
  5376. struct dsi_display_ext_bridge *ext_bridge;
  5377. struct drm_display_mode tmp;
  5378. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5379. if (!ext_bridge)
  5380. return;
  5381. tmp = *mode;
  5382. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5383. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5384. }
  5385. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5386. struct mipi_dsi_device *dsi)
  5387. {
  5388. struct dsi_display *display = to_dsi_display(host);
  5389. struct dsi_panel *panel;
  5390. if (!host || !dsi || !display->panel) {
  5391. DSI_ERR("Invalid param\n");
  5392. return -EINVAL;
  5393. }
  5394. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5395. dsi->name, dsi->channel, dsi->lanes,
  5396. dsi->format, dsi->mode_flags);
  5397. panel = display->panel;
  5398. panel->host_config.data_lanes = 0;
  5399. if (dsi->lanes > 0)
  5400. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5401. if (dsi->lanes > 1)
  5402. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5403. if (dsi->lanes > 2)
  5404. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5405. if (dsi->lanes > 3)
  5406. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5407. switch (dsi->format) {
  5408. case MIPI_DSI_FMT_RGB888:
  5409. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5410. break;
  5411. case MIPI_DSI_FMT_RGB666:
  5412. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5413. break;
  5414. case MIPI_DSI_FMT_RGB666_PACKED:
  5415. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5416. break;
  5417. case MIPI_DSI_FMT_RGB565:
  5418. default:
  5419. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5420. break;
  5421. }
  5422. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5423. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5424. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5425. panel->video_config.traffic_mode =
  5426. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5427. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5428. panel->video_config.traffic_mode =
  5429. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5430. else
  5431. panel->video_config.traffic_mode =
  5432. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5433. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  5434. panel->video_config.hsa_lp11_en =
  5435. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA;
  5436. panel->video_config.hbp_lp11_en =
  5437. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP;
  5438. panel->video_config.hfp_lp11_en =
  5439. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP;
  5440. #else
  5441. panel->video_config.hsa_lp11_en =
  5442. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5443. panel->video_config.hbp_lp11_en =
  5444. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5445. panel->video_config.hfp_lp11_en =
  5446. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5447. #endif
  5448. panel->video_config.pulse_mode_hsa_he =
  5449. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5450. } else {
  5451. panel->panel_mode = DSI_OP_CMD_MODE;
  5452. DSI_ERR("command mode not supported by ext bridge\n");
  5453. return -ENOTSUPP;
  5454. }
  5455. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5456. return 0;
  5457. }
  5458. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5459. .attach = dsi_host_ext_attach,
  5460. .detach = dsi_host_detach,
  5461. .transfer = dsi_host_transfer,
  5462. };
  5463. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5464. {
  5465. if (!display || !display->panel) {
  5466. pr_err("invalid param(s)\n");
  5467. return NULL;
  5468. }
  5469. return &display->panel->drm_panel;
  5470. }
  5471. bool dsi_display_has_dsc_switch_support(struct dsi_display *display)
  5472. {
  5473. if (!display || !display->panel) {
  5474. pr_err("invalid param(s)\n");
  5475. return false;
  5476. }
  5477. return display->panel->dsc_switch_supported;
  5478. }
  5479. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5480. struct drm_encoder *encoder, struct drm_connector *connector)
  5481. {
  5482. struct drm_device *drm;
  5483. struct drm_bridge *bridge;
  5484. struct drm_bridge *ext_bridge;
  5485. struct drm_connector *ext_conn;
  5486. struct sde_connector *sde_conn;
  5487. struct drm_bridge *prev_bridge;
  5488. int rc = 0, i;
  5489. if (!display || !encoder || !connector)
  5490. return -EINVAL;
  5491. drm = encoder->dev;
  5492. bridge = drm_bridge_chain_get_first_bridge(encoder);
  5493. sde_conn = to_sde_connector(connector);
  5494. prev_bridge = bridge;
  5495. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5496. return 0;
  5497. if (!bridge)
  5498. return -EINVAL;
  5499. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5500. struct dsi_display_ext_bridge *ext_bridge_info =
  5501. &display->ext_bridge[i];
  5502. struct drm_encoder *c_encoder;
  5503. /* return if ext bridge is already initialized */
  5504. if (ext_bridge_info->bridge)
  5505. return 0;
  5506. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5507. if (IS_ERR_OR_NULL(ext_bridge)) {
  5508. rc = PTR_ERR(ext_bridge);
  5509. DSI_ERR("failed to find ext bridge\n");
  5510. goto error;
  5511. }
  5512. /* override functions for mode adjustment */
  5513. if (display->ext_bridge_cnt > 1) {
  5514. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5515. if (ext_bridge->funcs->mode_fixup)
  5516. ext_bridge_info->bridge_funcs.mode_fixup =
  5517. dsi_display_drm_ext_bridge_mode_fixup;
  5518. if (ext_bridge->funcs->mode_valid)
  5519. ext_bridge_info->bridge_funcs.mode_valid =
  5520. dsi_display_drm_ext_bridge_mode_valid;
  5521. if (ext_bridge->funcs->mode_set)
  5522. ext_bridge_info->bridge_funcs.mode_set =
  5523. dsi_display_drm_ext_bridge_mode_set;
  5524. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5525. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5526. }
  5527. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge,
  5528. DRM_BRIDGE_ATTACH_NO_CONNECTOR);
  5529. if (rc) {
  5530. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5531. display->name, rc);
  5532. goto error;
  5533. }
  5534. ext_bridge_info->display = display;
  5535. ext_bridge_info->bridge = ext_bridge;
  5536. prev_bridge = ext_bridge;
  5537. /* ext bridge will init its own connector during attach,
  5538. * we need to extract it out of the connector list
  5539. */
  5540. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5541. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5542. struct drm_connector, head);
  5543. if (!ext_conn) {
  5544. DSI_ERR("failed to get external connector\n");
  5545. rc = PTR_ERR(ext_conn);
  5546. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5547. goto error;
  5548. }
  5549. drm_connector_for_each_possible_encoder(ext_conn, c_encoder)
  5550. break;
  5551. if (!c_encoder) {
  5552. DSI_ERR("failed to get encoder\n");
  5553. rc = PTR_ERR(c_encoder);
  5554. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5555. goto error;
  5556. }
  5557. if (ext_conn && ext_conn != connector &&
  5558. c_encoder->base.id == bridge->encoder->base.id) {
  5559. list_del_init(&ext_conn->head);
  5560. display->ext_conn = ext_conn;
  5561. }
  5562. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5563. /* if there is no valid external connector created, or in split
  5564. * mode, default setting is used from panel defined in DT file.
  5565. */
  5566. if (!display->ext_conn ||
  5567. !display->ext_conn->funcs ||
  5568. !display->ext_conn->helper_private ||
  5569. display->ext_bridge_cnt > 1) {
  5570. display->ext_conn = NULL;
  5571. continue;
  5572. }
  5573. /* otherwise, hook up the functions to use external connector */
  5574. if (display->ext_conn->funcs->detect)
  5575. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5576. if (display->ext_conn->helper_private->get_modes)
  5577. sde_conn->ops.get_modes =
  5578. dsi_display_drm_ext_get_modes;
  5579. if (display->ext_conn->helper_private->mode_valid)
  5580. sde_conn->ops.mode_valid =
  5581. dsi_display_drm_ext_mode_valid;
  5582. if (display->ext_conn->helper_private->atomic_check)
  5583. sde_conn->ops.atomic_check =
  5584. dsi_display_drm_ext_atomic_check;
  5585. sde_conn->ops.get_info =
  5586. dsi_display_ext_get_info;
  5587. sde_conn->ops.get_mode_info =
  5588. dsi_display_ext_get_mode_info;
  5589. /* add support to attach/detach */
  5590. display->host.ops = &dsi_host_ext_ops;
  5591. }
  5592. return 0;
  5593. error:
  5594. return rc;
  5595. }
  5596. int dsi_display_get_info(struct drm_connector *connector,
  5597. struct msm_display_info *info, void *disp)
  5598. {
  5599. struct dsi_display *display;
  5600. struct dsi_panel_phy_props phy_props;
  5601. struct dsi_host_common_cfg *host;
  5602. int i, rc;
  5603. if (!info || !disp) {
  5604. DSI_ERR("invalid params\n");
  5605. return -EINVAL;
  5606. }
  5607. display = disp;
  5608. if (!display->panel) {
  5609. DSI_ERR("invalid display panel\n");
  5610. return -EINVAL;
  5611. }
  5612. mutex_lock(&display->display_lock);
  5613. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5614. if (rc) {
  5615. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5616. display->name, rc);
  5617. goto error;
  5618. }
  5619. memset(info, 0, sizeof(struct msm_display_info));
  5620. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5621. info->num_of_h_tiles = display->ctrl_count;
  5622. for (i = 0; i < info->num_of_h_tiles; i++)
  5623. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5624. info->is_connected = display->is_active;
  5625. if (!strcmp(display->display_type, "primary"))
  5626. info->display_type = SDE_CONNECTOR_PRIMARY;
  5627. else if (!strcmp(display->display_type, "secondary"))
  5628. info->display_type = SDE_CONNECTOR_SECONDARY;
  5629. info->width_mm = phy_props.panel_width_mm;
  5630. info->height_mm = phy_props.panel_height_mm;
  5631. info->max_width = 1920;
  5632. info->max_height = 1080;
  5633. info->qsync_min_fps = display->panel->qsync_caps.qsync_min_fps;
  5634. info->has_qsync_min_fps_list = (display->panel->qsync_caps.qsync_min_fps_list_len > 0);
  5635. info->avr_step_fps = display->panel->avr_caps.avr_step_fps;
  5636. info->poms_align_vsync = display->panel->poms_align_vsync;
  5637. switch (display->panel->panel_mode) {
  5638. case DSI_OP_VIDEO_MODE:
  5639. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5640. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5641. if (display->panel->panel_mode_switch_enabled)
  5642. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5643. break;
  5644. case DSI_OP_CMD_MODE:
  5645. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5646. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5647. if (display->panel->panel_mode_switch_enabled)
  5648. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5649. info->is_te_using_watchdog_timer = is_sim_panel(display);
  5650. break;
  5651. default:
  5652. DSI_ERR("unknwown dsi panel mode %d\n",
  5653. display->panel->panel_mode);
  5654. break;
  5655. }
  5656. if (display->panel->esd_config.esd_enabled && !is_sim_panel(display))
  5657. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5658. info->te_source = display->te_source;
  5659. host = &display->panel->host_config;
  5660. if (host->split_link.enabled)
  5661. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5662. info->dsc_count = display->panel->dsc_count;
  5663. info->lm_count = display->panel->lm_count;
  5664. error:
  5665. mutex_unlock(&display->display_lock);
  5666. return rc;
  5667. }
  5668. int dsi_display_get_mode_count(struct dsi_display *display,
  5669. u32 *count)
  5670. {
  5671. if (!display || !display->panel) {
  5672. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5673. display ? display->panel != NULL : 0);
  5674. return -EINVAL;
  5675. }
  5676. mutex_lock(&display->display_lock);
  5677. *count = display->panel->num_display_modes;
  5678. mutex_unlock(&display->display_lock);
  5679. return 0;
  5680. }
  5681. void dsi_display_adjust_mode_timing(struct dsi_display *display,
  5682. struct dsi_display_mode *dsi_mode,
  5683. int lanes, int bpp)
  5684. {
  5685. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5686. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5687. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  5688. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5689. /* Constant FPS is not supported on command mode */
  5690. if (!(dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE))
  5691. return;
  5692. if (!dyn_clk_caps->maintain_const_fps)
  5693. return;
  5694. /*
  5695. * When there is a dynamic clock switch, there is small change
  5696. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5697. * is adjusted. It has been assumed that the refined porch values
  5698. * are supported by the panel. This logic can be enhanced further
  5699. * in future by taking min/max porches supported by the panel.
  5700. */
  5701. switch (dyn_clk_caps->type) {
  5702. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5703. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5704. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5705. do_div(old_htotal, display->ctrl_count);
  5706. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5707. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5708. if (dsi_is_type_cphy(&display->panel->host_config)) {
  5709. new_htotal = new_htotal * bits_per_symbol;
  5710. div = div * num_of_symbols;
  5711. }
  5712. do_div(new_htotal, div);
  5713. if (old_htotal > new_htotal)
  5714. dsi_mode->timing.h_front_porch -=
  5715. ((old_htotal - new_htotal) * display->ctrl_count);
  5716. else
  5717. dsi_mode->timing.h_front_porch +=
  5718. ((new_htotal - old_htotal) * display->ctrl_count);
  5719. break;
  5720. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5721. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5722. do_div(htotal, display->ctrl_count);
  5723. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5724. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5725. if (dsi_is_type_cphy(&display->panel->host_config)) {
  5726. new_vtotal = new_vtotal * bits_per_symbol;
  5727. div = div * num_of_symbols;
  5728. }
  5729. do_div(new_vtotal, div);
  5730. dsi_mode->timing.v_front_porch = new_vtotal -
  5731. dsi_mode->timing.v_back_porch -
  5732. dsi_mode->timing.v_sync_width -
  5733. dsi_mode->timing.v_active;
  5734. break;
  5735. default:
  5736. break;
  5737. }
  5738. dsi_mode->pixel_clk_khz = div_u64(dsi_mode->timing.clk_rate_hz * lanes, bpp);
  5739. do_div(dsi_mode->pixel_clk_khz, 1000);
  5740. dsi_mode->pixel_clk_khz *= display->ctrl_count;
  5741. }
  5742. static void _dsi_display_populate_bit_clks(struct dsi_display *display, int start, int end)
  5743. {
  5744. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5745. struct dsi_display_mode *src, dst;
  5746. struct dsi_host_common_cfg *cfg;
  5747. int i, j, bpp, lanes = 0;
  5748. if (!display)
  5749. return;
  5750. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5751. if (!dyn_clk_caps->dyn_clk_support)
  5752. return;
  5753. cfg = &(display->panel->host_config);
  5754. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5755. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5756. lanes++;
  5757. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5758. lanes++;
  5759. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5760. lanes++;
  5761. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5762. lanes++;
  5763. for (i = start; i < end; i++) {
  5764. src = &display->modes[i];
  5765. if (!src)
  5766. return;
  5767. if (!src->priv_info->bit_clk_list.count)
  5768. continue;
  5769. src->timing.clk_rate_hz = src->priv_info->bit_clk_list.rates[0];
  5770. dsi_display_adjust_mode_timing(display, src, lanes, bpp);
  5771. /* populate mode adjusted values */
  5772. for (j = 0; j < src->priv_info->bit_clk_list.count; j++) {
  5773. memcpy(&dst, src, sizeof(struct dsi_display_mode));
  5774. memcpy(&dst.timing, &src->timing, sizeof(struct dsi_mode_info));
  5775. dst.timing.clk_rate_hz = src->priv_info->bit_clk_list.rates[j];
  5776. dsi_display_adjust_mode_timing(display, &dst, lanes, bpp);
  5777. /* store the list of RFI matching porches */
  5778. switch (dyn_clk_caps->type) {
  5779. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5780. src->priv_info->bit_clk_list.front_porches[j] =
  5781. dst.timing.h_front_porch;
  5782. break;
  5783. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5784. src->priv_info->bit_clk_list.front_porches[j] =
  5785. dst.timing.v_front_porch;
  5786. break;
  5787. default:
  5788. break;
  5789. }
  5790. /* store the list of RFI matching pixel clocks */
  5791. src->priv_info->bit_clk_list.pixel_clks_khz[j] = dst.pixel_clk_khz;
  5792. }
  5793. }
  5794. }
  5795. static int dsi_display_mode_dyn_clk_cpy(struct dsi_display *display,
  5796. struct dsi_display_mode *src, struct dsi_display_mode *dst)
  5797. {
  5798. int rc = 0;
  5799. u32 count = 0;
  5800. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5801. struct msm_dyn_clk_list *bit_clk_list;
  5802. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5803. if (!dyn_clk_caps->dyn_clk_support)
  5804. return rc;
  5805. count = dst->priv_info->bit_clk_list.count;
  5806. bit_clk_list = &dst->priv_info->bit_clk_list;
  5807. bit_clk_list->front_porches =
  5808. kcalloc(count, sizeof(u32), GFP_KERNEL);
  5809. if (!bit_clk_list->front_porches) {
  5810. DSI_ERR("failed to allocate space for front porch list\n");
  5811. rc = -ENOMEM;
  5812. goto error;
  5813. }
  5814. bit_clk_list->rates =
  5815. kcalloc(count, sizeof(u32), GFP_KERNEL);
  5816. if (!bit_clk_list->rates) {
  5817. DSI_ERR("failed to allocate space for rates list\n");
  5818. rc = -ENOMEM;
  5819. goto error;
  5820. }
  5821. memcpy(bit_clk_list->rates, src->priv_info->bit_clk_list.rates,
  5822. count*sizeof(u32));
  5823. bit_clk_list->pixel_clks_khz =
  5824. kcalloc(count, sizeof(u32), GFP_KERNEL);
  5825. if (!bit_clk_list->pixel_clks_khz) {
  5826. DSI_ERR("failed to allocate space for pixel clocks list\n");
  5827. rc = -ENOMEM;
  5828. goto error;
  5829. }
  5830. return rc;
  5831. error:
  5832. kfree(bit_clk_list->rates);
  5833. kfree(bit_clk_list->front_porches);
  5834. kfree(bit_clk_list->pixel_clks_khz);
  5835. return rc;
  5836. }
  5837. int dsi_display_restore_bit_clk(struct dsi_display *display, struct dsi_display_mode *mode)
  5838. {
  5839. int i;
  5840. u32 clk_rate_hz = 0;
  5841. if (!display || !mode || !mode->priv_info) {
  5842. DSI_ERR("invalid arguments\n");
  5843. return -EINVAL;
  5844. }
  5845. /* avoid updating bit_clk for dyn clk feature disbaled usecase */
  5846. if (!display->panel->dyn_clk_caps.dyn_clk_support)
  5847. return 0;
  5848. clk_rate_hz = display->cached_clk_rate;
  5849. if (mode->priv_info->bit_clk_list.count) {
  5850. /* use first entry as the default bit clk rate */
  5851. clk_rate_hz = mode->priv_info->bit_clk_list.rates[0];
  5852. for (i = 0; i < mode->priv_info->bit_clk_list.count; i++) {
  5853. if (display->dyn_bit_clk == mode->priv_info->bit_clk_list.rates[i])
  5854. clk_rate_hz = display->dyn_bit_clk;
  5855. }
  5856. }
  5857. mode->timing.clk_rate_hz = clk_rate_hz;
  5858. mode->priv_info->clk_rate_hz = clk_rate_hz;
  5859. SDE_EVT32(clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5860. DSI_DEBUG("clk_rate_hz:%u, cached_clk_rate:%u, dyn_bit_clk:%u\n",
  5861. clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5862. return 0;
  5863. }
  5864. void dsi_display_put_mode(struct dsi_display *display,
  5865. struct dsi_display_mode *mode)
  5866. {
  5867. dsi_panel_put_mode(mode);
  5868. }
  5869. int dsi_display_get_modes_helper(struct dsi_display *display,
  5870. struct dsi_display_ctrl *ctrl, u32 timing_mode_count,
  5871. struct dsi_dfps_capabilities dfps_caps, struct dsi_qsync_capabilities *qsync_caps,
  5872. struct dsi_dyn_clk_caps *dyn_clk_caps, struct dsi_avr_capabilities *avr_caps)
  5873. {
  5874. int dsc_modes = 0, nondsc_modes = 0, rc = 0, i, start, end;
  5875. u32 num_dfps_rates, mode_idx, sublinks_count, array_idx = 0;
  5876. bool is_split_link, support_cmd_mode, support_video_mode;
  5877. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5878. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5879. struct dsi_display_mode display_mode;
  5880. int topology_override = NO_OVERRIDE;
  5881. bool is_preferred = false;
  5882. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5883. struct msm_dyn_clk_list *bit_clk_list;
  5884. memset(&display_mode, 0, sizeof(display_mode));
  5885. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5886. &display_mode,
  5887. topology_override);
  5888. if (rc) {
  5889. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5890. display->name, mode_idx);
  5891. rc = -EINVAL;
  5892. return rc;
  5893. }
  5894. if (display->cmdline_timing == display_mode.mode_idx) {
  5895. topology_override = display->cmdline_topology;
  5896. is_preferred = true;
  5897. }
  5898. support_cmd_mode = display_mode.panel_mode_caps & DSI_OP_CMD_MODE;
  5899. support_video_mode = display_mode.panel_mode_caps & DSI_OP_VIDEO_MODE;
  5900. if (display_mode.priv_info->dsc_enabled)
  5901. dsc_modes++;
  5902. else
  5903. nondsc_modes++;
  5904. /* Setup widebus support */
  5905. display_mode.priv_info->widebus_support =
  5906. ctrl->ctrl->hw.widebus_support;
  5907. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5908. !support_video_mode) ? 1 : dfps_caps.dfps_list_len);
  5909. /* Calculate dsi frame transfer time */
  5910. if (support_cmd_mode) {
  5911. dsi_panel_calc_dsi_transfer_time(
  5912. &display->panel->host_config,
  5913. &display_mode, frame_threshold_us);
  5914. display_mode.priv_info->dsi_transfer_time_us =
  5915. display_mode.timing.dsi_transfer_time_us;
  5916. display_mode.priv_info->min_dsi_clk_hz =
  5917. display_mode.timing.min_dsi_clk_hz;
  5918. display_mode.priv_info->mdp_transfer_time_us =
  5919. display_mode.timing.mdp_transfer_time_us;
  5920. }
  5921. is_split_link = host->split_link.enabled;
  5922. sublinks_count = host->split_link.num_sublinks;
  5923. if (is_split_link && sublinks_count > 1) {
  5924. display_mode.timing.h_active *= sublinks_count;
  5925. display_mode.timing.h_front_porch *= sublinks_count;
  5926. display_mode.timing.h_sync_width *= sublinks_count;
  5927. display_mode.timing.h_back_porch *= sublinks_count;
  5928. display_mode.timing.h_skew *= sublinks_count;
  5929. display_mode.pixel_clk_khz *= sublinks_count;
  5930. } else {
  5931. display_mode.timing.h_active *= display->ctrl_count;
  5932. display_mode.timing.h_front_porch *=
  5933. display->ctrl_count;
  5934. display_mode.timing.h_sync_width *=
  5935. display->ctrl_count;
  5936. display_mode.timing.h_back_porch *=
  5937. display->ctrl_count;
  5938. display_mode.timing.h_skew *= display->ctrl_count;
  5939. display_mode.pixel_clk_khz *= display->ctrl_count;
  5940. }
  5941. start = array_idx;
  5942. for (i = 0; i < num_dfps_rates; i++) {
  5943. struct dsi_display_mode *sub_mode =
  5944. &display->modes[array_idx];
  5945. u32 curr_refresh_rate;
  5946. if (!sub_mode) {
  5947. DSI_ERR("invalid mode data\n");
  5948. rc = -EFAULT;
  5949. return rc;
  5950. }
  5951. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5952. array_idx++;
  5953. /*
  5954. * Populate mode qsync min fps from panel min qsync fps dt property
  5955. * in video mode & in command mode where per mode qsync min fps is
  5956. * not defined.
  5957. */
  5958. if (!sub_mode->timing.qsync_min_fps && qsync_caps->qsync_min_fps)
  5959. sub_mode->timing.qsync_min_fps = qsync_caps->qsync_min_fps;
  5960. /* populate avr step fps, same way as qsync min fps */
  5961. if (!sub_mode->timing.avr_step_fps && avr_caps->avr_step_fps)
  5962. sub_mode->timing.avr_step_fps = avr_caps->avr_step_fps;
  5963. /*
  5964. * Qsync min fps for the mode will be populated in the timing info
  5965. * in dsi_panel_get_mode function.
  5966. */
  5967. display_mode.priv_info->qsync_min_fps = sub_mode->timing.qsync_min_fps;
  5968. if (!dfps_caps.dfps_support || !support_video_mode)
  5969. continue;
  5970. sub_mode->priv_info = kmemdup(display_mode.priv_info,
  5971. sizeof(*sub_mode->priv_info), GFP_KERNEL);
  5972. if (!sub_mode->priv_info) {
  5973. rc = -ENOMEM;
  5974. return rc;
  5975. }
  5976. rc = dsi_display_mode_dyn_clk_cpy(display,
  5977. &display_mode, sub_mode);
  5978. if (rc) {
  5979. DSI_ERR("unable to copy dyn clock list\n");
  5980. return rc;
  5981. }
  5982. sub_mode->mode_idx += (array_idx - 1);
  5983. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5984. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5985. /* Override with qsync min fps list in dfps usecases */
  5986. if (qsync_caps->qsync_min_fps && qsync_caps->qsync_min_fps_list_len) {
  5987. sub_mode->timing.qsync_min_fps = qsync_caps->qsync_min_fps_list[i];
  5988. sub_mode->priv_info->qsync_min_fps = sub_mode->timing.qsync_min_fps;
  5989. }
  5990. /* Override with avr step fps list in dfps usecases */
  5991. if (avr_caps->avr_step_fps_list_len) {
  5992. sub_mode->timing.avr_step_fps = avr_caps->avr_step_fps_list[i];
  5993. sub_mode->priv_info->avr_step_fps = sub_mode->timing.avr_step_fps;
  5994. }
  5995. dsi_display_get_dfps_timing(display, sub_mode,
  5996. curr_refresh_rate);
  5997. sub_mode->panel_mode_caps = DSI_OP_VIDEO_MODE;
  5998. }
  5999. end = array_idx;
  6000. _dsi_display_populate_bit_clks(display, start, end);
  6001. if (is_preferred) {
  6002. /* Set first timing sub mode as preferred mode */
  6003. display->modes[start].is_preferred = true;
  6004. }
  6005. bit_clk_list = &display_mode.priv_info->bit_clk_list;
  6006. if (support_video_mode && dfps_caps.dfps_support) {
  6007. if (dyn_clk_caps->dyn_clk_support) {
  6008. kfree(bit_clk_list->rates);
  6009. kfree(bit_clk_list->front_porches);
  6010. kfree(bit_clk_list->pixel_clks_khz);
  6011. }
  6012. kfree(display_mode.priv_info);
  6013. }
  6014. }
  6015. if (dsc_modes && nondsc_modes)
  6016. display->panel->dsc_switch_supported = true;
  6017. return rc;
  6018. }
  6019. int dsi_display_get_modes(struct dsi_display *display,
  6020. struct dsi_display_mode **out_modes)
  6021. {
  6022. struct dsi_dfps_capabilities dfps_caps;
  6023. struct dsi_display_ctrl *ctrl;
  6024. u32 timing_mode_count, display_mode_count;
  6025. struct dsi_dyn_clk_caps *dyn_clk_caps;
  6026. int rc = -EINVAL;
  6027. struct dsi_qsync_capabilities *qsync_caps;
  6028. struct dsi_avr_capabilities *avr_caps;
  6029. if (!display || !out_modes) {
  6030. DSI_ERR("Invalid params\n");
  6031. return -EINVAL;
  6032. }
  6033. *out_modes = NULL;
  6034. ctrl = &display->ctrl[0];
  6035. mutex_lock(&display->display_lock);
  6036. if (display->modes)
  6037. goto exit;
  6038. display_mode_count = display->panel->num_display_modes;
  6039. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  6040. GFP_KERNEL);
  6041. if (!display->modes) {
  6042. rc = -ENOMEM;
  6043. goto error;
  6044. }
  6045. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  6046. if (rc) {
  6047. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  6048. display->name);
  6049. goto error;
  6050. }
  6051. qsync_caps = &(display->panel->qsync_caps);
  6052. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  6053. avr_caps = &(display->panel->avr_caps);
  6054. timing_mode_count = display->panel->num_timing_nodes;
  6055. /* Validate command line timing */
  6056. if ((display->cmdline_timing != NO_OVERRIDE) &&
  6057. (display->cmdline_timing >= timing_mode_count))
  6058. display->cmdline_timing = NO_OVERRIDE;
  6059. rc = dsi_display_get_modes_helper(display, ctrl, timing_mode_count,
  6060. dfps_caps, qsync_caps, dyn_clk_caps, avr_caps);
  6061. if (rc)
  6062. goto error;
  6063. exit:
  6064. *out_modes = display->modes;
  6065. rc = 0;
  6066. error:
  6067. if (rc)
  6068. kfree(display->modes);
  6069. mutex_unlock(&display->display_lock);
  6070. return rc;
  6071. }
  6072. int dsi_display_get_panel_vfp(void *dsi_display,
  6073. int h_active, int v_active)
  6074. {
  6075. int i, rc = 0;
  6076. u32 count, refresh_rate = 0;
  6077. struct dsi_dfps_capabilities dfps_caps;
  6078. struct dsi_display *display = (struct dsi_display *)dsi_display;
  6079. struct dsi_host_common_cfg *host;
  6080. if (!display || !display->panel)
  6081. return -EINVAL;
  6082. mutex_lock(&display->display_lock);
  6083. count = display->panel->num_display_modes;
  6084. if (display->panel->cur_mode)
  6085. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  6086. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  6087. if (dfps_caps.dfps_support)
  6088. refresh_rate = dfps_caps.max_refresh_rate;
  6089. if (!refresh_rate) {
  6090. mutex_unlock(&display->display_lock);
  6091. DSI_ERR("Null Refresh Rate\n");
  6092. return -EINVAL;
  6093. }
  6094. host = &display->panel->host_config;
  6095. if (host->split_link.enabled)
  6096. h_active *= host->split_link.num_sublinks;
  6097. else
  6098. h_active *= display->ctrl_count;
  6099. for (i = 0; i < count; i++) {
  6100. struct dsi_display_mode *m = &display->modes[i];
  6101. if (m && v_active == m->timing.v_active &&
  6102. h_active == m->timing.h_active &&
  6103. refresh_rate == m->timing.refresh_rate) {
  6104. rc = m->timing.v_front_porch;
  6105. break;
  6106. }
  6107. }
  6108. mutex_unlock(&display->display_lock);
  6109. return rc;
  6110. }
  6111. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  6112. {
  6113. struct dsi_display *display = (struct dsi_display *)dsi_display;
  6114. u32 count, i;
  6115. int rc = 0;
  6116. *num_lm = 0;
  6117. mutex_lock(&display->display_lock);
  6118. count = display->panel->num_display_modes;
  6119. mutex_unlock(&display->display_lock);
  6120. if (!display->modes) {
  6121. struct dsi_display_mode *m;
  6122. rc = dsi_display_get_modes(display, &m);
  6123. if (rc)
  6124. return rc;
  6125. }
  6126. mutex_lock(&display->display_lock);
  6127. for (i = 0; i < count; i++) {
  6128. struct dsi_display_mode *m = &display->modes[i];
  6129. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  6130. }
  6131. mutex_unlock(&display->display_lock);
  6132. return rc;
  6133. }
  6134. int dsi_display_update_transfer_time(void *display, u32 transfer_time)
  6135. {
  6136. struct dsi_display *disp = (struct dsi_display *)display;
  6137. int rc = 0, i = 0;
  6138. u32 transfer_time_min, transfer_time_max;
  6139. struct dsi_display_ctrl *ctrl;
  6140. if (!disp->panel || !disp->panel->cur_mode || !disp->panel->cur_mode->priv_info)
  6141. return -EINVAL;
  6142. transfer_time_min = disp->panel->cur_mode->priv_info->mdp_transfer_time_us_min;
  6143. transfer_time_max = disp->panel->cur_mode->priv_info->mdp_transfer_time_us_max;
  6144. if (!transfer_time_min || !transfer_time_max)
  6145. return 0;
  6146. if (transfer_time < transfer_time_min || transfer_time > transfer_time_max) {
  6147. DSI_ERR("invalid transfer time %u, min: %u, max: %u\n",
  6148. transfer_time, transfer_time_min, transfer_time_max);
  6149. return -EINVAL;
  6150. }
  6151. disp->panel->cur_mode->priv_info->mdp_transfer_time_us = transfer_time;
  6152. disp->panel->cur_mode->priv_info->dsi_transfer_time_us = transfer_time;
  6153. display_for_each_ctrl(i, disp) {
  6154. ctrl = &disp->ctrl[i];
  6155. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &disp->config,
  6156. disp->panel->cur_mode, 0x0,
  6157. disp->dsi_clk_handle);
  6158. if (rc) {
  6159. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n", disp->name, rc);
  6160. return rc;
  6161. }
  6162. }
  6163. atomic_set(&disp->clkrate_change_pending, 1);
  6164. return 0;
  6165. }
  6166. int dsi_display_get_panel_scan_line(void *display, u16 *scan_line, ktime_t *scan_line_ts)
  6167. {
  6168. struct dsi_display *dsi_display = (struct dsi_display *)display;
  6169. u8 scan_line_tx_buffer[] = {0x6, 0x1, 0x0, 0xa, 0x0, 0x0, 0x1, 0x45};
  6170. u8 rx_buffer[2];
  6171. int rx_len, rc = 0;
  6172. ktime_t ts = 0;
  6173. if (!dsi_display || !scan_line || !scan_line_ts)
  6174. return -EINVAL;
  6175. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6176. rx_len = dsi_display_cmd_receive(dsi_display, scan_line_tx_buffer,
  6177. ARRAY_SIZE(scan_line_tx_buffer), rx_buffer, ARRAY_SIZE(rx_buffer), &ts);
  6178. if (rx_len <= 0) {
  6179. rc = -EINVAL;
  6180. goto end;
  6181. }
  6182. *scan_line = (rx_buffer[0] << 8) | rx_buffer[1];
  6183. *scan_line_ts = ts;
  6184. end:
  6185. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rx_len, rx_buffer[0], rx_buffer[1],
  6186. ktime_us_delta(ktime_get(), ts));
  6187. return rc;
  6188. }
  6189. static bool dsi_display_match_timings(const struct dsi_display_mode *mode1,
  6190. struct dsi_display_mode *mode2, unsigned int match_flags)
  6191. {
  6192. bool is_matching = false;
  6193. if (match_flags & DSI_MODE_MATCH_ACTIVE_TIMINGS) {
  6194. is_matching = mode1->timing.h_active == mode2->timing.h_active &&
  6195. mode1->timing.v_active == mode2->timing.v_active &&
  6196. mode1->timing.refresh_rate == mode2->timing.refresh_rate;
  6197. if (!is_matching)
  6198. goto end;
  6199. }
  6200. if (match_flags & DSI_MODE_MATCH_PORCH_TIMINGS)
  6201. is_matching = mode1->timing.h_back_porch == mode2->timing.h_back_porch &&
  6202. mode1->timing.h_front_porch == mode2->timing.h_front_porch &&
  6203. mode1->timing.h_sync_width == mode2->timing.h_sync_width &&
  6204. mode1->timing.h_skew == mode2->timing.h_skew &&
  6205. mode1->timing.v_back_porch == mode2->timing.v_back_porch &&
  6206. mode1->timing.v_front_porch == mode2->timing.v_front_porch &&
  6207. mode1->timing.v_sync_width == mode2->timing.v_sync_width;
  6208. end:
  6209. return is_matching;
  6210. }
  6211. bool dsi_display_mode_match(const struct dsi_display_mode *mode1,
  6212. struct dsi_display_mode *mode2, unsigned int match_flags)
  6213. {
  6214. if (!mode1 && !mode2)
  6215. return true;
  6216. if (!mode1 || !mode2)
  6217. return false;
  6218. if ((match_flags & DSI_MODE_MATCH_FULL_TIMINGS) &&
  6219. !dsi_display_match_timings(mode1, mode2, match_flags))
  6220. return false;
  6221. if ((match_flags & DSI_MODE_MATCH_DSC_CONFIG) &&
  6222. mode1->priv_info->dsc_enabled != mode2->priv_info->dsc_enabled)
  6223. return false;
  6224. return true;
  6225. }
  6226. int dsi_display_find_mode(struct dsi_display *display,
  6227. struct dsi_display_mode *cmp,
  6228. struct msm_sub_mode *sub_mode,
  6229. struct dsi_display_mode **out_mode)
  6230. {
  6231. u32 count, i;
  6232. int rc;
  6233. struct dsi_display_mode *m;
  6234. struct dsi_dyn_clk_caps *dyn_clk_caps;
  6235. unsigned int match_flags = DSI_MODE_MATCH_FULL_TIMINGS;
  6236. struct dsi_display_mode_priv_info *priv_info;
  6237. if (!display || !out_mode)
  6238. return -EINVAL;
  6239. *out_mode = NULL;
  6240. mutex_lock(&display->display_lock);
  6241. count = display->panel->num_display_modes;
  6242. mutex_unlock(&display->display_lock);
  6243. if (!display->modes) {
  6244. rc = dsi_display_get_modes(display, &m);
  6245. if (rc)
  6246. return rc;
  6247. }
  6248. priv_info = kvzalloc(sizeof(struct dsi_display_mode_priv_info),
  6249. GFP_KERNEL);
  6250. if (ZERO_OR_NULL_PTR(priv_info))
  6251. return -ENOMEM;
  6252. mutex_lock(&display->display_lock);
  6253. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  6254. for (i = 0; i < count; i++) {
  6255. m = &display->modes[i];
  6256. /**
  6257. * When dynamic bit clock is enabled with contants FPS,
  6258. * the adjusted mode porches value may not match the panel
  6259. * default mode porches and panel mode lookup will fail.
  6260. * In that case we omit porches in mode matching function.
  6261. */
  6262. if (dyn_clk_caps->maintain_const_fps)
  6263. match_flags = DSI_MODE_MATCH_ACTIVE_TIMINGS;
  6264. if (sub_mode && sub_mode->dsc_mode) {
  6265. match_flags |= DSI_MODE_MATCH_DSC_CONFIG;
  6266. cmp->priv_info = priv_info;
  6267. cmp->priv_info->dsc_enabled = (sub_mode->dsc_mode ==
  6268. MSM_DISPLAY_DSC_MODE_ENABLED) ? true : false;
  6269. }
  6270. if (dsi_display_mode_match(cmp, m, match_flags)) {
  6271. *out_mode = m;
  6272. rc = 0;
  6273. break;
  6274. }
  6275. }
  6276. cmp->priv_info = NULL;
  6277. mutex_unlock(&display->display_lock);
  6278. kvfree(priv_info);
  6279. if (!*out_mode) {
  6280. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  6281. display->name, cmp->timing.v_active,
  6282. cmp->timing.h_active, cmp->timing.refresh_rate,
  6283. cmp->pixel_clk_khz);
  6284. rc = -ENOENT;
  6285. }
  6286. return rc;
  6287. }
  6288. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  6289. struct dsi_display_mode *adj)
  6290. {
  6291. /*
  6292. * If there is a change in the hfp or vfp of the current and adjoining
  6293. * mode,then either it is a dfps mode switch or dynamic clk change with
  6294. * constant fps.
  6295. */
  6296. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  6297. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  6298. return true;
  6299. else
  6300. return false;
  6301. }
  6302. /**
  6303. * dsi_display_validate_mode_change() - Validate mode change case.
  6304. * @display: DSI display handle.
  6305. * @cur_mode: Current mode.
  6306. * @adj_mode: Mode to be set.
  6307. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  6308. * is change in hfp or vfp but vactive and hactive are same.
  6309. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  6310. * is change in clk but vactive and hactive are same.
  6311. * Return: error code.
  6312. */
  6313. int dsi_display_validate_mode_change(struct dsi_display *display,
  6314. struct dsi_display_mode *cur_mode,
  6315. struct dsi_display_mode *adj_mode)
  6316. {
  6317. int rc = 0;
  6318. struct dsi_dfps_capabilities dfps_caps;
  6319. struct dsi_dyn_clk_caps *dyn_clk_caps;
  6320. struct sde_connector *sde_conn;
  6321. if (!display || !adj_mode || !display->drm_conn) {
  6322. DSI_ERR("Invalid params\n");
  6323. return -EINVAL;
  6324. }
  6325. if (!display->panel || !display->panel->cur_mode) {
  6326. DSI_DEBUG("Current panel mode not set\n");
  6327. return rc;
  6328. }
  6329. if ((cur_mode->timing.v_active != adj_mode->timing.v_active) ||
  6330. (cur_mode->timing.h_active != adj_mode->timing.h_active)) {
  6331. DSI_DEBUG("Avoid VRR and POMS when resolution is changed\n");
  6332. return rc;
  6333. }
  6334. sde_conn = to_sde_connector(display->drm_conn);
  6335. mutex_lock(&display->display_lock);
  6336. if (sde_conn->expected_panel_mode == MSM_DISPLAY_VIDEO_MODE &&
  6337. display->config.panel_mode == DSI_OP_CMD_MODE) {
  6338. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  6339. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, sde_conn->expected_panel_mode,
  6340. display->config.panel_mode);
  6341. DSI_DEBUG("Panel operating mode change to video detected\n");
  6342. } else if (sde_conn->expected_panel_mode == MSM_DISPLAY_CMD_MODE &&
  6343. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6344. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  6345. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, sde_conn->expected_panel_mode,
  6346. display->config.panel_mode);
  6347. DSI_DEBUG("Panel operating mode change to command detected\n");
  6348. } else if (cur_mode->timing.dsc_enabled != adj_mode->timing.dsc_enabled) {
  6349. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  6350. SDE_EVT32(SDE_EVTLOG_FUNC_CASE3, cur_mode->timing.dsc_enabled,
  6351. adj_mode->timing.dsc_enabled);
  6352. DSI_DEBUG("DSC mode change detected\n");
  6353. } else {
  6354. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  6355. /* dfps and dynamic clock with const fps use case */
  6356. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  6357. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  6358. if (dfps_caps.dfps_support ||
  6359. dyn_clk_caps->maintain_const_fps) {
  6360. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  6361. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  6362. SDE_EVT32(SDE_EVTLOG_FUNC_CASE4,
  6363. cur_mode->timing.refresh_rate,
  6364. adj_mode->timing.refresh_rate,
  6365. cur_mode->timing.h_front_porch,
  6366. adj_mode->timing.h_front_porch,
  6367. cur_mode->timing.v_front_porch,
  6368. adj_mode->timing.v_front_porch);
  6369. }
  6370. }
  6371. /* dynamic clk change use case */
  6372. if (display->dyn_bit_clk_pending) {
  6373. if (dyn_clk_caps->dyn_clk_support) {
  6374. DSI_DEBUG("dynamic clk change detected\n");
  6375. if ((adj_mode->dsi_mode_flags &
  6376. DSI_MODE_FLAG_VRR) &&
  6377. (!dyn_clk_caps->maintain_const_fps)) {
  6378. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  6379. rc = -ENOTSUPP;
  6380. goto error;
  6381. }
  6382. /**
  6383. * Set VRR flag whenever there is a dynamic clock
  6384. * change on video mode panel as dynamic refresh is
  6385. * always required when fps compensation is enabled.
  6386. */
  6387. if ((display->config.panel_mode == DSI_OP_VIDEO_MODE) &&
  6388. dyn_clk_caps->maintain_const_fps)
  6389. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  6390. adj_mode->dsi_mode_flags |=
  6391. DSI_MODE_FLAG_DYN_CLK;
  6392. SDE_EVT32(SDE_EVTLOG_FUNC_CASE5,
  6393. cur_mode->pixel_clk_khz,
  6394. adj_mode->pixel_clk_khz);
  6395. }
  6396. display->dyn_bit_clk_pending = false;
  6397. }
  6398. }
  6399. error:
  6400. mutex_unlock(&display->display_lock);
  6401. return rc;
  6402. }
  6403. int dsi_display_validate_mode(struct dsi_display *display,
  6404. struct dsi_display_mode *mode,
  6405. u32 flags)
  6406. {
  6407. int rc = 0;
  6408. int i;
  6409. struct dsi_display_ctrl *ctrl;
  6410. struct dsi_display_mode adj_mode;
  6411. if (!display || !mode) {
  6412. DSI_ERR("Invalid params\n");
  6413. return -EINVAL;
  6414. }
  6415. mutex_lock(&display->display_lock);
  6416. adj_mode = *mode;
  6417. adjust_timing_by_ctrl_count(display, &adj_mode);
  6418. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  6419. if (rc) {
  6420. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  6421. display->name, rc);
  6422. goto error;
  6423. }
  6424. display_for_each_ctrl(i, display) {
  6425. ctrl = &display->ctrl[i];
  6426. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  6427. if (rc) {
  6428. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  6429. display->name, rc);
  6430. goto error;
  6431. }
  6432. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  6433. if (rc) {
  6434. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  6435. display->name, rc);
  6436. goto error;
  6437. }
  6438. }
  6439. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  6440. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  6441. rc = dsi_display_validate_mode_seamless(display, mode);
  6442. if (rc) {
  6443. DSI_ERR("[%s] seamless not possible rc=%d\n",
  6444. display->name, rc);
  6445. goto error;
  6446. }
  6447. }
  6448. error:
  6449. mutex_unlock(&display->display_lock);
  6450. return rc;
  6451. }
  6452. int dsi_display_set_mode(struct dsi_display *display,
  6453. struct dsi_display_mode *mode,
  6454. u32 flags)
  6455. {
  6456. int rc = 0;
  6457. struct dsi_display_mode adj_mode;
  6458. struct dsi_mode_info timing;
  6459. if (!display || !mode || !display->panel) {
  6460. DSI_ERR("Invalid params\n");
  6461. return -EINVAL;
  6462. }
  6463. mutex_lock(&display->display_lock);
  6464. adj_mode = *mode;
  6465. timing = adj_mode.timing;
  6466. adjust_timing_by_ctrl_count(display, &adj_mode);
  6467. if (!display->panel->cur_mode) {
  6468. display->panel->cur_mode =
  6469. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  6470. if (!display->panel->cur_mode) {
  6471. rc = -ENOMEM;
  6472. goto error;
  6473. }
  6474. }
  6475. rc = dsi_display_restore_bit_clk(display, &adj_mode);
  6476. if (rc) {
  6477. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  6478. goto error;
  6479. }
  6480. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  6481. if (rc) {
  6482. DSI_ERR("[%s] mode cannot be set\n", display->name);
  6483. goto error;
  6484. }
  6485. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  6486. if (rc) {
  6487. DSI_ERR("[%s] failed to set mode\n", display->name);
  6488. goto error;
  6489. }
  6490. DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d, clk_rate=%llu\n",
  6491. adj_mode.priv_info->mdp_transfer_time_us,
  6492. timing.h_active, timing.v_active, timing.refresh_rate,
  6493. adj_mode.priv_info->clk_rate_hz);
  6494. SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
  6495. timing.h_active, timing.v_active, timing.refresh_rate,
  6496. adj_mode.priv_info->clk_rate_hz);
  6497. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  6498. error:
  6499. mutex_unlock(&display->display_lock);
  6500. return rc;
  6501. }
  6502. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable,
  6503. enum dsi_test_pattern type,
  6504. u32 init_val,
  6505. enum dsi_ctrl_tpg_pattern pattern)
  6506. {
  6507. int rc = 0;
  6508. int i;
  6509. struct dsi_display_ctrl *ctrl;
  6510. if (!display) {
  6511. DSI_ERR("Invalid params\n");
  6512. return -EINVAL;
  6513. }
  6514. display_for_each_ctrl(i, display) {
  6515. ctrl = &display->ctrl[i];
  6516. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable, type, init_val, pattern);
  6517. if (rc) {
  6518. DSI_ERR("[%s] failed to set tpg state for host_%d\n", display->name, i);
  6519. goto error;
  6520. }
  6521. if (enable && ctrl->ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) {
  6522. rc = dsi_ctrl_trigger_test_pattern(ctrl->ctrl);
  6523. if (rc) {
  6524. DSI_ERR("[%s] failed to start tpg for host_%d\n", display->name, i);
  6525. goto error;
  6526. }
  6527. }
  6528. }
  6529. display->is_tpg_enabled = enable;
  6530. error:
  6531. return rc;
  6532. }
  6533. static int dsi_display_pre_switch(struct dsi_display *display)
  6534. {
  6535. int rc = 0;
  6536. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6537. DSI_CORE_CLK, DSI_CLK_ON);
  6538. if (rc) {
  6539. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6540. display->name, rc);
  6541. goto error;
  6542. }
  6543. rc = dsi_display_ctrl_update(display);
  6544. if (rc) {
  6545. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  6546. display->name, rc);
  6547. goto error_ctrl_clk_off;
  6548. }
  6549. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6550. DSI_LINK_CLK, DSI_CLK_ON);
  6551. if (rc) {
  6552. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6553. display->name, rc);
  6554. goto error_ctrl_deinit;
  6555. }
  6556. goto error;
  6557. error_ctrl_deinit:
  6558. (void)dsi_display_ctrl_deinit(display);
  6559. error_ctrl_clk_off:
  6560. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6561. DSI_CORE_CLK, DSI_CLK_OFF);
  6562. error:
  6563. return rc;
  6564. }
  6565. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  6566. {
  6567. int i;
  6568. struct dsi_display_ctrl *ctrl;
  6569. display_for_each_ctrl(i, display) {
  6570. ctrl = &display->ctrl[i];
  6571. if (!ctrl->ctrl)
  6572. continue;
  6573. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  6574. return false;
  6575. }
  6576. return true;
  6577. }
  6578. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  6579. {
  6580. struct dsi_display *display = NULL;
  6581. display = container_of(work, struct dsi_display, fifo_underflow_work);
  6582. if (!display || !display->panel ||
  6583. atomic_read(&display->panel->esd_recovery_pending)) {
  6584. DSI_DEBUG("Invalid recovery use case\n");
  6585. return;
  6586. }
  6587. mutex_lock(&display->display_lock);
  6588. if (!_dsi_display_validate_host_state(display)) {
  6589. mutex_unlock(&display->display_lock);
  6590. return;
  6591. }
  6592. DSI_INFO("handle DSI FIFO underflow error\n");
  6593. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6594. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6595. DSI_ALL_CLKS, DSI_CLK_ON);
  6596. dsi_display_soft_reset(display);
  6597. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6598. DSI_ALL_CLKS, DSI_CLK_OFF);
  6599. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6600. mutex_unlock(&display->display_lock);
  6601. }
  6602. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6603. {
  6604. struct dsi_display *display = NULL;
  6605. struct dsi_display_ctrl *ctrl;
  6606. int i, rc;
  6607. int mask = BIT(20); /* clock lane */
  6608. int (*cb_func)(void *event_usr_ptr,
  6609. uint32_t event_idx, uint32_t instance_idx,
  6610. uint32_t data0, uint32_t data1,
  6611. uint32_t data2, uint32_t data3);
  6612. void *data;
  6613. u32 version = 0;
  6614. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6615. if (!display || !display->panel ||
  6616. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6617. atomic_read(&display->panel->esd_recovery_pending)) {
  6618. DSI_DEBUG("Invalid recovery use case\n");
  6619. return;
  6620. }
  6621. mutex_lock(&display->display_lock);
  6622. if (!_dsi_display_validate_host_state(display)) {
  6623. mutex_unlock(&display->display_lock);
  6624. return;
  6625. }
  6626. DSI_INFO("handle DSI FIFO overflow error\n");
  6627. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6628. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6629. DSI_ALL_CLKS, DSI_CLK_ON);
  6630. /*
  6631. * below recovery sequence is not applicable to
  6632. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6633. */
  6634. ctrl = &display->ctrl[display->clk_master_idx];
  6635. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6636. if (!version || (version < 0x20020001))
  6637. goto end;
  6638. /* reset ctrl and lanes */
  6639. display_for_each_ctrl(i, display) {
  6640. ctrl = &display->ctrl[i];
  6641. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6642. rc = dsi_phy_lane_reset(ctrl->phy);
  6643. }
  6644. /* wait for display line count to be in active area */
  6645. ctrl = &display->ctrl[display->clk_master_idx];
  6646. if (ctrl->ctrl->recovery_cb.event_cb) {
  6647. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6648. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6649. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6650. display->clk_master_idx, 0, 0, 0, 0);
  6651. if (rc < 0) {
  6652. DSI_DEBUG("sde callback failed\n");
  6653. goto end;
  6654. }
  6655. }
  6656. /* Enable Video mode for DSI controller */
  6657. display_for_each_ctrl(i, display) {
  6658. ctrl = &display->ctrl[i];
  6659. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6660. }
  6661. /*
  6662. * Add sufficient delay to make sure
  6663. * pixel transmission has started
  6664. */
  6665. udelay(200);
  6666. end:
  6667. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6668. DSI_ALL_CLKS, DSI_CLK_OFF);
  6669. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6670. mutex_unlock(&display->display_lock);
  6671. }
  6672. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6673. {
  6674. struct dsi_display *display = NULL;
  6675. struct dsi_display_ctrl *ctrl;
  6676. int i, rc;
  6677. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6678. int (*cb_func)(void *event_usr_ptr,
  6679. uint32_t event_idx, uint32_t instance_idx,
  6680. uint32_t data0, uint32_t data1,
  6681. uint32_t data2, uint32_t data3);
  6682. void *data;
  6683. u32 version = 0;
  6684. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6685. if (!display || !display->panel ||
  6686. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6687. atomic_read(&display->panel->esd_recovery_pending)) {
  6688. DSI_DEBUG("Invalid recovery use case\n");
  6689. return;
  6690. }
  6691. mutex_lock(&display->display_lock);
  6692. if (!_dsi_display_validate_host_state(display)) {
  6693. mutex_unlock(&display->display_lock);
  6694. return;
  6695. }
  6696. DSI_INFO("handle DSI LP RX Timeout error\n");
  6697. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6698. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6699. DSI_ALL_CLKS, DSI_CLK_ON);
  6700. /*
  6701. * below recovery sequence is not applicable to
  6702. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6703. */
  6704. ctrl = &display->ctrl[display->clk_master_idx];
  6705. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6706. if (!version || (version < 0x20020001))
  6707. goto end;
  6708. /* reset ctrl and lanes */
  6709. display_for_each_ctrl(i, display) {
  6710. ctrl = &display->ctrl[i];
  6711. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6712. rc = dsi_phy_lane_reset(ctrl->phy);
  6713. }
  6714. ctrl = &display->ctrl[display->clk_master_idx];
  6715. if (ctrl->ctrl->recovery_cb.event_cb) {
  6716. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6717. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6718. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6719. display->clk_master_idx, 0, 0, 0, 0);
  6720. if (rc < 0) {
  6721. DSI_DEBUG("Target is in suspend/shutdown\n");
  6722. goto end;
  6723. }
  6724. }
  6725. /* Enable Video mode for DSI controller */
  6726. display_for_each_ctrl(i, display) {
  6727. ctrl = &display->ctrl[i];
  6728. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6729. }
  6730. /*
  6731. * Add sufficient delay to make sure
  6732. * pixel transmission as started
  6733. */
  6734. udelay(200);
  6735. end:
  6736. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6737. DSI_ALL_CLKS, DSI_CLK_OFF);
  6738. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6739. mutex_unlock(&display->display_lock);
  6740. }
  6741. static int dsi_display_cb_error_handler(void *data,
  6742. uint32_t event_idx, uint32_t instance_idx,
  6743. uint32_t data0, uint32_t data1,
  6744. uint32_t data2, uint32_t data3)
  6745. {
  6746. struct dsi_display *display = data;
  6747. if (!display || !(display->err_workq))
  6748. return -EINVAL;
  6749. switch (event_idx) {
  6750. case DSI_FIFO_UNDERFLOW:
  6751. queue_work(display->err_workq, &display->fifo_underflow_work);
  6752. break;
  6753. case DSI_FIFO_OVERFLOW:
  6754. queue_work(display->err_workq, &display->fifo_overflow_work);
  6755. break;
  6756. case DSI_LP_Rx_TIMEOUT:
  6757. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6758. break;
  6759. default:
  6760. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6761. break;
  6762. }
  6763. return 0;
  6764. }
  6765. static void dsi_display_register_error_handler(struct dsi_display *display)
  6766. {
  6767. int i = 0;
  6768. struct dsi_display_ctrl *ctrl;
  6769. struct dsi_event_cb_info event_info;
  6770. if (!display)
  6771. return;
  6772. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6773. if (!display->err_workq) {
  6774. DSI_ERR("failed to create dsi workq!\n");
  6775. return;
  6776. }
  6777. INIT_WORK(&display->fifo_underflow_work,
  6778. dsi_display_handle_fifo_underflow);
  6779. INIT_WORK(&display->fifo_overflow_work,
  6780. dsi_display_handle_fifo_overflow);
  6781. INIT_WORK(&display->lp_rx_timeout_work,
  6782. dsi_display_handle_lp_rx_timeout);
  6783. memset(&event_info, 0, sizeof(event_info));
  6784. event_info.event_cb = dsi_display_cb_error_handler;
  6785. event_info.event_usr_ptr = display;
  6786. display_for_each_ctrl(i, display) {
  6787. ctrl = &display->ctrl[i];
  6788. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6789. }
  6790. }
  6791. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6792. {
  6793. int i = 0;
  6794. struct dsi_display_ctrl *ctrl;
  6795. if (!display)
  6796. return;
  6797. display_for_each_ctrl(i, display) {
  6798. ctrl = &display->ctrl[i];
  6799. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6800. 0, sizeof(struct dsi_event_cb_info));
  6801. }
  6802. if (display->err_workq) {
  6803. destroy_workqueue(display->err_workq);
  6804. display->err_workq = NULL;
  6805. }
  6806. }
  6807. int dsi_display_prepare(struct dsi_display *display)
  6808. {
  6809. int rc = 0;
  6810. struct dsi_display_mode *mode;
  6811. if (!display) {
  6812. DSI_ERR("Invalid params\n");
  6813. return -EINVAL;
  6814. }
  6815. if (!display->panel->cur_mode) {
  6816. DSI_ERR("no valid mode set for the display\n");
  6817. return -EINVAL;
  6818. }
  6819. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6820. mutex_lock(&display->display_lock);
  6821. display->hw_ownership = true;
  6822. mode = display->panel->cur_mode;
  6823. dsi_display_set_ctrl_esd_check_flag(display, false);
  6824. /* Set up ctrl isr before enabling core clk */
  6825. if (!display->trusted_vm_env)
  6826. dsi_display_ctrl_isr_configure(display, true);
  6827. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6828. if (display->is_cont_splash_enabled &&
  6829. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6830. DSI_ERR("DMS not supported on first frame\n");
  6831. rc = -EINVAL;
  6832. goto error;
  6833. }
  6834. if (!is_skip_op_required(display)) {
  6835. /* update dsi ctrl for new mode */
  6836. rc = dsi_display_pre_switch(display);
  6837. if (rc)
  6838. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6839. display->name, rc);
  6840. goto error;
  6841. }
  6842. }
  6843. if (!display->poms_pending &&
  6844. (!is_skip_op_required(display))) {
  6845. /*
  6846. * For continuous splash/trusted vm, we skip panel
  6847. * pre prepare since the regulator vote is already
  6848. * taken care in splash resource init
  6849. */
  6850. rc = dsi_panel_pre_prepare(display->panel);
  6851. if (rc) {
  6852. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6853. display->name, rc);
  6854. goto error;
  6855. }
  6856. }
  6857. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6858. DSI_CORE_CLK, DSI_CLK_ON);
  6859. if (rc) {
  6860. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6861. display->name, rc);
  6862. goto error_panel_post_unprep;
  6863. }
  6864. /*
  6865. * If ULPS during suspend feature is enabled, then DSI PHY was
  6866. * left on during suspend. In this case, we do not need to reset/init
  6867. * PHY. This would have already been done when the CORE clocks are
  6868. * turned on. However, if cont splash is disabled, the first time DSI
  6869. * is powered on, phy init needs to be done unconditionally.
  6870. */
  6871. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6872. rc = dsi_display_phy_sw_reset(display);
  6873. if (rc) {
  6874. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6875. display->name, rc);
  6876. goto error_ctrl_clk_off;
  6877. }
  6878. rc = dsi_display_phy_enable(display);
  6879. if (rc) {
  6880. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6881. display->name, rc);
  6882. goto error_ctrl_clk_off;
  6883. }
  6884. }
  6885. rc = dsi_display_ctrl_init(display);
  6886. if (rc) {
  6887. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6888. display->name, rc);
  6889. goto error_phy_disable;
  6890. }
  6891. /* Set up DSI ERROR event callback */
  6892. dsi_display_register_error_handler(display);
  6893. rc = dsi_display_ctrl_host_enable(display);
  6894. if (rc) {
  6895. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6896. display->name, rc);
  6897. goto error_ctrl_deinit;
  6898. }
  6899. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6900. DSI_LINK_CLK, DSI_CLK_ON);
  6901. if (rc) {
  6902. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6903. display->name, rc);
  6904. goto error_host_engine_off;
  6905. }
  6906. if (!is_skip_op_required(display)) {
  6907. /*
  6908. * For continuous splash/trusted vm, skip panel prepare and
  6909. * ctl reset since the pnael and ctrl is already in active
  6910. * state and panel on commands are not needed
  6911. */
  6912. rc = dsi_display_soft_reset(display);
  6913. if (rc) {
  6914. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6915. display->name, rc);
  6916. goto error_ctrl_link_off;
  6917. }
  6918. if (!display->poms_pending) {
  6919. rc = dsi_panel_prepare(display->panel);
  6920. if (rc) {
  6921. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6922. display->name, rc);
  6923. goto error_ctrl_link_off;
  6924. }
  6925. }
  6926. }
  6927. goto error;
  6928. error_ctrl_link_off:
  6929. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6930. DSI_LINK_CLK, DSI_CLK_OFF);
  6931. error_host_engine_off:
  6932. (void)dsi_display_ctrl_host_disable(display);
  6933. error_ctrl_deinit:
  6934. (void)dsi_display_ctrl_deinit(display);
  6935. error_phy_disable:
  6936. (void)dsi_display_phy_disable(display);
  6937. error_ctrl_clk_off:
  6938. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6939. DSI_CORE_CLK, DSI_CLK_OFF);
  6940. error_panel_post_unprep:
  6941. (void)dsi_panel_post_unprepare(display->panel);
  6942. error:
  6943. mutex_unlock(&display->display_lock);
  6944. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6945. return rc;
  6946. }
  6947. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6948. const struct dsi_display_ctrl *ctrl,
  6949. const struct msm_roi_list *req_rois,
  6950. struct dsi_rect *out_roi)
  6951. {
  6952. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6953. struct dsi_display_mode *cur_mode;
  6954. struct msm_roi_caps *roi_caps;
  6955. struct dsi_rect req_roi = { 0 };
  6956. int rc = 0;
  6957. cur_mode = display->panel->cur_mode;
  6958. if (!cur_mode)
  6959. return 0;
  6960. roi_caps = &cur_mode->priv_info->roi_caps;
  6961. if (req_rois->num_rects > roi_caps->num_roi) {
  6962. DSI_ERR("request for %d rois greater than max %d\n",
  6963. req_rois->num_rects,
  6964. roi_caps->num_roi);
  6965. rc = -EINVAL;
  6966. goto exit;
  6967. }
  6968. /**
  6969. * if no rois, user wants to reset back to full resolution
  6970. * note: h_active is already divided by ctrl_count
  6971. */
  6972. if (!req_rois->num_rects) {
  6973. *out_roi = *bounds;
  6974. goto exit;
  6975. }
  6976. /* intersect with the bounds */
  6977. req_roi.x = req_rois->roi[0].x1;
  6978. req_roi.y = req_rois->roi[0].y1;
  6979. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6980. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6981. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6982. exit:
  6983. /* adjust the ctrl origin to be top left within the ctrl */
  6984. out_roi->x = out_roi->x - bounds->x;
  6985. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6986. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6987. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6988. bounds->x, bounds->y, bounds->w, bounds->h,
  6989. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6990. return rc;
  6991. }
  6992. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6993. {
  6994. int i;
  6995. int rc = 0;
  6996. mutex_lock(&display->display_lock);
  6997. display_for_each_ctrl(i, display) {
  6998. if (enable) {
  6999. /* send the commands to enable qsync */
  7000. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  7001. if (rc) {
  7002. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  7003. goto exit;
  7004. }
  7005. } else {
  7006. /* send the commands to enable qsync */
  7007. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  7008. if (rc) {
  7009. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  7010. goto exit;
  7011. }
  7012. }
  7013. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  7014. }
  7015. exit:
  7016. SDE_EVT32(enable, display->panel->qsync_caps.qsync_min_fps, rc);
  7017. mutex_unlock(&display->display_lock);
  7018. return rc;
  7019. }
  7020. static int dsi_display_set_roi(struct dsi_display *display,
  7021. struct msm_roi_list *rois)
  7022. {
  7023. struct dsi_display_mode *cur_mode;
  7024. struct msm_roi_caps *roi_caps;
  7025. int rc = 0;
  7026. int i;
  7027. if (!display || !rois || !display->panel)
  7028. return -EINVAL;
  7029. cur_mode = display->panel->cur_mode;
  7030. if (!cur_mode)
  7031. return 0;
  7032. roi_caps = &cur_mode->priv_info->roi_caps;
  7033. if (!roi_caps->enabled)
  7034. return 0;
  7035. display_for_each_ctrl(i, display) {
  7036. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  7037. struct dsi_rect ctrl_roi;
  7038. bool changed = false;
  7039. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  7040. if (rc) {
  7041. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  7042. return rc;
  7043. }
  7044. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  7045. if (rc) {
  7046. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  7047. return rc;
  7048. }
  7049. if (!changed)
  7050. continue;
  7051. /* re-program the ctrl with the timing based on the new roi */
  7052. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  7053. if (rc) {
  7054. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  7055. return rc;
  7056. }
  7057. /* send the new roi to the panel via dcs commands */
  7058. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  7059. if (rc) {
  7060. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  7061. return rc;
  7062. }
  7063. }
  7064. return rc;
  7065. }
  7066. int dsi_display_pre_kickoff(struct drm_connector *connector,
  7067. struct dsi_display *display,
  7068. struct msm_display_kickoff_params *params)
  7069. {
  7070. int rc = 0, ret = 0;
  7071. int i;
  7072. /* check and setup MISR */
  7073. if (display->misr_enable)
  7074. _dsi_display_setup_misr(display);
  7075. /* dynamic DSI clock setting */
  7076. if (atomic_read(&display->clkrate_change_pending)) {
  7077. mutex_lock(&display->display_lock);
  7078. /*
  7079. * acquire panel_lock to make sure no commands are in progress
  7080. */
  7081. dsi_panel_acquire_panel_lock(display->panel);
  7082. /*
  7083. * Wait for DSI command engine not to be busy sending data
  7084. * from display engine.
  7085. * If waiting fails, return "rc" instead of below "ret" so as
  7086. * not to impact DRM commit. The clock updating would be
  7087. * deferred to the next DRM commit.
  7088. */
  7089. display_for_each_ctrl(i, display) {
  7090. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  7091. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  7092. if (ret)
  7093. goto wait_failure;
  7094. }
  7095. /*
  7096. * Don't check the return value so as not to impact DRM commit
  7097. * when error occurs.
  7098. */
  7099. (void)dsi_display_force_update_dsi_clk(display);
  7100. wait_failure:
  7101. /* release panel_lock */
  7102. dsi_panel_release_panel_lock(display->panel);
  7103. mutex_unlock(&display->display_lock);
  7104. }
  7105. if (!ret)
  7106. rc = dsi_display_set_roi(display, params->rois);
  7107. return rc;
  7108. }
  7109. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  7110. {
  7111. int rc = 0;
  7112. if (!display || !display->panel) {
  7113. DSI_ERR("Invalid params\n");
  7114. return -EINVAL;
  7115. }
  7116. if (!display->panel->cur_mode) {
  7117. DSI_ERR("no valid mode set for the display\n");
  7118. return -EINVAL;
  7119. }
  7120. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7121. rc = dsi_display_vid_engine_enable(display);
  7122. if (rc) {
  7123. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  7124. display->name, rc);
  7125. goto error_out;
  7126. }
  7127. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  7128. rc = dsi_display_cmd_engine_enable(display);
  7129. if (rc) {
  7130. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  7131. display->name, rc);
  7132. goto error_out;
  7133. }
  7134. } else {
  7135. DSI_ERR("[%s] Invalid configuration\n", display->name);
  7136. rc = -EINVAL;
  7137. }
  7138. error_out:
  7139. return rc;
  7140. }
  7141. int dsi_display_pre_commit(void *display,
  7142. struct msm_display_conn_params *params)
  7143. {
  7144. bool enable = false;
  7145. int rc = 0;
  7146. if (!display || !params) {
  7147. pr_err("Invalid params\n");
  7148. return -EINVAL;
  7149. }
  7150. if (params->qsync_update) {
  7151. enable = (params->qsync_mode > 0) ? true : false;
  7152. rc = dsi_display_qsync(display, enable);
  7153. if (rc)
  7154. pr_err("%s failed to send qsync commands\n",
  7155. __func__);
  7156. SDE_EVT32(params->qsync_mode, rc);
  7157. }
  7158. return rc;
  7159. }
  7160. static void dsi_display_panel_id_notification(struct dsi_display *display)
  7161. {
  7162. if (display->panel_id != ~0x0 &&
  7163. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  7164. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  7165. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  7166. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  7167. 0, ((display->panel_id & 0xffffffff00000000) >> 32),
  7168. (display->panel_id & 0xffffffff), 0, 0);
  7169. }
  7170. }
  7171. int dsi_display_enable(struct dsi_display *display)
  7172. {
  7173. int rc = 0;
  7174. struct dsi_display_mode *mode;
  7175. if (!display || !display->panel) {
  7176. DSI_ERR("Invalid params\n");
  7177. return -EINVAL;
  7178. }
  7179. if (!display->panel->cur_mode) {
  7180. DSI_ERR("no valid mode set for the display\n");
  7181. return -EINVAL;
  7182. }
  7183. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7184. /*
  7185. * Engine states and panel states are populated during splash
  7186. * resource/trusted vm and hence we return early
  7187. */
  7188. if (is_skip_op_required(display)) {
  7189. dsi_display_config_ctrl_for_cont_splash(display);
  7190. rc = dsi_display_splash_res_cleanup(display);
  7191. if (rc) {
  7192. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  7193. rc);
  7194. return -EINVAL;
  7195. }
  7196. display->panel->panel_initialized = true;
  7197. DSI_DEBUG("cont splash enabled, display enable not required\n");
  7198. dsi_display_panel_id_notification(display);
  7199. return 0;
  7200. }
  7201. mutex_lock(&display->display_lock);
  7202. mode = display->panel->cur_mode;
  7203. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  7204. rc = dsi_panel_post_switch(display->panel);
  7205. if (rc) {
  7206. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  7207. display->name, rc);
  7208. goto error;
  7209. }
  7210. } else if (!display->poms_pending) {
  7211. rc = dsi_panel_enable(display->panel);
  7212. if (rc) {
  7213. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  7214. display->name, rc);
  7215. goto error;
  7216. }
  7217. }
  7218. dsi_display_panel_id_notification(display);
  7219. /* Block sending pps command if modeset is due to fps difference */
  7220. if ((mode->priv_info->dsc_enabled ||
  7221. mode->priv_info->vdc_enabled) &&
  7222. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  7223. rc = dsi_panel_update_pps(display->panel);
  7224. if (rc) {
  7225. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  7226. display->name, rc);
  7227. goto error;
  7228. }
  7229. }
  7230. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  7231. rc = dsi_panel_switch(display->panel);
  7232. if (rc)
  7233. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  7234. display->name, rc);
  7235. goto error;
  7236. }
  7237. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7238. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  7239. rc = dsi_display_vid_engine_enable(display);
  7240. if (rc) {
  7241. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  7242. display->name, rc);
  7243. goto error_disable_panel;
  7244. }
  7245. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  7246. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  7247. rc = dsi_display_cmd_engine_enable(display);
  7248. if (rc) {
  7249. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  7250. display->name, rc);
  7251. goto error_disable_panel;
  7252. }
  7253. } else {
  7254. DSI_ERR("[%s] Invalid configuration\n", display->name);
  7255. rc = -EINVAL;
  7256. goto error_disable_panel;
  7257. }
  7258. goto error;
  7259. error_disable_panel:
  7260. (void)dsi_panel_disable(display->panel);
  7261. error:
  7262. mutex_unlock(&display->display_lock);
  7263. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7264. return rc;
  7265. }
  7266. int dsi_display_post_enable(struct dsi_display *display)
  7267. {
  7268. int rc = 0;
  7269. if (!display) {
  7270. DSI_ERR("Invalid params\n");
  7271. return -EINVAL;
  7272. }
  7273. mutex_lock(&display->display_lock);
  7274. if (display->panel->cur_mode->dsi_mode_flags &
  7275. DSI_MODE_FLAG_POMS_TO_CMD) {
  7276. dsi_panel_switch_cmd_mode_in(display->panel);
  7277. } else if (display->panel->cur_mode->dsi_mode_flags &
  7278. DSI_MODE_FLAG_POMS_TO_VID)
  7279. dsi_panel_switch_video_mode_in(display->panel);
  7280. else {
  7281. rc = dsi_panel_post_enable(display->panel);
  7282. if (rc)
  7283. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  7284. display->name, rc);
  7285. }
  7286. /* remove the clk vote for CMD mode panels */
  7287. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7288. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7289. DSI_ALL_CLKS, DSI_CLK_OFF);
  7290. mutex_unlock(&display->display_lock);
  7291. return rc;
  7292. }
  7293. int dsi_display_pre_disable(struct dsi_display *display)
  7294. {
  7295. int rc = 0;
  7296. if (!display) {
  7297. DSI_ERR("Invalid params\n");
  7298. return -EINVAL;
  7299. }
  7300. mutex_lock(&display->display_lock);
  7301. /* enable the clk vote for CMD mode panels */
  7302. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7303. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7304. DSI_ALL_CLKS, DSI_CLK_ON);
  7305. if (display->poms_pending) {
  7306. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7307. dsi_panel_switch_cmd_mode_out(display->panel);
  7308. if (display->config.panel_mode == DSI_OP_VIDEO_MODE)
  7309. dsi_panel_switch_video_mode_out(display->panel);
  7310. } else {
  7311. rc = dsi_panel_pre_disable(display->panel);
  7312. if (rc)
  7313. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  7314. display->name, rc);
  7315. }
  7316. mutex_unlock(&display->display_lock);
  7317. return rc;
  7318. }
  7319. static void dsi_display_handle_poms_te(struct work_struct *work)
  7320. {
  7321. struct dsi_display *display = NULL;
  7322. struct delayed_work *dw = to_delayed_work(work);
  7323. struct mipi_dsi_device *dsi = NULL;
  7324. struct dsi_panel *panel = NULL;
  7325. int rc = 0;
  7326. display = container_of(dw, struct dsi_display, poms_te_work);
  7327. if (!display || !display->panel) {
  7328. DSI_ERR("Invalid params\n");
  7329. return;
  7330. }
  7331. panel = display->panel;
  7332. mutex_lock(&panel->panel_lock);
  7333. if (!dsi_panel_initialized(panel)) {
  7334. rc = -EINVAL;
  7335. goto error;
  7336. }
  7337. dsi = &panel->mipi_device;
  7338. rc = mipi_dsi_dcs_set_tear_off(dsi);
  7339. error:
  7340. mutex_unlock(&panel->panel_lock);
  7341. if (rc < 0)
  7342. DSI_ERR("failed to set tear off\n");
  7343. }
  7344. int dsi_display_disable(struct dsi_display *display)
  7345. {
  7346. int rc = 0;
  7347. if (!display) {
  7348. DSI_ERR("Invalid params\n");
  7349. return -EINVAL;
  7350. }
  7351. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7352. mutex_lock(&display->display_lock);
  7353. /* cancel delayed work */
  7354. if (display->poms_pending &&
  7355. display->panel->poms_align_vsync)
  7356. cancel_delayed_work_sync(&display->poms_te_work);
  7357. rc = dsi_display_wake_up(display);
  7358. if (rc)
  7359. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7360. display->name, rc);
  7361. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7362. rc = dsi_display_vid_engine_disable(display);
  7363. if (rc)
  7364. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  7365. display->name, rc);
  7366. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  7367. /**
  7368. * On POMS request , disable panel TE through
  7369. * delayed work queue.
  7370. */
  7371. if (display->poms_pending &&
  7372. display->panel->poms_align_vsync) {
  7373. INIT_DELAYED_WORK(&display->poms_te_work,
  7374. dsi_display_handle_poms_te);
  7375. queue_delayed_work(system_wq,
  7376. &display->poms_te_work,
  7377. msecs_to_jiffies(100));
  7378. }
  7379. rc = dsi_display_cmd_engine_disable(display);
  7380. if (rc)
  7381. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  7382. display->name, rc);
  7383. } else {
  7384. DSI_ERR("[%s] Invalid configuration\n", display->name);
  7385. rc = -EINVAL;
  7386. }
  7387. if (!display->poms_pending && !is_skip_op_required(display)) {
  7388. rc = dsi_panel_disable(display->panel);
  7389. if (rc)
  7390. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  7391. display->name, rc);
  7392. }
  7393. if (is_skip_op_required(display)) {
  7394. /* applicable only for trusted vm */
  7395. display->panel->panel_initialized = false;
  7396. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  7397. }
  7398. mutex_unlock(&display->display_lock);
  7399. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7400. return rc;
  7401. }
  7402. int dsi_display_update_pps(char *pps_cmd, void *disp)
  7403. {
  7404. struct dsi_display *display;
  7405. if (pps_cmd == NULL || disp == NULL) {
  7406. DSI_ERR("Invalid parameter\n");
  7407. return -EINVAL;
  7408. }
  7409. display = disp;
  7410. mutex_lock(&display->display_lock);
  7411. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  7412. mutex_unlock(&display->display_lock);
  7413. return 0;
  7414. }
  7415. int dsi_display_update_dyn_bit_clk(struct dsi_display *display,
  7416. struct dsi_display_mode *mode)
  7417. {
  7418. struct dsi_dyn_clk_caps *dyn_clk_caps;
  7419. struct dsi_host_common_cfg *host_cfg;
  7420. int bpp, lanes = 0;
  7421. if (!display || !mode) {
  7422. DSI_ERR("invalid arguments\n");
  7423. return -EINVAL;
  7424. }
  7425. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  7426. if (!dyn_clk_caps->dyn_clk_support) {
  7427. DSI_DEBUG("dynamic bit clock support not enabled\n");
  7428. return 0;
  7429. } else if (!display->dyn_bit_clk_pending) {
  7430. DSI_DEBUG("dynamic bit clock rate not updated\n");
  7431. return 0;
  7432. } else if (!display->dyn_bit_clk) {
  7433. DSI_DEBUG("dynamic bit clock rate cleared\n");
  7434. return 0;
  7435. } else if (display->dyn_bit_clk < mode->priv_info->min_dsi_clk_hz) {
  7436. DSI_ERR("dynamic bit clock rate %llu smaller than minimum value:%llu\n",
  7437. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz);
  7438. return -EINVAL;
  7439. }
  7440. /* update mode clk rate with user value */
  7441. mode->timing.clk_rate_hz = display->dyn_bit_clk;
  7442. mode->priv_info->clk_rate_hz = display->dyn_bit_clk;
  7443. host_cfg = &(display->panel->host_config);
  7444. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  7445. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  7446. lanes++;
  7447. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  7448. lanes++;
  7449. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  7450. lanes++;
  7451. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  7452. lanes++;
  7453. dsi_display_adjust_mode_timing(display, mode, lanes, bpp);
  7454. SDE_EVT32(display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, mode->pixel_clk_khz);
  7455. DSI_DEBUG("dynamic bit clk:%u, min dsi clk:%llu, lanes:%d, bpp:%d, pck:%d Khz\n",
  7456. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, lanes, bpp,
  7457. mode->pixel_clk_khz);
  7458. return 0;
  7459. }
  7460. int dsi_display_dump_clks_state(struct dsi_display *display)
  7461. {
  7462. int rc = 0;
  7463. if (!display) {
  7464. DSI_ERR("invalid display argument\n");
  7465. return -EINVAL;
  7466. }
  7467. if (!display->clk_mngr) {
  7468. DSI_ERR("invalid clk manager\n");
  7469. return -EINVAL;
  7470. }
  7471. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  7472. DSI_ERR("invalid clk handles\n");
  7473. return -EINVAL;
  7474. }
  7475. mutex_lock(&display->display_lock);
  7476. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  7477. if (rc) {
  7478. DSI_ERR("failed to dump dsi clock state\n");
  7479. goto end;
  7480. }
  7481. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  7482. if (rc) {
  7483. DSI_ERR("failed to dump mdp clock state\n");
  7484. goto end;
  7485. }
  7486. end:
  7487. mutex_unlock(&display->display_lock);
  7488. return rc;
  7489. }
  7490. int dsi_display_unprepare(struct dsi_display *display)
  7491. {
  7492. int rc = 0;
  7493. if (!display) {
  7494. DSI_ERR("Invalid params\n");
  7495. return -EINVAL;
  7496. }
  7497. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7498. mutex_lock(&display->display_lock);
  7499. rc = dsi_display_wake_up(display);
  7500. if (rc)
  7501. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7502. display->name, rc);
  7503. if (!display->poms_pending && !is_skip_op_required(display)) {
  7504. rc = dsi_panel_unprepare(display->panel);
  7505. if (rc)
  7506. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  7507. display->name, rc);
  7508. }
  7509. rc = dsi_display_ctrl_host_disable(display);
  7510. if (rc)
  7511. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  7512. display->name, rc);
  7513. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7514. DSI_LINK_CLK, DSI_CLK_OFF);
  7515. if (rc)
  7516. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  7517. display->name, rc);
  7518. rc = dsi_display_ctrl_deinit(display);
  7519. if (rc)
  7520. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  7521. display->name, rc);
  7522. if (!display->panel->ulps_suspend_enabled) {
  7523. rc = dsi_display_phy_disable(display);
  7524. if (rc)
  7525. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  7526. display->name, rc);
  7527. }
  7528. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7529. DSI_CORE_CLK, DSI_CLK_OFF);
  7530. if (rc)
  7531. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  7532. display->name, rc);
  7533. /* destrory dsi isr set up */
  7534. dsi_display_ctrl_isr_configure(display, false);
  7535. if (!display->poms_pending && !is_skip_op_required(display)) {
  7536. rc = dsi_panel_post_unprepare(display->panel);
  7537. if (rc)
  7538. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  7539. display->name, rc);
  7540. }
  7541. display->hw_ownership = false;
  7542. mutex_unlock(&display->display_lock);
  7543. /* Free up DSI ERROR event callback */
  7544. dsi_display_unregister_error_handler(display);
  7545. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7546. return rc;
  7547. }
  7548. void __init dsi_display_register(void)
  7549. {
  7550. dsi_phy_drv_register();
  7551. dsi_ctrl_drv_register();
  7552. dsi_display_parse_boot_display_selection();
  7553. platform_driver_register(&dsi_display_driver);
  7554. }
  7555. void __exit dsi_display_unregister(void)
  7556. {
  7557. platform_driver_unregister(&dsi_display_driver);
  7558. dsi_ctrl_drv_unregister();
  7559. dsi_phy_drv_unregister();
  7560. }
  7561. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  7562. 0600);
  7563. MODULE_PARM_DESC(dsi_display0,
  7564. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  7565. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  7566. 0600);
  7567. MODULE_PARM_DESC(dsi_display1,
  7568. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");