4416896a16
Handle crypto errors and timeouts better leaving room for lesser sync issues (especially during timeouts). Also, support the crypto status changes in the v5.8 CE engine. Tests: oemcrypto tests on pineapple. Change-Id: I8d381c9a2b80853260bc779afbea58ae600bccaf Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
257 lignes
7.5 KiB
C
257 lignes
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DRIVERS_CRYPTO_MSM_QCE50_H_
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#define _DRIVERS_CRYPTO_MSM_QCE50_H_
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#include "linux/msm-sps.h"
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/* MAX Data xfer block size between BAM and CE */
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#define MAX_CE_BAM_BURST_SIZE 0x40
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#define QCEBAM_BURST_SIZE MAX_CE_BAM_BURST_SIZE
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#define GET_VIRT_ADDR(x) \
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((uintptr_t)pce_dev->coh_vmem + \
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((uintptr_t)x - (uintptr_t)pce_dev->coh_pmem))
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#define GET_PHYS_ADDR(x) \
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(phys_addr_t)(((uintptr_t)pce_dev->coh_pmem + \
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((uintptr_t)x - (uintptr_t)pce_dev->coh_vmem)))
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#define CRYPTO_REG_SIZE 4
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#define NUM_OF_CRYPTO_AUTH_IV_REG 16
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#define NUM_OF_CRYPTO_CNTR_IV_REG 4
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#define NUM_OF_CRYPTO_AUTH_BYTE_COUNT_REG 4
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#define CRYPTO_TOTAL_REGISTERS_DUMPED 26
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#define CRYPTO_RESULT_DUMP_SIZE \
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ALIGN((CRYPTO_TOTAL_REGISTERS_DUMPED * CRYPTO_REG_SIZE), \
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QCEBAM_BURST_SIZE)
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/* QCE max number of descriptor in a descriptor list */
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#define QCE_MAX_NUM_DESC 128
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#define SPS_MAX_PKT_SIZE (32 * 1024 - 64)
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/* default bam ipc log level */
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#define QCE_BAM_DEFAULT_IPC_LOGLVL 2
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/* State of consumer/producer Pipe */
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enum qce_pipe_st_enum {
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QCE_PIPE_STATE_IDLE = 0,
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QCE_PIPE_STATE_IN_PROG = 1,
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QCE_PIPE_STATE_COMP = 2,
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QCE_PIPE_STATE_LAST
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};
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enum qce_xfer_type_enum {
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QCE_XFER_HASHING,
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QCE_XFER_CIPHERING,
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QCE_XFER_AEAD,
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QCE_XFER_F8,
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QCE_XFER_F9,
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QCE_XFER_TYPE_LAST
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};
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struct qce_sps_ep_conn_data {
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struct sps_pipe *pipe;
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struct sps_connect connect;
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struct sps_register_event event;
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};
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/* CE Result DUMP format*/
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struct ce_result_dump_format {
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uint32_t auth_iv[NUM_OF_CRYPTO_AUTH_IV_REG];
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uint32_t auth_byte_count[NUM_OF_CRYPTO_AUTH_BYTE_COUNT_REG];
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uint32_t encr_cntr_iv[NUM_OF_CRYPTO_CNTR_IV_REG];
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__be32 status;
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__be32 status2;
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};
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struct qce_cmdlist_info {
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unsigned long cmdlist;
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struct sps_command_element *crypto_cfg;
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struct sps_command_element *crypto_cfg_le;
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struct sps_command_element *encr_seg_cfg;
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struct sps_command_element *encr_seg_size;
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struct sps_command_element *encr_seg_start;
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struct sps_command_element *encr_key;
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struct sps_command_element *encr_xts_key;
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struct sps_command_element *encr_cntr_iv;
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struct sps_command_element *encr_ccm_cntr_iv;
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struct sps_command_element *encr_mask_0;
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struct sps_command_element *encr_mask_1;
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struct sps_command_element *encr_mask_2;
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struct sps_command_element *encr_mask_3;
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struct sps_command_element *encr_xts_du_size;
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struct sps_command_element *pattern_info;
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struct sps_command_element *block_offset;
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struct sps_command_element *auth_seg_cfg;
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struct sps_command_element *auth_seg_size;
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struct sps_command_element *auth_seg_start;
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struct sps_command_element *auth_key;
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struct sps_command_element *auth_iv;
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struct sps_command_element *auth_nonce_info;
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struct sps_command_element *auth_bytecount;
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struct sps_command_element *seg_size;
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struct sps_command_element *go_proc;
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ptrdiff_t size;
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};
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struct qce_cmdlistptr_ops {
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struct qce_cmdlist_info cipher_aes_128_cbc_ctr;
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struct qce_cmdlist_info cipher_aes_256_cbc_ctr;
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struct qce_cmdlist_info cipher_aes_128_ecb;
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struct qce_cmdlist_info cipher_aes_256_ecb;
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struct qce_cmdlist_info cipher_aes_128_xts;
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struct qce_cmdlist_info cipher_aes_256_xts;
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struct qce_cmdlist_info cipher_des_cbc;
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struct qce_cmdlist_info cipher_des_ecb;
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struct qce_cmdlist_info cipher_3des_cbc;
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struct qce_cmdlist_info cipher_3des_ecb;
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struct qce_cmdlist_info auth_sha1;
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struct qce_cmdlist_info auth_sha256;
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struct qce_cmdlist_info auth_sha1_hmac;
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struct qce_cmdlist_info auth_sha256_hmac;
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struct qce_cmdlist_info auth_aes_128_cmac;
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struct qce_cmdlist_info auth_aes_256_cmac;
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struct qce_cmdlist_info aead_hmac_sha1_cbc_aes_128;
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struct qce_cmdlist_info aead_hmac_sha1_cbc_aes_256;
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struct qce_cmdlist_info aead_hmac_sha1_cbc_des;
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struct qce_cmdlist_info aead_hmac_sha1_cbc_3des;
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struct qce_cmdlist_info aead_hmac_sha256_cbc_aes_128;
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struct qce_cmdlist_info aead_hmac_sha256_cbc_aes_256;
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struct qce_cmdlist_info aead_hmac_sha256_cbc_des;
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struct qce_cmdlist_info aead_hmac_sha256_cbc_3des;
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struct qce_cmdlist_info aead_aes_128_ccm;
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struct qce_cmdlist_info aead_aes_256_ccm;
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struct qce_cmdlist_info cipher_null;
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struct qce_cmdlist_info f8_kasumi;
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struct qce_cmdlist_info f8_snow3g;
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struct qce_cmdlist_info f9_kasumi;
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struct qce_cmdlist_info f9_snow3g;
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struct qce_cmdlist_info unlock_all_pipes;
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};
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struct qce_ce_cfg_reg_setting {
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uint32_t crypto_cfg_be;
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uint32_t crypto_cfg_le;
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uint32_t encr_cfg_aes_cbc_128;
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uint32_t encr_cfg_aes_cbc_256;
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uint32_t encr_cfg_aes_ecb_128;
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uint32_t encr_cfg_aes_ecb_256;
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uint32_t encr_cfg_aes_xts_128;
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uint32_t encr_cfg_aes_xts_256;
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uint32_t encr_cfg_aes_ctr_128;
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uint32_t encr_cfg_aes_ctr_256;
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uint32_t encr_cfg_aes_ccm_128;
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uint32_t encr_cfg_aes_ccm_256;
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uint32_t encr_cfg_des_cbc;
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uint32_t encr_cfg_des_ecb;
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uint32_t encr_cfg_3des_cbc;
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uint32_t encr_cfg_3des_ecb;
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uint32_t encr_cfg_kasumi;
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uint32_t encr_cfg_snow3g;
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uint32_t auth_cfg_cmac_128;
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uint32_t auth_cfg_cmac_256;
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uint32_t auth_cfg_sha1;
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uint32_t auth_cfg_sha256;
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uint32_t auth_cfg_hmac_sha1;
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uint32_t auth_cfg_hmac_sha256;
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uint32_t auth_cfg_aes_ccm_128;
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uint32_t auth_cfg_aes_ccm_256;
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uint32_t auth_cfg_aead_sha1_hmac;
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uint32_t auth_cfg_aead_sha256_hmac;
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uint32_t auth_cfg_kasumi;
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uint32_t auth_cfg_snow3g;
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/* iv0 - bits 127:96 - CRYPTO_CNTR_MASK_REG0*/
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uint32_t encr_cntr_mask_0;
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/* iv1 - bits 95:64 - CRYPTO_CNTR_MASK_REG1*/
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uint32_t encr_cntr_mask_1;
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/* iv2 - bits 63:32 - CRYPTO_CNTR_MASK_REG2*/
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uint32_t encr_cntr_mask_2;
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/* iv3 - bits 31:0 - CRYPTO_CNTR_MASK_REG*/
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uint32_t encr_cntr_mask_3;
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};
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struct ce_bam_info {
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uint32_t bam_irq;
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uint32_t bam_mem;
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void __iomem *bam_iobase;
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uint32_t ce_device;
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uint32_t ce_hw_instance;
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uint32_t bam_ee;
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unsigned int pipe_pair_index[QCE_OFFLOAD_OPER_LAST];
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unsigned int src_pipe_index[QCE_OFFLOAD_OPER_LAST];
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unsigned int dest_pipe_index[QCE_OFFLOAD_OPER_LAST];
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unsigned long bam_handle;
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int ce_burst_size;
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uint32_t minor_version;
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uint32_t major_version;
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struct qce_sps_ep_conn_data producer[QCE_OFFLOAD_OPER_LAST];
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struct qce_sps_ep_conn_data consumer[QCE_OFFLOAD_OPER_LAST];
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};
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/* SPS data structure with buffers, commandlists & commmand pointer lists */
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struct ce_sps_data {
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enum qce_pipe_st_enum producer_state; /* Producer pipe state */
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int consumer_status; /* consumer pipe status */
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int producer_status; /* producer pipe status */
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struct sps_transfer in_transfer;
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struct sps_transfer out_transfer;
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struct qce_cmdlistptr_ops cmdlistptr;
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uint32_t result_dump; /* reuslt dump virtual address */
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uint32_t result_dump_null;
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uint32_t result_dump_phy; /* result dump physical address (32 bits) */
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uint32_t result_dump_null_phy;
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uint32_t ignore_buffer; /* ignore buffer virtual address */
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struct ce_result_dump_format *result; /* ponter to result dump */
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struct ce_result_dump_format *result_null;
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};
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struct ce_request_info {
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atomic_t in_use;
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bool in_prog;
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enum qce_xfer_type_enum xfer_type;
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struct ce_sps_data ce_sps;
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qce_comp_func_ptr_t qce_cb; /* qce callback function pointer */
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void *user;
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void *areq;
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int assoc_nents;
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struct scatterlist *asg; /* Formatted associated data sg */
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int src_nents;
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int dst_nents;
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dma_addr_t phy_iv_in;
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unsigned char dec_iv[16];
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int dir;
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enum qce_cipher_mode_enum mode;
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dma_addr_t phy_ota_src;
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dma_addr_t phy_ota_dst;
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unsigned int ota_size;
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unsigned int req_len;
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unsigned int offload_op;
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};
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struct qce_driver_stats {
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int no_of_timeouts;
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int no_of_dummy_reqs;
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int current_mode;
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int outstanding_reqs;
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};
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#endif /* _DRIVERS_CRYPTO_MSM_QCE50_H */
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