sde_encoder_phys_wb.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  6. #include <linux/debugfs.h>
  7. #include <drm/sde_drm.h>
  8. #include "sde_encoder_phys.h"
  9. #include "sde_formats.h"
  10. #include "sde_hw_top.h"
  11. #include "sde_hw_interrupts.h"
  12. #include "sde_core_irq.h"
  13. #include "sde_wb.h"
  14. #include "sde_vbif.h"
  15. #include "sde_crtc.h"
  16. #define to_sde_encoder_phys_wb(x) \
  17. container_of(x, struct sde_encoder_phys_wb, base)
  18. #define WBID(wb_enc) \
  19. ((wb_enc && wb_enc->wb_dev) ? wb_enc->wb_dev->wb_idx - WB_0 : -1)
  20. #define TO_S15D16(_x_) ((_x_) << 7)
  21. #define SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg) \
  22. (SDE_FORMAT_IS_UBWC(fmt) ? wb_cfg->sblk->maxlinewidth : \
  23. wb_cfg->sblk->maxlinewidth_linear)
  24. static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, INTR_IDX_PP1_OVFL,
  25. INTR_IDX_PP2_OVFL, INTR_IDX_PP3_OVFL, INTR_IDX_PP4_OVFL,
  26. INTR_IDX_PP5_OVFL, SDE_NONE, SDE_NONE};
  27. /**
  28. * sde_rgb2yuv_601l - rgb to yuv color space conversion matrix
  29. *
  30. */
  31. static struct sde_csc_cfg sde_encoder_phys_wb_rgb2yuv_601l = {
  32. {
  33. TO_S15D16(0x0083), TO_S15D16(0x0102), TO_S15D16(0x0032),
  34. TO_S15D16(0x1fb5), TO_S15D16(0x1f6c), TO_S15D16(0x00e1),
  35. TO_S15D16(0x00e1), TO_S15D16(0x1f45), TO_S15D16(0x1fdc)
  36. },
  37. { 0x00, 0x00, 0x00 },
  38. { 0x0040, 0x0200, 0x0200 },
  39. { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
  40. { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
  41. };
  42. /**
  43. * sde_encoder_phys_wb_is_master - report wb always as master encoder
  44. */
  45. static bool sde_encoder_phys_wb_is_master(struct sde_encoder_phys *phys_enc)
  46. {
  47. return true;
  48. }
  49. /**
  50. * sde_encoder_phys_wb_get_intr_type - get interrupt type based on block mode
  51. * @hw_wb: Pointer to h/w writeback driver
  52. */
  53. static enum sde_intr_type sde_encoder_phys_wb_get_intr_type(
  54. struct sde_hw_wb *hw_wb)
  55. {
  56. return (hw_wb->caps->features & BIT(SDE_WB_BLOCK_MODE)) ?
  57. SDE_IRQ_TYPE_WB_ROT_COMP : SDE_IRQ_TYPE_WB_WFD_COMP;
  58. }
  59. /**
  60. * sde_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
  61. * @phys_enc: Pointer to physical encoder
  62. */
  63. static void sde_encoder_phys_wb_set_ot_limit(
  64. struct sde_encoder_phys *phys_enc)
  65. {
  66. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  67. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  68. struct sde_vbif_set_ot_params ot_params;
  69. memset(&ot_params, 0, sizeof(ot_params));
  70. ot_params.xin_id = hw_wb->caps->xin_id;
  71. ot_params.num = hw_wb->idx - WB_0;
  72. ot_params.width = wb_enc->wb_roi.w;
  73. ot_params.height = wb_enc->wb_roi.h;
  74. ot_params.is_wfd = true;
  75. ot_params.frame_rate = phys_enc->cached_mode.vrefresh;
  76. ot_params.vbif_idx = hw_wb->caps->vbif_idx;
  77. ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  78. ot_params.rd = false;
  79. sde_vbif_set_ot_limit(phys_enc->sde_kms, &ot_params);
  80. }
  81. /**
  82. * sde_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
  83. * @phys_enc: Pointer to physical encoder
  84. */
  85. static void sde_encoder_phys_wb_set_qos_remap(
  86. struct sde_encoder_phys *phys_enc)
  87. {
  88. struct sde_encoder_phys_wb *wb_enc;
  89. struct sde_hw_wb *hw_wb;
  90. struct drm_crtc *crtc;
  91. struct sde_vbif_set_qos_params qos_params;
  92. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
  93. SDE_ERROR("invalid arguments\n");
  94. return;
  95. }
  96. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  97. if (!wb_enc->crtc) {
  98. SDE_ERROR("invalid crtc");
  99. return;
  100. }
  101. crtc = wb_enc->crtc;
  102. if (!wb_enc->hw_wb || !wb_enc->hw_wb->caps) {
  103. SDE_ERROR("invalid writeback hardware\n");
  104. return;
  105. }
  106. hw_wb = wb_enc->hw_wb;
  107. memset(&qos_params, 0, sizeof(qos_params));
  108. qos_params.vbif_idx = hw_wb->caps->vbif_idx;
  109. qos_params.xin_id = hw_wb->caps->xin_id;
  110. qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  111. qos_params.num = hw_wb->idx - WB_0;
  112. qos_params.client_type = phys_enc->in_clone_mode ?
  113. VBIF_CWB_CLIENT : VBIF_NRT_CLIENT;
  114. SDE_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d clone:%d\n",
  115. qos_params.num,
  116. qos_params.vbif_idx,
  117. qos_params.xin_id, qos_params.client_type);
  118. sde_vbif_set_qos_remap(phys_enc->sde_kms, &qos_params);
  119. }
  120. /**
  121. * sde_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
  122. * @phys_enc: Pointer to physical encoder
  123. */
  124. static void sde_encoder_phys_wb_set_qos(struct sde_encoder_phys *phys_enc)
  125. {
  126. struct sde_encoder_phys_wb *wb_enc;
  127. struct sde_hw_wb *hw_wb;
  128. struct sde_hw_wb_qos_cfg qos_cfg = {0};
  129. struct sde_perf_cfg *perf;
  130. u32 fps_index = 0, lut_index, index, frame_rate, qos_count;
  131. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog) {
  132. SDE_ERROR("invalid parameter(s)\n");
  133. return;
  134. }
  135. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  136. if (!wb_enc->hw_wb) {
  137. SDE_ERROR("invalid writeback hardware\n");
  138. return;
  139. }
  140. perf = &phys_enc->sde_kms->catalog->perf;
  141. frame_rate = phys_enc->cached_mode.vrefresh;
  142. hw_wb = wb_enc->hw_wb;
  143. qos_count = perf->qos_refresh_count;
  144. while (qos_count && perf->qos_refresh_rate) {
  145. if (frame_rate >= perf->qos_refresh_rate[qos_count - 1]) {
  146. fps_index = qos_count - 1;
  147. break;
  148. }
  149. qos_count--;
  150. }
  151. qos_cfg.danger_safe_en = true;
  152. if (phys_enc->in_clone_mode)
  153. lut_index = SDE_QOS_LUT_USAGE_CWB;
  154. else
  155. lut_index = SDE_QOS_LUT_USAGE_NRT;
  156. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  157. qos_cfg.danger_lut = perf->danger_lut[index];
  158. qos_cfg.safe_lut = (u32) perf->safe_lut[index];
  159. qos_cfg.creq_lut = perf->creq_lut[index];
  160. SDE_DEBUG("wb_enc:%d hw idx:%d fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  161. DRMID(phys_enc->parent), hw_wb->idx - WB_0,
  162. frame_rate, phys_enc->in_clone_mode,
  163. qos_cfg.danger_lut, qos_cfg.safe_lut, qos_cfg.creq_lut);
  164. if (hw_wb->ops.setup_qos_lut)
  165. hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
  166. }
  167. /**
  168. * sde_encoder_phys_setup_cdm - setup chroma down block
  169. * @phys_enc: Pointer to physical encoder
  170. * @fb: Pointer to output framebuffer
  171. * @format: Output format
  172. */
  173. void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
  174. struct drm_framebuffer *fb, const struct sde_format *format,
  175. struct sde_rect *wb_roi)
  176. {
  177. struct sde_hw_cdm *hw_cdm;
  178. struct sde_hw_cdm_cfg *cdm_cfg;
  179. struct sde_hw_pingpong *hw_pp;
  180. int ret;
  181. if (!phys_enc || !format)
  182. return;
  183. cdm_cfg = &phys_enc->cdm_cfg;
  184. hw_pp = phys_enc->hw_pp;
  185. hw_cdm = phys_enc->hw_cdm;
  186. if (!hw_cdm)
  187. return;
  188. if (!SDE_FORMAT_IS_YUV(format)) {
  189. SDE_DEBUG("[cdm_disable fmt:%x]\n",
  190. format->base.pixel_format);
  191. if (hw_cdm && hw_cdm->ops.disable)
  192. hw_cdm->ops.disable(hw_cdm);
  193. return;
  194. }
  195. memset(cdm_cfg, 0, sizeof(struct sde_hw_cdm_cfg));
  196. if (!wb_roi)
  197. return;
  198. cdm_cfg->output_width = wb_roi->w;
  199. cdm_cfg->output_height = wb_roi->h;
  200. cdm_cfg->output_fmt = format;
  201. cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB;
  202. cdm_cfg->output_bit_depth = SDE_FORMAT_IS_DX(format) ?
  203. CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
  204. /* enable 10 bit logic */
  205. switch (cdm_cfg->output_fmt->chroma_sample) {
  206. case SDE_CHROMA_RGB:
  207. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  208. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  209. break;
  210. case SDE_CHROMA_H2V1:
  211. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  212. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  213. break;
  214. case SDE_CHROMA_420:
  215. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  216. cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
  217. break;
  218. case SDE_CHROMA_H1V2:
  219. default:
  220. SDE_ERROR("unsupported chroma sampling type\n");
  221. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  222. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  223. break;
  224. }
  225. SDE_DEBUG("[cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
  226. cdm_cfg->output_width,
  227. cdm_cfg->output_height,
  228. cdm_cfg->output_fmt->base.pixel_format,
  229. cdm_cfg->output_type,
  230. cdm_cfg->output_bit_depth,
  231. cdm_cfg->h_cdwn_type,
  232. cdm_cfg->v_cdwn_type);
  233. if (hw_cdm && hw_cdm->ops.setup_csc_data) {
  234. ret = hw_cdm->ops.setup_csc_data(hw_cdm,
  235. &sde_encoder_phys_wb_rgb2yuv_601l);
  236. if (ret < 0) {
  237. SDE_ERROR("failed to setup CSC %d\n", ret);
  238. return;
  239. }
  240. }
  241. if (hw_cdm && hw_cdm->ops.setup_cdwn) {
  242. ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg);
  243. if (ret < 0) {
  244. SDE_ERROR("failed to setup CDM %d\n", ret);
  245. return;
  246. }
  247. }
  248. if (hw_cdm && hw_pp && hw_cdm->ops.enable) {
  249. cdm_cfg->pp_id = hw_pp->idx;
  250. ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
  251. if (ret < 0) {
  252. SDE_ERROR("failed to enable CDM %d\n", ret);
  253. return;
  254. }
  255. }
  256. }
  257. /**
  258. * sde_encoder_phys_wb_setup_fb - setup output framebuffer
  259. * @phys_enc: Pointer to physical encoder
  260. * @fb: Pointer to output framebuffer
  261. * @wb_roi: Pointer to output region of interest
  262. */
  263. static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc,
  264. struct drm_framebuffer *fb, struct sde_rect *wb_roi)
  265. {
  266. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  267. struct sde_hw_wb *hw_wb;
  268. struct sde_hw_wb_cfg *wb_cfg;
  269. struct sde_hw_wb_cdp_cfg *cdp_cfg;
  270. const struct msm_format *format;
  271. int ret;
  272. struct msm_gem_address_space *aspace;
  273. u32 fb_mode;
  274. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog ||
  275. !phys_enc->connector) {
  276. SDE_ERROR("invalid encoder\n");
  277. return;
  278. }
  279. hw_wb = wb_enc->hw_wb;
  280. wb_cfg = &wb_enc->wb_cfg;
  281. cdp_cfg = &wb_enc->cdp_cfg;
  282. memset(wb_cfg, 0, sizeof(struct sde_hw_wb_cfg));
  283. wb_cfg->intf_mode = phys_enc->intf_mode;
  284. fb_mode = sde_connector_get_property(phys_enc->connector->state,
  285. CONNECTOR_PROP_FB_TRANSLATION_MODE);
  286. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  287. wb_cfg->is_secure = false;
  288. else if (fb_mode == SDE_DRM_FB_SEC)
  289. wb_cfg->is_secure = true;
  290. else
  291. wb_cfg->is_secure = false;
  292. aspace = (wb_cfg->is_secure) ?
  293. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] :
  294. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  295. SDE_DEBUG("[fb_secure:%d]\n", wb_cfg->is_secure);
  296. ret = msm_framebuffer_prepare(fb, aspace);
  297. if (ret) {
  298. SDE_ERROR("prep fb failed, %d\n", ret);
  299. return;
  300. }
  301. /* cache framebuffer for cleanup in writeback done */
  302. wb_enc->wb_fb = fb;
  303. wb_enc->wb_aspace = aspace;
  304. drm_framebuffer_get(fb);
  305. format = msm_framebuffer_format(fb);
  306. if (!format) {
  307. SDE_DEBUG("invalid format for fb\n");
  308. return;
  309. }
  310. wb_cfg->dest.format = sde_get_sde_format_ext(
  311. format->pixel_format,
  312. fb->modifier);
  313. if (!wb_cfg->dest.format) {
  314. /* this error should be detected during atomic_check */
  315. SDE_ERROR("failed to get format %x\n", format->pixel_format);
  316. return;
  317. }
  318. wb_cfg->roi = *wb_roi;
  319. if (hw_wb->caps->features & BIT(SDE_WB_XY_ROI_OFFSET)) {
  320. ret = sde_format_populate_layout(aspace, fb, &wb_cfg->dest);
  321. if (ret) {
  322. SDE_DEBUG("failed to populate layout %d\n", ret);
  323. return;
  324. }
  325. wb_cfg->dest.width = fb->width;
  326. wb_cfg->dest.height = fb->height;
  327. wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
  328. } else {
  329. ret = sde_format_populate_layout_with_roi(aspace, fb, wb_roi,
  330. &wb_cfg->dest);
  331. if (ret) {
  332. /* this error should be detected during atomic_check */
  333. SDE_DEBUG("failed to populate layout %d\n", ret);
  334. return;
  335. }
  336. }
  337. if ((wb_cfg->dest.format->fetch_planes == SDE_PLANE_PLANAR) &&
  338. (wb_cfg->dest.format->element[0] == C1_B_Cb))
  339. swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
  340. SDE_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  341. wb_cfg->dest.plane_addr[0],
  342. wb_cfg->dest.plane_addr[1],
  343. wb_cfg->dest.plane_addr[2],
  344. wb_cfg->dest.plane_addr[3]);
  345. SDE_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  346. wb_cfg->dest.plane_pitch[0],
  347. wb_cfg->dest.plane_pitch[1],
  348. wb_cfg->dest.plane_pitch[2],
  349. wb_cfg->dest.plane_pitch[3]);
  350. if (hw_wb->ops.setup_roi)
  351. hw_wb->ops.setup_roi(hw_wb, wb_cfg);
  352. if (hw_wb->ops.setup_outformat)
  353. hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
  354. if (hw_wb->ops.setup_cdp) {
  355. memset(cdp_cfg, 0, sizeof(struct sde_hw_wb_cdp_cfg));
  356. cdp_cfg->enable = phys_enc->sde_kms->catalog->perf.cdp_cfg
  357. [SDE_PERF_CDP_USAGE_NRT].wr_enable;
  358. cdp_cfg->ubwc_meta_enable =
  359. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format);
  360. cdp_cfg->tile_amortize_enable =
  361. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format) ||
  362. SDE_FORMAT_IS_TILE(wb_cfg->dest.format);
  363. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  364. hw_wb->ops.setup_cdp(hw_wb, cdp_cfg);
  365. }
  366. if (hw_wb->ops.setup_outaddress) {
  367. SDE_EVT32(hw_wb->idx,
  368. wb_cfg->dest.width,
  369. wb_cfg->dest.height,
  370. wb_cfg->dest.plane_addr[0],
  371. wb_cfg->dest.plane_size[0],
  372. wb_cfg->dest.plane_addr[1],
  373. wb_cfg->dest.plane_size[1],
  374. wb_cfg->dest.plane_addr[2],
  375. wb_cfg->dest.plane_size[2],
  376. wb_cfg->dest.plane_addr[3],
  377. wb_cfg->dest.plane_size[3]);
  378. hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
  379. }
  380. }
  381. static void _sde_encoder_phys_wb_setup_cwb(struct sde_encoder_phys *phys_enc,
  382. bool enable)
  383. {
  384. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  385. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  386. struct sde_hw_ctl *hw_ctl = phys_enc->hw_ctl;
  387. struct sde_crtc *crtc = to_sde_crtc(wb_enc->crtc);
  388. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  389. bool need_merge = (crtc->num_mixers > 1);
  390. int i = 0;
  391. if (!phys_enc->in_clone_mode) {
  392. SDE_DEBUG("not in CWB mode. early return\n");
  393. return;
  394. }
  395. if (!hw_pp || !hw_ctl || !hw_wb || hw_pp->idx >= PINGPONG_MAX) {
  396. SDE_ERROR("invalid hw resources - return\n");
  397. return;
  398. }
  399. hw_ctl = crtc->mixers[0].hw_ctl;
  400. if (hw_ctl && hw_ctl->ops.setup_intf_cfg_v1 &&
  401. test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  402. struct sde_hw_intf_cfg_v1 intf_cfg = { 0, };
  403. for (i = 0; i < crtc->num_mixers; i++)
  404. intf_cfg.cwb[intf_cfg.cwb_count++] =
  405. (enum sde_cwb)(hw_pp->idx + i);
  406. if (hw_pp->merge_3d && (intf_cfg.merge_3d_count <
  407. MAX_MERGE_3D_PER_CTL_V1) && need_merge)
  408. intf_cfg.merge_3d[intf_cfg.merge_3d_count++] =
  409. hw_pp->merge_3d->idx;
  410. if (hw_pp->ops.setup_3d_mode)
  411. hw_pp->ops.setup_3d_mode(hw_pp, (enable && need_merge) ?
  412. BLEND_3D_H_ROW_INT : 0);
  413. if (hw_wb->ops.bind_pingpong_blk)
  414. hw_wb->ops.bind_pingpong_blk(hw_wb, enable, hw_pp->idx);
  415. if (hw_ctl->ops.update_intf_cfg) {
  416. hw_ctl->ops.update_intf_cfg(hw_ctl, &intf_cfg, enable);
  417. SDE_DEBUG("in CWB mode on CTL_%d PP-%d merge3d:%d\n",
  418. hw_ctl->idx - CTL_0,
  419. hw_pp->idx - PINGPONG_0,
  420. hw_pp->merge_3d ?
  421. hw_pp->merge_3d->idx - MERGE_3D_0 : -1);
  422. }
  423. } else {
  424. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  425. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  426. intf_cfg->intf = SDE_NONE;
  427. intf_cfg->wb = hw_wb->idx;
  428. if (hw_ctl && hw_ctl->ops.update_wb_cfg) {
  429. hw_ctl->ops.update_wb_cfg(hw_ctl, intf_cfg, enable);
  430. SDE_DEBUG("in CWB mode adding WB for CTL_%d\n",
  431. hw_ctl->idx - CTL_0);
  432. }
  433. }
  434. }
  435. /**
  436. * sde_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
  437. * @phys_enc: Pointer to physical encoder
  438. */
  439. static void sde_encoder_phys_wb_setup_cdp(struct sde_encoder_phys *phys_enc,
  440. const struct sde_format *format)
  441. {
  442. struct sde_encoder_phys_wb *wb_enc;
  443. struct sde_hw_wb *hw_wb;
  444. struct sde_hw_cdm *hw_cdm;
  445. struct sde_hw_ctl *ctl;
  446. const int num_wb = 1;
  447. if (!phys_enc) {
  448. SDE_ERROR("invalid encoder\n");
  449. return;
  450. }
  451. if (phys_enc->in_clone_mode) {
  452. SDE_DEBUG("in CWB mode. early return\n");
  453. return;
  454. }
  455. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  456. hw_wb = wb_enc->hw_wb;
  457. hw_cdm = phys_enc->hw_cdm;
  458. ctl = phys_enc->hw_ctl;
  459. if (test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  460. (phys_enc->hw_ctl &&
  461. phys_enc->hw_ctl->ops.setup_intf_cfg_v1)) {
  462. struct sde_hw_intf_cfg_v1 *intf_cfg_v1 = &phys_enc->intf_cfg_v1;
  463. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  464. enum sde_3d_blend_mode mode_3d;
  465. memset(intf_cfg_v1, 0, sizeof(struct sde_hw_intf_cfg_v1));
  466. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  467. intf_cfg_v1->intf_count = SDE_NONE;
  468. intf_cfg_v1->wb_count = num_wb;
  469. intf_cfg_v1->wb[0] = hw_wb->idx;
  470. if (SDE_FORMAT_IS_YUV(format)) {
  471. intf_cfg_v1->cdm_count = num_wb;
  472. intf_cfg_v1->cdm[0] = hw_cdm->idx;
  473. }
  474. if (mode_3d && hw_pp && hw_pp->merge_3d &&
  475. intf_cfg_v1->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  476. intf_cfg_v1->merge_3d[intf_cfg_v1->merge_3d_count++] =
  477. hw_pp->merge_3d->idx;
  478. if (hw_pp && hw_pp->ops.setup_3d_mode)
  479. hw_pp->ops.setup_3d_mode(hw_pp, mode_3d);
  480. /* setup which pp blk will connect to this wb */
  481. if (hw_pp && hw_wb->ops.bind_pingpong_blk)
  482. hw_wb->ops.bind_pingpong_blk(hw_wb, true,
  483. hw_pp->idx);
  484. phys_enc->hw_ctl->ops.setup_intf_cfg_v1(phys_enc->hw_ctl,
  485. intf_cfg_v1);
  486. } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
  487. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  488. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  489. intf_cfg->intf = SDE_NONE;
  490. intf_cfg->wb = hw_wb->idx;
  491. intf_cfg->mode_3d =
  492. sde_encoder_helper_get_3d_blend_mode(phys_enc);
  493. phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
  494. intf_cfg);
  495. }
  496. }
  497. static void _sde_enc_phys_wb_detect_cwb(struct sde_encoder_phys *phys_enc,
  498. struct drm_crtc_state *crtc_state)
  499. {
  500. struct drm_encoder *encoder;
  501. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  502. const struct sde_wb_cfg *wb_cfg = wb_enc->hw_wb->caps;
  503. phys_enc->in_clone_mode = false;
  504. /* Check if WB has CWB support */
  505. if (!(wb_cfg->features & BIT(SDE_WB_HAS_CWB)))
  506. return;
  507. /* if any other encoder is connected to same crtc enable clone mode*/
  508. drm_for_each_encoder(encoder, crtc_state->crtc->dev) {
  509. if (encoder->crtc != crtc_state->crtc)
  510. continue;
  511. if (phys_enc->parent != encoder) {
  512. phys_enc->in_clone_mode = true;
  513. break;
  514. }
  515. }
  516. SDE_DEBUG("detect CWB - status:%d\n", phys_enc->in_clone_mode);
  517. }
  518. static int _sde_enc_phys_wb_validate_cwb(struct sde_encoder_phys *phys_enc,
  519. struct drm_crtc_state *crtc_state,
  520. struct drm_connector_state *conn_state)
  521. {
  522. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc_state);
  523. struct sde_rect wb_roi = {0,};
  524. struct sde_rect pu_roi = {0,};
  525. int data_pt;
  526. int ds_outw = 0;
  527. int ds_outh = 0;
  528. int ds_in_use = false;
  529. int i = 0;
  530. int ret = 0;
  531. if (!phys_enc->in_clone_mode) {
  532. SDE_DEBUG("not in CWB mode. early return\n");
  533. goto exit;
  534. }
  535. ret = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  536. if (ret) {
  537. SDE_ERROR("failed to get roi %d\n", ret);
  538. goto exit;
  539. }
  540. data_pt = sde_crtc_get_property(cstate, CRTC_PROP_CAPTURE_OUTPUT);
  541. /* compute cumulative ds output dimensions if in use */
  542. for (i = 0; i < cstate->num_ds; i++)
  543. if (cstate->ds_cfg[i].scl3_cfg.enable) {
  544. ds_in_use = true;
  545. ds_outw += cstate->ds_cfg[i].scl3_cfg.dst_width;
  546. ds_outh = cstate->ds_cfg[i].scl3_cfg.dst_height;
  547. }
  548. /* if ds in use check wb roi against ds output dimensions */
  549. if ((data_pt == CAPTURE_DSPP_OUT) && ds_in_use &&
  550. ((wb_roi.w != ds_outw) || (wb_roi.h != ds_outh))) {
  551. SDE_ERROR("invalid wb roi with dest scalar [%dx%d vs %dx%d]\n",
  552. wb_roi.w, wb_roi.h, ds_outw, ds_outh);
  553. ret = -EINVAL;
  554. goto exit;
  555. }
  556. /* validate conn roi against pu rect */
  557. if (cstate->user_roi_list.num_rects) {
  558. sde_kms_rect_merge_rectangles(&cstate->user_roi_list, &pu_roi);
  559. if (wb_roi.w != pu_roi.w || wb_roi.h != pu_roi.h) {
  560. SDE_ERROR("invalid wb roi with pu [%dx%d vs %dx%d]\n",
  561. wb_roi.w, wb_roi.h, pu_roi.w, pu_roi.h);
  562. ret = -EINVAL;
  563. goto exit;
  564. }
  565. }
  566. exit:
  567. return ret;
  568. }
  569. /**
  570. * sde_encoder_phys_wb_atomic_check - verify and fixup given atomic states
  571. * @phys_enc: Pointer to physical encoder
  572. * @crtc_state: Pointer to CRTC atomic state
  573. * @conn_state: Pointer to connector atomic state
  574. */
  575. static int sde_encoder_phys_wb_atomic_check(
  576. struct sde_encoder_phys *phys_enc,
  577. struct drm_crtc_state *crtc_state,
  578. struct drm_connector_state *conn_state)
  579. {
  580. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  581. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  582. const struct sde_wb_cfg *wb_cfg = hw_wb->caps;
  583. struct drm_framebuffer *fb;
  584. const struct sde_format *fmt;
  585. struct sde_rect wb_roi;
  586. const struct drm_display_mode *mode = &crtc_state->mode;
  587. int rc;
  588. SDE_DEBUG("[atomic_check:%d,\"%s\",%d,%d]\n",
  589. hw_wb->idx - WB_0, mode->name,
  590. mode->hdisplay, mode->vdisplay);
  591. if (!conn_state || !conn_state->connector) {
  592. SDE_ERROR("invalid connector state\n");
  593. return -EINVAL;
  594. } else if (conn_state->connector->status !=
  595. connector_status_connected) {
  596. SDE_ERROR("connector not connected %d\n",
  597. conn_state->connector->status);
  598. return -EINVAL;
  599. }
  600. _sde_enc_phys_wb_detect_cwb(phys_enc, crtc_state);
  601. memset(&wb_roi, 0, sizeof(struct sde_rect));
  602. rc = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  603. if (rc) {
  604. SDE_ERROR("failed to get roi %d\n", rc);
  605. return rc;
  606. }
  607. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi.x, wb_roi.y,
  608. wb_roi.w, wb_roi.h);
  609. /* bypass check if commit with no framebuffer */
  610. fb = sde_wb_connector_state_get_output_fb(conn_state);
  611. if (!fb) {
  612. SDE_DEBUG("no output framebuffer\n");
  613. return 0;
  614. }
  615. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  616. fb->width, fb->height);
  617. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  618. if (!fmt) {
  619. SDE_ERROR("unsupported output pixel format:%x\n",
  620. fb->format->format);
  621. return -EINVAL;
  622. }
  623. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  624. fb->modifier);
  625. if (SDE_FORMAT_IS_YUV(fmt) &&
  626. !(wb_cfg->features & BIT(SDE_WB_YUV_CONFIG))) {
  627. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  628. return -EINVAL;
  629. }
  630. if (SDE_FORMAT_IS_UBWC(fmt) &&
  631. !(wb_cfg->features & BIT(SDE_WB_UBWC))) {
  632. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  633. return -EINVAL;
  634. }
  635. if (SDE_FORMAT_IS_YUV(fmt) != !!phys_enc->hw_cdm)
  636. crtc_state->mode_changed = true;
  637. if (wb_roi.w && wb_roi.h) {
  638. if (wb_roi.w != mode->hdisplay) {
  639. SDE_ERROR("invalid roi w=%d, mode w=%d\n", wb_roi.w,
  640. mode->hdisplay);
  641. return -EINVAL;
  642. } else if (wb_roi.h != mode->vdisplay) {
  643. SDE_ERROR("invalid roi h=%d, mode h=%d\n", wb_roi.h,
  644. mode->vdisplay);
  645. return -EINVAL;
  646. } else if (wb_roi.x + wb_roi.w > fb->width) {
  647. SDE_ERROR("invalid roi x=%d, w=%d, fb w=%d\n",
  648. wb_roi.x, wb_roi.w, fb->width);
  649. return -EINVAL;
  650. } else if (wb_roi.y + wb_roi.h > fb->height) {
  651. SDE_ERROR("invalid roi y=%d, h=%d, fb h=%d\n",
  652. wb_roi.y, wb_roi.h, fb->height);
  653. return -EINVAL;
  654. } else if (wb_roi.w > SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg)) {
  655. SDE_ERROR("invalid roi ubwc=%d w=%d, maxlinewidth=%u\n",
  656. SDE_FORMAT_IS_UBWC(fmt), wb_roi.w,
  657. SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg));
  658. return -EINVAL;
  659. }
  660. } else {
  661. if (wb_roi.x || wb_roi.y) {
  662. SDE_ERROR("invalid roi x=%d, y=%d\n",
  663. wb_roi.x, wb_roi.y);
  664. return -EINVAL;
  665. } else if (fb->width != mode->hdisplay) {
  666. SDE_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
  667. mode->hdisplay);
  668. return -EINVAL;
  669. } else if (fb->height != mode->vdisplay) {
  670. SDE_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
  671. mode->vdisplay);
  672. return -EINVAL;
  673. } else if (fb->width > SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg)) {
  674. SDE_ERROR("invalid fb ubwc=%d w=%d, maxlinewidth=%u\n",
  675. SDE_FORMAT_IS_UBWC(fmt), fb->width,
  676. SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg));
  677. return -EINVAL;
  678. }
  679. }
  680. rc = _sde_enc_phys_wb_validate_cwb(phys_enc, crtc_state, conn_state);
  681. if (rc) {
  682. SDE_ERROR("failed in cwb validation %d\n", rc);
  683. return rc;
  684. }
  685. return rc;
  686. }
  687. static void _sde_encoder_phys_wb_update_cwb_flush(
  688. struct sde_encoder_phys *phys_enc, bool enable)
  689. {
  690. struct sde_encoder_phys_wb *wb_enc;
  691. struct sde_hw_wb *hw_wb;
  692. struct sde_hw_ctl *hw_ctl;
  693. struct sde_hw_cdm *hw_cdm;
  694. struct sde_hw_pingpong *hw_pp;
  695. struct sde_crtc *crtc;
  696. struct sde_crtc_state *crtc_state;
  697. int i = 0;
  698. int cwb_capture_mode = 0;
  699. enum sde_cwb cwb_idx = 0;
  700. enum sde_cwb src_pp_idx = 0;
  701. bool dspp_out = false;
  702. bool need_merge = false;
  703. if (!phys_enc->in_clone_mode) {
  704. SDE_DEBUG("not in CWB mode. early return\n");
  705. return;
  706. }
  707. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  708. crtc = to_sde_crtc(wb_enc->crtc);
  709. crtc_state = to_sde_crtc_state(wb_enc->crtc->state);
  710. cwb_capture_mode = sde_crtc_get_property(crtc_state,
  711. CRTC_PROP_CAPTURE_OUTPUT);
  712. hw_pp = phys_enc->hw_pp;
  713. hw_wb = wb_enc->hw_wb;
  714. hw_cdm = phys_enc->hw_cdm;
  715. /* In CWB mode, program actual source master sde_hw_ctl from crtc */
  716. hw_ctl = crtc->mixers[0].hw_ctl;
  717. if (!hw_ctl || !hw_wb || !hw_pp) {
  718. SDE_ERROR("[wb] HW resource not available for CWB\n");
  719. return;
  720. }
  721. /* treating LM idx of primary display ctl path as source ping-pong idx*/
  722. src_pp_idx = (enum sde_cwb)crtc->mixers[0].hw_lm->idx;
  723. cwb_idx = (enum sde_cwb)hw_pp->idx;
  724. dspp_out = (cwb_capture_mode == CAPTURE_DSPP_OUT);
  725. need_merge = (crtc->num_mixers > 1) ? true : false;
  726. if (src_pp_idx > CWB_0 || ((cwb_idx + crtc->num_mixers) > CWB_MAX)) {
  727. SDE_ERROR("invalid hw config for CWB\n");
  728. return;
  729. }
  730. if (hw_ctl->ops.update_bitmask)
  731. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_WB,
  732. hw_wb->idx, 1);
  733. if (hw_ctl->ops.update_bitmask && hw_cdm)
  734. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_CDM,
  735. hw_cdm->idx, 1);
  736. if (test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  737. for (i = 0; i < crtc->num_mixers; i++) {
  738. cwb_idx = (enum sde_cwb) (hw_pp->idx + i);
  739. src_pp_idx = (enum sde_cwb) (src_pp_idx + i);
  740. if (hw_wb->ops.program_cwb_ctrl)
  741. hw_wb->ops.program_cwb_ctrl(hw_wb, cwb_idx,
  742. src_pp_idx, dspp_out, enable);
  743. if (hw_ctl->ops.update_bitmask)
  744. hw_ctl->ops.update_bitmask(hw_ctl,
  745. SDE_HW_FLUSH_CWB, cwb_idx, 1);
  746. }
  747. if (need_merge && hw_ctl->ops.update_bitmask
  748. && hw_pp && hw_pp->merge_3d)
  749. hw_ctl->ops.update_bitmask(hw_ctl,
  750. SDE_HW_FLUSH_MERGE_3D,
  751. hw_pp->merge_3d->idx, 1);
  752. } else {
  753. phys_enc->hw_mdptop->ops.set_cwb_ppb_cntl(phys_enc->hw_mdptop,
  754. need_merge, dspp_out);
  755. }
  756. }
  757. /**
  758. * _sde_encoder_phys_wb_update_flush - flush hardware update
  759. * @phys_enc: Pointer to physical encoder
  760. */
  761. static void _sde_encoder_phys_wb_update_flush(struct sde_encoder_phys *phys_enc)
  762. {
  763. struct sde_encoder_phys_wb *wb_enc;
  764. struct sde_hw_wb *hw_wb;
  765. struct sde_hw_ctl *hw_ctl;
  766. struct sde_hw_cdm *hw_cdm;
  767. struct sde_hw_pingpong *hw_pp;
  768. struct sde_ctl_flush_cfg pending_flush = {0,};
  769. if (!phys_enc)
  770. return;
  771. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  772. hw_wb = wb_enc->hw_wb;
  773. hw_cdm = phys_enc->hw_cdm;
  774. hw_pp = phys_enc->hw_pp;
  775. hw_ctl = phys_enc->hw_ctl;
  776. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  777. if (phys_enc->in_clone_mode) {
  778. SDE_DEBUG("in CWB mode. early return\n");
  779. return;
  780. }
  781. if (!hw_ctl) {
  782. SDE_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
  783. return;
  784. }
  785. if (hw_ctl->ops.update_bitmask)
  786. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_WB,
  787. hw_wb->idx, 1);
  788. if (hw_ctl->ops.update_bitmask && hw_cdm)
  789. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_CDM,
  790. hw_cdm->idx, 1);
  791. if (hw_ctl->ops.update_bitmask && hw_pp && hw_pp->merge_3d)
  792. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  793. hw_pp->merge_3d->idx, 1);
  794. if (hw_ctl->ops.get_pending_flush)
  795. hw_ctl->ops.get_pending_flush(hw_ctl,
  796. &pending_flush);
  797. SDE_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
  798. hw_ctl->idx - CTL_0, pending_flush.pending_flush_mask,
  799. hw_wb->idx - WB_0);
  800. }
  801. /**
  802. * sde_encoder_phys_wb_setup - setup writeback encoder
  803. * @phys_enc: Pointer to physical encoder
  804. */
  805. static void sde_encoder_phys_wb_setup(
  806. struct sde_encoder_phys *phys_enc)
  807. {
  808. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  809. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  810. struct drm_display_mode mode = phys_enc->cached_mode;
  811. struct drm_framebuffer *fb;
  812. struct sde_rect *wb_roi = &wb_enc->wb_roi;
  813. SDE_DEBUG("[mode_set:%d,\"%s\",%d,%d]\n",
  814. hw_wb->idx - WB_0, mode.name,
  815. mode.hdisplay, mode.vdisplay);
  816. memset(wb_roi, 0, sizeof(struct sde_rect));
  817. /* clear writeback framebuffer - will be updated in setup_fb */
  818. wb_enc->wb_fb = NULL;
  819. wb_enc->wb_aspace = NULL;
  820. if (phys_enc->enable_state == SDE_ENC_DISABLING) {
  821. fb = wb_enc->fb_disable;
  822. wb_roi->w = 0;
  823. wb_roi->h = 0;
  824. } else {
  825. fb = sde_wb_get_output_fb(wb_enc->wb_dev);
  826. sde_wb_get_output_roi(wb_enc->wb_dev, wb_roi);
  827. }
  828. if (!fb) {
  829. SDE_DEBUG("no output framebuffer\n");
  830. return;
  831. }
  832. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  833. fb->width, fb->height);
  834. if (wb_roi->w == 0 || wb_roi->h == 0) {
  835. wb_roi->x = 0;
  836. wb_roi->y = 0;
  837. wb_roi->w = fb->width;
  838. wb_roi->h = fb->height;
  839. }
  840. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi->x, wb_roi->y,
  841. wb_roi->w, wb_roi->h);
  842. wb_enc->wb_fmt = sde_get_sde_format_ext(fb->format->format,
  843. fb->modifier);
  844. if (!wb_enc->wb_fmt) {
  845. SDE_ERROR("unsupported output pixel format: %d\n",
  846. fb->format->format);
  847. return;
  848. }
  849. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  850. fb->modifier);
  851. sde_encoder_phys_wb_set_ot_limit(phys_enc);
  852. sde_encoder_phys_wb_set_qos_remap(phys_enc);
  853. sde_encoder_phys_wb_set_qos(phys_enc);
  854. sde_encoder_phys_setup_cdm(phys_enc, fb, wb_enc->wb_fmt, wb_roi);
  855. sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi);
  856. sde_encoder_phys_wb_setup_cdp(phys_enc, wb_enc->wb_fmt);
  857. _sde_encoder_phys_wb_setup_cwb(phys_enc, true);
  858. }
  859. static void _sde_encoder_phys_wb_frame_done_helper(void *arg, bool frame_error)
  860. {
  861. struct sde_encoder_phys_wb *wb_enc = arg;
  862. struct sde_encoder_phys *phys_enc = &wb_enc->base;
  863. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  864. u32 event = frame_error ? SDE_ENCODER_FRAME_EVENT_ERROR : 0;
  865. SDE_DEBUG("[wb:%d,%u]\n", hw_wb->idx - WB_0, wb_enc->frame_count);
  866. /* don't notify upper layer for internal commit */
  867. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  868. goto complete;
  869. if (phys_enc->parent_ops.handle_frame_done &&
  870. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0)) {
  871. event |= SDE_ENCODER_FRAME_EVENT_DONE |
  872. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
  873. if (phys_enc->in_clone_mode)
  874. event |= SDE_ENCODER_FRAME_EVENT_CWB_DONE;
  875. else
  876. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  877. phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
  878. phys_enc, event);
  879. }
  880. if (!phys_enc->in_clone_mode && phys_enc->parent_ops.handle_vblank_virt)
  881. phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
  882. phys_enc);
  883. SDE_EVT32_IRQ(DRMID(phys_enc->parent), hw_wb->idx - WB_0, event,
  884. frame_error);
  885. complete:
  886. wake_up_all(&phys_enc->pending_kickoff_wq);
  887. }
  888. /**
  889. * sde_encoder_phys_wb_done_irq - Pingpong overflow interrupt handler for CWB
  890. * @arg: Pointer to writeback encoder
  891. * @irq_idx: interrupt index
  892. */
  893. static void sde_encoder_phys_cwb_ovflow(void *arg, int irq_idx)
  894. {
  895. _sde_encoder_phys_wb_frame_done_helper(arg, true);
  896. }
  897. /**
  898. * sde_encoder_phys_wb_done_irq - writeback interrupt handler
  899. * @arg: Pointer to writeback encoder
  900. * @irq_idx: interrupt index
  901. */
  902. static void sde_encoder_phys_wb_done_irq(void *arg, int irq_idx)
  903. {
  904. _sde_encoder_phys_wb_frame_done_helper(arg, false);
  905. }
  906. /**
  907. * sde_encoder_phys_wb_irq_ctrl - irq control of WB
  908. * @phys: Pointer to physical encoder
  909. * @enable: indicates enable or disable interrupts
  910. */
  911. static void sde_encoder_phys_wb_irq_ctrl(
  912. struct sde_encoder_phys *phys, bool enable)
  913. {
  914. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys);
  915. int index = 0, refcount;
  916. int ret = 0, pp = 0;
  917. if (!wb_enc)
  918. return;
  919. if (wb_enc->bypass_irqreg)
  920. return;
  921. pp = phys->hw_pp->idx - PINGPONG_0;
  922. if ((pp + CRTC_DUAL_MIXERS_ONLY) >= PINGPONG_MAX) {
  923. SDE_ERROR("invalid pingpong index for WB or CWB\n");
  924. return;
  925. }
  926. refcount = atomic_read(&phys->wbirq_refcount);
  927. if (enable && atomic_inc_return(&phys->wbirq_refcount) == 1) {
  928. sde_encoder_helper_register_irq(phys, INTR_IDX_WB_DONE);
  929. if (ret)
  930. atomic_dec_return(&phys->wbirq_refcount);
  931. for (index = 0; index < CRTC_DUAL_MIXERS_ONLY; index++)
  932. if (cwb_irq_tbl[index + pp] != SDE_NONE)
  933. sde_encoder_helper_register_irq(phys,
  934. cwb_irq_tbl[index + pp]);
  935. } else if (!enable &&
  936. atomic_dec_return(&phys->wbirq_refcount) == 0) {
  937. sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_DONE);
  938. if (ret)
  939. atomic_inc_return(&phys->wbirq_refcount);
  940. for (index = 0; index < CRTC_DUAL_MIXERS_ONLY; index++)
  941. if (cwb_irq_tbl[index + pp] != SDE_NONE)
  942. sde_encoder_helper_unregister_irq(phys,
  943. cwb_irq_tbl[index + pp]);
  944. }
  945. }
  946. /**
  947. * sde_encoder_phys_wb_mode_set - set display mode
  948. * @phys_enc: Pointer to physical encoder
  949. * @mode: Pointer to requested display mode
  950. * @adj_mode: Pointer to adjusted display mode
  951. */
  952. static void sde_encoder_phys_wb_mode_set(
  953. struct sde_encoder_phys *phys_enc,
  954. struct drm_display_mode *mode,
  955. struct drm_display_mode *adj_mode)
  956. {
  957. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  958. struct sde_rm *rm = &phys_enc->sde_kms->rm;
  959. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  960. struct sde_rm_hw_iter iter;
  961. int i, instance;
  962. phys_enc->cached_mode = *adj_mode;
  963. instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  964. SDE_DEBUG("[mode_set_cache:%d,\"%s\",%d,%d]\n",
  965. hw_wb->idx - WB_0, mode->name,
  966. mode->hdisplay, mode->vdisplay);
  967. phys_enc->hw_ctl = NULL;
  968. phys_enc->hw_cdm = NULL;
  969. /* Retrieve previously allocated HW Resources. CTL shouldn't fail */
  970. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  971. for (i = 0; i <= instance; i++) {
  972. sde_rm_get_hw(rm, &iter);
  973. if (i == instance)
  974. phys_enc->hw_ctl = (struct sde_hw_ctl *) iter.hw;
  975. }
  976. if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  977. SDE_ERROR("failed init ctl: %ld\n",
  978. (!phys_enc->hw_ctl) ?
  979. -EINVAL : PTR_ERR(phys_enc->hw_ctl));
  980. phys_enc->hw_ctl = NULL;
  981. return;
  982. }
  983. /* CDM is optional */
  984. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CDM);
  985. for (i = 0; i <= instance; i++) {
  986. sde_rm_get_hw(rm, &iter);
  987. if (i == instance)
  988. phys_enc->hw_cdm = (struct sde_hw_cdm *) iter.hw;
  989. }
  990. if (IS_ERR(phys_enc->hw_cdm)) {
  991. SDE_ERROR("CDM required but not allocated: %ld\n",
  992. PTR_ERR(phys_enc->hw_cdm));
  993. phys_enc->hw_cdm = NULL;
  994. }
  995. }
  996. static int sde_encoder_phys_wb_frame_timeout(struct sde_encoder_phys *phys_enc)
  997. {
  998. u32 event = 0;
  999. while (atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0) &&
  1000. phys_enc->parent_ops.handle_frame_done) {
  1001. event = SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE
  1002. | SDE_ENCODER_FRAME_EVENT_ERROR;
  1003. if (phys_enc->in_clone_mode)
  1004. event |= SDE_ENCODER_FRAME_EVENT_CWB_DONE;
  1005. else
  1006. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  1007. phys_enc->parent_ops.handle_frame_done(
  1008. phys_enc->parent, phys_enc, event);
  1009. SDE_EVT32(DRMID(phys_enc->parent), event,
  1010. atomic_read(&phys_enc->pending_retire_fence_cnt));
  1011. }
  1012. return event;
  1013. }
  1014. static int _sde_encoder_phys_wb_wait_for_commit_done(
  1015. struct sde_encoder_phys *phys_enc, bool is_disable)
  1016. {
  1017. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1018. u32 event = 0;
  1019. u64 wb_time = 0;
  1020. int rc = 0;
  1021. struct sde_encoder_wait_info wait_info = {0};
  1022. /* Return EWOULDBLOCK since we know the wait isn't necessary */
  1023. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1024. SDE_ERROR("encoder already disabled\n");
  1025. return -EWOULDBLOCK;
  1026. }
  1027. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1028. wb_enc->kickoff_count, !!wb_enc->wb_fb, is_disable,
  1029. phys_enc->in_clone_mode);
  1030. if (!is_disable && phys_enc->in_clone_mode &&
  1031. (atomic_read(&phys_enc->pending_retire_fence_cnt) <= 1))
  1032. goto skip_wait;
  1033. /* signal completion if commit with no framebuffer */
  1034. if (!wb_enc->wb_fb) {
  1035. SDE_DEBUG("no output framebuffer\n");
  1036. _sde_encoder_phys_wb_frame_done_helper(wb_enc, false);
  1037. }
  1038. wait_info.wq = &phys_enc->pending_kickoff_wq;
  1039. wait_info.atomic_cnt = &phys_enc->pending_retire_fence_cnt;
  1040. wait_info.timeout_ms = max_t(u32, wb_enc->wbdone_timeout,
  1041. KICKOFF_TIMEOUT_MS);
  1042. rc = sde_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_WB_DONE,
  1043. &wait_info);
  1044. if (rc == -ETIMEDOUT) {
  1045. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1046. wb_enc->frame_count, SDE_EVTLOG_ERROR);
  1047. SDE_ERROR("wb:%d kickoff timed out\n", WBID(wb_enc));
  1048. event = sde_encoder_phys_wb_frame_timeout(phys_enc);
  1049. }
  1050. /* cleanup writeback framebuffer */
  1051. if (wb_enc->wb_fb && wb_enc->wb_aspace) {
  1052. msm_framebuffer_cleanup(wb_enc->wb_fb, wb_enc->wb_aspace);
  1053. drm_framebuffer_put(wb_enc->wb_fb);
  1054. wb_enc->wb_fb = NULL;
  1055. wb_enc->wb_aspace = NULL;
  1056. }
  1057. skip_wait:
  1058. /* remove vote for iommu/clk/bus */
  1059. wb_enc->frame_count++;
  1060. if (!rc) {
  1061. wb_enc->end_time = ktime_get();
  1062. wb_time = (u64)ktime_to_us(wb_enc->end_time) -
  1063. (u64)ktime_to_us(wb_enc->start_time);
  1064. SDE_DEBUG("wb:%d took %llu us\n", WBID(wb_enc), wb_time);
  1065. }
  1066. /* cleanup previous buffer if pending */
  1067. if (wb_enc->cwb_old_fb && wb_enc->cwb_old_aspace) {
  1068. msm_framebuffer_cleanup(wb_enc->cwb_old_fb, wb_enc->cwb_old_aspace);
  1069. drm_framebuffer_put(wb_enc->cwb_old_fb);
  1070. wb_enc->cwb_old_fb = NULL;
  1071. wb_enc->cwb_old_aspace = NULL;
  1072. }
  1073. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1074. wb_time, event, rc);
  1075. return rc;
  1076. }
  1077. /**
  1078. * sde_encoder_phys_wb_wait_for_commit_done - wait until request is committed
  1079. * @phys_enc: Pointer to physical encoder
  1080. */
  1081. static int sde_encoder_phys_wb_wait_for_commit_done(
  1082. struct sde_encoder_phys *phys_enc)
  1083. {
  1084. return _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, false);
  1085. }
  1086. /**
  1087. * sde_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
  1088. * @phys_enc: Pointer to physical encoder
  1089. * @params: kickoff parameters
  1090. * Returns: Zero on success
  1091. */
  1092. static int sde_encoder_phys_wb_prepare_for_kickoff(
  1093. struct sde_encoder_phys *phys_enc,
  1094. struct sde_encoder_kickoff_params *params)
  1095. {
  1096. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1097. SDE_DEBUG("[wb:%d,%u]\n", wb_enc->hw_wb->idx - WB_0,
  1098. wb_enc->kickoff_count);
  1099. if (phys_enc->in_clone_mode) {
  1100. wb_enc->cwb_old_fb = wb_enc->wb_fb;
  1101. wb_enc->cwb_old_aspace = wb_enc->wb_aspace;
  1102. }
  1103. wb_enc->kickoff_count++;
  1104. /* set OT limit & enable traffic shaper */
  1105. sde_encoder_phys_wb_setup(phys_enc);
  1106. _sde_encoder_phys_wb_update_flush(phys_enc);
  1107. _sde_encoder_phys_wb_update_cwb_flush(phys_enc, true);
  1108. /* vote for iommu/clk/bus */
  1109. wb_enc->start_time = ktime_get();
  1110. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1111. wb_enc->kickoff_count, wb_enc->frame_count,
  1112. phys_enc->in_clone_mode);
  1113. return 0;
  1114. }
  1115. /**
  1116. * sde_encoder_phys_wb_trigger_flush - trigger flush processing
  1117. * @phys_enc: Pointer to physical encoder
  1118. */
  1119. static void sde_encoder_phys_wb_trigger_flush(struct sde_encoder_phys *phys_enc)
  1120. {
  1121. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1122. if (!phys_enc || !wb_enc->hw_wb) {
  1123. SDE_ERROR("invalid encoder\n");
  1124. return;
  1125. }
  1126. /*
  1127. * Bail out iff in CWB mode. In case of CWB, primary control-path
  1128. * which is actually driving would trigger the flush
  1129. */
  1130. if (phys_enc->in_clone_mode) {
  1131. SDE_DEBUG("in CWB mode. early return\n");
  1132. return;
  1133. }
  1134. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1135. /* clear pending flush if commit with no framebuffer */
  1136. if (!wb_enc->wb_fb) {
  1137. SDE_DEBUG("no output framebuffer\n");
  1138. return;
  1139. }
  1140. sde_encoder_helper_trigger_flush(phys_enc);
  1141. }
  1142. /**
  1143. * sde_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
  1144. * @phys_enc: Pointer to physical encoder
  1145. */
  1146. static void sde_encoder_phys_wb_handle_post_kickoff(
  1147. struct sde_encoder_phys *phys_enc)
  1148. {
  1149. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1150. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1151. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc));
  1152. }
  1153. /**
  1154. * _sde_encoder_phys_wb_init_internal_fb - create fb for internal commit
  1155. * @wb_enc: Pointer to writeback encoder
  1156. * @pixel_format: DRM pixel format
  1157. * @width: Desired fb width
  1158. * @height: Desired fb height
  1159. * @pitch: Desired fb pitch
  1160. */
  1161. static int _sde_encoder_phys_wb_init_internal_fb(
  1162. struct sde_encoder_phys_wb *wb_enc,
  1163. uint32_t pixel_format, uint32_t width,
  1164. uint32_t height, uint32_t pitch)
  1165. {
  1166. struct drm_device *dev;
  1167. struct drm_framebuffer *fb;
  1168. struct drm_mode_fb_cmd2 mode_cmd;
  1169. uint32_t size;
  1170. int nplanes, i, ret;
  1171. struct msm_gem_address_space *aspace;
  1172. const struct drm_format_info *info;
  1173. if (!wb_enc || !wb_enc->base.parent || !wb_enc->base.sde_kms) {
  1174. SDE_ERROR("invalid params\n");
  1175. return -EINVAL;
  1176. }
  1177. aspace = wb_enc->base.sde_kms->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  1178. if (!aspace) {
  1179. SDE_ERROR("invalid address space\n");
  1180. return -EINVAL;
  1181. }
  1182. dev = wb_enc->base.sde_kms->dev;
  1183. if (!dev) {
  1184. SDE_ERROR("invalid dev\n");
  1185. return -EINVAL;
  1186. }
  1187. memset(&mode_cmd, 0, sizeof(mode_cmd));
  1188. mode_cmd.pixel_format = pixel_format;
  1189. mode_cmd.width = width;
  1190. mode_cmd.height = height;
  1191. mode_cmd.pitches[0] = pitch;
  1192. size = sde_format_get_framebuffer_size(pixel_format,
  1193. mode_cmd.width, mode_cmd.height,
  1194. mode_cmd.pitches, 0);
  1195. if (!size) {
  1196. SDE_DEBUG("not creating zero size buffer\n");
  1197. return -EINVAL;
  1198. }
  1199. /* allocate gem tracking object */
  1200. info = drm_get_format_info(dev, &mode_cmd);
  1201. nplanes = info->num_planes;
  1202. if (nplanes >= SDE_MAX_PLANES) {
  1203. SDE_ERROR("requested format has too many planes\n");
  1204. return -EINVAL;
  1205. }
  1206. wb_enc->bo_disable[0] = msm_gem_new(dev, size,
  1207. MSM_BO_SCANOUT | MSM_BO_WC);
  1208. if (IS_ERR_OR_NULL(wb_enc->bo_disable[0])) {
  1209. ret = PTR_ERR(wb_enc->bo_disable[0]);
  1210. wb_enc->bo_disable[0] = NULL;
  1211. SDE_ERROR("failed to create bo, %d\n", ret);
  1212. return ret;
  1213. }
  1214. for (i = 0; i < nplanes; ++i) {
  1215. wb_enc->bo_disable[i] = wb_enc->bo_disable[0];
  1216. mode_cmd.pitches[i] = width * info->cpp[i];
  1217. }
  1218. fb = msm_framebuffer_init(dev, &mode_cmd, wb_enc->bo_disable);
  1219. if (IS_ERR_OR_NULL(fb)) {
  1220. ret = PTR_ERR(fb);
  1221. drm_gem_object_put(wb_enc->bo_disable[0]);
  1222. wb_enc->bo_disable[0] = NULL;
  1223. SDE_ERROR("failed to init fb, %d\n", ret);
  1224. return ret;
  1225. }
  1226. /* prepare the backing buffer now so that it's available later */
  1227. ret = msm_framebuffer_prepare(fb, aspace);
  1228. if (!ret)
  1229. wb_enc->fb_disable = fb;
  1230. return ret;
  1231. }
  1232. /**
  1233. * _sde_encoder_phys_wb_destroy_internal_fb - deconstruct internal fb
  1234. * @wb_enc: Pointer to writeback encoder
  1235. */
  1236. static void _sde_encoder_phys_wb_destroy_internal_fb(
  1237. struct sde_encoder_phys_wb *wb_enc)
  1238. {
  1239. if (!wb_enc)
  1240. return;
  1241. if (wb_enc->fb_disable) {
  1242. drm_framebuffer_unregister_private(wb_enc->fb_disable);
  1243. drm_framebuffer_remove(wb_enc->fb_disable);
  1244. wb_enc->fb_disable = NULL;
  1245. }
  1246. if (wb_enc->bo_disable[0]) {
  1247. drm_gem_object_put(wb_enc->bo_disable[0]);
  1248. wb_enc->bo_disable[0] = NULL;
  1249. }
  1250. }
  1251. /**
  1252. * sde_encoder_phys_wb_enable - enable writeback encoder
  1253. * @phys_enc: Pointer to physical encoder
  1254. */
  1255. static void sde_encoder_phys_wb_enable(struct sde_encoder_phys *phys_enc)
  1256. {
  1257. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1258. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1259. struct drm_device *dev;
  1260. struct drm_connector *connector;
  1261. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1262. if (!wb_enc->base.parent || !wb_enc->base.parent->dev) {
  1263. SDE_ERROR("invalid drm device\n");
  1264. return;
  1265. }
  1266. dev = wb_enc->base.parent->dev;
  1267. /* find associated writeback connector */
  1268. connector = phys_enc->connector;
  1269. if (!connector || connector->encoder != phys_enc->parent) {
  1270. SDE_ERROR("failed to find writeback connector\n");
  1271. return;
  1272. }
  1273. wb_enc->wb_dev = sde_wb_connector_get_wb(connector);
  1274. phys_enc->enable_state = SDE_ENC_ENABLED;
  1275. /*
  1276. * cache the crtc in wb_enc on enable for duration of use case
  1277. * for correctly servicing asynchronous irq events and timers
  1278. */
  1279. wb_enc->crtc = phys_enc->parent->crtc;
  1280. }
  1281. /**
  1282. * sde_encoder_phys_wb_disable - disable writeback encoder
  1283. * @phys_enc: Pointer to physical encoder
  1284. */
  1285. static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
  1286. {
  1287. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1288. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1289. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1290. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1291. SDE_ERROR("encoder is already disabled\n");
  1292. return;
  1293. }
  1294. SDE_DEBUG("[wait_for_done: wb:%d, frame:%u, kickoff:%u]\n",
  1295. hw_wb->idx - WB_0, wb_enc->frame_count,
  1296. wb_enc->kickoff_count);
  1297. _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1298. if (!phys_enc->hw_ctl || !phys_enc->parent ||
  1299. !phys_enc->sde_kms || !wb_enc->fb_disable) {
  1300. SDE_DEBUG("invalid enc, skipping extra commit\n");
  1301. goto exit;
  1302. }
  1303. /* avoid reset frame for CWB */
  1304. if (phys_enc->in_clone_mode) {
  1305. _sde_encoder_phys_wb_setup_cwb(phys_enc, false);
  1306. _sde_encoder_phys_wb_update_cwb_flush(phys_enc, false);
  1307. phys_enc->in_clone_mode = false;
  1308. goto exit;
  1309. }
  1310. /* reset h/w before final flush */
  1311. if (phys_enc->hw_ctl->ops.clear_pending_flush)
  1312. phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
  1313. /*
  1314. * New CTL reset sequence from 5.0 MDP onwards.
  1315. * If has_3d_merge_reset is not set, legacy reset
  1316. * sequence is executed.
  1317. */
  1318. if (hw_wb->catalog->has_3d_merge_reset) {
  1319. sde_encoder_helper_phys_disable(phys_enc, wb_enc);
  1320. goto exit;
  1321. }
  1322. if (sde_encoder_helper_reset_mixers(phys_enc, NULL))
  1323. goto exit;
  1324. phys_enc->enable_state = SDE_ENC_DISABLING;
  1325. sde_encoder_phys_wb_prepare_for_kickoff(phys_enc, NULL);
  1326. sde_encoder_phys_wb_irq_ctrl(phys_enc, true);
  1327. if (phys_enc->hw_ctl->ops.trigger_flush)
  1328. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  1329. sde_encoder_helper_trigger_start(phys_enc);
  1330. _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1331. sde_encoder_phys_wb_irq_ctrl(phys_enc, false);
  1332. exit:
  1333. /*
  1334. * frame count and kickoff count are only used for debug purpose. Frame
  1335. * count can be more than kickoff count at the end of disable call due
  1336. * to extra frame_done wait. It does not cause any issue because
  1337. * frame_done wait is based on retire_fence count. Leaving these
  1338. * counters for debugging purpose.
  1339. */
  1340. if (wb_enc->frame_count != wb_enc->kickoff_count) {
  1341. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1342. wb_enc->kickoff_count, wb_enc->frame_count,
  1343. phys_enc->in_clone_mode);
  1344. wb_enc->frame_count = wb_enc->kickoff_count;
  1345. }
  1346. phys_enc->enable_state = SDE_ENC_DISABLED;
  1347. wb_enc->crtc = NULL;
  1348. phys_enc->hw_cdm = NULL;
  1349. phys_enc->hw_ctl = NULL;
  1350. }
  1351. /**
  1352. * sde_encoder_phys_wb_get_hw_resources - get hardware resources
  1353. * @phys_enc: Pointer to physical encoder
  1354. * @hw_res: Pointer to encoder resources
  1355. */
  1356. static void sde_encoder_phys_wb_get_hw_resources(
  1357. struct sde_encoder_phys *phys_enc,
  1358. struct sde_encoder_hw_resources *hw_res,
  1359. struct drm_connector_state *conn_state)
  1360. {
  1361. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1362. struct sde_hw_wb *hw_wb;
  1363. struct drm_framebuffer *fb;
  1364. const struct sde_format *fmt = NULL;
  1365. if (!phys_enc) {
  1366. SDE_ERROR("invalid encoder\n");
  1367. return;
  1368. }
  1369. fb = sde_wb_connector_state_get_output_fb(conn_state);
  1370. if (fb) {
  1371. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  1372. if (!fmt) {
  1373. SDE_ERROR("unsupported output pixel format:%d\n",
  1374. fb->format->format);
  1375. return;
  1376. }
  1377. }
  1378. hw_wb = wb_enc->hw_wb;
  1379. hw_res->wbs[hw_wb->idx - WB_0] = phys_enc->intf_mode;
  1380. hw_res->needs_cdm = fmt ? SDE_FORMAT_IS_YUV(fmt) : false;
  1381. SDE_DEBUG("[wb:%d] intf_mode=%d needs_cdm=%d\n", hw_wb->idx - WB_0,
  1382. hw_res->wbs[hw_wb->idx - WB_0],
  1383. hw_res->needs_cdm);
  1384. }
  1385. #ifdef CONFIG_DEBUG_FS
  1386. /**
  1387. * sde_encoder_phys_wb_init_debugfs - initialize writeback encoder debugfs
  1388. * @phys_enc: Pointer to physical encoder
  1389. * @debugfs_root: Pointer to virtual encoder's debugfs_root dir
  1390. */
  1391. static int sde_encoder_phys_wb_init_debugfs(
  1392. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1393. {
  1394. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1395. if (!phys_enc || !wb_enc->hw_wb || !debugfs_root)
  1396. return -EINVAL;
  1397. if (!debugfs_create_u32("wbdone_timeout", 0600,
  1398. debugfs_root, &wb_enc->wbdone_timeout)) {
  1399. SDE_ERROR("failed to create debugfs/wbdone_timeout\n");
  1400. return -ENOMEM;
  1401. }
  1402. return 0;
  1403. }
  1404. #else
  1405. static int sde_encoder_phys_wb_init_debugfs(
  1406. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1407. {
  1408. return 0;
  1409. }
  1410. #endif
  1411. static int sde_encoder_phys_wb_late_register(struct sde_encoder_phys *phys_enc,
  1412. struct dentry *debugfs_root)
  1413. {
  1414. return sde_encoder_phys_wb_init_debugfs(phys_enc, debugfs_root);
  1415. }
  1416. /**
  1417. * sde_encoder_phys_wb_destroy - destroy writeback encoder
  1418. * @phys_enc: Pointer to physical encoder
  1419. */
  1420. static void sde_encoder_phys_wb_destroy(struct sde_encoder_phys *phys_enc)
  1421. {
  1422. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1423. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1424. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1425. if (!phys_enc)
  1426. return;
  1427. _sde_encoder_phys_wb_destroy_internal_fb(wb_enc);
  1428. kfree(wb_enc);
  1429. }
  1430. /**
  1431. * sde_encoder_phys_wb_init_ops - initialize writeback operations
  1432. * @ops: Pointer to encoder operation table
  1433. */
  1434. static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops)
  1435. {
  1436. ops->late_register = sde_encoder_phys_wb_late_register;
  1437. ops->is_master = sde_encoder_phys_wb_is_master;
  1438. ops->mode_set = sde_encoder_phys_wb_mode_set;
  1439. ops->enable = sde_encoder_phys_wb_enable;
  1440. ops->disable = sde_encoder_phys_wb_disable;
  1441. ops->destroy = sde_encoder_phys_wb_destroy;
  1442. ops->atomic_check = sde_encoder_phys_wb_atomic_check;
  1443. ops->get_hw_resources = sde_encoder_phys_wb_get_hw_resources;
  1444. ops->wait_for_commit_done = sde_encoder_phys_wb_wait_for_commit_done;
  1445. ops->prepare_for_kickoff = sde_encoder_phys_wb_prepare_for_kickoff;
  1446. ops->handle_post_kickoff = sde_encoder_phys_wb_handle_post_kickoff;
  1447. ops->trigger_flush = sde_encoder_phys_wb_trigger_flush;
  1448. ops->trigger_start = sde_encoder_helper_trigger_start;
  1449. ops->hw_reset = sde_encoder_helper_hw_reset;
  1450. ops->irq_control = sde_encoder_phys_wb_irq_ctrl;
  1451. }
  1452. /**
  1453. * sde_encoder_phys_wb_init - initialize writeback encoder
  1454. * @init: Pointer to init info structure with initialization params
  1455. */
  1456. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  1457. struct sde_enc_phys_init_params *p)
  1458. {
  1459. struct sde_encoder_phys *phys_enc;
  1460. struct sde_encoder_phys_wb *wb_enc;
  1461. struct sde_hw_mdp *hw_mdp;
  1462. struct sde_encoder_irq *irq;
  1463. int ret = 0;
  1464. SDE_DEBUG("\n");
  1465. if (!p || !p->parent) {
  1466. SDE_ERROR("invalid params\n");
  1467. ret = -EINVAL;
  1468. goto fail_alloc;
  1469. }
  1470. wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
  1471. if (!wb_enc) {
  1472. SDE_ERROR("failed to allocate wb enc\n");
  1473. ret = -ENOMEM;
  1474. goto fail_alloc;
  1475. }
  1476. wb_enc->wbdone_timeout = KICKOFF_TIMEOUT_MS;
  1477. phys_enc = &wb_enc->base;
  1478. if (p->sde_kms->vbif[VBIF_NRT]) {
  1479. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1480. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_UNSECURE];
  1481. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1482. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_SECURE];
  1483. } else {
  1484. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1485. p->sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  1486. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1487. p->sde_kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  1488. }
  1489. hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
  1490. if (IS_ERR_OR_NULL(hw_mdp)) {
  1491. ret = PTR_ERR(hw_mdp);
  1492. SDE_ERROR("failed to init hw_top: %d\n", ret);
  1493. goto fail_mdp_init;
  1494. }
  1495. phys_enc->hw_mdptop = hw_mdp;
  1496. /**
  1497. * hw_wb resource permanently assigned to this encoder
  1498. * Other resources allocated at atomic commit time by use case
  1499. */
  1500. if (p->wb_idx != SDE_NONE) {
  1501. struct sde_rm_hw_iter iter;
  1502. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_WB);
  1503. while (sde_rm_get_hw(&p->sde_kms->rm, &iter)) {
  1504. struct sde_hw_wb *hw_wb = (struct sde_hw_wb *)iter.hw;
  1505. if (hw_wb->idx == p->wb_idx) {
  1506. wb_enc->hw_wb = hw_wb;
  1507. break;
  1508. }
  1509. }
  1510. if (!wb_enc->hw_wb) {
  1511. ret = -EINVAL;
  1512. SDE_ERROR("failed to init hw_wb%d\n", p->wb_idx - WB_0);
  1513. goto fail_wb_init;
  1514. }
  1515. } else {
  1516. ret = -EINVAL;
  1517. SDE_ERROR("invalid wb_idx\n");
  1518. goto fail_wb_check;
  1519. }
  1520. sde_encoder_phys_wb_init_ops(&phys_enc->ops);
  1521. phys_enc->parent = p->parent;
  1522. phys_enc->parent_ops = p->parent_ops;
  1523. phys_enc->sde_kms = p->sde_kms;
  1524. phys_enc->split_role = p->split_role;
  1525. phys_enc->intf_mode = INTF_MODE_WB_LINE;
  1526. phys_enc->intf_idx = p->intf_idx;
  1527. phys_enc->enc_spinlock = p->enc_spinlock;
  1528. phys_enc->vblank_ctl_lock = p->vblank_ctl_lock;
  1529. atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
  1530. atomic_set(&phys_enc->wbirq_refcount, 0);
  1531. init_waitqueue_head(&phys_enc->pending_kickoff_wq);
  1532. irq = &phys_enc->irq[INTR_IDX_WB_DONE];
  1533. INIT_LIST_HEAD(&irq->cb.list);
  1534. irq->name = "wb_done";
  1535. irq->hw_idx = wb_enc->hw_wb->idx;
  1536. irq->irq_idx = -1;
  1537. irq->intr_type = sde_encoder_phys_wb_get_intr_type(wb_enc->hw_wb);
  1538. irq->intr_idx = INTR_IDX_WB_DONE;
  1539. irq->cb.arg = wb_enc;
  1540. irq->cb.func = sde_encoder_phys_wb_done_irq;
  1541. irq = &phys_enc->irq[INTR_IDX_PP1_OVFL];
  1542. INIT_LIST_HEAD(&irq->cb.list);
  1543. irq->name = "pp1_overflow";
  1544. irq->hw_idx = CWB_1;
  1545. irq->irq_idx = -1;
  1546. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1547. irq->intr_idx = INTR_IDX_PP1_OVFL;
  1548. irq->cb.arg = wb_enc;
  1549. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1550. irq = &phys_enc->irq[INTR_IDX_PP2_OVFL];
  1551. INIT_LIST_HEAD(&irq->cb.list);
  1552. irq->name = "pp2_overflow";
  1553. irq->hw_idx = CWB_2;
  1554. irq->irq_idx = -1;
  1555. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1556. irq->intr_idx = INTR_IDX_PP2_OVFL;
  1557. irq->cb.arg = wb_enc;
  1558. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1559. irq = &phys_enc->irq[INTR_IDX_PP3_OVFL];
  1560. INIT_LIST_HEAD(&irq->cb.list);
  1561. irq->name = "pp3_overflow";
  1562. irq->hw_idx = CWB_3;
  1563. irq->irq_idx = -1;
  1564. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1565. irq->intr_idx = INTR_IDX_PP3_OVFL;
  1566. irq->cb.arg = wb_enc;
  1567. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1568. irq = &phys_enc->irq[INTR_IDX_PP4_OVFL];
  1569. INIT_LIST_HEAD(&irq->cb.list);
  1570. irq->name = "pp4_overflow";
  1571. irq->hw_idx = CWB_4;
  1572. irq->irq_idx = -1;
  1573. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1574. irq->intr_idx = INTR_IDX_PP4_OVFL;
  1575. irq->cb.arg = wb_enc;
  1576. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1577. irq = &phys_enc->irq[INTR_IDX_PP5_OVFL];
  1578. INIT_LIST_HEAD(&irq->cb.list);
  1579. irq->name = "pp5_overflow";
  1580. irq->hw_idx = CWB_5;
  1581. irq->irq_idx = -1;
  1582. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1583. irq->intr_idx = INTR_IDX_PP5_OVFL;
  1584. irq->cb.arg = wb_enc;
  1585. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1586. /* create internal buffer for disable logic */
  1587. if (_sde_encoder_phys_wb_init_internal_fb(wb_enc,
  1588. DRM_FORMAT_RGB888, 2, 1, 6)) {
  1589. SDE_ERROR("failed to init internal fb\n");
  1590. goto fail_wb_init;
  1591. }
  1592. SDE_DEBUG("Created sde_encoder_phys_wb for wb %d\n",
  1593. wb_enc->hw_wb->idx - WB_0);
  1594. return phys_enc;
  1595. fail_wb_init:
  1596. fail_wb_check:
  1597. fail_mdp_init:
  1598. kfree(wb_enc);
  1599. fail_alloc:
  1600. return ERR_PTR(ret);
  1601. }