dsi_phy_hw_v4_0.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "dsi-phy-hw-v4: %s:" fmt, __func__
  6. #include <linux/math64.h>
  7. #include <linux/delay.h>
  8. #include <linux/iopoll.h>
  9. #include "dsi_hw.h"
  10. #include "dsi_phy_hw.h"
  11. #include "dsi_catalog.h"
  12. #define DSIPHY_CMN_REVISION_ID0 0x000
  13. #define DSIPHY_CMN_REVISION_ID1 0x004
  14. #define DSIPHY_CMN_REVISION_ID2 0x008
  15. #define DSIPHY_CMN_REVISION_ID3 0x00C
  16. #define DSIPHY_CMN_CLK_CFG0 0x010
  17. #define DSIPHY_CMN_CLK_CFG1 0x014
  18. #define DSIPHY_CMN_GLBL_CTRL 0x018
  19. #define DSIPHY_CMN_RBUF_CTRL 0x01C
  20. #define DSIPHY_CMN_VREG_CTRL_0 0x020
  21. #define DSIPHY_CMN_CTRL_0 0x024
  22. #define DSIPHY_CMN_CTRL_1 0x028
  23. #define DSIPHY_CMN_CTRL_2 0x02C
  24. #define DSIPHY_CMN_CTRL_3 0x030
  25. #define DSIPHY_CMN_LANE_CFG0 0x034
  26. #define DSIPHY_CMN_LANE_CFG1 0x038
  27. #define DSIPHY_CMN_PLL_CNTRL 0x03C
  28. #define DSIPHY_CMN_DPHY_SOT 0x040
  29. #define DSIPHY_CMN_LANE_CTRL0 0x0A0
  30. #define DSIPHY_CMN_LANE_CTRL1 0x0A4
  31. #define DSIPHY_CMN_LANE_CTRL2 0x0A8
  32. #define DSIPHY_CMN_LANE_CTRL3 0x0AC
  33. #define DSIPHY_CMN_LANE_CTRL4 0x0B0
  34. #define DSIPHY_CMN_TIMING_CTRL_0 0x0B4
  35. #define DSIPHY_CMN_TIMING_CTRL_1 0x0B8
  36. #define DSIPHY_CMN_TIMING_CTRL_2 0x0Bc
  37. #define DSIPHY_CMN_TIMING_CTRL_3 0x0C0
  38. #define DSIPHY_CMN_TIMING_CTRL_4 0x0C4
  39. #define DSIPHY_CMN_TIMING_CTRL_5 0x0C8
  40. #define DSIPHY_CMN_TIMING_CTRL_6 0x0CC
  41. #define DSIPHY_CMN_TIMING_CTRL_7 0x0D0
  42. #define DSIPHY_CMN_TIMING_CTRL_8 0x0D4
  43. #define DSIPHY_CMN_TIMING_CTRL_9 0x0D8
  44. #define DSIPHY_CMN_TIMING_CTRL_10 0x0DC
  45. #define DSIPHY_CMN_TIMING_CTRL_11 0x0E0
  46. #define DSIPHY_CMN_TIMING_CTRL_12 0x0E4
  47. #define DSIPHY_CMN_TIMING_CTRL_13 0x0E8
  48. #define DSIPHY_CMN_GLBL_HSTX_STR_CTRL_0 0x0EC
  49. #define DSIPHY_CMN_GLBL_HSTX_STR_CTRL_1 0x0F0
  50. #define DSIPHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x0F4
  51. #define DSIPHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x0F8
  52. #define DSIPHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x0FC
  53. #define DSIPHY_CMN_GLBL_LPTX_STR_CTRL 0x100
  54. #define DSIPHY_CMN_GLBL_PEMPH_CTRL_0 0x104
  55. #define DSIPHY_CMN_GLBL_PEMPH_CTRL_1 0x108
  56. #define DSIPHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x10C
  57. #define DSIPHY_CMN_VREG_CTRL_1 0x110
  58. #define DSIPHY_CMN_CTRL_4 0x114
  59. #define DSIPHY_CMN_PHY_STATUS 0x140
  60. #define DSIPHY_CMN_LANE_STATUS0 0x148
  61. #define DSIPHY_CMN_LANE_STATUS1 0x14C
  62. /* n = 0..3 for data lanes and n = 4 for clock lane */
  63. #define DSIPHY_LNX_CFG0(n) (0x200 + (0x80 * (n)))
  64. #define DSIPHY_LNX_CFG1(n) (0x204 + (0x80 * (n)))
  65. #define DSIPHY_LNX_CFG2(n) (0x208 + (0x80 * (n)))
  66. #define DSIPHY_LNX_TEST_DATAPATH(n) (0x20C + (0x80 * (n)))
  67. #define DSIPHY_LNX_PIN_SWAP(n) (0x210 + (0x80 * (n)))
  68. #define DSIPHY_LNX_LPRX_CTRL(n) (0x214 + (0x80 * (n)))
  69. #define DSIPHY_LNX_TX_DCTRL(n) (0x218 + (0x80 * (n)))
  70. /* dynamic refresh control registers */
  71. #define DSI_DYN_REFRESH_CTRL (0x000)
  72. #define DSI_DYN_REFRESH_PIPE_DELAY (0x004)
  73. #define DSI_DYN_REFRESH_PIPE_DELAY2 (0x008)
  74. #define DSI_DYN_REFRESH_PLL_DELAY (0x00C)
  75. #define DSI_DYN_REFRESH_STATUS (0x010)
  76. #define DSI_DYN_REFRESH_PLL_CTRL0 (0x014)
  77. #define DSI_DYN_REFRESH_PLL_CTRL1 (0x018)
  78. #define DSI_DYN_REFRESH_PLL_CTRL2 (0x01C)
  79. #define DSI_DYN_REFRESH_PLL_CTRL3 (0x020)
  80. #define DSI_DYN_REFRESH_PLL_CTRL4 (0x024)
  81. #define DSI_DYN_REFRESH_PLL_CTRL5 (0x028)
  82. #define DSI_DYN_REFRESH_PLL_CTRL6 (0x02C)
  83. #define DSI_DYN_REFRESH_PLL_CTRL7 (0x030)
  84. #define DSI_DYN_REFRESH_PLL_CTRL8 (0x034)
  85. #define DSI_DYN_REFRESH_PLL_CTRL9 (0x038)
  86. #define DSI_DYN_REFRESH_PLL_CTRL10 (0x03C)
  87. #define DSI_DYN_REFRESH_PLL_CTRL11 (0x040)
  88. #define DSI_DYN_REFRESH_PLL_CTRL12 (0x044)
  89. #define DSI_DYN_REFRESH_PLL_CTRL13 (0x048)
  90. #define DSI_DYN_REFRESH_PLL_CTRL14 (0x04C)
  91. #define DSI_DYN_REFRESH_PLL_CTRL15 (0x050)
  92. #define DSI_DYN_REFRESH_PLL_CTRL16 (0x054)
  93. #define DSI_DYN_REFRESH_PLL_CTRL17 (0x058)
  94. #define DSI_DYN_REFRESH_PLL_CTRL18 (0x05C)
  95. #define DSI_DYN_REFRESH_PLL_CTRL19 (0x060)
  96. #define DSI_DYN_REFRESH_PLL_CTRL20 (0x064)
  97. #define DSI_DYN_REFRESH_PLL_CTRL21 (0x068)
  98. #define DSI_DYN_REFRESH_PLL_CTRL22 (0x06C)
  99. #define DSI_DYN_REFRESH_PLL_CTRL23 (0x070)
  100. #define DSI_DYN_REFRESH_PLL_CTRL24 (0x074)
  101. #define DSI_DYN_REFRESH_PLL_CTRL25 (0x078)
  102. #define DSI_DYN_REFRESH_PLL_CTRL26 (0x07C)
  103. #define DSI_DYN_REFRESH_PLL_CTRL27 (0x080)
  104. #define DSI_DYN_REFRESH_PLL_CTRL28 (0x084)
  105. #define DSI_DYN_REFRESH_PLL_CTRL29 (0x088)
  106. #define DSI_DYN_REFRESH_PLL_CTRL30 (0x08C)
  107. #define DSI_DYN_REFRESH_PLL_CTRL31 (0x090)
  108. #define DSI_DYN_REFRESH_PLL_UPPER_ADDR (0x094)
  109. #define DSI_DYN_REFRESH_PLL_UPPER_ADDR2 (0x098)
  110. static int dsi_phy_hw_v4_0_is_pll_on(struct dsi_phy_hw *phy)
  111. {
  112. u32 data = 0;
  113. data = DSI_R32(phy, DSIPHY_CMN_PLL_CNTRL);
  114. mb(); /*make sure read happened */
  115. return (data & BIT(0));
  116. }
  117. static void dsi_phy_hw_v4_0_config_lpcdrx(struct dsi_phy_hw *phy,
  118. struct dsi_phy_cfg *cfg, bool enable)
  119. {
  120. int phy_lane_0 = dsi_phy_conv_logical_to_phy_lane(&cfg->lane_map,
  121. DSI_LOGICAL_LANE_0);
  122. /*
  123. * LPRX and CDRX need to enabled only for physical data lane
  124. * corresponding to the logical data lane 0
  125. */
  126. if (enable)
  127. DSI_W32(phy, DSIPHY_LNX_LPRX_CTRL(phy_lane_0),
  128. cfg->strength.lane[phy_lane_0][1]);
  129. else
  130. DSI_W32(phy, DSIPHY_LNX_LPRX_CTRL(phy_lane_0), 0);
  131. }
  132. static void dsi_phy_hw_v4_0_lane_swap_config(struct dsi_phy_hw *phy,
  133. struct dsi_lane_map *lane_map)
  134. {
  135. DSI_W32(phy, DSIPHY_CMN_LANE_CFG0,
  136. (lane_map->lane_map_v2[DSI_LOGICAL_LANE_0] |
  137. (lane_map->lane_map_v2[DSI_LOGICAL_LANE_1] << 4)));
  138. DSI_W32(phy, DSIPHY_CMN_LANE_CFG1,
  139. (lane_map->lane_map_v2[DSI_LOGICAL_LANE_2] |
  140. (lane_map->lane_map_v2[DSI_LOGICAL_LANE_3] << 4)));
  141. }
  142. static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy,
  143. struct dsi_phy_cfg *cfg)
  144. {
  145. int i;
  146. u8 tx_dctrl_v4[] = {0x00, 0x00, 0x00, 0x04, 0x01};
  147. u8 tx_dctrl_v4_1[] = {0x40, 0x40, 0x40, 0x46, 0x41};
  148. u8 *tx_dctrl;
  149. if (phy->version == DSI_PHY_VERSION_4_1)
  150. tx_dctrl = &tx_dctrl_v4_1[0];
  151. else
  152. tx_dctrl = &tx_dctrl_v4[0];
  153. /* Strength ctrl settings */
  154. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
  155. /*
  156. * Disable LPRX and CDRX for all lanes. And later on, it will
  157. * be only enabled for the physical data lane corresponding
  158. * to the logical data lane 0
  159. */
  160. DSI_W32(phy, DSIPHY_LNX_LPRX_CTRL(i), 0);
  161. DSI_W32(phy, DSIPHY_LNX_PIN_SWAP(i), 0x0);
  162. }
  163. dsi_phy_hw_v4_0_config_lpcdrx(phy, cfg, true);
  164. /* other settings */
  165. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
  166. DSI_W32(phy, DSIPHY_LNX_CFG0(i), cfg->lanecfg.lane[i][0]);
  167. DSI_W32(phy, DSIPHY_LNX_CFG1(i), cfg->lanecfg.lane[i][1]);
  168. DSI_W32(phy, DSIPHY_LNX_CFG2(i), cfg->lanecfg.lane[i][2]);
  169. DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(i), tx_dctrl[i]);
  170. }
  171. if (cfg->force_clk_lane_hs) {
  172. u32 reg = DSI_R32(phy, DSIPHY_CMN_LANE_CTRL1);
  173. reg |= BIT(5) | BIT(6);
  174. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL1, reg);
  175. }
  176. }
  177. /**
  178. * enable() - Enable PHY hardware
  179. * @phy: Pointer to DSI PHY hardware object.
  180. * @cfg: Per lane configurations for timing, strength and lane
  181. * configurations.
  182. */
  183. void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
  184. struct dsi_phy_cfg *cfg)
  185. {
  186. int rc = 0;
  187. u32 status;
  188. u32 const delay_us = 5;
  189. u32 const timeout_us = 1000;
  190. struct dsi_phy_per_lane_cfgs *timing = &cfg->timing;
  191. u32 data;
  192. u32 minor_ver = 0;
  193. bool less_than_1500_mhz = false;
  194. u32 vreg_ctrl_0 = 0;
  195. u32 glbl_str_swi_cal_sel_ctrl = 0;
  196. u32 glbl_hstx_str_ctrl_0 = 0;
  197. u32 glbl_rescode_top_ctrl = 0;
  198. u32 glbl_rescode_bot_ctrl = 0;
  199. if (dsi_phy_hw_v4_0_is_pll_on(phy))
  200. pr_warn("PLL turned on before configuring PHY\n");
  201. /* wait for REFGEN READY */
  202. rc = readl_poll_timeout_atomic(phy->base + DSIPHY_CMN_PHY_STATUS,
  203. status, (status & BIT(0)), delay_us, timeout_us);
  204. if (rc) {
  205. pr_err("Ref gen not ready. Aborting\n");
  206. return;
  207. }
  208. /* Alter PHY configurations if data rate less than 1.5GHZ*/
  209. if (cfg->bit_clk_rate_hz <= 1500000000)
  210. less_than_1500_mhz = true;
  211. if (phy->version == DSI_PHY_VERSION_4_1) {
  212. vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
  213. glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
  214. glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
  215. glbl_str_swi_cal_sel_ctrl = 0x00;
  216. glbl_hstx_str_ctrl_0 = 0x88;
  217. } else {
  218. vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
  219. glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
  220. glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
  221. glbl_rescode_top_ctrl = 0x03;
  222. glbl_rescode_bot_ctrl = 0x3c;
  223. }
  224. /* de-assert digital and pll power down */
  225. data = BIT(6) | BIT(5);
  226. DSI_W32(phy, DSIPHY_CMN_CTRL_0, data);
  227. /* Assert PLL core reset */
  228. DSI_W32(phy, DSIPHY_CMN_PLL_CNTRL, 0x00);
  229. /* turn off resync FIFO */
  230. DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x00);
  231. /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
  232. minor_ver = DSI_R32(phy, DSIPHY_CMN_REVISION_ID0);
  233. minor_ver = minor_ver & (0xf0);
  234. if (minor_ver == 0x20)
  235. DSI_W32(phy, DSIPHY_CMN_CTRL_4, 0x04);
  236. /* Configure PHY lane swap */
  237. dsi_phy_hw_v4_0_lane_swap_config(phy, &cfg->lane_map);
  238. /* Enable LDO */
  239. DSI_W32(phy, DSIPHY_CMN_VREG_CTRL_0, vreg_ctrl_0);
  240. DSI_W32(phy, DSIPHY_CMN_VREG_CTRL_1, 0x5c);
  241. DSI_W32(phy, DSIPHY_CMN_CTRL_3, 0x00);
  242. DSI_W32(phy, DSIPHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,
  243. glbl_str_swi_cal_sel_ctrl);
  244. DSI_W32(phy, DSIPHY_CMN_GLBL_HSTX_STR_CTRL_0, glbl_hstx_str_ctrl_0);
  245. DSI_W32(phy, DSIPHY_CMN_GLBL_PEMPH_CTRL_0, 0x00);
  246. DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
  247. glbl_rescode_top_ctrl);
  248. DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
  249. glbl_rescode_bot_ctrl);
  250. DSI_W32(phy, DSIPHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
  251. /* Remove power down from all blocks */
  252. DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0x7f);
  253. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL0, 0x1F);
  254. /* Select full-rate mode */
  255. DSI_W32(phy, DSIPHY_CMN_CTRL_2, 0x40);
  256. switch (cfg->pll_source) {
  257. case DSI_PLL_SOURCE_STANDALONE:
  258. case DSI_PLL_SOURCE_NATIVE:
  259. data = 0x0; /* internal PLL */
  260. break;
  261. case DSI_PLL_SOURCE_NON_NATIVE:
  262. data = 0x1; /* external PLL */
  263. break;
  264. default:
  265. break;
  266. }
  267. DSI_W32(phy, DSIPHY_CMN_CLK_CFG1, (data << 2)); /* set PLL src */
  268. /* DSI PHY timings */
  269. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_0, timing->lane_v4[0]);
  270. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_1, timing->lane_v4[1]);
  271. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_2, timing->lane_v4[2]);
  272. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_3, timing->lane_v4[3]);
  273. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_4, timing->lane_v4[4]);
  274. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_5, timing->lane_v4[5]);
  275. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_6, timing->lane_v4[6]);
  276. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_7, timing->lane_v4[7]);
  277. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_8, timing->lane_v4[8]);
  278. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_9, timing->lane_v4[9]);
  279. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_10, timing->lane_v4[10]);
  280. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_11, timing->lane_v4[11]);
  281. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_12, timing->lane_v4[12]);
  282. DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_13, timing->lane_v4[13]);
  283. /* DSI lane settings */
  284. dsi_phy_hw_v4_0_lane_settings(phy, cfg);
  285. pr_debug("[DSI_%d]Phy enabled\n", phy->index);
  286. }
  287. /**
  288. * disable() - Disable PHY hardware
  289. * @phy: Pointer to DSI PHY hardware object.
  290. */
  291. void dsi_phy_hw_v4_0_disable(struct dsi_phy_hw *phy,
  292. struct dsi_phy_cfg *cfg)
  293. {
  294. u32 data = 0;
  295. if (dsi_phy_hw_v4_0_is_pll_on(phy))
  296. pr_warn("Turning OFF PHY while PLL is on\n");
  297. dsi_phy_hw_v4_0_config_lpcdrx(phy, cfg, false);
  298. data = DSI_R32(phy, DSIPHY_CMN_CTRL_0);
  299. /* disable all lanes */
  300. data &= ~0x1F;
  301. DSI_W32(phy, DSIPHY_CMN_CTRL_0, data);
  302. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL0, 0);
  303. /* Turn off all PHY blocks */
  304. DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0x00);
  305. /* make sure phy is turned off */
  306. wmb();
  307. pr_debug("[DSI_%d]Phy disabled\n", phy->index);
  308. }
  309. void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy)
  310. {
  311. DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x00);
  312. /* ensure that the FIFO is off */
  313. wmb();
  314. DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x1);
  315. /* ensure that the FIFO is toggled back on */
  316. wmb();
  317. }
  318. void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy)
  319. {
  320. u32 data = 0;
  321. /*Turning off CLK_EN_SEL after retime buffer sync */
  322. data = DSI_R32(phy, DSIPHY_CMN_CLK_CFG1);
  323. data &= ~BIT(4);
  324. DSI_W32(phy, DSIPHY_CMN_CLK_CFG1, data);
  325. /* ensure that clk_en_sel bit is turned off */
  326. wmb();
  327. }
  328. int dsi_phy_hw_v4_0_wait_for_lane_idle(
  329. struct dsi_phy_hw *phy, u32 lanes)
  330. {
  331. int rc = 0, val = 0;
  332. u32 stop_state_mask = 0;
  333. u32 const sleep_us = 10;
  334. u32 const timeout_us = 100;
  335. stop_state_mask = BIT(4); /* clock lane */
  336. if (lanes & DSI_DATA_LANE_0)
  337. stop_state_mask |= BIT(0);
  338. if (lanes & DSI_DATA_LANE_1)
  339. stop_state_mask |= BIT(1);
  340. if (lanes & DSI_DATA_LANE_2)
  341. stop_state_mask |= BIT(2);
  342. if (lanes & DSI_DATA_LANE_3)
  343. stop_state_mask |= BIT(3);
  344. pr_debug("%s: polling for lanes to be in stop state, mask=0x%08x\n",
  345. __func__, stop_state_mask);
  346. rc = readl_poll_timeout(phy->base + DSIPHY_CMN_LANE_STATUS1, val,
  347. ((val & stop_state_mask) == stop_state_mask),
  348. sleep_us, timeout_us);
  349. if (rc) {
  350. pr_err("%s: lanes not in stop state, LANE_STATUS=0x%08x\n",
  351. __func__, val);
  352. return rc;
  353. }
  354. return 0;
  355. }
  356. void dsi_phy_hw_v4_0_ulps_request(struct dsi_phy_hw *phy,
  357. struct dsi_phy_cfg *cfg, u32 lanes)
  358. {
  359. u32 reg = 0;
  360. if (lanes & DSI_CLOCK_LANE)
  361. reg = BIT(4);
  362. if (lanes & DSI_DATA_LANE_0)
  363. reg |= BIT(0);
  364. if (lanes & DSI_DATA_LANE_1)
  365. reg |= BIT(1);
  366. if (lanes & DSI_DATA_LANE_2)
  367. reg |= BIT(2);
  368. if (lanes & DSI_DATA_LANE_3)
  369. reg |= BIT(3);
  370. if (cfg->force_clk_lane_hs)
  371. reg |= BIT(5) | BIT(6);
  372. /*
  373. * ULPS entry request. Wait for short time to make sure
  374. * that the lanes enter ULPS. Recommended as per HPG.
  375. */
  376. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL1, reg);
  377. usleep_range(100, 110);
  378. /* disable LPRX and CDRX */
  379. dsi_phy_hw_v4_0_config_lpcdrx(phy, cfg, false);
  380. pr_debug("[DSI_PHY%d] ULPS requested for lanes 0x%x\n", phy->index,
  381. lanes);
  382. }
  383. int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy)
  384. {
  385. int ret = 0, loop = 10, u_dly = 200;
  386. u32 ln_status = 0;
  387. while ((ln_status != 0x1f) && loop) {
  388. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL3, 0x1f);
  389. wmb(); /* ensure register is committed */
  390. loop--;
  391. udelay(u_dly);
  392. ln_status = DSI_R32(phy, DSIPHY_CMN_LANE_STATUS1);
  393. pr_debug("trial no: %d\n", loop);
  394. }
  395. if (!loop)
  396. pr_debug("could not reset phy lanes\n");
  397. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL3, 0x0);
  398. wmb(); /* ensure register is committed */
  399. return ret;
  400. }
  401. void dsi_phy_hw_v4_0_ulps_exit(struct dsi_phy_hw *phy,
  402. struct dsi_phy_cfg *cfg, u32 lanes)
  403. {
  404. u32 reg = 0;
  405. if (lanes & DSI_CLOCK_LANE)
  406. reg = BIT(4);
  407. if (lanes & DSI_DATA_LANE_0)
  408. reg |= BIT(0);
  409. if (lanes & DSI_DATA_LANE_1)
  410. reg |= BIT(1);
  411. if (lanes & DSI_DATA_LANE_2)
  412. reg |= BIT(2);
  413. if (lanes & DSI_DATA_LANE_3)
  414. reg |= BIT(3);
  415. /* enable LPRX and CDRX */
  416. dsi_phy_hw_v4_0_config_lpcdrx(phy, cfg, true);
  417. /* ULPS exit request */
  418. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL2, reg);
  419. usleep_range(1000, 1010);
  420. /* Clear ULPS request flags on all lanes */
  421. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL1, 0);
  422. /* Clear ULPS exit flags on all lanes */
  423. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL2, 0);
  424. /*
  425. * Sometimes when exiting ULPS, it is possible that some DSI
  426. * lanes are not in the stop state which could lead to DSI
  427. * commands not going through. To avoid this, force the lanes
  428. * to be in stop state.
  429. */
  430. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL3, reg);
  431. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL3, 0);
  432. usleep_range(100, 110);
  433. if (cfg->force_clk_lane_hs) {
  434. reg = BIT(5) | BIT(6);
  435. DSI_W32(phy, DSIPHY_CMN_LANE_CTRL1, reg);
  436. }
  437. }
  438. u32 dsi_phy_hw_v4_0_get_lanes_in_ulps(struct dsi_phy_hw *phy)
  439. {
  440. u32 lanes = 0;
  441. lanes = DSI_R32(phy, DSIPHY_CMN_LANE_STATUS0);
  442. pr_debug("[DSI_PHY%d] lanes in ulps = 0x%x\n", phy->index, lanes);
  443. return lanes;
  444. }
  445. bool dsi_phy_hw_v4_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes)
  446. {
  447. if (lanes & ulps_lanes)
  448. return false;
  449. return true;
  450. }
  451. int dsi_phy_hw_timing_val_v4_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
  452. u32 *timing_val, u32 size)
  453. {
  454. int i = 0;
  455. if (size != DSI_PHY_TIMING_V4_SIZE) {
  456. pr_err("Unexpected timing array size %d\n", size);
  457. return -EINVAL;
  458. }
  459. for (i = 0; i < size; i++)
  460. timing_cfg->lane_v4[i] = timing_val[i];
  461. return 0;
  462. }
  463. void dsi_phy_hw_v4_0_dyn_refresh_config(struct dsi_phy_hw *phy,
  464. struct dsi_phy_cfg *cfg, bool is_master)
  465. {
  466. u32 reg;
  467. if (is_master) {
  468. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL19,
  469. DSIPHY_CMN_TIMING_CTRL_0, DSIPHY_CMN_TIMING_CTRL_1,
  470. cfg->timing.lane_v4[0], cfg->timing.lane_v4[1]);
  471. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL20,
  472. DSIPHY_CMN_TIMING_CTRL_2, DSIPHY_CMN_TIMING_CTRL_3,
  473. cfg->timing.lane_v4[2], cfg->timing.lane_v4[3]);
  474. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL21,
  475. DSIPHY_CMN_TIMING_CTRL_4, DSIPHY_CMN_TIMING_CTRL_5,
  476. cfg->timing.lane_v4[4], cfg->timing.lane_v4[5]);
  477. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL22,
  478. DSIPHY_CMN_TIMING_CTRL_6, DSIPHY_CMN_TIMING_CTRL_7,
  479. cfg->timing.lane_v4[6], cfg->timing.lane_v4[7]);
  480. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL23,
  481. DSIPHY_CMN_TIMING_CTRL_8, DSIPHY_CMN_TIMING_CTRL_9,
  482. cfg->timing.lane_v4[8], cfg->timing.lane_v4[9]);
  483. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL24,
  484. DSIPHY_CMN_TIMING_CTRL_10, DSIPHY_CMN_TIMING_CTRL_11,
  485. cfg->timing.lane_v4[10], cfg->timing.lane_v4[11]);
  486. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL25,
  487. DSIPHY_CMN_TIMING_CTRL_12, DSIPHY_CMN_TIMING_CTRL_13,
  488. cfg->timing.lane_v4[12], cfg->timing.lane_v4[13]);
  489. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL26,
  490. DSIPHY_CMN_CTRL_0, DSIPHY_CMN_LANE_CTRL0,
  491. 0x7f, 0x1f);
  492. } else {
  493. reg = DSI_R32(phy, DSIPHY_CMN_CLK_CFG1);
  494. reg &= ~BIT(5);
  495. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL0,
  496. DSIPHY_CMN_CLK_CFG1, DSIPHY_CMN_PLL_CNTRL,
  497. reg, 0x0);
  498. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL1,
  499. DSIPHY_CMN_RBUF_CTRL, DSIPHY_CMN_TIMING_CTRL_0,
  500. 0x0, cfg->timing.lane_v4[0]);
  501. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL2,
  502. DSIPHY_CMN_TIMING_CTRL_1, DSIPHY_CMN_TIMING_CTRL_2,
  503. cfg->timing.lane_v4[1], cfg->timing.lane_v4[2]);
  504. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL3,
  505. DSIPHY_CMN_TIMING_CTRL_3, DSIPHY_CMN_TIMING_CTRL_4,
  506. cfg->timing.lane_v4[3], cfg->timing.lane_v4[4]);
  507. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL4,
  508. DSIPHY_CMN_TIMING_CTRL_5, DSIPHY_CMN_TIMING_CTRL_6,
  509. cfg->timing.lane_v4[5], cfg->timing.lane_v4[6]);
  510. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL5,
  511. DSIPHY_CMN_TIMING_CTRL_7, DSIPHY_CMN_TIMING_CTRL_8,
  512. cfg->timing.lane_v4[7], cfg->timing.lane_v4[8]);
  513. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL6,
  514. DSIPHY_CMN_TIMING_CTRL_9, DSIPHY_CMN_TIMING_CTRL_10,
  515. cfg->timing.lane_v4[9], cfg->timing.lane_v4[10]);
  516. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL7,
  517. DSIPHY_CMN_TIMING_CTRL_11, DSIPHY_CMN_TIMING_CTRL_12,
  518. cfg->timing.lane_v4[11], cfg->timing.lane_v4[12]);
  519. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL8,
  520. DSIPHY_CMN_TIMING_CTRL_13, DSIPHY_CMN_CTRL_0,
  521. cfg->timing.lane_v4[13], 0x7f);
  522. DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL9,
  523. DSIPHY_CMN_LANE_CTRL0, DSIPHY_CMN_CTRL_2,
  524. 0x1f, 0x40);
  525. /*
  526. * fill with dummy register writes since controller will blindly
  527. * send these values to DSI PHY.
  528. */
  529. reg = DSI_DYN_REFRESH_PLL_CTRL11;
  530. while (reg <= DSI_DYN_REFRESH_PLL_CTRL29) {
  531. DSI_DYN_REF_REG_W(phy->dyn_pll_base, reg,
  532. DSIPHY_CMN_LANE_CTRL0, DSIPHY_CMN_CTRL_0,
  533. 0x1f, 0x7f);
  534. reg += 0x4;
  535. }
  536. DSI_GEN_W32(phy->dyn_pll_base,
  537. DSI_DYN_REFRESH_PLL_UPPER_ADDR, 0);
  538. DSI_GEN_W32(phy->dyn_pll_base,
  539. DSI_DYN_REFRESH_PLL_UPPER_ADDR2, 0);
  540. }
  541. wmb(); /* make sure all registers are updated */
  542. }
  543. void dsi_phy_hw_v4_0_dyn_refresh_pipe_delay(struct dsi_phy_hw *phy,
  544. struct dsi_dyn_clk_delay *delay)
  545. {
  546. if (!delay)
  547. return;
  548. DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_PIPE_DELAY,
  549. delay->pipe_delay);
  550. DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_PIPE_DELAY2,
  551. delay->pipe_delay2);
  552. DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_DELAY,
  553. delay->pll_delay);
  554. }
  555. void dsi_phy_hw_v4_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset)
  556. {
  557. u32 reg;
  558. /*
  559. * if no offset is mentioned then this means we want to clear
  560. * the dynamic refresh ctrl register which is the last step
  561. * of dynamic refresh sequence.
  562. */
  563. if (!offset) {
  564. reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL);
  565. reg &= ~(BIT(0) | BIT(8));
  566. DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg);
  567. wmb(); /* ensure dynamic fps is cleared */
  568. return;
  569. }
  570. if (offset & BIT(DYN_REFRESH_INTF_SEL)) {
  571. reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL);
  572. reg |= BIT(13);
  573. DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg);
  574. }
  575. if (offset & BIT(DYN_REFRESH_SYNC_MODE)) {
  576. reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL);
  577. reg |= BIT(16);
  578. DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg);
  579. }
  580. if (offset & BIT(DYN_REFRESH_SWI_CTRL)) {
  581. reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL);
  582. reg |= BIT(0);
  583. DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg);
  584. }
  585. if (offset & BIT(DYN_REFRESH_SW_TRIGGER)) {
  586. reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL);
  587. reg |= BIT(8);
  588. DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg);
  589. wmb(); /* ensure dynamic fps is triggered */
  590. }
  591. }
  592. int dsi_phy_hw_v4_0_cache_phy_timings(struct dsi_phy_per_lane_cfgs *timings,
  593. u32 *dst, u32 size)
  594. {
  595. int i;
  596. if (!timings || !dst || !size)
  597. return -EINVAL;
  598. if (size != DSI_PHY_TIMING_V4_SIZE) {
  599. pr_err("size mis-match\n");
  600. return -EINVAL;
  601. }
  602. for (i = 0; i < size; i++)
  603. dst[i] = timings->lane_v4[i];
  604. return 0;
  605. }