debug.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
  3. /* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
  4. #include <linux/err.h>
  5. #include <linux/seq_file.h>
  6. #include <linux/debugfs.h>
  7. #include "main.h"
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "pci.h"
  11. #define MMIO_REG_ACCESS_MEM_TYPE 0xFF
  12. #define MMIO_REG_RAW_ACCESS_MEM_TYPE 0xFE
  13. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  14. void *cnss_ipc_log_context;
  15. void *cnss_ipc_log_long_context;
  16. #endif
  17. static int cnss_pin_connect_show(struct seq_file *s, void *data)
  18. {
  19. struct cnss_plat_data *cnss_priv = s->private;
  20. seq_puts(s, "Pin connect results\n");
  21. seq_printf(s, "FW power pin result: %04x\n",
  22. cnss_priv->pin_result.fw_pwr_pin_result);
  23. seq_printf(s, "FW PHY IO pin result: %04x\n",
  24. cnss_priv->pin_result.fw_phy_io_pin_result);
  25. seq_printf(s, "FW RF pin result: %04x\n",
  26. cnss_priv->pin_result.fw_rf_pin_result);
  27. seq_printf(s, "Host pin result: %04x\n",
  28. cnss_priv->pin_result.host_pin_result);
  29. seq_puts(s, "\n");
  30. return 0;
  31. }
  32. static int cnss_pin_connect_open(struct inode *inode, struct file *file)
  33. {
  34. return single_open(file, cnss_pin_connect_show, inode->i_private);
  35. }
  36. static const struct file_operations cnss_pin_connect_fops = {
  37. .read = seq_read,
  38. .release = single_release,
  39. .open = cnss_pin_connect_open,
  40. .owner = THIS_MODULE,
  41. .llseek = seq_lseek,
  42. };
  43. static int cnss_stats_show_state(struct seq_file *s,
  44. struct cnss_plat_data *plat_priv)
  45. {
  46. enum cnss_driver_state i;
  47. int skip = 0;
  48. unsigned long state;
  49. seq_printf(s, "\nState: 0x%lx(", plat_priv->driver_state);
  50. for (i = 0, state = plat_priv->driver_state; state != 0;
  51. state >>= 1, i++) {
  52. if (!(state & 0x1))
  53. continue;
  54. if (skip++)
  55. seq_puts(s, " | ");
  56. switch (i) {
  57. case CNSS_QMI_WLFW_CONNECTED:
  58. seq_puts(s, "QMI_WLFW_CONNECTED");
  59. continue;
  60. case CNSS_FW_MEM_READY:
  61. seq_puts(s, "FW_MEM_READY");
  62. continue;
  63. case CNSS_FW_READY:
  64. seq_puts(s, "FW_READY");
  65. continue;
  66. case CNSS_IN_COLD_BOOT_CAL:
  67. seq_puts(s, "IN_COLD_BOOT_CAL");
  68. continue;
  69. case CNSS_DRIVER_LOADING:
  70. seq_puts(s, "DRIVER_LOADING");
  71. continue;
  72. case CNSS_DRIVER_UNLOADING:
  73. seq_puts(s, "DRIVER_UNLOADING");
  74. continue;
  75. case CNSS_DRIVER_IDLE_RESTART:
  76. seq_puts(s, "IDLE_RESTART");
  77. continue;
  78. case CNSS_DRIVER_IDLE_SHUTDOWN:
  79. seq_puts(s, "IDLE_SHUTDOWN");
  80. continue;
  81. case CNSS_DRIVER_PROBED:
  82. seq_puts(s, "DRIVER_PROBED");
  83. continue;
  84. case CNSS_DRIVER_RECOVERY:
  85. seq_puts(s, "DRIVER_RECOVERY");
  86. continue;
  87. case CNSS_FW_BOOT_RECOVERY:
  88. seq_puts(s, "FW_BOOT_RECOVERY");
  89. continue;
  90. case CNSS_DEV_ERR_NOTIFY:
  91. seq_puts(s, "DEV_ERR");
  92. continue;
  93. case CNSS_DRIVER_DEBUG:
  94. seq_puts(s, "DRIVER_DEBUG");
  95. continue;
  96. case CNSS_COEX_CONNECTED:
  97. seq_puts(s, "COEX_CONNECTED");
  98. continue;
  99. case CNSS_IMS_CONNECTED:
  100. seq_puts(s, "IMS_CONNECTED");
  101. continue;
  102. case CNSS_IN_SUSPEND_RESUME:
  103. seq_puts(s, "IN_SUSPEND_RESUME");
  104. continue;
  105. case CNSS_IN_REBOOT:
  106. seq_puts(s, "IN_REBOOT");
  107. continue;
  108. case CNSS_COLD_BOOT_CAL_DONE:
  109. seq_puts(s, "COLD_BOOT_CAL_DONE");
  110. continue;
  111. case CNSS_IN_PANIC:
  112. seq_puts(s, "IN_PANIC");
  113. continue;
  114. case CNSS_QMI_DEL_SERVER:
  115. seq_puts(s, "DEL_SERVER_IN_PROGRESS");
  116. continue;
  117. case CNSS_QMI_DMS_CONNECTED:
  118. seq_puts(s, "DMS_CONNECTED");
  119. continue;
  120. case CNSS_DMS_DEL_SERVER:
  121. seq_puts(s, "DMS_DEL_SERVER");
  122. continue;
  123. case CNSS_DAEMON_CONNECTED:
  124. seq_puts(s, "DAEMON_CONNECTED");
  125. continue;
  126. case CNSS_PCI_PROBE_DONE:
  127. seq_puts(s, "PCI PROBE DONE");
  128. continue;
  129. case CNSS_DRIVER_REGISTER:
  130. seq_puts(s, "DRIVER REGISTERED");
  131. continue;
  132. case CNSS_WLAN_HW_DISABLED:
  133. seq_puts(s, "WLAN HW DISABLED");
  134. continue;
  135. case CNSS_FS_READY:
  136. seq_puts(s, "FS READY");
  137. continue;
  138. case CNSS_DRIVER_REGISTERED:
  139. seq_puts(s, "DRIVER REGISTERED");
  140. continue;
  141. }
  142. seq_printf(s, "UNKNOWN-%d", i);
  143. }
  144. seq_puts(s, ")\n");
  145. return 0;
  146. }
  147. static int cnss_stats_show_gpio_state(struct seq_file *s,
  148. struct cnss_plat_data *plat_priv)
  149. {
  150. seq_printf(s, "\nHost SOL: %d", cnss_get_host_sol_value(plat_priv));
  151. seq_printf(s, "\nDev SOL: %d", cnss_get_dev_sol_value(plat_priv));
  152. return 0;
  153. }
  154. static int cnss_stats_show(struct seq_file *s, void *data)
  155. {
  156. struct cnss_plat_data *plat_priv = s->private;
  157. cnss_stats_show_state(s, plat_priv);
  158. cnss_stats_show_gpio_state(s, plat_priv);
  159. return 0;
  160. }
  161. static int cnss_stats_open(struct inode *inode, struct file *file)
  162. {
  163. return single_open(file, cnss_stats_show, inode->i_private);
  164. }
  165. static const struct file_operations cnss_stats_fops = {
  166. .read = seq_read,
  167. .release = single_release,
  168. .open = cnss_stats_open,
  169. .owner = THIS_MODULE,
  170. .llseek = seq_lseek,
  171. };
  172. static ssize_t cnss_dev_boot_debug_write(struct file *fp,
  173. const char __user *user_buf,
  174. size_t count, loff_t *off)
  175. {
  176. struct cnss_plat_data *plat_priv =
  177. ((struct seq_file *)fp->private_data)->private;
  178. struct cnss_pci_data *pci_priv;
  179. char buf[64];
  180. char *cmd;
  181. unsigned int len = 0;
  182. char *sptr, *token;
  183. const char *delim = " ";
  184. int ret = 0;
  185. if (!plat_priv)
  186. return -ENODEV;
  187. len = min(count, sizeof(buf) - 1);
  188. if (copy_from_user(buf, user_buf, len))
  189. return -EFAULT;
  190. buf[len] = '\0';
  191. sptr = buf;
  192. token = strsep(&sptr, delim);
  193. if (!token)
  194. return -EINVAL;
  195. cmd = token;
  196. cnss_pr_dbg("Received dev_boot debug command: %s\n", cmd);
  197. if (sysfs_streq(cmd, "on")) {
  198. ret = cnss_power_on_device(plat_priv, false);
  199. } else if (sysfs_streq(cmd, "off")) {
  200. cnss_power_off_device(plat_priv);
  201. } else if (sysfs_streq(cmd, "enumerate")) {
  202. ret = cnss_pci_init(plat_priv);
  203. } else if (sysfs_streq(cmd, "powerup")) {
  204. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  205. ret = cnss_driver_event_post(plat_priv,
  206. CNSS_DRIVER_EVENT_POWER_UP,
  207. CNSS_EVENT_SYNC, NULL);
  208. } else if (sysfs_streq(cmd, "shutdown")) {
  209. ret = cnss_driver_event_post(plat_priv,
  210. CNSS_DRIVER_EVENT_POWER_DOWN,
  211. 0, NULL);
  212. clear_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  213. } else if (sysfs_streq(cmd, "assert_host_sol")) {
  214. ret = cnss_set_host_sol_value(plat_priv, 1);
  215. } else if (sysfs_streq(cmd, "deassert_host_sol")) {
  216. ret = cnss_set_host_sol_value(plat_priv, 0);
  217. } else if (sysfs_streq(cmd, "pdc_update")) {
  218. if (!sptr)
  219. return -EINVAL;
  220. ret = cnss_aop_send_msg(plat_priv, sptr);
  221. } else if (sysfs_streq(cmd, "dev_check")) {
  222. cnss_wlan_hw_disable_check(plat_priv);
  223. } else if (sysfs_streq(cmd, "dev_enable")) {
  224. cnss_wlan_hw_enable();
  225. } else {
  226. pci_priv = plat_priv->bus_priv;
  227. if (!pci_priv)
  228. return -ENODEV;
  229. if (sysfs_streq(cmd, "download")) {
  230. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  231. ret = cnss_pci_start_mhi(pci_priv);
  232. } else if (sysfs_streq(cmd, "linkup")) {
  233. ret = cnss_resume_pci_link(pci_priv);
  234. } else if (sysfs_streq(cmd, "linkdown")) {
  235. ret = cnss_suspend_pci_link(pci_priv);
  236. } else if (sysfs_streq(cmd, "assert")) {
  237. cnss_pr_info("FW Assert triggered for debug\n");
  238. ret = cnss_force_fw_assert(&pci_priv->pci_dev->dev);
  239. } else if (sysfs_streq(cmd, "set_cbc_done")) {
  240. cnss_pr_dbg("Force set cold boot cal done status\n");
  241. set_bit(CNSS_COLD_BOOT_CAL_DONE,
  242. &plat_priv->driver_state);
  243. } else {
  244. cnss_pr_err("Device boot debugfs command is invalid\n");
  245. ret = -EINVAL;
  246. }
  247. }
  248. if (ret < 0)
  249. return ret;
  250. return count;
  251. }
  252. static int cnss_dev_boot_debug_show(struct seq_file *s, void *data)
  253. {
  254. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/dev_boot\n");
  255. seq_puts(s, "<action> can be one of below:\n");
  256. seq_puts(s, "on: turn on device power, assert WLAN_EN\n");
  257. seq_puts(s, "off: de-assert WLAN_EN, turn off device power\n");
  258. seq_puts(s, "enumerate: de-assert PERST, enumerate PCIe\n");
  259. seq_puts(s, "download: download FW and do QMI handshake with FW\n");
  260. seq_puts(s, "linkup: bring up PCIe link\n");
  261. seq_puts(s, "linkdown: bring down PCIe link\n");
  262. seq_puts(s, "powerup: full power on sequence to boot device, download FW and do QMI handshake with FW\n");
  263. seq_puts(s, "shutdown: full power off sequence to shutdown device\n");
  264. seq_puts(s, "assert: trigger firmware assert\n");
  265. seq_puts(s, "set_cbc_done: Set cold boot calibration done status\n");
  266. seq_puts(s, "\npdc_update usage:");
  267. seq_puts(s, "1. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: <vreg>.<mode>, <seq>: <val>} > <debugfs_path>/cnss/dev_boot\n");
  268. seq_puts(s, "2. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: pdc, enable: <val>} > <debugfs_path>/cnss/dev_boot\n");
  269. return 0;
  270. }
  271. static int cnss_dev_boot_debug_open(struct inode *inode, struct file *file)
  272. {
  273. return single_open(file, cnss_dev_boot_debug_show, inode->i_private);
  274. }
  275. static const struct file_operations cnss_dev_boot_debug_fops = {
  276. .read = seq_read,
  277. .write = cnss_dev_boot_debug_write,
  278. .release = single_release,
  279. .open = cnss_dev_boot_debug_open,
  280. .owner = THIS_MODULE,
  281. .llseek = seq_lseek,
  282. };
  283. static int cnss_reg_read_debug_show(struct seq_file *s, void *data)
  284. {
  285. struct cnss_plat_data *plat_priv = s->private;
  286. mutex_lock(&plat_priv->dev_lock);
  287. if (!plat_priv->diag_reg_read_buf) {
  288. seq_puts(s, "\nUsage: echo <mem_type> <offset> <data_len> > <debugfs_path>/cnss/reg_read\n");
  289. seq_puts(s, "Use mem_type = 0xff for register read by IO access, data_len will be ignored\n");
  290. seq_puts(s, "Use mem_type = 0xfe for register read by raw IO access which skips sanity checks, data_len will be ignored\n");
  291. seq_puts(s, "Use other mem_type for register read by QMI\n");
  292. mutex_unlock(&plat_priv->dev_lock);
  293. return 0;
  294. }
  295. seq_printf(s, "\nRegister read, address: 0x%x memory type: 0x%x length: 0x%x\n\n",
  296. plat_priv->diag_reg_read_addr,
  297. plat_priv->diag_reg_read_mem_type,
  298. plat_priv->diag_reg_read_len);
  299. seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 32, 4,
  300. plat_priv->diag_reg_read_buf,
  301. plat_priv->diag_reg_read_len, false);
  302. plat_priv->diag_reg_read_len = 0;
  303. kfree(plat_priv->diag_reg_read_buf);
  304. plat_priv->diag_reg_read_buf = NULL;
  305. mutex_unlock(&plat_priv->dev_lock);
  306. return 0;
  307. }
  308. static ssize_t cnss_reg_read_debug_write(struct file *fp,
  309. const char __user *user_buf,
  310. size_t count, loff_t *off)
  311. {
  312. struct cnss_plat_data *plat_priv =
  313. ((struct seq_file *)fp->private_data)->private;
  314. char buf[64];
  315. char *sptr, *token;
  316. unsigned int len = 0;
  317. u32 reg_offset, mem_type;
  318. u32 data_len = 0, reg_val = 0;
  319. u8 *reg_buf = NULL;
  320. const char *delim = " ";
  321. int ret = 0;
  322. len = min(count, sizeof(buf) - 1);
  323. if (copy_from_user(buf, user_buf, len))
  324. return -EFAULT;
  325. buf[len] = '\0';
  326. sptr = buf;
  327. token = strsep(&sptr, delim);
  328. if (!token)
  329. return -EINVAL;
  330. if (!sptr)
  331. return -EINVAL;
  332. if (kstrtou32(token, 0, &mem_type))
  333. return -EINVAL;
  334. token = strsep(&sptr, delim);
  335. if (!token)
  336. return -EINVAL;
  337. if (!sptr)
  338. return -EINVAL;
  339. if (kstrtou32(token, 0, &reg_offset))
  340. return -EINVAL;
  341. token = strsep(&sptr, delim);
  342. if (!token)
  343. return -EINVAL;
  344. if (kstrtou32(token, 0, &data_len))
  345. return -EINVAL;
  346. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  347. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  348. ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, &reg_val,
  349. mem_type ==
  350. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  351. if (ret)
  352. return ret;
  353. cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val,
  354. reg_offset);
  355. return count;
  356. }
  357. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  358. cnss_pr_err("Firmware is not ready yet\n");
  359. return -EINVAL;
  360. }
  361. mutex_lock(&plat_priv->dev_lock);
  362. kfree(plat_priv->diag_reg_read_buf);
  363. plat_priv->diag_reg_read_buf = NULL;
  364. reg_buf = kzalloc(data_len, GFP_KERNEL);
  365. if (!reg_buf) {
  366. mutex_unlock(&plat_priv->dev_lock);
  367. return -ENOMEM;
  368. }
  369. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, reg_offset,
  370. mem_type, data_len,
  371. reg_buf);
  372. if (ret) {
  373. kfree(reg_buf);
  374. mutex_unlock(&plat_priv->dev_lock);
  375. return ret;
  376. }
  377. plat_priv->diag_reg_read_addr = reg_offset;
  378. plat_priv->diag_reg_read_mem_type = mem_type;
  379. plat_priv->diag_reg_read_len = data_len;
  380. plat_priv->diag_reg_read_buf = reg_buf;
  381. mutex_unlock(&plat_priv->dev_lock);
  382. return count;
  383. }
  384. static int cnss_reg_read_debug_open(struct inode *inode, struct file *file)
  385. {
  386. return single_open(file, cnss_reg_read_debug_show, inode->i_private);
  387. }
  388. static const struct file_operations cnss_reg_read_debug_fops = {
  389. .read = seq_read,
  390. .write = cnss_reg_read_debug_write,
  391. .open = cnss_reg_read_debug_open,
  392. .owner = THIS_MODULE,
  393. .llseek = seq_lseek,
  394. };
  395. static int cnss_reg_write_debug_show(struct seq_file *s, void *data)
  396. {
  397. seq_puts(s, "\nUsage: echo <mem_type> <offset> <reg_val> > <debugfs_path>/cnss/reg_write\n");
  398. seq_puts(s, "Use mem_type = 0xff for register write by IO access\n");
  399. seq_puts(s, "Use mem_type = 0xfe for register write by raw IO access which skips sanity checks\n");
  400. seq_puts(s, "Use other mem_type for register write by QMI\n");
  401. return 0;
  402. }
  403. static ssize_t cnss_reg_write_debug_write(struct file *fp,
  404. const char __user *user_buf,
  405. size_t count, loff_t *off)
  406. {
  407. struct cnss_plat_data *plat_priv =
  408. ((struct seq_file *)fp->private_data)->private;
  409. char buf[64];
  410. char *sptr, *token;
  411. unsigned int len = 0;
  412. u32 reg_offset, mem_type, reg_val;
  413. const char *delim = " ";
  414. int ret = 0;
  415. len = min(count, sizeof(buf) - 1);
  416. if (copy_from_user(buf, user_buf, len))
  417. return -EFAULT;
  418. buf[len] = '\0';
  419. sptr = buf;
  420. token = strsep(&sptr, delim);
  421. if (!token)
  422. return -EINVAL;
  423. if (!sptr)
  424. return -EINVAL;
  425. if (kstrtou32(token, 0, &mem_type))
  426. return -EINVAL;
  427. token = strsep(&sptr, delim);
  428. if (!token)
  429. return -EINVAL;
  430. if (!sptr)
  431. return -EINVAL;
  432. if (kstrtou32(token, 0, &reg_offset))
  433. return -EINVAL;
  434. token = strsep(&sptr, delim);
  435. if (!token)
  436. return -EINVAL;
  437. if (kstrtou32(token, 0, &reg_val))
  438. return -EINVAL;
  439. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  440. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  441. ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val,
  442. mem_type ==
  443. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  444. if (ret)
  445. return ret;
  446. cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val,
  447. reg_offset);
  448. return count;
  449. }
  450. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  451. cnss_pr_err("Firmware is not ready yet\n");
  452. return -EINVAL;
  453. }
  454. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type,
  455. sizeof(u32),
  456. (u8 *)&reg_val);
  457. if (ret)
  458. return ret;
  459. return count;
  460. }
  461. static int cnss_reg_write_debug_open(struct inode *inode, struct file *file)
  462. {
  463. return single_open(file, cnss_reg_write_debug_show, inode->i_private);
  464. }
  465. static const struct file_operations cnss_reg_write_debug_fops = {
  466. .read = seq_read,
  467. .write = cnss_reg_write_debug_write,
  468. .open = cnss_reg_write_debug_open,
  469. .owner = THIS_MODULE,
  470. .llseek = seq_lseek,
  471. };
  472. static ssize_t cnss_runtime_pm_debug_write(struct file *fp,
  473. const char __user *user_buf,
  474. size_t count, loff_t *off)
  475. {
  476. struct cnss_plat_data *plat_priv =
  477. ((struct seq_file *)fp->private_data)->private;
  478. struct cnss_pci_data *pci_priv;
  479. char buf[64];
  480. char *cmd;
  481. unsigned int len = 0;
  482. int ret = 0;
  483. if (!plat_priv)
  484. return -ENODEV;
  485. pci_priv = plat_priv->bus_priv;
  486. if (!pci_priv)
  487. return -ENODEV;
  488. len = min(count, sizeof(buf) - 1);
  489. if (copy_from_user(buf, user_buf, len))
  490. return -EFAULT;
  491. buf[len] = '\0';
  492. cmd = buf;
  493. cnss_pr_dbg("Received runtime_pm debug command: %s\n", cmd);
  494. if (sysfs_streq(cmd, "usage_count")) {
  495. cnss_pci_pm_runtime_show_usage_count(pci_priv);
  496. } else if (sysfs_streq(cmd, "request_resume")) {
  497. ret = cnss_pci_pm_request_resume(pci_priv);
  498. } else if (sysfs_streq(cmd, "resume")) {
  499. ret = cnss_pci_pm_runtime_resume(pci_priv);
  500. } else if (sysfs_streq(cmd, "get")) {
  501. ret = cnss_pci_pm_runtime_get(pci_priv, RTPM_ID_CNSS);
  502. } else if (sysfs_streq(cmd, "get_noresume")) {
  503. cnss_pci_pm_runtime_get_noresume(pci_priv, RTPM_ID_CNSS);
  504. } else if (sysfs_streq(cmd, "put_autosuspend")) {
  505. ret = cnss_pci_pm_runtime_put_autosuspend(pci_priv,
  506. RTPM_ID_CNSS);
  507. } else if (sysfs_streq(cmd, "put_noidle")) {
  508. cnss_pci_pm_runtime_put_noidle(pci_priv, RTPM_ID_CNSS);
  509. } else if (sysfs_streq(cmd, "mark_last_busy")) {
  510. cnss_pci_pm_runtime_mark_last_busy(pci_priv);
  511. } else if (sysfs_streq(cmd, "resume_bus")) {
  512. cnss_pci_resume_bus(pci_priv);
  513. } else if (sysfs_streq(cmd, "suspend_bus")) {
  514. cnss_pci_suspend_bus(pci_priv);
  515. } else {
  516. cnss_pr_err("Runtime PM debugfs command is invalid\n");
  517. ret = -EINVAL;
  518. }
  519. if (ret < 0)
  520. return ret;
  521. return count;
  522. }
  523. static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data)
  524. {
  525. struct cnss_plat_data *plat_priv = s->private;
  526. struct cnss_pci_data *pci_priv;
  527. int i;
  528. if (!plat_priv)
  529. return -ENODEV;
  530. pci_priv = plat_priv->bus_priv;
  531. if (!pci_priv)
  532. return -ENODEV;
  533. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/runtime_pm\n");
  534. seq_puts(s, "<action> can be one of below:\n");
  535. seq_puts(s, "usage_count: get runtime PM usage count\n");
  536. seq_puts(s, "reques_resume: do async runtime PM resume\n");
  537. seq_puts(s, "resume: do sync runtime PM resume\n");
  538. seq_puts(s, "get: do runtime PM get\n");
  539. seq_puts(s, "get_noresume: do runtime PM get noresume\n");
  540. seq_puts(s, "put_noidle: do runtime PM put noidle\n");
  541. seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n");
  542. seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n");
  543. seq_puts(s, "resume_bus: do bus resume only\n");
  544. seq_puts(s, "suspend_bus: do bus suspend only\n");
  545. seq_puts(s, "\nStats:\n");
  546. seq_printf(s, "%s: %u\n", "get count",
  547. atomic_read(&pci_priv->pm_stats.runtime_get));
  548. seq_printf(s, "%s: %u\n", "put count",
  549. atomic_read(&pci_priv->pm_stats.runtime_put));
  550. seq_printf(s, "%-10s%-10s%-10s%-15s%-15s\n",
  551. "id:", "get", "put", "get time(us)", "put time(us)");
  552. for (i = 0; i < RTPM_ID_MAX; i++) {
  553. seq_printf(s, "%d%-9s", i, ":");
  554. seq_printf(s, "%-10d",
  555. atomic_read(&pci_priv->pm_stats.runtime_get_id[i]));
  556. seq_printf(s, "%-10d",
  557. atomic_read(&pci_priv->pm_stats.runtime_put_id[i]));
  558. seq_printf(s, "%-15llu",
  559. pci_priv->pm_stats.runtime_get_timestamp_id[i]);
  560. seq_printf(s, "%-15llu\n",
  561. pci_priv->pm_stats.runtime_put_timestamp_id[i]);
  562. }
  563. return 0;
  564. }
  565. static int cnss_runtime_pm_debug_open(struct inode *inode, struct file *file)
  566. {
  567. return single_open(file, cnss_runtime_pm_debug_show, inode->i_private);
  568. }
  569. static const struct file_operations cnss_runtime_pm_debug_fops = {
  570. .read = seq_read,
  571. .write = cnss_runtime_pm_debug_write,
  572. .open = cnss_runtime_pm_debug_open,
  573. .owner = THIS_MODULE,
  574. .llseek = seq_lseek,
  575. };
  576. static int process_drv(struct cnss_plat_data *plat_priv, bool enabled)
  577. {
  578. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  579. cnss_pr_err("DRV cmd must be used before QMI ready\n");
  580. return -EINVAL;
  581. }
  582. enabled ? cnss_set_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01) :
  583. cnss_clear_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01);
  584. cnss_pr_info("%s DRV suspend\n", enabled ? "enable" : "disable");
  585. return 0;
  586. }
  587. static int process_quirks(struct cnss_plat_data *plat_priv, u32 val)
  588. {
  589. enum cnss_debug_quirks i;
  590. int ret = 0;
  591. unsigned long state;
  592. unsigned long quirks = 0;
  593. for (i = 0, state = val; i < QUIRK_MAX_VALUE; state >>= 1, i++) {
  594. switch (i) {
  595. case DISABLE_DRV:
  596. ret = process_drv(plat_priv, !(state & 0x1));
  597. if (!ret)
  598. quirks |= (state & 0x1) << i;
  599. continue;
  600. default:
  601. quirks |= (state & 0x1) << i;
  602. continue;
  603. }
  604. }
  605. plat_priv->ctrl_params.quirks = quirks;
  606. return 0;
  607. }
  608. static ssize_t cnss_control_params_debug_write(struct file *fp,
  609. const char __user *user_buf,
  610. size_t count, loff_t *off)
  611. {
  612. struct cnss_plat_data *plat_priv =
  613. ((struct seq_file *)fp->private_data)->private;
  614. char buf[64];
  615. char *sptr, *token;
  616. char *cmd;
  617. u32 val;
  618. unsigned int len = 0;
  619. const char *delim = " ";
  620. if (!plat_priv)
  621. return -ENODEV;
  622. len = min(count, sizeof(buf) - 1);
  623. if (copy_from_user(buf, user_buf, len))
  624. return -EFAULT;
  625. buf[len] = '\0';
  626. sptr = buf;
  627. token = strsep(&sptr, delim);
  628. if (!token)
  629. return -EINVAL;
  630. if (!sptr)
  631. return -EINVAL;
  632. cmd = token;
  633. token = strsep(&sptr, delim);
  634. if (!token)
  635. return -EINVAL;
  636. if (kstrtou32(token, 0, &val))
  637. return -EINVAL;
  638. if (strcmp(cmd, "quirks") == 0)
  639. process_quirks(plat_priv, val);
  640. else if (strcmp(cmd, "mhi_timeout") == 0)
  641. plat_priv->ctrl_params.mhi_timeout = val;
  642. else if (strcmp(cmd, "mhi_m2_timeout") == 0)
  643. plat_priv->ctrl_params.mhi_m2_timeout = val;
  644. else if (strcmp(cmd, "qmi_timeout") == 0)
  645. plat_priv->ctrl_params.qmi_timeout = val;
  646. else if (strcmp(cmd, "bdf_type") == 0)
  647. plat_priv->ctrl_params.bdf_type = val;
  648. else if (strcmp(cmd, "time_sync_period") == 0)
  649. plat_priv->ctrl_params.time_sync_period = val;
  650. else
  651. return -EINVAL;
  652. return count;
  653. }
  654. static int cnss_show_quirks_state(struct seq_file *s,
  655. struct cnss_plat_data *plat_priv)
  656. {
  657. enum cnss_debug_quirks i;
  658. int skip = 0;
  659. unsigned long state;
  660. seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks);
  661. for (i = 0, state = plat_priv->ctrl_params.quirks;
  662. state != 0; state >>= 1, i++) {
  663. if (!(state & 0x1))
  664. continue;
  665. if (skip++)
  666. seq_puts(s, " | ");
  667. switch (i) {
  668. case LINK_DOWN_SELF_RECOVERY:
  669. seq_puts(s, "LINK_DOWN_SELF_RECOVERY");
  670. continue;
  671. case SKIP_DEVICE_BOOT:
  672. seq_puts(s, "SKIP_DEVICE_BOOT");
  673. continue;
  674. case USE_CORE_ONLY_FW:
  675. seq_puts(s, "USE_CORE_ONLY_FW");
  676. continue;
  677. case SKIP_RECOVERY:
  678. seq_puts(s, "SKIP_RECOVERY");
  679. continue;
  680. case QMI_BYPASS:
  681. seq_puts(s, "QMI_BYPASS");
  682. continue;
  683. case ENABLE_WALTEST:
  684. seq_puts(s, "WALTEST");
  685. continue;
  686. case ENABLE_PCI_LINK_DOWN_PANIC:
  687. seq_puts(s, "PCI_LINK_DOWN_PANIC");
  688. continue;
  689. case FBC_BYPASS:
  690. seq_puts(s, "FBC_BYPASS");
  691. continue;
  692. case ENABLE_DAEMON_SUPPORT:
  693. seq_puts(s, "DAEMON_SUPPORT");
  694. continue;
  695. case DISABLE_DRV:
  696. seq_puts(s, "DISABLE_DRV");
  697. continue;
  698. case DISABLE_IO_COHERENCY:
  699. seq_puts(s, "DISABLE_IO_COHERENCY");
  700. continue;
  701. case IGNORE_PCI_LINK_FAILURE:
  702. seq_puts(s, "IGNORE_PCI_LINK_FAILURE");
  703. continue;
  704. case DISABLE_TIME_SYNC:
  705. seq_puts(s, "DISABLE_TIME_SYNC");
  706. continue;
  707. case FORCE_ONE_MSI:
  708. seq_puts(s, "FORCE_ONE_MSI");
  709. continue;
  710. default:
  711. continue;
  712. }
  713. }
  714. seq_puts(s, ")\n");
  715. return 0;
  716. }
  717. static int cnss_control_params_debug_show(struct seq_file *s, void *data)
  718. {
  719. struct cnss_plat_data *cnss_priv = s->private;
  720. seq_puts(s, "\nUsage: echo <params_name> <value> > <debugfs_path>/cnss/control_params\n");
  721. seq_puts(s, "<params_name> can be one of below:\n");
  722. seq_puts(s, "quirks: Debug quirks for driver\n");
  723. seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n");
  724. seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n");
  725. seq_puts(s, "bdf_type: Type of board data file to be downloaded\n");
  726. seq_puts(s, "time_sync_period: Time period to do time sync with device in milliseconds\n");
  727. seq_puts(s, "\nCurrent value:\n");
  728. cnss_show_quirks_state(s, cnss_priv);
  729. seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
  730. seq_printf(s, "mhi_m2_timeout: %u\n",
  731. cnss_priv->ctrl_params.mhi_m2_timeout);
  732. seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
  733. seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
  734. seq_printf(s, "time_sync_period: %u\n",
  735. cnss_priv->ctrl_params.time_sync_period);
  736. return 0;
  737. }
  738. static int cnss_control_params_debug_open(struct inode *inode,
  739. struct file *file)
  740. {
  741. return single_open(file, cnss_control_params_debug_show,
  742. inode->i_private);
  743. }
  744. static const struct file_operations cnss_control_params_debug_fops = {
  745. .read = seq_read,
  746. .write = cnss_control_params_debug_write,
  747. .open = cnss_control_params_debug_open,
  748. .owner = THIS_MODULE,
  749. .llseek = seq_lseek,
  750. };
  751. static ssize_t cnss_dynamic_feature_write(struct file *fp,
  752. const char __user *user_buf,
  753. size_t count, loff_t *off)
  754. {
  755. struct cnss_plat_data *plat_priv =
  756. ((struct seq_file *)fp->private_data)->private;
  757. int ret = 0;
  758. u64 val;
  759. ret = kstrtou64_from_user(user_buf, count, 0, &val);
  760. if (ret)
  761. return ret;
  762. plat_priv->dynamic_feature = val;
  763. ret = cnss_wlfw_dynamic_feature_mask_send_sync(plat_priv);
  764. if (ret < 0)
  765. return ret;
  766. return count;
  767. }
  768. static int cnss_dynamic_feature_show(struct seq_file *s, void *data)
  769. {
  770. struct cnss_plat_data *cnss_priv = s->private;
  771. seq_printf(s, "dynamic_feature: 0x%llx\n", cnss_priv->dynamic_feature);
  772. return 0;
  773. }
  774. static int cnss_dynamic_feature_open(struct inode *inode,
  775. struct file *file)
  776. {
  777. return single_open(file, cnss_dynamic_feature_show,
  778. inode->i_private);
  779. }
  780. static const struct file_operations cnss_dynamic_feature_fops = {
  781. .read = seq_read,
  782. .write = cnss_dynamic_feature_write,
  783. .open = cnss_dynamic_feature_open,
  784. .owner = THIS_MODULE,
  785. .llseek = seq_lseek,
  786. };
  787. static int cnss_smmu_fault_timestamp_show(struct seq_file *s, void *data)
  788. {
  789. struct cnss_plat_data *plat_priv = s->private;
  790. struct cnss_pci_data *pci_priv = plat_priv->bus_priv;
  791. if (!pci_priv)
  792. return -ENODEV;
  793. seq_printf(s, "smmu irq cb entry timestamp : %llu ns\n",
  794. pci_priv->smmu_fault_timestamp[SMMU_CB_ENTRY]);
  795. seq_printf(s, "smmu irq cb before doorbell ring timestamp : %llu ns\n",
  796. pci_priv->smmu_fault_timestamp[SMMU_CB_DOORBELL_RING]);
  797. seq_printf(s, "smmu irq cb after doorbell ring timestamp : %llu ns\n",
  798. pci_priv->smmu_fault_timestamp[SMMU_CB_EXIT]);
  799. return 0;
  800. }
  801. static int cnss_smmu_fault_timestamp_open(struct inode *inode,
  802. struct file *file)
  803. {
  804. return single_open(file, cnss_smmu_fault_timestamp_show,
  805. inode->i_private);
  806. }
  807. static const struct file_operations cnss_smmu_fault_timestamp_fops = {
  808. .read = seq_read,
  809. .release = single_release,
  810. .open = cnss_smmu_fault_timestamp_open,
  811. .owner = THIS_MODULE,
  812. .llseek = seq_lseek,
  813. };
  814. #ifdef CONFIG_DEBUG_FS
  815. #ifdef CONFIG_CNSS2_DEBUG
  816. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  817. {
  818. struct dentry *root_dentry = plat_priv->root_dentry;
  819. debugfs_create_file("dev_boot", 0600, root_dentry, plat_priv,
  820. &cnss_dev_boot_debug_fops);
  821. debugfs_create_file("reg_read", 0600, root_dentry, plat_priv,
  822. &cnss_reg_read_debug_fops);
  823. debugfs_create_file("reg_write", 0600, root_dentry, plat_priv,
  824. &cnss_reg_write_debug_fops);
  825. debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv,
  826. &cnss_runtime_pm_debug_fops);
  827. debugfs_create_file("control_params", 0600, root_dentry, plat_priv,
  828. &cnss_control_params_debug_fops);
  829. debugfs_create_file("dynamic_feature", 0600, root_dentry, plat_priv,
  830. &cnss_dynamic_feature_fops);
  831. debugfs_create_file("cnss_smmu_fault_timestamp", 0600, root_dentry,
  832. plat_priv, &cnss_smmu_fault_timestamp_fops);
  833. return 0;
  834. }
  835. #else
  836. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  837. {
  838. return 0;
  839. }
  840. #endif
  841. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  842. {
  843. int ret = 0;
  844. struct dentry *root_dentry;
  845. char name[CNSS_FS_NAME_SIZE];
  846. if (cnss_is_dual_wlan_enabled())
  847. snprintf(name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME "_%d",
  848. plat_priv->plat_idx);
  849. else
  850. snprintf(name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  851. root_dentry = debugfs_create_dir(name, 0);
  852. if (IS_ERR(root_dentry)) {
  853. ret = PTR_ERR(root_dentry);
  854. cnss_pr_err("Unable to create debugfs %d\n", ret);
  855. goto out;
  856. }
  857. plat_priv->root_dentry = root_dentry;
  858. debugfs_create_file("pin_connect_result", 0644, root_dentry, plat_priv,
  859. &cnss_pin_connect_fops);
  860. debugfs_create_file("stats", 0644, root_dentry, plat_priv,
  861. &cnss_stats_fops);
  862. cnss_create_debug_only_node(plat_priv);
  863. out:
  864. return ret;
  865. }
  866. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  867. {
  868. debugfs_remove_recursive(plat_priv->root_dentry);
  869. }
  870. #else
  871. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  872. {
  873. plat_priv->root_dentry = NULL;
  874. return 0;
  875. }
  876. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  877. {
  878. }
  879. #endif
  880. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  881. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  882. const char *log_level, char *fmt, ...)
  883. {
  884. struct va_format vaf;
  885. va_list va_args;
  886. va_start(va_args, fmt);
  887. vaf.fmt = fmt;
  888. vaf.va = &va_args;
  889. if (log_level)
  890. printk("%scnss: %pV", log_level, &vaf);
  891. ipc_log_string(log_ctx, "[%s] %s: %pV", process, fn, &vaf);
  892. va_end(va_args);
  893. }
  894. static int cnss_ipc_logging_init(void)
  895. {
  896. cnss_ipc_log_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  897. "cnss", 0);
  898. if (!cnss_ipc_log_context) {
  899. cnss_pr_err("Unable to create IPC log context\n");
  900. return -EINVAL;
  901. }
  902. cnss_ipc_log_long_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  903. "cnss-long", 0);
  904. if (!cnss_ipc_log_long_context) {
  905. cnss_pr_err("Unable to create IPC long log context\n");
  906. ipc_log_context_destroy(cnss_ipc_log_context);
  907. return -EINVAL;
  908. }
  909. return 0;
  910. }
  911. static void cnss_ipc_logging_deinit(void)
  912. {
  913. if (cnss_ipc_log_long_context) {
  914. ipc_log_context_destroy(cnss_ipc_log_long_context);
  915. cnss_ipc_log_long_context = NULL;
  916. }
  917. if (cnss_ipc_log_context) {
  918. ipc_log_context_destroy(cnss_ipc_log_context);
  919. cnss_ipc_log_context = NULL;
  920. }
  921. }
  922. #else
  923. static int cnss_ipc_logging_init(void) { return 0; }
  924. static void cnss_ipc_logging_deinit(void) {}
  925. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  926. const char *log_level, char *fmt, ...)
  927. {
  928. struct va_format vaf;
  929. va_list va_args;
  930. va_start(va_args, fmt);
  931. vaf.fmt = fmt;
  932. vaf.va = &va_args;
  933. if (log_level)
  934. printk("%scnss: %pV", log_level, &vaf);
  935. va_end(va_args);
  936. }
  937. #endif
  938. int cnss_debug_init(void)
  939. {
  940. return cnss_ipc_logging_init();
  941. }
  942. void cnss_debug_deinit(void)
  943. {
  944. cnss_ipc_logging_deinit();
  945. }