wcd937x.c 103 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/regmap.h>
  14. #include <linux/pm_runtime.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include <soc/soundwire.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <asoc/wcdcal-hwdep.h>
  21. #include <asoc/msm-cdc-pinctrl.h>
  22. #include <bindings/audio-codec-port-types.h>
  23. #include <asoc/msm-cdc-supply.h>
  24. #include <linux/qti-regmap-debugfs.h>
  25. #include "wcd937x-registers.h"
  26. #include "wcd937x.h"
  27. #include "internal.h"
  28. #include "asoc/bolero-slave-internal.h"
  29. #define WCD9370_VARIANT 0
  30. #define WCD9375_VARIANT 5
  31. #define WCD937X_VARIANT_ENTRY_SIZE 32
  32. #define NUM_SWRS_DT_PARAMS 5
  33. #define WCD937X_VERSION_1_0 1
  34. #define WCD937X_VERSION_ENTRY_SIZE 32
  35. #define EAR_RX_PATH_AUX 1
  36. #define NUM_ATTEMPTS 5
  37. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  38. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  39. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  40. SNDRV_PCM_RATE_384000)
  41. /* Fractional Rates */
  42. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  43. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  44. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  45. SNDRV_PCM_FMTBIT_S24_LE |\
  46. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  47. enum {
  48. CODEC_TX = 0,
  49. CODEC_RX,
  50. };
  51. enum {
  52. ALLOW_BUCK_DISABLE,
  53. HPH_COMP_DELAY,
  54. HPH_PA_DELAY,
  55. AMIC2_BCS_ENABLE,
  56. };
  57. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  58. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  59. static int wcd937x_handle_post_irq(void *data);
  60. static int wcd937x_reset(struct device *dev);
  61. static int wcd937x_reset_low(struct device *dev);
  62. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  80. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  81. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  82. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  83. };
  84. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  85. .name = "wcd937x",
  86. .irqs = wcd937x_irqs,
  87. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  88. .num_regs = 3,
  89. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  90. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  91. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  92. .use_ack = 1,
  93. .clear_ack = 1,
  94. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  95. .runtime_pm = false,
  96. .handle_post_irq = wcd937x_handle_post_irq,
  97. .irq_drv_data = NULL,
  98. };
  99. static struct snd_soc_dai_driver wcd937x_dai[] = {
  100. {
  101. .name = "wcd937x_cdc",
  102. .playback = {
  103. .stream_name = "WCD937X_AIF Playback",
  104. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  105. .formats = WCD937X_FORMATS,
  106. .rate_max = 384000,
  107. .rate_min = 8000,
  108. .channels_min = 1,
  109. .channels_max = 4,
  110. },
  111. .capture = {
  112. .stream_name = "WCD937X_AIF Capture",
  113. .rates = WCD937X_RATES,
  114. .formats = WCD937X_FORMATS,
  115. .rate_max = 192000,
  116. .rate_min = 8000,
  117. .channels_min = 1,
  118. .channels_max = 4,
  119. },
  120. },
  121. };
  122. static int wcd937x_handle_post_irq(void *data)
  123. {
  124. struct wcd937x_priv *wcd937x = data;
  125. u32 status1 = 0, status2 = 0, status3 = 0;
  126. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  127. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  128. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  129. wcd937x->tx_swr_dev->slave_irq_pending =
  130. ((status1 || status2 || status3) ? true : false);
  131. return IRQ_HANDLED;
  132. }
  133. static int wcd937x_init_reg(struct snd_soc_component *component)
  134. {
  135. u32 val = 0;
  136. val = snd_soc_component_read(component, WCD937X_DIGITAL_EFUSE_REG_29)
  137. & 0x0F;
  138. if (snd_soc_component_read(component, WCD937X_DIGITAL_EFUSE_REG_16)
  139. == 0x02 || snd_soc_component_read(component,
  140. WCD937X_DIGITAL_EFUSE_REG_17) > 0x09) {
  141. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  142. 0x0E, val);
  143. } else {
  144. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  145. 0x0E, 0x0E);
  146. }
  147. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  148. 0x80, 0x80);
  149. usleep_range(1000, 1010);
  150. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  151. 0x40, 0x40);
  152. usleep_range(1000, 1010);
  153. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  154. 0x10, 0x00);
  155. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  156. 0xF0, 0x80);
  157. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  158. 0x80, 0x80);
  159. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  160. 0x40, 0x40);
  161. usleep_range(10000, 10010);
  162. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  163. 0x40, 0x00);
  164. snd_soc_component_update_bits(component,
  165. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  166. 0xFF, 0xD9);
  167. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  168. 0xFF, 0xFA);
  169. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  170. 0xFF, 0xFA);
  171. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  172. 0xFF, 0xFA);
  173. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_2,
  174. 0x38, 0x00);
  175. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_2,
  176. 0x38, 0x00);
  177. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_2,
  178. 0x38, 0x00);
  179. /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */
  180. if (snd_soc_component_read(component, WCD937X_DIGITAL_EFUSE_REG_16)
  181. == 0x01) {
  182. snd_soc_component_update_bits(component,
  183. WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0);
  184. } else if (snd_soc_component_read(component,
  185. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) {
  186. snd_soc_component_update_bits(component,
  187. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04);
  188. snd_soc_component_update_bits(component,
  189. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04);
  190. snd_soc_component_update_bits(component,
  191. WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0);
  192. snd_soc_component_update_bits(component,
  193. WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50);
  194. }
  195. return 0;
  196. }
  197. static int wcd937x_set_port_params(struct snd_soc_component *component,
  198. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  199. u8 *ch_mask, u32 *ch_rate,
  200. u8 *port_type, u8 path)
  201. {
  202. int i, j;
  203. u8 num_ports = 0;
  204. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  205. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  206. switch (path) {
  207. case CODEC_RX:
  208. map = &wcd937x->rx_port_mapping;
  209. num_ports = wcd937x->num_rx_ports;
  210. break;
  211. case CODEC_TX:
  212. map = &wcd937x->tx_port_mapping;
  213. num_ports = wcd937x->num_tx_ports;
  214. break;
  215. default:
  216. dev_err(component->dev, "%s Invalid path selected %u\n",
  217. __func__, path);
  218. return -EINVAL;
  219. }
  220. for (i = 0; i <= num_ports; i++) {
  221. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  222. if ((*map)[i][j].slave_port_type == slv_prt_type)
  223. goto found;
  224. }
  225. }
  226. found:
  227. if (i > num_ports || j == MAX_CH_PER_PORT) {
  228. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  229. __func__, slv_prt_type);
  230. return -EINVAL;
  231. }
  232. *port_id = i;
  233. *num_ch = (*map)[i][j].num_ch;
  234. *ch_mask = (*map)[i][j].ch_mask;
  235. *ch_rate = (*map)[i][j].ch_rate;
  236. *port_type = (*map)[i][j].master_port_type;
  237. return 0;
  238. }
  239. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  240. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  241. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  242. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  243. static int wcd937x_parse_port_params(struct device *dev,
  244. char *prop, u8 path)
  245. {
  246. u32 *dt_array, map_size, max_uc;
  247. int ret = 0;
  248. u32 cnt = 0;
  249. u32 i, j;
  250. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  251. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  252. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  253. switch (path) {
  254. case CODEC_TX:
  255. map = &wcd937x->tx_port_params;
  256. map_uc = &wcd937x->swr_tx_port_params;
  257. break;
  258. default:
  259. ret = -EINVAL;
  260. goto err_port_map;
  261. }
  262. if (!of_find_property(dev->of_node, prop,
  263. &map_size)) {
  264. dev_err(dev, "missing port mapping prop %s\n", prop);
  265. ret = -EINVAL;
  266. goto err_port_map;
  267. }
  268. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  269. if (max_uc != SWR_UC_MAX) {
  270. dev_err(dev, "%s: port params not provided for all usecases\n",
  271. __func__);
  272. ret = -EINVAL;
  273. goto err_port_map;
  274. }
  275. dt_array = kzalloc(map_size, GFP_KERNEL);
  276. if (!dt_array) {
  277. ret = -ENOMEM;
  278. goto err_alloc;
  279. }
  280. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  281. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  282. if (ret) {
  283. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  284. __func__, prop);
  285. goto err_pdata_fail;
  286. }
  287. for (i = 0; i < max_uc; i++) {
  288. for (j = 0; j < SWR_NUM_PORTS; j++) {
  289. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  290. (*map)[i][j].offset1 = dt_array[cnt];
  291. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  292. }
  293. (*map_uc)[i].pp = &(*map)[i][0];
  294. }
  295. kfree(dt_array);
  296. return 0;
  297. err_pdata_fail:
  298. kfree(dt_array);
  299. err_alloc:
  300. err_port_map:
  301. return ret;
  302. }
  303. static int wcd937x_parse_port_mapping(struct device *dev,
  304. char *prop, u8 path)
  305. {
  306. u32 *dt_array, map_size, map_length;
  307. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  308. u32 slave_port_type, master_port_type;
  309. u32 i, ch_iter = 0;
  310. int ret = 0;
  311. u8 *num_ports = NULL;
  312. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  313. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  314. switch (path) {
  315. case CODEC_RX:
  316. map = &wcd937x->rx_port_mapping;
  317. num_ports = &wcd937x->num_rx_ports;
  318. break;
  319. case CODEC_TX:
  320. map = &wcd937x->tx_port_mapping;
  321. num_ports = &wcd937x->num_tx_ports;
  322. break;
  323. default:
  324. dev_err(dev, "%s Invalid path selected %u\n",
  325. __func__, path);
  326. return -EINVAL;
  327. }
  328. if (!of_find_property(dev->of_node, prop,
  329. &map_size)) {
  330. dev_err(dev, "missing port mapping prop %s\n", prop);
  331. ret = -EINVAL;
  332. goto err;
  333. }
  334. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  335. dt_array = kzalloc(map_size, GFP_KERNEL);
  336. if (!dt_array) {
  337. ret = -ENOMEM;
  338. goto err;
  339. }
  340. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  341. NUM_SWRS_DT_PARAMS * map_length);
  342. if (ret) {
  343. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  344. __func__, prop);
  345. ret = -EINVAL;
  346. goto err_pdata_fail;
  347. }
  348. for (i = 0; i < map_length; i++) {
  349. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  350. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  351. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  352. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  353. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  354. if (port_num != old_port_num)
  355. ch_iter = 0;
  356. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  357. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  358. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  359. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  360. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  361. old_port_num = port_num;
  362. }
  363. *num_ports = port_num;
  364. kfree(dt_array);
  365. return 0;
  366. err_pdata_fail:
  367. kfree(dt_array);
  368. err:
  369. return ret;
  370. }
  371. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  372. u8 slv_port_type, u8 enable)
  373. {
  374. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  375. u8 port_id;
  376. u8 num_ch;
  377. u8 ch_mask;
  378. u32 ch_rate;
  379. u8 ch_type = 0;
  380. int slave_ch_idx;
  381. u8 num_port = 1;
  382. int ret = 0;
  383. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  384. &num_ch, &ch_mask, &ch_rate,
  385. &ch_type, CODEC_TX);
  386. if (ret)
  387. return ret;
  388. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  389. if (slave_ch_idx != -EINVAL)
  390. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  391. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  392. __func__, slave_ch_idx, ch_type);
  393. if (enable)
  394. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  395. num_port, &ch_mask, &ch_rate,
  396. &num_ch, &ch_type);
  397. else
  398. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  399. num_port, &ch_mask, &ch_type);
  400. return ret;
  401. }
  402. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  403. u8 slv_port_type, u8 enable)
  404. {
  405. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  406. u8 port_id;
  407. u8 num_ch;
  408. u8 ch_mask;
  409. u32 ch_rate;
  410. u8 port_type;
  411. u8 num_port = 1;
  412. int ret = 0;
  413. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  414. &num_ch, &ch_mask, &ch_rate,
  415. &port_type, CODEC_RX);
  416. if (ret)
  417. return ret;
  418. if (enable)
  419. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  420. num_port, &ch_mask, &ch_rate,
  421. &num_ch, &port_type);
  422. else
  423. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  424. num_port, &ch_mask, &port_type);
  425. return ret;
  426. }
  427. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  428. {
  429. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  430. if (wcd937x->rx_clk_cnt == 0) {
  431. snd_soc_component_update_bits(component,
  432. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  433. snd_soc_component_update_bits(component,
  434. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  435. snd_soc_component_update_bits(component,
  436. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  437. snd_soc_component_update_bits(component,
  438. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  439. snd_soc_component_update_bits(component,
  440. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  441. snd_soc_component_update_bits(component,
  442. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  443. snd_soc_component_update_bits(component,
  444. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  445. }
  446. wcd937x->rx_clk_cnt++;
  447. return 0;
  448. }
  449. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  450. {
  451. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  452. if (wcd937x->rx_clk_cnt == 0) {
  453. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  454. return 0;
  455. }
  456. wcd937x->rx_clk_cnt--;
  457. if (wcd937x->rx_clk_cnt == 0) {
  458. snd_soc_component_update_bits(component,
  459. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  460. snd_soc_component_update_bits(component,
  461. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  462. 0x02, 0x00);
  463. snd_soc_component_update_bits(component,
  464. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  465. 0x01, 0x00);
  466. }
  467. return 0;
  468. }
  469. /*
  470. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  471. * @component: handle to snd_soc_component *
  472. *
  473. * return wcd937x_mbhc handle or error code in case of failure
  474. */
  475. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  476. {
  477. struct wcd937x_priv *wcd937x;
  478. if (!component) {
  479. pr_err("%s: Invalid params, NULL component\n", __func__);
  480. return NULL;
  481. }
  482. wcd937x = snd_soc_component_get_drvdata(component);
  483. if (!wcd937x) {
  484. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  485. return NULL;
  486. }
  487. return wcd937x->mbhc;
  488. }
  489. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  490. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  491. struct snd_kcontrol *kcontrol,
  492. int event)
  493. {
  494. struct snd_soc_component *component =
  495. snd_soc_dapm_to_component(w->dapm);
  496. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  497. int hph_mode = wcd937x->hph_mode;
  498. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  499. w->name, event);
  500. switch (event) {
  501. case SND_SOC_DAPM_PRE_PMU:
  502. wcd937x_rx_clk_enable(component);
  503. snd_soc_component_update_bits(component,
  504. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  505. 0x01, 0x01);
  506. snd_soc_component_update_bits(component,
  507. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  508. 0x04, 0x04);
  509. snd_soc_component_update_bits(component,
  510. WCD937X_HPH_RDAC_CLK_CTL1,
  511. 0x80, 0x00);
  512. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  513. break;
  514. case SND_SOC_DAPM_POST_PMU:
  515. if ((snd_soc_component_read(component,
  516. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) &&
  517. ((snd_soc_component_read(component,
  518. WCD937X_ANA_HPH) & 0x0C) == 0x0C))
  519. snd_soc_component_update_bits(component,
  520. WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90);
  521. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  522. snd_soc_component_update_bits(component,
  523. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  524. 0x0F, 0x02);
  525. else if (hph_mode == CLS_H_LOHIFI)
  526. snd_soc_component_update_bits(component,
  527. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  528. 0x0F, 0x06);
  529. if (wcd937x->comp1_enable) {
  530. snd_soc_component_update_bits(component,
  531. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  532. 0x02, 0x02);
  533. snd_soc_component_update_bits(component,
  534. WCD937X_HPH_L_EN, 0x20, 0x00);
  535. if (wcd937x->comp2_enable) {
  536. snd_soc_component_update_bits(component,
  537. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  538. 0x01, 0x01);
  539. snd_soc_component_update_bits(component,
  540. WCD937X_HPH_R_EN, 0x20, 0x00);
  541. }
  542. /*
  543. * 5ms sleep is required after COMP is enabled as per
  544. * HW requirement
  545. */
  546. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  547. usleep_range(5000, 5100);
  548. clear_bit(HPH_COMP_DELAY,
  549. &wcd937x->status_mask);
  550. }
  551. } else {
  552. snd_soc_component_update_bits(component,
  553. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  554. 0x02, 0x00);
  555. snd_soc_component_update_bits(component,
  556. WCD937X_HPH_L_EN, 0x20, 0x20);
  557. }
  558. snd_soc_component_update_bits(component,
  559. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  560. break;
  561. case SND_SOC_DAPM_POST_PMD:
  562. if ((snd_soc_component_read(component,
  563. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) &&
  564. ((snd_soc_component_read(component,
  565. WCD937X_ANA_HPH) & 0x0C) == 0x0C))
  566. snd_soc_component_update_bits(component,
  567. WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80);
  568. snd_soc_component_update_bits(component,
  569. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  570. 0x0F, 0x01);
  571. break;
  572. }
  573. return 0;
  574. }
  575. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  576. struct snd_kcontrol *kcontrol,
  577. int event)
  578. {
  579. struct snd_soc_component *component =
  580. snd_soc_dapm_to_component(w->dapm);
  581. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  582. int hph_mode = wcd937x->hph_mode;
  583. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  584. w->name, event);
  585. switch (event) {
  586. case SND_SOC_DAPM_PRE_PMU:
  587. wcd937x_rx_clk_enable(component);
  588. snd_soc_component_update_bits(component,
  589. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  590. snd_soc_component_update_bits(component,
  591. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  592. snd_soc_component_update_bits(component,
  593. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  594. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  595. break;
  596. case SND_SOC_DAPM_POST_PMU:
  597. if ((snd_soc_component_read(component,
  598. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) &&
  599. ((snd_soc_component_read(component,
  600. WCD937X_ANA_HPH) & 0x0C) == 0x0C))
  601. snd_soc_component_update_bits(component,
  602. WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90);
  603. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  604. snd_soc_component_update_bits(component,
  605. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  606. 0x0F, 0x02);
  607. else if (hph_mode == CLS_H_LOHIFI)
  608. snd_soc_component_update_bits(component,
  609. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  610. 0x0F, 0x06);
  611. if (wcd937x->comp2_enable) {
  612. snd_soc_component_update_bits(component,
  613. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  614. 0x01, 0x01);
  615. snd_soc_component_update_bits(component,
  616. WCD937X_HPH_R_EN, 0x20, 0x00);
  617. if (wcd937x->comp1_enable) {
  618. snd_soc_component_update_bits(component,
  619. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  620. 0x02, 0x02);
  621. snd_soc_component_update_bits(component,
  622. WCD937X_HPH_L_EN, 0x20, 0x00);
  623. }
  624. /*
  625. * 5ms sleep is required after COMP is enabled as per
  626. * HW requirement
  627. */
  628. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  629. usleep_range(5000, 5100);
  630. clear_bit(HPH_COMP_DELAY,
  631. &wcd937x->status_mask);
  632. }
  633. } else {
  634. snd_soc_component_update_bits(component,
  635. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  636. 0x01, 0x00);
  637. snd_soc_component_update_bits(component,
  638. WCD937X_HPH_R_EN, 0x20, 0x20);
  639. }
  640. snd_soc_component_update_bits(component,
  641. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  642. break;
  643. case SND_SOC_DAPM_POST_PMD:
  644. if ((snd_soc_component_read(component,
  645. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) &&
  646. ((snd_soc_component_read(component,
  647. WCD937X_ANA_HPH) & 0x0C) == 0x0C))
  648. snd_soc_component_update_bits(component,
  649. WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80);
  650. snd_soc_component_update_bits(component,
  651. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  652. 0x0F, 0x01);
  653. break;
  654. }
  655. return 0;
  656. }
  657. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  658. struct snd_kcontrol *kcontrol,
  659. int event)
  660. {
  661. struct snd_soc_component *component =
  662. snd_soc_dapm_to_component(w->dapm);
  663. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  664. int hph_mode = wcd937x->hph_mode;
  665. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  666. w->name, event);
  667. switch (event) {
  668. case SND_SOC_DAPM_PRE_PMU:
  669. wcd937x_rx_clk_enable(component);
  670. snd_soc_component_update_bits(component,
  671. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  672. 0x04, 0x04);
  673. snd_soc_component_update_bits(component,
  674. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  675. 0x01, 0x01);
  676. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  677. snd_soc_component_update_bits(component,
  678. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  679. 0x0F, 0x02);
  680. else if (hph_mode == CLS_H_LOHIFI)
  681. snd_soc_component_update_bits(component,
  682. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  683. 0x0F, 0x06);
  684. if (wcd937x->comp1_enable)
  685. snd_soc_component_update_bits(component,
  686. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  687. 0x02, 0x02);
  688. usleep_range(5000, 5010);
  689. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  690. 0x04, 0x00);
  691. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  692. WCD_CLSH_EVENT_PRE_DAC,
  693. WCD_CLSH_STATE_EAR,
  694. hph_mode);
  695. break;
  696. case SND_SOC_DAPM_POST_PMD:
  697. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  698. hph_mode == CLS_H_HIFI)
  699. snd_soc_component_update_bits(component,
  700. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  701. 0x0F, 0x01);
  702. if (wcd937x->comp1_enable)
  703. snd_soc_component_update_bits(component,
  704. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  705. 0x02, 0x00);
  706. break;
  707. };
  708. return 0;
  709. }
  710. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  711. struct snd_kcontrol *kcontrol,
  712. int event)
  713. {
  714. struct snd_soc_component *component =
  715. snd_soc_dapm_to_component(w->dapm);
  716. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  717. int hph_mode = wcd937x->hph_mode;
  718. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  719. w->name, event);
  720. switch (event) {
  721. case SND_SOC_DAPM_PRE_PMU:
  722. wcd937x_rx_clk_enable(component);
  723. snd_soc_component_update_bits(component,
  724. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  725. 0x04, 0x04);
  726. snd_soc_component_update_bits(component,
  727. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  728. 0x04, 0x04);
  729. snd_soc_component_update_bits(component,
  730. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  731. 0x01, 0x01);
  732. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  733. WCD_CLSH_EVENT_PRE_DAC,
  734. WCD_CLSH_STATE_AUX,
  735. hph_mode);
  736. break;
  737. case SND_SOC_DAPM_POST_PMD:
  738. snd_soc_component_update_bits(component,
  739. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  740. 0x04, 0x00);
  741. break;
  742. };
  743. return 0;
  744. }
  745. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  746. struct snd_kcontrol *kcontrol,
  747. int event)
  748. {
  749. struct snd_soc_component *component =
  750. snd_soc_dapm_to_component(w->dapm);
  751. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  752. int ret = 0;
  753. int hph_mode = wcd937x->hph_mode;
  754. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  755. w->name, event);
  756. switch (event) {
  757. case SND_SOC_DAPM_PRE_PMU:
  758. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  759. wcd937x->rx_swr_dev->dev_num,
  760. true);
  761. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  762. WCD_CLSH_EVENT_PRE_DAC,
  763. WCD_CLSH_STATE_HPHR,
  764. hph_mode);
  765. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  766. 0x10, 0x10);
  767. usleep_range(100, 110);
  768. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  769. snd_soc_component_update_bits(component,
  770. WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  771. break;
  772. case SND_SOC_DAPM_POST_PMU:
  773. /*
  774. * 7ms sleep is required after PA is enabled as per
  775. * HW requirement. If compander is disabled, then
  776. * 20ms delay is required.
  777. */
  778. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  779. if (!wcd937x->comp2_enable)
  780. usleep_range(20000, 20100);
  781. else
  782. usleep_range(7000, 7100);
  783. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  784. }
  785. snd_soc_component_update_bits(component,
  786. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  787. 0x02, 0x02);
  788. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  789. snd_soc_component_update_bits(component,
  790. WCD937X_ANA_RX_SUPPLIES,
  791. 0x02, 0x02);
  792. if (wcd937x->update_wcd_event)
  793. wcd937x->update_wcd_event(wcd937x->handle,
  794. SLV_BOLERO_EVT_RX_MUTE,
  795. (WCD_RX2 << 0x10));
  796. wcd_enable_irq(&wcd937x->irq_info,
  797. WCD937X_IRQ_HPHR_PDM_WD_INT);
  798. break;
  799. case SND_SOC_DAPM_PRE_PMD:
  800. wcd_disable_irq(&wcd937x->irq_info,
  801. WCD937X_IRQ_HPHR_PDM_WD_INT);
  802. if (wcd937x->update_wcd_event)
  803. wcd937x->update_wcd_event(wcd937x->handle,
  804. SLV_BOLERO_EVT_RX_MUTE,
  805. (WCD_RX2 << 0x10 | 0x1));
  806. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  807. WCD_EVENT_PRE_HPHR_PA_OFF,
  808. &wcd937x->mbhc->wcd_mbhc);
  809. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  810. break;
  811. case SND_SOC_DAPM_POST_PMD:
  812. /*
  813. * 7ms sleep is required after PA is disabled as per
  814. * HW requirement. If compander is disabled, then
  815. * 20ms delay is required.
  816. */
  817. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  818. if (!wcd937x->comp2_enable)
  819. usleep_range(20000, 20100);
  820. else
  821. usleep_range(7000, 7100);
  822. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  823. }
  824. snd_soc_component_update_bits(component,
  825. WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  826. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  827. WCD_EVENT_POST_HPHR_PA_OFF,
  828. &wcd937x->mbhc->wcd_mbhc);
  829. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  830. 0x10, 0x00);
  831. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  832. WCD_CLSH_EVENT_POST_PA,
  833. WCD_CLSH_STATE_HPHR,
  834. hph_mode);
  835. break;
  836. };
  837. return ret;
  838. }
  839. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  840. struct snd_kcontrol *kcontrol,
  841. int event)
  842. {
  843. struct snd_soc_component *component =
  844. snd_soc_dapm_to_component(w->dapm);
  845. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  846. int ret = 0;
  847. int hph_mode = wcd937x->hph_mode;
  848. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  849. w->name, event);
  850. switch (event) {
  851. case SND_SOC_DAPM_PRE_PMU:
  852. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  853. wcd937x->rx_swr_dev->dev_num,
  854. true);
  855. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  856. WCD_CLSH_EVENT_PRE_DAC,
  857. WCD_CLSH_STATE_HPHL,
  858. hph_mode);
  859. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  860. 0x20, 0x20);
  861. usleep_range(100, 110);
  862. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  863. snd_soc_component_update_bits(component,
  864. WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  865. break;
  866. case SND_SOC_DAPM_POST_PMU:
  867. /*
  868. * 7ms sleep is required after PA is enabled as per
  869. * HW requirement. If compander is disabled, then
  870. * 20ms delay is required.
  871. */
  872. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  873. if (!wcd937x->comp1_enable)
  874. usleep_range(20000, 20100);
  875. else
  876. usleep_range(7000, 7100);
  877. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  878. }
  879. snd_soc_component_update_bits(component,
  880. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  881. 0x02, 0x02);
  882. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  883. snd_soc_component_update_bits(component,
  884. WCD937X_ANA_RX_SUPPLIES,
  885. 0x02, 0x02);
  886. if (wcd937x->update_wcd_event)
  887. wcd937x->update_wcd_event(wcd937x->handle,
  888. SLV_BOLERO_EVT_RX_MUTE,
  889. (WCD_RX1 << 0x10));
  890. wcd_enable_irq(&wcd937x->irq_info,
  891. WCD937X_IRQ_HPHL_PDM_WD_INT);
  892. break;
  893. case SND_SOC_DAPM_PRE_PMD:
  894. wcd_disable_irq(&wcd937x->irq_info,
  895. WCD937X_IRQ_HPHL_PDM_WD_INT);
  896. if (wcd937x->update_wcd_event)
  897. wcd937x->update_wcd_event(wcd937x->handle,
  898. SLV_BOLERO_EVT_RX_MUTE,
  899. (WCD_RX1 << 0x10 | 0x1));
  900. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  901. WCD_EVENT_PRE_HPHL_PA_OFF,
  902. &wcd937x->mbhc->wcd_mbhc);
  903. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  904. break;
  905. case SND_SOC_DAPM_POST_PMD:
  906. /*
  907. * 7ms sleep is required after PA is disabled as per
  908. * HW requirement. If compander is disabled, then
  909. * 20ms delay is required.
  910. */
  911. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  912. if (!wcd937x->comp1_enable)
  913. usleep_range(20000, 20100);
  914. else
  915. usleep_range(7000, 7100);
  916. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  917. }
  918. snd_soc_component_update_bits(component,
  919. WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  920. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  921. WCD_EVENT_POST_HPHL_PA_OFF,
  922. &wcd937x->mbhc->wcd_mbhc);
  923. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  924. 0x20, 0x00);
  925. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  926. WCD_CLSH_EVENT_POST_PA,
  927. WCD_CLSH_STATE_HPHL,
  928. hph_mode);
  929. break;
  930. };
  931. return ret;
  932. }
  933. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  934. struct snd_kcontrol *kcontrol,
  935. int event)
  936. {
  937. struct snd_soc_component *component =
  938. snd_soc_dapm_to_component(w->dapm);
  939. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  940. int hph_mode = wcd937x->hph_mode;
  941. int ret = 0;
  942. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  943. w->name, event);
  944. switch (event) {
  945. case SND_SOC_DAPM_PRE_PMU:
  946. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  947. wcd937x->rx_swr_dev->dev_num,
  948. true);
  949. snd_soc_component_update_bits(component,
  950. WCD937X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  951. break;
  952. case SND_SOC_DAPM_POST_PMU:
  953. usleep_range(1000, 1010);
  954. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  955. snd_soc_component_update_bits(component,
  956. WCD937X_ANA_RX_SUPPLIES,
  957. 0x02, 0x02);
  958. if (wcd937x->update_wcd_event)
  959. wcd937x->update_wcd_event(wcd937x->handle,
  960. SLV_BOLERO_EVT_RX_MUTE,
  961. (WCD_RX3 << 0x10));
  962. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  963. break;
  964. case SND_SOC_DAPM_PRE_PMD:
  965. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  966. if (wcd937x->update_wcd_event)
  967. wcd937x->update_wcd_event(wcd937x->handle,
  968. SLV_BOLERO_EVT_RX_MUTE,
  969. (WCD_RX3 << 0x10 | 0x1));
  970. break;
  971. case SND_SOC_DAPM_POST_PMD:
  972. /* Add delay as per hw requirement */
  973. usleep_range(2000, 2010);
  974. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  975. WCD_CLSH_EVENT_POST_PA,
  976. WCD_CLSH_STATE_AUX,
  977. hph_mode);
  978. snd_soc_component_update_bits(component,
  979. WCD937X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  980. break;
  981. };
  982. return ret;
  983. }
  984. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  985. struct snd_kcontrol *kcontrol,
  986. int event)
  987. {
  988. struct snd_soc_component *component =
  989. snd_soc_dapm_to_component(w->dapm);
  990. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  991. int hph_mode = wcd937x->hph_mode;
  992. int ret = 0;
  993. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  994. w->name, event);
  995. switch (event) {
  996. case SND_SOC_DAPM_PRE_PMU:
  997. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  998. wcd937x->rx_swr_dev->dev_num,
  999. true);
  1000. /*
  1001. * Enable watchdog interrupt for HPHL or AUX
  1002. * depending on mux value
  1003. */
  1004. wcd937x->ear_rx_path =
  1005. snd_soc_component_read(
  1006. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  1007. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1008. snd_soc_component_update_bits(component,
  1009. WCD937X_DIGITAL_PDM_WD_CTL2,
  1010. 0x01, 0x01);
  1011. else
  1012. snd_soc_component_update_bits(component,
  1013. WCD937X_DIGITAL_PDM_WD_CTL0,
  1014. 0x07, 0x03);
  1015. if (!wcd937x->comp1_enable)
  1016. snd_soc_component_update_bits(component,
  1017. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1018. break;
  1019. case SND_SOC_DAPM_POST_PMU:
  1020. usleep_range(6000, 6010);
  1021. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  1022. snd_soc_component_update_bits(component,
  1023. WCD937X_ANA_RX_SUPPLIES,
  1024. 0x02, 0x02);
  1025. if (wcd937x->update_wcd_event)
  1026. wcd937x->update_wcd_event(wcd937x->handle,
  1027. SLV_BOLERO_EVT_RX_MUTE,
  1028. (WCD_RX1 << 0x10));
  1029. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1030. wcd_enable_irq(&wcd937x->irq_info,
  1031. WCD937X_IRQ_AUX_PDM_WD_INT);
  1032. else
  1033. wcd_enable_irq(&wcd937x->irq_info,
  1034. WCD937X_IRQ_HPHL_PDM_WD_INT);
  1035. break;
  1036. case SND_SOC_DAPM_PRE_PMD:
  1037. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1038. wcd_disable_irq(&wcd937x->irq_info,
  1039. WCD937X_IRQ_AUX_PDM_WD_INT);
  1040. else
  1041. wcd_disable_irq(&wcd937x->irq_info,
  1042. WCD937X_IRQ_HPHL_PDM_WD_INT);
  1043. if (wcd937x->update_wcd_event)
  1044. wcd937x->update_wcd_event(wcd937x->handle,
  1045. SLV_BOLERO_EVT_RX_MUTE,
  1046. (WCD_RX1 << 0x10 | 0x1));
  1047. break;
  1048. case SND_SOC_DAPM_POST_PMD:
  1049. if (!wcd937x->comp1_enable)
  1050. snd_soc_component_update_bits(component,
  1051. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1052. usleep_range(7000, 7010);
  1053. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  1054. WCD_CLSH_EVENT_POST_PA,
  1055. WCD_CLSH_STATE_EAR,
  1056. hph_mode);
  1057. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  1058. 0x04, 0x04);
  1059. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1060. snd_soc_component_update_bits(component,
  1061. WCD937X_DIGITAL_PDM_WD_CTL2,
  1062. 0x01, 0x00);
  1063. else
  1064. snd_soc_component_update_bits(component,
  1065. WCD937X_DIGITAL_PDM_WD_CTL0,
  1066. 0x07, 0x00);
  1067. break;
  1068. };
  1069. return ret;
  1070. }
  1071. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  1072. struct snd_kcontrol *kcontrol,
  1073. int event)
  1074. {
  1075. struct snd_soc_component *component =
  1076. snd_soc_dapm_to_component(w->dapm);
  1077. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1078. int mode = wcd937x->hph_mode;
  1079. int ret = 0;
  1080. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1081. w->name, event);
  1082. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1083. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1084. wcd937x_rx_connect_port(component, CLSH,
  1085. SND_SOC_DAPM_EVENT_ON(event));
  1086. }
  1087. if (SND_SOC_DAPM_EVENT_OFF(event))
  1088. ret = swr_slvdev_datapath_control(
  1089. wcd937x->rx_swr_dev,
  1090. wcd937x->rx_swr_dev->dev_num,
  1091. false);
  1092. return ret;
  1093. }
  1094. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  1095. struct snd_kcontrol *kcontrol,
  1096. int event)
  1097. {
  1098. struct snd_soc_component *component =
  1099. snd_soc_dapm_to_component(w->dapm);
  1100. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1101. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1102. w->name, event);
  1103. switch (event) {
  1104. case SND_SOC_DAPM_PRE_PMU:
  1105. wcd937x_rx_connect_port(component, HPH_L, true);
  1106. if (wcd937x->comp1_enable)
  1107. wcd937x_rx_connect_port(component, COMP_L, true);
  1108. break;
  1109. case SND_SOC_DAPM_POST_PMD:
  1110. wcd937x_rx_connect_port(component, HPH_L, false);
  1111. if (wcd937x->comp1_enable)
  1112. wcd937x_rx_connect_port(component, COMP_L, false);
  1113. wcd937x_rx_clk_disable(component);
  1114. snd_soc_component_update_bits(component,
  1115. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1116. 0x01, 0x00);
  1117. break;
  1118. };
  1119. return 0;
  1120. }
  1121. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1122. struct snd_kcontrol *kcontrol, int event)
  1123. {
  1124. struct snd_soc_component *component =
  1125. snd_soc_dapm_to_component(w->dapm);
  1126. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1127. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1128. w->name, event);
  1129. switch (event) {
  1130. case SND_SOC_DAPM_PRE_PMU:
  1131. wcd937x_rx_connect_port(component, HPH_R, true);
  1132. if (wcd937x->comp2_enable)
  1133. wcd937x_rx_connect_port(component, COMP_R, true);
  1134. break;
  1135. case SND_SOC_DAPM_POST_PMD:
  1136. wcd937x_rx_connect_port(component, HPH_R, false);
  1137. if (wcd937x->comp2_enable)
  1138. wcd937x_rx_connect_port(component, COMP_R, false);
  1139. wcd937x_rx_clk_disable(component);
  1140. snd_soc_component_update_bits(component,
  1141. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1142. 0x02, 0x00);
  1143. break;
  1144. };
  1145. return 0;
  1146. }
  1147. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1148. struct snd_kcontrol *kcontrol,
  1149. int event)
  1150. {
  1151. struct snd_soc_component *component =
  1152. snd_soc_dapm_to_component(w->dapm);
  1153. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1154. w->name, event);
  1155. switch (event) {
  1156. case SND_SOC_DAPM_PRE_PMU:
  1157. wcd937x_rx_connect_port(component, LO, true);
  1158. break;
  1159. case SND_SOC_DAPM_POST_PMD:
  1160. wcd937x_rx_connect_port(component, LO, false);
  1161. usleep_range(6000, 6010);
  1162. wcd937x_rx_clk_disable(component);
  1163. snd_soc_component_update_bits(component,
  1164. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1165. break;
  1166. }
  1167. return 0;
  1168. }
  1169. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1170. struct snd_kcontrol *kcontrol,
  1171. int event)
  1172. {
  1173. struct snd_soc_component *component =
  1174. snd_soc_dapm_to_component(w->dapm);
  1175. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1176. u16 dmic_clk_reg;
  1177. s32 *dmic_clk_cnt;
  1178. unsigned int dmic;
  1179. char *wname;
  1180. int ret = 0;
  1181. wname = strpbrk(w->name, "012345");
  1182. if (!wname) {
  1183. dev_err(component->dev, "%s: widget not found\n", __func__);
  1184. return -EINVAL;
  1185. }
  1186. ret = kstrtouint(wname, 10, &dmic);
  1187. if (ret < 0) {
  1188. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1189. __func__);
  1190. return -EINVAL;
  1191. }
  1192. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1193. w->name, event);
  1194. switch (dmic) {
  1195. case 0:
  1196. case 1:
  1197. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1198. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1199. break;
  1200. case 2:
  1201. case 3:
  1202. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1203. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1204. break;
  1205. case 4:
  1206. case 5:
  1207. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1208. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1209. break;
  1210. default:
  1211. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1212. __func__);
  1213. return -EINVAL;
  1214. };
  1215. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1216. __func__, event, dmic, *dmic_clk_cnt);
  1217. switch (event) {
  1218. case SND_SOC_DAPM_PRE_PMU:
  1219. snd_soc_component_update_bits(component,
  1220. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1221. snd_soc_component_update_bits(component,
  1222. dmic_clk_reg, 0x07, 0x02);
  1223. snd_soc_component_update_bits(component,
  1224. dmic_clk_reg, 0x08, 0x08);
  1225. snd_soc_component_update_bits(component,
  1226. dmic_clk_reg, 0x70, 0x20);
  1227. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1228. wcd937x->tx_swr_dev->dev_num,
  1229. true);
  1230. break;
  1231. case SND_SOC_DAPM_POST_PMD:
  1232. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1233. break;
  1234. };
  1235. return 0;
  1236. }
  1237. /*
  1238. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1239. * @micb_mv: micbias in mv
  1240. *
  1241. * return register value converted
  1242. */
  1243. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1244. {
  1245. /* min micbias voltage is 1V and maximum is 2.85V */
  1246. if (micb_mv < 1000 || micb_mv > 2850) {
  1247. pr_err("%s: unsupported micbias voltage\n", __func__);
  1248. return -EINVAL;
  1249. }
  1250. return (micb_mv - 1000) / 50;
  1251. }
  1252. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1253. /*
  1254. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1255. * @component: handle to snd_soc_component *
  1256. * @req_volt: micbias voltage to be set
  1257. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1258. *
  1259. * return 0 if adjustment is success or error code in case of failure
  1260. */
  1261. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1262. int req_volt, int micb_num)
  1263. {
  1264. struct wcd937x_priv *wcd937x =
  1265. snd_soc_component_get_drvdata(component);
  1266. int cur_vout_ctl, req_vout_ctl;
  1267. int micb_reg, micb_val, micb_en;
  1268. int ret = 0;
  1269. switch (micb_num) {
  1270. case MIC_BIAS_1:
  1271. micb_reg = WCD937X_ANA_MICB1;
  1272. break;
  1273. case MIC_BIAS_2:
  1274. micb_reg = WCD937X_ANA_MICB2;
  1275. break;
  1276. case MIC_BIAS_3:
  1277. micb_reg = WCD937X_ANA_MICB3;
  1278. break;
  1279. default:
  1280. return -EINVAL;
  1281. }
  1282. mutex_lock(&wcd937x->micb_lock);
  1283. /*
  1284. * If requested micbias voltage is same as current micbias
  1285. * voltage, then just return. Otherwise, adjust voltage as
  1286. * per requested value. If micbias is already enabled, then
  1287. * to avoid slow micbias ramp-up or down enable pull-up
  1288. * momentarily, change the micbias value and then re-enable
  1289. * micbias.
  1290. */
  1291. micb_val = snd_soc_component_read(component, micb_reg);
  1292. micb_en = (micb_val & 0xC0) >> 6;
  1293. cur_vout_ctl = micb_val & 0x3F;
  1294. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1295. if (req_vout_ctl < 0) {
  1296. ret = -EINVAL;
  1297. goto exit;
  1298. }
  1299. if (cur_vout_ctl == req_vout_ctl) {
  1300. ret = 0;
  1301. goto exit;
  1302. }
  1303. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1304. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1305. req_volt, micb_en);
  1306. if (micb_en == 0x1)
  1307. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1308. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1309. if (micb_en == 0x1) {
  1310. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1311. /*
  1312. * Add 2ms delay as per HW requirement after enabling
  1313. * micbias
  1314. */
  1315. usleep_range(2000, 2100);
  1316. }
  1317. exit:
  1318. mutex_unlock(&wcd937x->micb_lock);
  1319. return ret;
  1320. }
  1321. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1322. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1323. struct snd_kcontrol *kcontrol,
  1324. int event)
  1325. {
  1326. struct snd_soc_component *component =
  1327. snd_soc_dapm_to_component(w->dapm);
  1328. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1329. int ret = 0;
  1330. switch (event) {
  1331. case SND_SOC_DAPM_PRE_PMU:
  1332. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1333. /* Enable BCS for Headset mic */
  1334. if (w->shift == 1 && !(snd_soc_component_read(component,
  1335. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1336. if (!wcd937x->bcs_dis) {
  1337. wcd937x_tx_connect_port(
  1338. component, MBHC, true);
  1339. set_bit(AMIC2_BCS_ENABLE,
  1340. &wcd937x->status_mask);
  1341. }
  1342. }
  1343. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1344. } else {
  1345. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1346. }
  1347. break;
  1348. case SND_SOC_DAPM_POST_PMD:
  1349. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1350. wcd937x->tx_swr_dev->dev_num,
  1351. false);
  1352. break;
  1353. };
  1354. return ret;
  1355. }
  1356. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1357. struct snd_kcontrol *kcontrol,
  1358. int event){
  1359. struct snd_soc_component *component =
  1360. snd_soc_dapm_to_component(w->dapm);
  1361. struct wcd937x_priv *wcd937x =
  1362. snd_soc_component_get_drvdata(component);
  1363. int ret = 0;
  1364. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1365. w->name, event);
  1366. switch (event) {
  1367. case SND_SOC_DAPM_PRE_PMU:
  1368. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1369. wcd937x->ana_clk_count++;
  1370. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1371. wcd937x->adc_count++;
  1372. snd_soc_component_update_bits(component,
  1373. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1374. snd_soc_component_update_bits(component,
  1375. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1376. snd_soc_component_update_bits(component,
  1377. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1378. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1379. wcd937x->tx_swr_dev->dev_num,
  1380. true);
  1381. break;
  1382. case SND_SOC_DAPM_POST_PMD:
  1383. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1384. if (w->shift == 1 &&
  1385. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1386. wcd937x_tx_connect_port(component, MBHC, false);
  1387. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1388. }
  1389. wcd937x->adc_count--;
  1390. if (wcd937x->adc_count <= 0) {
  1391. snd_soc_component_update_bits(component,
  1392. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1393. wcd937x->adc_count = 0;
  1394. }
  1395. break;
  1396. };
  1397. return ret;
  1398. }
  1399. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1400. struct snd_kcontrol *kcontrol, int event)
  1401. {
  1402. struct snd_soc_component *component =
  1403. snd_soc_dapm_to_component(w->dapm);
  1404. struct wcd937x_priv *wcd937x =
  1405. snd_soc_component_get_drvdata(component);
  1406. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1407. w->name, event);
  1408. switch (event) {
  1409. case SND_SOC_DAPM_PRE_PMU:
  1410. snd_soc_component_update_bits(component,
  1411. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1412. snd_soc_component_update_bits(component,
  1413. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1414. snd_soc_component_update_bits(component,
  1415. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1416. snd_soc_component_update_bits(component,
  1417. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1418. snd_soc_component_update_bits(component,
  1419. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1420. snd_soc_component_update_bits(component,
  1421. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1422. snd_soc_component_update_bits(component,
  1423. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1424. snd_soc_component_update_bits(component,
  1425. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1426. snd_soc_component_update_bits(component,
  1427. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1428. break;
  1429. case SND_SOC_DAPM_POST_PMD:
  1430. if (wcd937x->adc_count == 0) {
  1431. snd_soc_component_update_bits(component,
  1432. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1433. snd_soc_component_update_bits(component,
  1434. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1435. snd_soc_component_update_bits(component,
  1436. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1437. snd_soc_component_update_bits(component,
  1438. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1439. snd_soc_component_update_bits(component,
  1440. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1441. }
  1442. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1443. wcd937x->ana_clk_count--;
  1444. if (wcd937x->ana_clk_count <= 0) {
  1445. snd_soc_component_update_bits(component,
  1446. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1447. wcd937x->ana_clk_count = 0;
  1448. }
  1449. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1450. break;
  1451. };
  1452. return 0;
  1453. }
  1454. int wcd937x_micbias_control(struct snd_soc_component *component,
  1455. int micb_num, int req, bool is_dapm)
  1456. {
  1457. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1458. int micb_index = micb_num - 1;
  1459. u16 micb_reg;
  1460. int pre_off_event = 0, post_off_event = 0;
  1461. int post_on_event = 0, post_dapm_off = 0;
  1462. int post_dapm_on = 0;
  1463. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1464. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1465. __func__, micb_index);
  1466. return -EINVAL;
  1467. }
  1468. switch (micb_num) {
  1469. case MIC_BIAS_1:
  1470. micb_reg = WCD937X_ANA_MICB1;
  1471. break;
  1472. case MIC_BIAS_2:
  1473. micb_reg = WCD937X_ANA_MICB2;
  1474. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1475. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1476. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1477. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1478. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1479. break;
  1480. case MIC_BIAS_3:
  1481. micb_reg = WCD937X_ANA_MICB3;
  1482. break;
  1483. default:
  1484. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1485. __func__, micb_num);
  1486. return -EINVAL;
  1487. };
  1488. mutex_lock(&wcd937x->micb_lock);
  1489. switch (req) {
  1490. case MICB_PULLUP_ENABLE:
  1491. wcd937x->pullup_ref[micb_index]++;
  1492. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1493. (wcd937x->micb_ref[micb_index] == 0))
  1494. snd_soc_component_update_bits(component, micb_reg,
  1495. 0xC0, 0x80);
  1496. break;
  1497. case MICB_PULLUP_DISABLE:
  1498. if (wcd937x->pullup_ref[micb_index] > 0)
  1499. wcd937x->pullup_ref[micb_index]--;
  1500. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1501. (wcd937x->micb_ref[micb_index] == 0))
  1502. snd_soc_component_update_bits(component, micb_reg,
  1503. 0xC0, 0x00);
  1504. break;
  1505. case MICB_ENABLE:
  1506. wcd937x->micb_ref[micb_index]++;
  1507. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1508. wcd937x->ana_clk_count++;
  1509. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1510. if (wcd937x->micb_ref[micb_index] == 1) {
  1511. snd_soc_component_update_bits(component,
  1512. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1513. snd_soc_component_update_bits(component,
  1514. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1515. snd_soc_component_update_bits(component,
  1516. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1517. snd_soc_component_update_bits(component,
  1518. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1519. snd_soc_component_update_bits(component,
  1520. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1521. snd_soc_component_update_bits(component,
  1522. micb_reg, 0xC0, 0x40);
  1523. if (post_on_event)
  1524. blocking_notifier_call_chain(
  1525. &wcd937x->mbhc->notifier, post_on_event,
  1526. &wcd937x->mbhc->wcd_mbhc);
  1527. }
  1528. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1529. blocking_notifier_call_chain(
  1530. &wcd937x->mbhc->notifier, post_dapm_on,
  1531. &wcd937x->mbhc->wcd_mbhc);
  1532. break;
  1533. case MICB_DISABLE:
  1534. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1535. wcd937x->ana_clk_count--;
  1536. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1537. if (wcd937x->micb_ref[micb_index] > 0)
  1538. wcd937x->micb_ref[micb_index]--;
  1539. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1540. (wcd937x->pullup_ref[micb_index] > 0))
  1541. snd_soc_component_update_bits(component, micb_reg,
  1542. 0xC0, 0x80);
  1543. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1544. (wcd937x->pullup_ref[micb_index] == 0)) {
  1545. if (pre_off_event && wcd937x->mbhc)
  1546. blocking_notifier_call_chain(
  1547. &wcd937x->mbhc->notifier, pre_off_event,
  1548. &wcd937x->mbhc->wcd_mbhc);
  1549. snd_soc_component_update_bits(component, micb_reg,
  1550. 0xC0, 0x00);
  1551. if (post_off_event && wcd937x->mbhc)
  1552. blocking_notifier_call_chain(
  1553. &wcd937x->mbhc->notifier,
  1554. post_off_event,
  1555. &wcd937x->mbhc->wcd_mbhc);
  1556. }
  1557. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1558. if (wcd937x->ana_clk_count <= 0) {
  1559. snd_soc_component_update_bits(component,
  1560. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1561. 0x10, 0x00);
  1562. wcd937x->ana_clk_count = 0;
  1563. }
  1564. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1565. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1566. blocking_notifier_call_chain(
  1567. &wcd937x->mbhc->notifier, post_dapm_off,
  1568. &wcd937x->mbhc->wcd_mbhc);
  1569. break;
  1570. };
  1571. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1572. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1573. wcd937x->pullup_ref[micb_index]);
  1574. mutex_unlock(&wcd937x->micb_lock);
  1575. return 0;
  1576. }
  1577. EXPORT_SYMBOL(wcd937x_micbias_control);
  1578. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1579. bool bcs_disable)
  1580. {
  1581. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1582. if (wcd937x->update_wcd_event) {
  1583. if (bcs_disable)
  1584. wcd937x->update_wcd_event(wcd937x->handle,
  1585. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1586. else
  1587. wcd937x->update_wcd_event(wcd937x->handle,
  1588. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1589. }
  1590. }
  1591. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1592. {
  1593. int ret = 0;
  1594. uint8_t devnum = 0;
  1595. int num_retry = NUM_ATTEMPTS;
  1596. do {
  1597. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1598. if (ret) {
  1599. dev_err(&swr_dev->dev,
  1600. "%s get devnum %d for dev addr %lx failed\n",
  1601. __func__, devnum, swr_dev->addr);
  1602. /* retry after 1ms */
  1603. usleep_range(1000, 1010);
  1604. }
  1605. } while (ret && --num_retry);
  1606. swr_dev->dev_num = devnum;
  1607. return 0;
  1608. }
  1609. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1610. struct wcd_mbhc_config *mbhc_cfg)
  1611. {
  1612. if (mbhc_cfg->enable_usbc_analog) {
  1613. if (!(snd_soc_component_read(component, WCD937X_ANA_MBHC_MECH)
  1614. & 0x20))
  1615. return true;
  1616. }
  1617. return false;
  1618. }
  1619. static int wcd937x_event_notify(struct notifier_block *block,
  1620. unsigned long val,
  1621. void *data)
  1622. {
  1623. u16 event = (val & 0xffff);
  1624. u16 amic = (val >> 0x10);
  1625. u16 mask = 0x40, reg = 0x0;
  1626. int ret = 0;
  1627. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1628. struct snd_soc_component *component = wcd937x->component;
  1629. struct wcd_mbhc *mbhc;
  1630. switch (event) {
  1631. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1632. if (amic == 0x1 || amic == 0x2)
  1633. reg = WCD937X_ANA_TX_CH2;
  1634. else if (amic == 0x3)
  1635. reg = WCD937X_ANA_TX_CH3_HPF;
  1636. else
  1637. return 0;
  1638. if (amic == 0x2)
  1639. mask = 0x20;
  1640. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1641. break;
  1642. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1643. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1644. 0xC0, 0x00);
  1645. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1646. 0x80, 0x00);
  1647. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1648. 0x80, 0x00);
  1649. break;
  1650. case BOLERO_SLV_EVT_SSR_DOWN:
  1651. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1652. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1653. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1654. mbhc->mbhc_cfg);
  1655. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1656. wcd937x_reset_low(wcd937x->dev);
  1657. break;
  1658. case BOLERO_SLV_EVT_SSR_UP:
  1659. wcd937x_reset(wcd937x->dev);
  1660. /* allow reset to take effect */
  1661. usleep_range(10000, 10010);
  1662. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1663. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1664. wcd937x_init_reg(component);
  1665. regcache_mark_dirty(wcd937x->regmap);
  1666. regcache_sync(wcd937x->regmap);
  1667. /* Initialize MBHC module */
  1668. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1669. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1670. if (ret) {
  1671. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1672. __func__);
  1673. } else {
  1674. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1675. if (wcd937x->usbc_hs_status)
  1676. mdelay(500);
  1677. }
  1678. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1679. break;
  1680. default:
  1681. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1682. event);
  1683. break;
  1684. }
  1685. return 0;
  1686. }
  1687. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1688. int event)
  1689. {
  1690. struct snd_soc_component *component =
  1691. snd_soc_dapm_to_component(w->dapm);
  1692. int micb_num;
  1693. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1694. __func__, w->name, event);
  1695. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1696. micb_num = MIC_BIAS_1;
  1697. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1698. micb_num = MIC_BIAS_2;
  1699. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1700. micb_num = MIC_BIAS_3;
  1701. else
  1702. return -EINVAL;
  1703. switch (event) {
  1704. case SND_SOC_DAPM_PRE_PMU:
  1705. wcd937x_micbias_control(component, micb_num,
  1706. MICB_ENABLE, true);
  1707. break;
  1708. case SND_SOC_DAPM_POST_PMU:
  1709. usleep_range(1000, 1100);
  1710. break;
  1711. case SND_SOC_DAPM_POST_PMD:
  1712. wcd937x_micbias_control(component, micb_num,
  1713. MICB_DISABLE, true);
  1714. break;
  1715. };
  1716. return 0;
  1717. }
  1718. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1719. struct snd_kcontrol *kcontrol,
  1720. int event)
  1721. {
  1722. return __wcd937x_codec_enable_micbias(w, event);
  1723. }
  1724. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1725. int event)
  1726. {
  1727. struct snd_soc_component *component =
  1728. snd_soc_dapm_to_component(w->dapm);
  1729. int micb_num;
  1730. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1731. __func__, w->name, event);
  1732. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1733. micb_num = MIC_BIAS_1;
  1734. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1735. micb_num = MIC_BIAS_2;
  1736. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1737. micb_num = MIC_BIAS_3;
  1738. else
  1739. return -EINVAL;
  1740. switch (event) {
  1741. case SND_SOC_DAPM_PRE_PMU:
  1742. wcd937x_micbias_control(component, micb_num,
  1743. MICB_PULLUP_ENABLE, true);
  1744. break;
  1745. case SND_SOC_DAPM_POST_PMU:
  1746. /* 1 msec delay as per HW requirement */
  1747. usleep_range(1000, 1100);
  1748. break;
  1749. case SND_SOC_DAPM_POST_PMD:
  1750. wcd937x_micbias_control(component, micb_num,
  1751. MICB_PULLUP_DISABLE, true);
  1752. break;
  1753. };
  1754. return 0;
  1755. }
  1756. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1757. struct snd_kcontrol *kcontrol,
  1758. int event)
  1759. {
  1760. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1761. }
  1762. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1763. struct snd_ctl_elem_value *ucontrol)
  1764. {
  1765. struct snd_soc_component *component =
  1766. snd_soc_kcontrol_component(kcontrol);
  1767. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1768. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1769. return 0;
  1770. }
  1771. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1772. struct snd_ctl_elem_value *ucontrol)
  1773. {
  1774. struct snd_soc_component *component =
  1775. snd_soc_kcontrol_component(kcontrol);
  1776. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1777. u32 mode_val;
  1778. mode_val = ucontrol->value.enumerated.item[0];
  1779. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1780. if (mode_val == 0) {
  1781. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1782. __func__);
  1783. mode_val = 3; /* enum will be updated later */
  1784. }
  1785. wcd937x->hph_mode = mode_val;
  1786. return 0;
  1787. }
  1788. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1789. struct snd_ctl_elem_value *ucontrol)
  1790. {
  1791. struct snd_soc_component *component =
  1792. snd_soc_kcontrol_component(kcontrol);
  1793. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1794. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1795. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1796. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1797. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1798. return 0;
  1799. }
  1800. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1801. struct snd_ctl_elem_value *ucontrol)
  1802. {
  1803. struct snd_soc_component *component =
  1804. snd_soc_kcontrol_component(kcontrol);
  1805. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1806. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1807. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1808. __func__, pwr_level);
  1809. if (strnstr(kcontrol->id.name, "CH1",
  1810. sizeof(kcontrol->id.name))) {
  1811. snd_soc_component_update_bits(component,
  1812. WCD937X_ANA_TX_CH1, 0x60,
  1813. pwr_level << 0x5);
  1814. wcd937x->tx_ch_pwr[0] = pwr_level;
  1815. } else if (strnstr(kcontrol->id.name, "CH3",
  1816. sizeof(kcontrol->id.name))) {
  1817. snd_soc_component_update_bits(component,
  1818. WCD937X_ANA_TX_CH3, 0x60,
  1819. pwr_level << 0x5);
  1820. wcd937x->tx_ch_pwr[1] = pwr_level;
  1821. }
  1822. return 0;
  1823. }
  1824. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1825. struct snd_ctl_elem_value *ucontrol)
  1826. {
  1827. u8 ear_pa_gain = 0;
  1828. struct snd_soc_component *component =
  1829. snd_soc_kcontrol_component(kcontrol);
  1830. ear_pa_gain = snd_soc_component_read(component,
  1831. WCD937X_ANA_EAR_COMPANDER_CTL);
  1832. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1833. ucontrol->value.integer.value[0] = ear_pa_gain;
  1834. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1835. ear_pa_gain);
  1836. return 0;
  1837. }
  1838. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1839. struct snd_ctl_elem_value *ucontrol)
  1840. {
  1841. u8 ear_pa_gain = 0;
  1842. struct snd_soc_component *component =
  1843. snd_soc_kcontrol_component(kcontrol);
  1844. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1845. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1846. __func__, ucontrol->value.integer.value[0]);
  1847. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1848. if (!wcd937x->comp1_enable) {
  1849. snd_soc_component_update_bits(component,
  1850. WCD937X_ANA_EAR_COMPANDER_CTL,
  1851. 0x7C, ear_pa_gain);
  1852. }
  1853. return 0;
  1854. }
  1855. /* wcd937x_codec_get_dev_num - returns swr device number
  1856. * @component: Codec instance
  1857. *
  1858. * Return: swr device number on success or negative error
  1859. * code on failure.
  1860. */
  1861. int wcd937x_codec_get_dev_num(struct snd_soc_component *component)
  1862. {
  1863. struct wcd937x_priv *wcd937x;
  1864. if (!component)
  1865. return -EINVAL;
  1866. wcd937x = snd_soc_component_get_drvdata(component);
  1867. if (!wcd937x || !wcd937x->rx_swr_dev) {
  1868. pr_err("%s: wcd937x component is NULL\n", __func__);
  1869. return -EINVAL;
  1870. }
  1871. return wcd937x->rx_swr_dev->dev_num;
  1872. }
  1873. EXPORT_SYMBOL_GPL(wcd937x_codec_get_dev_num);
  1874. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1875. struct snd_ctl_elem_value *ucontrol)
  1876. {
  1877. struct snd_soc_component *component =
  1878. snd_soc_kcontrol_component(kcontrol);
  1879. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1880. bool hphr;
  1881. struct soc_multi_mixer_control *mc;
  1882. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1883. hphr = mc->shift;
  1884. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1885. wcd937x->comp1_enable;
  1886. return 0;
  1887. }
  1888. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1889. struct snd_ctl_elem_value *ucontrol)
  1890. {
  1891. struct snd_soc_component *component =
  1892. snd_soc_kcontrol_component(kcontrol);
  1893. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1894. int value = ucontrol->value.integer.value[0];
  1895. bool hphr;
  1896. struct soc_multi_mixer_control *mc;
  1897. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1898. hphr = mc->shift;
  1899. if (hphr)
  1900. wcd937x->comp2_enable = value;
  1901. else
  1902. wcd937x->comp1_enable = value;
  1903. return 0;
  1904. }
  1905. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1906. struct snd_kcontrol *kcontrol,
  1907. int event)
  1908. {
  1909. struct snd_soc_component *component =
  1910. snd_soc_dapm_to_component(w->dapm);
  1911. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1912. struct wcd937x_pdata *pdata = NULL;
  1913. int ret = 0;
  1914. pdata = dev_get_platdata(wcd937x->dev);
  1915. if (!pdata) {
  1916. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1917. return -EINVAL;
  1918. }
  1919. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1920. w->name, event);
  1921. switch (event) {
  1922. case SND_SOC_DAPM_PRE_PMU:
  1923. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1924. dev_dbg(component->dev,
  1925. "%s: buck already in enabled state\n",
  1926. __func__);
  1927. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1928. return 0;
  1929. }
  1930. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1931. wcd937x->supplies,
  1932. pdata->regulator,
  1933. pdata->num_supplies,
  1934. "cdc-vdd-buck");
  1935. if (ret == -EINVAL) {
  1936. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1937. __func__);
  1938. return ret;
  1939. }
  1940. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1941. /*
  1942. * 200us sleep is required after LDO15 is enabled as per
  1943. * HW requirement
  1944. */
  1945. usleep_range(200, 250);
  1946. break;
  1947. case SND_SOC_DAPM_POST_PMD:
  1948. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1949. break;
  1950. }
  1951. return 0;
  1952. }
  1953. static const char * const rx_hph_mode_mux_text[] = {
  1954. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1955. "CLS_H_ULP", "CLS_AB_HIFI",
  1956. };
  1957. const char * const tx_master_ch_text[] = {
  1958. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1959. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1960. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1961. "SWRM_TX_PCM_IN",
  1962. };
  1963. const struct soc_enum tx_master_ch_enum =
  1964. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1965. tx_master_ch_text);
  1966. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1967. {
  1968. u8 ch_type = 0;
  1969. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1970. ch_type = ADC1;
  1971. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1972. ch_type = ADC2;
  1973. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1974. ch_type = ADC3;
  1975. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1976. ch_type = DMIC0;
  1977. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1978. ch_type = DMIC1;
  1979. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1980. ch_type = MBHC;
  1981. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1982. ch_type = DMIC2;
  1983. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1984. ch_type = DMIC3;
  1985. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1986. ch_type = DMIC4;
  1987. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1988. ch_type = DMIC5;
  1989. else
  1990. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1991. if (ch_type)
  1992. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1993. else
  1994. *ch_idx = -EINVAL;
  1995. }
  1996. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1997. struct snd_ctl_elem_value *ucontrol)
  1998. {
  1999. struct snd_soc_component *component =
  2000. snd_soc_kcontrol_component(kcontrol);
  2001. struct wcd937x_priv *wcd937x = NULL;
  2002. int slave_ch_idx = -EINVAL;
  2003. if (component == NULL)
  2004. return -EINVAL;
  2005. wcd937x = snd_soc_component_get_drvdata(component);
  2006. if (wcd937x == NULL)
  2007. return -EINVAL;
  2008. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2009. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  2010. return -EINVAL;
  2011. ucontrol->value.integer.value[0] =
  2012. wcd937x_slave_get_master_ch_val(
  2013. wcd937x->tx_master_ch_map[slave_ch_idx]);
  2014. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2015. __func__, ucontrol->value.integer.value[0]);
  2016. return 0;
  2017. }
  2018. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2019. struct snd_ctl_elem_value *ucontrol)
  2020. {
  2021. struct snd_soc_component *component =
  2022. snd_soc_kcontrol_component(kcontrol);
  2023. struct wcd937x_priv *wcd937x;
  2024. int slave_ch_idx = -EINVAL, idx = 0;
  2025. if (component == NULL)
  2026. return -EINVAL;
  2027. wcd937x = snd_soc_component_get_drvdata(component);
  2028. if (wcd937x == NULL)
  2029. return -EINVAL;
  2030. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2031. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  2032. return -EINVAL;
  2033. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2034. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2035. __func__, ucontrol->value.enumerated.item[0]);
  2036. idx = ucontrol->value.enumerated.item[0];
  2037. if (idx < 0 || idx >= ARRAY_SIZE(wcd937x_swr_master_ch_map))
  2038. return -EINVAL;
  2039. wcd937x->tx_master_ch_map[slave_ch_idx] =
  2040. wcd937x_slave_get_master_ch(idx);
  2041. return 0;
  2042. }
  2043. static int wcd937x_bcs_get(struct snd_kcontrol *kcontrol,
  2044. struct snd_ctl_elem_value *ucontrol)
  2045. {
  2046. struct snd_soc_component *component =
  2047. snd_soc_kcontrol_component(kcontrol);
  2048. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2049. ucontrol->value.integer.value[0] = wcd937x->bcs_dis;
  2050. return 0;
  2051. }
  2052. static int wcd937x_bcs_put(struct snd_kcontrol *kcontrol,
  2053. struct snd_ctl_elem_value *ucontrol)
  2054. {
  2055. struct snd_soc_component *component =
  2056. snd_soc_kcontrol_component(kcontrol);
  2057. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2058. wcd937x->bcs_dis = ucontrol->value.integer.value[0];
  2059. dev_dbg(component->dev, "%s: BCS Disable %d\n", __func__, wcd937x->bcs_dis);
  2060. return 0;
  2061. }
  2062. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  2063. "L0", "L1", "L2", "L3",
  2064. };
  2065. static const char * const wcd937x_ear_pa_gain_text[] = {
  2066. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2067. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2068. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2069. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2070. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2071. };
  2072. static const struct soc_enum rx_hph_mode_mux_enum =
  2073. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2074. rx_hph_mode_mux_text);
  2075. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  2076. wcd937x_ear_pa_gain_text);
  2077. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  2078. wcd937x_tx_ch_pwr_level_text);
  2079. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  2080. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  2081. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  2082. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2083. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  2084. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2085. wcd937x_get_compander, wcd937x_set_compander),
  2086. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2087. wcd937x_get_compander, wcd937x_set_compander),
  2088. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2089. wcd937x_bcs_get, wcd937x_bcs_put),
  2090. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  2091. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  2092. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  2093. analog_gain),
  2094. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  2095. analog_gain),
  2096. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  2097. analog_gain),
  2098. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2099. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2100. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2101. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2102. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2103. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2104. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2105. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2106. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2107. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2108. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2109. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2110. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2111. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2112. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2113. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2114. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2115. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2116. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2117. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2118. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  2119. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2120. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  2121. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2122. };
  2123. static const struct snd_kcontrol_new adc1_switch[] = {
  2124. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2125. };
  2126. static const struct snd_kcontrol_new adc2_switch[] = {
  2127. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2128. };
  2129. static const struct snd_kcontrol_new adc3_switch[] = {
  2130. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2131. };
  2132. static const struct snd_kcontrol_new dmic1_switch[] = {
  2133. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2134. };
  2135. static const struct snd_kcontrol_new dmic2_switch[] = {
  2136. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2137. };
  2138. static const struct snd_kcontrol_new dmic3_switch[] = {
  2139. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2140. };
  2141. static const struct snd_kcontrol_new dmic4_switch[] = {
  2142. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2143. };
  2144. static const struct snd_kcontrol_new dmic5_switch[] = {
  2145. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2146. };
  2147. static const struct snd_kcontrol_new dmic6_switch[] = {
  2148. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2149. };
  2150. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2151. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2152. };
  2153. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2154. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2155. };
  2156. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2157. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2158. };
  2159. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2160. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2161. };
  2162. static const char * const adc2_mux_text[] = {
  2163. "INP2", "INP3"
  2164. };
  2165. static const char * const rdac3_mux_text[] = {
  2166. "RX1", "RX3"
  2167. };
  2168. static const struct soc_enum adc2_enum =
  2169. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  2170. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2171. static const struct soc_enum rdac3_enum =
  2172. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2173. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2174. static const struct snd_kcontrol_new tx_adc2_mux =
  2175. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2176. static const struct snd_kcontrol_new rx_rdac3_mux =
  2177. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2178. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  2179. /*input widgets*/
  2180. SND_SOC_DAPM_INPUT("AMIC1"),
  2181. SND_SOC_DAPM_INPUT("AMIC2"),
  2182. SND_SOC_DAPM_INPUT("AMIC3"),
  2183. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2184. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2185. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2186. /*
  2187. * These dummy widgets are null connected to WCD937x dapm input and
  2188. * output widgets which are not actual path endpoints. This ensures
  2189. * dapm doesnt set these dapm input and output widgets as endpoints.
  2190. */
  2191. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2192. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2193. /*tx widgets*/
  2194. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2195. wcd937x_codec_enable_adc,
  2196. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2197. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2198. wcd937x_codec_enable_adc,
  2199. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2200. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2201. NULL, 0, wcd937x_enable_req,
  2202. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2203. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2204. NULL, 0, wcd937x_enable_req,
  2205. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2206. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2207. &tx_adc2_mux),
  2208. /*tx mixers*/
  2209. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2210. adc1_switch, ARRAY_SIZE(adc1_switch),
  2211. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2212. SND_SOC_DAPM_POST_PMD),
  2213. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2214. adc2_switch, ARRAY_SIZE(adc2_switch),
  2215. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2216. SND_SOC_DAPM_POST_PMD),
  2217. /* micbias widgets*/
  2218. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2219. wcd937x_codec_enable_micbias,
  2220. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2221. SND_SOC_DAPM_POST_PMD),
  2222. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2223. wcd937x_codec_enable_micbias,
  2224. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2225. SND_SOC_DAPM_POST_PMD),
  2226. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2227. wcd937x_codec_enable_micbias,
  2228. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2229. SND_SOC_DAPM_POST_PMD),
  2230. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2231. wcd937x_codec_enable_vdd_buck,
  2232. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2233. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2234. wcd937x_enable_clsh,
  2235. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2236. /*rx widgets*/
  2237. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2238. wcd937x_codec_enable_ear_pa,
  2239. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2240. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2241. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2242. wcd937x_codec_enable_aux_pa,
  2243. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2244. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2245. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2246. wcd937x_codec_enable_hphl_pa,
  2247. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2248. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2249. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2250. wcd937x_codec_enable_hphr_pa,
  2251. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2252. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2253. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2254. wcd937x_codec_hphl_dac_event,
  2255. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2256. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2257. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2258. wcd937x_codec_hphr_dac_event,
  2259. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2260. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2261. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2262. wcd937x_codec_ear_dac_event,
  2263. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2264. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2265. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2266. wcd937x_codec_aux_dac_event,
  2267. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2268. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2269. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2270. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2271. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2272. SND_SOC_DAPM_POST_PMD),
  2273. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2274. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2275. SND_SOC_DAPM_POST_PMD),
  2276. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2277. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2278. SND_SOC_DAPM_POST_PMD),
  2279. /* rx mixer widgets*/
  2280. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2281. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2282. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2283. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2284. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2285. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2286. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2287. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2288. /*output widgets tx*/
  2289. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2290. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2291. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2292. /*output widgets rx*/
  2293. SND_SOC_DAPM_OUTPUT("EAR"),
  2294. SND_SOC_DAPM_OUTPUT("AUX"),
  2295. SND_SOC_DAPM_OUTPUT("HPHL"),
  2296. SND_SOC_DAPM_OUTPUT("HPHR"),
  2297. /* micbias pull up widgets*/
  2298. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2299. wcd937x_codec_enable_micbias_pullup,
  2300. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2301. SND_SOC_DAPM_POST_PMD),
  2302. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2303. wcd937x_codec_enable_micbias_pullup,
  2304. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2305. SND_SOC_DAPM_POST_PMD),
  2306. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2307. wcd937x_codec_enable_micbias_pullup,
  2308. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2309. SND_SOC_DAPM_POST_PMD),
  2310. };
  2311. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2312. /*input widgets*/
  2313. SND_SOC_DAPM_INPUT("AMIC4"),
  2314. /*tx widgets*/
  2315. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2316. wcd937x_codec_enable_adc,
  2317. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2318. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2319. NULL, 0, wcd937x_enable_req,
  2320. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2321. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2322. wcd937x_codec_enable_dmic,
  2323. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2324. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2325. wcd937x_codec_enable_dmic,
  2326. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2327. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2328. wcd937x_codec_enable_dmic,
  2329. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2330. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2331. wcd937x_codec_enable_dmic,
  2332. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2333. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2334. wcd937x_codec_enable_dmic,
  2335. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2336. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2337. wcd937x_codec_enable_dmic,
  2338. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2339. /*tx mixer widgets*/
  2340. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2341. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2342. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2343. SND_SOC_DAPM_POST_PMD),
  2344. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2345. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2346. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2347. SND_SOC_DAPM_POST_PMD),
  2348. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2349. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2350. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2351. SND_SOC_DAPM_POST_PMD),
  2352. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2353. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2354. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2355. SND_SOC_DAPM_POST_PMD),
  2356. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2357. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2358. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2359. SND_SOC_DAPM_POST_PMD),
  2360. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2361. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2362. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2363. SND_SOC_DAPM_POST_PMD),
  2364. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2365. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2366. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2367. /*output widgets*/
  2368. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2369. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2370. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2371. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2372. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2373. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2374. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2375. };
  2376. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2377. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2378. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2379. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2380. {"ADC1 REQ", NULL, "ADC1"},
  2381. {"ADC1", NULL, "AMIC1"},
  2382. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2383. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2384. {"ADC2 REQ", NULL, "ADC2"},
  2385. {"ADC2", NULL, "ADC2 MUX"},
  2386. {"ADC2 MUX", "INP3", "AMIC3"},
  2387. {"ADC2 MUX", "INP2", "AMIC2"},
  2388. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2389. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2390. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2391. {"RX1", NULL, "IN1_HPHL"},
  2392. {"RDAC1", NULL, "RX1"},
  2393. {"HPHL_RDAC", "Switch", "RDAC1"},
  2394. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2395. {"HPHL", NULL, "HPHL PGA"},
  2396. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2397. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2398. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2399. {"RX2", NULL, "IN2_HPHR"},
  2400. {"RDAC2", NULL, "RX2"},
  2401. {"HPHR_RDAC", "Switch", "RDAC2"},
  2402. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2403. {"HPHR", NULL, "HPHR PGA"},
  2404. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2405. {"IN3_AUX", NULL, "VDD_BUCK"},
  2406. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2407. {"RX3", NULL, "IN3_AUX"},
  2408. {"RDAC4", NULL, "RX3"},
  2409. {"AUX_RDAC", "Switch", "RDAC4"},
  2410. {"AUX PGA", NULL, "AUX_RDAC"},
  2411. {"AUX", NULL, "AUX PGA"},
  2412. {"RDAC3_MUX", "RX3", "RX3"},
  2413. {"RDAC3_MUX", "RX1", "RX1"},
  2414. {"RDAC3", NULL, "RDAC3_MUX"},
  2415. {"EAR_RDAC", "Switch", "RDAC3"},
  2416. {"EAR PGA", NULL, "EAR_RDAC"},
  2417. {"EAR", NULL, "EAR PGA"},
  2418. };
  2419. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2420. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2421. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2422. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2423. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2424. {"ADC3 REQ", NULL, "ADC3"},
  2425. {"ADC3", NULL, "AMIC4"},
  2426. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2427. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2428. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2429. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2430. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2431. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2432. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2433. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2434. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2435. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2436. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2437. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2438. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2439. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2440. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2441. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2442. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2443. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2444. };
  2445. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2446. void *file_private_data,
  2447. struct file *file,
  2448. char __user *buf, size_t count,
  2449. loff_t pos)
  2450. {
  2451. struct wcd937x_priv *priv;
  2452. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2453. int len = 0;
  2454. priv = (struct wcd937x_priv *) entry->private_data;
  2455. if (!priv) {
  2456. pr_err("%s: wcd937x priv is null\n", __func__);
  2457. return -EINVAL;
  2458. }
  2459. switch (priv->version) {
  2460. case WCD937X_VERSION_1_0:
  2461. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2462. break;
  2463. default:
  2464. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2465. }
  2466. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2467. }
  2468. static struct snd_info_entry_ops wcd937x_info_ops = {
  2469. .read = wcd937x_version_read,
  2470. };
  2471. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2472. void *file_private_data,
  2473. struct file *file,
  2474. char __user *buf, size_t count,
  2475. loff_t pos)
  2476. {
  2477. struct wcd937x_priv *priv;
  2478. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2479. int len = 0;
  2480. priv = (struct wcd937x_priv *) entry->private_data;
  2481. if (!priv) {
  2482. pr_err("%s: wcd937x priv is null\n", __func__);
  2483. return -EINVAL;
  2484. }
  2485. switch (priv->variant) {
  2486. case WCD9370_VARIANT:
  2487. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2488. break;
  2489. case WCD9375_VARIANT:
  2490. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2491. break;
  2492. default:
  2493. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2494. }
  2495. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2496. }
  2497. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2498. .read = wcd937x_variant_read,
  2499. };
  2500. /*
  2501. * wcd937x_get_codec_variant
  2502. * @component: component instance
  2503. *
  2504. * Return: codec variant or -EINVAL in error.
  2505. */
  2506. int wcd937x_get_codec_variant(struct snd_soc_component *component)
  2507. {
  2508. struct wcd937x_priv *priv = NULL;
  2509. if (!component)
  2510. return -EINVAL;
  2511. priv = snd_soc_component_get_drvdata(component);
  2512. if (!priv) {
  2513. dev_err(component->dev,
  2514. "%s:wcd937x not probed\n", __func__);
  2515. return 0;
  2516. }
  2517. return priv->variant;
  2518. }
  2519. EXPORT_SYMBOL_GPL(wcd937x_get_codec_variant);
  2520. /*
  2521. * wcd937x_info_create_codec_entry - creates wcd937x module
  2522. * @codec_root: The parent directory
  2523. * @component: component instance
  2524. *
  2525. * Creates wcd937x module, variant and version entry under the given
  2526. * parent directory.
  2527. *
  2528. * Return: 0 on success or negative error code on failure.
  2529. */
  2530. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2531. struct snd_soc_component *component)
  2532. {
  2533. struct snd_info_entry *version_entry;
  2534. struct snd_info_entry *variant_entry;
  2535. struct wcd937x_priv *priv;
  2536. struct snd_soc_card *card;
  2537. if (!codec_root || !component)
  2538. return -EINVAL;
  2539. priv = snd_soc_component_get_drvdata(component);
  2540. if (priv->entry) {
  2541. dev_dbg(priv->dev,
  2542. "%s:wcd937x module already created\n", __func__);
  2543. return 0;
  2544. }
  2545. card = component->card;
  2546. priv->entry = snd_info_create_module_entry(codec_root->module,
  2547. "wcd937x", codec_root);
  2548. if (!priv->entry) {
  2549. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2550. __func__);
  2551. return -ENOMEM;
  2552. }
  2553. priv->entry->mode = S_IFDIR | 0555;
  2554. if (snd_info_register(priv->entry) < 0) {
  2555. snd_info_free_entry(priv->entry);
  2556. return -ENOMEM;
  2557. }
  2558. version_entry = snd_info_create_card_entry(card->snd_card,
  2559. "version",
  2560. priv->entry);
  2561. if (!version_entry) {
  2562. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2563. __func__);
  2564. snd_info_free_entry(priv->entry);
  2565. return -ENOMEM;
  2566. }
  2567. version_entry->private_data = priv;
  2568. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2569. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2570. version_entry->c.ops = &wcd937x_info_ops;
  2571. if (snd_info_register(version_entry) < 0) {
  2572. snd_info_free_entry(version_entry);
  2573. snd_info_free_entry(priv->entry);
  2574. return -ENOMEM;
  2575. }
  2576. priv->version_entry = version_entry;
  2577. variant_entry = snd_info_create_card_entry(card->snd_card,
  2578. "variant",
  2579. priv->entry);
  2580. if (!variant_entry) {
  2581. dev_dbg(component->dev,
  2582. "%s: failed to create wcd937x variant entry\n",
  2583. __func__);
  2584. snd_info_free_entry(version_entry);
  2585. snd_info_free_entry(priv->entry);
  2586. return -ENOMEM;
  2587. }
  2588. variant_entry->private_data = priv;
  2589. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2590. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2591. variant_entry->c.ops = &wcd937x_variant_ops;
  2592. if (snd_info_register(variant_entry) < 0) {
  2593. snd_info_free_entry(variant_entry);
  2594. snd_info_free_entry(version_entry);
  2595. snd_info_free_entry(priv->entry);
  2596. return -ENOMEM;
  2597. }
  2598. priv->variant_entry = variant_entry;
  2599. return 0;
  2600. }
  2601. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2602. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2603. struct wcd937x_pdata *pdata)
  2604. {
  2605. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2606. int rc = 0;
  2607. if (!pdata) {
  2608. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2609. return -ENODEV;
  2610. }
  2611. /* set micbias voltage */
  2612. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2613. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2614. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2615. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2616. rc = -EINVAL;
  2617. goto done;
  2618. }
  2619. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2620. vout_ctl_1);
  2621. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2622. vout_ctl_2);
  2623. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2624. vout_ctl_3);
  2625. done:
  2626. return rc;
  2627. }
  2628. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2629. {
  2630. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2631. struct snd_soc_dapm_context *dapm =
  2632. snd_soc_component_get_dapm(component);
  2633. int variant;
  2634. int ret = -EINVAL;
  2635. dev_info(component->dev, "%s()\n", __func__);
  2636. wcd937x = snd_soc_component_get_drvdata(component);
  2637. if (!wcd937x)
  2638. return -EINVAL;
  2639. wcd937x->component = component;
  2640. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2641. devm_regmap_qti_debugfs_register(&wcd937x->tx_swr_dev->dev, wcd937x->regmap);
  2642. variant = (snd_soc_component_read(
  2643. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2644. wcd937x->variant = variant;
  2645. wcd937x->adc_count = 0;
  2646. wcd937x->fw_data = devm_kzalloc(component->dev,
  2647. sizeof(*(wcd937x->fw_data)),
  2648. GFP_KERNEL);
  2649. if (!wcd937x->fw_data) {
  2650. dev_err(component->dev, "Failed to allocate fw_data\n");
  2651. ret = -ENOMEM;
  2652. goto err;
  2653. }
  2654. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2655. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2656. WCD9XXX_CODEC_HWDEP_NODE, component);
  2657. if (ret < 0) {
  2658. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2659. goto err_hwdep;
  2660. }
  2661. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2662. if (ret) {
  2663. pr_err("%s: mbhc initialization failed\n", __func__);
  2664. goto err_hwdep;
  2665. }
  2666. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2667. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2668. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2669. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2670. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2671. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2672. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2673. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2674. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2675. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2676. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2677. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2678. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2679. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2680. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2681. snd_soc_dapm_sync(dapm);
  2682. wcd_cls_h_init(&wcd937x->clsh_info);
  2683. wcd937x_init_reg(component);
  2684. if (wcd937x->variant == WCD9375_VARIANT) {
  2685. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2686. ARRAY_SIZE(wcd9375_dapm_widgets));
  2687. if (ret < 0) {
  2688. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2689. __func__);
  2690. goto err_hwdep;
  2691. }
  2692. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2693. ARRAY_SIZE(wcd9375_audio_map));
  2694. if (ret < 0) {
  2695. dev_err(component->dev, "%s: Failed to add routes\n",
  2696. __func__);
  2697. goto err_hwdep;
  2698. }
  2699. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2700. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2701. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2702. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2703. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2704. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2705. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2706. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2707. snd_soc_dapm_sync(dapm);
  2708. }
  2709. wcd937x->version = WCD937X_VERSION_1_0;
  2710. /* Register event notifier */
  2711. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2712. if (wcd937x->register_notifier) {
  2713. ret = wcd937x->register_notifier(wcd937x->handle,
  2714. &wcd937x->nblock,
  2715. true);
  2716. if (ret) {
  2717. dev_err(component->dev,
  2718. "%s: Failed to register notifier %d\n",
  2719. __func__, ret);
  2720. return ret;
  2721. }
  2722. }
  2723. return ret;
  2724. err_hwdep:
  2725. wcd937x->fw_data = NULL;
  2726. err:
  2727. return ret;
  2728. }
  2729. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2730. {
  2731. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2732. if (!wcd937x)
  2733. return;
  2734. if (wcd937x->register_notifier)
  2735. wcd937x->register_notifier(wcd937x->handle,
  2736. &wcd937x->nblock,
  2737. false);
  2738. return;
  2739. }
  2740. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2741. .name = WCD937X_DRV_NAME,
  2742. .probe = wcd937x_soc_codec_probe,
  2743. .remove = wcd937x_soc_codec_remove,
  2744. .controls = wcd937x_snd_controls,
  2745. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2746. .dapm_widgets = wcd937x_dapm_widgets,
  2747. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2748. .dapm_routes = wcd937x_audio_map,
  2749. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2750. };
  2751. #ifdef CONFIG_PM_SLEEP
  2752. static int wcd937x_suspend(struct device *dev)
  2753. {
  2754. struct wcd937x_priv *wcd937x = NULL;
  2755. int ret = 0;
  2756. struct wcd937x_pdata *pdata = NULL;
  2757. if (!dev)
  2758. return -ENODEV;
  2759. wcd937x = dev_get_drvdata(dev);
  2760. if (!wcd937x)
  2761. return -EINVAL;
  2762. pdata = dev_get_platdata(wcd937x->dev);
  2763. if (!pdata) {
  2764. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2765. return -EINVAL;
  2766. }
  2767. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2768. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2769. wcd937x->supplies,
  2770. pdata->regulator,
  2771. pdata->num_supplies,
  2772. "cdc-vdd-buck");
  2773. if (ret == -EINVAL) {
  2774. dev_err(dev, "%s: vdd buck is not disabled\n",
  2775. __func__);
  2776. return 0;
  2777. }
  2778. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2779. }
  2780. return 0;
  2781. }
  2782. static int wcd937x_resume(struct device *dev)
  2783. {
  2784. return 0;
  2785. }
  2786. #endif
  2787. static int wcd937x_reset(struct device *dev)
  2788. {
  2789. struct wcd937x_priv *wcd937x = NULL;
  2790. int rc = 0;
  2791. int value = 0;
  2792. if (!dev)
  2793. return -ENODEV;
  2794. wcd937x = dev_get_drvdata(dev);
  2795. if (!wcd937x)
  2796. return -EINVAL;
  2797. if (!wcd937x->rst_np) {
  2798. dev_err(dev, "%s: reset gpio device node not specified\n",
  2799. __func__);
  2800. return -EINVAL;
  2801. }
  2802. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2803. if (value > 0)
  2804. return 0;
  2805. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2806. if (rc) {
  2807. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2808. __func__);
  2809. return -EPROBE_DEFER;
  2810. }
  2811. /* 20ms sleep required after pulling the reset gpio to LOW */
  2812. usleep_range(20, 30);
  2813. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2814. if (rc) {
  2815. dev_err(dev, "%s: wcd active state request fail!\n",
  2816. __func__);
  2817. return -EPROBE_DEFER;
  2818. }
  2819. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2820. usleep_range(20, 30);
  2821. return rc;
  2822. }
  2823. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2824. u32 *val)
  2825. {
  2826. int rc = 0;
  2827. rc = of_property_read_u32(dev->of_node, name, val);
  2828. if (rc)
  2829. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2830. __func__, name, dev->of_node->full_name);
  2831. return rc;
  2832. }
  2833. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2834. struct wcd937x_micbias_setting *mb)
  2835. {
  2836. u32 prop_val = 0;
  2837. int rc = 0;
  2838. /* MB1 */
  2839. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2840. NULL)) {
  2841. rc = wcd937x_read_of_property_u32(dev,
  2842. "qcom,cdc-micbias1-mv",
  2843. &prop_val);
  2844. if (!rc)
  2845. mb->micb1_mv = prop_val;
  2846. } else {
  2847. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2848. __func__);
  2849. }
  2850. /* MB2 */
  2851. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2852. NULL)) {
  2853. rc = wcd937x_read_of_property_u32(dev,
  2854. "qcom,cdc-micbias2-mv",
  2855. &prop_val);
  2856. if (!rc)
  2857. mb->micb2_mv = prop_val;
  2858. } else {
  2859. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2860. __func__);
  2861. }
  2862. /* MB3 */
  2863. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2864. NULL)) {
  2865. rc = wcd937x_read_of_property_u32(dev,
  2866. "qcom,cdc-micbias3-mv",
  2867. &prop_val);
  2868. if (!rc)
  2869. mb->micb3_mv = prop_val;
  2870. } else {
  2871. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2872. __func__);
  2873. }
  2874. }
  2875. static int wcd937x_reset_low(struct device *dev)
  2876. {
  2877. struct wcd937x_priv *wcd937x = NULL;
  2878. int rc = 0;
  2879. if (!dev)
  2880. return -ENODEV;
  2881. wcd937x = dev_get_drvdata(dev);
  2882. if (!wcd937x)
  2883. return -EINVAL;
  2884. if (!wcd937x->rst_np) {
  2885. dev_err(dev, "%s: reset gpio device node not specified\n",
  2886. __func__);
  2887. return -EINVAL;
  2888. }
  2889. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2890. if (rc) {
  2891. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2892. __func__);
  2893. return rc;
  2894. }
  2895. /* 20ms sleep required after pulling the reset gpio to LOW */
  2896. usleep_range(20, 30);
  2897. return rc;
  2898. }
  2899. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2900. {
  2901. struct wcd937x_pdata *pdata = NULL;
  2902. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2903. GFP_KERNEL);
  2904. if (!pdata)
  2905. return NULL;
  2906. pdata->rst_np = of_parse_phandle(dev->of_node,
  2907. "qcom,wcd-rst-gpio-node", 0);
  2908. if (!pdata->rst_np) {
  2909. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2910. __func__, "qcom,wcd-rst-gpio-node",
  2911. dev->of_node->full_name);
  2912. return NULL;
  2913. }
  2914. /* Parse power supplies */
  2915. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2916. &pdata->num_supplies);
  2917. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2918. dev_err(dev, "%s: no power supplies defined for codec\n",
  2919. __func__);
  2920. return NULL;
  2921. }
  2922. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2923. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2924. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2925. return pdata;
  2926. }
  2927. static int wcd937x_wakeup(void *handle, bool enable)
  2928. {
  2929. struct wcd937x_priv *priv;
  2930. if (!handle) {
  2931. pr_err("%s: NULL handle\n", __func__);
  2932. return -EINVAL;
  2933. }
  2934. priv = (struct wcd937x_priv *)handle;
  2935. if (!priv->tx_swr_dev) {
  2936. pr_err("%s: tx swr dev is NULL\n", __func__);
  2937. return -EINVAL;
  2938. }
  2939. if (enable)
  2940. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2941. else
  2942. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2943. }
  2944. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2945. {
  2946. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2947. __func__, irq);
  2948. return IRQ_HANDLED;
  2949. }
  2950. static int wcd937x_bind(struct device *dev)
  2951. {
  2952. int ret = 0, i = 0;
  2953. struct wcd937x_priv *wcd937x = NULL;
  2954. struct wcd937x_pdata *pdata = NULL;
  2955. struct wcd_ctrl_platform_data *plat_data = NULL;
  2956. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2957. if (!wcd937x)
  2958. return -ENOMEM;
  2959. dev_set_drvdata(dev, wcd937x);
  2960. pdata = wcd937x_populate_dt_data(dev);
  2961. if (!pdata) {
  2962. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2963. return -EINVAL;
  2964. }
  2965. wcd937x->dev = dev;
  2966. wcd937x->dev->platform_data = pdata;
  2967. wcd937x->rst_np = pdata->rst_np;
  2968. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2969. pdata->regulator, pdata->num_supplies);
  2970. if (!wcd937x->supplies) {
  2971. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2972. __func__);
  2973. goto err_bind_all;
  2974. }
  2975. plat_data = dev_get_platdata(dev->parent);
  2976. if (!plat_data) {
  2977. dev_err(dev, "%s: platform data from parent is NULL\n",
  2978. __func__);
  2979. ret = -EINVAL;
  2980. goto err_bind_all;
  2981. }
  2982. wcd937x->handle = (void *)plat_data->handle;
  2983. if (!wcd937x->handle) {
  2984. dev_err(dev, "%s: handle is NULL\n", __func__);
  2985. ret = -EINVAL;
  2986. goto err_bind_all;
  2987. }
  2988. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2989. if (!wcd937x->update_wcd_event) {
  2990. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2991. __func__);
  2992. ret = -EINVAL;
  2993. goto err_bind_all;
  2994. }
  2995. wcd937x->register_notifier = plat_data->register_notifier;
  2996. if (!wcd937x->register_notifier) {
  2997. dev_err(dev, "%s: register_notifier api is null!\n",
  2998. __func__);
  2999. ret = -EINVAL;
  3000. goto err_bind_all;
  3001. }
  3002. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  3003. pdata->regulator,
  3004. pdata->num_supplies);
  3005. if (ret) {
  3006. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3007. __func__);
  3008. goto err_bind_all;
  3009. }
  3010. ret = wcd937x_reset(dev);
  3011. if (ret == -EPROBE_DEFER) {
  3012. dev_err(dev, "%s: wcd reset failed!\n", __func__);
  3013. goto err_bind_all;
  3014. }
  3015. /*
  3016. * Add 5msec delay to provide sufficient time for
  3017. * soundwire auto enumeration of slave devices as
  3018. * as per HW requirement.
  3019. */
  3020. usleep_range(5000, 5010);
  3021. wcd937x->wakeup = wcd937x_wakeup;
  3022. ret = component_bind_all(dev, wcd937x);
  3023. if (ret) {
  3024. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3025. __func__, ret);
  3026. goto err_bind_all;
  3027. }
  3028. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  3029. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  3030. if (ret) {
  3031. dev_err(dev, "Failed to read port mapping\n");
  3032. goto err;
  3033. }
  3034. ret = wcd937x_parse_port_params(dev, "qcom,swr-tx-port-params",
  3035. CODEC_TX);
  3036. if (ret) {
  3037. dev_err(dev, "Failed to read port params\n");
  3038. goto err;
  3039. }
  3040. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3041. if (!wcd937x->rx_swr_dev) {
  3042. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3043. __func__);
  3044. ret = -ENODEV;
  3045. goto err;
  3046. }
  3047. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3048. if (!wcd937x->tx_swr_dev) {
  3049. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3050. __func__);
  3051. ret = -ENODEV;
  3052. goto err;
  3053. }
  3054. swr_init_port_params(wcd937x->tx_swr_dev, SWR_NUM_PORTS,
  3055. wcd937x->swr_tx_port_params);
  3056. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  3057. &wcd937x_regmap_config);
  3058. if (!wcd937x->regmap) {
  3059. dev_err(dev, "%s: Regmap init failed\n",
  3060. __func__);
  3061. goto err;
  3062. }
  3063. /* Set all interupts as edge triggered */
  3064. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  3065. regmap_write(wcd937x->regmap,
  3066. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3067. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  3068. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  3069. wcd937x->irq_info.codec_name = "WCD937X";
  3070. wcd937x->irq_info.regmap = wcd937x->regmap;
  3071. wcd937x->irq_info.dev = dev;
  3072. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  3073. if (ret) {
  3074. dev_err(dev, "%s: IRQ init failed: %d\n",
  3075. __func__, ret);
  3076. goto err;
  3077. }
  3078. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  3079. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  3080. if (ret < 0) {
  3081. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3082. goto err_irq;
  3083. }
  3084. /* default L1 power setting */
  3085. wcd937x->tx_ch_pwr[0] = 1;
  3086. wcd937x->tx_ch_pwr[1] = 1;
  3087. mutex_init(&wcd937x->micb_lock);
  3088. mutex_init(&wcd937x->ana_tx_clk_lock);
  3089. /* Request for watchdog interrupt */
  3090. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  3091. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  3092. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  3093. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  3094. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  3095. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  3096. /* Disable watchdog interrupt for HPH and AUX */
  3097. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  3098. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  3099. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  3100. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  3101. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  3102. if (ret) {
  3103. dev_err(dev, "%s: Codec registration failed\n",
  3104. __func__);
  3105. goto err_irq;
  3106. }
  3107. return ret;
  3108. err_irq:
  3109. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  3110. err:
  3111. component_unbind_all(dev, wcd937x);
  3112. err_bind_all:
  3113. dev_set_drvdata(dev, NULL);
  3114. kfree(pdata);
  3115. kfree(wcd937x);
  3116. return ret;
  3117. }
  3118. static void wcd937x_unbind(struct device *dev)
  3119. {
  3120. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  3121. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  3122. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  3123. snd_soc_unregister_component(dev);
  3124. component_unbind_all(dev, wcd937x);
  3125. mutex_destroy(&wcd937x->micb_lock);
  3126. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  3127. dev_set_drvdata(dev, NULL);
  3128. kfree(pdata);
  3129. kfree(wcd937x);
  3130. }
  3131. static const struct of_device_id wcd937x_dt_match[] = {
  3132. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  3133. {}
  3134. };
  3135. static const struct component_master_ops wcd937x_comp_ops = {
  3136. .bind = wcd937x_bind,
  3137. .unbind = wcd937x_unbind,
  3138. };
  3139. static int wcd937x_compare_of(struct device *dev, void *data)
  3140. {
  3141. return dev->of_node == data;
  3142. }
  3143. static void wcd937x_release_of(struct device *dev, void *data)
  3144. {
  3145. of_node_put(data);
  3146. }
  3147. static int wcd937x_add_slave_components(struct device *dev,
  3148. struct component_match **matchptr)
  3149. {
  3150. struct device_node *np, *rx_node, *tx_node;
  3151. np = dev->of_node;
  3152. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3153. if (!rx_node) {
  3154. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3155. return -ENODEV;
  3156. }
  3157. of_node_get(rx_node);
  3158. component_match_add_release(dev, matchptr,
  3159. wcd937x_release_of,
  3160. wcd937x_compare_of,
  3161. rx_node);
  3162. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3163. if (!tx_node) {
  3164. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3165. return -ENODEV;
  3166. }
  3167. of_node_get(tx_node);
  3168. component_match_add_release(dev, matchptr,
  3169. wcd937x_release_of,
  3170. wcd937x_compare_of,
  3171. tx_node);
  3172. return 0;
  3173. }
  3174. static int wcd937x_probe(struct platform_device *pdev)
  3175. {
  3176. struct component_match *match = NULL;
  3177. int ret;
  3178. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  3179. if (ret)
  3180. return ret;
  3181. return component_master_add_with_match(&pdev->dev,
  3182. &wcd937x_comp_ops, match);
  3183. }
  3184. static int wcd937x_remove(struct platform_device *pdev)
  3185. {
  3186. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  3187. dev_set_drvdata(&pdev->dev, NULL);
  3188. return 0;
  3189. }
  3190. #ifdef CONFIG_PM_SLEEP
  3191. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  3192. SET_SYSTEM_SLEEP_PM_OPS(
  3193. wcd937x_suspend,
  3194. wcd937x_resume
  3195. )
  3196. };
  3197. #endif
  3198. static struct platform_driver wcd937x_codec_driver = {
  3199. .probe = wcd937x_probe,
  3200. .remove = wcd937x_remove,
  3201. .driver = {
  3202. .name = "wcd937x_codec",
  3203. .owner = THIS_MODULE,
  3204. .of_match_table = of_match_ptr(wcd937x_dt_match),
  3205. #ifdef CONFIG_PM_SLEEP
  3206. .pm = &wcd937x_dev_pm_ops,
  3207. #endif
  3208. .suppress_bind_attrs = true,
  3209. },
  3210. };
  3211. module_platform_driver(wcd937x_codec_driver);
  3212. MODULE_DESCRIPTION("WCD937X Codec driver");
  3213. MODULE_LICENSE("GPL v2");