sde_encoder.h 28 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788
  1. /*
  2. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef __SDE_ENCODER_H__
  20. #define __SDE_ENCODER_H__
  21. #include <drm/drm_crtc.h>
  22. #include <drm/drm_bridge.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_prop.h"
  25. #include "sde_hw_mdss.h"
  26. #include "sde_kms.h"
  27. #include "sde_connector.h"
  28. #include "sde_power_handle.h"
  29. /*
  30. * Two to anticipate panels that can do cmd/vid dynamic switching
  31. * plan is to create all possible physical encoder types, and switch between
  32. * them at runtime
  33. */
  34. #define NUM_PHYS_ENCODER_TYPES 2
  35. #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
  36. (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
  37. #define MAX_CHANNELS_PER_ENC 4
  38. #define SDE_ENCODER_FRAME_EVENT_DONE BIT(0)
  39. #define SDE_ENCODER_FRAME_EVENT_ERROR BIT(1)
  40. #define SDE_ENCODER_FRAME_EVENT_PANEL_DEAD BIT(2)
  41. #define SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE BIT(3)
  42. #define SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE BIT(4)
  43. #define SDE_ENCODER_FRAME_EVENT_CWB_DONE BIT(5)
  44. #define IDLE_POWERCOLLAPSE_DURATION (66 - 16/2)
  45. #define IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP (200 - 16/2)
  46. /* below this fps limit, timeouts are adjusted based on fps */
  47. #define DEFAULT_TIMEOUT_FPS_THRESHOLD 24
  48. #define SDE_ENC_IRQ_REGISTERED(phys_enc, idx) \
  49. ((!(phys_enc) || ((idx) < 0) || ((idx) >= INTR_IDX_MAX)) ? \
  50. 0 : ((phys_enc)->irq[(idx)].irq_idx >= 0))
  51. #define DEFAULT_MIN_FPS 10
  52. /**
  53. * Encoder functions and data types
  54. * @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused
  55. * @wbs: Writebacks this encoder is using, INTF_MODE_NONE if unused
  56. * @needs_cdm: Encoder requests a CDM based on pixel format conversion needs
  57. * @display_num_of_h_tiles: Number of horizontal tiles in case of split
  58. * interface
  59. * @display_type: Type of the display
  60. * @topology: Topology of the display
  61. * @comp_info: Compression parameters information
  62. */
  63. struct sde_encoder_hw_resources {
  64. enum sde_intf_mode intfs[INTF_MAX];
  65. enum sde_intf_mode wbs[WB_MAX];
  66. bool needs_cdm;
  67. u32 display_num_of_h_tiles;
  68. enum sde_connector_display display_type;
  69. struct msm_display_topology topology;
  70. struct msm_compression_info *comp_info;
  71. };
  72. /**
  73. * sde_encoder_kickoff_params - info encoder requires at kickoff
  74. * @affected_displays: bitmask, bit set means the ROI of the commit lies within
  75. * the bounds of the physical display at the bit index
  76. * @recovery_events_enabled: indicates status of client for recoovery events
  77. * @frame_trigger_mode: indicates frame trigger mode
  78. */
  79. struct sde_encoder_kickoff_params {
  80. unsigned long affected_displays;
  81. bool recovery_events_enabled;
  82. enum frame_trigger_mode_type frame_trigger_mode;
  83. };
  84. /*
  85. * enum sde_enc_rc_states - states that the resource control maintains
  86. * @SDE_ENC_RC_STATE_OFF: Resource is in OFF state
  87. * @SDE_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
  88. * @SDE_ENC_RC_STATE_ON: Resource is in ON state
  89. * @SDE_ENC_RC_STATE_MODESET: Resource is in modeset state
  90. * @SDE_ENC_RC_STATE_IDLE: Resource is in IDLE state
  91. */
  92. enum sde_enc_rc_states {
  93. SDE_ENC_RC_STATE_OFF,
  94. SDE_ENC_RC_STATE_PRE_OFF,
  95. SDE_ENC_RC_STATE_ON,
  96. SDE_ENC_RC_STATE_MODESET,
  97. SDE_ENC_RC_STATE_IDLE
  98. };
  99. /*
  100. * enum sde_sim_qsync_frame - simulated QSYNC frame type
  101. * @SDE_SIM_QSYNC_FRAME_NOMINAL: Frame is triggered early and TE must come at nominal frame rate.
  102. * @SDE_SIM_QSYNC_FRAME_EARLY_OR_LATE: Frame could be triggered early or late and TE must adjust
  103. * accordingly.
  104. * @SDE_SIM_QSYNC_FRAME_TIMEOUT: Frame is triggered too late and TE must adjust to the
  105. * minimum QSYNC FPS.
  106. */
  107. enum sde_sim_qsync_frame {
  108. SDE_SIM_QSYNC_FRAME_NOMINAL,
  109. SDE_SIM_QSYNC_FRAME_EARLY_OR_LATE,
  110. SDE_SIM_QSYNC_FRAME_TIMEOUT
  111. };
  112. /*
  113. * enum sde_sim_qsync_event - events that simulates a QSYNC panel
  114. * @SDE_SIM_QSYNC_EVENT_FRAME_DETECTED: Event when DDIC is detecting a frame.
  115. * @SDE_SIM_QSYNC_EVENT_TE_TRIGGER: Event when DDIC is triggering TE signal.
  116. */
  117. enum sde_sim_qsync_event {
  118. SDE_SIM_QSYNC_EVENT_FRAME_DETECTED,
  119. SDE_SIM_QSYNC_EVENT_TE_TRIGGER
  120. };
  121. /* Frame rate value to trigger the watchdog TE in 200 us */
  122. #define SDE_SIM_QSYNC_IMMEDIATE_FPS 5000
  123. /**
  124. * struct sde_encoder_virt - virtual encoder. Container of one or more physical
  125. * encoders. Virtual encoder manages one "logical" display. Physical
  126. * encoders manage one intf block, tied to a specific panel/sub-panel.
  127. * Virtual encoder defers as much as possible to the physical encoders.
  128. * Virtual encoder registers itself with the DRM Framework as the encoder.
  129. * @base: drm_encoder base class for registration with DRM
  130. * @enc_spin_lock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
  131. * @bus_scaling_client: Client handle to the bus scaling interface
  132. * @te_source: vsync source pin information
  133. * @num_phys_encs: Actual number of physical encoders contained.
  134. * @phys_encs: Container of physical encoders managed.
  135. * @phys_vid_encs: Video physical encoders for panel mode switch.
  136. * @phys_cmd_encs: Command physical encoders for panel mode switch.
  137. * @cur_master: Pointer to the current master in this mode. Optimization
  138. * Only valid after enable. Cleared as disable.
  139. * @hw_pp Handle to the pingpong blocks used for the display. No.
  140. * pingpong blocks can be different than num_phys_encs.
  141. * @hw_dsc: Array of DSC block handles used for the display.
  142. * @hw_vdc: Array of VDC block handles used for the display.
  143. * @dirty_dsc_ids: Cached dsc indexes for dirty DSC blocks needing flush
  144. * @intfs_swapped Whether or not the phys_enc interfaces have been swapped
  145. * for partial update right-only cases, such as pingpong
  146. * split where virtual pingpong does not generate IRQs
  147. * @qdss_status: indicate if qdss is modified since last update
  148. * @crtc_vblank_cb: Callback into the upper layer / CRTC for
  149. * notification of the VBLANK
  150. * @crtc_vblank_cb_data: Data from upper layer for VBLANK notification
  151. * @crtc_kickoff_cb: Callback into CRTC that will flush & start
  152. * all CTL paths
  153. * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb
  154. * @debugfs_root: Debug file system root file node
  155. * @enc_lock: Lock around physical encoder create/destroy and
  156. access.
  157. * @frame_done_cnt: Atomic counter for tracking which phys_enc is
  158. * done with frame processing
  159. * @crtc_frame_event_cb: callback handler for frame event
  160. * @crtc_frame_event_cb_data: callback handler private data
  161. * @rsc_client: rsc client pointer
  162. * @rsc_state_init: boolean to indicate rsc config init
  163. * @disp_info: local copy of msm_display_info struct
  164. * @misr_enable: misr enable/disable status
  165. * @misr_reconfigure: boolean entry indicates misr reconfigure status
  166. * @misr_frame_count: misr frame count before start capturing the data
  167. * @idle_pc_enabled: indicate if idle power collapse is enabled
  168. * currently. This can be controlled by user-mode
  169. * @restore_te_rd_ptr: flag to indicate that te read pointer value must
  170. * be restored after idle power collapse
  171. * @rc_lock: resource control mutex lock to protect
  172. * virt encoder over various state changes
  173. * @rc_state: resource controller state
  174. * @delayed_off_work: delayed worker to schedule disabling of
  175. * clks and resources after IDLE_TIMEOUT time.
  176. * @early_wakeup_work: worker to handle early wakeup event
  177. * @input_event_work: worker to handle input device touch events
  178. * @esd_trigger_work: worker to handle esd trigger events
  179. * @input_handler: handler for input device events
  180. * @topology: topology of the display
  181. * @vblank_enabled: boolean to track userspace vblank vote
  182. * @idle_pc_restore: flag to indicate idle_pc_restore happened
  183. * @frame_trigger_mode: frame trigger mode indication for command mode
  184. * display
  185. * @dynamic_hdr_updated: flag to indicate if mempool was unchanged
  186. * @rsc_config: rsc configuration for display vtotal, fps, etc.
  187. * @cur_conn_roi: current connector roi
  188. * @prv_conn_roi: previous connector roi to optimize if unchanged
  189. * @crtc pointer to drm_crtc
  190. * @fal10_veto_override: software override for micro idle fal10 veto
  191. * @recovery_events_enabled: status of hw recovery feature enable by client
  192. * @elevated_ahb_vote: increase AHB bus speed for the first frame
  193. * after power collapse
  194. * @pm_qos_cpu_req: qos request for all cpu core frequency
  195. * @valid_cpu_mask: actual voted cpu core mask
  196. * @mode_info: stores the current mode and should be used
  197. * only in commit phase
  198. * @delay_kickoff boolean to delay the kickoff, used in case
  199. * of esd attack to ensure esd workqueue detects
  200. * the previous frame transfer completion before
  201. * next update is triggered.
  202. * @autorefresh_solver_disable It tracks if solver state is disabled from this
  203. * encoder due to autorefresh concurrency.
  204. * @ctl_done_supported boolean flag to indicate the availability of
  205. * ctl done irq support for the hardware
  206. * @dynamic_irqs_config bitmask config to enable encoder dynamic irqs
  207. */
  208. struct sde_encoder_virt {
  209. struct drm_encoder base;
  210. spinlock_t enc_spinlock;
  211. struct mutex vblank_ctl_lock;
  212. uint32_t bus_scaling_client;
  213. uint32_t display_num_of_h_tiles;
  214. uint32_t te_source;
  215. unsigned int num_phys_encs;
  216. struct sde_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
  217. struct sde_encoder_phys *phys_vid_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
  218. struct sde_encoder_phys *phys_cmd_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
  219. struct sde_encoder_phys *cur_master;
  220. struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
  221. struct sde_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
  222. struct sde_hw_vdc *hw_vdc[MAX_CHANNELS_PER_ENC];
  223. struct sde_hw_pingpong *hw_dsc_pp[MAX_CHANNELS_PER_ENC];
  224. enum sde_dsc dirty_dsc_ids[MAX_CHANNELS_PER_ENC];
  225. enum sde_vdc dirty_vdc_ids[MAX_CHANNELS_PER_ENC];
  226. bool intfs_swapped;
  227. bool qdss_status;
  228. void (*crtc_vblank_cb)(void *data, ktime_t ts);
  229. void *crtc_vblank_cb_data;
  230. struct dentry *debugfs_root;
  231. struct mutex enc_lock;
  232. atomic_t frame_done_cnt[MAX_PHYS_ENCODERS_PER_VIRTUAL];
  233. void (*crtc_frame_event_cb)(void *data, u32 event, ktime_t ts);
  234. struct sde_kms_frame_event_cb_data crtc_frame_event_cb_data;
  235. struct sde_rsc_client *rsc_client;
  236. bool rsc_state_init;
  237. struct msm_display_info disp_info;
  238. atomic_t misr_enable;
  239. bool misr_reconfigure;
  240. u32 misr_frame_count;
  241. bool idle_pc_enabled;
  242. bool input_event_enabled;
  243. struct mutex rc_lock;
  244. enum sde_enc_rc_states rc_state;
  245. struct kthread_delayed_work delayed_off_work;
  246. struct kthread_work early_wakeup_work;
  247. struct kthread_work input_event_work;
  248. struct kthread_work esd_trigger_work;
  249. struct input_handler *input_handler;
  250. bool vblank_enabled;
  251. bool idle_pc_restore;
  252. bool restore_te_rd_ptr;
  253. enum frame_trigger_mode_type frame_trigger_mode;
  254. bool dynamic_hdr_updated;
  255. struct sde_rsc_cmd_config rsc_config;
  256. struct sde_rect cur_conn_roi;
  257. struct sde_rect prv_conn_roi;
  258. struct drm_crtc *crtc;
  259. bool fal10_veto_override;
  260. bool recovery_events_enabled;
  261. bool elevated_ahb_vote;
  262. struct dev_pm_qos_request pm_qos_cpu_req[NR_CPUS];
  263. struct cpumask valid_cpu_mask;
  264. struct msm_mode_info mode_info;
  265. bool delay_kickoff;
  266. bool autorefresh_solver_disable;
  267. bool ctl_done_supported;
  268. unsigned long dynamic_irqs_config;
  269. };
  270. #define to_sde_encoder_virt(x) container_of(x, struct sde_encoder_virt, base)
  271. /**
  272. * sde_encoder_get_hw_resources - Populate table of required hardware resources
  273. * @encoder: encoder pointer
  274. * @hw_res: resource table to populate with encoder required resources
  275. * @conn_state: report hw reqs based on this proposed connector state
  276. */
  277. void sde_encoder_get_hw_resources(struct drm_encoder *encoder,
  278. struct sde_encoder_hw_resources *hw_res,
  279. struct drm_connector_state *conn_state);
  280. /**
  281. * sde_encoder_early_wakeup - early wake up display
  282. * @encoder: encoder pointer
  283. */
  284. void sde_encoder_early_wakeup(struct drm_encoder *drm_enc);
  285. /**
  286. * sde_encoder_register_vblank_callback - provide callback to encoder that
  287. * will be called on the next vblank.
  288. * @encoder: encoder pointer
  289. * @cb: callback pointer, provide NULL to deregister and disable IRQs
  290. * @data: user data provided to callback
  291. */
  292. void sde_encoder_register_vblank_callback(struct drm_encoder *encoder,
  293. void (*cb)(void *, ktime_t), void *data);
  294. /**
  295. * sde_encoder_register_frame_event_callback - provide callback to encoder that
  296. * will be called after the request is complete, or other events.
  297. * @encoder: encoder pointer
  298. * @cb: callback pointer, provide NULL to deregister
  299. * @crtc: pointer to drm_crtc object interested in frame events
  300. */
  301. void sde_encoder_register_frame_event_callback(struct drm_encoder *encoder,
  302. void (*cb)(void *, u32, ktime_t), struct drm_crtc *crtc);
  303. /**
  304. * sde_encoder_get_rsc_client - gets the rsc client state for primary
  305. * for primary display.
  306. * @encoder: encoder pointer
  307. */
  308. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *encoder);
  309. /**
  310. * sde_encoder_poll_line_counts - poll encoder line counts for start of frame
  311. * @encoder: encoder pointer
  312. * @Returns: zero on success
  313. */
  314. int sde_encoder_poll_line_counts(struct drm_encoder *encoder);
  315. /**
  316. * sde_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl
  317. * path (i.e. ctl flush and start) at next appropriate time.
  318. * Immediately: if no previous commit is outstanding.
  319. * Delayed: Block until next trigger can be issued.
  320. * @encoder: encoder pointer
  321. * @params: kickoff time parameters
  322. * @Returns: Zero on success, last detected error otherwise
  323. */
  324. int sde_encoder_prepare_for_kickoff(struct drm_encoder *encoder,
  325. struct sde_encoder_kickoff_params *params);
  326. /**
  327. * sde_encoder_trigger_kickoff_pending - Clear the flush bits from previous
  328. * kickoff and trigger the ctl prepare progress for command mode display.
  329. * @encoder: encoder pointer
  330. */
  331. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *encoder);
  332. /**
  333. * sde_encoder_kickoff - trigger a double buffer flip of the ctl path
  334. * (i.e. ctl flush and start) immediately.
  335. * @encoder: encoder pointer
  336. * @config_changed: if true new configuration is applied on the control path
  337. */
  338. void sde_encoder_kickoff(struct drm_encoder *encoder, bool config_changed);
  339. /**
  340. * sde_encoder_wait_for_event - Waits for encoder events
  341. * @encoder: encoder pointer
  342. * @event: event to wait for
  343. * MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pending
  344. * frames to hardware at a vblank or wr_ptr_start
  345. * Encoders will map this differently depending on the
  346. * panel type.
  347. * vid mode -> vsync_irq
  348. * cmd mode -> wr_ptr_start_irq
  349. * MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels to
  350. * the panel. Encoders will map this differently
  351. * depending on the panel type.
  352. * vid mode -> vsync_irq
  353. * cmd mode -> pp_done
  354. * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
  355. */
  356. int sde_encoder_wait_for_event(struct drm_encoder *drm_encoder,
  357. enum msm_event_wait event);
  358. /**
  359. * sde_encoder_idle_request - request for idle request to avoid 4 vsync cycle
  360. * to turn off the clocks.
  361. * @encoder: encoder pointer
  362. * Returns: 0 on success, errorcode otherwise
  363. */
  364. int sde_encoder_idle_request(struct drm_encoder *drm_enc);
  365. /*
  366. * sde_encoder_get_fps - get interface frame rate of the given encoder
  367. * @encoder: Pointer to drm encoder object
  368. */
  369. u32 sde_encoder_get_fps(struct drm_encoder *encoder);
  370. /*
  371. * sde_encoder_get_intf_mode - get interface mode of the given encoder
  372. * @encoder: Pointer to drm encoder object
  373. */
  374. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder);
  375. /*
  376. * sde_encoder_get_frame_count - get hardware frame count of the given encoder
  377. * @encoder: Pointer to drm encoder object
  378. */
  379. u32 sde_encoder_get_frame_count(struct drm_encoder *encoder);
  380. /**
  381. * sde_encoder_get_avr_status - get combined avr_status from all intfs for given virt encoder
  382. * @drm_enc: Pointer to drm encoder structure
  383. */
  384. int sde_encoder_get_avr_status(struct drm_encoder *drm_enc);
  385. /*
  386. * sde_encoder_get_vblank_timestamp - get the last vsync timestamp
  387. * @encoder: Pointer to drm encoder object
  388. * @tvblank: vblank timestamp
  389. */
  390. bool sde_encoder_get_vblank_timestamp(struct drm_encoder *encoder,
  391. ktime_t *tvblank);
  392. /**
  393. * sde_encoder_idle_pc_enter - control enable/disable VSYNC_IN_EN & cache display status at ipc
  394. * @encoder: encoder pointer
  395. */
  396. void sde_encoder_idle_pc_enter(struct drm_encoder *encoder);
  397. /**
  398. * sde_encoder_virt_restore - restore the encoder configs
  399. * @encoder: encoder pointer
  400. */
  401. void sde_encoder_virt_restore(struct drm_encoder *encoder);
  402. /**
  403. * sde_encoder_is_dsc_merge - check if encoder is in DSC merge mode
  404. * @drm_enc: Pointer to drm encoder object
  405. * @Return: true if encoder is in DSC merge mode
  406. */
  407. bool sde_encoder_is_dsc_merge(struct drm_encoder *drm_enc);
  408. /**
  409. * sde_encoder_check_curr_mode - check if given mode is supported or not
  410. * @drm_enc: Pointer to drm encoder object
  411. * @mode: Mode to be checked
  412. * @Return: true if it is cmd mode
  413. */
  414. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode);
  415. /**
  416. * sde_encoder_init - initialize virtual encoder object
  417. * @dev: Pointer to drm device structure
  418. * @disp_info: Pointer to display information structure
  419. * Returns: Pointer to newly created drm encoder
  420. */
  421. struct drm_encoder *sde_encoder_init(
  422. struct drm_device *dev,
  423. struct msm_display_info *disp_info);
  424. /**
  425. * sde_encoder_destroy - destroy previously initialized virtual encoder
  426. * @drm_enc: Pointer to previously created drm encoder structure
  427. */
  428. void sde_encoder_destroy(struct drm_encoder *drm_enc);
  429. /**
  430. * sde_encoder_prepare_commit - prepare encoder at the very beginning of an
  431. * atomic commit, before any registers are written
  432. * @drm_enc: Pointer to previously created drm encoder structure
  433. */
  434. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc);
  435. /**
  436. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  437. * device bootup when cont_splash is enabled
  438. * @drm_enc: Pointer to drm encoder structure
  439. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  440. * @enable: boolean indicates enable or displae state of splash
  441. * @Return: true if successful in updating the encoder structure
  442. */
  443. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  444. struct sde_splash_display *splash_display, bool enable);
  445. /**
  446. * sde_encoder_display_failure_notification - update sde encoder state for
  447. * esd timeout or other display failure notification. This event flows from
  448. * dsi, sde_connector to sde_encoder.
  449. *
  450. * This api must not be called from crtc_commit (display) thread because it
  451. * requests the flush work on same thread. It is called from esd check thread
  452. * based on current design.
  453. *
  454. * TODO: manage the event at sde_kms level for forward processing.
  455. * @drm_enc: Pointer to drm encoder structure
  456. * @skip_pre_kickoff: Caller can avoid pre_kickoff if it is triggering this
  457. * event only to switch the panel TE to watchdog mode.
  458. * @Return: true if successful in updating the encoder structure
  459. */
  460. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  461. bool skip_pre_kickoff);
  462. /**
  463. * sde_encoder_recovery_events_enabled - checks if client has enabled
  464. * sw recovery mechanism for this connector
  465. * @drm_enc: Pointer to drm encoder structure
  466. * @Return: true if enabled
  467. */
  468. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder);
  469. /**
  470. * sde_encoder_enable_recovery_event - handler to enable the sw recovery
  471. * for this connector
  472. * @drm_enc: Pointer to drm encoder structure
  473. */
  474. void sde_encoder_enable_recovery_event(struct drm_encoder *encoder);
  475. /**
  476. * sde_encoder_in_clone_mode - checks if underlying phys encoder is in clone
  477. * mode or independent display mode. ref@ WB in Concurrent writeback mode.
  478. * @drm_enc: Pointer to drm encoder structure
  479. * @Return: true if successful in updating the encoder structure
  480. */
  481. bool sde_encoder_in_clone_mode(struct drm_encoder *enc);
  482. /**
  483. * sde_encoder_set_clone_mode - cwb in wb phys enc is enabled.
  484. * drm_enc: Pointer to drm encoder structure
  485. * drm_crtc_state: Pointer to drm_crtc_state
  486. */
  487. void sde_encoder_set_clone_mode(struct drm_encoder *drm_enc,
  488. struct drm_crtc_state *crtc_state);
  489. /*
  490. * sde_encoder_is_cwb_disabling - check if cwb encoder disable is pending
  491. * @drm_enc: Pointer to drm encoder structure
  492. * @drm_crtc: Pointer to drm crtc structure
  493. * @Return: true if cwb encoder disable is pending
  494. */
  495. bool sde_encoder_is_cwb_disabling(struct drm_encoder *drm_enc,
  496. struct drm_crtc *drm_crtc);
  497. /**
  498. * sde_encoder_is_primary_display - checks if underlying display is primary
  499. * display or not.
  500. * @drm_enc: Pointer to drm encoder structure
  501. * @Return: true if it is primary display. false otherwise
  502. */
  503. bool sde_encoder_is_primary_display(struct drm_encoder *enc);
  504. /**
  505. * sde_encoder_is_built_in_display - checks if underlying display is built in
  506. * display or not.
  507. * @drm_enc: Pointer to drm encoder structure
  508. * @Return: true if it is a built in display. false otherwise
  509. */
  510. bool sde_encoder_is_built_in_display(struct drm_encoder *enc);
  511. /**
  512. * sde_encoder_check_ctl_done_support - checks if ctl_done irq is available
  513. * for the display
  514. * @drm_enc: Pointer to drm encoder structure
  515. * @Return: true if scheduler update is enabled
  516. */
  517. static inline bool sde_encoder_check_ctl_done_support(struct drm_encoder *drm_enc)
  518. {
  519. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  520. return sde_enc && sde_enc->ctl_done_supported;
  521. }
  522. /**
  523. * sde_encoder_is_dsi_display - checks if underlying display is DSI
  524. * display or not.
  525. * @drm_enc: Pointer to drm encoder structure
  526. * @Return: true if it is a dsi display. false otherwise
  527. */
  528. bool sde_encoder_is_dsi_display(struct drm_encoder *enc);
  529. /**
  530. * sde_encoder_control_idle_pc - control enable/disable of idle power collapse
  531. * @drm_enc: Pointer to drm encoder structure
  532. * @enable: enable/disable flag
  533. */
  534. void sde_encoder_control_idle_pc(struct drm_encoder *enc, bool enable);
  535. /**
  536. * sde_encoder_in_cont_splash - checks if display is in continuous splash
  537. * @drm_enc: Pointer to drm encoder structure
  538. * @Return: true if display in continuous splash
  539. */
  540. int sde_encoder_in_cont_splash(struct drm_encoder *enc);
  541. /**
  542. * sde_encoder_helper_hw_reset - hw reset helper function
  543. * @drm_enc: Pointer to drm encoder structure
  544. */
  545. void sde_encoder_needs_hw_reset(struct drm_encoder *enc);
  546. /**
  547. * sde_encoder_uidle_enable - control enable/disable of uidle
  548. * @drm_enc: Pointer to drm encoder structure
  549. * @enable: enable/disable flag
  550. */
  551. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable);
  552. /**
  553. * sde_encoder_irq_control - control enable/disable of IRQ's
  554. * @drm_enc: Pointer to drm encoder structure
  555. * @enable: enable/disable flag
  556. */
  557. void sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable);
  558. /**sde_encoder_get_connector - get connector corresponding to encoder
  559. * @dev: Pointer to drm device structure
  560. * @drm_enc: Pointer to drm encoder structure
  561. * Returns: drm connector if found, null if not found
  562. */
  563. struct drm_connector *sde_encoder_get_connector(struct drm_device *dev,
  564. struct drm_encoder *drm_enc);
  565. /**sde_encoder_needs_dsc_disable - indicates if dsc should be disabled
  566. * based on previous topology
  567. * @drm_enc: Pointer to drm encoder structure
  568. */
  569. bool sde_encoder_needs_dsc_disable(struct drm_encoder *drm_enc);
  570. /**
  571. * sde_encoder_get_transfer_time - get the mdp transfer time in usecs
  572. * @drm_enc: Pointer to drm encoder structure
  573. * @transfer_time_us: Pointer to store the output value
  574. */
  575. void sde_encoder_get_transfer_time(struct drm_encoder *drm_enc,
  576. u32 *transfer_time_us);
  577. /**
  578. * sde_encoder_helper_update_out_fence_txq - updates hw-fence tx queue
  579. * @sde_enc: Pointer to sde encoder structure
  580. * @is_vid: Boolean to indicate if is video-mode
  581. */
  582. void sde_encoder_helper_update_out_fence_txq(struct sde_encoder_virt *sde_enc, bool is_vid);
  583. /*
  584. * sde_encoder_get_dfps_maxfps - get dynamic FPS max frame rate of
  585. the given encoder
  586. * @encoder: Pointer to drm encoder object
  587. */
  588. static inline u32 sde_encoder_get_dfps_maxfps(struct drm_encoder *drm_enc)
  589. {
  590. struct sde_encoder_virt *sde_enc;
  591. if (!drm_enc) {
  592. SDE_ERROR("invalid encoder\n");
  593. return 0;
  594. }
  595. sde_enc = to_sde_encoder_virt(drm_enc);
  596. return sde_enc->mode_info.dfps_maxfps;
  597. }
  598. /**
  599. * sde_encoder_virt_reset - delay encoder virt reset
  600. * @drm_enc: Pointer to drm encoder structure
  601. */
  602. void sde_encoder_virt_reset(struct drm_encoder *drm_enc);
  603. /**
  604. * sde_encoder_calc_last_vsync_timestamp - read last HW vsync timestamp counter
  605. * and calculate the corresponding vsync ktime. Return ktime_get
  606. * when HW support is not available
  607. * @drm_enc: Pointer to drm encoder structure
  608. */
  609. ktime_t sde_encoder_calc_last_vsync_timestamp(struct drm_encoder *drm_enc);
  610. /**
  611. * sde_encoder_cancel_delayed_work - cancel delayed off work for encoder
  612. * @drm_enc: Pointer to drm encoder structure
  613. */
  614. void sde_encoder_cancel_delayed_work(struct drm_encoder *encoder);
  615. /**
  616. * sde_encoder_get_kms - retrieve the kms from encoder
  617. * @drm_enc: Pointer to drm encoder structure
  618. */
  619. static inline struct sde_kms *sde_encoder_get_kms(struct drm_encoder *drm_enc)
  620. {
  621. struct msm_drm_private *priv;
  622. if (!drm_enc || !drm_enc->dev) {
  623. SDE_ERROR("invalid encoder\n");
  624. return NULL;
  625. }
  626. priv = drm_enc->dev->dev_private;
  627. if (!priv || !priv->kms) {
  628. SDE_ERROR("invalid kms\n");
  629. return NULL;
  630. }
  631. return to_sde_kms(priv->kms);
  632. }
  633. /*
  634. * sde_encoder_is_widebus_enabled - check if widebus is enabled for current mode
  635. * @drm_enc: Pointer to drm encoder structure
  636. * @Return: true if widebus is enabled for current mode
  637. */
  638. static inline bool sde_encoder_is_widebus_enabled(struct drm_encoder *drm_enc)
  639. {
  640. struct sde_encoder_virt *sde_enc;
  641. if (!drm_enc)
  642. return false;
  643. sde_enc = to_sde_encoder_virt(drm_enc);
  644. return sde_enc->mode_info.wide_bus_en;
  645. }
  646. /*
  647. * sde_encoder_is_line_insertion_supported - get line insertion
  648. * feature bit value from panel
  649. * @drm_enc: Pointer to drm encoder structure
  650. * @Return: line insertion support status
  651. */
  652. bool sde_encoder_is_line_insertion_supported(struct drm_encoder *drm_enc);
  653. /**
  654. * sde_encoder_get_hw_ctl - gets hw ctl from the connector
  655. * @c_conn: sde connector
  656. * @Return: pointer to the hw ctl from the encoder upon success, otherwise null
  657. */
  658. struct sde_hw_ctl *sde_encoder_get_hw_ctl(struct sde_connector *c_conn);
  659. /*
  660. * sde_encoder_get_programmed_fetch_time - gets the programmable fetch time for video encoders
  661. * @drm_enc: Pointer to drm encoder structure
  662. * @Return: programmable fetch time in microseconds
  663. */
  664. u32 sde_encoder_get_programmed_fetch_time(struct drm_encoder *encoder);
  665. void sde_encoder_add_data_to_minidump_va(struct drm_encoder *drm_enc);
  666. /**
  667. * sde_encoder_misr_sign_event_notify - collect MISR, check with previous value
  668. * if change then notify to client with custom event
  669. * @drm_enc: pointer to drm encoder
  670. */
  671. void sde_encoder_misr_sign_event_notify(struct drm_encoder *drm_enc);
  672. /**
  673. * sde_encoder_register_misr_event - register or deregister MISR event
  674. * @drm_enc: pointer to drm encoder
  675. * @val: indicates register or deregister
  676. */
  677. static inline int sde_encoder_register_misr_event(struct drm_encoder *drm_enc, bool val)
  678. {
  679. struct sde_encoder_virt *sde_enc = NULL;
  680. if (!drm_enc)
  681. return -EINVAL;
  682. sde_enc = to_sde_encoder_virt(drm_enc);
  683. atomic_set(&sde_enc->misr_enable, val);
  684. /*
  685. * To setup MISR ctl reg, set misr_reconfigure as true.
  686. * MISR is calculated for the specific number of frames.
  687. */
  688. if (atomic_read(&sde_enc->misr_enable)) {
  689. sde_enc->misr_reconfigure = true;
  690. sde_enc->misr_frame_count = 1;
  691. }
  692. return 0;
  693. }
  694. #endif /* __SDE_ENCODER_H__ */