Make sure global tx desc count is decremented during tx desc pool flush Change-Id: I5ba21cd9a4b1dbd3dbaf55e56a5852fe7703e36c CRs-Fixed: 3501063
625 рядки
18 KiB
C
625 рядки
18 KiB
C
/*
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* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "cdp_txrx_cmn_struct.h"
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#include "dp_types.h"
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#include "dp_tx.h"
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#include "dp_li_tx.h"
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#include "dp_tx_desc.h"
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#include <dp_internal.h>
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#include <dp_htt.h>
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#include <hal_li_api.h>
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#include <hal_li_tx.h>
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#include "dp_peer.h"
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#ifdef FEATURE_WDS
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#include "dp_txrx_wds.h"
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#endif
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#include "dp_li.h"
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extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
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void dp_tx_comp_get_params_from_hal_desc_li(struct dp_soc *soc,
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void *tx_comp_hal_desc,
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struct dp_tx_desc_s **r_tx_desc)
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{
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uint8_t pool_id;
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uint32_t tx_desc_id;
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tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
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pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
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DP_TX_DESC_ID_POOL_OS;
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/* Find Tx descriptor */
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*r_tx_desc = dp_tx_desc_find(soc, pool_id,
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(tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
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DP_TX_DESC_ID_PAGE_OS,
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(tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
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DP_TX_DESC_ID_OFFSET_OS);
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/* Pool id is not matching. Error */
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if ((*r_tx_desc)->pool_id != pool_id) {
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dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
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pool_id, (*r_tx_desc)->pool_id);
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qdf_assert_always(0);
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}
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(*r_tx_desc)->peer_id = hal_tx_comp_get_peer_id(tx_comp_hal_desc);
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}
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static inline
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void dp_tx_process_mec_notify_li(struct dp_soc *soc, uint8_t *status)
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{
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struct dp_vdev *vdev;
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uint8_t vdev_id;
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uint32_t *htt_desc = (uint32_t *)status;
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/*
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* Get vdev id from HTT status word in case of MEC
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* notification
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*/
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vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
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if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
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return;
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vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
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DP_MOD_ID_HTT_COMP);
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if (!vdev)
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return;
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dp_tx_mec_handler(vdev, status);
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dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
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}
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void dp_tx_process_htt_completion_li(struct dp_soc *soc,
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struct dp_tx_desc_s *tx_desc,
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uint8_t *status,
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uint8_t ring_id)
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{
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uint8_t tx_status;
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struct dp_pdev *pdev;
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struct dp_vdev *vdev = NULL;
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struct hal_tx_completion_status ts = {0};
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uint32_t *htt_desc = (uint32_t *)status;
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struct dp_txrx_peer *txrx_peer;
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dp_txrx_ref_handle txrx_ref_handle = NULL;
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struct cdp_tid_tx_stats *tid_stats = NULL;
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struct htt_soc *htt_handle;
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uint8_t vdev_id;
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tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
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htt_handle = (struct htt_soc *)soc->htt_handle;
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htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
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/*
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* There can be scenario where WBM consuming descriptor enqueued
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* from TQM2WBM first and TQM completion can happen before MEC
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* notification comes from FW2WBM. Avoid access any field of tx
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* descriptor in case of MEC notify.
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*/
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if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
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return dp_tx_process_mec_notify_li(soc, status);
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/*
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* If the descriptor is already freed in vdev_detach,
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* continue to next descriptor
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*/
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if (qdf_unlikely(!tx_desc->flags)) {
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dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
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tx_desc->id);
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return;
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}
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if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
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dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
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tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
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goto release_tx_desc;
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}
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pdev = tx_desc->pdev;
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if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
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dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
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tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
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goto release_tx_desc;
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}
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qdf_assert(tx_desc->pdev);
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vdev_id = tx_desc->vdev_id;
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vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
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DP_MOD_ID_HTT_COMP);
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if (qdf_unlikely(!vdev)) {
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dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
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tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
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goto release_tx_desc;
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}
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switch (tx_status) {
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case HTT_TX_FW2WBM_TX_STATUS_OK:
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case HTT_TX_FW2WBM_TX_STATUS_DROP:
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case HTT_TX_FW2WBM_TX_STATUS_TTL:
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{
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uint8_t tid;
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if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
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ts.peer_id =
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HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
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htt_desc[2]);
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ts.tid =
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HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
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htt_desc[2]);
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} else {
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ts.peer_id = HTT_INVALID_PEER;
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ts.tid = HTT_INVALID_TID;
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}
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ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
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ts.ppdu_id =
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HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
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htt_desc[1]);
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ts.ack_frame_rssi =
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HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
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htt_desc[1]);
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ts.tsf = htt_desc[3];
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ts.first_msdu = 1;
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ts.last_msdu = 1;
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switch (tx_status) {
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case HTT_TX_FW2WBM_TX_STATUS_OK:
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ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
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break;
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case HTT_TX_FW2WBM_TX_STATUS_DROP:
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ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
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break;
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case HTT_TX_FW2WBM_TX_STATUS_TTL:
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ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
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break;
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}
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tid = ts.tid;
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if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
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tid = CDP_MAX_DATA_TIDS - 1;
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tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
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if (qdf_unlikely(pdev->delay_stats_flag) ||
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qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
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dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
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if (tx_status < CDP_MAX_TX_HTT_STATUS)
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tid_stats->htt_status_cnt[tx_status]++;
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txrx_peer = dp_txrx_peer_get_ref_by_id(soc, ts.peer_id,
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&txrx_ref_handle,
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DP_MOD_ID_HTT_COMP);
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if (qdf_likely(txrx_peer)) {
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DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1,
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qdf_nbuf_len(tx_desc->nbuf));
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if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
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DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
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}
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dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
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ring_id);
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dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
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dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
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if (qdf_likely(txrx_peer))
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dp_txrx_peer_unref_delete(txrx_ref_handle,
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DP_MOD_ID_HTT_COMP);
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break;
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}
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case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
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{
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uint8_t reinject_reason;
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reinject_reason =
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HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(
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htt_desc[0]);
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dp_tx_reinject_handler(soc, vdev, tx_desc,
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status, reinject_reason);
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break;
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}
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case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
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{
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dp_tx_inspect_handler(soc, vdev, tx_desc, status);
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break;
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}
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case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
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{
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DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
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goto release_tx_desc;
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}
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default:
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dp_tx_comp_err("Invalid HTT tx_status %d\n",
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tx_status);
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goto release_tx_desc;
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}
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dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
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return;
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release_tx_desc:
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dp_tx_comp_free_buf(soc, tx_desc, false);
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dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
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if (vdev)
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dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
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}
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#ifdef QCA_OL_TX_MULTIQ_SUPPORT
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/**
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* dp_tx_get_rbm_id_li() - Get the RBM ID for data transmission completion.
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* @soc: DP soc structure pointer
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* @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
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*
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* Return: HAL ring handle
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*/
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#ifdef IPA_OFFLOAD
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static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
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uint8_t ring_id)
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{
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return (ring_id + soc->wbm_sw0_bm_id);
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}
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#else
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#ifndef QCA_DP_ENABLE_TX_COMP_RING4
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static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
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uint8_t ring_id)
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{
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return (ring_id ? HAL_WBM_SW0_BM_ID + (ring_id - 1) :
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HAL_WBM_SW2_BM_ID);
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}
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#else
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static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
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uint8_t ring_id)
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{
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if (ring_id == soc->num_tcl_data_rings)
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return HAL_WBM_SW4_BM_ID(soc->wbm_sw0_bm_id);
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return (ring_id + HAL_WBM_SW0_BM_ID(soc->wbm_sw0_bm_id));
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}
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#endif
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#endif
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#else
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#ifdef TX_MULTI_TCL
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#ifdef IPA_OFFLOAD
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static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
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uint8_t ring_id)
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{
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if (soc->wlan_cfg_ctx->ipa_enabled)
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return (ring_id + soc->wbm_sw0_bm_id);
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return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
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}
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#else
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static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
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uint8_t ring_id)
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{
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return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
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}
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#endif
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#else
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static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
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uint8_t ring_id)
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{
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return (ring_id + soc->wbm_sw0_bm_id);
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}
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#endif
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#endif
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#if defined(CLEAR_SW2TCL_CONSUMED_DESC)
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/**
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* dp_tx_clear_consumed_hw_descs - Reset all the consumed Tx ring descs to 0
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*
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* @soc: DP soc handle
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* @hal_ring_hdl: Source ring pointer
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*
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* Return: void
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*/
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static inline
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void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
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hal_ring_handle_t hal_ring_hdl)
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{
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void *desc = hal_srng_src_get_next_consumed(soc->hal_soc, hal_ring_hdl);
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while (desc) {
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hal_tx_desc_clear(desc);
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desc = hal_srng_src_get_next_consumed(soc->hal_soc,
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hal_ring_hdl);
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}
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}
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#else
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static inline
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void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
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hal_ring_handle_t hal_ring_hdl)
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{
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}
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#endif /* CLEAR_SW2TCL_CONSUMED_DESC */
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#ifdef WLAN_CONFIG_TX_DELAY
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static inline
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QDF_STATUS dp_tx_compute_hw_delay_li(struct dp_soc *soc,
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struct dp_vdev *vdev,
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struct hal_tx_completion_status *ts,
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uint32_t *delay_us)
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{
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return dp_tx_compute_hw_delay_us(ts, vdev->delta_tsf, delay_us);
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}
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#else
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static inline
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QDF_STATUS dp_tx_compute_hw_delay_li(struct dp_soc *soc,
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struct dp_vdev *vdev,
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struct hal_tx_completion_status *ts,
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uint32_t *delay_us)
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{
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return QDF_STATUS_SUCCESS;
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}
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#endif
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#ifdef CONFIG_SAWF
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/**
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* dp_sawf_config_li - Configure sawf specific fields in tcl
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*
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* @soc: DP soc handle
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* @hal_tx_desc_cached: tx descriptor
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* @fw_metadata: firmware metadata
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* @vdev_id: vdev id
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* @nbuf: skb buffer
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* @msdu_info: msdu info
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*
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* Return: void
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*/
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static inline
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void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
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uint16_t *fw_metadata, uint16_t vdev_id,
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qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
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{
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uint8_t q_id = 0;
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uint32_t flow_idx = 0;
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if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
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return;
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q_id = dp_sawf_queue_id_get(nbuf);
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if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
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return;
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msdu_info->tid = (q_id & (CDP_DATA_TID_MAX - 1));
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hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
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(q_id & (CDP_DATA_TID_MAX - 1)));
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if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
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(q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
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return;
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dp_sawf_tcl_cmd(fw_metadata, nbuf);
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/* For SAWF, q_id starts from DP_SAWF_Q_MAX */
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if (!dp_sawf_get_search_index(soc, nbuf, vdev_id,
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q_id, &flow_idx))
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hal_tx_desc_set_to_fw(hal_tx_desc_cached, true);
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hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
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HAL_TX_ADDR_INDEX_SEARCH);
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hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
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flow_idx);
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}
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#else
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static inline
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void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
|
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uint16_t *fw_metadata, uint16_t vdev_id,
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qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
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{
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}
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|
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#define dp_sawf_tx_enqueue_peer_stats(soc, tx_desc)
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#define dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc)
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#endif
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|
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QDF_STATUS
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dp_tx_hw_enqueue_li(struct dp_soc *soc, struct dp_vdev *vdev,
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struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
|
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struct cdp_tx_exception_metadata *tx_exc_metadata,
|
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struct dp_tx_msdu_info_s *msdu_info)
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{
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void *hal_tx_desc;
|
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uint32_t *hal_tx_desc_cached;
|
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int coalesce = 0;
|
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struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
|
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uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
|
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uint8_t tid;
|
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|
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/*
|
|
* Setting it initialization statically here to avoid
|
|
* a memset call jump with qdf_mem_set call
|
|
*/
|
|
uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
|
|
|
|
enum cdp_sec_type sec_type = ((tx_exc_metadata &&
|
|
tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
|
|
tx_exc_metadata->sec_type : vdev->sec_type);
|
|
|
|
/* Return Buffer Manager ID */
|
|
uint8_t bm_id = dp_tx_get_rbm_id_li(soc, ring_id);
|
|
|
|
hal_ring_handle_t hal_ring_hdl = NULL;
|
|
|
|
QDF_STATUS status = QDF_STATUS_E_RESOURCES;
|
|
|
|
if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
|
|
dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
|
|
return QDF_STATUS_E_RESOURCES;
|
|
}
|
|
|
|
hal_tx_desc_cached = (void *)cached_desc;
|
|
|
|
hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
|
|
tx_desc->dma_addr, bm_id, tx_desc->id,
|
|
(tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
|
|
hal_tx_desc_set_lmac_id_li(soc->hal_soc, hal_tx_desc_cached,
|
|
vdev->lmac_id);
|
|
hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
|
|
vdev->search_type);
|
|
hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
|
|
vdev->bss_ast_idx);
|
|
hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
|
|
vdev->dscp_tid_map_id);
|
|
|
|
hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
|
|
sec_type_map[sec_type]);
|
|
hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
|
|
(vdev->bss_ast_hash & 0xF));
|
|
|
|
if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
|
|
dp_sawf_config_li(soc, hal_tx_desc_cached, &fw_metadata,
|
|
vdev->vdev_id, tx_desc->nbuf, msdu_info);
|
|
dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
|
|
}
|
|
|
|
hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
|
|
hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
|
|
hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
|
|
hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
|
|
hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
|
|
vdev->hal_desc_addr_search_flags);
|
|
|
|
if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
|
|
hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
|
|
|
|
/* verify checksum offload configuration*/
|
|
if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
|
|
QDF_NBUF_TX_CKSUM_TCP_UDP) ||
|
|
qdf_nbuf_is_tso(tx_desc->nbuf)) {
|
|
hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
|
|
hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
|
|
}
|
|
|
|
tid = msdu_info->tid;
|
|
if (tid != HTT_TX_EXT_TID_INVALID)
|
|
hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
|
|
|
|
if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
|
|
hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
|
|
|
|
if (!dp_tx_desc_set_ktimestamp(vdev, tx_desc))
|
|
dp_tx_desc_set_timestamp(tx_desc);
|
|
|
|
dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
|
|
tx_desc->length,
|
|
(tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
|
|
(uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
|
|
tx_desc->id);
|
|
|
|
hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
|
|
|
|
if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
|
|
QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
|
|
"%s %d : HAL RING Access Failed -- %pK",
|
|
__func__, __LINE__, hal_ring_hdl);
|
|
DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
|
|
DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
|
|
dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
|
|
return status;
|
|
}
|
|
|
|
dp_tx_clear_consumed_hw_descs(soc, hal_ring_hdl);
|
|
|
|
/* Sync cached descriptor with HW */
|
|
|
|
hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
|
|
if (qdf_unlikely(!hal_tx_desc)) {
|
|
dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
|
|
DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
|
|
DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
|
|
dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
|
|
goto ring_access_fail;
|
|
}
|
|
|
|
tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
|
|
dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
|
|
hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
|
|
coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
|
|
msdu_info, ring_id);
|
|
DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
|
|
DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
|
|
dp_tx_update_stats(soc, tx_desc, ring_id);
|
|
status = QDF_STATUS_SUCCESS;
|
|
|
|
dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
|
|
hal_ring_hdl, soc, ring_id);
|
|
|
|
ring_access_fail:
|
|
dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
|
|
dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
|
|
qdf_get_log_timestamp(), tx_desc->nbuf);
|
|
|
|
return status;
|
|
}
|
|
|
|
QDF_STATUS dp_tx_desc_pool_init_li(struct dp_soc *soc,
|
|
uint32_t num_elem,
|
|
uint8_t pool_id)
|
|
{
|
|
uint32_t id, count, page_id, offset, pool_id_32;
|
|
struct dp_tx_desc_s *tx_desc;
|
|
struct dp_tx_desc_pool_s *tx_desc_pool;
|
|
uint16_t num_desc_per_page;
|
|
|
|
tx_desc_pool = &soc->tx_desc[pool_id];
|
|
tx_desc = tx_desc_pool->freelist;
|
|
count = 0;
|
|
pool_id_32 = (uint32_t)pool_id;
|
|
num_desc_per_page = tx_desc_pool->desc_pages.num_element_per_page;
|
|
while (tx_desc) {
|
|
page_id = count / num_desc_per_page;
|
|
offset = count % num_desc_per_page;
|
|
id = ((pool_id_32 << DP_TX_DESC_ID_POOL_OS) |
|
|
(page_id << DP_TX_DESC_ID_PAGE_OS) | offset);
|
|
|
|
tx_desc->id = id;
|
|
tx_desc->pool_id = pool_id;
|
|
tx_desc->vdev_id = DP_INVALID_VDEV_ID;
|
|
dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
|
|
tx_desc = tx_desc->next;
|
|
count++;
|
|
}
|
|
|
|
return QDF_STATUS_SUCCESS;
|
|
}
|
|
|
|
void dp_tx_desc_pool_deinit_li(struct dp_soc *soc,
|
|
struct dp_tx_desc_pool_s *tx_desc_pool,
|
|
uint8_t pool_id)
|
|
{
|
|
}
|
|
|
|
QDF_STATUS dp_tx_compute_tx_delay_li(struct dp_soc *soc,
|
|
struct dp_vdev *vdev,
|
|
struct hal_tx_completion_status *ts,
|
|
uint32_t *delay_us)
|
|
{
|
|
return dp_tx_compute_hw_delay_li(soc, vdev, ts, delay_us);
|
|
}
|
|
|
|
QDF_STATUS dp_tx_desc_pool_alloc_li(struct dp_soc *soc, uint32_t num_elem,
|
|
uint8_t pool_id)
|
|
{
|
|
return QDF_STATUS_SUCCESS;
|
|
}
|
|
|
|
void dp_tx_desc_pool_free_li(struct dp_soc *soc, uint8_t pool_id)
|
|
{
|
|
}
|