wcd9378.c 133 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include <asoc/msm-cdc-supply.h>
  20. #include <bindings/audio-codec-port-types.h>
  21. #include <linux/qti-regmap-debugfs.h>
  22. #include "wcd9378-reg-masks.h"
  23. #include "wcd9378.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD9378_MOBILE_MODE 0x01
  28. #define WCD9378_VERSION_1_0 1
  29. #define WCD9378_VERSION_ENTRY_SIZE 32
  30. #define SWR_BASECLK_19P2MHZ (0x01)
  31. #define SWR_BASECLK_24P576MHZ (0x03)
  32. #define SWR_BASECLK_22P5792MHZ (0x04)
  33. #define SWR_CLKSCALE_DIV2 (0x02)
  34. #define SWR_CLKSCALE_DIV4 (0x03)
  35. #define ADC_MODE_VAL_HIFI 0x01
  36. #define ADC_MODE_VAL_NORMAL 0x03
  37. #define ADC_MODE_VAL_LP 0x05
  38. #define PWR_LEVEL_LOHIFI_VAL 0x00
  39. #define PWR_LEVEL_LP_VAL 0x01
  40. #define PWR_LEVEL_HIFI_VAL 0x02
  41. #define PWR_LEVEL_ULP_VAL 0x03
  42. #define MICB_USAGE_VAL_DISABLE 0x00
  43. #define MICB_USAGE_VAL_PULL_DOWN 0x01
  44. #define MICB_USAGE_VAL_1P2V 0x02
  45. #define MICB_USAGE_VAL_1P8VORPULLUP 0x03
  46. #define MICB_USAGE_VAL_2P5V 0x04
  47. #define MICB_USAGE_VAL_2P75V 0x05
  48. #define MICB_USAGE_VAL_2P2V 0xF0
  49. #define MICB_USAGE_VAL_2P7V 0xF1
  50. #define MICB_USAGE_VAL_2P8V 0xF2
  51. #define MICB_USAGE_VAL_MICB1_TABLE_VAL 0xF3
  52. #define MICB_USAGE_VAL_MICB2_TABLE_VAL 0xF4
  53. #define MICB_USAGE_VAL_MICB3_TABLE_VAL 0xF5
  54. #define WCD_TX_SYS_USAGE_BIT_MASK (0xFC)
  55. #define WCD_RX_SYS_USAGE_BIT_MASK (0x1F00)
  56. #define MICB_NUM_MAX 3
  57. #define NUM_ATTEMPTS 20
  58. #define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  59. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  60. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  61. SNDRV_PCM_RATE_384000)
  62. /* Fractional Rates */
  63. #define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  64. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  65. #define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  66. SNDRV_PCM_FMTBIT_S24_LE |\
  67. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  68. #define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  69. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  70. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  71. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  72. .tlv.p = (tlv_array), \
  73. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  74. .put = wcd9378_ear_pa_put_gain, \
  75. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  76. #define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  77. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  78. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  79. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  80. .tlv.p = (tlv_array), \
  81. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  82. .put = wcd9378_aux_pa_put_gain, \
  83. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  84. enum {
  85. CODEC_TX = 0,
  86. CODEC_RX,
  87. };
  88. enum {
  89. RX2_HP_MODE,
  90. RX2_NORMAL_MODE,
  91. };
  92. enum {
  93. CLASS_AB_EN = 0,
  94. TX1_FOR_JACK,
  95. TX2_AMIC4_EN,
  96. TX2_AMIC1_EN,
  97. TX1_AMIC3_EN,
  98. TX1_AMIC2_EN,
  99. TX0_AMIC2_EN,
  100. TX0_AMIC1_EN,
  101. RX2_EAR_EN,
  102. RX2_AUX_EN,
  103. RX1_AUX_EN,
  104. RX0_EAR_EN,
  105. RX0_RX1_HPH_EN,
  106. };
  107. enum {
  108. WCD_ADC1 = 0,
  109. WCD_ADC2,
  110. WCD_ADC3,
  111. WCD_ADC4,
  112. ALLOW_BUCK_DISABLE,
  113. HPH_COMP_DELAY,
  114. HPH_PA_DELAY,
  115. AMIC2_BCS_ENABLE,
  116. WCD_SUPPLIES_LPM_MODE,
  117. WCD_ADC1_MODE,
  118. WCD_ADC2_MODE,
  119. WCD_ADC3_MODE,
  120. WCD_ADC4_MODE,
  121. WCD_AUX_EN,
  122. WCD_EAR_EN,
  123. };
  124. enum {
  125. SYS_USAGE_0,
  126. SYS_USAGE_1,
  127. SYS_USAGE_2,
  128. SYS_USAGE_3,
  129. SYS_USAGE_4,
  130. SYS_USAGE_5,
  131. SYS_USAGE_6,
  132. SYS_USAGE_7,
  133. SYS_USAGE_8,
  134. SYS_USAGE_9,
  135. SYS_USAGE_10,
  136. SYS_USAGE_11,
  137. SYS_USAGE_12,
  138. SYS_USAGE_NUM,
  139. };
  140. enum {
  141. NO_MICB_USED,
  142. MICB1,
  143. MICB2,
  144. MICB3,
  145. MICB_NUM,
  146. };
  147. enum {
  148. ADC_MODE_INVALID = 0,
  149. ADC_MODE_HIFI,
  150. ADC_MODE_NORMAL,
  151. ADC_MODE_LP,
  152. };
  153. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
  154. static int wcd9378_reset(struct device *dev);
  155. static int wcd9378_reset_low(struct device *dev);
  156. static void wcd9378_class_load(struct snd_soc_component *component);
  157. /* sys_usage:
  158. * rx0_rx1_hph_en,
  159. * rx0_ear_en, rx1_aux_en, rx2_aux_en, rx2_ear_en,
  160. * tx0_amic1_en, tx0_amic2_en, tx1_amic2_en, tx1_amic3_en,
  161. * tx2_amic1_en, tx2_amic4_en, tx1_for_jack, class_ab_en;
  162. */
  163. static const int sys_usage[SYS_USAGE_NUM] = {
  164. [SYS_USAGE_0] = 0x0c95, /*0b0 1100 1001 0101*/
  165. [SYS_USAGE_1] = 0x12a7, /*0b1 0010 1010 0111*/
  166. [SYS_USAGE_2] = 0x0c99, /*0b0 1100 1001 1001*/
  167. [SYS_USAGE_3] = 0x1aab, /*0b1 1010 1010 1011*/
  168. [SYS_USAGE_4] = 0x0894, /*0b0 1000 1001 0100*/
  169. [SYS_USAGE_5] = 0x11a6, /*0b1 0001 1010 0110*/
  170. [SYS_USAGE_6] = 0x0898, /*0b0 1000 1001 1000*/
  171. [SYS_USAGE_7] = 0x11ab, /*0b1 0001 1010 1011*/
  172. [SYS_USAGE_8] = 0x126a, /*0b1 0010 0110 1010*/
  173. [SYS_USAGE_9] = 0x116b, /*0b1 0001 0110 1011*/
  174. [SYS_USAGE_10] = 0x1ca7, /*0b1 1100 1010 0111*/
  175. [SYS_USAGE_11] = 0x1195, /*0b1 0001 1001 0101*/
  176. [SYS_USAGE_12] = 0x1296, /*0b1 0010 1001 0101*/
  177. };
  178. static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
  179. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  180. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  181. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  182. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  183. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
  184. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
  185. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
  186. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
  187. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
  188. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
  189. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
  190. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
  191. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
  192. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  193. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  194. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  195. REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
  196. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  197. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  198. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  199. REGMAP_IRQ_REG(WCD9378_IRQ_SAPU_PROT_MODE_CHG, 2, 0x40),
  200. };
  201. static int wcd9378_handle_post_irq(void *data)
  202. {
  203. struct wcd9378_priv *wcd9378 = data;
  204. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  205. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, 0xff);
  206. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, 0xff);
  207. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, 0xff);
  208. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
  209. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
  210. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
  211. wcd9378->tx_swr_dev->slave_irq_pending =
  212. ((sts1 || sts2 || sts3) ? true : false);
  213. return IRQ_HANDLED;
  214. }
  215. static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
  216. .name = "wcd9378",
  217. .irqs = wcd9378_regmap_irqs,
  218. .num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
  219. .num_regs = 3,
  220. .status_base = SWRS_SCP_SDCA_INTSTAT_1,
  221. .unmask_base = SWRS_SCP_SDCA_INTMASK_1,
  222. .type_base = SWRS_SCP_SDCA_INTRTYPE_1,
  223. .ack_base = SWRS_SCP_SDCA_INTSTAT_1,
  224. .use_ack = 1,
  225. .runtime_pm = false,
  226. .handle_post_irq = wcd9378_handle_post_irq,
  227. .irq_drv_data = NULL,
  228. };
  229. static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  230. {
  231. int ret = 0;
  232. int bank = 0;
  233. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  234. if (ret)
  235. return -EINVAL;
  236. return ((bank & 0x40) ? 1 : 0);
  237. }
  238. static int wcd9378_swr_reset_check(struct wcd9378_priv *wcd9378, int path)
  239. {
  240. if (((path == TX_PATH) &&
  241. (wcd9378->sys_usage_status & WCD_TX_SYS_USAGE_BIT_MASK)) ||
  242. ((path == RX_PATH) &&
  243. (wcd9378->sys_usage_status & WCD_RX_SYS_USAGE_BIT_MASK)))
  244. return false;
  245. return true;
  246. }
  247. static int wcd9378_swr_slvdev_datapath_control(struct device *dev,
  248. int path, bool enable)
  249. {
  250. struct wcd9378_priv *wcd9378 = NULL;
  251. struct swr_device *swr_dev = NULL;
  252. int bank = 0, ret = 0;
  253. u8 clk_rst = 0x00, scale_rst = 0x00;
  254. u8 swr_clk = 0, clk_scale = 0;
  255. u16 scale_reg = 0, scale_reg2 = 0;
  256. wcd9378 = dev_get_drvdata(dev);
  257. if (!wcd9378)
  258. return -EINVAL;
  259. if (path == RX_PATH) {
  260. swr_dev = wcd9378->rx_swr_dev;
  261. swr_clk = wcd9378->rx_swrclk;
  262. clk_scale = wcd9378->rx_clkscale;
  263. } else {
  264. swr_dev = wcd9378->tx_swr_dev;
  265. swr_clk = wcd9378->tx_swrclk;
  266. clk_scale = wcd9378->tx_clkscale;
  267. }
  268. bank = (wcd9378_swr_slv_get_current_bank(swr_dev,
  269. swr_dev->dev_num) ? 0 : 1);
  270. scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  271. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  272. scale_reg2 = (!bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  273. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  274. if (enable) {
  275. swr_write(swr_dev, swr_dev->dev_num,
  276. SWRS_SCP_BASE_CLK_BASE, &swr_clk);
  277. swr_write(swr_dev, swr_dev->dev_num,
  278. scale_reg, &clk_scale);
  279. swr_write(swr_dev, swr_dev->dev_num,
  280. scale_reg2, &clk_scale);
  281. ret = swr_slvdev_datapath_control(swr_dev,
  282. swr_dev->dev_num, true);
  283. } else {
  284. if (wcd9378_swr_reset_check(wcd9378, path)) {
  285. swr_write(swr_dev, swr_dev->dev_num,
  286. SWRS_SCP_BASE_CLK_BASE, &clk_rst);
  287. swr_write(swr_dev, swr_dev->dev_num,
  288. scale_reg, &scale_rst);
  289. swr_write(swr_dev, swr_dev->dev_num,
  290. scale_reg2, &scale_rst);
  291. }
  292. ret = swr_slvdev_datapath_control(swr_dev,
  293. swr_dev->dev_num, false);
  294. }
  295. return ret;
  296. }
  297. static int wcd9378_init_reg(struct snd_soc_component *component)
  298. {
  299. struct wcd9378_priv *wcd9378 =
  300. snd_soc_component_get_drvdata(component);
  301. u32 val = 0;
  302. val = snd_soc_component_read(component, WCD9378_EFUSE_REG_16);
  303. if (!val)
  304. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  305. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  306. 0x03);
  307. else
  308. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  309. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  310. 0x01);
  311. /*0.9 Volts*/
  312. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  313. WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
  314. /*BG_EN ENABLE*/
  315. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  316. WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
  317. usleep_range(1000, 1010);
  318. /*LDOL_BG_SEL SLEEP_BG*/
  319. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  320. WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
  321. usleep_range(1000, 1010);
  322. /*Start up analog master bias. Sequence cannot change*/
  323. /*VBG_FINE_ADJ 0.005 Volts*/
  324. snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
  325. WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
  326. /*ANALOG_BIAS_EN ENABLE*/
  327. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  328. WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
  329. /*PRECHRG_EN ENABLE*/
  330. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  331. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
  332. usleep_range(10000, 10010);
  333. /*PRECHRG_EN DISABLE*/
  334. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  335. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
  336. /*End Analog Master Bias enable*/
  337. /*ANA_TXSCBIAS_CLK_EN ENABLE*/
  338. snd_soc_component_update_bits(component, WCD9378_CDC_ANA_TX_CLK_CTL,
  339. WCD9378_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN_MASK, 0x01);
  340. /*SEQ_BYPASS ENABLE*/
  341. snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
  342. WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
  343. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  344. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
  345. WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
  346. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  347. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
  348. WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
  349. /*IBIAS_LDO_DRIVER 5e-06*/
  350. snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
  351. WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  352. /*IBIAS_LDO_DRIVER 5e-06*/
  353. snd_soc_component_update_bits(component, WCD9378_MICB2_TEST_CTL_2,
  354. WCD9378_MICB2_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  355. /*IBIAS_LDO_DRIVER 5e-06*/
  356. snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
  357. WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  358. /*HD2_RES_DIV_CTL_L 82.77*/
  359. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
  360. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
  361. /*HD2_RES_DIV_CTL_R 82.77*/
  362. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
  363. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
  364. /*RDAC_GAINCTL 0.55*/
  365. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
  366. WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
  367. /*HPH_UP_T0: 0.002*/
  368. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
  369. WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
  370. /*HPH_UP_T9: 0.002*/
  371. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
  372. WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
  373. /*HPH_DN_T0: 0.007*/
  374. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
  375. WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
  376. /*SM0 MB SEL:MB1*/
  377. snd_soc_component_update_bits(component, WCD9378_SM0_MB_SEL,
  378. WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK, 0x01);
  379. /*SM1 MB SEL:MB2*/
  380. snd_soc_component_update_bits(component, WCD9378_SM1_MB_SEL,
  381. WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK, 0x02);
  382. /*SM2 MB SEL:MB3*/
  383. snd_soc_component_update_bits(component, WCD9378_SM2_MB_SEL,
  384. WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK, 0x03);
  385. /*INIT SYS_USAGE*/
  386. snd_soc_component_update_bits(component,
  387. WCD9378_SYS_USAGE_CTRL,
  388. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  389. 0);
  390. wcd9378->sys_usage = 0;
  391. wcd9378_class_load(component);
  392. return 0;
  393. }
  394. static int wcd9378_set_port_params(struct snd_soc_component *component,
  395. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  396. u8 *ch_mask, u32 *ch_rate,
  397. u8 *port_type, u8 path)
  398. {
  399. int i, j;
  400. u8 num_ports = 0;
  401. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  402. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  403. switch (path) {
  404. case CODEC_RX:
  405. map = &wcd9378->rx_port_mapping;
  406. num_ports = wcd9378->num_rx_ports;
  407. break;
  408. case CODEC_TX:
  409. map = &wcd9378->tx_port_mapping;
  410. num_ports = wcd9378->num_tx_ports;
  411. break;
  412. default:
  413. dev_err(component->dev, "%s Invalid path selected %u\n",
  414. __func__, path);
  415. return -EINVAL;
  416. }
  417. for (i = 0; i <= num_ports; i++) {
  418. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  419. if ((*map)[i][j].slave_port_type == slv_prt_type)
  420. goto found;
  421. }
  422. }
  423. found:
  424. if (i > num_ports || j == MAX_CH_PER_PORT) {
  425. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  426. __func__, slv_prt_type);
  427. return -EINVAL;
  428. }
  429. *port_id = i;
  430. *num_ch = (*map)[i][j].num_ch;
  431. *ch_mask = (*map)[i][j].ch_mask;
  432. *ch_rate = (*map)[i][j].ch_rate;
  433. *port_type = (*map)[i][j].master_port_type;
  434. return 0;
  435. }
  436. static int wcd9378_parse_port_params(struct device *dev,
  437. char *prop, u8 path)
  438. {
  439. u32 *dt_array, map_size, max_uc;
  440. int ret = 0;
  441. u32 cnt = 0;
  442. u32 i, j;
  443. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  444. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  445. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  446. switch (path) {
  447. case CODEC_TX:
  448. map = &wcd9378->tx_port_params;
  449. map_uc = &wcd9378->swr_tx_port_params;
  450. break;
  451. default:
  452. ret = -EINVAL;
  453. goto err_port_map;
  454. }
  455. if (!of_find_property(dev->of_node, prop,
  456. &map_size)) {
  457. dev_err(dev, "missing port mapping prop %s\n", prop);
  458. ret = -EINVAL;
  459. goto err_port_map;
  460. }
  461. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  462. if (max_uc != SWR_UC_MAX) {
  463. dev_err(dev, "%s: port params not provided for all usecases\n",
  464. __func__);
  465. ret = -EINVAL;
  466. goto err_port_map;
  467. }
  468. dt_array = kzalloc(map_size, GFP_KERNEL);
  469. if (!dt_array) {
  470. ret = -ENOMEM;
  471. goto err_alloc;
  472. }
  473. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  474. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  475. if (ret) {
  476. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  477. __func__, prop);
  478. goto err_pdata_fail;
  479. }
  480. for (i = 0; i < max_uc; i++) {
  481. for (j = 0; j < SWR_NUM_PORTS; j++) {
  482. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  483. (*map)[i][j].offset1 = dt_array[cnt];
  484. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  485. }
  486. (*map_uc)[i].pp = &(*map)[i][0];
  487. }
  488. kfree(dt_array);
  489. return 0;
  490. err_pdata_fail:
  491. kfree(dt_array);
  492. err_alloc:
  493. err_port_map:
  494. return ret;
  495. }
  496. static int wcd9378_parse_port_mapping(struct device *dev,
  497. char *prop, u8 path)
  498. {
  499. u32 *dt_array, map_size, map_length;
  500. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  501. u32 slave_port_type, master_port_type;
  502. u32 i, ch_iter = 0;
  503. int ret = 0;
  504. u8 *num_ports = NULL;
  505. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  506. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  507. switch (path) {
  508. case CODEC_RX:
  509. map = &wcd9378->rx_port_mapping;
  510. num_ports = &wcd9378->num_rx_ports;
  511. break;
  512. case CODEC_TX:
  513. map = &wcd9378->tx_port_mapping;
  514. num_ports = &wcd9378->num_tx_ports;
  515. break;
  516. default:
  517. dev_err(dev, "%s Invalid path selected %u\n",
  518. __func__, path);
  519. return -EINVAL;
  520. }
  521. if (!of_find_property(dev->of_node, prop,
  522. &map_size)) {
  523. dev_err(dev, "missing port mapping prop %s\n", prop);
  524. ret = -EINVAL;
  525. goto err_port_map;
  526. }
  527. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  528. dt_array = kzalloc(map_size, GFP_KERNEL);
  529. if (!dt_array) {
  530. ret = -ENOMEM;
  531. goto err_alloc;
  532. }
  533. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  534. NUM_SWRS_DT_PARAMS * map_length);
  535. if (ret) {
  536. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  537. __func__, prop);
  538. goto err_pdata_fail;
  539. }
  540. for (i = 0; i < map_length; i++) {
  541. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  542. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  543. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  544. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  545. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  546. if (port_num != old_port_num)
  547. ch_iter = 0;
  548. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  549. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  550. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  551. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  552. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  553. old_port_num = port_num;
  554. }
  555. *num_ports = port_num;
  556. kfree(dt_array);
  557. return 0;
  558. err_pdata_fail:
  559. kfree(dt_array);
  560. err_alloc:
  561. err_port_map:
  562. return ret;
  563. }
  564. static int wcd9378_tx_connect_port(struct snd_soc_component *component,
  565. u8 slv_port_type, int clk_rate,
  566. u8 enable)
  567. {
  568. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  569. u8 port_id, num_ch, ch_mask;
  570. u8 ch_type = 0;
  571. u32 ch_rate;
  572. int slave_ch_idx;
  573. u8 num_port = 1;
  574. int ret = 0;
  575. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  576. &num_ch, &ch_mask, &ch_rate,
  577. &ch_type, CODEC_TX);
  578. if (ret)
  579. return ret;
  580. if (clk_rate)
  581. ch_rate = clk_rate;
  582. slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
  583. if (slave_ch_idx != -EINVAL)
  584. ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
  585. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  586. __func__, slave_ch_idx, ch_type);
  587. if (enable)
  588. ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
  589. num_port, &ch_mask, &ch_rate,
  590. &num_ch, &ch_type);
  591. else
  592. ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
  593. num_port, &ch_mask, &ch_type);
  594. return ret;
  595. }
  596. static int wcd9378_rx_connect_port(struct snd_soc_component *component,
  597. u8 slv_port_type, u8 enable)
  598. {
  599. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  600. u8 port_id, num_ch, ch_mask, port_type;
  601. u32 ch_rate;
  602. u8 num_port = 1;
  603. int ret = 0;
  604. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  605. &num_ch, &ch_mask, &ch_rate,
  606. &port_type, CODEC_RX);
  607. if (ret)
  608. return ret;
  609. if (enable)
  610. ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
  611. num_port, &ch_mask, &ch_rate,
  612. &num_ch, &port_type);
  613. else
  614. ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
  615. num_port, &ch_mask, &port_type);
  616. return ret;
  617. }
  618. static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
  619. struct snd_kcontrol *kcontrol,
  620. int event)
  621. {
  622. struct snd_soc_component *component =
  623. snd_soc_dapm_to_component(w->dapm);
  624. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  625. int mode = wcd9378->hph_mode;
  626. int ret = 0;
  627. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  628. w->name, event);
  629. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  630. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  631. wcd9378_rx_connect_port(component, CLSH,
  632. SND_SOC_DAPM_EVENT_ON(event));
  633. }
  634. if (SND_SOC_DAPM_EVENT_OFF(event))
  635. ret = wcd9378_swr_slvdev_datapath_control(wcd9378->dev,
  636. RX_PATH, false);
  637. return ret;
  638. }
  639. static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  640. struct snd_kcontrol *kcontrol,
  641. int event)
  642. {
  643. struct snd_soc_component *component =
  644. snd_soc_dapm_to_component(w->dapm);
  645. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  646. u32 dmic_clk_reg, dmic_clk_en_reg;
  647. s32 *dmic_clk_cnt;
  648. u8 dmic_ctl_shift = 0;
  649. u8 dmic_clk_shift = 0;
  650. u8 dmic_clk_mask = 0;
  651. u32 dmic2_left_en = 0;
  652. int ret = 0;
  653. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  654. w->name, event);
  655. switch (w->shift) {
  656. case 0:
  657. case 1:
  658. dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
  659. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  660. dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
  661. dmic_clk_mask = 0x0F;
  662. dmic_clk_shift = 0x00;
  663. dmic_ctl_shift = 0x00;
  664. break;
  665. case 2:
  666. dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
  667. fallthrough;
  668. case 3:
  669. dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
  670. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  671. dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
  672. dmic_clk_mask = 0xF0;
  673. dmic_clk_shift = 0x04;
  674. dmic_ctl_shift = 0x01;
  675. break;
  676. case 4:
  677. case 5:
  678. dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
  679. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
  680. dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
  681. dmic_clk_mask = 0x0F;
  682. dmic_clk_shift = 0x00;
  683. dmic_ctl_shift = 0x02;
  684. break;
  685. default:
  686. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  687. __func__);
  688. return -EINVAL;
  689. };
  690. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  691. __func__, event, (w->shift + 1), *dmic_clk_cnt);
  692. switch (event) {
  693. case SND_SOC_DAPM_PRE_PMU:
  694. snd_soc_component_update_bits(component,
  695. WCD9378_CDC_AMIC_CTL,
  696. (0x01 << dmic_ctl_shift), 0x00);
  697. /* 250us sleep as per HW requirement */
  698. usleep_range(250, 260);
  699. if (dmic2_left_en)
  700. snd_soc_component_update_bits(component,
  701. dmic2_left_en, 0x80, 0x80);
  702. /* Setting DMIC clock rate to 2.4MHz */
  703. snd_soc_component_update_bits(component,
  704. dmic_clk_reg, dmic_clk_mask,
  705. (0x03 << dmic_clk_shift));
  706. snd_soc_component_update_bits(component,
  707. dmic_clk_en_reg, 0x08, 0x08);
  708. /* enable clock scaling */
  709. snd_soc_component_update_bits(component,
  710. WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
  711. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  712. wcd9378->tx_swr_dev->dev_num,
  713. true);
  714. break;
  715. case SND_SOC_DAPM_POST_PMD:
  716. wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
  717. false);
  718. snd_soc_component_update_bits(component,
  719. WCD9378_CDC_AMIC_CTL,
  720. (0x01 << dmic_ctl_shift),
  721. (0x01 << dmic_ctl_shift));
  722. if (dmic2_left_en)
  723. snd_soc_component_update_bits(component,
  724. dmic2_left_en, 0x80, 0x00);
  725. snd_soc_component_update_bits(component,
  726. dmic_clk_en_reg, 0x08, 0x00);
  727. break;
  728. };
  729. return ret;
  730. }
  731. /*
  732. * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
  733. * @micb_mv: micbias in mv
  734. *
  735. * return register value converted
  736. */
  737. int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
  738. {
  739. /* min micbias voltage is 1V and maximum is 2.85V */
  740. if (micb_mv < 1000 || micb_mv > 2850) {
  741. pr_err("%s: unsupported micbias voltage\n", __func__);
  742. return -EINVAL;
  743. }
  744. return (micb_mv - 1000) / 50;
  745. }
  746. EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
  747. /*
  748. * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  749. * @component: handle to snd_soc_component *
  750. * @req_volt: micbias voltage to be set
  751. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  752. *
  753. * return 0 if adjustment is success or error code in case of failure
  754. */
  755. static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
  756. u32 micb_mv, int micb_num)
  757. {
  758. int vcout_ctl;
  759. switch (micb_mv) {
  760. case 2200:
  761. return MICB_USAGE_VAL_2P2V;
  762. case 2700:
  763. return MICB_USAGE_VAL_2P7V;
  764. case 2800:
  765. return MICB_USAGE_VAL_2P8V;
  766. default:
  767. vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
  768. if (micb_num == MIC_BIAS_1) {
  769. snd_soc_component_update_bits(component,
  770. WCD9378_MICB_REMAP_TABLE_VAL_3,
  771. WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
  772. vcout_ctl);
  773. return MICB_USAGE_VAL_MICB1_TABLE_VAL;
  774. } else if (micb_num == MIC_BIAS_2) {
  775. snd_soc_component_update_bits(component,
  776. WCD9378_MICB_REMAP_TABLE_VAL_4,
  777. WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
  778. vcout_ctl);
  779. return MICB_USAGE_VAL_MICB2_TABLE_VAL;
  780. } else if (micb_num == MIC_BIAS_3) {
  781. snd_soc_component_update_bits(component,
  782. WCD9378_MICB_REMAP_TABLE_VAL_5,
  783. WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
  784. vcout_ctl);
  785. return MICB_USAGE_VAL_MICB3_TABLE_VAL;
  786. }
  787. }
  788. return 0;
  789. }
  790. static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
  791. u32 micb_mv, int micb_num)
  792. {
  793. switch (micb_mv) {
  794. case 0:
  795. return MICB_USAGE_VAL_PULL_DOWN;
  796. case 1200:
  797. return MICB_USAGE_VAL_1P2V;
  798. case 1800:
  799. return MICB_USAGE_VAL_1P8VORPULLUP;
  800. case 2500:
  801. return MICB_USAGE_VAL_2P5V;
  802. case 2750:
  803. return MICB_USAGE_VAL_2P75V;
  804. default:
  805. return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
  806. }
  807. return MICB_USAGE_VAL_DISABLE;
  808. }
  809. int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  810. int req_volt, int micb_num)
  811. {
  812. struct wcd9378_priv *wcd9378 =
  813. snd_soc_component_get_drvdata(component);
  814. int micb_usage = 0, micb_mask = 0, req_vout_ctl = 0;
  815. if (wcd9378 == NULL) {
  816. dev_err(component->dev,
  817. "%s: wcd9378 private data is NULL\n", __func__);
  818. return -EINVAL;
  819. }
  820. switch (micb_num) {
  821. case MIC_BIAS_1:
  822. micb_usage = WCD9378_IT11_USAGE;
  823. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  824. break;
  825. case MIC_BIAS_2:
  826. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  827. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  828. break;
  829. case MIC_BIAS_3:
  830. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  831. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  832. break;
  833. default:
  834. dev_err(component->dev,
  835. "%s: wcd9378 private data is NULL\n", __func__);
  836. break;
  837. }
  838. mutex_lock(&wcd9378->micb_lock);
  839. req_vout_ctl =
  840. wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
  841. snd_soc_component_update_bits(component,
  842. micb_usage, micb_mask, req_vout_ctl);
  843. if (micb_num == MIC_BIAS_2) {
  844. dev_err(component->dev,
  845. "%s: sj micbias set\n", __func__);
  846. snd_soc_component_update_bits(component,
  847. WCD9378_IT31_MICB,
  848. WCD9378_IT31_MICB_IT31_MICB_MASK,
  849. req_vout_ctl);
  850. wcd9378->curr_micbias2 = req_volt;
  851. }
  852. mutex_unlock(&wcd9378->micb_lock);
  853. return 0;
  854. }
  855. EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
  856. void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  857. bool bcs_disable)
  858. {
  859. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  860. if (wcd9378->update_wcd_event) {
  861. if (bcs_disable)
  862. wcd9378->update_wcd_event(wcd9378->handle,
  863. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  864. else
  865. wcd9378->update_wcd_event(wcd9378->handle,
  866. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  867. }
  868. }
  869. static void wcd9378_get_swr_clk_val(
  870. struct snd_soc_component *component,
  871. int rate)
  872. {
  873. struct wcd9378_priv *wcd9378 =
  874. snd_soc_component_get_drvdata(component);
  875. switch (rate) {
  876. case SWR_CLK_RATE_4P8MHZ:
  877. wcd9378->tx_swrclk = SWR_BASECLK_19P2MHZ;
  878. wcd9378->tx_clkscale = SWR_CLKSCALE_DIV4;
  879. break;
  880. case SWR_CLK_RATE_9P6MHZ:
  881. wcd9378->tx_swrclk = SWR_BASECLK_19P2MHZ;
  882. wcd9378->tx_clkscale = SWR_CLKSCALE_DIV2;
  883. break;
  884. default:
  885. dev_dbg(component->dev, "%s: unsupport rate: %d\n",
  886. __func__, rate);
  887. break;
  888. }
  889. dev_dbg(component->dev, "%s: rate: %d, tx_swrclk: 0x%x, tx_clkscale: 0x%x\n",
  890. __func__, rate, wcd9378->tx_swrclk, wcd9378->tx_clkscale);
  891. }
  892. static int wcd9378_get_clk_rate(int mode)
  893. {
  894. int rate;
  895. switch (mode) {
  896. case ADC_MODE_LP:
  897. rate = SWR_CLK_RATE_4P8MHZ;
  898. break;
  899. case ADC_MODE_INVALID:
  900. case ADC_MODE_NORMAL:
  901. case ADC_MODE_HIFI:
  902. default:
  903. rate = SWR_CLK_RATE_9P6MHZ;
  904. break;
  905. }
  906. pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
  907. return rate;
  908. }
  909. static int wcd9378_get_adc_mode_val(int mode)
  910. {
  911. int ret = 0;
  912. switch (mode) {
  913. case ADC_MODE_INVALID:
  914. case ADC_MODE_NORMAL:
  915. ret = ADC_MODE_VAL_NORMAL;
  916. break;
  917. case ADC_MODE_HIFI:
  918. ret = ADC_MODE_VAL_HIFI;
  919. break;
  920. case ADC_MODE_LP:
  921. ret = ADC_MODE_VAL_LP;
  922. break;
  923. default:
  924. ret = -EINVAL;
  925. pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
  926. break;
  927. }
  928. return ret;
  929. }
  930. static int wcd9378_sys_usage_auto_udpate(struct snd_soc_component *component,
  931. int sys_usage_bit, bool set_enable)
  932. {
  933. struct wcd9378_priv *wcd9378 =
  934. snd_soc_component_get_drvdata(component);
  935. int i = 0;
  936. dev_dbg(component->dev,
  937. "%s: enter, current sys_usage: %d, sys_usage_status: 0x%x, sys_usage_bit: %d, set_enable: %d\n",
  938. __func__, wcd9378->sys_usage,
  939. wcd9378->sys_usage_status,
  940. sys_usage_bit, set_enable);
  941. mutex_lock(&wcd9378->sys_usage_lock);
  942. if (set_enable) {
  943. set_bit(sys_usage_bit, &wcd9378->sys_usage_status);
  944. if ((sys_usage[wcd9378->sys_usage] &
  945. wcd9378->sys_usage_status) == wcd9378->sys_usage_status)
  946. goto exit;
  947. for (i = 0; i < SYS_USAGE_NUM; i++) {
  948. if ((sys_usage[i] & wcd9378->sys_usage_status)
  949. == wcd9378->sys_usage_status) {
  950. snd_soc_component_update_bits(component,
  951. WCD9378_SYS_USAGE_CTRL,
  952. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  953. i);
  954. wcd9378->sys_usage = i;
  955. dev_dbg(component->dev, "%s: update sys_usage: %d\n",
  956. __func__, wcd9378->sys_usage);
  957. goto exit;
  958. }
  959. }
  960. dev_dbg(component->dev, "%s: cannot find sys_usage\n",
  961. __func__);
  962. } else {
  963. clear_bit(sys_usage_bit, &wcd9378->sys_usage_status);
  964. }
  965. exit:
  966. mutex_unlock(&wcd9378->sys_usage_lock);
  967. return 0;
  968. }
  969. static int wcd9378_sys_usage_bit_get(
  970. struct snd_soc_component *component, u32 w_shift,
  971. int *sys_usage_bit, int event)
  972. {
  973. struct wcd9378_priv *wcd9378 =
  974. snd_soc_component_get_drvdata(component);
  975. dev_dbg(component->dev, "%s: wshift: %d event: %d\n", __func__,
  976. w_shift, event);
  977. switch (event) {
  978. case SND_SOC_DAPM_PRE_PMU:
  979. switch (w_shift) {
  980. case ADC1:
  981. if ((snd_soc_component_read(component,
  982. WCD9378_TX_NEW_TX_CH12_MUX) &
  983. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK) == 0x01) {
  984. *sys_usage_bit = TX0_AMIC1_EN;
  985. } else if ((snd_soc_component_read(component,
  986. WCD9378_TX_NEW_TX_CH12_MUX) &
  987. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK) == 0x02) {
  988. *sys_usage_bit = TX0_AMIC2_EN;
  989. } else {
  990. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  991. __func__);
  992. return -EINVAL;
  993. }
  994. break;
  995. case ADC2:
  996. if ((snd_soc_component_read(component,
  997. WCD9378_TX_NEW_TX_CH12_MUX) &
  998. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10) {
  999. *sys_usage_bit = TX1_AMIC2_EN;
  1000. } else if ((snd_soc_component_read(component,
  1001. WCD9378_TX_NEW_TX_CH12_MUX) &
  1002. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x18) {
  1003. *sys_usage_bit = TX1_AMIC3_EN;
  1004. } else {
  1005. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  1006. __func__);
  1007. return -EINVAL;
  1008. }
  1009. break;
  1010. case ADC3:
  1011. if ((snd_soc_component_read(component,
  1012. WCD9378_TX_NEW_TX_CH34_MUX) &
  1013. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_MASK) == 0x01) {
  1014. *sys_usage_bit = TX2_AMIC1_EN;
  1015. } else if ((snd_soc_component_read(component,
  1016. WCD9378_TX_NEW_TX_CH34_MUX) &
  1017. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_MASK) == 0x03) {
  1018. *sys_usage_bit = TX2_AMIC4_EN;
  1019. } else {
  1020. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  1021. __func__);
  1022. return -EINVAL;
  1023. }
  1024. break;
  1025. default:
  1026. break;
  1027. }
  1028. break;
  1029. case SND_SOC_DAPM_POST_PMD:
  1030. switch (w_shift) {
  1031. case ADC1:
  1032. if (test_bit(TX0_AMIC1_EN, &wcd9378->sys_usage_status))
  1033. *sys_usage_bit = TX0_AMIC1_EN;
  1034. if (test_bit(TX0_AMIC2_EN, &wcd9378->sys_usage_status))
  1035. *sys_usage_bit = TX0_AMIC2_EN;
  1036. break;
  1037. case ADC2:
  1038. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  1039. *sys_usage_bit = TX1_AMIC2_EN;
  1040. if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status))
  1041. *sys_usage_bit = TX1_AMIC3_EN;
  1042. break;
  1043. case ADC3:
  1044. if (test_bit(TX2_AMIC1_EN, &wcd9378->sys_usage_status))
  1045. *sys_usage_bit = TX2_AMIC1_EN;
  1046. if (test_bit(TX2_AMIC4_EN, &wcd9378->sys_usage_status))
  1047. *sys_usage_bit = TX2_AMIC4_EN;
  1048. break;
  1049. default:
  1050. break;
  1051. }
  1052. break;
  1053. default:
  1054. break;
  1055. }
  1056. dev_dbg(component->dev, "%s: done, event: %d, sys_usage_bit: %d\n",
  1057. __func__, event, *sys_usage_bit);
  1058. return 0;
  1059. }
  1060. static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
  1061. struct snd_kcontrol *kcontrol, int event)
  1062. {
  1063. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1064. struct wcd9378_priv *wcd9378 =
  1065. snd_soc_component_get_drvdata(component);
  1066. int mode_val = 0, bank = 0, ret = 0, rate = 0;
  1067. int act_ps = 0, sys_usage_bit = 0;
  1068. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
  1069. wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
  1070. dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
  1071. w->name, w->shift, event);
  1072. ret = wcd9378_sys_usage_bit_get(component, w->shift, &sys_usage_bit, event);
  1073. if (ret < 0)
  1074. return ret;
  1075. switch (event) {
  1076. case SND_SOC_DAPM_PRE_PMU:
  1077. /*Update sys_usage*/
  1078. wcd9378_sys_usage_auto_udpate(component, sys_usage_bit, true);
  1079. mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
  1080. if (mode_val < 0) {
  1081. dev_dbg(component->dev,
  1082. "%s: invalid mode, setting to normal mode\n",
  1083. __func__);
  1084. mode_val = ADC_MODE_VAL_NORMAL;
  1085. }
  1086. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  1087. if (w->shift == ADC2 && !((snd_soc_component_read(component,
  1088. WCD9378_TX_NEW_TX_CH12_MUX) &
  1089. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
  1090. if (!wcd9378->bcs_dis) {
  1091. wcd9378_tx_connect_port(component, MBHC,
  1092. SWR_CLK_RATE_4P8MHZ, true);
  1093. set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1094. }
  1095. }
  1096. set_bit(w->shift - ADC1, &wcd9378->status_mask);
  1097. wcd9378_tx_connect_port(component, w->shift, rate,
  1098. true);
  1099. wcd9378_get_swr_clk_val(component, rate);
  1100. switch (w->shift) {
  1101. case ADC1:
  1102. /*SMP MIC0 IT11 USAGE SET*/
  1103. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  1104. WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
  1105. /*Hold TXFE in Initialization During Startup*/
  1106. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1107. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
  1108. /*Power up TX0 sequencer*/
  1109. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1110. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  1111. break;
  1112. case ADC2:
  1113. /*Check if amic2 is connected to ADC2 MUX*/
  1114. if ((snd_soc_component_read(component,
  1115. WCD9378_TX_NEW_TX_CH12_MUX) &
  1116. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10) {
  1117. /*SMP JACK IT31 USAGE SET*/
  1118. snd_soc_component_update_bits(component,
  1119. WCD9378_IT31_USAGE,
  1120. WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
  1121. /*Power up TX1 sequencer*/
  1122. snd_soc_component_update_bits(component,
  1123. WCD9378_PDE34_REQ_PS,
  1124. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
  1125. } else {
  1126. snd_soc_component_update_bits(component,
  1127. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  1128. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  1129. mode_val);
  1130. /*Hold TXFE in Initialization During Startup*/
  1131. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1132. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
  1133. /*Power up TX1 sequencer*/
  1134. snd_soc_component_update_bits(component,
  1135. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  1136. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  1137. 0x00);
  1138. }
  1139. break;
  1140. case ADC3:
  1141. /*SMP MIC2 IT11 USAGE SET*/
  1142. snd_soc_component_update_bits(component,
  1143. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  1144. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  1145. mode_val);
  1146. /*Hold TXFE in Initialization During Startup*/
  1147. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1148. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
  1149. /*Power up TX2 sequencer*/
  1150. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  1151. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  1152. break;
  1153. default:
  1154. break;
  1155. }
  1156. /*default delay 800us*/
  1157. usleep_range(800, 810);
  1158. wcd9378_swr_slvdev_datapath_control(wcd9378->dev, TX_PATH, true);
  1159. switch (w->shift) {
  1160. case ADC1:
  1161. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1162. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1163. act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
  1164. if (act_ps)
  1165. dev_dbg(component->dev,
  1166. "%s: TX0 sequencer power on failed\n", __func__);
  1167. else
  1168. dev_dbg(component->dev,
  1169. "%s: TX0 sequencer power on success\n", __func__);
  1170. break;
  1171. case ADC2:
  1172. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1173. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
  1174. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  1175. act_ps = snd_soc_component_read(component,
  1176. WCD9378_PDE34_ACT_PS);
  1177. else
  1178. act_ps = snd_soc_component_read(component,
  1179. WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
  1180. if (act_ps)
  1181. dev_dbg(component->dev,
  1182. "%s: TX1 sequencer power on failed\n", __func__);
  1183. else
  1184. dev_dbg(component->dev,
  1185. "%s: TX1 sequencer power on success\n", __func__);
  1186. break;
  1187. case ADC3:
  1188. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1189. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1190. act_ps = snd_soc_component_read(component,
  1191. WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS);
  1192. if (act_ps)
  1193. dev_dbg(component->dev,
  1194. "%s: TX2 sequencer power on failed\n", __func__);
  1195. else
  1196. dev_dbg(component->dev,
  1197. "%s: TX2 sequencer power on success\n", __func__);
  1198. break;
  1199. };
  1200. break;
  1201. case SND_SOC_DAPM_POST_PMD:
  1202. wcd9378_tx_connect_port(component, w->shift, 0, false);
  1203. if (w->shift == ADC2 &&
  1204. test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
  1205. wcd9378_tx_connect_port(component, MBHC, 0,
  1206. false);
  1207. clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1208. }
  1209. switch (w->shift) {
  1210. case ADC1:
  1211. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  1212. WCD9378_IT11_USAGE_IT11_USAGE_MASK, 0x00);
  1213. /*Normal TXFE Startup*/
  1214. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1215. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1216. /*tear down TX0 sequencer*/
  1217. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1218. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1219. break;
  1220. case ADC2:
  1221. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status)) {
  1222. snd_soc_component_update_bits(component,
  1223. WCD9378_IT31_USAGE,
  1224. WCD9378_IT31_USAGE_IT31_USAGE_MASK, 0x00);
  1225. /*tear down TX1 sequencer*/
  1226. snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
  1227. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
  1228. }
  1229. if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status)) {
  1230. snd_soc_component_update_bits(component,
  1231. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  1232. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  1233. 0x00);
  1234. /*Normal TXFE Startup*/
  1235. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1236. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1237. /*tear down TX1 sequencer*/
  1238. snd_soc_component_update_bits(component,
  1239. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  1240. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  1241. 0x03);
  1242. }
  1243. break;
  1244. case ADC3:
  1245. snd_soc_component_update_bits(component,
  1246. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  1247. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  1248. 0x00);
  1249. /*Normal TXFE Startup*/
  1250. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1251. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1252. /*tear down TX2 sequencer*/
  1253. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  1254. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1255. break;
  1256. default:
  1257. break;
  1258. }
  1259. /*default delay 800us*/
  1260. usleep_range(800, 810);
  1261. /*Disable sys_usage_status*/
  1262. wcd9378_sys_usage_auto_udpate(component, sys_usage_bit, false);
  1263. wcd9378_swr_slvdev_datapath_control(wcd9378->dev, TX_PATH, false);
  1264. break;
  1265. default:
  1266. break;
  1267. }
  1268. return ret;
  1269. }
  1270. static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1271. struct snd_kcontrol *kcontrol,
  1272. int event)
  1273. {
  1274. struct snd_soc_component *component =
  1275. snd_soc_dapm_to_component(w->dapm);
  1276. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1277. int ret = 0;
  1278. switch (event) {
  1279. case SND_SOC_DAPM_PRE_PMU:
  1280. wcd9378_tx_connect_port(component, w->shift,
  1281. SWR_CLK_RATE_2P4MHZ, true);
  1282. break;
  1283. case SND_SOC_DAPM_POST_PMD:
  1284. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1285. wcd9378->tx_swr_dev->dev_num,
  1286. false);
  1287. break;
  1288. };
  1289. return ret;
  1290. }
  1291. static int wcd9378_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1292. struct snd_kcontrol *kcontrol,
  1293. int event)
  1294. {
  1295. struct snd_soc_component *component =
  1296. snd_soc_dapm_to_component(w->dapm);
  1297. int micb_num = 0;
  1298. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1299. __func__, w->name, event);
  1300. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1301. micb_num = MIC_BIAS_1;
  1302. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1303. micb_num = MIC_BIAS_2;
  1304. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1305. micb_num = MIC_BIAS_3;
  1306. else
  1307. return -EINVAL;
  1308. switch (event) {
  1309. case SND_SOC_DAPM_PRE_PMU:
  1310. wcd9378_micbias_control(component, micb_num,
  1311. MICB_ENABLE, true);
  1312. break;
  1313. case SND_SOC_DAPM_POST_PMU:
  1314. usleep_range(1000, 1100);
  1315. break;
  1316. case SND_SOC_DAPM_POST_PMD:
  1317. wcd9378_micbias_control(component, micb_num,
  1318. MICB_DISABLE, true);
  1319. break;
  1320. };
  1321. return 0;
  1322. }
  1323. static int wcd9378_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1324. struct snd_kcontrol *kcontrol,
  1325. int event)
  1326. {
  1327. struct snd_soc_component *component =
  1328. snd_soc_dapm_to_component(w->dapm);
  1329. int micb_num = 0;
  1330. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1331. __func__, w->name, event);
  1332. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1333. micb_num = MIC_BIAS_1;
  1334. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1335. micb_num = MIC_BIAS_2;
  1336. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1337. micb_num = MIC_BIAS_3;
  1338. else
  1339. return -EINVAL;
  1340. switch (event) {
  1341. case SND_SOC_DAPM_PRE_PMU:
  1342. wcd9378_micbias_control(component, micb_num,
  1343. MICB_PULLUP_ENABLE, true);
  1344. break;
  1345. case SND_SOC_DAPM_POST_PMU:
  1346. usleep_range(1000, 1100);
  1347. break;
  1348. case SND_SOC_DAPM_POST_PMD:
  1349. wcd9378_micbias_control(component, micb_num,
  1350. MICB_PULLUP_DISABLE, true);
  1351. break;
  1352. };
  1353. return 0;
  1354. }
  1355. /*
  1356. * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
  1357. * @component: handle to snd_soc_component *
  1358. *
  1359. * return wcd9378_mbhc handle or error code in case of failure
  1360. */
  1361. struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
  1362. {
  1363. struct wcd9378_priv *wcd9378;
  1364. if (!component) {
  1365. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  1366. return NULL;
  1367. }
  1368. wcd9378 = snd_soc_component_get_drvdata(component);
  1369. if (!wcd9378) {
  1370. pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
  1371. return NULL;
  1372. }
  1373. return wcd9378->mbhc;
  1374. }
  1375. EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
  1376. static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1377. struct snd_kcontrol *kcontrol,
  1378. int event)
  1379. {
  1380. struct snd_soc_component *component =
  1381. snd_soc_dapm_to_component(w->dapm);
  1382. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1383. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1384. w->name, event);
  1385. switch (event) {
  1386. case SND_SOC_DAPM_PRE_PMU:
  1387. /*OCP FSM EN*/
  1388. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1389. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  1390. /*SCD OP EN*/
  1391. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1392. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  1393. /*HPHL ENABLE*/
  1394. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1395. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1396. /*OPAMP_CHOP_CLK DISABLE*/
  1397. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  1398. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  1399. wcd9378_rx_connect_port(component, HPH_L, true);
  1400. if (wcd9378->comp1_enable) {
  1401. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1402. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
  1403. wcd9378_rx_connect_port(component, COMP_L, true);
  1404. }
  1405. break;
  1406. case SND_SOC_DAPM_POST_PMD:
  1407. /*OCP FSM DISABLE*/
  1408. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1409. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x00);
  1410. /*SCD OP DISABLE*/
  1411. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1412. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x00);
  1413. /*HPHL DISABLE*/
  1414. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1415. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1416. wcd9378_rx_connect_port(component, HPH_L, false);
  1417. if (wcd9378->comp1_enable)
  1418. wcd9378_rx_connect_port(component, COMP_L, false);
  1419. break;
  1420. default:
  1421. break;
  1422. };
  1423. return 0;
  1424. }
  1425. static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1426. struct snd_kcontrol *kcontrol,
  1427. int event)
  1428. {
  1429. struct snd_soc_component *component =
  1430. snd_soc_dapm_to_component(w->dapm);
  1431. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1432. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1433. w->name, event);
  1434. switch (event) {
  1435. case SND_SOC_DAPM_PRE_PMU:
  1436. /*OCP FSM EN*/
  1437. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1438. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  1439. /*SCD OP EN*/
  1440. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1441. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  1442. /*HPHR ENABLE*/
  1443. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1444. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1445. /*OPAMP_CHOP_CLK DISABLE*/
  1446. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  1447. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  1448. wcd9378_rx_connect_port(component, HPH_R, true);
  1449. if (wcd9378->comp2_enable) {
  1450. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1451. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
  1452. wcd9378_rx_connect_port(component, COMP_R, true);
  1453. }
  1454. break;
  1455. case SND_SOC_DAPM_POST_PMD:
  1456. /*OCP FSM DISABLE*/
  1457. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1458. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x00);
  1459. /*SCD OP DISABLE*/
  1460. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1461. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x00);
  1462. /*HPHR DISABLE*/
  1463. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1464. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
  1465. wcd9378_rx_connect_port(component, HPH_R, false);
  1466. if (wcd9378->comp2_enable)
  1467. wcd9378_rx_connect_port(component, COMP_R, false);
  1468. break;
  1469. default:
  1470. break;
  1471. };
  1472. return 0;
  1473. }
  1474. static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1475. struct snd_kcontrol *kcontrol,
  1476. int event)
  1477. {
  1478. struct snd_soc_component *component =
  1479. snd_soc_dapm_to_component(w->dapm);
  1480. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1481. int bank = 0;
  1482. int act_ps = 0;
  1483. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1484. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1485. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1486. w->name, event);
  1487. switch (event) {
  1488. case SND_SOC_DAPM_PRE_PMU:
  1489. if (wcd9378->update_wcd_event)
  1490. wcd9378->update_wcd_event(wcd9378->handle,
  1491. SLV_BOLERO_EVT_RX_MUTE,
  1492. (WCD_RX1 << 0x10 | 0x01));
  1493. if (wcd9378->update_wcd_event)
  1494. wcd9378->update_wcd_event(wcd9378->handle,
  1495. SLV_BOLERO_EVT_RX_MUTE,
  1496. (WCD_RX1 << 0x10));
  1497. wcd_enable_irq(&wcd9378->irq_info,
  1498. WCD9378_IRQ_HPHL_PDM_WD_INT);
  1499. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1500. if (act_ps)
  1501. dev_dbg(component->dev,
  1502. "%s: HPH sequencer power on failed\n", __func__);
  1503. else
  1504. dev_dbg(component->dev,
  1505. "%s: HPH sequencer power on success\n", __func__);
  1506. break;
  1507. case SND_SOC_DAPM_POST_PMD:
  1508. if (wcd9378->update_wcd_event)
  1509. wcd9378->update_wcd_event(wcd9378->handle,
  1510. SLV_BOLERO_EVT_RX_MUTE,
  1511. (WCD_RX1 << 0x10 | 0x1));
  1512. wcd_disable_irq(&wcd9378->irq_info,
  1513. WCD9378_IRQ_HPHL_PDM_WD_INT);
  1514. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1515. wcd9378->update_wcd_event(wcd9378->handle,
  1516. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1517. (WCD_RX1 << 0x10));
  1518. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1519. WCD_EVENT_POST_HPHL_PA_OFF,
  1520. &wcd9378->mbhc->wcd_mbhc);
  1521. break;
  1522. default:
  1523. break;
  1524. };
  1525. return 0;
  1526. }
  1527. static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1528. struct snd_kcontrol *kcontrol,
  1529. int event)
  1530. {
  1531. struct snd_soc_component *component =
  1532. snd_soc_dapm_to_component(w->dapm);
  1533. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1534. int act_ps = 0;
  1535. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1536. w->name, event);
  1537. switch (event) {
  1538. case SND_SOC_DAPM_PRE_PMU:
  1539. if (wcd9378->update_wcd_event)
  1540. wcd9378->update_wcd_event(wcd9378->handle,
  1541. SLV_BOLERO_EVT_RX_MUTE,
  1542. (WCD_RX2 << 0x10 | 0x1));
  1543. if (wcd9378->update_wcd_event)
  1544. wcd9378->update_wcd_event(wcd9378->handle,
  1545. SLV_BOLERO_EVT_RX_MUTE,
  1546. (WCD_RX2 << 0x10));
  1547. wcd_enable_irq(&wcd9378->irq_info,
  1548. WCD9378_IRQ_HPHR_PDM_WD_INT);
  1549. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1550. if (act_ps)
  1551. dev_dbg(component->dev,
  1552. "%s: HPH sequencer power on failed\n", __func__);
  1553. else
  1554. dev_dbg(component->dev,
  1555. "%s: HPH sequencer power on success\n", __func__);
  1556. break;
  1557. case SND_SOC_DAPM_POST_PMD:
  1558. if (wcd9378->update_wcd_event)
  1559. wcd9378->update_wcd_event(wcd9378->handle,
  1560. SLV_BOLERO_EVT_RX_MUTE,
  1561. (WCD_RX2 << 0x10 | 0x1));
  1562. wcd_disable_irq(&wcd9378->irq_info,
  1563. WCD9378_IRQ_HPHR_PDM_WD_INT);
  1564. if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
  1565. wcd9378->update_wcd_event(wcd9378->handle,
  1566. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1567. (WCD_RX2 << 0x10));
  1568. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1569. WCD_EVENT_POST_HPHR_PA_OFF,
  1570. &wcd9378->mbhc->wcd_mbhc);
  1571. break;
  1572. default:
  1573. break;
  1574. };
  1575. return 0;
  1576. }
  1577. static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1578. struct snd_kcontrol *kcontrol,
  1579. int event)
  1580. {
  1581. struct snd_soc_component *component =
  1582. snd_soc_dapm_to_component(w->dapm);
  1583. struct wcd9378_priv *wcd9378 =
  1584. snd_soc_component_get_drvdata(component);
  1585. int ret = 0, act_ps = 0;
  1586. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1587. w->name, event);
  1588. switch (event) {
  1589. case SND_SOC_DAPM_PRE_PMU:
  1590. wcd9378_swr_slvdev_datapath_control(wcd9378->dev, RX_PATH, true);
  1591. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1592. if (wcd9378->update_wcd_event)
  1593. wcd9378->update_wcd_event(wcd9378->handle,
  1594. SLV_BOLERO_EVT_RX_MUTE,
  1595. (WCD_RX2 << 0x10));
  1596. wcd_enable_irq(&wcd9378->irq_info,
  1597. WCD9378_IRQ_HPHR_PDM_WD_INT);
  1598. } else {
  1599. if (wcd9378->update_wcd_event)
  1600. wcd9378->update_wcd_event(wcd9378->handle,
  1601. SLV_BOLERO_EVT_RX_MUTE,
  1602. (WCD_RX3 << 0x10));
  1603. wcd_enable_irq(&wcd9378->irq_info,
  1604. WCD9378_IRQ_AUX_PDM_WD_INT);
  1605. }
  1606. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1607. if (act_ps)
  1608. dev_dbg(component->dev,
  1609. "%s: SA sequencer power on failed\n", __func__);
  1610. else
  1611. dev_dbg(component->dev,
  1612. "%s: SA sequencer power on success\n", __func__);
  1613. break;
  1614. case SND_SOC_DAPM_POST_PMD:
  1615. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1616. if (wcd9378->update_wcd_event)
  1617. wcd9378->update_wcd_event(wcd9378->handle,
  1618. SLV_BOLERO_EVT_RX_MUTE,
  1619. (WCD_RX2 << 0x10 | 0x1));
  1620. wcd_disable_irq(&wcd9378->irq_info,
  1621. WCD9378_IRQ_HPHR_PDM_WD_INT);
  1622. } else {
  1623. if (wcd9378->update_wcd_event)
  1624. wcd9378->update_wcd_event(wcd9378->handle,
  1625. SLV_BOLERO_EVT_RX_MUTE,
  1626. (WCD_RX3 << 0x10 | 0x1));
  1627. wcd_disable_irq(&wcd9378->irq_info,
  1628. WCD9378_IRQ_AUX_PDM_WD_INT);
  1629. }
  1630. break;
  1631. };
  1632. return ret;
  1633. }
  1634. static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1635. struct snd_kcontrol *kcontrol,
  1636. int event)
  1637. {
  1638. struct snd_soc_component *component =
  1639. snd_soc_dapm_to_component(w->dapm);
  1640. struct wcd9378_priv *wcd9378 =
  1641. snd_soc_component_get_drvdata(component);
  1642. int ret = 0, act_ps = 0;
  1643. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1644. w->name, event);
  1645. switch (event) {
  1646. case SND_SOC_DAPM_PRE_PMU:
  1647. wcd9378_swr_slvdev_datapath_control(wcd9378->dev, RX_PATH, true);
  1648. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1649. if (wcd9378->update_wcd_event)
  1650. wcd9378->update_wcd_event(wcd9378->handle,
  1651. SLV_BOLERO_EVT_RX_MUTE,
  1652. (WCD_RX1 << 0x10));
  1653. wcd_enable_irq(&wcd9378->irq_info,
  1654. WCD9378_IRQ_HPHL_PDM_WD_INT);
  1655. } else {
  1656. if (wcd9378->update_wcd_event)
  1657. wcd9378->update_wcd_event(wcd9378->handle,
  1658. SLV_BOLERO_EVT_RX_MUTE,
  1659. (WCD_RX3 << 0x10));
  1660. wcd_enable_irq(&wcd9378->irq_info,
  1661. WCD9378_IRQ_AUX_PDM_WD_INT);
  1662. }
  1663. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1664. if (act_ps)
  1665. dev_dbg(component->dev,
  1666. "%s: SA sequencer power on failed\n", __func__);
  1667. else
  1668. dev_dbg(component->dev,
  1669. "%s: SA sequencer power on successful\n", __func__);
  1670. break;
  1671. case SND_SOC_DAPM_POST_PMD:
  1672. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1673. if (wcd9378->update_wcd_event)
  1674. wcd9378->update_wcd_event(wcd9378->handle,
  1675. SLV_BOLERO_EVT_RX_MUTE,
  1676. (WCD_RX1 << 0x10 | 0x1));
  1677. wcd_disable_irq(&wcd9378->irq_info,
  1678. WCD9378_IRQ_HPHL_PDM_WD_INT);
  1679. } else {
  1680. if (wcd9378->update_wcd_event)
  1681. wcd9378->update_wcd_event(wcd9378->handle,
  1682. SLV_BOLERO_EVT_RX_MUTE,
  1683. (WCD_RX3 << 0x10 | 0x1));
  1684. wcd_disable_irq(&wcd9378->irq_info,
  1685. WCD9378_IRQ_AUX_PDM_WD_INT);
  1686. }
  1687. break;
  1688. };
  1689. return ret;
  1690. }
  1691. static int wcd9378_get_hph_pwr_level(int hph_mode)
  1692. {
  1693. switch (hph_mode) {
  1694. case CLS_H_LOHIFI:
  1695. case CLS_AB_LOHIFI:
  1696. return PWR_LEVEL_LOHIFI_VAL;
  1697. case CLS_H_LP:
  1698. case CLS_AB_LP:
  1699. return PWR_LEVEL_LP_VAL;
  1700. case CLS_H_HIFI:
  1701. case CLS_AB_HIFI:
  1702. return PWR_LEVEL_HIFI_VAL;
  1703. case CLS_H_ULP:
  1704. case CLS_AB:
  1705. case CLS_H_NORMAL:
  1706. default:
  1707. return PWR_LEVEL_ULP_VAL;
  1708. }
  1709. return PWR_LEVEL_ULP_VAL;
  1710. }
  1711. static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
  1712. {
  1713. struct wcd9378_priv *wcd9378 =
  1714. snd_soc_component_get_drvdata(component);
  1715. u8 msb_val = 0, lsb_val = 0;
  1716. if ((!wcd9378->comp1_enable) &&
  1717. (!wcd9378->comp2_enable)) {
  1718. msb_val = (wcd9378->hph_gain >> 8);
  1719. lsb_val = (wcd9378->hph_gain & 0x00ff);
  1720. regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH1_MSB, msb_val);
  1721. regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH1_LSB, lsb_val);
  1722. regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH2_MSB, msb_val);
  1723. regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH2_LSB, lsb_val);
  1724. }
  1725. }
  1726. static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
  1727. struct snd_kcontrol *kcontrol, int event)
  1728. {
  1729. struct snd_soc_component *component =
  1730. snd_soc_dapm_to_component(w->dapm);
  1731. struct wcd9378_priv *wcd9378 =
  1732. snd_soc_component_get_drvdata(component);
  1733. int power_level, ret = 0;
  1734. struct swr_device *swr_dev = wcd9378->tx_swr_dev;
  1735. u8 commit_val = 0x02;
  1736. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1737. w->name, event);
  1738. switch (event) {
  1739. case SND_SOC_DAPM_PRE_PMU:
  1740. wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, true);
  1741. regmap_write(wcd9378->regmap, WCD9378_CMT_GRP_MASK, 0x02);
  1742. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
  1743. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
  1744. WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
  1745. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
  1746. WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
  1747. }
  1748. if ((wcd9378->hph_mode == CLS_AB) ||
  1749. (wcd9378->hph_mode == CLS_AB_HIFI) ||
  1750. (wcd9378->hph_mode == CLS_AB_LP) ||
  1751. (wcd9378->hph_mode == CLS_AB_LOHIFI))
  1752. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1753. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1754. /*GET HPH_MODE*/
  1755. power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
  1756. /*SET HPH_MODE*/
  1757. snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
  1758. WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
  1759. /*TURN ON HPH SEQUENCER*/
  1760. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1761. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
  1762. wcd9378_hph_set_channel_volume(component);
  1763. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
  1764. /*PA delay is 22400us*/
  1765. usleep_range(22500, 22510);
  1766. else
  1767. /*COMP delay is 9400us*/
  1768. usleep_range(9500, 9510);
  1769. regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH1_CN, 0x00);
  1770. regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH2_CN, 0x00);
  1771. if (wcd9378->sys_usage == SYS_USAGE_10)
  1772. /*FU23 UNMUTE*/
  1773. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1774. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1775. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &commit_val);
  1776. wcd9378_swr_slvdev_datapath_control(wcd9378->dev, RX_PATH, true);
  1777. break;
  1778. case SND_SOC_DAPM_POST_PMD:
  1779. regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH1_CN, 0x01);
  1780. regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH2_CN, 0x01);
  1781. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &commit_val);
  1782. /*TEAR DOWN HPH SEQUENCER*/
  1783. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1784. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
  1785. if (!wcd9378->comp1_enable || !wcd9378->comp2_enable)
  1786. /*PA delay is 24250us*/
  1787. usleep_range(24300, 24310);
  1788. else
  1789. /*COMP delay is 11250us*/
  1790. usleep_range(11300, 11310);
  1791. wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, false);
  1792. break;
  1793. default:
  1794. break;
  1795. };
  1796. return ret;
  1797. }
  1798. static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1799. struct snd_kcontrol *kcontrol,
  1800. int event)
  1801. {
  1802. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1803. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1804. int ear_rx2 = 0;
  1805. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1806. w->name, event);
  1807. ear_rx2 = snd_soc_component_read(component, WCD9378_CDC_AUX_GAIN_CTL) &
  1808. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK;
  1809. switch (event) {
  1810. case SND_SOC_DAPM_PRE_PMU:
  1811. /*SHORT_PROT_EN ENABLE*/
  1812. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1813. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
  1814. if (!ear_rx2) {
  1815. /*RX0 ENABLE*/
  1816. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1817. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1818. wcd9378_sys_usage_auto_udpate(component, RX0_EAR_EN, true);
  1819. if (wcd9378->comp1_enable) {
  1820. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1821. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
  1822. wcd9378_rx_connect_port(component, COMP_L, true);
  1823. }
  1824. wcd9378_rx_connect_port(component, HPH_L, true);
  1825. } else {
  1826. wcd9378_sys_usage_auto_udpate(component, RX2_EAR_EN, true);
  1827. /*FORCE CLASS_AB EN*/
  1828. snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
  1829. WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
  1830. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1831. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1832. if (wcd9378->rx2_clk_mode)
  1833. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1834. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1835. wcd9378_rx_connect_port(component, LO, true);
  1836. }
  1837. break;
  1838. case SND_SOC_DAPM_POST_PMD:
  1839. /*SHORT_PROT_EN DISABLE*/
  1840. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1841. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x00);
  1842. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1843. /*RX0 DISABLE*/
  1844. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1845. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1846. wcd9378_rx_connect_port(component, HPH_L, false);
  1847. if (wcd9378->comp1_enable) {
  1848. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1849. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
  1850. wcd9378_rx_connect_port(component, COMP_L, false);
  1851. }
  1852. wcd9378_sys_usage_auto_udpate(component, RX0_EAR_EN, false);
  1853. } else {
  1854. wcd9378_rx_connect_port(component, LO, false);
  1855. wcd9378_sys_usage_auto_udpate(component, RX2_EAR_EN, false);
  1856. wcd9378_swr_slvdev_datapath_control(wcd9378->dev, RX_PATH, false);
  1857. }
  1858. break;
  1859. };
  1860. return 0;
  1861. }
  1862. static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  1863. struct snd_kcontrol *kcontrol,
  1864. int event)
  1865. {
  1866. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1867. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1868. int aux_rx2 = 0;
  1869. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1870. w->name, event);
  1871. aux_rx2 = snd_soc_component_read(component, WCD9378_CDC_AUX_GAIN_CTL) &
  1872. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK;
  1873. switch (event) {
  1874. case SND_SOC_DAPM_PRE_PMU:
  1875. /*AUXPA SHORT PROT ENABLE*/
  1876. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1877. WCD9378_AUX_AUXPA_AUX_PA_SHORT_PROT_EN_MASK, 0x40);
  1878. if (!aux_rx2) {
  1879. /*RX1 ENABLE*/
  1880. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1881. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1882. wcd9378_sys_usage_auto_udpate(component, RX1_AUX_EN, true);
  1883. wcd9378_rx_connect_port(component, HPH_R, true);
  1884. } else {
  1885. wcd9378_sys_usage_auto_udpate(component, RX2_AUX_EN, true);
  1886. if (wcd9378->rx2_clk_mode)
  1887. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1888. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1889. wcd9378_rx_connect_port(component, LO, true);
  1890. }
  1891. break;
  1892. case SND_SOC_DAPM_POST_PMD:
  1893. /*AUXPA SHORT PROT DISABLE*/
  1894. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1895. WCD9378_AUX_AUXPA_AUX_PA_SHORT_PROT_EN_MASK, 0x00);
  1896. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1897. wcd9378_rx_connect_port(component, HPH_R, false);
  1898. wcd9378_sys_usage_auto_udpate(component, RX1_AUX_EN, false);
  1899. } else {
  1900. wcd9378_rx_connect_port(component, LO, false);
  1901. wcd9378_sys_usage_auto_udpate(component, RX2_AUX_EN, false);
  1902. wcd9378_swr_slvdev_datapath_control(wcd9378->dev, RX_PATH, false);
  1903. }
  1904. break;
  1905. };
  1906. return 0;
  1907. }
  1908. static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
  1909. struct snd_kcontrol *kcontrol, int event)
  1910. {
  1911. struct snd_soc_component *component =
  1912. snd_soc_dapm_to_component(w->dapm);
  1913. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1914. w->name, event);
  1915. switch (event) {
  1916. case SND_SOC_DAPM_PRE_PMU:
  1917. /*TURN ON AMP SEQUENCER*/
  1918. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1919. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
  1920. /*default delay 8550us*/
  1921. usleep_range(8600, 8610);
  1922. /*FU23 UNMUTE*/
  1923. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1924. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1925. break;
  1926. case SND_SOC_DAPM_POST_PMD:
  1927. /*FU23 MUTE*/
  1928. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1929. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
  1930. /*TEAR DOWN AMP SEQUENCER*/
  1931. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1932. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
  1933. /*default delay 1530us*/
  1934. usleep_range(15400, 15410);
  1935. break;
  1936. default:
  1937. break;
  1938. };
  1939. return 0;
  1940. }
  1941. int wcd9378_micbias_control(struct snd_soc_component *component,
  1942. int micb_num, int req, bool is_dapm)
  1943. {
  1944. struct wcd9378_priv *wcd9378 =
  1945. snd_soc_component_get_drvdata(component);
  1946. struct wcd9378_pdata *pdata =
  1947. dev_get_platdata(wcd9378->dev);
  1948. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  1949. int micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
  1950. int pre_off_event = 0, post_off_event = 0;
  1951. int post_on_event = 0, post_dapm_off = 0;
  1952. int post_dapm_on = 0;
  1953. int pull_up_mask = 0, pull_up_en = 0;
  1954. int micb_index = 0, ret = 0;
  1955. switch (micb_num) {
  1956. case MIC_BIAS_1:
  1957. pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
  1958. pull_up_en = 0x01;
  1959. micb_usage = WCD9378_IT11_MICB;
  1960. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  1961. micb_usage_val = mb->micb1_usage_val;
  1962. break;
  1963. case MIC_BIAS_2:
  1964. pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
  1965. pull_up_en = 0x02;
  1966. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  1967. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  1968. micb_usage_val = mb->micb2_usage_val;
  1969. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1970. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1971. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1972. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1973. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1974. break;
  1975. case MIC_BIAS_3:
  1976. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  1977. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  1978. pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
  1979. pull_up_en = 0x04;
  1980. micb_usage_val = mb->micb3_usage_val;
  1981. break;
  1982. default:
  1983. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1984. __func__, micb_num);
  1985. return -EINVAL;
  1986. }
  1987. mutex_lock(&wcd9378->micb_lock);
  1988. micb_index = micb_num - 1;
  1989. switch (req) {
  1990. case MICB_PULLUP_ENABLE:
  1991. wcd9378->pullup_ref[micb_index]++;
  1992. if ((wcd9378->pullup_ref[micb_index] == 1) &&
  1993. (wcd9378->micb_ref[micb_index] == 0)) {
  1994. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1995. pull_up_mask, pull_up_en);
  1996. snd_soc_component_update_bits(component,
  1997. micb_usage, micb_mask, micb_usage_val);
  1998. if (micb_num == MIC_BIAS_2) {
  1999. snd_soc_component_update_bits(component,
  2000. WCD9378_IT31_MICB,
  2001. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2002. micb_usage_val);
  2003. wcd9378->curr_micbias2 = mb->micb2_mv;
  2004. }
  2005. }
  2006. break;
  2007. case MICB_PULLUP_DISABLE:
  2008. if (wcd9378->pullup_ref[micb_index] > 0)
  2009. wcd9378->pullup_ref[micb_index]--;
  2010. if ((wcd9378->pullup_ref[micb_index] == 0) &&
  2011. (wcd9378->micb_ref[micb_index] == 0)) {
  2012. snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
  2013. if (micb_num == MIC_BIAS_2) {
  2014. snd_soc_component_update_bits(component,
  2015. WCD9378_IT31_MICB,
  2016. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2017. 0x01);
  2018. wcd9378->curr_micbias2 = 0;
  2019. }
  2020. }
  2021. break;
  2022. case MICB_ENABLE:
  2023. wcd9378->micb_ref[micb_index]++;
  2024. if (wcd9378->micb_ref[micb_index] == 1) {
  2025. dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
  2026. __func__, micb_usage, micb_usage_val);
  2027. snd_soc_component_update_bits(component,
  2028. micb_usage, micb_mask, micb_usage_val);
  2029. if (micb_num == MIC_BIAS_2) {
  2030. snd_soc_component_update_bits(component,
  2031. WCD9378_IT31_MICB,
  2032. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2033. micb_usage_val);
  2034. wcd9378->curr_micbias2 = mb->micb2_mv;
  2035. }
  2036. if (post_on_event)
  2037. blocking_notifier_call_chain(
  2038. &wcd9378->mbhc->notifier,
  2039. post_on_event,
  2040. &wcd9378->mbhc->wcd_mbhc);
  2041. }
  2042. if (is_dapm && post_dapm_on && wcd9378->mbhc)
  2043. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  2044. post_dapm_on,
  2045. &wcd9378->mbhc->wcd_mbhc);
  2046. break;
  2047. case MICB_DISABLE:
  2048. if (wcd9378->micb_ref[micb_index] > 0)
  2049. wcd9378->micb_ref[micb_index]--;
  2050. if ((wcd9378->micb_ref[micb_index] == 0) &&
  2051. (wcd9378->pullup_ref[micb_index] > 0)) {
  2052. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  2053. pull_up_mask, pull_up_en);
  2054. if (micb_num == MIC_BIAS_2)
  2055. wcd9378->curr_micbias2 = mb->micb2_mv;
  2056. } else if ((wcd9378->micb_ref[micb_index] == 0) &&
  2057. (wcd9378->pullup_ref[micb_index] == 0)) {
  2058. if (pre_off_event && wcd9378->mbhc)
  2059. blocking_notifier_call_chain(
  2060. &wcd9378->mbhc->notifier,
  2061. pre_off_event,
  2062. &wcd9378->mbhc->wcd_mbhc);
  2063. snd_soc_component_update_bits(component, micb_usage,
  2064. micb_mask, 0x00);
  2065. if (micb_num == MIC_BIAS_2) {
  2066. snd_soc_component_update_bits(component,
  2067. WCD9378_IT31_MICB,
  2068. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2069. 0x00);
  2070. wcd9378->curr_micbias2 = 0;
  2071. }
  2072. if (post_off_event && wcd9378->mbhc)
  2073. blocking_notifier_call_chain(
  2074. &wcd9378->mbhc->notifier,
  2075. post_off_event,
  2076. &wcd9378->mbhc->wcd_mbhc);
  2077. }
  2078. if (is_dapm && post_dapm_off && wcd9378->mbhc)
  2079. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  2080. post_dapm_off,
  2081. &wcd9378->mbhc->wcd_mbhc);
  2082. break;
  2083. default:
  2084. dev_err(component->dev, "%s: Invalid req event: %d\n",
  2085. __func__, req);
  2086. return -EINVAL;
  2087. }
  2088. dev_dbg(component->dev,
  2089. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  2090. __func__, micb_num, wcd9378->micb_ref[micb_index],
  2091. wcd9378->pullup_ref[micb_index]);
  2092. mutex_unlock(&wcd9378->micb_lock);
  2093. return ret;
  2094. }
  2095. EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
  2096. static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
  2097. {
  2098. int ret = 0;
  2099. uint8_t devnum = 0;
  2100. int num_retry = NUM_ATTEMPTS;
  2101. do {
  2102. /* retry after 4ms */
  2103. usleep_range(4000, 4010);
  2104. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  2105. } while (ret && --num_retry);
  2106. if (ret)
  2107. dev_err(&swr_dev->dev,
  2108. "%s get devnum %d for dev addr %llx failed\n",
  2109. __func__, devnum, swr_dev->addr);
  2110. swr_dev->dev_num = devnum;
  2111. return 0;
  2112. }
  2113. static bool get_usbc_hs_status(struct snd_soc_component *component,
  2114. struct wcd_mbhc_config *mbhc_cfg)
  2115. {
  2116. if (mbhc_cfg->enable_usbc_analog) {
  2117. if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
  2118. & 0x20))
  2119. return true;
  2120. }
  2121. return false;
  2122. }
  2123. int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
  2124. struct notifier_block *nblock,
  2125. bool enable)
  2126. {
  2127. struct wcd9378_priv *wcd9378_priv = NULL;
  2128. if (component == NULL) {
  2129. pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
  2130. return -EINVAL;
  2131. }
  2132. wcd9378_priv = snd_soc_component_get_drvdata(component);
  2133. wcd9378_priv->notify_swr_dmic = enable;
  2134. if (enable)
  2135. return blocking_notifier_chain_register(&wcd9378_priv->notifier,
  2136. nblock);
  2137. else
  2138. return blocking_notifier_chain_unregister(
  2139. &wcd9378_priv->notifier, nblock);
  2140. }
  2141. EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
  2142. static int wcd9378_event_notify(struct notifier_block *block,
  2143. unsigned long val,
  2144. void *data)
  2145. {
  2146. u16 event = (val & 0xffff);
  2147. int ret = 0;
  2148. struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
  2149. struct snd_soc_component *component = wcd9378->component;
  2150. struct wcd_mbhc *mbhc;
  2151. int rx_clk_type;
  2152. switch (event) {
  2153. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2154. if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
  2155. snd_soc_component_update_bits(component,
  2156. WCD9378_ANA_TX_CH2, 0x40, 0x00);
  2157. set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
  2158. clear_bit(WCD_ADC1, &wcd9378->status_mask);
  2159. }
  2160. if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
  2161. snd_soc_component_update_bits(component,
  2162. WCD9378_ANA_TX_CH2, 0x20, 0x00);
  2163. set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
  2164. clear_bit(WCD_ADC2, &wcd9378->status_mask);
  2165. }
  2166. if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
  2167. snd_soc_component_update_bits(component,
  2168. WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
  2169. set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
  2170. clear_bit(WCD_ADC3, &wcd9378->status_mask);
  2171. }
  2172. break;
  2173. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2174. snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
  2175. 0xC0, 0x00);
  2176. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  2177. 0x80, 0x00);
  2178. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  2179. 0x80, 0x00);
  2180. break;
  2181. case BOLERO_SLV_EVT_SSR_DOWN:
  2182. if (wcd9378->notify_swr_dmic)
  2183. blocking_notifier_call_chain(&wcd9378->notifier,
  2184. WCD9378_EVT_SSR_DOWN,
  2185. NULL);
  2186. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
  2187. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2188. wcd9378->usbc_hs_status = get_usbc_hs_status(component,
  2189. mbhc->mbhc_cfg);
  2190. wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
  2191. wcd9378_reset_low(wcd9378->dev);
  2192. break;
  2193. case BOLERO_SLV_EVT_SSR_UP:
  2194. wcd9378_reset(wcd9378->dev);
  2195. /* allow reset to take effect */
  2196. usleep_range(10000, 10010);
  2197. wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
  2198. wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
  2199. wcd9378->tx_swr_dev->scp1_val = 0;
  2200. wcd9378->tx_swr_dev->scp2_val = 0;
  2201. wcd9378->rx_swr_dev->scp1_val = 0;
  2202. wcd9378->rx_swr_dev->scp2_val = 0;
  2203. wcd9378_init_reg(component);
  2204. regcache_mark_dirty(wcd9378->regmap);
  2205. regcache_sync(wcd9378->regmap);
  2206. /* Initialize MBHC module */
  2207. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2208. ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
  2209. if (ret) {
  2210. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2211. __func__);
  2212. } else {
  2213. wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2214. }
  2215. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
  2216. if (wcd9378->notify_swr_dmic)
  2217. blocking_notifier_call_chain(&wcd9378->notifier,
  2218. WCD9378_EVT_SSR_UP,
  2219. NULL);
  2220. if (wcd9378->usbc_hs_status)
  2221. mdelay(500);
  2222. break;
  2223. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2224. snd_soc_component_update_bits(component,
  2225. WCD9378_TOP_CLK_CFG, 0x06,
  2226. ((val >> 0x10) << 0x01));
  2227. rx_clk_type = (val >> 0x10);
  2228. switch (rx_clk_type) {
  2229. case RX_CLK_12P288MHZ:
  2230. wcd9378->rx_swrclk = SWR_BASECLK_24P576MHZ;
  2231. wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
  2232. break;
  2233. case RX_CLK_11P2896MHZ:
  2234. wcd9378->rx_swrclk = SWR_BASECLK_22P5792MHZ;
  2235. wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
  2236. break;
  2237. default:
  2238. wcd9378->rx_swrclk = SWR_BASECLK_19P2MHZ;
  2239. wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
  2240. break;
  2241. }
  2242. dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
  2243. __func__, wcd9378->rx_swrclk, wcd9378->rx_clkscale);
  2244. break;
  2245. default:
  2246. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2247. break;
  2248. }
  2249. return 0;
  2250. }
  2251. static int wcd9378_wakeup(void *handle, bool enable)
  2252. {
  2253. struct wcd9378_priv *priv;
  2254. int ret = 0;
  2255. if (!handle) {
  2256. pr_err("%s: NULL handle\n", __func__);
  2257. return -EINVAL;
  2258. }
  2259. priv = (struct wcd9378_priv *)handle;
  2260. if (!priv->tx_swr_dev) {
  2261. pr_err("%s: tx swr dev is NULL\n", __func__);
  2262. return -EINVAL;
  2263. }
  2264. mutex_lock(&priv->wakeup_lock);
  2265. if (enable)
  2266. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2267. else
  2268. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2269. mutex_unlock(&priv->wakeup_lock);
  2270. return ret;
  2271. }
  2272. static inline int wcd9378_tx_path_get(const char *wname,
  2273. unsigned int *path_num)
  2274. {
  2275. int ret = 0;
  2276. char *widget_name = NULL;
  2277. char *w_name = NULL;
  2278. char *path_num_char = NULL;
  2279. char *path_name = NULL;
  2280. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2281. if (!widget_name)
  2282. return -EINVAL;
  2283. w_name = widget_name;
  2284. path_name = strsep(&widget_name, " ");
  2285. if (!path_name) {
  2286. pr_err("%s: Invalid widget name = %s\n",
  2287. __func__, widget_name);
  2288. ret = -EINVAL;
  2289. goto err;
  2290. }
  2291. path_num_char = strpbrk(path_name, "0123");
  2292. if (!path_num_char) {
  2293. pr_err("%s: tx path index not found\n",
  2294. __func__);
  2295. ret = -EINVAL;
  2296. goto err;
  2297. }
  2298. ret = kstrtouint(path_num_char, 10, path_num);
  2299. if (ret < 0)
  2300. pr_err("%s: Invalid tx path = %s\n",
  2301. __func__, w_name);
  2302. err:
  2303. kfree(w_name);
  2304. return ret;
  2305. }
  2306. static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
  2307. struct snd_ctl_elem_value *ucontrol)
  2308. {
  2309. struct snd_soc_component *component =
  2310. snd_soc_kcontrol_component(kcontrol);
  2311. struct wcd9378_priv *wcd9378 = NULL;
  2312. int ret = 0;
  2313. unsigned int path = 0;
  2314. if (!component)
  2315. return -EINVAL;
  2316. wcd9378 = snd_soc_component_get_drvdata(component);
  2317. if (!wcd9378)
  2318. return -EINVAL;
  2319. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2320. if (ret < 0)
  2321. return ret;
  2322. ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
  2323. return 0;
  2324. }
  2325. static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
  2326. struct snd_ctl_elem_value *ucontrol)
  2327. {
  2328. struct snd_soc_component *component =
  2329. snd_soc_kcontrol_component(kcontrol);
  2330. struct wcd9378_priv *wcd9378 = NULL;
  2331. u32 mode_val;
  2332. unsigned int path = 0;
  2333. int ret = 0;
  2334. if (!component)
  2335. return -EINVAL;
  2336. wcd9378 = snd_soc_component_get_drvdata(component);
  2337. if (!wcd9378)
  2338. return -EINVAL;
  2339. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2340. if (ret)
  2341. return ret;
  2342. mode_val = ucontrol->value.enumerated.item[0];
  2343. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2344. wcd9378->tx_mode[path] = mode_val;
  2345. return 0;
  2346. }
  2347. static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
  2348. struct snd_ctl_elem_value *ucontrol)
  2349. {
  2350. struct snd_soc_component *component =
  2351. snd_soc_kcontrol_component(kcontrol);
  2352. u32 loopback_mode = 0;
  2353. if (!component)
  2354. return -EINVAL;
  2355. loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
  2356. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
  2357. ucontrol->value.integer.value[0] = loopback_mode;
  2358. return 0;
  2359. }
  2360. static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
  2361. struct snd_ctl_elem_value *ucontrol)
  2362. {
  2363. struct snd_soc_component *component =
  2364. snd_soc_kcontrol_component(kcontrol);
  2365. u32 loopback_mode = 0;
  2366. if (!component)
  2367. return -EINVAL;
  2368. loopback_mode = ucontrol->value.enumerated.item[0];
  2369. snd_soc_component_update_bits(component,
  2370. WCD9378_LOOP_BACK_MODE,
  2371. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
  2372. loopback_mode);
  2373. dev_dbg(component->dev, "%s: loopback_mode: %d\n",
  2374. __func__, loopback_mode);
  2375. return 0;
  2376. }
  2377. static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
  2378. struct snd_ctl_elem_value *ucontrol)
  2379. {
  2380. struct snd_soc_component *component =
  2381. snd_soc_kcontrol_component(kcontrol);
  2382. u32 aux_dsm_in = 0;
  2383. if (!component)
  2384. return -EINVAL;
  2385. aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2386. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
  2387. ucontrol->value.integer.value[0] = aux_dsm_in;
  2388. return 0;
  2389. }
  2390. static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
  2391. struct snd_ctl_elem_value *ucontrol)
  2392. {
  2393. struct snd_soc_component *component =
  2394. snd_soc_kcontrol_component(kcontrol);
  2395. u32 aux_dsm_in = 0;
  2396. if (!component)
  2397. return -EINVAL;
  2398. aux_dsm_in = ucontrol->value.enumerated.item[0];
  2399. snd_soc_component_update_bits(component,
  2400. WCD9378_LB_IN_SEL_CTL,
  2401. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
  2402. aux_dsm_in);
  2403. dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
  2404. __func__, aux_dsm_in);
  2405. return 0;
  2406. }
  2407. static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
  2408. struct snd_ctl_elem_value *ucontrol)
  2409. {
  2410. struct snd_soc_component *component =
  2411. snd_soc_kcontrol_component(kcontrol);
  2412. u32 hph_dsm_in = 0;
  2413. if (!component)
  2414. return -EINVAL;
  2415. hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2416. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
  2417. ucontrol->value.integer.value[0] = hph_dsm_in;
  2418. return 0;
  2419. }
  2420. static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
  2421. struct snd_ctl_elem_value *ucontrol)
  2422. {
  2423. struct snd_soc_component *component =
  2424. snd_soc_kcontrol_component(kcontrol);
  2425. u32 hph_dsm_in = 0;
  2426. if (!component)
  2427. return -EINVAL;
  2428. hph_dsm_in = ucontrol->value.enumerated.item[0];
  2429. snd_soc_component_update_bits(component,
  2430. WCD9378_LB_IN_SEL_CTL,
  2431. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
  2432. hph_dsm_in);
  2433. dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
  2434. __func__, hph_dsm_in);
  2435. return 0;
  2436. }
  2437. static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
  2438. struct snd_ctl_elem_value *ucontrol)
  2439. {
  2440. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2441. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2442. u16 offset = ucontrol->value.enumerated.item[0];
  2443. u32 temp = 0;
  2444. temp = 0x00 - offset * 0x180;
  2445. wcd9378->hph_gain = (u16)(temp & 0xffff);
  2446. dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
  2447. return 0;
  2448. }
  2449. static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
  2450. struct snd_ctl_elem_value *ucontrol)
  2451. {
  2452. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2453. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2454. u32 temp = 0;
  2455. u16 offset = 0;
  2456. temp = 0 - wcd9378->hph_gain;
  2457. offset = (u16)(temp & 0xffff);
  2458. offset /= 0x180;
  2459. ucontrol->value.enumerated.item[0] = offset;
  2460. dev_dbg(component->dev, "%s: offset is 0x%0x\n", __func__, offset);
  2461. return 0;
  2462. }
  2463. static int wcd9378_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2464. struct snd_ctl_elem_value *ucontrol)
  2465. {
  2466. struct snd_soc_component *component =
  2467. snd_soc_kcontrol_component(kcontrol);
  2468. int ear_gain = 0;
  2469. if (component == NULL)
  2470. return -EINVAL;
  2471. ear_gain =
  2472. snd_soc_component_read(component, WCD9378_ANA_EAR_COMPANDER_CTL) &
  2473. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK;
  2474. ucontrol->value.enumerated.item[0] = ear_gain;
  2475. dev_dbg(component->dev, "%s: get ear_gain val: 0x%x\n",
  2476. __func__, ear_gain);
  2477. return 0;
  2478. }
  2479. static int wcd9378_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2480. struct snd_ctl_elem_value *ucontrol)
  2481. {
  2482. struct snd_soc_component *component =
  2483. snd_soc_kcontrol_component(kcontrol);
  2484. int ear_gain = 0;
  2485. if (component == NULL)
  2486. return -EINVAL;
  2487. if (ucontrol->value.integer.value[0] < 0 ||
  2488. ucontrol->value.integer.value[0] > 0x10) {
  2489. dev_err(component->dev, "%s: Unsupported gain val %ld\n",
  2490. __func__, ucontrol->value.integer.value[0]);
  2491. return -EINVAL;
  2492. }
  2493. ear_gain = ucontrol->value.integer.value[0];
  2494. snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
  2495. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
  2496. ear_gain);
  2497. dev_dbg(component->dev, "%s: set ear_gain val: 0x%x\n",
  2498. __func__, ear_gain);
  2499. return 0;
  2500. }
  2501. static int wcd9378_aux_pa_gain_get(struct snd_kcontrol *kcontrol,
  2502. struct snd_ctl_elem_value *ucontrol)
  2503. {
  2504. struct snd_soc_component *component =
  2505. snd_soc_kcontrol_component(kcontrol);
  2506. int aux_gain = 0;
  2507. if (component == NULL)
  2508. return -EINVAL;
  2509. aux_gain = snd_soc_component_read(component, WCD9378_AUX_INT_MISC) &
  2510. WCD9378_AUX_INT_MISC_PA_GAIN_MASK;
  2511. ucontrol->value.enumerated.item[0] = aux_gain;
  2512. dev_dbg(component->dev, "%s: get aux_gain val: 0x%x\n",
  2513. __func__, aux_gain);
  2514. return 0;
  2515. }
  2516. static int wcd9378_aux_pa_gain_put(struct snd_kcontrol *kcontrol,
  2517. struct snd_ctl_elem_value *ucontrol)
  2518. {
  2519. struct snd_soc_component *component =
  2520. snd_soc_kcontrol_component(kcontrol);
  2521. int aux_gain = 0;
  2522. if (component == NULL)
  2523. return -EINVAL;
  2524. if (ucontrol->value.integer.value[0] < 0 ||
  2525. ucontrol->value.integer.value[0] > 0x8) {
  2526. dev_err(component->dev, "%s: Unsupported gain val %ld\n",
  2527. __func__, ucontrol->value.integer.value[0]);
  2528. return -EINVAL;
  2529. }
  2530. aux_gain = ucontrol->value.integer.value[0];
  2531. snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
  2532. WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
  2533. aux_gain);
  2534. dev_dbg(component->dev, "%s: set aux_gain val: 0x%x\n",
  2535. __func__, aux_gain);
  2536. return 0;
  2537. }
  2538. static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
  2539. struct snd_ctl_elem_value *ucontrol)
  2540. {
  2541. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2542. struct wcd9378_priv *wcd9378 =
  2543. snd_soc_component_get_drvdata(component);
  2544. if (ucontrol->value.enumerated.item[0])
  2545. wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
  2546. else
  2547. wcd9378->rx2_clk_mode = RX2_HP_MODE;
  2548. return 1;
  2549. }
  2550. static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2551. struct snd_ctl_elem_value *ucontrol)
  2552. {
  2553. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2554. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2555. ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
  2556. return 0;
  2557. }
  2558. static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2559. struct snd_ctl_elem_value *ucontrol)
  2560. {
  2561. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2562. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2563. if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
  2564. return 0;
  2565. wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
  2566. return 1;
  2567. }
  2568. /* wcd9378_codec_get_dev_num - returns swr device number
  2569. * @component: Codec instance
  2570. *
  2571. * Return: swr device number on success or negative error
  2572. * code on failure.
  2573. */
  2574. int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
  2575. {
  2576. struct wcd9378_priv *wcd9378;
  2577. if (!component)
  2578. return -EINVAL;
  2579. wcd9378 = snd_soc_component_get_drvdata(component);
  2580. if (!wcd9378 || !wcd9378->rx_swr_dev) {
  2581. pr_err("%s: wcd9378 component is NULL\n", __func__);
  2582. return -EINVAL;
  2583. }
  2584. return wcd9378->rx_swr_dev->dev_num;
  2585. }
  2586. EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
  2587. static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
  2588. struct snd_ctl_elem_value *ucontrol)
  2589. {
  2590. struct snd_soc_component *component =
  2591. snd_soc_kcontrol_component(kcontrol);
  2592. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2593. bool hphr;
  2594. struct soc_multi_mixer_control *mc;
  2595. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2596. hphr = mc->shift;
  2597. ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
  2598. wcd9378->comp1_enable;
  2599. return 0;
  2600. }
  2601. static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
  2602. struct snd_ctl_elem_value *ucontrol)
  2603. {
  2604. struct snd_soc_component *component =
  2605. snd_soc_kcontrol_component(kcontrol);
  2606. struct wcd9378_priv *wcd9378 =
  2607. snd_soc_component_get_drvdata(component);
  2608. int value = ucontrol->value.integer.value[0];
  2609. bool hphr;
  2610. struct soc_multi_mixer_control *mc;
  2611. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2612. hphr = mc->shift;
  2613. if (hphr)
  2614. wcd9378->comp2_enable = value;
  2615. else
  2616. wcd9378->comp1_enable = value;
  2617. dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
  2618. return 0;
  2619. }
  2620. static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2621. struct snd_kcontrol *kcontrol,
  2622. int event)
  2623. {
  2624. struct snd_soc_component *component =
  2625. snd_soc_dapm_to_component(w->dapm);
  2626. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2627. struct wcd9378_pdata *pdata = NULL;
  2628. int ret = 0;
  2629. pdata = dev_get_platdata(wcd9378->dev);
  2630. if (!pdata) {
  2631. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2632. return -EINVAL;
  2633. }
  2634. if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
  2635. wcd9378->supplies,
  2636. pdata->regulator,
  2637. pdata->num_supplies,
  2638. "cdc-vdd-buck"))
  2639. return 0;
  2640. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2641. w->name, event);
  2642. switch (event) {
  2643. case SND_SOC_DAPM_PRE_PMU:
  2644. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  2645. dev_dbg(component->dev,
  2646. "%s: buck already in enabled state\n",
  2647. __func__);
  2648. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2649. return 0;
  2650. }
  2651. ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
  2652. wcd9378->supplies,
  2653. pdata->regulator,
  2654. pdata->num_supplies,
  2655. "cdc-vdd-buck");
  2656. if (ret == -EINVAL) {
  2657. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2658. __func__);
  2659. return ret;
  2660. }
  2661. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2662. /*
  2663. * 200us sleep is required after LDO is enabled as per
  2664. * HW requirement
  2665. */
  2666. usleep_range(200, 250);
  2667. break;
  2668. case SND_SOC_DAPM_POST_PMD:
  2669. set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2670. break;
  2671. }
  2672. return 0;
  2673. }
  2674. static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2675. {
  2676. u8 ch_type = 0;
  2677. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2678. ch_type = ADC1;
  2679. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2680. ch_type = ADC2;
  2681. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2682. ch_type = ADC3;
  2683. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2684. ch_type = ADC4;
  2685. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2686. ch_type = DMIC0;
  2687. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2688. ch_type = DMIC1;
  2689. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2690. ch_type = MBHC;
  2691. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2692. ch_type = DMIC2;
  2693. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2694. ch_type = DMIC3;
  2695. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2696. ch_type = DMIC4;
  2697. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2698. ch_type = DMIC5;
  2699. else
  2700. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2701. if (ch_type)
  2702. *ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
  2703. else
  2704. *ch_idx = -EINVAL;
  2705. }
  2706. static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2707. struct snd_ctl_elem_value *ucontrol)
  2708. {
  2709. struct snd_soc_component *component =
  2710. snd_soc_kcontrol_component(kcontrol);
  2711. struct wcd9378_priv *wcd9378 = NULL;
  2712. int slave_ch_idx = -EINVAL;
  2713. if (component == NULL)
  2714. return -EINVAL;
  2715. wcd9378 = snd_soc_component_get_drvdata(component);
  2716. if (wcd9378 == NULL)
  2717. return -EINVAL;
  2718. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2719. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2720. return -EINVAL;
  2721. ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
  2722. wcd9378->tx_master_ch_map[slave_ch_idx]);
  2723. return 0;
  2724. }
  2725. static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2726. struct snd_ctl_elem_value *ucontrol)
  2727. {
  2728. struct snd_soc_component *component =
  2729. snd_soc_kcontrol_component(kcontrol);
  2730. struct wcd9378_priv *wcd9378 = NULL;
  2731. int slave_ch_idx = -EINVAL, idx = 0;
  2732. if (component == NULL)
  2733. return -EINVAL;
  2734. wcd9378 = snd_soc_component_get_drvdata(component);
  2735. if (wcd9378 == NULL)
  2736. return -EINVAL;
  2737. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2738. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2739. return -EINVAL;
  2740. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2741. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2742. __func__, ucontrol->value.enumerated.item[0]);
  2743. idx = ucontrol->value.enumerated.item[0];
  2744. if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
  2745. return -EINVAL;
  2746. wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
  2747. return 0;
  2748. }
  2749. static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
  2750. struct snd_ctl_elem_value *ucontrol)
  2751. {
  2752. struct snd_soc_component *component =
  2753. snd_soc_kcontrol_component(kcontrol);
  2754. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2755. ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
  2756. return 0;
  2757. }
  2758. static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
  2759. struct snd_ctl_elem_value *ucontrol)
  2760. {
  2761. struct snd_soc_component *component =
  2762. snd_soc_kcontrol_component(kcontrol);
  2763. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2764. wcd9378->bcs_dis = ucontrol->value.integer.value[0];
  2765. return 0;
  2766. }
  2767. static const char * const loopback_mode_text[] = {
  2768. "NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
  2769. };
  2770. static const struct soc_enum loopback_mode_enum =
  2771. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
  2772. loopback_mode_text);
  2773. static const char * const aux_dsm_text[] = {
  2774. "TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
  2775. };
  2776. static const struct soc_enum aux_dsm_enum =
  2777. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
  2778. aux_dsm_text);
  2779. static const char * const hph_dsm_text[] = {
  2780. "HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
  2781. };
  2782. static const struct soc_enum hph_dsm_enum =
  2783. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
  2784. hph_dsm_text);
  2785. static const char * const tx_mode_mux_text[] = {
  2786. "ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
  2787. };
  2788. static const struct soc_enum tx_mode_mux_enum =
  2789. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2790. tx_mode_mux_text);
  2791. static const char * const rx2_mode_text[] = {
  2792. "HP", "NORMAL",
  2793. };
  2794. static const struct soc_enum rx2_mode_enum =
  2795. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
  2796. rx2_mode_text);
  2797. static const char * const rx_hph_mode_mux_text[] = {
  2798. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2799. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2800. };
  2801. static const struct soc_enum rx_hph_mode_mux_enum =
  2802. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2803. rx_hph_mode_mux_text);
  2804. static const char * const ear_pa_gain_text[] = {
  2805. "GAIN_6DB", "GAIN_4P5DB", "GAIN_3DB", "GAIN_1P5DB", "GAIN_0DB",
  2806. "GAIN_M1P5DB", "GAIN_M3DB", "GAIN_M4P5DB", "GAIN_M6DB",
  2807. "GAIN_M7P5DB", "GAIN_M9DB", "GAIN_M10P5DB", "GAIN_M12DB",
  2808. "GAIN_M13P5DB", "GAIN_M15DB", "GAIN_M16P5DB", "GAIN_M18DB",
  2809. };
  2810. static const struct soc_enum ear_pa_gain_enum =
  2811. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ear_pa_gain_text),
  2812. ear_pa_gain_text);
  2813. static const char * const aux_pa_gain_text[] = {
  2814. "GAIN_6DB", "GAIN_4P5DB", "GAIN_3DB", "GAIN_1P5DB", "GAIN_0DB",
  2815. "GAIN_M1P5DB", "GAIN_M3DB", "GAIN_M4P5DB", "GAIN_M6DB",
  2816. };
  2817. static const struct soc_enum aux_pa_gain_enum =
  2818. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_pa_gain_text),
  2819. aux_pa_gain_text);
  2820. const char * const tx_master_ch_text[] = {
  2821. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2822. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2823. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2824. "SWRM_PCM_IN",
  2825. };
  2826. const struct soc_enum tx_master_ch_enum =
  2827. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2828. tx_master_ch_text);
  2829. static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
  2830. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2831. wcd9378_get_compander, wcd9378_set_compander),
  2832. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2833. wcd9378_get_compander, wcd9378_set_compander),
  2834. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2835. wcd9378_bcs_get, wcd9378_bcs_put),
  2836. SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
  2837. wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
  2838. SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
  2839. wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
  2840. SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
  2841. wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
  2842. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2843. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2844. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2845. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2846. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2847. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2848. SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
  2849. NULL, wcd9378_rx2_mode_put),
  2850. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2851. wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
  2852. SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
  2853. wcd9378_hph_get_gain, wcd9378_hph_put_gain),
  2854. SOC_ENUM_EXT("EAR_PA Gain", ear_pa_gain_enum,
  2855. wcd9378_ear_pa_gain_get, wcd9378_ear_pa_gain_put),
  2856. SOC_ENUM_EXT("AUX_PA Gain", aux_pa_gain_enum,
  2857. wcd9378_aux_pa_gain_get, wcd9378_aux_pa_gain_put),
  2858. SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
  2859. analog_gain),
  2860. SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
  2861. analog_gain),
  2862. SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
  2863. analog_gain),
  2864. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2865. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2866. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2867. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2868. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2869. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2870. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2871. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2872. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2873. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2874. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2875. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2876. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2877. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2878. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2879. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2880. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2881. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2882. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2883. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2884. };
  2885. static const struct snd_kcontrol_new amic1_switch[] = {
  2886. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2887. };
  2888. static const struct snd_kcontrol_new amic2_switch[] = {
  2889. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2890. };
  2891. static const struct snd_kcontrol_new amic3_switch[] = {
  2892. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2893. };
  2894. static const struct snd_kcontrol_new amic4_switch[] = {
  2895. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2896. };
  2897. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2898. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2899. };
  2900. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2901. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2902. };
  2903. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2904. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2905. };
  2906. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2907. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2908. };
  2909. static const struct snd_kcontrol_new dmic1_switch[] = {
  2910. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2911. };
  2912. static const struct snd_kcontrol_new dmic2_switch[] = {
  2913. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2914. };
  2915. static const struct snd_kcontrol_new dmic3_switch[] = {
  2916. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2917. };
  2918. static const struct snd_kcontrol_new dmic4_switch[] = {
  2919. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2920. };
  2921. static const struct snd_kcontrol_new dmic5_switch[] = {
  2922. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2923. };
  2924. static const struct snd_kcontrol_new dmic6_switch[] = {
  2925. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2926. };
  2927. static const char * const adc1_mux_text[] = {
  2928. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
  2929. };
  2930. static const char * const adc2_mux_text[] = {
  2931. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
  2932. };
  2933. static const char * const adc3_mux_text[] = {
  2934. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4"
  2935. };
  2936. static const char * const ear_mux_text[] = {
  2937. "RX0", "RX2"
  2938. };
  2939. static const char * const aux_mux_text[] = {
  2940. "RX1", "RX2"
  2941. };
  2942. static const struct soc_enum adc1_enum =
  2943. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2944. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
  2945. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  2946. static const struct soc_enum adc2_enum =
  2947. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2948. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
  2949. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2950. static const struct soc_enum adc3_enum =
  2951. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
  2952. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
  2953. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2954. static const struct soc_enum ear_enum =
  2955. SOC_ENUM_SINGLE(WCD9378_CDC_AUX_GAIN_CTL,
  2956. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT,
  2957. ARRAY_SIZE(ear_mux_text), ear_mux_text);
  2958. static const struct soc_enum aux_enum =
  2959. SOC_ENUM_SINGLE(WCD9378_CDC_AUX_GAIN_CTL,
  2960. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT,
  2961. ARRAY_SIZE(aux_mux_text), aux_mux_text);
  2962. static const struct snd_kcontrol_new tx_adc1_mux =
  2963. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  2964. static const struct snd_kcontrol_new tx_adc2_mux =
  2965. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2966. static const struct snd_kcontrol_new tx_adc3_mux =
  2967. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2968. static const struct snd_kcontrol_new ear_mux =
  2969. SOC_DAPM_ENUM("EAR Mux", ear_enum);
  2970. static const struct snd_kcontrol_new aux_mux =
  2971. SOC_DAPM_ENUM("AUX Mux", aux_enum);
  2972. static const struct snd_kcontrol_new dac1_switch[] = {
  2973. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2974. };
  2975. static const struct snd_kcontrol_new dac2_switch[] = {
  2976. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2977. };
  2978. static const struct snd_kcontrol_new ear_mixer_switch[] = {
  2979. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2980. };
  2981. static const struct snd_kcontrol_new aux_mixer_switch[] = {
  2982. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2983. };
  2984. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2985. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2986. };
  2987. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2988. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2989. };
  2990. static const struct snd_kcontrol_new rx0_switch[] = {
  2991. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2992. };
  2993. static const struct snd_kcontrol_new rx1_switch[] = {
  2994. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2995. };
  2996. static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
  2997. /*input widgets*/
  2998. SND_SOC_DAPM_INPUT("AMIC1"),
  2999. SND_SOC_DAPM_INPUT("AMIC2"),
  3000. SND_SOC_DAPM_INPUT("AMIC3"),
  3001. SND_SOC_DAPM_INPUT("AMIC4"),
  3002. SND_SOC_DAPM_INPUT("VA AMIC1"),
  3003. SND_SOC_DAPM_INPUT("VA AMIC2"),
  3004. SND_SOC_DAPM_INPUT("VA AMIC3"),
  3005. SND_SOC_DAPM_INPUT("VA AMIC4"),
  3006. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  3007. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  3008. SND_SOC_DAPM_INPUT("IN3_AUX"),
  3009. /*tx widgets*/
  3010. SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
  3011. NULL, 0, wcd9378_tx_sequencer_enable,
  3012. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3013. SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
  3014. NULL, 0, wcd9378_tx_sequencer_enable,
  3015. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3016. SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
  3017. NULL, 0, wcd9378_tx_sequencer_enable,
  3018. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3019. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  3020. &tx_adc1_mux),
  3021. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3022. &tx_adc2_mux),
  3023. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3024. &tx_adc3_mux),
  3025. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3026. wcd9378_codec_enable_dmic,
  3027. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3028. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3029. wcd9378_codec_enable_dmic,
  3030. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3031. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3032. wcd9378_codec_enable_dmic,
  3033. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3034. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3035. wcd9378_codec_enable_dmic,
  3036. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3037. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3038. wcd9378_codec_enable_dmic,
  3039. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3040. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3041. wcd9378_codec_enable_dmic,
  3042. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3043. /*rx widgets*/
  3044. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3045. wcd9378_codec_hphl_dac_event,
  3046. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3047. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3048. wcd9378_codec_hphr_dac_event,
  3049. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3050. SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
  3051. wcd9378_hph_sequencer_enable,
  3052. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3053. SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3054. wcd9378_codec_enable_hphl_pa,
  3055. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3056. SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3057. wcd9378_codec_enable_hphr_pa,
  3058. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3059. SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
  3060. NULL, 0, wcd9378_sa_sequencer_enable,
  3061. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3062. SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  3063. wcd9378_codec_ear_dac_event,
  3064. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3065. SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  3066. wcd9378_codec_aux_dac_event,
  3067. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3068. SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3069. wcd9378_codec_enable_ear_pa,
  3070. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3071. SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3072. wcd9378_codec_enable_aux_pa,
  3073. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3074. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3075. wcd9378_codec_enable_vdd_buck,
  3076. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3077. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3078. wcd9378_enable_clsh,
  3079. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3080. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3081. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3082. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3083. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3084. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3085. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3086. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3087. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3088. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3089. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3090. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3091. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3092. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3093. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3094. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3095. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3096. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3097. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3098. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3099. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3100. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3101. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3102. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3103. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3104. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3105. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3106. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3107. SND_SOC_DAPM_POST_PMD),
  3108. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3109. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3110. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3111. SND_SOC_DAPM_POST_PMD),
  3112. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3113. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3114. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3115. SND_SOC_DAPM_POST_PMD),
  3116. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3117. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3118. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3119. SND_SOC_DAPM_POST_PMD),
  3120. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3121. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3122. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3123. SND_SOC_DAPM_POST_PMD),
  3124. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3125. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3126. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3127. SND_SOC_DAPM_POST_PMD),
  3128. /* micbias widgets*/
  3129. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3130. wcd9378_codec_enable_micbias,
  3131. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3132. SND_SOC_DAPM_POST_PMD),
  3133. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3134. wcd9378_codec_enable_micbias,
  3135. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3136. SND_SOC_DAPM_POST_PMD),
  3137. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3138. wcd9378_codec_enable_micbias,
  3139. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3140. SND_SOC_DAPM_POST_PMD),
  3141. /* micbias pull up widgets*/
  3142. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3143. wcd9378_codec_enable_micbias_pullup,
  3144. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3145. SND_SOC_DAPM_POST_PMD),
  3146. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3147. wcd9378_codec_enable_micbias_pullup,
  3148. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3149. SND_SOC_DAPM_POST_PMD),
  3150. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3151. wcd9378_codec_enable_micbias_pullup,
  3152. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3153. SND_SOC_DAPM_POST_PMD),
  3154. /* rx mixer widgets*/
  3155. SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
  3156. SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
  3157. SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
  3158. ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
  3159. SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
  3160. aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
  3161. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
  3162. dac1_switch, ARRAY_SIZE(dac1_switch)),
  3163. SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
  3164. dac2_switch, ARRAY_SIZE(dac2_switch)),
  3165. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3166. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3167. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3168. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3169. /*output widgets tx*/
  3170. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  3171. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  3172. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  3173. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  3174. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  3175. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  3176. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  3177. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  3178. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  3179. /*output widgets rx*/
  3180. SND_SOC_DAPM_OUTPUT("EAR"),
  3181. SND_SOC_DAPM_OUTPUT("AUX"),
  3182. SND_SOC_DAPM_OUTPUT("HPHL"),
  3183. SND_SOC_DAPM_OUTPUT("HPHR"),
  3184. };
  3185. static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
  3186. /*ADC-1 (channel-1)*/
  3187. {"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
  3188. {"TX0 SEQUENCER", NULL, "ADC1 MUX"},
  3189. {"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
  3190. {"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
  3191. {"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
  3192. {"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
  3193. /*ADC-2 (channel-2)*/
  3194. {"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
  3195. {"TX1 SEQUENCER", NULL, "ADC2 MUX"},
  3196. {"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
  3197. {"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
  3198. {"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
  3199. {"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
  3200. /*ADC-3 (channel-3)*/
  3201. {"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
  3202. {"TX2 SEQUENCER", NULL, "ADC3 MUX"},
  3203. {"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
  3204. {"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
  3205. {"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
  3206. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3207. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3208. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3209. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3210. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3211. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3212. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3213. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3214. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3215. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3216. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3217. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3218. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  3219. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3220. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  3221. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3222. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  3223. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3224. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  3225. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3226. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  3227. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3228. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  3229. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3230. /*Headphone playback*/
  3231. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3232. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3233. {"HPH SEQUENCER", NULL, "IN1_HPHL"},
  3234. {"RDAC1", NULL, "HPH SEQUENCER"},
  3235. {"HPHL_RDAC", "Switch", "RDAC1"},
  3236. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3237. {"HPHL", NULL, "HPHL PGA"},
  3238. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3239. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3240. {"HPH SEQUENCER", NULL, "IN2_HPHR"},
  3241. {"RDAC2", NULL, "HPH SEQUENCER"},
  3242. {"HPHR_RDAC", "Switch", "RDAC2"},
  3243. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3244. {"HPHR", NULL, "HPHR PGA"},
  3245. /*Amplier playback*/
  3246. {"IN3_AUX", NULL, "VDD_BUCK"},
  3247. {"EAR_MUX", "RX0", "IN1_HPHL"},
  3248. {"EAR_MUX", "RX2", "IN3_AUX"},
  3249. {"DAC1", "Switch", "EAR_MUX"},
  3250. {"EAR_RDAC", NULL, "DAC1"},
  3251. {"SA SEQUENCER", NULL, "EAR_RDAC"},
  3252. {"EAR_MIXER", "Switch", "SA SEQUENCER"},
  3253. {"EAR PGA", NULL, "EAR_MIXER"},
  3254. {"EAR", NULL, "EAR PGA"},
  3255. {"AUX_MUX", "RX1", "IN2_HPHR"},
  3256. {"AUX_MUX", "RX2", "IN3_AUX"},
  3257. {"DAC2", "Switch", "AUX_MUX"},
  3258. {"AUX_RDAC", NULL, "DAC2"},
  3259. {"SA SEQUENCER", NULL, "AUX_RDAC"},
  3260. {"AUX_MIXER", "Switch", "SA SEQUENCER",},
  3261. {"AUX PGA", NULL, "AUX_MIXER"},
  3262. {"AUX", NULL, "AUX PGA"},
  3263. };
  3264. static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
  3265. void *file_private_data,
  3266. struct file *file,
  3267. char __user *buf, size_t count,
  3268. loff_t pos)
  3269. {
  3270. struct wcd9378_priv *priv;
  3271. char buffer[WCD9378_VERSION_ENTRY_SIZE];
  3272. int len = 0;
  3273. priv = (struct wcd9378_priv *) entry->private_data;
  3274. if (!priv) {
  3275. pr_err("%s: wcd9378 priv is null\n", __func__);
  3276. return -EINVAL;
  3277. }
  3278. switch (priv->version) {
  3279. case WCD9378_VERSION_1_0:
  3280. len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
  3281. break;
  3282. default:
  3283. len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3284. }
  3285. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3286. }
  3287. static struct snd_info_entry_ops wcd9378_info_ops = {
  3288. .read = wcd9378_version_read,
  3289. };
  3290. /*
  3291. * wcd9378_info_create_codec_entry - creates wcd9378 module
  3292. * @codec_root: The parent directory
  3293. * @component: component instance
  3294. *
  3295. * Creates wcd9378 module, version entry under the given
  3296. * parent directory.
  3297. *
  3298. * Return: 0 on success or negative error code on failure.
  3299. */
  3300. int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
  3301. struct snd_soc_component *component)
  3302. {
  3303. struct snd_info_entry *version_entry;
  3304. struct wcd9378_priv *priv;
  3305. struct snd_soc_card *card;
  3306. if (!codec_root || !component)
  3307. return -EINVAL;
  3308. priv = snd_soc_component_get_drvdata(component);
  3309. if (priv->entry) {
  3310. dev_dbg(priv->dev,
  3311. "%s:wcd9378 module already created\n", __func__);
  3312. return 0;
  3313. }
  3314. card = component->card;
  3315. priv->entry = snd_info_create_module_entry(codec_root->module,
  3316. "wcd9378", codec_root);
  3317. if (!priv->entry) {
  3318. dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
  3319. __func__);
  3320. return -ENOMEM;
  3321. }
  3322. priv->entry->mode = S_IFDIR | 0555;
  3323. if (snd_info_register(priv->entry) < 0) {
  3324. snd_info_free_entry(priv->entry);
  3325. return -ENOMEM;
  3326. }
  3327. version_entry = snd_info_create_card_entry(card->snd_card,
  3328. "version",
  3329. priv->entry);
  3330. if (!version_entry) {
  3331. dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
  3332. __func__);
  3333. snd_info_free_entry(priv->entry);
  3334. return -ENOMEM;
  3335. }
  3336. version_entry->private_data = priv;
  3337. version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
  3338. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3339. version_entry->c.ops = &wcd9378_info_ops;
  3340. if (snd_info_register(version_entry) < 0) {
  3341. snd_info_free_entry(version_entry);
  3342. snd_info_free_entry(priv->entry);
  3343. return -ENOMEM;
  3344. }
  3345. priv->version_entry = version_entry;
  3346. return 0;
  3347. }
  3348. EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
  3349. static void wcd9378_class_load(struct snd_soc_component *component)
  3350. {
  3351. /*SMP AMP CLASS LOADING*/
  3352. snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
  3353. WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3354. usleep_range(20000, 20010);
  3355. snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
  3356. WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3357. /*SMP JACK CLASS LOADING*/
  3358. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
  3359. WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3360. usleep_range(30000, 30010);
  3361. snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
  3362. WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
  3363. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
  3364. WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3365. /*SMP MIC0 CLASS LOADING*/
  3366. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
  3367. WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3368. usleep_range(5000, 5010);
  3369. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
  3370. WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3371. /*SMP MIC1 CLASS LOADING*/
  3372. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
  3373. WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3374. usleep_range(5000, 5010);
  3375. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
  3376. WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3377. /*SMP MIC2 CLASS LOADING*/
  3378. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
  3379. WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3380. usleep_range(5000, 5010);
  3381. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
  3382. WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3383. }
  3384. static void wcd9378_micb_value_convert(struct snd_soc_component *component)
  3385. {
  3386. struct wcd9378_priv *wcd9378 =
  3387. snd_soc_component_get_drvdata(component);
  3388. struct wcd9378_pdata *pdata =
  3389. dev_get_platdata(wcd9378->dev);
  3390. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  3391. mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
  3392. mb->micb1_mv, MIC_BIAS_1);
  3393. mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
  3394. mb->micb2_mv, MIC_BIAS_2);
  3395. mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
  3396. mb->micb3_mv, MIC_BIAS_3);
  3397. pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
  3398. mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
  3399. }
  3400. static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
  3401. {
  3402. struct wcd9378_priv *wcd9378 =
  3403. snd_soc_component_get_drvdata(component);
  3404. if (snd_soc_component_read(component,
  3405. WCD9378_EFUSE_REG_29)
  3406. & WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
  3407. if (((snd_soc_component_read(component,
  3408. WCD9378_EFUSE_REG_29) &
  3409. WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
  3410. return true;
  3411. else
  3412. return false;
  3413. } else {
  3414. if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
  3415. & WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
  3416. return true;
  3417. else
  3418. return false;
  3419. }
  3420. return 0;
  3421. }
  3422. static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
  3423. {
  3424. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3425. struct snd_soc_dapm_context *dapm =
  3426. snd_soc_component_get_dapm(component);
  3427. int ret = -EINVAL;
  3428. wcd9378 = snd_soc_component_get_drvdata(component);
  3429. if (!wcd9378)
  3430. return -EINVAL;
  3431. wcd9378->component = component;
  3432. snd_soc_component_init_regmap(component, wcd9378->regmap);
  3433. devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
  3434. ret = wcd9378_wcd_mode_check(component);
  3435. if (!ret) {
  3436. dev_err(component->dev, "wcd mode check failed\n");
  3437. ret = -EINVAL;
  3438. goto exit;
  3439. }
  3440. ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
  3441. if (ret) {
  3442. pr_err("%s: mbhc initialization failed\n", __func__);
  3443. ret = -EINVAL;
  3444. goto exit;
  3445. }
  3446. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3447. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3448. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3449. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3450. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3451. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3452. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3453. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3454. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3455. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3456. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3457. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  3458. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  3459. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  3460. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3461. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3462. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3463. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3464. snd_soc_dapm_sync(dapm);
  3465. wcd_cls_h_init(&wcd9378->clsh_info);
  3466. wcd9378_init_reg(component);
  3467. wcd9378_micb_value_convert(component);
  3468. wcd9378->version = WCD9378_VERSION_1_0;
  3469. /* Register event notifier */
  3470. wcd9378->nblock.notifier_call = wcd9378_event_notify;
  3471. if (wcd9378->register_notifier) {
  3472. ret = wcd9378->register_notifier(wcd9378->handle,
  3473. &wcd9378->nblock,
  3474. true);
  3475. if (ret) {
  3476. dev_err(component->dev,
  3477. "%s: Failed to register notifier %d\n",
  3478. __func__, ret);
  3479. return ret;
  3480. }
  3481. }
  3482. exit:
  3483. return ret;
  3484. }
  3485. static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
  3486. {
  3487. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3488. if (!wcd9378) {
  3489. dev_err(component->dev, "%s: wcd9378 is already NULL\n",
  3490. __func__);
  3491. return;
  3492. }
  3493. if (wcd9378->register_notifier)
  3494. wcd9378->register_notifier(wcd9378->handle,
  3495. &wcd9378->nblock,
  3496. false);
  3497. }
  3498. static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
  3499. {
  3500. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3501. if (!wcd9378)
  3502. return 0;
  3503. wcd9378->dapm_bias_off = true;
  3504. return 0;
  3505. }
  3506. static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
  3507. {
  3508. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3509. if (!wcd9378)
  3510. return 0;
  3511. wcd9378->dapm_bias_off = false;
  3512. return 0;
  3513. }
  3514. static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
  3515. .name = WCD9378_DRV_NAME,
  3516. .probe = wcd9378_soc_codec_probe,
  3517. .remove = wcd9378_soc_codec_remove,
  3518. .controls = wcd9378_snd_controls,
  3519. .num_controls = ARRAY_SIZE(wcd9378_snd_controls),
  3520. .dapm_widgets = wcd9378_dapm_widgets,
  3521. .num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
  3522. .dapm_routes = wcd9378_audio_map,
  3523. .num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
  3524. .suspend = wcd9378_soc_codec_suspend,
  3525. .resume = wcd9378_soc_codec_resume,
  3526. };
  3527. static int wcd9378_reset(struct device *dev)
  3528. {
  3529. struct wcd9378_priv *wcd9378 = NULL;
  3530. int rc = 0;
  3531. int value = 0;
  3532. if (!dev)
  3533. return -ENODEV;
  3534. wcd9378 = dev_get_drvdata(dev);
  3535. if (!wcd9378)
  3536. return -EINVAL;
  3537. if (!wcd9378->rst_np) {
  3538. dev_err(dev, "%s: reset gpio device node not specified\n",
  3539. __func__);
  3540. return -EINVAL;
  3541. }
  3542. value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
  3543. if (value > 0)
  3544. return 0;
  3545. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3546. if (rc) {
  3547. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3548. __func__);
  3549. return -EPROBE_DEFER;
  3550. }
  3551. /* 20us sleep required after pulling the reset gpio to LOW */
  3552. usleep_range(80, 85);
  3553. rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
  3554. if (rc) {
  3555. dev_err(dev, "%s: wcd active state request fail!\n",
  3556. __func__);
  3557. return -EPROBE_DEFER;
  3558. }
  3559. /* 20us sleep required after pulling the reset gpio to HIGH */
  3560. usleep_range(80, 85);
  3561. return rc;
  3562. }
  3563. static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
  3564. u32 *val)
  3565. {
  3566. int rc = 0;
  3567. rc = of_property_read_u32(dev->of_node, name, val);
  3568. if (rc)
  3569. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3570. __func__, name, dev->of_node->full_name);
  3571. return rc;
  3572. }
  3573. static void wcd9378_dt_parse_micbias_info(struct device *dev,
  3574. struct wcd9378_micbias_setting *mb)
  3575. {
  3576. u32 prop_val = 0;
  3577. int rc = 0;
  3578. /* MB1 */
  3579. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3580. NULL)) {
  3581. rc = wcd9378_read_of_property_u32(dev,
  3582. "qcom,cdc-micbias1-mv",
  3583. &prop_val);
  3584. if (!rc)
  3585. mb->micb1_mv = prop_val;
  3586. } else {
  3587. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3588. __func__);
  3589. }
  3590. /* MB2 */
  3591. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3592. NULL)) {
  3593. rc = wcd9378_read_of_property_u32(dev,
  3594. "qcom,cdc-micbias2-mv",
  3595. &prop_val);
  3596. if (!rc)
  3597. mb->micb2_mv = prop_val;
  3598. } else {
  3599. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3600. __func__);
  3601. }
  3602. /* MB3 */
  3603. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3604. NULL)) {
  3605. rc = wcd9378_read_of_property_u32(dev,
  3606. "qcom,cdc-micbias3-mv",
  3607. &prop_val);
  3608. if (!rc)
  3609. mb->micb3_mv = prop_val;
  3610. } else {
  3611. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3612. __func__);
  3613. }
  3614. }
  3615. static int wcd9378_reset_low(struct device *dev)
  3616. {
  3617. struct wcd9378_priv *wcd9378 = NULL;
  3618. int rc = 0;
  3619. if (!dev)
  3620. return -ENODEV;
  3621. wcd9378 = dev_get_drvdata(dev);
  3622. if (!wcd9378)
  3623. return -EINVAL;
  3624. if (!wcd9378->rst_np) {
  3625. dev_err(dev, "%s: reset gpio device node not specified\n",
  3626. __func__);
  3627. return -EINVAL;
  3628. }
  3629. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3630. if (rc) {
  3631. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3632. __func__);
  3633. return rc;
  3634. }
  3635. /* 20us sleep required after pulling the reset gpio to LOW */
  3636. usleep_range(20, 30);
  3637. return rc;
  3638. }
  3639. struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
  3640. {
  3641. struct wcd9378_pdata *pdata = NULL;
  3642. pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
  3643. GFP_KERNEL);
  3644. if (!pdata)
  3645. return NULL;
  3646. pdata->rst_np = of_parse_phandle(dev->of_node,
  3647. "qcom,wcd-rst-gpio-node", 0);
  3648. if (!pdata->rst_np) {
  3649. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3650. __func__, "qcom,wcd-rst-gpio-node",
  3651. dev->of_node->full_name);
  3652. return NULL;
  3653. }
  3654. /* Parse power supplies */
  3655. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3656. &pdata->num_supplies);
  3657. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3658. dev_err(dev, "%s: no power supplies defined for codec\n",
  3659. __func__);
  3660. return NULL;
  3661. }
  3662. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3663. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3664. wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
  3665. return pdata;
  3666. }
  3667. static struct snd_soc_dai_driver wcd9378_dai[] = {
  3668. {
  3669. .name = "wcd9378_cdc",
  3670. .playback = {
  3671. .stream_name = "WCD9378_AIF Playback",
  3672. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3673. .formats = WCD9378_FORMATS,
  3674. .rate_max = 384000,
  3675. .rate_min = 8000,
  3676. .channels_min = 1,
  3677. .channels_max = 4,
  3678. },
  3679. .capture = {
  3680. .stream_name = "WCD9378_AIF Capture",
  3681. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3682. .formats = WCD9378_FORMATS,
  3683. .rate_max = 384000,
  3684. .rate_min = 8000,
  3685. .channels_min = 1,
  3686. .channels_max = 4,
  3687. },
  3688. },
  3689. };
  3690. static irqreturn_t wcd9378_wd_handle_irq(int irq, void *data)
  3691. {
  3692. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3693. __func__, irq);
  3694. return IRQ_HANDLED;
  3695. }
  3696. static int wcd9378_bind(struct device *dev)
  3697. {
  3698. int ret = 0;
  3699. struct wcd9378_pdata *pdata = dev_get_platdata(dev);
  3700. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3701. /*
  3702. * Add 5msec delay to provide sufficient time for
  3703. * soundwire auto enumeration of slave devices as
  3704. * per HW requirement.
  3705. */
  3706. usleep_range(5000, 5010);
  3707. ret = component_bind_all(dev, wcd9378);
  3708. if (ret) {
  3709. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3710. __func__, ret);
  3711. return ret;
  3712. }
  3713. wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3714. if (!wcd9378->rx_swr_dev) {
  3715. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3716. __func__);
  3717. ret = -ENODEV;
  3718. goto err;
  3719. }
  3720. wcd9378->rx_swr_dev->paging_support = true;
  3721. wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3722. if (!wcd9378->tx_swr_dev) {
  3723. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3724. __func__);
  3725. ret = -ENODEV;
  3726. goto err;
  3727. }
  3728. wcd9378->tx_swr_dev->paging_support = true;
  3729. swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
  3730. wcd9378->swr_tx_port_params);
  3731. wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
  3732. &wcd9378_regmap_config);
  3733. if (!wcd9378->regmap) {
  3734. dev_err(dev, "%s: Regmap init failed\n",
  3735. __func__);
  3736. goto err;
  3737. }
  3738. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
  3739. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
  3740. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
  3741. wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
  3742. wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
  3743. wcd9378->irq_info.codec_name = "WCD9378";
  3744. wcd9378->irq_info.regmap = wcd9378->regmap;
  3745. wcd9378->irq_info.dev = dev;
  3746. ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
  3747. if (ret) {
  3748. dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
  3749. __func__, ret);
  3750. goto err;
  3751. }
  3752. dev_err(wcd9378->dev, "%s: wcd irq init done\n",
  3753. __func__);
  3754. wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
  3755. /* Request for watchdog interrupt */
  3756. wcd_request_irq(&wcd9378->irq_info, WCD9378_IRQ_HPHR_PDM_WD_INT,
  3757. "HPHR PDM WD INT", wcd9378_wd_handle_irq, NULL);
  3758. wcd_request_irq(&wcd9378->irq_info, WCD9378_IRQ_HPHL_PDM_WD_INT,
  3759. "HPHL PDM WD INT", wcd9378_wd_handle_irq, NULL);
  3760. wcd_request_irq(&wcd9378->irq_info, WCD9378_IRQ_AUX_PDM_WD_INT,
  3761. "AUX PDM WD INT", wcd9378_wd_handle_irq, NULL);
  3762. /* Disable watchdog interrupt for HPH and AUX */
  3763. wcd_disable_irq(&wcd9378->irq_info, WCD9378_IRQ_HPHR_PDM_WD_INT);
  3764. wcd_disable_irq(&wcd9378->irq_info, WCD9378_IRQ_HPHL_PDM_WD_INT);
  3765. wcd_disable_irq(&wcd9378->irq_info, WCD9378_IRQ_AUX_PDM_WD_INT);
  3766. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
  3767. wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
  3768. if (ret) {
  3769. dev_err(dev, "%s: Codec registration failed\n",
  3770. __func__);
  3771. goto err_irq;
  3772. }
  3773. return ret;
  3774. err_irq:
  3775. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3776. err:
  3777. component_unbind_all(dev, wcd9378);
  3778. return ret;
  3779. }
  3780. static void wcd9378_unbind(struct device *dev)
  3781. {
  3782. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3783. wcd_free_irq(&wcd9378->irq_info, WCD9378_IRQ_HPHR_PDM_WD_INT, NULL);
  3784. wcd_free_irq(&wcd9378->irq_info, WCD9378_IRQ_HPHL_PDM_WD_INT, NULL);
  3785. wcd_free_irq(&wcd9378->irq_info, WCD9378_IRQ_AUX_PDM_WD_INT, NULL);
  3786. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3787. snd_soc_unregister_component(dev);
  3788. component_unbind_all(dev, wcd9378);
  3789. }
  3790. static const struct of_device_id wcd9378_dt_match[] = {
  3791. { .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
  3792. {}
  3793. };
  3794. static const struct component_master_ops wcd9378_comp_ops = {
  3795. .bind = wcd9378_bind,
  3796. .unbind = wcd9378_unbind,
  3797. };
  3798. static int wcd9378_compare_of(struct device *dev, void *data)
  3799. {
  3800. return dev->of_node == data;
  3801. }
  3802. static void wcd9378_release_of(struct device *dev, void *data)
  3803. {
  3804. of_node_put(data);
  3805. }
  3806. static int wcd9378_add_slave_components(struct device *dev,
  3807. struct component_match **matchptr)
  3808. {
  3809. struct device_node *np, *rx_node, *tx_node;
  3810. np = dev->of_node;
  3811. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3812. if (!rx_node) {
  3813. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3814. return -ENODEV;
  3815. }
  3816. of_node_get(rx_node);
  3817. component_match_add_release(dev, matchptr,
  3818. wcd9378_release_of,
  3819. wcd9378_compare_of,
  3820. rx_node);
  3821. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3822. if (!tx_node) {
  3823. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3824. return -ENODEV;
  3825. }
  3826. of_node_get(tx_node);
  3827. component_match_add_release(dev, matchptr,
  3828. wcd9378_release_of,
  3829. wcd9378_compare_of,
  3830. tx_node);
  3831. return 0;
  3832. }
  3833. static int wcd9378_probe(struct platform_device *pdev)
  3834. {
  3835. struct component_match *match = NULL;
  3836. struct wcd9378_priv *wcd9378 = NULL;
  3837. struct wcd9378_pdata *pdata = NULL;
  3838. struct wcd_ctrl_platform_data *plat_data = NULL;
  3839. struct device *dev = &pdev->dev;
  3840. int ret;
  3841. wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
  3842. GFP_KERNEL);
  3843. if (!wcd9378)
  3844. return -ENOMEM;
  3845. dev_set_drvdata(dev, wcd9378);
  3846. wcd9378->dev = dev;
  3847. pdata = wcd9378_populate_dt_data(dev);
  3848. if (!pdata) {
  3849. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3850. return -EINVAL;
  3851. }
  3852. dev->platform_data = pdata;
  3853. wcd9378->rst_np = pdata->rst_np;
  3854. ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
  3855. pdata->regulator, pdata->num_supplies);
  3856. if (!wcd9378->supplies) {
  3857. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3858. __func__);
  3859. return ret;
  3860. }
  3861. plat_data = dev_get_platdata(dev->parent);
  3862. if (!plat_data) {
  3863. dev_err(dev, "%s: platform data from parent is NULL\n",
  3864. __func__);
  3865. return -EINVAL;
  3866. }
  3867. wcd9378->handle = (void *)plat_data->handle;
  3868. if (!wcd9378->handle) {
  3869. dev_err(dev, "%s: handle is NULL\n", __func__);
  3870. return -EINVAL;
  3871. }
  3872. wcd9378->update_wcd_event = plat_data->update_wcd_event;
  3873. if (!wcd9378->update_wcd_event) {
  3874. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3875. __func__);
  3876. return -EINVAL;
  3877. }
  3878. wcd9378->register_notifier = plat_data->register_notifier;
  3879. if (!wcd9378->register_notifier) {
  3880. dev_err(dev, "%s: register_notifier api is null!\n",
  3881. __func__);
  3882. return -EINVAL;
  3883. }
  3884. ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
  3885. &wcd9378->wcd_mode);
  3886. if (ret) {
  3887. dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
  3888. __func__);
  3889. wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
  3890. }
  3891. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
  3892. pdata->regulator,
  3893. pdata->num_supplies);
  3894. if (ret) {
  3895. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3896. __func__);
  3897. return ret;
  3898. }
  3899. ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3900. CODEC_RX);
  3901. ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3902. CODEC_TX);
  3903. if (ret) {
  3904. dev_err(dev, "Failed to read port mapping\n");
  3905. goto err;
  3906. }
  3907. ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
  3908. CODEC_TX);
  3909. if (ret) {
  3910. dev_err(dev, "Failed to read port params\n");
  3911. goto err;
  3912. }
  3913. mutex_init(&wcd9378->wakeup_lock);
  3914. mutex_init(&wcd9378->micb_lock);
  3915. mutex_init(&wcd9378->sys_usage_lock);
  3916. ret = wcd9378_add_slave_components(dev, &match);
  3917. if (ret)
  3918. goto err_lock_init;
  3919. ret = wcd9378_reset(dev);
  3920. if (ret == -EPROBE_DEFER) {
  3921. dev_err(dev, "%s: wcd reset failed!\n", __func__);
  3922. goto err_lock_init;
  3923. }
  3924. wcd9378->wakeup = wcd9378_wakeup;
  3925. return component_master_add_with_match(dev,
  3926. &wcd9378_comp_ops, match);
  3927. err_lock_init:
  3928. mutex_destroy(&wcd9378->micb_lock);
  3929. mutex_destroy(&wcd9378->wakeup_lock);
  3930. mutex_destroy(&wcd9378->sys_usage_lock);
  3931. err:
  3932. return ret;
  3933. }
  3934. static int wcd9378_remove(struct platform_device *pdev)
  3935. {
  3936. struct wcd9378_priv *wcd9378 = NULL;
  3937. wcd9378 = platform_get_drvdata(pdev);
  3938. component_master_del(&pdev->dev, &wcd9378_comp_ops);
  3939. mutex_destroy(&wcd9378->micb_lock);
  3940. mutex_destroy(&wcd9378->wakeup_lock);
  3941. mutex_destroy(&wcd9378->sys_usage_lock);
  3942. dev_set_drvdata(&pdev->dev, NULL);
  3943. return 0;
  3944. }
  3945. #ifdef CONFIG_PM_SLEEP
  3946. static int wcd9378_suspend(struct device *dev)
  3947. {
  3948. struct wcd9378_priv *wcd9378 = NULL;
  3949. int ret = 0;
  3950. struct wcd9378_pdata *pdata = NULL;
  3951. if (!dev)
  3952. return -ENODEV;
  3953. wcd9378 = dev_get_drvdata(dev);
  3954. if (!wcd9378)
  3955. return -EINVAL;
  3956. pdata = dev_get_platdata(wcd9378->dev);
  3957. if (!pdata) {
  3958. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3959. return -EINVAL;
  3960. }
  3961. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  3962. ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
  3963. wcd9378->supplies,
  3964. pdata->regulator,
  3965. pdata->num_supplies,
  3966. "cdc-vdd-buck");
  3967. if (ret == -EINVAL) {
  3968. dev_err(dev, "%s: vdd buck is not disabled\n",
  3969. __func__);
  3970. return 0;
  3971. }
  3972. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  3973. }
  3974. if (wcd9378->dapm_bias_off ||
  3975. (wcd9378->component &&
  3976. (snd_soc_component_get_bias_level(wcd9378->component) ==
  3977. SND_SOC_BIAS_OFF))) {
  3978. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3979. wcd9378->supplies,
  3980. pdata->regulator,
  3981. pdata->num_supplies,
  3982. true);
  3983. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3984. }
  3985. return 0;
  3986. }
  3987. static int wcd9378_resume(struct device *dev)
  3988. {
  3989. struct wcd9378_priv *wcd9378 = NULL;
  3990. struct wcd9378_pdata *pdata = NULL;
  3991. if (!dev)
  3992. return -ENODEV;
  3993. wcd9378 = dev_get_drvdata(dev);
  3994. if (!wcd9378)
  3995. return -EINVAL;
  3996. pdata = dev_get_platdata(wcd9378->dev);
  3997. if (!pdata) {
  3998. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3999. return -EINVAL;
  4000. }
  4001. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
  4002. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  4003. wcd9378->supplies,
  4004. pdata->regulator,
  4005. pdata->num_supplies,
  4006. false);
  4007. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  4008. }
  4009. return 0;
  4010. }
  4011. static const struct dev_pm_ops wcd9378_dev_pm_ops = {
  4012. .suspend_late = wcd9378_suspend,
  4013. .resume_early = wcd9378_resume,
  4014. };
  4015. #endif
  4016. static struct platform_driver wcd9378_codec_driver = {
  4017. .probe = wcd9378_probe,
  4018. .remove = wcd9378_remove,
  4019. .driver = {
  4020. .name = "wcd9378_codec",
  4021. .of_match_table = of_match_ptr(wcd9378_dt_match),
  4022. #ifdef CONFIG_PM_SLEEP
  4023. .pm = &wcd9378_dev_pm_ops,
  4024. #endif
  4025. .suppress_bind_attrs = true,
  4026. },
  4027. };
  4028. module_platform_driver(wcd9378_codec_driver);
  4029. MODULE_DESCRIPTION("WCD9378 Codec driver");
  4030. MODULE_LICENSE("GPL");