qcs405.c 229 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/input.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_qos.h>
  23. #include <sound/core.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/info.h>
  29. #include <dsp/audio_notifier.h>
  30. #include <dsp/q6afe-v2.h>
  31. #include <dsp/q6core.h>
  32. #include "device_event.h"
  33. #include "msm-pcm-routing-v2.h"
  34. #include "codecs/msm-cdc-pinctrl.h"
  35. #include "codecs/wcd9335.h"
  36. #include "codecs/wsa881x.h"
  37. #include "codecs/csra66x0/csra66x0.h"
  38. #include <dt-bindings/sound/audio-codec-port-types.h>
  39. #include "codecs/bolero/bolero-cdc.h"
  40. #include "codecs/bolero/wsa-macro.h"
  41. #define DRV_NAME "qcs405-asoc-snd"
  42. #define __CHIPSET__ "QCS405 "
  43. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  44. #define DEV_NAME_STR_LEN 32
  45. #define SAMPLING_RATE_8KHZ 8000
  46. #define SAMPLING_RATE_11P025KHZ 11025
  47. #define SAMPLING_RATE_16KHZ 16000
  48. #define SAMPLING_RATE_22P05KHZ 22050
  49. #define SAMPLING_RATE_32KHZ 32000
  50. #define SAMPLING_RATE_44P1KHZ 44100
  51. #define SAMPLING_RATE_48KHZ 48000
  52. #define SAMPLING_RATE_88P2KHZ 88200
  53. #define SAMPLING_RATE_96KHZ 96000
  54. #define SAMPLING_RATE_176P4KHZ 176400
  55. #define SAMPLING_RATE_192KHZ 192000
  56. #define SAMPLING_RATE_352P8KHZ 352800
  57. #define SAMPLING_RATE_384KHZ 384000
  58. #define SPDIF_TX_CORE_CLK_204_P8_MHZ 204800000
  59. #define TLMM_EAST_SPARE 0x07BA0000
  60. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  61. #define WSA8810_NAME_1 "wsa881x.20170211"
  62. #define WSA8810_NAME_2 "wsa881x.20170212"
  63. #define WCN_CDC_SLIM_RX_CH_MAX 2
  64. #define WCN_CDC_SLIM_TX_CH_MAX 3
  65. #define TDM_CHANNEL_MAX 8
  66. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  67. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  68. enum {
  69. SLIM_RX_0 = 0,
  70. SLIM_RX_1,
  71. SLIM_RX_2,
  72. SLIM_RX_3,
  73. SLIM_RX_4,
  74. SLIM_RX_5,
  75. SLIM_RX_6,
  76. SLIM_RX_7,
  77. SLIM_RX_MAX,
  78. };
  79. enum {
  80. SLIM_TX_0 = 0,
  81. SLIM_TX_1,
  82. SLIM_TX_2,
  83. SLIM_TX_3,
  84. SLIM_TX_4,
  85. SLIM_TX_5,
  86. SLIM_TX_6,
  87. SLIM_TX_7,
  88. SLIM_TX_8,
  89. SLIM_TX_MAX,
  90. };
  91. enum {
  92. PRIM_MI2S = 0,
  93. SEC_MI2S,
  94. TERT_MI2S,
  95. QUAT_MI2S,
  96. QUIN_MI2S,
  97. MI2S_MAX,
  98. };
  99. enum {
  100. PRIM_AUX_PCM = 0,
  101. SEC_AUX_PCM,
  102. TERT_AUX_PCM,
  103. QUAT_AUX_PCM,
  104. QUIN_AUX_PCM,
  105. AUX_PCM_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_RX_0 = 0,
  109. WSA_CDC_DMA_RX_1,
  110. CDC_DMA_RX_MAX,
  111. };
  112. enum {
  113. WSA_CDC_DMA_TX_0 = 0,
  114. WSA_CDC_DMA_TX_1,
  115. WSA_CDC_DMA_TX_2,
  116. VA_CDC_DMA_TX_0,
  117. VA_CDC_DMA_TX_1,
  118. CDC_DMA_TX_MAX,
  119. };
  120. enum {
  121. PRIM_SPDIF_RX = 0,
  122. SEC_SPDIF_RX,
  123. SPDIF_RX_MAX,
  124. };
  125. enum {
  126. PRIM_SPDIF_TX = 0,
  127. SEC_SPDIF_TX,
  128. SPDIF_TX_MAX,
  129. };
  130. struct mi2s_conf {
  131. struct mutex lock;
  132. u32 ref_cnt;
  133. u32 msm_is_mi2s_master;
  134. };
  135. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  136. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  137. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  138. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  141. };
  142. struct dev_config {
  143. u32 sample_rate;
  144. u32 bit_format;
  145. u32 channels;
  146. };
  147. struct msm_wsa881x_dev_info {
  148. struct device_node *of_node;
  149. u32 index;
  150. };
  151. struct msm_csra66x0_dev_info {
  152. struct device_node *of_node;
  153. u32 index;
  154. };
  155. enum pinctrl_pin_state {
  156. STATE_DISABLE = 0, /* All pins are in sleep state */
  157. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  158. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  159. };
  160. struct msm_pinctrl_info {
  161. struct pinctrl *pinctrl;
  162. struct pinctrl_state *mi2s_disable;
  163. struct pinctrl_state *tdm_disable;
  164. struct pinctrl_state *mi2s_active;
  165. struct pinctrl_state *tdm_active;
  166. enum pinctrl_pin_state curr_state;
  167. };
  168. struct msm_asoc_mach_data {
  169. struct snd_info_entry *codec_root;
  170. struct msm_pinctrl_info pinctrl_info;
  171. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  172. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  173. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  174. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  175. int dmic_01_gpio_cnt;
  176. int dmic_23_gpio_cnt;
  177. int dmic_45_gpio_cnt;
  178. int dmic_67_gpio_cnt;
  179. };
  180. struct msm_asoc_wcd93xx_codec {
  181. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  182. enum afe_config_type config_type);
  183. };
  184. static const char *const pin_states[] = {"sleep", "i2s-active",
  185. "tdm-active"};
  186. enum {
  187. TDM_0 = 0,
  188. TDM_1,
  189. TDM_2,
  190. TDM_3,
  191. TDM_4,
  192. TDM_5,
  193. TDM_6,
  194. TDM_7,
  195. TDM_PORT_MAX,
  196. };
  197. enum {
  198. TDM_PRI = 0,
  199. TDM_SEC,
  200. TDM_TERT,
  201. TDM_QUAT,
  202. TDM_QUIN,
  203. TDM_INTERFACE_MAX,
  204. };
  205. struct tdm_port {
  206. u32 mode;
  207. u32 channel;
  208. };
  209. /* TDM default config */
  210. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  211. { /* PRI TDM */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  220. },
  221. { /* SEC TDM */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  230. },
  231. { /* TERT TDM */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  240. },
  241. { /* QUAT TDM */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  250. },
  251. { /* QUIN TDM */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  260. }
  261. };
  262. /* TDM default config */
  263. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  264. { /* PRI TDM */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  273. },
  274. { /* SEC TDM */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  283. },
  284. { /* TERT TDM */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  293. },
  294. { /* QUAT TDM */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  303. },
  304. { /* QUIN TDM */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  313. }
  314. };
  315. /* Default configuration of slimbus channels */
  316. static struct dev_config slim_rx_cfg[] = {
  317. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. };
  326. static struct dev_config slim_tx_cfg[] = {
  327. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  328. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  336. };
  337. /* Default configuration of Codec DMA Interface Tx */
  338. static struct dev_config cdc_dma_rx_cfg[] = {
  339. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  340. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  341. };
  342. /* Default configuration of Codec DMA Interface Rx */
  343. static struct dev_config cdc_dma_tx_cfg[] = {
  344. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  345. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  346. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  348. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  349. };
  350. static struct dev_config usb_rx_cfg = {
  351. .sample_rate = SAMPLING_RATE_48KHZ,
  352. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  353. .channels = 2,
  354. };
  355. static struct dev_config usb_tx_cfg = {
  356. .sample_rate = SAMPLING_RATE_48KHZ,
  357. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  358. .channels = 1,
  359. };
  360. static struct dev_config proxy_rx_cfg = {
  361. .sample_rate = SAMPLING_RATE_48KHZ,
  362. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  363. .channels = 2,
  364. };
  365. /* Default configuration of MI2S channels */
  366. static struct dev_config mi2s_rx_cfg[] = {
  367. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  368. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  369. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  372. };
  373. /* Default configuration of SPDIF channels */
  374. static struct dev_config spdif_rx_cfg[] = {
  375. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  376. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  377. };
  378. static struct dev_config spdif_tx_cfg[] = {
  379. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  380. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  381. };
  382. static struct dev_config mi2s_tx_cfg[] = {
  383. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  384. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  385. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. };
  389. static struct dev_config aux_pcm_rx_cfg[] = {
  390. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  391. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  392. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. };
  396. static struct dev_config aux_pcm_tx_cfg[] = {
  397. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  400. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. };
  403. static int msm_vi_feed_tx_ch = 2;
  404. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  405. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  406. "Five", "Six", "Seven",
  407. "Eight"};
  408. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  409. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  410. "S32_LE"};
  411. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  412. "KHZ_32", "KHZ_44P1", "KHZ_48",
  413. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  414. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  415. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  416. "KHZ_44P1", "KHZ_48",
  417. "KHZ_88P2", "KHZ_96"};
  418. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  419. "Five", "Six", "Seven",
  420. "Eight"};
  421. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  422. "Six", "Seven", "Eight"};
  423. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  424. "KHZ_16", "KHZ_22P05",
  425. "KHZ_32", "KHZ_44P1", "KHZ_48",
  426. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  427. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  428. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  429. "Five", "Six", "Seven", "Eight"};
  430. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  431. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  432. "KHZ_48", "KHZ_176P4",
  433. "KHZ_352P8"};
  434. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  435. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  436. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  437. "KHZ_48", "KHZ_96", "KHZ_192"};
  438. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  439. "Five", "Six", "Seven",
  440. "Eight"};
  441. static const char *const qos_text[] = {"Disable", "Enable"};
  442. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  443. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  444. "Five", "Six", "Seven",
  445. "Eight"};
  446. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  447. "KHZ_16", "KHZ_22P05",
  448. "KHZ_32", "KHZ_44P1", "KHZ_48",
  449. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  450. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  451. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  452. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  453. "KHZ_192"};
  454. static const char *spdif_ch_text[] = {"One", "Two"};
  455. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  456. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  534. cdc_dma_sample_rate_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  536. cdc_dma_sample_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  538. cdc_dma_sample_rate_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  540. cdc_dma_sample_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  542. cdc_dma_sample_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  544. cdc_dma_sample_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  546. cdc_dma_sample_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  553. static struct platform_device *spdev;
  554. static bool is_initial_boot;
  555. static bool codec_reg_done;
  556. static struct snd_soc_aux_dev *msm_aux_dev;
  557. static struct snd_soc_codec_conf *msm_codec_conf;
  558. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  559. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  560. int enable, bool dapm);
  561. static int msm_wsa881x_init(struct snd_soc_component *component);
  562. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  563. struct snd_ctl_elem_value *ucontrol);
  564. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  565. {"MIC BIAS1", NULL, "MCLK TX"},
  566. {"MIC BIAS2", NULL, "MCLK TX"},
  567. {"MIC BIAS3", NULL, "MCLK TX"},
  568. {"MIC BIAS4", NULL, "MCLK TX"},
  569. };
  570. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  571. {
  572. AFE_API_VERSION_I2S_CONFIG,
  573. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  574. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  575. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  576. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  577. 0,
  578. },
  579. {
  580. AFE_API_VERSION_I2S_CONFIG,
  581. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  582. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  583. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  584. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  585. 0,
  586. },
  587. {
  588. AFE_API_VERSION_I2S_CONFIG,
  589. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  590. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  591. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  592. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  593. 0,
  594. },
  595. {
  596. AFE_API_VERSION_I2S_CONFIG,
  597. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  598. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  599. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  600. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  601. 0,
  602. },
  603. {
  604. AFE_API_VERSION_I2S_CONFIG,
  605. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  606. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  607. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  608. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  609. 0,
  610. }
  611. };
  612. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  613. static int slim_get_sample_rate_val(int sample_rate)
  614. {
  615. int sample_rate_val = 0;
  616. switch (sample_rate) {
  617. case SAMPLING_RATE_8KHZ:
  618. sample_rate_val = 0;
  619. break;
  620. case SAMPLING_RATE_16KHZ:
  621. sample_rate_val = 1;
  622. break;
  623. case SAMPLING_RATE_32KHZ:
  624. sample_rate_val = 2;
  625. break;
  626. case SAMPLING_RATE_44P1KHZ:
  627. sample_rate_val = 3;
  628. break;
  629. case SAMPLING_RATE_48KHZ:
  630. sample_rate_val = 4;
  631. break;
  632. case SAMPLING_RATE_88P2KHZ:
  633. sample_rate_val = 5;
  634. break;
  635. case SAMPLING_RATE_96KHZ:
  636. sample_rate_val = 6;
  637. break;
  638. case SAMPLING_RATE_176P4KHZ:
  639. sample_rate_val = 7;
  640. break;
  641. case SAMPLING_RATE_192KHZ:
  642. sample_rate_val = 8;
  643. break;
  644. case SAMPLING_RATE_352P8KHZ:
  645. sample_rate_val = 9;
  646. break;
  647. case SAMPLING_RATE_384KHZ:
  648. sample_rate_val = 10;
  649. break;
  650. default:
  651. sample_rate_val = 4;
  652. break;
  653. }
  654. return sample_rate_val;
  655. }
  656. static int slim_get_sample_rate(int value)
  657. {
  658. int sample_rate = 0;
  659. switch (value) {
  660. case 0:
  661. sample_rate = SAMPLING_RATE_8KHZ;
  662. break;
  663. case 1:
  664. sample_rate = SAMPLING_RATE_16KHZ;
  665. break;
  666. case 2:
  667. sample_rate = SAMPLING_RATE_32KHZ;
  668. break;
  669. case 3:
  670. sample_rate = SAMPLING_RATE_44P1KHZ;
  671. break;
  672. case 4:
  673. sample_rate = SAMPLING_RATE_48KHZ;
  674. break;
  675. case 5:
  676. sample_rate = SAMPLING_RATE_88P2KHZ;
  677. break;
  678. case 6:
  679. sample_rate = SAMPLING_RATE_96KHZ;
  680. break;
  681. case 7:
  682. sample_rate = SAMPLING_RATE_176P4KHZ;
  683. break;
  684. case 8:
  685. sample_rate = SAMPLING_RATE_192KHZ;
  686. break;
  687. case 9:
  688. sample_rate = SAMPLING_RATE_352P8KHZ;
  689. break;
  690. case 10:
  691. sample_rate = SAMPLING_RATE_384KHZ;
  692. break;
  693. default:
  694. sample_rate = SAMPLING_RATE_48KHZ;
  695. break;
  696. }
  697. return sample_rate;
  698. }
  699. static int slim_get_bit_format_val(int bit_format)
  700. {
  701. int val = 0;
  702. switch (bit_format) {
  703. case SNDRV_PCM_FORMAT_S32_LE:
  704. val = 3;
  705. break;
  706. case SNDRV_PCM_FORMAT_S24_3LE:
  707. val = 2;
  708. break;
  709. case SNDRV_PCM_FORMAT_S24_LE:
  710. val = 1;
  711. break;
  712. case SNDRV_PCM_FORMAT_S16_LE:
  713. default:
  714. val = 0;
  715. break;
  716. }
  717. return val;
  718. }
  719. static int slim_get_bit_format(int val)
  720. {
  721. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  722. switch (val) {
  723. case 0:
  724. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  725. break;
  726. case 1:
  727. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  728. break;
  729. case 2:
  730. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  731. break;
  732. case 3:
  733. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  734. break;
  735. default:
  736. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  737. break;
  738. }
  739. return bit_fmt;
  740. }
  741. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  742. {
  743. int port_id = 0;
  744. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  745. port_id = SLIM_RX_0;
  746. } else if (strnstr(kcontrol->id.name,
  747. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  748. port_id = SLIM_RX_2;
  749. } else if (strnstr(kcontrol->id.name,
  750. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  751. port_id = SLIM_RX_5;
  752. } else if (strnstr(kcontrol->id.name,
  753. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  754. port_id = SLIM_RX_6;
  755. } else if (strnstr(kcontrol->id.name,
  756. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  757. port_id = SLIM_TX_0;
  758. } else if (strnstr(kcontrol->id.name,
  759. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  760. port_id = SLIM_TX_1;
  761. } else {
  762. pr_err("%s: unsupported channel: %s",
  763. __func__, kcontrol->id.name);
  764. return -EINVAL;
  765. }
  766. return port_id;
  767. }
  768. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  769. struct snd_ctl_elem_value *ucontrol)
  770. {
  771. int ch_num = slim_get_port_idx(kcontrol);
  772. if (ch_num < 0)
  773. return ch_num;
  774. ucontrol->value.enumerated.item[0] =
  775. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  776. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  777. ch_num, slim_rx_cfg[ch_num].sample_rate,
  778. ucontrol->value.enumerated.item[0]);
  779. return 0;
  780. }
  781. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  782. struct snd_ctl_elem_value *ucontrol)
  783. {
  784. int ch_num = slim_get_port_idx(kcontrol);
  785. if (ch_num < 0)
  786. return ch_num;
  787. slim_rx_cfg[ch_num].sample_rate =
  788. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  789. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  790. ch_num, slim_rx_cfg[ch_num].sample_rate,
  791. ucontrol->value.enumerated.item[0]);
  792. return 0;
  793. }
  794. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  795. struct snd_ctl_elem_value *ucontrol)
  796. {
  797. int ch_num = slim_get_port_idx(kcontrol);
  798. if (ch_num < 0)
  799. return ch_num;
  800. ucontrol->value.enumerated.item[0] =
  801. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  802. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  803. ch_num, slim_tx_cfg[ch_num].sample_rate,
  804. ucontrol->value.enumerated.item[0]);
  805. return 0;
  806. }
  807. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  808. struct snd_ctl_elem_value *ucontrol)
  809. {
  810. int sample_rate = 0;
  811. int ch_num = slim_get_port_idx(kcontrol);
  812. if (ch_num < 0)
  813. return ch_num;
  814. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  815. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  816. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  817. __func__, sample_rate);
  818. return -EINVAL;
  819. }
  820. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  821. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  822. ch_num, slim_tx_cfg[ch_num].sample_rate,
  823. ucontrol->value.enumerated.item[0]);
  824. return 0;
  825. }
  826. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  827. struct snd_ctl_elem_value *ucontrol)
  828. {
  829. int ch_num = slim_get_port_idx(kcontrol);
  830. if (ch_num < 0)
  831. return ch_num;
  832. ucontrol->value.enumerated.item[0] =
  833. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  834. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  835. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  836. ucontrol->value.enumerated.item[0]);
  837. return 0;
  838. }
  839. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  840. struct snd_ctl_elem_value *ucontrol)
  841. {
  842. int ch_num = slim_get_port_idx(kcontrol);
  843. if (ch_num < 0)
  844. return ch_num;
  845. slim_rx_cfg[ch_num].bit_format =
  846. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  847. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  848. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  849. ucontrol->value.enumerated.item[0]);
  850. return 0;
  851. }
  852. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  853. struct snd_ctl_elem_value *ucontrol)
  854. {
  855. int ch_num = slim_get_port_idx(kcontrol);
  856. if (ch_num < 0)
  857. return ch_num;
  858. ucontrol->value.enumerated.item[0] =
  859. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  860. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  861. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  862. ucontrol->value.enumerated.item[0]);
  863. return 0;
  864. }
  865. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  866. struct snd_ctl_elem_value *ucontrol)
  867. {
  868. int ch_num = slim_get_port_idx(kcontrol);
  869. if (ch_num < 0)
  870. return ch_num;
  871. slim_tx_cfg[ch_num].bit_format =
  872. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  873. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  874. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  875. ucontrol->value.enumerated.item[0]);
  876. return 0;
  877. }
  878. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  879. struct snd_ctl_elem_value *ucontrol)
  880. {
  881. int ch_num = slim_get_port_idx(kcontrol);
  882. if (ch_num < 0)
  883. return ch_num;
  884. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  885. ch_num, slim_rx_cfg[ch_num].channels);
  886. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  887. return 0;
  888. }
  889. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  890. struct snd_ctl_elem_value *ucontrol)
  891. {
  892. int ch_num = slim_get_port_idx(kcontrol);
  893. if (ch_num < 0)
  894. return ch_num;
  895. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  896. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  897. ch_num, slim_rx_cfg[ch_num].channels);
  898. return 1;
  899. }
  900. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  901. struct snd_ctl_elem_value *ucontrol)
  902. {
  903. int ch_num = slim_get_port_idx(kcontrol);
  904. if (ch_num < 0)
  905. return ch_num;
  906. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  907. ch_num, slim_tx_cfg[ch_num].channels);
  908. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  909. return 0;
  910. }
  911. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  912. struct snd_ctl_elem_value *ucontrol)
  913. {
  914. int ch_num = slim_get_port_idx(kcontrol);
  915. if (ch_num < 0)
  916. return ch_num;
  917. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  918. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  919. ch_num, slim_tx_cfg[ch_num].channels);
  920. return 1;
  921. }
  922. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  923. struct snd_ctl_elem_value *ucontrol)
  924. {
  925. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  926. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  927. ucontrol->value.integer.value[0]);
  928. return 0;
  929. }
  930. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  931. struct snd_ctl_elem_value *ucontrol)
  932. {
  933. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  934. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  935. return 1;
  936. }
  937. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  938. struct snd_ctl_elem_value *ucontrol)
  939. {
  940. /*
  941. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  942. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  943. * value.
  944. */
  945. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  946. case SAMPLING_RATE_96KHZ:
  947. ucontrol->value.integer.value[0] = 5;
  948. break;
  949. case SAMPLING_RATE_88P2KHZ:
  950. ucontrol->value.integer.value[0] = 4;
  951. break;
  952. case SAMPLING_RATE_48KHZ:
  953. ucontrol->value.integer.value[0] = 3;
  954. break;
  955. case SAMPLING_RATE_44P1KHZ:
  956. ucontrol->value.integer.value[0] = 2;
  957. break;
  958. case SAMPLING_RATE_16KHZ:
  959. ucontrol->value.integer.value[0] = 1;
  960. break;
  961. case SAMPLING_RATE_8KHZ:
  962. default:
  963. ucontrol->value.integer.value[0] = 0;
  964. break;
  965. }
  966. pr_debug("%s: sample rate = %d", __func__,
  967. slim_rx_cfg[SLIM_RX_7].sample_rate);
  968. return 0;
  969. }
  970. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  971. struct snd_ctl_elem_value *ucontrol)
  972. {
  973. switch (ucontrol->value.integer.value[0]) {
  974. case 1:
  975. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  976. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  977. break;
  978. case 2:
  979. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  980. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  981. break;
  982. case 3:
  983. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  984. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  985. break;
  986. case 4:
  987. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  988. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  989. break;
  990. case 5:
  991. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  992. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  993. break;
  994. case 0:
  995. default:
  996. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  997. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  998. break;
  999. }
  1000. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1001. __func__,
  1002. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1003. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1004. ucontrol->value.enumerated.item[0]);
  1005. return 0;
  1006. }
  1007. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1008. {
  1009. int idx = 0;
  1010. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1011. sizeof("WSA_CDC_DMA_RX_0")))
  1012. idx = WSA_CDC_DMA_RX_0;
  1013. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1014. sizeof("WSA_CDC_DMA_RX_0")))
  1015. idx = WSA_CDC_DMA_RX_1;
  1016. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1017. sizeof("WSA_CDC_DMA_TX_0")))
  1018. idx = WSA_CDC_DMA_TX_0;
  1019. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1020. sizeof("WSA_CDC_DMA_TX_1")))
  1021. idx = WSA_CDC_DMA_TX_1;
  1022. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1023. sizeof("WSA_CDC_DMA_TX_2")))
  1024. idx = WSA_CDC_DMA_TX_2;
  1025. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1026. sizeof("VA_CDC_DMA_TX_0")))
  1027. idx = VA_CDC_DMA_TX_0;
  1028. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1029. sizeof("VA_CDC_DMA_TX_1")))
  1030. idx = VA_CDC_DMA_TX_1;
  1031. else {
  1032. pr_err("%s: unsupported port: %s\n",
  1033. __func__, kcontrol->id.name);
  1034. return -EINVAL;
  1035. }
  1036. return idx;
  1037. }
  1038. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1039. struct snd_ctl_elem_value *ucontrol)
  1040. {
  1041. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1042. if (ch_num < 0)
  1043. return ch_num;
  1044. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1045. cdc_dma_rx_cfg[ch_num].channels - 1);
  1046. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1047. return 0;
  1048. }
  1049. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1050. struct snd_ctl_elem_value *ucontrol)
  1051. {
  1052. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1053. if (ch_num < 0)
  1054. return ch_num;
  1055. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1056. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1057. cdc_dma_rx_cfg[ch_num].channels);
  1058. return 1;
  1059. }
  1060. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1061. struct snd_ctl_elem_value *ucontrol)
  1062. {
  1063. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1064. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1065. case SNDRV_PCM_FORMAT_S32_LE:
  1066. ucontrol->value.integer.value[0] = 3;
  1067. break;
  1068. case SNDRV_PCM_FORMAT_S24_3LE:
  1069. ucontrol->value.integer.value[0] = 2;
  1070. break;
  1071. case SNDRV_PCM_FORMAT_S24_LE:
  1072. ucontrol->value.integer.value[0] = 1;
  1073. break;
  1074. case SNDRV_PCM_FORMAT_S16_LE:
  1075. default:
  1076. ucontrol->value.integer.value[0] = 0;
  1077. break;
  1078. }
  1079. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1080. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1081. ucontrol->value.integer.value[0]);
  1082. return 0;
  1083. }
  1084. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1085. struct snd_ctl_elem_value *ucontrol)
  1086. {
  1087. int rc = 0;
  1088. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1089. switch (ucontrol->value.integer.value[0]) {
  1090. case 3:
  1091. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1092. break;
  1093. case 2:
  1094. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1095. break;
  1096. case 1:
  1097. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1098. break;
  1099. case 0:
  1100. default:
  1101. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1102. break;
  1103. }
  1104. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1105. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1106. ucontrol->value.integer.value[0]);
  1107. return rc;
  1108. }
  1109. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1110. {
  1111. int sample_rate_val = 0;
  1112. switch (sample_rate) {
  1113. case SAMPLING_RATE_8KHZ:
  1114. sample_rate_val = 0;
  1115. break;
  1116. case SAMPLING_RATE_16KHZ:
  1117. sample_rate_val = 1;
  1118. break;
  1119. case SAMPLING_RATE_32KHZ:
  1120. sample_rate_val = 2;
  1121. break;
  1122. case SAMPLING_RATE_44P1KHZ:
  1123. sample_rate_val = 3;
  1124. break;
  1125. case SAMPLING_RATE_48KHZ:
  1126. sample_rate_val = 4;
  1127. break;
  1128. case SAMPLING_RATE_88P2KHZ:
  1129. sample_rate_val = 5;
  1130. break;
  1131. case SAMPLING_RATE_96KHZ:
  1132. sample_rate_val = 6;
  1133. break;
  1134. case SAMPLING_RATE_176P4KHZ:
  1135. sample_rate_val = 7;
  1136. break;
  1137. case SAMPLING_RATE_192KHZ:
  1138. sample_rate_val = 8;
  1139. break;
  1140. case SAMPLING_RATE_352P8KHZ:
  1141. sample_rate_val = 9;
  1142. break;
  1143. case SAMPLING_RATE_384KHZ:
  1144. sample_rate_val = 10;
  1145. break;
  1146. default:
  1147. sample_rate_val = 4;
  1148. break;
  1149. }
  1150. return sample_rate_val;
  1151. }
  1152. static int cdc_dma_get_sample_rate(int value)
  1153. {
  1154. int sample_rate = 0;
  1155. switch (value) {
  1156. case 0:
  1157. sample_rate = SAMPLING_RATE_8KHZ;
  1158. break;
  1159. case 1:
  1160. sample_rate = SAMPLING_RATE_16KHZ;
  1161. break;
  1162. case 2:
  1163. sample_rate = SAMPLING_RATE_32KHZ;
  1164. break;
  1165. case 3:
  1166. sample_rate = SAMPLING_RATE_44P1KHZ;
  1167. break;
  1168. case 4:
  1169. sample_rate = SAMPLING_RATE_48KHZ;
  1170. break;
  1171. case 5:
  1172. sample_rate = SAMPLING_RATE_88P2KHZ;
  1173. break;
  1174. case 6:
  1175. sample_rate = SAMPLING_RATE_96KHZ;
  1176. break;
  1177. case 7:
  1178. sample_rate = SAMPLING_RATE_176P4KHZ;
  1179. break;
  1180. case 8:
  1181. sample_rate = SAMPLING_RATE_192KHZ;
  1182. break;
  1183. case 9:
  1184. sample_rate = SAMPLING_RATE_352P8KHZ;
  1185. break;
  1186. case 10:
  1187. sample_rate = SAMPLING_RATE_384KHZ;
  1188. break;
  1189. default:
  1190. sample_rate = SAMPLING_RATE_48KHZ;
  1191. break;
  1192. }
  1193. return sample_rate;
  1194. }
  1195. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1196. struct snd_ctl_elem_value *ucontrol)
  1197. {
  1198. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1199. if (ch_num < 0)
  1200. return ch_num;
  1201. ucontrol->value.enumerated.item[0] =
  1202. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1203. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1204. cdc_dma_rx_cfg[ch_num].sample_rate);
  1205. return 0;
  1206. }
  1207. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1208. struct snd_ctl_elem_value *ucontrol)
  1209. {
  1210. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1211. if (ch_num < 0)
  1212. return ch_num;
  1213. cdc_dma_rx_cfg[ch_num].sample_rate =
  1214. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1215. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1216. __func__, ucontrol->value.enumerated.item[0],
  1217. cdc_dma_rx_cfg[ch_num].sample_rate);
  1218. return 0;
  1219. }
  1220. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1221. struct snd_ctl_elem_value *ucontrol)
  1222. {
  1223. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1224. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1225. cdc_dma_tx_cfg[ch_num].channels);
  1226. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1227. return 0;
  1228. }
  1229. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1230. struct snd_ctl_elem_value *ucontrol)
  1231. {
  1232. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1233. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1234. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1235. cdc_dma_tx_cfg[ch_num].channels);
  1236. return 1;
  1237. }
  1238. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1239. struct snd_ctl_elem_value *ucontrol)
  1240. {
  1241. int sample_rate_val;
  1242. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1243. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1244. case SAMPLING_RATE_384KHZ:
  1245. sample_rate_val = 12;
  1246. break;
  1247. case SAMPLING_RATE_352P8KHZ:
  1248. sample_rate_val = 11;
  1249. break;
  1250. case SAMPLING_RATE_192KHZ:
  1251. sample_rate_val = 10;
  1252. break;
  1253. case SAMPLING_RATE_176P4KHZ:
  1254. sample_rate_val = 9;
  1255. break;
  1256. case SAMPLING_RATE_96KHZ:
  1257. sample_rate_val = 8;
  1258. break;
  1259. case SAMPLING_RATE_88P2KHZ:
  1260. sample_rate_val = 7;
  1261. break;
  1262. case SAMPLING_RATE_48KHZ:
  1263. sample_rate_val = 6;
  1264. break;
  1265. case SAMPLING_RATE_44P1KHZ:
  1266. sample_rate_val = 5;
  1267. break;
  1268. case SAMPLING_RATE_32KHZ:
  1269. sample_rate_val = 4;
  1270. break;
  1271. case SAMPLING_RATE_22P05KHZ:
  1272. sample_rate_val = 3;
  1273. break;
  1274. case SAMPLING_RATE_16KHZ:
  1275. sample_rate_val = 2;
  1276. break;
  1277. case SAMPLING_RATE_11P025KHZ:
  1278. sample_rate_val = 1;
  1279. break;
  1280. case SAMPLING_RATE_8KHZ:
  1281. sample_rate_val = 0;
  1282. break;
  1283. default:
  1284. sample_rate_val = 6;
  1285. break;
  1286. }
  1287. ucontrol->value.integer.value[0] = sample_rate_val;
  1288. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1289. cdc_dma_tx_cfg[ch_num].sample_rate);
  1290. return 0;
  1291. }
  1292. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1293. struct snd_ctl_elem_value *ucontrol)
  1294. {
  1295. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1296. switch (ucontrol->value.integer.value[0]) {
  1297. case 12:
  1298. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1299. break;
  1300. case 11:
  1301. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1302. break;
  1303. case 10:
  1304. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1305. break;
  1306. case 9:
  1307. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1308. break;
  1309. case 8:
  1310. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1311. break;
  1312. case 7:
  1313. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1314. break;
  1315. case 6:
  1316. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1317. break;
  1318. case 5:
  1319. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1320. break;
  1321. case 4:
  1322. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1323. break;
  1324. case 3:
  1325. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1326. break;
  1327. case 2:
  1328. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1329. break;
  1330. case 1:
  1331. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1332. break;
  1333. case 0:
  1334. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1335. break;
  1336. default:
  1337. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1338. break;
  1339. }
  1340. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1341. __func__, ucontrol->value.integer.value[0],
  1342. cdc_dma_tx_cfg[ch_num].sample_rate);
  1343. return 0;
  1344. }
  1345. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1346. struct snd_ctl_elem_value *ucontrol)
  1347. {
  1348. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1349. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1350. case SNDRV_PCM_FORMAT_S32_LE:
  1351. ucontrol->value.integer.value[0] = 3;
  1352. break;
  1353. case SNDRV_PCM_FORMAT_S24_3LE:
  1354. ucontrol->value.integer.value[0] = 2;
  1355. break;
  1356. case SNDRV_PCM_FORMAT_S24_LE:
  1357. ucontrol->value.integer.value[0] = 1;
  1358. break;
  1359. case SNDRV_PCM_FORMAT_S16_LE:
  1360. default:
  1361. ucontrol->value.integer.value[0] = 0;
  1362. break;
  1363. }
  1364. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1365. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1366. ucontrol->value.integer.value[0]);
  1367. return 0;
  1368. }
  1369. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1370. struct snd_ctl_elem_value *ucontrol)
  1371. {
  1372. int rc = 0;
  1373. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1374. switch (ucontrol->value.integer.value[0]) {
  1375. case 3:
  1376. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1377. break;
  1378. case 2:
  1379. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1380. break;
  1381. case 1:
  1382. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1383. break;
  1384. case 0:
  1385. default:
  1386. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1387. break;
  1388. }
  1389. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1390. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1391. ucontrol->value.integer.value[0]);
  1392. return rc;
  1393. }
  1394. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1395. struct snd_ctl_elem_value *ucontrol)
  1396. {
  1397. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1398. usb_rx_cfg.channels);
  1399. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1400. return 0;
  1401. }
  1402. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1403. struct snd_ctl_elem_value *ucontrol)
  1404. {
  1405. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1406. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1407. return 1;
  1408. }
  1409. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1410. struct snd_ctl_elem_value *ucontrol)
  1411. {
  1412. int sample_rate_val;
  1413. switch (usb_rx_cfg.sample_rate) {
  1414. case SAMPLING_RATE_384KHZ:
  1415. sample_rate_val = 12;
  1416. break;
  1417. case SAMPLING_RATE_352P8KHZ:
  1418. sample_rate_val = 11;
  1419. break;
  1420. case SAMPLING_RATE_192KHZ:
  1421. sample_rate_val = 10;
  1422. break;
  1423. case SAMPLING_RATE_176P4KHZ:
  1424. sample_rate_val = 9;
  1425. break;
  1426. case SAMPLING_RATE_96KHZ:
  1427. sample_rate_val = 8;
  1428. break;
  1429. case SAMPLING_RATE_88P2KHZ:
  1430. sample_rate_val = 7;
  1431. break;
  1432. case SAMPLING_RATE_48KHZ:
  1433. sample_rate_val = 6;
  1434. break;
  1435. case SAMPLING_RATE_44P1KHZ:
  1436. sample_rate_val = 5;
  1437. break;
  1438. case SAMPLING_RATE_32KHZ:
  1439. sample_rate_val = 4;
  1440. break;
  1441. case SAMPLING_RATE_22P05KHZ:
  1442. sample_rate_val = 3;
  1443. break;
  1444. case SAMPLING_RATE_16KHZ:
  1445. sample_rate_val = 2;
  1446. break;
  1447. case SAMPLING_RATE_11P025KHZ:
  1448. sample_rate_val = 1;
  1449. break;
  1450. case SAMPLING_RATE_8KHZ:
  1451. default:
  1452. sample_rate_val = 0;
  1453. break;
  1454. }
  1455. ucontrol->value.integer.value[0] = sample_rate_val;
  1456. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1457. usb_rx_cfg.sample_rate);
  1458. return 0;
  1459. }
  1460. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1461. struct snd_ctl_elem_value *ucontrol)
  1462. {
  1463. switch (ucontrol->value.integer.value[0]) {
  1464. case 12:
  1465. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1466. break;
  1467. case 11:
  1468. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1469. break;
  1470. case 10:
  1471. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1472. break;
  1473. case 9:
  1474. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1475. break;
  1476. case 8:
  1477. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1478. break;
  1479. case 7:
  1480. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1481. break;
  1482. case 6:
  1483. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1484. break;
  1485. case 5:
  1486. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1487. break;
  1488. case 4:
  1489. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1490. break;
  1491. case 3:
  1492. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1493. break;
  1494. case 2:
  1495. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1496. break;
  1497. case 1:
  1498. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1499. break;
  1500. case 0:
  1501. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1502. break;
  1503. default:
  1504. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1505. break;
  1506. }
  1507. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1508. __func__, ucontrol->value.integer.value[0],
  1509. usb_rx_cfg.sample_rate);
  1510. return 0;
  1511. }
  1512. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1513. struct snd_ctl_elem_value *ucontrol)
  1514. {
  1515. switch (usb_rx_cfg.bit_format) {
  1516. case SNDRV_PCM_FORMAT_S32_LE:
  1517. ucontrol->value.integer.value[0] = 3;
  1518. break;
  1519. case SNDRV_PCM_FORMAT_S24_3LE:
  1520. ucontrol->value.integer.value[0] = 2;
  1521. break;
  1522. case SNDRV_PCM_FORMAT_S24_LE:
  1523. ucontrol->value.integer.value[0] = 1;
  1524. break;
  1525. case SNDRV_PCM_FORMAT_S16_LE:
  1526. default:
  1527. ucontrol->value.integer.value[0] = 0;
  1528. break;
  1529. }
  1530. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1531. __func__, usb_rx_cfg.bit_format,
  1532. ucontrol->value.integer.value[0]);
  1533. return 0;
  1534. }
  1535. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1536. struct snd_ctl_elem_value *ucontrol)
  1537. {
  1538. int rc = 0;
  1539. switch (ucontrol->value.integer.value[0]) {
  1540. case 3:
  1541. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1542. break;
  1543. case 2:
  1544. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1545. break;
  1546. case 1:
  1547. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1548. break;
  1549. case 0:
  1550. default:
  1551. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1552. break;
  1553. }
  1554. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1555. __func__, usb_rx_cfg.bit_format,
  1556. ucontrol->value.integer.value[0]);
  1557. return rc;
  1558. }
  1559. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1560. struct snd_ctl_elem_value *ucontrol)
  1561. {
  1562. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1563. usb_tx_cfg.channels);
  1564. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1565. return 0;
  1566. }
  1567. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1568. struct snd_ctl_elem_value *ucontrol)
  1569. {
  1570. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1571. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1572. return 1;
  1573. }
  1574. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1575. struct snd_ctl_elem_value *ucontrol)
  1576. {
  1577. int sample_rate_val;
  1578. switch (usb_tx_cfg.sample_rate) {
  1579. case SAMPLING_RATE_384KHZ:
  1580. sample_rate_val = 12;
  1581. break;
  1582. case SAMPLING_RATE_352P8KHZ:
  1583. sample_rate_val = 11;
  1584. break;
  1585. case SAMPLING_RATE_192KHZ:
  1586. sample_rate_val = 10;
  1587. break;
  1588. case SAMPLING_RATE_176P4KHZ:
  1589. sample_rate_val = 9;
  1590. break;
  1591. case SAMPLING_RATE_96KHZ:
  1592. sample_rate_val = 8;
  1593. break;
  1594. case SAMPLING_RATE_88P2KHZ:
  1595. sample_rate_val = 7;
  1596. break;
  1597. case SAMPLING_RATE_48KHZ:
  1598. sample_rate_val = 6;
  1599. break;
  1600. case SAMPLING_RATE_44P1KHZ:
  1601. sample_rate_val = 5;
  1602. break;
  1603. case SAMPLING_RATE_32KHZ:
  1604. sample_rate_val = 4;
  1605. break;
  1606. case SAMPLING_RATE_22P05KHZ:
  1607. sample_rate_val = 3;
  1608. break;
  1609. case SAMPLING_RATE_16KHZ:
  1610. sample_rate_val = 2;
  1611. break;
  1612. case SAMPLING_RATE_11P025KHZ:
  1613. sample_rate_val = 1;
  1614. break;
  1615. case SAMPLING_RATE_8KHZ:
  1616. sample_rate_val = 0;
  1617. break;
  1618. default:
  1619. sample_rate_val = 6;
  1620. break;
  1621. }
  1622. ucontrol->value.integer.value[0] = sample_rate_val;
  1623. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1624. usb_tx_cfg.sample_rate);
  1625. return 0;
  1626. }
  1627. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1628. struct snd_ctl_elem_value *ucontrol)
  1629. {
  1630. switch (ucontrol->value.integer.value[0]) {
  1631. case 12:
  1632. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1633. break;
  1634. case 11:
  1635. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1636. break;
  1637. case 10:
  1638. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1639. break;
  1640. case 9:
  1641. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1642. break;
  1643. case 8:
  1644. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1645. break;
  1646. case 7:
  1647. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1648. break;
  1649. case 6:
  1650. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1651. break;
  1652. case 5:
  1653. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1654. break;
  1655. case 4:
  1656. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1657. break;
  1658. case 3:
  1659. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1660. break;
  1661. case 2:
  1662. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1663. break;
  1664. case 1:
  1665. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1666. break;
  1667. case 0:
  1668. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1669. break;
  1670. default:
  1671. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1672. break;
  1673. }
  1674. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1675. __func__, ucontrol->value.integer.value[0],
  1676. usb_tx_cfg.sample_rate);
  1677. return 0;
  1678. }
  1679. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1680. struct snd_ctl_elem_value *ucontrol)
  1681. {
  1682. switch (usb_tx_cfg.bit_format) {
  1683. case SNDRV_PCM_FORMAT_S32_LE:
  1684. ucontrol->value.integer.value[0] = 3;
  1685. break;
  1686. case SNDRV_PCM_FORMAT_S24_3LE:
  1687. ucontrol->value.integer.value[0] = 2;
  1688. break;
  1689. case SNDRV_PCM_FORMAT_S24_LE:
  1690. ucontrol->value.integer.value[0] = 1;
  1691. break;
  1692. case SNDRV_PCM_FORMAT_S16_LE:
  1693. default:
  1694. ucontrol->value.integer.value[0] = 0;
  1695. break;
  1696. }
  1697. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1698. __func__, usb_tx_cfg.bit_format,
  1699. ucontrol->value.integer.value[0]);
  1700. return 0;
  1701. }
  1702. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1703. struct snd_ctl_elem_value *ucontrol)
  1704. {
  1705. int rc = 0;
  1706. switch (ucontrol->value.integer.value[0]) {
  1707. case 3:
  1708. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1709. break;
  1710. case 2:
  1711. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1712. break;
  1713. case 1:
  1714. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1715. break;
  1716. case 0:
  1717. default:
  1718. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1719. break;
  1720. }
  1721. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1722. __func__, usb_tx_cfg.bit_format,
  1723. ucontrol->value.integer.value[0]);
  1724. return rc;
  1725. }
  1726. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1727. struct snd_ctl_elem_value *ucontrol)
  1728. {
  1729. pr_debug("%s: proxy_rx channels = %d\n",
  1730. __func__, proxy_rx_cfg.channels);
  1731. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1732. return 0;
  1733. }
  1734. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1735. struct snd_ctl_elem_value *ucontrol)
  1736. {
  1737. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1738. pr_debug("%s: proxy_rx channels = %d\n",
  1739. __func__, proxy_rx_cfg.channels);
  1740. return 1;
  1741. }
  1742. static int tdm_get_sample_rate(int value)
  1743. {
  1744. int sample_rate = 0;
  1745. switch (value) {
  1746. case 0:
  1747. sample_rate = SAMPLING_RATE_8KHZ;
  1748. break;
  1749. case 1:
  1750. sample_rate = SAMPLING_RATE_16KHZ;
  1751. break;
  1752. case 2:
  1753. sample_rate = SAMPLING_RATE_32KHZ;
  1754. break;
  1755. case 3:
  1756. sample_rate = SAMPLING_RATE_48KHZ;
  1757. break;
  1758. case 4:
  1759. sample_rate = SAMPLING_RATE_176P4KHZ;
  1760. break;
  1761. case 5:
  1762. sample_rate = SAMPLING_RATE_352P8KHZ;
  1763. break;
  1764. default:
  1765. sample_rate = SAMPLING_RATE_48KHZ;
  1766. break;
  1767. }
  1768. return sample_rate;
  1769. }
  1770. static int aux_pcm_get_sample_rate(int value)
  1771. {
  1772. int sample_rate;
  1773. switch (value) {
  1774. case 1:
  1775. sample_rate = SAMPLING_RATE_16KHZ;
  1776. break;
  1777. case 0:
  1778. default:
  1779. sample_rate = SAMPLING_RATE_8KHZ;
  1780. break;
  1781. }
  1782. return sample_rate;
  1783. }
  1784. static int tdm_get_sample_rate_val(int sample_rate)
  1785. {
  1786. int sample_rate_val = 0;
  1787. switch (sample_rate) {
  1788. case SAMPLING_RATE_8KHZ:
  1789. sample_rate_val = 0;
  1790. break;
  1791. case SAMPLING_RATE_16KHZ:
  1792. sample_rate_val = 1;
  1793. break;
  1794. case SAMPLING_RATE_32KHZ:
  1795. sample_rate_val = 2;
  1796. break;
  1797. case SAMPLING_RATE_48KHZ:
  1798. sample_rate_val = 3;
  1799. break;
  1800. case SAMPLING_RATE_176P4KHZ:
  1801. sample_rate_val = 4;
  1802. break;
  1803. case SAMPLING_RATE_352P8KHZ:
  1804. sample_rate_val = 5;
  1805. break;
  1806. default:
  1807. sample_rate_val = 3;
  1808. break;
  1809. }
  1810. return sample_rate_val;
  1811. }
  1812. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1813. {
  1814. int sample_rate_val;
  1815. switch (sample_rate) {
  1816. case SAMPLING_RATE_16KHZ:
  1817. sample_rate_val = 1;
  1818. break;
  1819. case SAMPLING_RATE_8KHZ:
  1820. default:
  1821. sample_rate_val = 0;
  1822. break;
  1823. }
  1824. return sample_rate_val;
  1825. }
  1826. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1827. struct tdm_port *port)
  1828. {
  1829. if (port) {
  1830. if (strnstr(kcontrol->id.name, "PRI",
  1831. sizeof(kcontrol->id.name))) {
  1832. port->mode = TDM_PRI;
  1833. } else if (strnstr(kcontrol->id.name, "SEC",
  1834. sizeof(kcontrol->id.name))) {
  1835. port->mode = TDM_SEC;
  1836. } else if (strnstr(kcontrol->id.name, "TERT",
  1837. sizeof(kcontrol->id.name))) {
  1838. port->mode = TDM_TERT;
  1839. } else if (strnstr(kcontrol->id.name, "QUAT",
  1840. sizeof(kcontrol->id.name))) {
  1841. port->mode = TDM_QUAT;
  1842. } else if (strnstr(kcontrol->id.name, "QUIN",
  1843. sizeof(kcontrol->id.name))) {
  1844. port->mode = TDM_QUIN;
  1845. } else {
  1846. pr_err("%s: unsupported mode in: %s",
  1847. __func__, kcontrol->id.name);
  1848. return -EINVAL;
  1849. }
  1850. if (strnstr(kcontrol->id.name, "RX_0",
  1851. sizeof(kcontrol->id.name)) ||
  1852. strnstr(kcontrol->id.name, "TX_0",
  1853. sizeof(kcontrol->id.name))) {
  1854. port->channel = TDM_0;
  1855. } else if (strnstr(kcontrol->id.name, "RX_1",
  1856. sizeof(kcontrol->id.name)) ||
  1857. strnstr(kcontrol->id.name, "TX_1",
  1858. sizeof(kcontrol->id.name))) {
  1859. port->channel = TDM_1;
  1860. } else if (strnstr(kcontrol->id.name, "RX_2",
  1861. sizeof(kcontrol->id.name)) ||
  1862. strnstr(kcontrol->id.name, "TX_2",
  1863. sizeof(kcontrol->id.name))) {
  1864. port->channel = TDM_2;
  1865. } else if (strnstr(kcontrol->id.name, "RX_3",
  1866. sizeof(kcontrol->id.name)) ||
  1867. strnstr(kcontrol->id.name, "TX_3",
  1868. sizeof(kcontrol->id.name))) {
  1869. port->channel = TDM_3;
  1870. } else if (strnstr(kcontrol->id.name, "RX_4",
  1871. sizeof(kcontrol->id.name)) ||
  1872. strnstr(kcontrol->id.name, "TX_4",
  1873. sizeof(kcontrol->id.name))) {
  1874. port->channel = TDM_4;
  1875. } else if (strnstr(kcontrol->id.name, "RX_5",
  1876. sizeof(kcontrol->id.name)) ||
  1877. strnstr(kcontrol->id.name, "TX_5",
  1878. sizeof(kcontrol->id.name))) {
  1879. port->channel = TDM_5;
  1880. } else if (strnstr(kcontrol->id.name, "RX_6",
  1881. sizeof(kcontrol->id.name)) ||
  1882. strnstr(kcontrol->id.name, "TX_6",
  1883. sizeof(kcontrol->id.name))) {
  1884. port->channel = TDM_6;
  1885. } else if (strnstr(kcontrol->id.name, "RX_7",
  1886. sizeof(kcontrol->id.name)) ||
  1887. strnstr(kcontrol->id.name, "TX_7",
  1888. sizeof(kcontrol->id.name))) {
  1889. port->channel = TDM_7;
  1890. } else {
  1891. pr_err("%s: unsupported channel in: %s",
  1892. __func__, kcontrol->id.name);
  1893. return -EINVAL;
  1894. }
  1895. } else
  1896. return -EINVAL;
  1897. return 0;
  1898. }
  1899. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1900. struct snd_ctl_elem_value *ucontrol)
  1901. {
  1902. struct tdm_port port;
  1903. int ret = tdm_get_port_idx(kcontrol, &port);
  1904. if (ret) {
  1905. pr_err("%s: unsupported control: %s",
  1906. __func__, kcontrol->id.name);
  1907. } else {
  1908. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1909. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1910. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1911. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1912. ucontrol->value.enumerated.item[0]);
  1913. }
  1914. return ret;
  1915. }
  1916. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1917. struct snd_ctl_elem_value *ucontrol)
  1918. {
  1919. struct tdm_port port;
  1920. int ret = tdm_get_port_idx(kcontrol, &port);
  1921. if (ret) {
  1922. pr_err("%s: unsupported control: %s",
  1923. __func__, kcontrol->id.name);
  1924. } else {
  1925. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1926. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1927. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1928. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1929. ucontrol->value.enumerated.item[0]);
  1930. }
  1931. return ret;
  1932. }
  1933. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1934. struct snd_ctl_elem_value *ucontrol)
  1935. {
  1936. struct tdm_port port;
  1937. int ret = tdm_get_port_idx(kcontrol, &port);
  1938. if (ret) {
  1939. pr_err("%s: unsupported control: %s",
  1940. __func__, kcontrol->id.name);
  1941. } else {
  1942. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1943. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1944. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1945. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1946. ucontrol->value.enumerated.item[0]);
  1947. }
  1948. return ret;
  1949. }
  1950. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1951. struct snd_ctl_elem_value *ucontrol)
  1952. {
  1953. struct tdm_port port;
  1954. int ret = tdm_get_port_idx(kcontrol, &port);
  1955. if (ret) {
  1956. pr_err("%s: unsupported control: %s",
  1957. __func__, kcontrol->id.name);
  1958. } else {
  1959. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1960. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1961. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1962. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1963. ucontrol->value.enumerated.item[0]);
  1964. }
  1965. return ret;
  1966. }
  1967. static int tdm_get_format(int value)
  1968. {
  1969. int format = 0;
  1970. switch (value) {
  1971. case 0:
  1972. format = SNDRV_PCM_FORMAT_S16_LE;
  1973. break;
  1974. case 1:
  1975. format = SNDRV_PCM_FORMAT_S24_LE;
  1976. break;
  1977. case 2:
  1978. format = SNDRV_PCM_FORMAT_S32_LE;
  1979. break;
  1980. default:
  1981. format = SNDRV_PCM_FORMAT_S16_LE;
  1982. break;
  1983. }
  1984. return format;
  1985. }
  1986. static int tdm_get_format_val(int format)
  1987. {
  1988. int value = 0;
  1989. switch (format) {
  1990. case SNDRV_PCM_FORMAT_S16_LE:
  1991. value = 0;
  1992. break;
  1993. case SNDRV_PCM_FORMAT_S24_LE:
  1994. value = 1;
  1995. break;
  1996. case SNDRV_PCM_FORMAT_S32_LE:
  1997. value = 2;
  1998. break;
  1999. default:
  2000. value = 0;
  2001. break;
  2002. }
  2003. return value;
  2004. }
  2005. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2006. struct snd_ctl_elem_value *ucontrol)
  2007. {
  2008. struct tdm_port port;
  2009. int ret = tdm_get_port_idx(kcontrol, &port);
  2010. if (ret) {
  2011. pr_err("%s: unsupported control: %s",
  2012. __func__, kcontrol->id.name);
  2013. } else {
  2014. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2015. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2016. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2017. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2018. ucontrol->value.enumerated.item[0]);
  2019. }
  2020. return ret;
  2021. }
  2022. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2023. struct snd_ctl_elem_value *ucontrol)
  2024. {
  2025. struct tdm_port port;
  2026. int ret = tdm_get_port_idx(kcontrol, &port);
  2027. if (ret) {
  2028. pr_err("%s: unsupported control: %s",
  2029. __func__, kcontrol->id.name);
  2030. } else {
  2031. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2032. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2033. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2034. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2035. ucontrol->value.enumerated.item[0]);
  2036. }
  2037. return ret;
  2038. }
  2039. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2040. struct snd_ctl_elem_value *ucontrol)
  2041. {
  2042. struct tdm_port port;
  2043. int ret = tdm_get_port_idx(kcontrol, &port);
  2044. if (ret) {
  2045. pr_err("%s: unsupported control: %s",
  2046. __func__, kcontrol->id.name);
  2047. } else {
  2048. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2049. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2050. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2051. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2052. ucontrol->value.enumerated.item[0]);
  2053. }
  2054. return ret;
  2055. }
  2056. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2057. struct snd_ctl_elem_value *ucontrol)
  2058. {
  2059. struct tdm_port port;
  2060. int ret = tdm_get_port_idx(kcontrol, &port);
  2061. if (ret) {
  2062. pr_err("%s: unsupported control: %s",
  2063. __func__, kcontrol->id.name);
  2064. } else {
  2065. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2066. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2067. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2068. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2069. ucontrol->value.enumerated.item[0]);
  2070. }
  2071. return ret;
  2072. }
  2073. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2074. struct snd_ctl_elem_value *ucontrol)
  2075. {
  2076. struct tdm_port port;
  2077. int ret = tdm_get_port_idx(kcontrol, &port);
  2078. if (ret) {
  2079. pr_err("%s: unsupported control: %s",
  2080. __func__, kcontrol->id.name);
  2081. } else {
  2082. ucontrol->value.enumerated.item[0] =
  2083. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2084. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2085. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2086. ucontrol->value.enumerated.item[0]);
  2087. }
  2088. return ret;
  2089. }
  2090. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2091. struct snd_ctl_elem_value *ucontrol)
  2092. {
  2093. struct tdm_port port;
  2094. int ret = tdm_get_port_idx(kcontrol, &port);
  2095. if (ret) {
  2096. pr_err("%s: unsupported control: %s",
  2097. __func__, kcontrol->id.name);
  2098. } else {
  2099. tdm_rx_cfg[port.mode][port.channel].channels =
  2100. ucontrol->value.enumerated.item[0] + 1;
  2101. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2102. tdm_rx_cfg[port.mode][port.channel].channels,
  2103. ucontrol->value.enumerated.item[0] + 1);
  2104. }
  2105. return ret;
  2106. }
  2107. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2108. struct snd_ctl_elem_value *ucontrol)
  2109. {
  2110. struct tdm_port port;
  2111. int ret = tdm_get_port_idx(kcontrol, &port);
  2112. if (ret) {
  2113. pr_err("%s: unsupported control: %s",
  2114. __func__, kcontrol->id.name);
  2115. } else {
  2116. ucontrol->value.enumerated.item[0] =
  2117. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2118. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2119. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2120. ucontrol->value.enumerated.item[0]);
  2121. }
  2122. return ret;
  2123. }
  2124. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2125. struct snd_ctl_elem_value *ucontrol)
  2126. {
  2127. struct tdm_port port;
  2128. int ret = tdm_get_port_idx(kcontrol, &port);
  2129. if (ret) {
  2130. pr_err("%s: unsupported control: %s",
  2131. __func__, kcontrol->id.name);
  2132. } else {
  2133. tdm_tx_cfg[port.mode][port.channel].channels =
  2134. ucontrol->value.enumerated.item[0] + 1;
  2135. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2136. tdm_tx_cfg[port.mode][port.channel].channels,
  2137. ucontrol->value.enumerated.item[0] + 1);
  2138. }
  2139. return ret;
  2140. }
  2141. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2142. {
  2143. int idx;
  2144. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2145. sizeof("PRIM_AUX_PCM")))
  2146. idx = PRIM_AUX_PCM;
  2147. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2148. sizeof("SEC_AUX_PCM")))
  2149. idx = SEC_AUX_PCM;
  2150. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2151. sizeof("TERT_AUX_PCM")))
  2152. idx = TERT_AUX_PCM;
  2153. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2154. sizeof("QUAT_AUX_PCM")))
  2155. idx = QUAT_AUX_PCM;
  2156. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2157. sizeof("QUIN_AUX_PCM")))
  2158. idx = QUIN_AUX_PCM;
  2159. else {
  2160. pr_err("%s: unsupported port: %s",
  2161. __func__, kcontrol->id.name);
  2162. idx = -EINVAL;
  2163. }
  2164. return idx;
  2165. }
  2166. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2167. struct snd_ctl_elem_value *ucontrol)
  2168. {
  2169. int idx = aux_pcm_get_port_idx(kcontrol);
  2170. if (idx < 0)
  2171. return idx;
  2172. aux_pcm_rx_cfg[idx].sample_rate =
  2173. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2174. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2175. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2176. ucontrol->value.enumerated.item[0]);
  2177. return 0;
  2178. }
  2179. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2180. struct snd_ctl_elem_value *ucontrol)
  2181. {
  2182. int idx = aux_pcm_get_port_idx(kcontrol);
  2183. if (idx < 0)
  2184. return idx;
  2185. ucontrol->value.enumerated.item[0] =
  2186. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2187. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2188. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2189. ucontrol->value.enumerated.item[0]);
  2190. return 0;
  2191. }
  2192. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2193. struct snd_ctl_elem_value *ucontrol)
  2194. {
  2195. int idx = aux_pcm_get_port_idx(kcontrol);
  2196. if (idx < 0)
  2197. return idx;
  2198. aux_pcm_tx_cfg[idx].sample_rate =
  2199. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2200. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2201. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2202. ucontrol->value.enumerated.item[0]);
  2203. return 0;
  2204. }
  2205. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2206. struct snd_ctl_elem_value *ucontrol)
  2207. {
  2208. int idx = aux_pcm_get_port_idx(kcontrol);
  2209. if (idx < 0)
  2210. return idx;
  2211. ucontrol->value.enumerated.item[0] =
  2212. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2213. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2214. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2215. ucontrol->value.enumerated.item[0]);
  2216. return 0;
  2217. }
  2218. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2219. {
  2220. int idx;
  2221. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2222. sizeof("PRIM_MI2S_RX")))
  2223. idx = PRIM_MI2S;
  2224. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2225. sizeof("SEC_MI2S_RX")))
  2226. idx = SEC_MI2S;
  2227. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2228. sizeof("TERT_MI2S_RX")))
  2229. idx = TERT_MI2S;
  2230. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2231. sizeof("QUAT_MI2S_RX")))
  2232. idx = QUAT_MI2S;
  2233. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2234. sizeof("QUIN_MI2S_RX")))
  2235. idx = QUIN_MI2S;
  2236. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2237. sizeof("PRIM_MI2S_TX")))
  2238. idx = PRIM_MI2S;
  2239. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2240. sizeof("SEC_MI2S_TX")))
  2241. idx = SEC_MI2S;
  2242. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2243. sizeof("TERT_MI2S_TX")))
  2244. idx = TERT_MI2S;
  2245. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2246. sizeof("QUAT_MI2S_TX")))
  2247. idx = QUAT_MI2S;
  2248. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2249. sizeof("QUIN_MI2S_TX")))
  2250. idx = QUIN_MI2S;
  2251. else {
  2252. pr_err("%s: unsupported channel: %s",
  2253. __func__, kcontrol->id.name);
  2254. idx = -EINVAL;
  2255. }
  2256. return idx;
  2257. }
  2258. static int mi2s_get_sample_rate_val(int sample_rate)
  2259. {
  2260. int sample_rate_val;
  2261. switch (sample_rate) {
  2262. case SAMPLING_RATE_8KHZ:
  2263. sample_rate_val = 0;
  2264. break;
  2265. case SAMPLING_RATE_11P025KHZ:
  2266. sample_rate_val = 1;
  2267. break;
  2268. case SAMPLING_RATE_16KHZ:
  2269. sample_rate_val = 2;
  2270. break;
  2271. case SAMPLING_RATE_22P05KHZ:
  2272. sample_rate_val = 3;
  2273. break;
  2274. case SAMPLING_RATE_32KHZ:
  2275. sample_rate_val = 4;
  2276. break;
  2277. case SAMPLING_RATE_44P1KHZ:
  2278. sample_rate_val = 5;
  2279. break;
  2280. case SAMPLING_RATE_48KHZ:
  2281. sample_rate_val = 6;
  2282. break;
  2283. case SAMPLING_RATE_96KHZ:
  2284. sample_rate_val = 7;
  2285. break;
  2286. case SAMPLING_RATE_192KHZ:
  2287. sample_rate_val = 8;
  2288. break;
  2289. default:
  2290. sample_rate_val = 6;
  2291. break;
  2292. }
  2293. return sample_rate_val;
  2294. }
  2295. static int mi2s_get_sample_rate(int value)
  2296. {
  2297. int sample_rate;
  2298. switch (value) {
  2299. case 0:
  2300. sample_rate = SAMPLING_RATE_8KHZ;
  2301. break;
  2302. case 1:
  2303. sample_rate = SAMPLING_RATE_11P025KHZ;
  2304. break;
  2305. case 2:
  2306. sample_rate = SAMPLING_RATE_16KHZ;
  2307. break;
  2308. case 3:
  2309. sample_rate = SAMPLING_RATE_22P05KHZ;
  2310. break;
  2311. case 4:
  2312. sample_rate = SAMPLING_RATE_32KHZ;
  2313. break;
  2314. case 5:
  2315. sample_rate = SAMPLING_RATE_44P1KHZ;
  2316. break;
  2317. case 6:
  2318. sample_rate = SAMPLING_RATE_48KHZ;
  2319. break;
  2320. case 7:
  2321. sample_rate = SAMPLING_RATE_96KHZ;
  2322. break;
  2323. case 8:
  2324. sample_rate = SAMPLING_RATE_192KHZ;
  2325. break;
  2326. default:
  2327. sample_rate = SAMPLING_RATE_48KHZ;
  2328. break;
  2329. }
  2330. return sample_rate;
  2331. }
  2332. static int mi2s_auxpcm_get_format(int value)
  2333. {
  2334. int format;
  2335. switch (value) {
  2336. case 0:
  2337. format = SNDRV_PCM_FORMAT_S16_LE;
  2338. break;
  2339. case 1:
  2340. format = SNDRV_PCM_FORMAT_S24_LE;
  2341. break;
  2342. case 2:
  2343. format = SNDRV_PCM_FORMAT_S24_3LE;
  2344. break;
  2345. case 3:
  2346. format = SNDRV_PCM_FORMAT_S32_LE;
  2347. break;
  2348. default:
  2349. format = SNDRV_PCM_FORMAT_S16_LE;
  2350. break;
  2351. }
  2352. return format;
  2353. }
  2354. static int mi2s_auxpcm_get_format_value(int format)
  2355. {
  2356. int value;
  2357. switch (format) {
  2358. case SNDRV_PCM_FORMAT_S16_LE:
  2359. value = 0;
  2360. break;
  2361. case SNDRV_PCM_FORMAT_S24_LE:
  2362. value = 1;
  2363. break;
  2364. case SNDRV_PCM_FORMAT_S24_3LE:
  2365. value = 2;
  2366. break;
  2367. case SNDRV_PCM_FORMAT_S32_LE:
  2368. value = 3;
  2369. break;
  2370. default:
  2371. value = 0;
  2372. break;
  2373. }
  2374. return value;
  2375. }
  2376. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2377. struct snd_ctl_elem_value *ucontrol)
  2378. {
  2379. int idx = mi2s_get_port_idx(kcontrol);
  2380. if (idx < 0)
  2381. return idx;
  2382. mi2s_rx_cfg[idx].sample_rate =
  2383. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2384. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2385. idx, mi2s_rx_cfg[idx].sample_rate,
  2386. ucontrol->value.enumerated.item[0]);
  2387. return 0;
  2388. }
  2389. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2390. struct snd_ctl_elem_value *ucontrol)
  2391. {
  2392. int idx = mi2s_get_port_idx(kcontrol);
  2393. if (idx < 0)
  2394. return idx;
  2395. ucontrol->value.enumerated.item[0] =
  2396. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2397. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2398. idx, mi2s_rx_cfg[idx].sample_rate,
  2399. ucontrol->value.enumerated.item[0]);
  2400. return 0;
  2401. }
  2402. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2403. struct snd_ctl_elem_value *ucontrol)
  2404. {
  2405. int idx = mi2s_get_port_idx(kcontrol);
  2406. if (idx < 0)
  2407. return idx;
  2408. mi2s_tx_cfg[idx].sample_rate =
  2409. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2410. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2411. idx, mi2s_tx_cfg[idx].sample_rate,
  2412. ucontrol->value.enumerated.item[0]);
  2413. return 0;
  2414. }
  2415. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2416. struct snd_ctl_elem_value *ucontrol)
  2417. {
  2418. int idx = mi2s_get_port_idx(kcontrol);
  2419. if (idx < 0)
  2420. return idx;
  2421. ucontrol->value.enumerated.item[0] =
  2422. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2423. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2424. idx, mi2s_tx_cfg[idx].sample_rate,
  2425. ucontrol->value.enumerated.item[0]);
  2426. return 0;
  2427. }
  2428. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2429. struct snd_ctl_elem_value *ucontrol)
  2430. {
  2431. int idx = mi2s_get_port_idx(kcontrol);
  2432. if (idx < 0)
  2433. return idx;
  2434. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2435. idx, mi2s_rx_cfg[idx].channels);
  2436. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2437. return 0;
  2438. }
  2439. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2440. struct snd_ctl_elem_value *ucontrol)
  2441. {
  2442. int idx = mi2s_get_port_idx(kcontrol);
  2443. if (idx < 0)
  2444. return idx;
  2445. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2446. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2447. idx, mi2s_rx_cfg[idx].channels);
  2448. return 1;
  2449. }
  2450. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2451. struct snd_ctl_elem_value *ucontrol)
  2452. {
  2453. int idx = mi2s_get_port_idx(kcontrol);
  2454. if (idx < 0)
  2455. return idx;
  2456. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2457. idx, mi2s_tx_cfg[idx].channels);
  2458. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2459. return 0;
  2460. }
  2461. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2462. struct snd_ctl_elem_value *ucontrol)
  2463. {
  2464. int idx = mi2s_get_port_idx(kcontrol);
  2465. if (idx < 0)
  2466. return idx;
  2467. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2468. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2469. idx, mi2s_tx_cfg[idx].channels);
  2470. return 1;
  2471. }
  2472. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2473. struct snd_ctl_elem_value *ucontrol)
  2474. {
  2475. int idx = mi2s_get_port_idx(kcontrol);
  2476. if (idx < 0)
  2477. return idx;
  2478. ucontrol->value.enumerated.item[0] =
  2479. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2480. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2481. idx, mi2s_rx_cfg[idx].bit_format,
  2482. ucontrol->value.enumerated.item[0]);
  2483. return 0;
  2484. }
  2485. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2486. struct snd_ctl_elem_value *ucontrol)
  2487. {
  2488. int idx = mi2s_get_port_idx(kcontrol);
  2489. if (idx < 0)
  2490. return idx;
  2491. mi2s_rx_cfg[idx].bit_format =
  2492. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2493. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2494. idx, mi2s_rx_cfg[idx].bit_format,
  2495. ucontrol->value.enumerated.item[0]);
  2496. return 0;
  2497. }
  2498. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2499. struct snd_ctl_elem_value *ucontrol)
  2500. {
  2501. int idx = mi2s_get_port_idx(kcontrol);
  2502. if (idx < 0)
  2503. return idx;
  2504. ucontrol->value.enumerated.item[0] =
  2505. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2506. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2507. idx, mi2s_tx_cfg[idx].bit_format,
  2508. ucontrol->value.enumerated.item[0]);
  2509. return 0;
  2510. }
  2511. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2512. struct snd_ctl_elem_value *ucontrol)
  2513. {
  2514. int idx = mi2s_get_port_idx(kcontrol);
  2515. if (idx < 0)
  2516. return idx;
  2517. mi2s_tx_cfg[idx].bit_format =
  2518. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2519. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2520. idx, mi2s_tx_cfg[idx].bit_format,
  2521. ucontrol->value.enumerated.item[0]);
  2522. return 0;
  2523. }
  2524. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2525. struct snd_ctl_elem_value *ucontrol)
  2526. {
  2527. int idx = aux_pcm_get_port_idx(kcontrol);
  2528. if (idx < 0)
  2529. return idx;
  2530. ucontrol->value.enumerated.item[0] =
  2531. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2532. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2533. idx, aux_pcm_rx_cfg[idx].bit_format,
  2534. ucontrol->value.enumerated.item[0]);
  2535. return 0;
  2536. }
  2537. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2538. struct snd_ctl_elem_value *ucontrol)
  2539. {
  2540. int idx = aux_pcm_get_port_idx(kcontrol);
  2541. if (idx < 0)
  2542. return idx;
  2543. aux_pcm_rx_cfg[idx].bit_format =
  2544. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2545. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2546. idx, aux_pcm_rx_cfg[idx].bit_format,
  2547. ucontrol->value.enumerated.item[0]);
  2548. return 0;
  2549. }
  2550. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2551. struct snd_ctl_elem_value *ucontrol)
  2552. {
  2553. int idx = aux_pcm_get_port_idx(kcontrol);
  2554. if (idx < 0)
  2555. return idx;
  2556. ucontrol->value.enumerated.item[0] =
  2557. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2558. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2559. idx, aux_pcm_tx_cfg[idx].bit_format,
  2560. ucontrol->value.enumerated.item[0]);
  2561. return 0;
  2562. }
  2563. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2564. struct snd_ctl_elem_value *ucontrol)
  2565. {
  2566. int idx = aux_pcm_get_port_idx(kcontrol);
  2567. if (idx < 0)
  2568. return idx;
  2569. aux_pcm_tx_cfg[idx].bit_format =
  2570. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2571. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2572. idx, aux_pcm_tx_cfg[idx].bit_format,
  2573. ucontrol->value.enumerated.item[0]);
  2574. return 0;
  2575. }
  2576. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2577. {
  2578. int idx;
  2579. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2580. sizeof("PRIM_SPDIF_RX")))
  2581. idx = PRIM_SPDIF_RX;
  2582. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2583. sizeof("SEC_SPDIF_RX")))
  2584. idx = SEC_SPDIF_RX;
  2585. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2586. sizeof("PRIM_SPDIF_TX")))
  2587. idx = PRIM_SPDIF_TX;
  2588. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2589. sizeof("SEC_SPDIF_TX")))
  2590. idx = SEC_SPDIF_TX;
  2591. else {
  2592. pr_err("%s: unsupported channel: %s",
  2593. __func__, kcontrol->id.name);
  2594. idx = -EINVAL;
  2595. }
  2596. return idx;
  2597. }
  2598. static int spdif_get_sample_rate_val(int sample_rate)
  2599. {
  2600. int sample_rate_val;
  2601. switch (sample_rate) {
  2602. case SAMPLING_RATE_32KHZ:
  2603. sample_rate_val = 0;
  2604. break;
  2605. case SAMPLING_RATE_44P1KHZ:
  2606. sample_rate_val = 1;
  2607. break;
  2608. case SAMPLING_RATE_48KHZ:
  2609. sample_rate_val = 2;
  2610. break;
  2611. case SAMPLING_RATE_88P2KHZ:
  2612. sample_rate_val = 3;
  2613. break;
  2614. case SAMPLING_RATE_96KHZ:
  2615. sample_rate_val = 4;
  2616. break;
  2617. case SAMPLING_RATE_176P4KHZ:
  2618. sample_rate_val = 5;
  2619. break;
  2620. case SAMPLING_RATE_192KHZ:
  2621. sample_rate_val = 6;
  2622. break;
  2623. default:
  2624. sample_rate_val = 2;
  2625. break;
  2626. }
  2627. return sample_rate_val;
  2628. }
  2629. static int spdif_get_sample_rate(int value)
  2630. {
  2631. int sample_rate;
  2632. switch (value) {
  2633. case 0:
  2634. sample_rate = SAMPLING_RATE_32KHZ;
  2635. break;
  2636. case 1:
  2637. sample_rate = SAMPLING_RATE_44P1KHZ;
  2638. break;
  2639. case 2:
  2640. sample_rate = SAMPLING_RATE_48KHZ;
  2641. break;
  2642. case 3:
  2643. sample_rate = SAMPLING_RATE_88P2KHZ;
  2644. break;
  2645. case 4:
  2646. sample_rate = SAMPLING_RATE_96KHZ;
  2647. break;
  2648. case 5:
  2649. sample_rate = SAMPLING_RATE_176P4KHZ;
  2650. break;
  2651. case 6:
  2652. sample_rate = SAMPLING_RATE_192KHZ;
  2653. break;
  2654. default:
  2655. sample_rate = SAMPLING_RATE_48KHZ;
  2656. break;
  2657. }
  2658. return sample_rate;
  2659. }
  2660. static int spdif_get_format(int value)
  2661. {
  2662. int format;
  2663. switch (value) {
  2664. case 0:
  2665. format = SNDRV_PCM_FORMAT_S16_LE;
  2666. break;
  2667. case 1:
  2668. format = SNDRV_PCM_FORMAT_S24_LE;
  2669. break;
  2670. default:
  2671. format = SNDRV_PCM_FORMAT_S16_LE;
  2672. break;
  2673. }
  2674. return format;
  2675. }
  2676. static int spdif_get_format_value(int format)
  2677. {
  2678. int value;
  2679. switch (format) {
  2680. case SNDRV_PCM_FORMAT_S16_LE:
  2681. value = 0;
  2682. break;
  2683. case SNDRV_PCM_FORMAT_S24_LE:
  2684. value = 1;
  2685. break;
  2686. default:
  2687. value = 0;
  2688. break;
  2689. }
  2690. return value;
  2691. }
  2692. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2693. struct snd_ctl_elem_value *ucontrol)
  2694. {
  2695. int idx = spdif_get_port_idx(kcontrol);
  2696. if (idx < 0)
  2697. return idx;
  2698. spdif_rx_cfg[idx].sample_rate =
  2699. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2700. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2701. idx, spdif_rx_cfg[idx].sample_rate,
  2702. ucontrol->value.enumerated.item[0]);
  2703. return 0;
  2704. }
  2705. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2706. struct snd_ctl_elem_value *ucontrol)
  2707. {
  2708. int idx = spdif_get_port_idx(kcontrol);
  2709. if (idx < 0)
  2710. return idx;
  2711. ucontrol->value.enumerated.item[0] =
  2712. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2713. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2714. idx, spdif_rx_cfg[idx].sample_rate,
  2715. ucontrol->value.enumerated.item[0]);
  2716. return 0;
  2717. }
  2718. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2719. struct snd_ctl_elem_value *ucontrol)
  2720. {
  2721. int idx = spdif_get_port_idx(kcontrol);
  2722. if (idx < 0)
  2723. return idx;
  2724. spdif_tx_cfg[idx].sample_rate =
  2725. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2726. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2727. idx, spdif_tx_cfg[idx].sample_rate,
  2728. ucontrol->value.enumerated.item[0]);
  2729. return 0;
  2730. }
  2731. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2732. struct snd_ctl_elem_value *ucontrol)
  2733. {
  2734. int idx = spdif_get_port_idx(kcontrol);
  2735. if (idx < 0)
  2736. return idx;
  2737. ucontrol->value.enumerated.item[0] =
  2738. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2739. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2740. idx, spdif_tx_cfg[idx].sample_rate,
  2741. ucontrol->value.enumerated.item[0]);
  2742. return 0;
  2743. }
  2744. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2745. struct snd_ctl_elem_value *ucontrol)
  2746. {
  2747. int idx = spdif_get_port_idx(kcontrol);
  2748. if (idx < 0)
  2749. return idx;
  2750. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2751. idx, spdif_rx_cfg[idx].channels);
  2752. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2753. return 0;
  2754. }
  2755. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2756. struct snd_ctl_elem_value *ucontrol)
  2757. {
  2758. int idx = spdif_get_port_idx(kcontrol);
  2759. if (idx < 0)
  2760. return idx;
  2761. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2762. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2763. idx, spdif_rx_cfg[idx].channels);
  2764. return 1;
  2765. }
  2766. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2767. struct snd_ctl_elem_value *ucontrol)
  2768. {
  2769. int idx = spdif_get_port_idx(kcontrol);
  2770. if (idx < 0)
  2771. return idx;
  2772. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2773. idx, spdif_tx_cfg[idx].channels);
  2774. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2775. return 0;
  2776. }
  2777. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2778. struct snd_ctl_elem_value *ucontrol)
  2779. {
  2780. int idx = spdif_get_port_idx(kcontrol);
  2781. if (idx < 0)
  2782. return idx;
  2783. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2784. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2785. idx, spdif_tx_cfg[idx].channels);
  2786. return 1;
  2787. }
  2788. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2789. struct snd_ctl_elem_value *ucontrol)
  2790. {
  2791. int idx = spdif_get_port_idx(kcontrol);
  2792. if (idx < 0)
  2793. return idx;
  2794. ucontrol->value.enumerated.item[0] =
  2795. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2796. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2797. idx, spdif_rx_cfg[idx].bit_format,
  2798. ucontrol->value.enumerated.item[0]);
  2799. return 0;
  2800. }
  2801. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2802. struct snd_ctl_elem_value *ucontrol)
  2803. {
  2804. int idx = spdif_get_port_idx(kcontrol);
  2805. if (idx < 0)
  2806. return idx;
  2807. spdif_rx_cfg[idx].bit_format =
  2808. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2809. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2810. idx, spdif_rx_cfg[idx].bit_format,
  2811. ucontrol->value.enumerated.item[0]);
  2812. return 0;
  2813. }
  2814. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2815. struct snd_ctl_elem_value *ucontrol)
  2816. {
  2817. int idx = spdif_get_port_idx(kcontrol);
  2818. if (idx < 0)
  2819. return idx;
  2820. ucontrol->value.enumerated.item[0] =
  2821. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2822. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2823. idx, spdif_tx_cfg[idx].bit_format,
  2824. ucontrol->value.enumerated.item[0]);
  2825. return 0;
  2826. }
  2827. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2828. struct snd_ctl_elem_value *ucontrol)
  2829. {
  2830. int idx = spdif_get_port_idx(kcontrol);
  2831. if (idx < 0)
  2832. return idx;
  2833. spdif_tx_cfg[idx].bit_format =
  2834. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2835. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2836. idx, spdif_tx_cfg[idx].bit_format,
  2837. ucontrol->value.enumerated.item[0]);
  2838. return 0;
  2839. }
  2840. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2841. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2842. slim_rx_ch_get, slim_rx_ch_put),
  2843. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2844. slim_rx_ch_get, slim_rx_ch_put),
  2845. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2846. slim_tx_ch_get, slim_tx_ch_put),
  2847. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2848. slim_tx_ch_get, slim_tx_ch_put),
  2849. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2850. slim_rx_ch_get, slim_rx_ch_put),
  2851. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2852. slim_rx_ch_get, slim_rx_ch_put),
  2853. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2854. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2855. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2856. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2857. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2858. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2859. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2860. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2861. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2862. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2863. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2864. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2865. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2866. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2867. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2868. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2869. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2870. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2871. };
  2872. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2873. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2874. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2875. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2876. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2877. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2878. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2879. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2880. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2881. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2882. va_cdc_dma_tx_0_sample_rate,
  2883. cdc_dma_tx_sample_rate_get,
  2884. cdc_dma_tx_sample_rate_put),
  2885. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2886. va_cdc_dma_tx_1_sample_rate,
  2887. cdc_dma_tx_sample_rate_get,
  2888. cdc_dma_tx_sample_rate_put),
  2889. };
  2890. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2891. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2892. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2893. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2894. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2895. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2896. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2897. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2898. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2899. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2900. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2901. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2902. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2903. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2904. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2905. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2906. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2907. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2908. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2909. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2910. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2911. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2912. wsa_cdc_dma_rx_0_sample_rate,
  2913. cdc_dma_rx_sample_rate_get,
  2914. cdc_dma_rx_sample_rate_put),
  2915. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2916. wsa_cdc_dma_rx_1_sample_rate,
  2917. cdc_dma_rx_sample_rate_get,
  2918. cdc_dma_rx_sample_rate_put),
  2919. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2920. wsa_cdc_dma_tx_0_sample_rate,
  2921. cdc_dma_tx_sample_rate_get,
  2922. cdc_dma_tx_sample_rate_put),
  2923. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2924. wsa_cdc_dma_tx_1_sample_rate,
  2925. cdc_dma_tx_sample_rate_get,
  2926. cdc_dma_tx_sample_rate_put),
  2927. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2928. wsa_cdc_dma_tx_2_sample_rate,
  2929. cdc_dma_tx_sample_rate_get,
  2930. cdc_dma_tx_sample_rate_put),
  2931. };
  2932. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2933. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2934. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2935. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2936. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2937. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2938. proxy_rx_ch_get, proxy_rx_ch_put),
  2939. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2940. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2941. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2942. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2943. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2944. msm_bt_sample_rate_get,
  2945. msm_bt_sample_rate_put),
  2946. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2947. usb_audio_rx_sample_rate_get,
  2948. usb_audio_rx_sample_rate_put),
  2949. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2950. usb_audio_tx_sample_rate_get,
  2951. usb_audio_tx_sample_rate_put),
  2952. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2953. tdm_rx_sample_rate_get,
  2954. tdm_rx_sample_rate_put),
  2955. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2956. tdm_tx_sample_rate_get,
  2957. tdm_tx_sample_rate_put),
  2958. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2959. tdm_rx_format_get,
  2960. tdm_rx_format_put),
  2961. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2962. tdm_tx_format_get,
  2963. tdm_tx_format_put),
  2964. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2965. tdm_rx_ch_get,
  2966. tdm_rx_ch_put),
  2967. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2968. tdm_tx_ch_get,
  2969. tdm_tx_ch_put),
  2970. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2971. tdm_rx_sample_rate_get,
  2972. tdm_rx_sample_rate_put),
  2973. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2974. tdm_tx_sample_rate_get,
  2975. tdm_tx_sample_rate_put),
  2976. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2977. tdm_rx_format_get,
  2978. tdm_rx_format_put),
  2979. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2980. tdm_tx_format_get,
  2981. tdm_tx_format_put),
  2982. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2983. tdm_rx_ch_get,
  2984. tdm_rx_ch_put),
  2985. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2986. tdm_tx_ch_get,
  2987. tdm_tx_ch_put),
  2988. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2989. tdm_rx_sample_rate_get,
  2990. tdm_rx_sample_rate_put),
  2991. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2992. tdm_tx_sample_rate_get,
  2993. tdm_tx_sample_rate_put),
  2994. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2995. tdm_rx_format_get,
  2996. tdm_rx_format_put),
  2997. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2998. tdm_tx_format_get,
  2999. tdm_tx_format_put),
  3000. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3001. tdm_rx_ch_get,
  3002. tdm_rx_ch_put),
  3003. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3004. tdm_tx_ch_get,
  3005. tdm_tx_ch_put),
  3006. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3007. tdm_rx_sample_rate_get,
  3008. tdm_rx_sample_rate_put),
  3009. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3010. tdm_tx_sample_rate_get,
  3011. tdm_tx_sample_rate_put),
  3012. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3013. tdm_rx_format_get,
  3014. tdm_rx_format_put),
  3015. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3016. tdm_tx_format_get,
  3017. tdm_tx_format_put),
  3018. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3019. tdm_rx_ch_get,
  3020. tdm_rx_ch_put),
  3021. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3022. tdm_tx_ch_get,
  3023. tdm_tx_ch_put),
  3024. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3025. tdm_rx_sample_rate_get,
  3026. tdm_rx_sample_rate_put),
  3027. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3028. tdm_tx_sample_rate_get,
  3029. tdm_tx_sample_rate_put),
  3030. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3031. tdm_rx_format_get,
  3032. tdm_rx_format_put),
  3033. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3034. tdm_tx_format_get,
  3035. tdm_tx_format_put),
  3036. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3037. tdm_rx_ch_get,
  3038. tdm_rx_ch_put),
  3039. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3040. tdm_tx_ch_get,
  3041. tdm_tx_ch_put),
  3042. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3043. aux_pcm_rx_sample_rate_get,
  3044. aux_pcm_rx_sample_rate_put),
  3045. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3046. aux_pcm_rx_sample_rate_get,
  3047. aux_pcm_rx_sample_rate_put),
  3048. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3049. aux_pcm_rx_sample_rate_get,
  3050. aux_pcm_rx_sample_rate_put),
  3051. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3052. aux_pcm_rx_sample_rate_get,
  3053. aux_pcm_rx_sample_rate_put),
  3054. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3055. aux_pcm_rx_sample_rate_get,
  3056. aux_pcm_rx_sample_rate_put),
  3057. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3058. aux_pcm_tx_sample_rate_get,
  3059. aux_pcm_tx_sample_rate_put),
  3060. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3061. aux_pcm_tx_sample_rate_get,
  3062. aux_pcm_tx_sample_rate_put),
  3063. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3064. aux_pcm_tx_sample_rate_get,
  3065. aux_pcm_tx_sample_rate_put),
  3066. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3067. aux_pcm_tx_sample_rate_get,
  3068. aux_pcm_tx_sample_rate_put),
  3069. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3070. aux_pcm_tx_sample_rate_get,
  3071. aux_pcm_tx_sample_rate_put),
  3072. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3073. mi2s_rx_sample_rate_get,
  3074. mi2s_rx_sample_rate_put),
  3075. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3076. mi2s_rx_sample_rate_get,
  3077. mi2s_rx_sample_rate_put),
  3078. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3079. mi2s_rx_sample_rate_get,
  3080. mi2s_rx_sample_rate_put),
  3081. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3082. mi2s_rx_sample_rate_get,
  3083. mi2s_rx_sample_rate_put),
  3084. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3085. mi2s_rx_sample_rate_get,
  3086. mi2s_rx_sample_rate_put),
  3087. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3088. mi2s_tx_sample_rate_get,
  3089. mi2s_tx_sample_rate_put),
  3090. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3091. mi2s_tx_sample_rate_get,
  3092. mi2s_tx_sample_rate_put),
  3093. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3094. mi2s_tx_sample_rate_get,
  3095. mi2s_tx_sample_rate_put),
  3096. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3097. mi2s_tx_sample_rate_get,
  3098. mi2s_tx_sample_rate_put),
  3099. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3100. mi2s_tx_sample_rate_get,
  3101. mi2s_tx_sample_rate_put),
  3102. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3103. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3104. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3105. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3106. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3107. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3108. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3109. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3110. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3111. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3112. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3113. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3114. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3115. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3116. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3117. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3118. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3119. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3120. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3121. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3122. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3123. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3124. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3125. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3126. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3127. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3128. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3129. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3130. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3131. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3132. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3133. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3134. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3135. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3136. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3137. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3138. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3139. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3140. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3141. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3142. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3143. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3144. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3145. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3146. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3147. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3148. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3149. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3150. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3151. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3152. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3153. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3154. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3155. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3156. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3157. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3158. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3159. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3160. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3161. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3162. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3163. msm_snd_vad_cfg_put),
  3164. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3165. msm_spdif_rx_sample_rate_get,
  3166. msm_spdif_rx_sample_rate_put),
  3167. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3168. msm_spdif_tx_sample_rate_get,
  3169. msm_spdif_tx_sample_rate_put),
  3170. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3171. msm_spdif_rx_sample_rate_get,
  3172. msm_spdif_rx_sample_rate_put),
  3173. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3174. msm_spdif_tx_sample_rate_get,
  3175. msm_spdif_tx_sample_rate_put),
  3176. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3177. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3178. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3179. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3180. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3181. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3182. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3183. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3184. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3185. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3186. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3187. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3188. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3189. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3190. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3191. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3192. };
  3193. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  3194. int enable, bool dapm)
  3195. {
  3196. int ret = 0;
  3197. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3198. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  3199. } else {
  3200. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  3201. __func__);
  3202. ret = -EINVAL;
  3203. }
  3204. return ret;
  3205. }
  3206. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  3207. int enable, bool dapm)
  3208. {
  3209. int ret = 0;
  3210. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3211. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  3212. } else {
  3213. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  3214. __func__);
  3215. ret = -EINVAL;
  3216. }
  3217. return ret;
  3218. }
  3219. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3220. struct snd_kcontrol *kcontrol, int event)
  3221. {
  3222. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3223. pr_debug("%s: event = %d\n", __func__, event);
  3224. switch (event) {
  3225. case SND_SOC_DAPM_PRE_PMU:
  3226. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  3227. case SND_SOC_DAPM_POST_PMD:
  3228. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  3229. }
  3230. return 0;
  3231. }
  3232. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3233. struct snd_kcontrol *kcontrol, int event)
  3234. {
  3235. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3236. pr_debug("%s: event = %d\n", __func__, event);
  3237. switch (event) {
  3238. case SND_SOC_DAPM_PRE_PMU:
  3239. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  3240. case SND_SOC_DAPM_POST_PMD:
  3241. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  3242. }
  3243. return 0;
  3244. }
  3245. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3246. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3247. msm_mclk_event,
  3248. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3249. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3250. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3251. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3252. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3253. };
  3254. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3255. struct snd_kcontrol *kcontrol, int event)
  3256. {
  3257. struct msm_asoc_mach_data *pdata = NULL;
  3258. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3259. int ret = 0;
  3260. uint32_t dmic_idx;
  3261. int *dmic_gpio_cnt;
  3262. struct device_node *dmic_gpio;
  3263. char *wname;
  3264. wname = strpbrk(w->name, "01234567");
  3265. if (!wname) {
  3266. dev_err(codec->dev, "%s: widget not found\n", __func__);
  3267. return -EINVAL;
  3268. }
  3269. ret = kstrtouint(wname, 10, &dmic_idx);
  3270. if (ret < 0) {
  3271. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  3272. __func__);
  3273. return -EINVAL;
  3274. }
  3275. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3276. switch (dmic_idx) {
  3277. case 0:
  3278. case 1:
  3279. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3280. dmic_gpio = pdata->dmic_01_gpio_p;
  3281. break;
  3282. case 2:
  3283. case 3:
  3284. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3285. dmic_gpio = pdata->dmic_23_gpio_p;
  3286. break;
  3287. case 4:
  3288. case 5:
  3289. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3290. dmic_gpio = pdata->dmic_45_gpio_p;
  3291. break;
  3292. case 6:
  3293. case 7:
  3294. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3295. dmic_gpio = pdata->dmic_67_gpio_p;
  3296. break;
  3297. default:
  3298. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  3299. __func__);
  3300. return -EINVAL;
  3301. }
  3302. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3303. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3304. switch (event) {
  3305. case SND_SOC_DAPM_PRE_PMU:
  3306. (*dmic_gpio_cnt)++;
  3307. if (*dmic_gpio_cnt == 1) {
  3308. ret = msm_cdc_pinctrl_select_active_state(
  3309. dmic_gpio);
  3310. if (ret < 0) {
  3311. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  3312. __func__, "dmic_gpio");
  3313. return ret;
  3314. }
  3315. }
  3316. break;
  3317. case SND_SOC_DAPM_POST_PMD:
  3318. (*dmic_gpio_cnt)--;
  3319. if (*dmic_gpio_cnt == 0) {
  3320. ret = msm_cdc_pinctrl_select_sleep_state(
  3321. dmic_gpio);
  3322. if (ret < 0) {
  3323. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3324. __func__, "dmic_gpio");
  3325. return ret;
  3326. }
  3327. }
  3328. break;
  3329. default:
  3330. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3331. __func__, event);
  3332. return -EINVAL;
  3333. }
  3334. return 0;
  3335. }
  3336. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3337. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3338. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3339. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3340. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3341. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3342. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3343. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3344. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3345. };
  3346. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3347. };
  3348. static inline int param_is_mask(int p)
  3349. {
  3350. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3351. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3352. }
  3353. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3354. int n)
  3355. {
  3356. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3357. }
  3358. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3359. unsigned int bit)
  3360. {
  3361. if (bit >= SNDRV_MASK_MAX)
  3362. return;
  3363. if (param_is_mask(n)) {
  3364. struct snd_mask *m = param_to_mask(p, n);
  3365. m->bits[0] = 0;
  3366. m->bits[1] = 0;
  3367. m->bits[bit >> 5] |= (1 << (bit & 31));
  3368. }
  3369. }
  3370. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3371. {
  3372. int ch_id = 0;
  3373. switch (be_id) {
  3374. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3375. ch_id = SLIM_RX_0;
  3376. break;
  3377. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3378. ch_id = SLIM_RX_1;
  3379. break;
  3380. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3381. ch_id = SLIM_RX_2;
  3382. break;
  3383. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3384. ch_id = SLIM_RX_3;
  3385. break;
  3386. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3387. ch_id = SLIM_RX_4;
  3388. break;
  3389. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3390. ch_id = SLIM_RX_6;
  3391. break;
  3392. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3393. ch_id = SLIM_TX_0;
  3394. break;
  3395. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3396. ch_id = SLIM_TX_3;
  3397. break;
  3398. default:
  3399. ch_id = SLIM_RX_0;
  3400. break;
  3401. }
  3402. return ch_id;
  3403. }
  3404. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3405. {
  3406. *port_id = 0xFFFF;
  3407. switch (be_id) {
  3408. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3409. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3410. break;
  3411. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3412. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3413. break;
  3414. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3415. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3416. break;
  3417. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3418. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3419. break;
  3420. default:
  3421. return -EINVAL;
  3422. }
  3423. return 0;
  3424. }
  3425. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3426. {
  3427. int idx = 0;
  3428. switch (be_id) {
  3429. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3430. idx = WSA_CDC_DMA_RX_0;
  3431. break;
  3432. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3433. idx = WSA_CDC_DMA_TX_0;
  3434. break;
  3435. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3436. idx = WSA_CDC_DMA_RX_1;
  3437. break;
  3438. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3439. idx = WSA_CDC_DMA_TX_1;
  3440. break;
  3441. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3442. idx = WSA_CDC_DMA_TX_2;
  3443. break;
  3444. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3445. idx = VA_CDC_DMA_TX_0;
  3446. break;
  3447. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3448. idx = VA_CDC_DMA_TX_1;
  3449. break;
  3450. default:
  3451. idx = VA_CDC_DMA_TX_0;
  3452. break;
  3453. }
  3454. return idx;
  3455. }
  3456. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3457. struct snd_pcm_hw_params *params)
  3458. {
  3459. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3460. struct snd_interval *rate = hw_param_interval(params,
  3461. SNDRV_PCM_HW_PARAM_RATE);
  3462. struct snd_interval *channels = hw_param_interval(params,
  3463. SNDRV_PCM_HW_PARAM_CHANNELS);
  3464. int rc = 0;
  3465. int idx;
  3466. void *config = NULL;
  3467. struct snd_soc_codec *codec = NULL;
  3468. pr_debug("%s: format = %d, rate = %d\n",
  3469. __func__, params_format(params), params_rate(params));
  3470. switch (dai_link->id) {
  3471. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3472. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3473. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3474. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3475. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3476. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3477. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3478. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3479. slim_rx_cfg[idx].bit_format);
  3480. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3481. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3482. break;
  3483. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3484. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3485. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3486. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3487. slim_tx_cfg[idx].bit_format);
  3488. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3489. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3490. break;
  3491. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3492. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3493. slim_tx_cfg[1].bit_format);
  3494. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3495. channels->min = channels->max = slim_tx_cfg[1].channels;
  3496. break;
  3497. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3498. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3499. SNDRV_PCM_FORMAT_S32_LE);
  3500. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3501. channels->min = channels->max = msm_vi_feed_tx_ch;
  3502. break;
  3503. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3504. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3505. slim_rx_cfg[5].bit_format);
  3506. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3507. channels->min = channels->max = slim_rx_cfg[5].channels;
  3508. break;
  3509. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3510. codec = rtd->codec;
  3511. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3512. channels->min = channels->max = 1;
  3513. config = msm_codec_fn.get_afe_config_fn(codec,
  3514. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3515. if (config) {
  3516. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3517. config, SLIMBUS_5_TX);
  3518. if (rc)
  3519. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3520. __func__, rc);
  3521. }
  3522. break;
  3523. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3524. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3525. slim_rx_cfg[SLIM_RX_7].bit_format);
  3526. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3527. channels->min = channels->max =
  3528. slim_rx_cfg[SLIM_RX_7].channels;
  3529. break;
  3530. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3531. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3532. channels->min = channels->max =
  3533. slim_tx_cfg[SLIM_TX_7].channels;
  3534. break;
  3535. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3536. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3537. channels->min = channels->max =
  3538. slim_tx_cfg[SLIM_TX_8].channels;
  3539. break;
  3540. case MSM_BACKEND_DAI_USB_RX:
  3541. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3542. usb_rx_cfg.bit_format);
  3543. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3544. channels->min = channels->max = usb_rx_cfg.channels;
  3545. break;
  3546. case MSM_BACKEND_DAI_USB_TX:
  3547. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3548. usb_tx_cfg.bit_format);
  3549. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3550. channels->min = channels->max = usb_tx_cfg.channels;
  3551. break;
  3552. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3553. channels->min = channels->max = proxy_rx_cfg.channels;
  3554. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3555. break;
  3556. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3557. channels->min = channels->max =
  3558. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3559. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3560. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3561. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3562. break;
  3563. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3564. channels->min = channels->max =
  3565. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3566. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3567. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3568. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3569. break;
  3570. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3571. channels->min = channels->max =
  3572. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3573. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3574. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3575. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3576. break;
  3577. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3578. channels->min = channels->max =
  3579. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3580. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3581. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3582. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3583. break;
  3584. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3585. channels->min = channels->max =
  3586. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3587. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3588. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3589. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3590. break;
  3591. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3592. channels->min = channels->max =
  3593. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3594. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3595. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3596. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3597. break;
  3598. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3599. channels->min = channels->max =
  3600. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3601. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3602. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3603. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3604. break;
  3605. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3606. channels->min = channels->max =
  3607. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3608. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3609. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3610. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3611. break;
  3612. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3613. channels->min = channels->max =
  3614. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3615. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3616. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3617. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3618. break;
  3619. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3620. channels->min = channels->max =
  3621. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3622. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3623. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3624. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3625. break;
  3626. case MSM_BACKEND_DAI_AUXPCM_RX:
  3627. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3628. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3629. rate->min = rate->max =
  3630. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3631. channels->min = channels->max =
  3632. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3633. break;
  3634. case MSM_BACKEND_DAI_AUXPCM_TX:
  3635. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3636. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3637. rate->min = rate->max =
  3638. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3639. channels->min = channels->max =
  3640. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3641. break;
  3642. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3643. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3644. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3645. rate->min = rate->max =
  3646. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3647. channels->min = channels->max =
  3648. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3649. break;
  3650. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3651. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3652. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3653. rate->min = rate->max =
  3654. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3655. channels->min = channels->max =
  3656. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3657. break;
  3658. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3659. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3660. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3661. rate->min = rate->max =
  3662. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3663. channels->min = channels->max =
  3664. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3665. break;
  3666. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3667. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3668. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3669. rate->min = rate->max =
  3670. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3671. channels->min = channels->max =
  3672. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3673. break;
  3674. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3675. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3676. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3677. rate->min = rate->max =
  3678. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3679. channels->min = channels->max =
  3680. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3681. break;
  3682. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3683. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3684. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3685. rate->min = rate->max =
  3686. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3687. channels->min = channels->max =
  3688. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3689. break;
  3690. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3691. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3692. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3693. rate->min = rate->max =
  3694. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3695. channels->min = channels->max =
  3696. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3697. break;
  3698. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3699. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3700. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3701. rate->min = rate->max =
  3702. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3703. channels->min = channels->max =
  3704. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3705. break;
  3706. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3707. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3708. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3709. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3710. channels->min = channels->max =
  3711. mi2s_rx_cfg[PRIM_MI2S].channels;
  3712. break;
  3713. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3714. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3715. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3716. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3717. channels->min = channels->max =
  3718. mi2s_tx_cfg[PRIM_MI2S].channels;
  3719. break;
  3720. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3721. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3722. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3723. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3724. channels->min = channels->max =
  3725. mi2s_rx_cfg[SEC_MI2S].channels;
  3726. break;
  3727. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3728. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3729. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3730. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3731. channels->min = channels->max =
  3732. mi2s_tx_cfg[SEC_MI2S].channels;
  3733. break;
  3734. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3735. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3736. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3737. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3738. channels->min = channels->max =
  3739. mi2s_rx_cfg[TERT_MI2S].channels;
  3740. break;
  3741. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3742. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3743. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3744. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3745. channels->min = channels->max =
  3746. mi2s_tx_cfg[TERT_MI2S].channels;
  3747. break;
  3748. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3749. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3750. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3751. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3752. channels->min = channels->max =
  3753. mi2s_rx_cfg[QUAT_MI2S].channels;
  3754. break;
  3755. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3756. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3757. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3758. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3759. channels->min = channels->max =
  3760. mi2s_tx_cfg[QUAT_MI2S].channels;
  3761. break;
  3762. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3763. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3764. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3765. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3766. channels->min = channels->max =
  3767. mi2s_rx_cfg[QUIN_MI2S].channels;
  3768. break;
  3769. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3770. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3771. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3772. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3773. channels->min = channels->max =
  3774. mi2s_tx_cfg[QUIN_MI2S].channels;
  3775. break;
  3776. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3777. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3778. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3779. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3780. cdc_dma_rx_cfg[idx].bit_format);
  3781. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3782. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3783. break;
  3784. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3785. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3786. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3787. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3788. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3789. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3790. cdc_dma_tx_cfg[idx].bit_format);
  3791. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3792. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3793. break;
  3794. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3795. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3796. SNDRV_PCM_FORMAT_S32_LE);
  3797. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3798. channels->min = channels->max = msm_vi_feed_tx_ch;
  3799. break;
  3800. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3801. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3802. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3803. rate->min = rate->max =
  3804. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3805. channels->min = channels->max =
  3806. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3807. break;
  3808. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3809. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3810. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3811. rate->min = rate->max =
  3812. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3813. channels->min = channels->max =
  3814. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  3815. break;
  3816. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  3817. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3818. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  3819. rate->min = rate->max =
  3820. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  3821. channels->min = channels->max =
  3822. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  3823. break;
  3824. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  3825. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3826. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  3827. rate->min = rate->max =
  3828. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  3829. channels->min = channels->max =
  3830. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  3831. break;
  3832. default:
  3833. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3834. break;
  3835. }
  3836. return rc;
  3837. }
  3838. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3839. {
  3840. int ret = 0;
  3841. void *config_data = NULL;
  3842. if (!msm_codec_fn.get_afe_config_fn) {
  3843. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3844. __func__);
  3845. return -EINVAL;
  3846. }
  3847. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3848. AFE_CDC_REGISTERS_CONFIG);
  3849. if (config_data) {
  3850. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3851. if (ret) {
  3852. dev_err(codec->dev,
  3853. "%s: Failed to set codec registers config %d\n",
  3854. __func__, ret);
  3855. return ret;
  3856. }
  3857. }
  3858. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3859. AFE_CDC_REGISTER_PAGE_CONFIG);
  3860. if (config_data) {
  3861. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3862. 0);
  3863. if (ret)
  3864. dev_err(codec->dev,
  3865. "%s: Failed to set cdc register page config\n",
  3866. __func__);
  3867. }
  3868. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3869. AFE_SLIMBUS_SLAVE_CONFIG);
  3870. if (config_data) {
  3871. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3872. if (ret) {
  3873. dev_err(codec->dev,
  3874. "%s: Failed to set slimbus slave config %d\n",
  3875. __func__, ret);
  3876. return ret;
  3877. }
  3878. }
  3879. return 0;
  3880. }
  3881. static void msm_afe_clear_config(void)
  3882. {
  3883. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3884. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3885. }
  3886. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3887. struct snd_card *card)
  3888. {
  3889. int ret = 0;
  3890. unsigned long timeout;
  3891. int adsp_ready = 0;
  3892. bool snd_card_online = 0;
  3893. timeout = jiffies +
  3894. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3895. do {
  3896. if (!snd_card_online) {
  3897. snd_card_online = snd_card_is_online_state(card);
  3898. pr_debug("%s: Sound card is %s\n", __func__,
  3899. snd_card_online ? "Online" : "Offline");
  3900. }
  3901. if (!adsp_ready) {
  3902. adsp_ready = q6core_is_adsp_ready();
  3903. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3904. adsp_ready ? "ready" : "not ready");
  3905. }
  3906. if (snd_card_online && adsp_ready)
  3907. break;
  3908. /*
  3909. * Sound card/ADSP will be coming up after subsystem restart and
  3910. * it might not be fully up when the control reaches
  3911. * here. So, wait for 50msec before checking ADSP state
  3912. */
  3913. msleep(50);
  3914. } while (time_after(timeout, jiffies));
  3915. if (!snd_card_online || !adsp_ready) {
  3916. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3917. __func__,
  3918. snd_card_online ? "Online" : "Offline",
  3919. adsp_ready ? "ready" : "not ready");
  3920. ret = -ETIMEDOUT;
  3921. goto err;
  3922. }
  3923. ret = msm_afe_set_config(codec);
  3924. if (ret)
  3925. pr_err("%s: Failed to set AFE config. err %d\n",
  3926. __func__, ret);
  3927. return 0;
  3928. err:
  3929. return ret;
  3930. }
  3931. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3932. unsigned long opcode, void *ptr)
  3933. {
  3934. int ret;
  3935. struct snd_soc_card *card = NULL;
  3936. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3937. struct snd_soc_pcm_runtime *rtd;
  3938. struct snd_soc_codec *codec;
  3939. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3940. switch (opcode) {
  3941. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3942. /*
  3943. * Use flag to ignore initial boot notifications
  3944. * On initial boot msm_adsp_power_up_config is
  3945. * called on init. There is no need to clear
  3946. * and set the config again on initial boot.
  3947. */
  3948. if (is_initial_boot)
  3949. break;
  3950. msm_afe_clear_config();
  3951. break;
  3952. case AUDIO_NOTIFIER_SERVICE_UP:
  3953. if (is_initial_boot) {
  3954. is_initial_boot = false;
  3955. break;
  3956. }
  3957. if (!spdev)
  3958. return -EINVAL;
  3959. card = platform_get_drvdata(spdev);
  3960. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3961. if (!rtd) {
  3962. dev_err(card->dev,
  3963. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3964. __func__, be_dl_name);
  3965. ret = -EINVAL;
  3966. goto err;
  3967. }
  3968. codec = rtd->codec;
  3969. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3970. if (ret < 0) {
  3971. dev_err(card->dev,
  3972. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3973. __func__, ret);
  3974. goto err;
  3975. }
  3976. break;
  3977. default:
  3978. break;
  3979. }
  3980. err:
  3981. return NOTIFY_OK;
  3982. }
  3983. static struct notifier_block service_nb = {
  3984. .notifier_call = qcs405_notifier_service_cb,
  3985. .priority = -INT_MAX,
  3986. };
  3987. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3988. {
  3989. int ret = 0;
  3990. void *config_data;
  3991. struct snd_soc_codec *codec = rtd->codec;
  3992. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3993. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3994. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3995. struct snd_card *card;
  3996. struct msm_asoc_mach_data *pdata =
  3997. snd_soc_card_get_drvdata(rtd->card);
  3998. /*
  3999. * Codec SLIMBUS configuration
  4000. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4001. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4002. * TX14, TX15, TX16
  4003. */
  4004. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4005. 151, 152, 153, 154, 155, 156};
  4006. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4007. 134, 135, 136, 137, 138, 139,
  4008. 140, 141, 142, 143};
  4009. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4010. rtd->pmdown_time = 0;
  4011. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  4012. ARRAY_SIZE(msm_snd_sb_controls));
  4013. if (ret < 0) {
  4014. pr_err("%s: add_codec_controls failed, err %d\n",
  4015. __func__, ret);
  4016. return ret;
  4017. }
  4018. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4019. ARRAY_SIZE(msm_dapm_widgets));
  4020. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4021. ARRAY_SIZE(wcd_audio_paths));
  4022. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4023. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4024. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4025. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4026. snd_soc_dapm_sync(dapm);
  4027. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4028. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4029. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4030. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  4031. if (ret) {
  4032. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  4033. __func__, ret);
  4034. goto err;
  4035. }
  4036. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4037. AFE_AANC_VERSION);
  4038. if (config_data) {
  4039. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4040. if (ret) {
  4041. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  4042. __func__, ret);
  4043. goto err;
  4044. }
  4045. }
  4046. card = rtd->card->snd_card;
  4047. if (!pdata->codec_root)
  4048. pdata->codec_root = snd_info_create_subdir(card->module,
  4049. "codecs", card->proc_root);
  4050. if (!pdata->codec_root) {
  4051. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4052. __func__);
  4053. ret = 0;
  4054. goto err;
  4055. }
  4056. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  4057. codec_reg_done = true;
  4058. return 0;
  4059. err:
  4060. return ret;
  4061. }
  4062. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4063. {
  4064. int ret = 0;
  4065. struct snd_soc_codec *codec = rtd->codec;
  4066. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4067. struct snd_card *card;
  4068. struct msm_asoc_mach_data *pdata =
  4069. snd_soc_card_get_drvdata(rtd->card);
  4070. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  4071. ARRAY_SIZE(msm_snd_va_controls));
  4072. if (ret < 0) {
  4073. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  4074. __func__, ret);
  4075. return ret;
  4076. }
  4077. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4078. ARRAY_SIZE(msm_va_dapm_widgets));
  4079. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4080. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4081. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4082. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4083. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4084. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4085. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4086. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4087. snd_soc_dapm_sync(dapm);
  4088. card = rtd->card->snd_card;
  4089. if (!pdata->codec_root)
  4090. pdata->codec_root = snd_info_create_subdir(card->module,
  4091. "codecs", card->proc_root);
  4092. if (!pdata->codec_root) {
  4093. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4094. __func__);
  4095. ret = 0;
  4096. goto done;
  4097. }
  4098. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4099. done:
  4100. return ret;
  4101. }
  4102. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4103. {
  4104. int ret = 0;
  4105. struct snd_soc_codec *codec = rtd->codec;
  4106. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4107. struct snd_soc_component *aux_comp;
  4108. struct snd_card *card;
  4109. struct msm_asoc_mach_data *pdata =
  4110. snd_soc_card_get_drvdata(rtd->card);
  4111. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  4112. ARRAY_SIZE(msm_snd_wsa_controls));
  4113. if (ret < 0) {
  4114. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4115. __func__, ret);
  4116. return ret;
  4117. }
  4118. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4119. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4120. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4121. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4122. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4123. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4124. snd_soc_dapm_sync(dapm);
  4125. /*
  4126. * Send speaker configuration only for WSA8810.
  4127. * Default configuration is for WSA8815.
  4128. */
  4129. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  4130. __func__, rtd->card->num_aux_devs);
  4131. if (rtd->card->num_aux_devs &&
  4132. !list_empty(&rtd->card->component_dev_list)) {
  4133. aux_comp = list_first_entry(
  4134. &rtd->card->component_dev_list,
  4135. struct snd_soc_component,
  4136. card_aux_list);
  4137. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4138. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4139. wsa_macro_set_spkr_mode(rtd->codec,
  4140. WSA_MACRO_SPKR_MODE_1);
  4141. wsa_macro_set_spkr_gain_offset(rtd->codec,
  4142. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4143. }
  4144. }
  4145. card = rtd->card->snd_card;
  4146. if (!pdata->codec_root)
  4147. pdata->codec_root = snd_info_create_subdir(card->module,
  4148. "codecs", card->proc_root);
  4149. if (!pdata->codec_root) {
  4150. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4151. __func__);
  4152. ret = 0;
  4153. goto done;
  4154. }
  4155. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4156. done:
  4157. return ret;
  4158. }
  4159. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4160. {
  4161. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4162. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  4163. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4164. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4165. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4166. }
  4167. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4168. struct snd_pcm_hw_params *params)
  4169. {
  4170. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4171. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4172. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4173. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4174. int ret = 0;
  4175. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4176. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4177. u32 user_set_tx_ch = 0;
  4178. u32 rx_ch_count;
  4179. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4180. ret = snd_soc_dai_get_channel_map(codec_dai,
  4181. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4182. if (ret < 0) {
  4183. pr_err("%s: failed to get codec chan map, err:%d\n",
  4184. __func__, ret);
  4185. goto err;
  4186. }
  4187. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4188. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4189. slim_rx_cfg[5].channels);
  4190. rx_ch_count = slim_rx_cfg[5].channels;
  4191. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4192. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4193. slim_rx_cfg[2].channels);
  4194. rx_ch_count = slim_rx_cfg[2].channels;
  4195. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4196. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4197. slim_rx_cfg[6].channels);
  4198. rx_ch_count = slim_rx_cfg[6].channels;
  4199. } else {
  4200. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4201. slim_rx_cfg[0].channels);
  4202. rx_ch_count = slim_rx_cfg[0].channels;
  4203. }
  4204. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4205. rx_ch_count, rx_ch);
  4206. if (ret < 0) {
  4207. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4208. __func__, ret);
  4209. goto err;
  4210. }
  4211. } else {
  4212. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4213. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4214. ret = snd_soc_dai_get_channel_map(codec_dai,
  4215. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4216. if (ret < 0) {
  4217. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4218. __func__, ret);
  4219. goto err;
  4220. }
  4221. /* For <codec>_tx1 case */
  4222. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4223. user_set_tx_ch = slim_tx_cfg[0].channels;
  4224. /* For <codec>_tx3 case */
  4225. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4226. user_set_tx_ch = slim_tx_cfg[1].channels;
  4227. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4228. user_set_tx_ch = msm_vi_feed_tx_ch;
  4229. else
  4230. user_set_tx_ch = tx_ch_cnt;
  4231. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4232. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4233. tx_ch_cnt, dai_link->id);
  4234. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4235. user_set_tx_ch, tx_ch, 0, 0);
  4236. if (ret < 0)
  4237. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4238. __func__, ret);
  4239. }
  4240. err:
  4241. return ret;
  4242. }
  4243. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4244. struct snd_pcm_hw_params *params)
  4245. {
  4246. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4247. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4248. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4249. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4250. int ret = 0;
  4251. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4252. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4253. u32 user_set_tx_ch = 0;
  4254. u32 user_set_rx_ch = 0;
  4255. u32 ch_id;
  4256. ret = snd_soc_dai_get_channel_map(codec_dai,
  4257. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4258. &rx_ch_cdc_dma);
  4259. if (ret < 0) {
  4260. pr_err("%s: failed to get codec chan map, err:%d\n",
  4261. __func__, ret);
  4262. goto err;
  4263. }
  4264. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4265. switch (dai_link->id) {
  4266. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4267. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4268. {
  4269. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4270. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4271. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4272. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4273. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4274. user_set_rx_ch, &rx_ch_cdc_dma);
  4275. if (ret < 0) {
  4276. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4277. __func__, ret);
  4278. goto err;
  4279. }
  4280. }
  4281. break;
  4282. }
  4283. } else {
  4284. switch (dai_link->id) {
  4285. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4286. {
  4287. user_set_tx_ch = msm_vi_feed_tx_ch;
  4288. }
  4289. break;
  4290. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4291. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4292. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4293. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4294. {
  4295. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4296. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4297. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4298. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4299. }
  4300. break;
  4301. }
  4302. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4303. &tx_ch_cdc_dma, 0, 0);
  4304. if (ret < 0) {
  4305. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4306. __func__, ret);
  4307. goto err;
  4308. }
  4309. }
  4310. err:
  4311. return ret;
  4312. }
  4313. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4314. struct snd_pcm_hw_params *params)
  4315. {
  4316. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4317. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4318. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4319. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4320. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4321. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4322. int ret;
  4323. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4324. codec_dai->name, codec_dai->id);
  4325. ret = snd_soc_dai_get_channel_map(codec_dai,
  4326. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4327. if (ret) {
  4328. dev_err(rtd->dev,
  4329. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4330. __func__, ret);
  4331. goto err;
  4332. }
  4333. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4334. __func__, tx_ch_cnt, dai_link->id);
  4335. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4336. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4337. if (ret)
  4338. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4339. __func__, ret);
  4340. err:
  4341. return ret;
  4342. }
  4343. static int msm_get_port_id(int be_id)
  4344. {
  4345. int afe_port_id;
  4346. switch (be_id) {
  4347. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4348. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4349. break;
  4350. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4351. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4352. break;
  4353. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4354. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4355. break;
  4356. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4357. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4358. break;
  4359. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4360. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4361. break;
  4362. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4363. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4364. break;
  4365. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4366. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4367. break;
  4368. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4369. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4370. break;
  4371. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4372. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4373. break;
  4374. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4375. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4376. break;
  4377. default:
  4378. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4379. afe_port_id = -EINVAL;
  4380. }
  4381. return afe_port_id;
  4382. }
  4383. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4384. {
  4385. u32 bit_per_sample;
  4386. switch (bit_format) {
  4387. case SNDRV_PCM_FORMAT_S32_LE:
  4388. case SNDRV_PCM_FORMAT_S24_3LE:
  4389. case SNDRV_PCM_FORMAT_S24_LE:
  4390. bit_per_sample = 32;
  4391. break;
  4392. case SNDRV_PCM_FORMAT_S16_LE:
  4393. default:
  4394. bit_per_sample = 16;
  4395. break;
  4396. }
  4397. return bit_per_sample;
  4398. }
  4399. static void update_mi2s_clk_val(int dai_id, int stream)
  4400. {
  4401. u32 bit_per_sample;
  4402. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4403. bit_per_sample =
  4404. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4405. mi2s_clk[dai_id].clk_freq_in_hz =
  4406. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4407. } else {
  4408. bit_per_sample =
  4409. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4410. mi2s_clk[dai_id].clk_freq_in_hz =
  4411. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4412. }
  4413. }
  4414. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4415. {
  4416. int ret = 0;
  4417. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4418. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4419. int port_id = 0;
  4420. int index = cpu_dai->id;
  4421. port_id = msm_get_port_id(rtd->dai_link->id);
  4422. if (port_id < 0) {
  4423. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4424. ret = port_id;
  4425. goto err;
  4426. }
  4427. if (enable) {
  4428. update_mi2s_clk_val(index, substream->stream);
  4429. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4430. mi2s_clk[index].clk_freq_in_hz);
  4431. }
  4432. mi2s_clk[index].enable = enable;
  4433. ret = afe_set_lpass_clock_v2(port_id,
  4434. &mi2s_clk[index]);
  4435. if (ret < 0) {
  4436. dev_err(rtd->card->dev,
  4437. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4438. __func__, port_id, ret);
  4439. goto err;
  4440. }
  4441. err:
  4442. return ret;
  4443. }
  4444. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4445. enum pinctrl_pin_state new_state)
  4446. {
  4447. int ret = 0;
  4448. int curr_state = 0;
  4449. if (pinctrl_info == NULL) {
  4450. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4451. ret = -EINVAL;
  4452. goto err;
  4453. }
  4454. if (pinctrl_info->pinctrl == NULL) {
  4455. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4456. ret = -EINVAL;
  4457. goto err;
  4458. }
  4459. curr_state = pinctrl_info->curr_state;
  4460. pinctrl_info->curr_state = new_state;
  4461. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4462. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4463. if (curr_state == pinctrl_info->curr_state) {
  4464. pr_debug("%s: Already in same state\n", __func__);
  4465. goto err;
  4466. }
  4467. if (curr_state != STATE_DISABLE &&
  4468. pinctrl_info->curr_state != STATE_DISABLE) {
  4469. pr_debug("%s: state already active cannot switch\n", __func__);
  4470. ret = -EIO;
  4471. goto err;
  4472. }
  4473. switch (pinctrl_info->curr_state) {
  4474. case STATE_MI2S_ACTIVE:
  4475. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4476. pinctrl_info->mi2s_active);
  4477. if (ret) {
  4478. pr_err("%s: MI2S state select failed with %d\n",
  4479. __func__, ret);
  4480. ret = -EIO;
  4481. goto err;
  4482. }
  4483. break;
  4484. case STATE_TDM_ACTIVE:
  4485. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4486. pinctrl_info->tdm_active);
  4487. if (ret) {
  4488. pr_err("%s: TDM state select failed with %d\n",
  4489. __func__, ret);
  4490. ret = -EIO;
  4491. goto err;
  4492. }
  4493. break;
  4494. case STATE_DISABLE:
  4495. if (curr_state == STATE_MI2S_ACTIVE) {
  4496. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4497. pinctrl_info->mi2s_disable);
  4498. } else {
  4499. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4500. pinctrl_info->tdm_disable);
  4501. }
  4502. if (ret) {
  4503. pr_err("%s: state disable failed with %d\n",
  4504. __func__, ret);
  4505. ret = -EIO;
  4506. goto err;
  4507. }
  4508. break;
  4509. default:
  4510. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4511. return -EINVAL;
  4512. }
  4513. err:
  4514. return ret;
  4515. }
  4516. static void msm_release_pinctrl(struct platform_device *pdev)
  4517. {
  4518. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4519. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4520. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4521. if (pinctrl_info->pinctrl) {
  4522. devm_pinctrl_put(pinctrl_info->pinctrl);
  4523. pinctrl_info->pinctrl = NULL;
  4524. }
  4525. }
  4526. static int msm_get_pinctrl(struct platform_device *pdev)
  4527. {
  4528. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4529. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4530. struct msm_pinctrl_info *pinctrl_info = NULL;
  4531. struct pinctrl *pinctrl;
  4532. int ret;
  4533. pinctrl_info = &pdata->pinctrl_info;
  4534. if (pinctrl_info == NULL) {
  4535. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4536. return -EINVAL;
  4537. }
  4538. pinctrl = devm_pinctrl_get(&pdev->dev);
  4539. if (IS_ERR_OR_NULL(pinctrl)) {
  4540. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4541. return -EINVAL;
  4542. }
  4543. pinctrl_info->pinctrl = pinctrl;
  4544. /* get all the states handles from Device Tree */
  4545. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4546. "quat-mi2s-sleep");
  4547. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4548. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4549. goto err;
  4550. }
  4551. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4552. "quat-mi2s-active");
  4553. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4554. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4555. goto err;
  4556. }
  4557. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4558. "quat-tdm-sleep");
  4559. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4560. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4561. goto err;
  4562. }
  4563. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4564. "quat-tdm-active");
  4565. if (IS_ERR(pinctrl_info->tdm_active)) {
  4566. pr_err("%s: could not get tdm_active pinstate\n",
  4567. __func__);
  4568. goto err;
  4569. }
  4570. /* Reset the TLMM pins to a default state */
  4571. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4572. pinctrl_info->mi2s_disable);
  4573. if (ret != 0) {
  4574. pr_err("%s: Disable TLMM pins failed with %d\n",
  4575. __func__, ret);
  4576. ret = -EIO;
  4577. goto err;
  4578. }
  4579. pinctrl_info->curr_state = STATE_DISABLE;
  4580. return 0;
  4581. err:
  4582. devm_pinctrl_put(pinctrl);
  4583. pinctrl_info->pinctrl = NULL;
  4584. return -EINVAL;
  4585. }
  4586. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4587. struct snd_pcm_hw_params *params)
  4588. {
  4589. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4590. struct snd_interval *rate = hw_param_interval(params,
  4591. SNDRV_PCM_HW_PARAM_RATE);
  4592. struct snd_interval *channels = hw_param_interval(params,
  4593. SNDRV_PCM_HW_PARAM_CHANNELS);
  4594. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4595. channels->min = channels->max =
  4596. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4597. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4598. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4599. rate->min = rate->max =
  4600. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4601. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4602. channels->min = channels->max =
  4603. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4604. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4605. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4606. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4607. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4608. channels->min = channels->max =
  4609. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4610. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4611. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4612. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4613. } else {
  4614. pr_err("%s: dai id 0x%x not supported\n",
  4615. __func__, cpu_dai->id);
  4616. return -EINVAL;
  4617. }
  4618. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4619. __func__, cpu_dai->id, channels->max, rate->max,
  4620. params_format(params));
  4621. return 0;
  4622. }
  4623. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4624. struct snd_pcm_hw_params *params)
  4625. {
  4626. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4627. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4628. int ret = 0;
  4629. int slot_width = 32;
  4630. int channels, slots;
  4631. unsigned int slot_mask, rate, clk_freq;
  4632. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4633. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4634. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4635. switch (cpu_dai->id) {
  4636. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4637. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4638. break;
  4639. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4640. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4641. break;
  4642. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4643. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4644. break;
  4645. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4646. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4647. break;
  4648. case AFE_PORT_ID_QUINARY_TDM_RX:
  4649. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4650. break;
  4651. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4652. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4653. break;
  4654. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4655. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4656. break;
  4657. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4658. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4659. break;
  4660. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4661. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4662. break;
  4663. case AFE_PORT_ID_QUINARY_TDM_TX:
  4664. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4665. break;
  4666. default:
  4667. pr_err("%s: dai id 0x%x not supported\n",
  4668. __func__, cpu_dai->id);
  4669. return -EINVAL;
  4670. }
  4671. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4672. /*2 slot config - bits 0 and 1 set for the first two slots */
  4673. slot_mask = 0x0000FFFF >> (16-slots);
  4674. channels = slots;
  4675. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4676. __func__, slot_width, slots);
  4677. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4678. slots, slot_width);
  4679. if (ret < 0) {
  4680. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4681. __func__, ret);
  4682. goto end;
  4683. }
  4684. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4685. 0, NULL, channels, slot_offset);
  4686. if (ret < 0) {
  4687. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4688. __func__, ret);
  4689. goto end;
  4690. }
  4691. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4692. /*2 slot config - bits 0 and 1 set for the first two slots */
  4693. slot_mask = 0x0000FFFF >> (16-slots);
  4694. channels = slots;
  4695. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4696. __func__, slot_width, slots);
  4697. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4698. slots, slot_width);
  4699. if (ret < 0) {
  4700. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4701. __func__, ret);
  4702. goto end;
  4703. }
  4704. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4705. channels, slot_offset, 0, NULL);
  4706. if (ret < 0) {
  4707. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4708. __func__, ret);
  4709. goto end;
  4710. }
  4711. } else {
  4712. ret = -EINVAL;
  4713. pr_err("%s: invalid use case, err:%d\n",
  4714. __func__, ret);
  4715. goto end;
  4716. }
  4717. rate = params_rate(params);
  4718. clk_freq = rate * slot_width * slots;
  4719. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4720. if (ret < 0)
  4721. pr_err("%s: failed to set tdm clk, err:%d\n",
  4722. __func__, ret);
  4723. end:
  4724. return ret;
  4725. }
  4726. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4727. {
  4728. int ret = 0;
  4729. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4730. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4731. struct snd_soc_card *card = rtd->card;
  4732. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4733. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4734. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4735. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4736. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4737. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4738. if (ret)
  4739. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4740. __func__, ret);
  4741. }
  4742. return ret;
  4743. }
  4744. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4745. {
  4746. int ret = 0;
  4747. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4748. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4749. struct snd_soc_card *card = rtd->card;
  4750. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4751. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4752. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4753. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4754. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4755. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4756. if (ret)
  4757. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4758. __func__, ret);
  4759. }
  4760. }
  4761. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4762. .hw_params = qcs405_tdm_snd_hw_params,
  4763. .startup = qcs405_tdm_snd_startup,
  4764. .shutdown = qcs405_tdm_snd_shutdown
  4765. };
  4766. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4767. {
  4768. cpumask_t mask;
  4769. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4770. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4771. cpumask_clear(&mask);
  4772. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4773. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4774. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4775. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4776. pm_qos_add_request(&substream->latency_pm_qos_req,
  4777. PM_QOS_CPU_DMA_LATENCY,
  4778. MSM_LL_QOS_VALUE);
  4779. return 0;
  4780. }
  4781. static struct snd_soc_ops msm_fe_qos_ops = {
  4782. .prepare = msm_fe_qos_prepare,
  4783. };
  4784. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4785. {
  4786. int ret = 0;
  4787. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4788. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4789. int index = cpu_dai->id;
  4790. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4791. struct snd_soc_card *card = rtd->card;
  4792. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4793. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4794. int ret_pinctrl = 0;
  4795. dev_dbg(rtd->card->dev,
  4796. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4797. __func__, substream->name, substream->stream,
  4798. cpu_dai->name, cpu_dai->id);
  4799. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4800. ret = -EINVAL;
  4801. dev_err(rtd->card->dev,
  4802. "%s: CPU DAI id (%d) out of range\n",
  4803. __func__, cpu_dai->id);
  4804. goto err;
  4805. }
  4806. /*
  4807. * Mutex protection in case the same MI2S
  4808. * interface using for both TX and RX so
  4809. * that the same clock won't be enable twice.
  4810. */
  4811. mutex_lock(&mi2s_intf_conf[index].lock);
  4812. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4813. /* Check if msm needs to provide the clock to the interface */
  4814. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4815. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4816. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4817. }
  4818. ret = msm_mi2s_set_sclk(substream, true);
  4819. if (ret < 0) {
  4820. dev_err(rtd->card->dev,
  4821. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4822. __func__, ret);
  4823. goto clean_up;
  4824. }
  4825. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4826. if (ret < 0) {
  4827. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4828. __func__, index, ret);
  4829. goto clk_off;
  4830. }
  4831. if (index == QUAT_MI2S) {
  4832. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4833. STATE_MI2S_ACTIVE);
  4834. if (ret_pinctrl)
  4835. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4836. __func__, ret_pinctrl);
  4837. }
  4838. }
  4839. clk_off:
  4840. if (ret < 0)
  4841. msm_mi2s_set_sclk(substream, false);
  4842. clean_up:
  4843. if (ret < 0)
  4844. mi2s_intf_conf[index].ref_cnt--;
  4845. mutex_unlock(&mi2s_intf_conf[index].lock);
  4846. err:
  4847. return ret;
  4848. }
  4849. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4850. {
  4851. int ret;
  4852. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4853. int index = rtd->cpu_dai->id;
  4854. struct snd_soc_card *card = rtd->card;
  4855. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4856. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4857. int ret_pinctrl = 0;
  4858. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4859. substream->name, substream->stream);
  4860. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4861. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4862. return;
  4863. }
  4864. mutex_lock(&mi2s_intf_conf[index].lock);
  4865. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4866. ret = msm_mi2s_set_sclk(substream, false);
  4867. if (ret < 0)
  4868. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4869. __func__, index, ret);
  4870. if (index == QUAT_MI2S) {
  4871. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4872. STATE_DISABLE);
  4873. if (ret_pinctrl)
  4874. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4875. __func__, ret_pinctrl);
  4876. }
  4877. }
  4878. mutex_unlock(&mi2s_intf_conf[index].lock);
  4879. }
  4880. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  4881. {
  4882. int ret = 0;
  4883. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4884. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4885. int port_id = cpu_dai->id;
  4886. struct afe_clk_set clk_cfg;
  4887. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  4888. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  4889. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  4890. clk_cfg.enable = enable;
  4891. /* Set core clock (based on sample rate for RX, fixed for TX) */
  4892. switch (port_id) {
  4893. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4894. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  4895. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  4896. clk_cfg.clk_freq_in_hz =
  4897. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4898. break;
  4899. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4900. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  4901. clk_cfg.clk_freq_in_hz =
  4902. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4903. break;
  4904. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  4905. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  4906. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4907. break;
  4908. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  4909. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  4910. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4911. break;
  4912. }
  4913. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4914. if (ret < 0) {
  4915. dev_err(rtd->card->dev,
  4916. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4917. __func__, port_id, ret);
  4918. goto err;
  4919. }
  4920. /* Set NPL clock for RX in addition */
  4921. switch (port_id) {
  4922. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4923. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  4924. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4925. if (ret < 0) {
  4926. dev_err(rtd->card->dev,
  4927. "%s: afe NPL failed port 0x%x, err:%d\n",
  4928. __func__, port_id, ret);
  4929. goto err;
  4930. }
  4931. break;
  4932. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4933. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  4934. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4935. if (ret < 0) {
  4936. dev_err(rtd->card->dev,
  4937. "%s: afe NPL failed for port 0x%x, err:%d\n",
  4938. __func__, port_id, ret);
  4939. goto err;
  4940. }
  4941. break;
  4942. }
  4943. if (enable) {
  4944. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4945. clk_cfg.clk_freq_in_hz);
  4946. }
  4947. err:
  4948. return ret;
  4949. }
  4950. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  4951. {
  4952. int ret = 0;
  4953. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4954. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4955. int port_id = cpu_dai->id;
  4956. dev_dbg(rtd->card->dev,
  4957. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4958. __func__, substream->name, substream->stream,
  4959. cpu_dai->name, cpu_dai->id);
  4960. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4961. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4962. ret = -EINVAL;
  4963. dev_err(rtd->card->dev,
  4964. "%s: CPU DAI id (%d) out of range\n",
  4965. __func__, cpu_dai->id);
  4966. goto err;
  4967. }
  4968. ret = msm_spdif_set_clk(substream, true);
  4969. if (ret < 0) {
  4970. dev_err(rtd->card->dev,
  4971. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  4972. __func__, port_id, ret);
  4973. }
  4974. err:
  4975. return ret;
  4976. }
  4977. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  4978. {
  4979. int ret;
  4980. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4981. int port_id = rtd->cpu_dai->id;
  4982. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4983. substream->name, substream->stream);
  4984. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4985. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4986. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  4987. return;
  4988. }
  4989. ret = msm_spdif_set_clk(substream, false);
  4990. if (ret < 0)
  4991. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  4992. __func__, port_id, ret);
  4993. }
  4994. static struct snd_soc_ops msm_mi2s_be_ops = {
  4995. .startup = msm_mi2s_snd_startup,
  4996. .shutdown = msm_mi2s_snd_shutdown,
  4997. };
  4998. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4999. .hw_params = msm_snd_cdc_dma_hw_params,
  5000. };
  5001. static struct snd_soc_ops msm_be_ops = {
  5002. .hw_params = msm_snd_hw_params,
  5003. };
  5004. static struct snd_soc_ops msm_wcn_ops = {
  5005. .hw_params = msm_wcn_hw_params,
  5006. };
  5007. static struct snd_soc_ops msm_spdif_be_ops = {
  5008. .startup = msm_spdif_snd_startup,
  5009. .shutdown = msm_spdif_snd_shutdown,
  5010. };
  5011. /* Digital audio interface glue - connects codec <---> CPU */
  5012. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5013. /* FrontEnd DAI Links */
  5014. {
  5015. .name = MSM_DAILINK_NAME(Media1),
  5016. .stream_name = "MultiMedia1",
  5017. .cpu_dai_name = "MultiMedia1",
  5018. .platform_name = "msm-pcm-dsp.0",
  5019. .dynamic = 1,
  5020. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5021. .dpcm_playback = 1,
  5022. .dpcm_capture = 1,
  5023. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5024. SND_SOC_DPCM_TRIGGER_POST},
  5025. .codec_dai_name = "snd-soc-dummy-dai",
  5026. .codec_name = "snd-soc-dummy",
  5027. .ignore_suspend = 1,
  5028. /* this dainlink has playback support */
  5029. .ignore_pmdown_time = 1,
  5030. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5031. },
  5032. {
  5033. .name = MSM_DAILINK_NAME(Media2),
  5034. .stream_name = "MultiMedia2",
  5035. .cpu_dai_name = "MultiMedia2",
  5036. .platform_name = "msm-pcm-dsp.0",
  5037. .dynamic = 1,
  5038. .dpcm_playback = 1,
  5039. .dpcm_capture = 1,
  5040. .codec_dai_name = "snd-soc-dummy-dai",
  5041. .codec_name = "snd-soc-dummy",
  5042. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5043. SND_SOC_DPCM_TRIGGER_POST},
  5044. .ignore_suspend = 1,
  5045. /* this dainlink has playback support */
  5046. .ignore_pmdown_time = 1,
  5047. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5048. },
  5049. {
  5050. .name = "VoiceMMode1",
  5051. .stream_name = "VoiceMMode1",
  5052. .cpu_dai_name = "VoiceMMode1",
  5053. .platform_name = "msm-pcm-voice",
  5054. .dynamic = 1,
  5055. .dpcm_playback = 1,
  5056. .dpcm_capture = 1,
  5057. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5058. SND_SOC_DPCM_TRIGGER_POST},
  5059. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5060. .ignore_suspend = 1,
  5061. .ignore_pmdown_time = 1,
  5062. .codec_dai_name = "snd-soc-dummy-dai",
  5063. .codec_name = "snd-soc-dummy",
  5064. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5065. },
  5066. {
  5067. .name = "MSM VoIP",
  5068. .stream_name = "VoIP",
  5069. .cpu_dai_name = "VoIP",
  5070. .platform_name = "msm-voip-dsp",
  5071. .dynamic = 1,
  5072. .dpcm_playback = 1,
  5073. .dpcm_capture = 1,
  5074. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5075. SND_SOC_DPCM_TRIGGER_POST},
  5076. .codec_dai_name = "snd-soc-dummy-dai",
  5077. .codec_name = "snd-soc-dummy",
  5078. .ignore_suspend = 1,
  5079. /* this dainlink has playback support */
  5080. .ignore_pmdown_time = 1,
  5081. .id = MSM_FRONTEND_DAI_VOIP,
  5082. },
  5083. {
  5084. .name = MSM_DAILINK_NAME(ULL),
  5085. .stream_name = "MultiMedia3",
  5086. .cpu_dai_name = "MultiMedia3",
  5087. .platform_name = "msm-pcm-dsp.2",
  5088. .dynamic = 1,
  5089. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5090. .dpcm_playback = 1,
  5091. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5092. SND_SOC_DPCM_TRIGGER_POST},
  5093. .codec_dai_name = "snd-soc-dummy-dai",
  5094. .codec_name = "snd-soc-dummy",
  5095. .ignore_suspend = 1,
  5096. /* this dainlink has playback support */
  5097. .ignore_pmdown_time = 1,
  5098. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5099. },
  5100. /* Hostless PCM purpose */
  5101. {
  5102. .name = "SLIMBUS_0 Hostless",
  5103. .stream_name = "SLIMBUS_0 Hostless",
  5104. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5105. .platform_name = "msm-pcm-hostless",
  5106. .dynamic = 1,
  5107. .dpcm_playback = 1,
  5108. .dpcm_capture = 1,
  5109. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5110. SND_SOC_DPCM_TRIGGER_POST},
  5111. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5112. .ignore_suspend = 1,
  5113. /* this dailink has playback support */
  5114. .ignore_pmdown_time = 1,
  5115. .codec_dai_name = "snd-soc-dummy-dai",
  5116. .codec_name = "snd-soc-dummy",
  5117. },
  5118. {
  5119. .name = "MSM AFE-PCM RX",
  5120. .stream_name = "AFE-PROXY RX",
  5121. .cpu_dai_name = "msm-dai-q6-dev.241",
  5122. .codec_name = "msm-stub-codec.1",
  5123. .codec_dai_name = "msm-stub-rx",
  5124. .platform_name = "msm-pcm-afe",
  5125. .dpcm_playback = 1,
  5126. .ignore_suspend = 1,
  5127. /* this dainlink has playback support */
  5128. .ignore_pmdown_time = 1,
  5129. },
  5130. {
  5131. .name = "MSM AFE-PCM TX",
  5132. .stream_name = "AFE-PROXY TX",
  5133. .cpu_dai_name = "msm-dai-q6-dev.240",
  5134. .codec_name = "msm-stub-codec.1",
  5135. .codec_dai_name = "msm-stub-tx",
  5136. .platform_name = "msm-pcm-afe",
  5137. .dpcm_capture = 1,
  5138. .ignore_suspend = 1,
  5139. },
  5140. {
  5141. .name = MSM_DAILINK_NAME(Compress1),
  5142. .stream_name = "Compress1",
  5143. .cpu_dai_name = "MultiMedia4",
  5144. .platform_name = "msm-compress-dsp",
  5145. .dynamic = 1,
  5146. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5147. .dpcm_playback = 1,
  5148. .dpcm_capture = 1,
  5149. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5150. SND_SOC_DPCM_TRIGGER_POST},
  5151. .codec_dai_name = "snd-soc-dummy-dai",
  5152. .codec_name = "snd-soc-dummy",
  5153. .ignore_suspend = 1,
  5154. .ignore_pmdown_time = 1,
  5155. /* this dainlink has playback support */
  5156. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5157. },
  5158. {
  5159. .name = "AUXPCM Hostless",
  5160. .stream_name = "AUXPCM Hostless",
  5161. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5162. .platform_name = "msm-pcm-hostless",
  5163. .dynamic = 1,
  5164. .dpcm_playback = 1,
  5165. .dpcm_capture = 1,
  5166. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5167. SND_SOC_DPCM_TRIGGER_POST},
  5168. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5169. .ignore_suspend = 1,
  5170. /* this dainlink has playback support */
  5171. .ignore_pmdown_time = 1,
  5172. .codec_dai_name = "snd-soc-dummy-dai",
  5173. .codec_name = "snd-soc-dummy",
  5174. },
  5175. {
  5176. .name = "SLIMBUS_1 Hostless",
  5177. .stream_name = "SLIMBUS_1 Hostless",
  5178. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5179. .platform_name = "msm-pcm-hostless",
  5180. .dynamic = 1,
  5181. .dpcm_playback = 1,
  5182. .dpcm_capture = 1,
  5183. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5184. SND_SOC_DPCM_TRIGGER_POST},
  5185. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5186. .ignore_suspend = 1,
  5187. /* this dailink has playback support */
  5188. .ignore_pmdown_time = 1,
  5189. .codec_dai_name = "snd-soc-dummy-dai",
  5190. .codec_name = "snd-soc-dummy",
  5191. },
  5192. {
  5193. .name = "SLIMBUS_3 Hostless",
  5194. .stream_name = "SLIMBUS_3 Hostless",
  5195. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5196. .platform_name = "msm-pcm-hostless",
  5197. .dynamic = 1,
  5198. .dpcm_playback = 1,
  5199. .dpcm_capture = 1,
  5200. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5201. SND_SOC_DPCM_TRIGGER_POST},
  5202. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5203. .ignore_suspend = 1,
  5204. /* this dailink has playback support */
  5205. .ignore_pmdown_time = 1,
  5206. .codec_dai_name = "snd-soc-dummy-dai",
  5207. .codec_name = "snd-soc-dummy",
  5208. },
  5209. {
  5210. .name = "SLIMBUS_4 Hostless",
  5211. .stream_name = "SLIMBUS_4 Hostless",
  5212. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5213. .platform_name = "msm-pcm-hostless",
  5214. .dynamic = 1,
  5215. .dpcm_playback = 1,
  5216. .dpcm_capture = 1,
  5217. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5218. SND_SOC_DPCM_TRIGGER_POST},
  5219. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5220. .ignore_suspend = 1,
  5221. /* this dailink has playback support */
  5222. .ignore_pmdown_time = 1,
  5223. .codec_dai_name = "snd-soc-dummy-dai",
  5224. .codec_name = "snd-soc-dummy",
  5225. },
  5226. {
  5227. .name = MSM_DAILINK_NAME(LowLatency),
  5228. .stream_name = "MultiMedia5",
  5229. .cpu_dai_name = "MultiMedia5",
  5230. .platform_name = "msm-pcm-dsp.1",
  5231. .dynamic = 1,
  5232. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5233. .dpcm_playback = 1,
  5234. .dpcm_capture = 1,
  5235. .codec_dai_name = "snd-soc-dummy-dai",
  5236. .codec_name = "snd-soc-dummy",
  5237. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5238. SND_SOC_DPCM_TRIGGER_POST},
  5239. .ignore_suspend = 1,
  5240. /* this dainlink has playback support */
  5241. .ignore_pmdown_time = 1,
  5242. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5243. .ops = &msm_fe_qos_ops,
  5244. },
  5245. {
  5246. .name = "Listen 1 Audio Service",
  5247. .stream_name = "Listen 1 Audio Service",
  5248. .cpu_dai_name = "LSM1",
  5249. .platform_name = "msm-lsm-client",
  5250. .dynamic = 1,
  5251. .dpcm_capture = 1,
  5252. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5253. SND_SOC_DPCM_TRIGGER_POST },
  5254. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5255. .ignore_suspend = 1,
  5256. .codec_dai_name = "snd-soc-dummy-dai",
  5257. .codec_name = "snd-soc-dummy",
  5258. .id = MSM_FRONTEND_DAI_LSM1,
  5259. },
  5260. /* Multiple Tunnel instances */
  5261. {
  5262. .name = MSM_DAILINK_NAME(Compress2),
  5263. .stream_name = "Compress2",
  5264. .cpu_dai_name = "MultiMedia7",
  5265. .platform_name = "msm-compress-dsp",
  5266. .dynamic = 1,
  5267. .dpcm_playback = 1,
  5268. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5269. SND_SOC_DPCM_TRIGGER_POST},
  5270. .codec_dai_name = "snd-soc-dummy-dai",
  5271. .codec_name = "snd-soc-dummy",
  5272. .ignore_suspend = 1,
  5273. .ignore_pmdown_time = 1,
  5274. /* this dainlink has playback support */
  5275. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5276. },
  5277. {
  5278. .name = MSM_DAILINK_NAME(MultiMedia10),
  5279. .stream_name = "MultiMedia10",
  5280. .cpu_dai_name = "MultiMedia10",
  5281. .platform_name = "msm-pcm-dsp.1",
  5282. .dynamic = 1,
  5283. .dpcm_playback = 1,
  5284. .dpcm_capture = 1,
  5285. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5286. SND_SOC_DPCM_TRIGGER_POST},
  5287. .codec_dai_name = "snd-soc-dummy-dai",
  5288. .codec_name = "snd-soc-dummy",
  5289. .ignore_suspend = 1,
  5290. .ignore_pmdown_time = 1,
  5291. /* this dainlink has playback support */
  5292. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5293. },
  5294. {
  5295. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5296. .stream_name = "MM_NOIRQ",
  5297. .cpu_dai_name = "MultiMedia8",
  5298. .platform_name = "msm-pcm-dsp-noirq",
  5299. .dynamic = 1,
  5300. .dpcm_playback = 1,
  5301. .dpcm_capture = 1,
  5302. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5303. SND_SOC_DPCM_TRIGGER_POST},
  5304. .codec_dai_name = "snd-soc-dummy-dai",
  5305. .codec_name = "snd-soc-dummy",
  5306. .ignore_suspend = 1,
  5307. .ignore_pmdown_time = 1,
  5308. /* this dainlink has playback support */
  5309. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5310. .ops = &msm_fe_qos_ops,
  5311. },
  5312. /* HDMI Hostless */
  5313. {
  5314. .name = "HDMI_RX_HOSTLESS",
  5315. .stream_name = "HDMI_RX_HOSTLESS",
  5316. .cpu_dai_name = "HDMI_HOSTLESS",
  5317. .platform_name = "msm-pcm-hostless",
  5318. .dynamic = 1,
  5319. .dpcm_playback = 1,
  5320. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5321. SND_SOC_DPCM_TRIGGER_POST},
  5322. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5323. .ignore_suspend = 1,
  5324. .ignore_pmdown_time = 1,
  5325. .codec_dai_name = "snd-soc-dummy-dai",
  5326. .codec_name = "snd-soc-dummy",
  5327. },
  5328. {
  5329. .name = "VoiceMMode2",
  5330. .stream_name = "VoiceMMode2",
  5331. .cpu_dai_name = "VoiceMMode2",
  5332. .platform_name = "msm-pcm-voice",
  5333. .dynamic = 1,
  5334. .dpcm_playback = 1,
  5335. .dpcm_capture = 1,
  5336. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5337. SND_SOC_DPCM_TRIGGER_POST},
  5338. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5339. .ignore_suspend = 1,
  5340. .ignore_pmdown_time = 1,
  5341. .codec_dai_name = "snd-soc-dummy-dai",
  5342. .codec_name = "snd-soc-dummy",
  5343. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5344. },
  5345. /* LSM FE */
  5346. {
  5347. .name = "Listen 2 Audio Service",
  5348. .stream_name = "Listen 2 Audio Service",
  5349. .cpu_dai_name = "LSM2",
  5350. .platform_name = "msm-lsm-client",
  5351. .dynamic = 1,
  5352. .dpcm_capture = 1,
  5353. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5354. SND_SOC_DPCM_TRIGGER_POST },
  5355. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5356. .ignore_suspend = 1,
  5357. .codec_dai_name = "snd-soc-dummy-dai",
  5358. .codec_name = "snd-soc-dummy",
  5359. .id = MSM_FRONTEND_DAI_LSM2,
  5360. },
  5361. {
  5362. .name = "Listen 3 Audio Service",
  5363. .stream_name = "Listen 3 Audio Service",
  5364. .cpu_dai_name = "LSM3",
  5365. .platform_name = "msm-lsm-client",
  5366. .dynamic = 1,
  5367. .dpcm_capture = 1,
  5368. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5369. SND_SOC_DPCM_TRIGGER_POST },
  5370. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5371. .ignore_suspend = 1,
  5372. .codec_dai_name = "snd-soc-dummy-dai",
  5373. .codec_name = "snd-soc-dummy",
  5374. .id = MSM_FRONTEND_DAI_LSM3,
  5375. },
  5376. {
  5377. .name = "Listen 4 Audio Service",
  5378. .stream_name = "Listen 4 Audio Service",
  5379. .cpu_dai_name = "LSM4",
  5380. .platform_name = "msm-lsm-client",
  5381. .dynamic = 1,
  5382. .dpcm_capture = 1,
  5383. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5384. SND_SOC_DPCM_TRIGGER_POST },
  5385. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5386. .ignore_suspend = 1,
  5387. .codec_dai_name = "snd-soc-dummy-dai",
  5388. .codec_name = "snd-soc-dummy",
  5389. .id = MSM_FRONTEND_DAI_LSM4,
  5390. },
  5391. {
  5392. .name = "Listen 5 Audio Service",
  5393. .stream_name = "Listen 5 Audio Service",
  5394. .cpu_dai_name = "LSM5",
  5395. .platform_name = "msm-lsm-client",
  5396. .dynamic = 1,
  5397. .dpcm_capture = 1,
  5398. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5399. SND_SOC_DPCM_TRIGGER_POST },
  5400. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5401. .ignore_suspend = 1,
  5402. .codec_dai_name = "snd-soc-dummy-dai",
  5403. .codec_name = "snd-soc-dummy",
  5404. .id = MSM_FRONTEND_DAI_LSM5,
  5405. },
  5406. {
  5407. .name = "Listen 6 Audio Service",
  5408. .stream_name = "Listen 6 Audio Service",
  5409. .cpu_dai_name = "LSM6",
  5410. .platform_name = "msm-lsm-client",
  5411. .dynamic = 1,
  5412. .dpcm_capture = 1,
  5413. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5414. SND_SOC_DPCM_TRIGGER_POST },
  5415. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5416. .ignore_suspend = 1,
  5417. .codec_dai_name = "snd-soc-dummy-dai",
  5418. .codec_name = "snd-soc-dummy",
  5419. .id = MSM_FRONTEND_DAI_LSM6,
  5420. },
  5421. {
  5422. .name = "Listen 7 Audio Service",
  5423. .stream_name = "Listen 7 Audio Service",
  5424. .cpu_dai_name = "LSM7",
  5425. .platform_name = "msm-lsm-client",
  5426. .dynamic = 1,
  5427. .dpcm_capture = 1,
  5428. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5429. SND_SOC_DPCM_TRIGGER_POST },
  5430. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5431. .ignore_suspend = 1,
  5432. .codec_dai_name = "snd-soc-dummy-dai",
  5433. .codec_name = "snd-soc-dummy",
  5434. .id = MSM_FRONTEND_DAI_LSM7,
  5435. },
  5436. {
  5437. .name = "Listen 8 Audio Service",
  5438. .stream_name = "Listen 8 Audio Service",
  5439. .cpu_dai_name = "LSM8",
  5440. .platform_name = "msm-lsm-client",
  5441. .dynamic = 1,
  5442. .dpcm_capture = 1,
  5443. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5444. SND_SOC_DPCM_TRIGGER_POST },
  5445. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5446. .ignore_suspend = 1,
  5447. .codec_dai_name = "snd-soc-dummy-dai",
  5448. .codec_name = "snd-soc-dummy",
  5449. .id = MSM_FRONTEND_DAI_LSM8,
  5450. },
  5451. {
  5452. .name = MSM_DAILINK_NAME(Media9),
  5453. .stream_name = "MultiMedia9",
  5454. .cpu_dai_name = "MultiMedia9",
  5455. .platform_name = "msm-pcm-dsp.0",
  5456. .dynamic = 1,
  5457. .dpcm_playback = 1,
  5458. .dpcm_capture = 1,
  5459. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5460. SND_SOC_DPCM_TRIGGER_POST},
  5461. .codec_dai_name = "snd-soc-dummy-dai",
  5462. .codec_name = "snd-soc-dummy",
  5463. .ignore_suspend = 1,
  5464. /* this dainlink has playback support */
  5465. .ignore_pmdown_time = 1,
  5466. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5467. },
  5468. {
  5469. .name = MSM_DAILINK_NAME(Compress4),
  5470. .stream_name = "Compress4",
  5471. .cpu_dai_name = "MultiMedia11",
  5472. .platform_name = "msm-compress-dsp",
  5473. .dynamic = 1,
  5474. .dpcm_playback = 1,
  5475. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5476. SND_SOC_DPCM_TRIGGER_POST},
  5477. .codec_dai_name = "snd-soc-dummy-dai",
  5478. .codec_name = "snd-soc-dummy",
  5479. .ignore_suspend = 1,
  5480. .ignore_pmdown_time = 1,
  5481. /* this dainlink has playback support */
  5482. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5483. },
  5484. {
  5485. .name = MSM_DAILINK_NAME(Compress5),
  5486. .stream_name = "Compress5",
  5487. .cpu_dai_name = "MultiMedia12",
  5488. .platform_name = "msm-compress-dsp",
  5489. .dynamic = 1,
  5490. .dpcm_playback = 1,
  5491. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5492. SND_SOC_DPCM_TRIGGER_POST},
  5493. .codec_dai_name = "snd-soc-dummy-dai",
  5494. .codec_name = "snd-soc-dummy",
  5495. .ignore_suspend = 1,
  5496. .ignore_pmdown_time = 1,
  5497. /* this dainlink has playback support */
  5498. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5499. },
  5500. {
  5501. .name = MSM_DAILINK_NAME(Compress6),
  5502. .stream_name = "Compress6",
  5503. .cpu_dai_name = "MultiMedia13",
  5504. .platform_name = "msm-compress-dsp",
  5505. .dynamic = 1,
  5506. .dpcm_playback = 1,
  5507. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5508. SND_SOC_DPCM_TRIGGER_POST},
  5509. .codec_dai_name = "snd-soc-dummy-dai",
  5510. .codec_name = "snd-soc-dummy",
  5511. .ignore_suspend = 1,
  5512. .ignore_pmdown_time = 1,
  5513. /* this dainlink has playback support */
  5514. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5515. },
  5516. {
  5517. .name = MSM_DAILINK_NAME(Compress7),
  5518. .stream_name = "Compress7",
  5519. .cpu_dai_name = "MultiMedia14",
  5520. .platform_name = "msm-compress-dsp",
  5521. .dynamic = 1,
  5522. .dpcm_playback = 1,
  5523. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5524. SND_SOC_DPCM_TRIGGER_POST},
  5525. .codec_dai_name = "snd-soc-dummy-dai",
  5526. .codec_name = "snd-soc-dummy",
  5527. .ignore_suspend = 1,
  5528. .ignore_pmdown_time = 1,
  5529. /* this dainlink has playback support */
  5530. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5531. },
  5532. {
  5533. .name = MSM_DAILINK_NAME(Compress8),
  5534. .stream_name = "Compress8",
  5535. .cpu_dai_name = "MultiMedia15",
  5536. .platform_name = "msm-compress-dsp",
  5537. .dynamic = 1,
  5538. .dpcm_playback = 1,
  5539. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5540. SND_SOC_DPCM_TRIGGER_POST},
  5541. .codec_dai_name = "snd-soc-dummy-dai",
  5542. .codec_name = "snd-soc-dummy",
  5543. .ignore_suspend = 1,
  5544. .ignore_pmdown_time = 1,
  5545. /* this dainlink has playback support */
  5546. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5547. },
  5548. {
  5549. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5550. .stream_name = "MM_NOIRQ_2",
  5551. .cpu_dai_name = "MultiMedia16",
  5552. .platform_name = "msm-pcm-dsp-noirq",
  5553. .dynamic = 1,
  5554. .dpcm_playback = 1,
  5555. .dpcm_capture = 1,
  5556. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5557. SND_SOC_DPCM_TRIGGER_POST},
  5558. .codec_dai_name = "snd-soc-dummy-dai",
  5559. .codec_name = "snd-soc-dummy",
  5560. .ignore_suspend = 1,
  5561. .ignore_pmdown_time = 1,
  5562. /* this dainlink has playback support */
  5563. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5564. },
  5565. {
  5566. .name = "SLIMBUS_8 Hostless",
  5567. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5568. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5569. .platform_name = "msm-pcm-hostless",
  5570. .dynamic = 1,
  5571. .dpcm_capture = 1,
  5572. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5573. SND_SOC_DPCM_TRIGGER_POST},
  5574. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5575. .ignore_suspend = 1,
  5576. .codec_dai_name = "snd-soc-dummy-dai",
  5577. .codec_name = "snd-soc-dummy",
  5578. },
  5579. /* Hostless PCM purpose */
  5580. {
  5581. .name = "CDC_DMA Hostless",
  5582. .stream_name = "CDC_DMA Hostless",
  5583. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5584. .platform_name = "msm-pcm-hostless",
  5585. .dynamic = 1,
  5586. .dpcm_playback = 1,
  5587. .dpcm_capture = 1,
  5588. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5589. SND_SOC_DPCM_TRIGGER_POST},
  5590. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5591. .ignore_suspend = 1,
  5592. /* this dailink has playback support */
  5593. .ignore_pmdown_time = 1,
  5594. .codec_dai_name = "snd-soc-dummy-dai",
  5595. .codec_name = "snd-soc-dummy",
  5596. },
  5597. };
  5598. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5599. {
  5600. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5601. .stream_name = "WSA CDC DMA0 Capture",
  5602. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5603. .platform_name = "msm-pcm-hostless",
  5604. .codec_name = "bolero_codec",
  5605. .codec_dai_name = "wsa_macro_vifeedback",
  5606. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5607. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5608. .ignore_suspend = 1,
  5609. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5610. .ops = &msm_cdc_dma_be_ops,
  5611. },
  5612. };
  5613. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5614. {
  5615. .name = MSM_DAILINK_NAME(ASM Loopback),
  5616. .stream_name = "MultiMedia6",
  5617. .cpu_dai_name = "MultiMedia6",
  5618. .platform_name = "msm-pcm-loopback",
  5619. .dynamic = 1,
  5620. .dpcm_playback = 1,
  5621. .dpcm_capture = 1,
  5622. .codec_dai_name = "snd-soc-dummy-dai",
  5623. .codec_name = "snd-soc-dummy",
  5624. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5625. SND_SOC_DPCM_TRIGGER_POST},
  5626. .ignore_suspend = 1,
  5627. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5628. .ignore_pmdown_time = 1,
  5629. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5630. },
  5631. {
  5632. .name = "USB Audio Hostless",
  5633. .stream_name = "USB Audio Hostless",
  5634. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5635. .platform_name = "msm-pcm-hostless",
  5636. .dynamic = 1,
  5637. .dpcm_playback = 1,
  5638. .dpcm_capture = 1,
  5639. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5640. SND_SOC_DPCM_TRIGGER_POST},
  5641. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5642. .ignore_suspend = 1,
  5643. .ignore_pmdown_time = 1,
  5644. .codec_dai_name = "snd-soc-dummy-dai",
  5645. .codec_name = "snd-soc-dummy",
  5646. },
  5647. {
  5648. .name = "SLIMBUS_7 Hostless",
  5649. .stream_name = "SLIMBUS_7 Hostless",
  5650. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5651. .platform_name = "msm-pcm-hostless",
  5652. .dynamic = 1,
  5653. .dpcm_capture = 1,
  5654. .dpcm_playback = 1,
  5655. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5656. SND_SOC_DPCM_TRIGGER_POST},
  5657. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5658. .ignore_suspend = 1,
  5659. .ignore_pmdown_time = 1,
  5660. .codec_dai_name = "snd-soc-dummy-dai",
  5661. .codec_name = "snd-soc-dummy",
  5662. },
  5663. {
  5664. .name = MSM_DAILINK_NAME(Compr Capture),
  5665. .stream_name = "Compr Capture",
  5666. .cpu_dai_name = "MultiMedia18",
  5667. .platform_name = "msm-compress-dsp",
  5668. .dynamic = 1,
  5669. .dpcm_capture = 1,
  5670. .codec_dai_name = "snd-soc-dummy-dai",
  5671. .codec_name = "snd-soc-dummy",
  5672. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5673. SND_SOC_DPCM_TRIGGER_POST},
  5674. .ignore_pmdown_time = 1,
  5675. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5676. },
  5677. };
  5678. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5679. /* Backend AFE DAI Links */
  5680. {
  5681. .name = LPASS_BE_AFE_PCM_RX,
  5682. .stream_name = "AFE Playback",
  5683. .cpu_dai_name = "msm-dai-q6-dev.224",
  5684. .platform_name = "msm-pcm-routing",
  5685. .codec_name = "msm-stub-codec.1",
  5686. .codec_dai_name = "msm-stub-rx",
  5687. .no_pcm = 1,
  5688. .dpcm_playback = 1,
  5689. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5690. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5691. /* this dainlink has playback support */
  5692. .ignore_pmdown_time = 1,
  5693. .ignore_suspend = 1,
  5694. },
  5695. {
  5696. .name = LPASS_BE_AFE_PCM_TX,
  5697. .stream_name = "AFE Capture",
  5698. .cpu_dai_name = "msm-dai-q6-dev.225",
  5699. .platform_name = "msm-pcm-routing",
  5700. .codec_name = "msm-stub-codec.1",
  5701. .codec_dai_name = "msm-stub-tx",
  5702. .no_pcm = 1,
  5703. .dpcm_capture = 1,
  5704. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5705. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5706. .ignore_suspend = 1,
  5707. },
  5708. /* Incall Record Uplink BACK END DAI Link */
  5709. {
  5710. .name = LPASS_BE_INCALL_RECORD_TX,
  5711. .stream_name = "Voice Uplink Capture",
  5712. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5713. .platform_name = "msm-pcm-routing",
  5714. .codec_name = "msm-stub-codec.1",
  5715. .codec_dai_name = "msm-stub-tx",
  5716. .no_pcm = 1,
  5717. .dpcm_capture = 1,
  5718. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5719. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5720. .ignore_suspend = 1,
  5721. },
  5722. /* Incall Record Downlink BACK END DAI Link */
  5723. {
  5724. .name = LPASS_BE_INCALL_RECORD_RX,
  5725. .stream_name = "Voice Downlink Capture",
  5726. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5727. .platform_name = "msm-pcm-routing",
  5728. .codec_name = "msm-stub-codec.1",
  5729. .codec_dai_name = "msm-stub-tx",
  5730. .no_pcm = 1,
  5731. .dpcm_capture = 1,
  5732. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5733. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5734. .ignore_suspend = 1,
  5735. },
  5736. /* Incall Music BACK END DAI Link */
  5737. {
  5738. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5739. .stream_name = "Voice Farend Playback",
  5740. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5741. .platform_name = "msm-pcm-routing",
  5742. .codec_name = "msm-stub-codec.1",
  5743. .codec_dai_name = "msm-stub-rx",
  5744. .no_pcm = 1,
  5745. .dpcm_playback = 1,
  5746. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5747. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5748. .ignore_suspend = 1,
  5749. .ignore_pmdown_time = 1,
  5750. },
  5751. /* Incall Music 2 BACK END DAI Link */
  5752. {
  5753. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5754. .stream_name = "Voice2 Farend Playback",
  5755. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5756. .platform_name = "msm-pcm-routing",
  5757. .codec_name = "msm-stub-codec.1",
  5758. .codec_dai_name = "msm-stub-rx",
  5759. .no_pcm = 1,
  5760. .dpcm_playback = 1,
  5761. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5762. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5763. .ignore_suspend = 1,
  5764. .ignore_pmdown_time = 1,
  5765. },
  5766. {
  5767. .name = LPASS_BE_USB_AUDIO_RX,
  5768. .stream_name = "USB Audio Playback",
  5769. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5770. .platform_name = "msm-pcm-routing",
  5771. .codec_name = "msm-stub-codec.1",
  5772. .codec_dai_name = "msm-stub-rx",
  5773. .no_pcm = 1,
  5774. .dpcm_playback = 1,
  5775. .id = MSM_BACKEND_DAI_USB_RX,
  5776. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5777. .ignore_pmdown_time = 1,
  5778. .ignore_suspend = 1,
  5779. },
  5780. {
  5781. .name = LPASS_BE_USB_AUDIO_TX,
  5782. .stream_name = "USB Audio Capture",
  5783. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5784. .platform_name = "msm-pcm-routing",
  5785. .codec_name = "msm-stub-codec.1",
  5786. .codec_dai_name = "msm-stub-tx",
  5787. .no_pcm = 1,
  5788. .dpcm_capture = 1,
  5789. .id = MSM_BACKEND_DAI_USB_TX,
  5790. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5791. .ignore_suspend = 1,
  5792. },
  5793. {
  5794. .name = LPASS_BE_PRI_TDM_RX_0,
  5795. .stream_name = "Primary TDM0 Playback",
  5796. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5797. .platform_name = "msm-pcm-routing",
  5798. .codec_name = "msm-stub-codec.1",
  5799. .codec_dai_name = "msm-stub-rx",
  5800. .no_pcm = 1,
  5801. .dpcm_playback = 1,
  5802. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5803. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5804. .ops = &qcs405_tdm_be_ops,
  5805. .ignore_suspend = 1,
  5806. .ignore_pmdown_time = 1,
  5807. },
  5808. {
  5809. .name = LPASS_BE_PRI_TDM_TX_0,
  5810. .stream_name = "Primary TDM0 Capture",
  5811. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5812. .platform_name = "msm-pcm-routing",
  5813. .codec_name = "msm-stub-codec.1",
  5814. .codec_dai_name = "msm-stub-tx",
  5815. .no_pcm = 1,
  5816. .dpcm_capture = 1,
  5817. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5818. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5819. .ops = &qcs405_tdm_be_ops,
  5820. .ignore_suspend = 1,
  5821. },
  5822. {
  5823. .name = LPASS_BE_SEC_TDM_RX_0,
  5824. .stream_name = "Secondary TDM0 Playback",
  5825. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5826. .platform_name = "msm-pcm-routing",
  5827. .codec_name = "msm-stub-codec.1",
  5828. .codec_dai_name = "msm-stub-rx",
  5829. .no_pcm = 1,
  5830. .dpcm_playback = 1,
  5831. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5832. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5833. .ops = &qcs405_tdm_be_ops,
  5834. .ignore_suspend = 1,
  5835. .ignore_pmdown_time = 1,
  5836. },
  5837. {
  5838. .name = LPASS_BE_SEC_TDM_TX_0,
  5839. .stream_name = "Secondary TDM0 Capture",
  5840. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5841. .platform_name = "msm-pcm-routing",
  5842. .codec_name = "msm-stub-codec.1",
  5843. .codec_dai_name = "msm-stub-tx",
  5844. .no_pcm = 1,
  5845. .dpcm_capture = 1,
  5846. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5847. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5848. .ops = &qcs405_tdm_be_ops,
  5849. .ignore_suspend = 1,
  5850. },
  5851. {
  5852. .name = LPASS_BE_TERT_TDM_RX_0,
  5853. .stream_name = "Tertiary TDM0 Playback",
  5854. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5855. .platform_name = "msm-pcm-routing",
  5856. .codec_name = "msm-stub-codec.1",
  5857. .codec_dai_name = "msm-stub-rx",
  5858. .no_pcm = 1,
  5859. .dpcm_playback = 1,
  5860. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5862. .ops = &qcs405_tdm_be_ops,
  5863. .ignore_suspend = 1,
  5864. .ignore_pmdown_time = 1,
  5865. },
  5866. {
  5867. .name = LPASS_BE_TERT_TDM_TX_0,
  5868. .stream_name = "Tertiary TDM0 Capture",
  5869. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5870. .platform_name = "msm-pcm-routing",
  5871. .codec_name = "msm-stub-codec.1",
  5872. .codec_dai_name = "msm-stub-tx",
  5873. .no_pcm = 1,
  5874. .dpcm_capture = 1,
  5875. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5876. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5877. .ops = &qcs405_tdm_be_ops,
  5878. .ignore_suspend = 1,
  5879. },
  5880. {
  5881. .name = LPASS_BE_QUAT_TDM_RX_0,
  5882. .stream_name = "Quaternary TDM0 Playback",
  5883. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5884. .platform_name = "msm-pcm-routing",
  5885. .codec_name = "msm-stub-codec.1",
  5886. .codec_dai_name = "msm-stub-rx",
  5887. .no_pcm = 1,
  5888. .dpcm_playback = 1,
  5889. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5890. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5891. .ops = &qcs405_tdm_be_ops,
  5892. .ignore_suspend = 1,
  5893. .ignore_pmdown_time = 1,
  5894. },
  5895. {
  5896. .name = LPASS_BE_QUAT_TDM_TX_0,
  5897. .stream_name = "Quaternary TDM0 Capture",
  5898. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5899. .platform_name = "msm-pcm-routing",
  5900. .codec_name = "msm-stub-codec.1",
  5901. .codec_dai_name = "msm-stub-tx",
  5902. .no_pcm = 1,
  5903. .dpcm_capture = 1,
  5904. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5905. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5906. .ops = &qcs405_tdm_be_ops,
  5907. .ignore_suspend = 1,
  5908. },
  5909. {
  5910. .name = LPASS_BE_QUIN_TDM_RX_0,
  5911. .stream_name = "Quinary TDM0 Playback",
  5912. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5913. .platform_name = "msm-pcm-routing",
  5914. .codec_name = "msm-stub-codec.1",
  5915. .codec_dai_name = "msm-stub-rx",
  5916. .no_pcm = 1,
  5917. .dpcm_playback = 1,
  5918. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5919. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5920. .ops = &qcs405_tdm_be_ops,
  5921. .ignore_suspend = 1,
  5922. .ignore_pmdown_time = 1,
  5923. },
  5924. {
  5925. .name = LPASS_BE_QUIN_TDM_TX_0,
  5926. .stream_name = "Quinary TDM0 Capture",
  5927. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5928. .platform_name = "msm-pcm-routing",
  5929. .codec_name = "msm-stub-codec.1",
  5930. .codec_dai_name = "msm-stub-tx",
  5931. .no_pcm = 1,
  5932. .dpcm_capture = 1,
  5933. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5934. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5935. .ops = &qcs405_tdm_be_ops,
  5936. .ignore_suspend = 1,
  5937. },
  5938. };
  5939. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5940. {
  5941. .name = LPASS_BE_SLIMBUS_0_RX,
  5942. .stream_name = "Slimbus Playback",
  5943. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5944. .platform_name = "msm-pcm-routing",
  5945. .codec_name = "tasha_codec",
  5946. .codec_dai_name = "tasha_mix_rx1",
  5947. .no_pcm = 1,
  5948. .dpcm_playback = 1,
  5949. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5950. .init = &msm_audrx_init,
  5951. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5952. /* this dainlink has playback support */
  5953. .ignore_pmdown_time = 1,
  5954. .ignore_suspend = 1,
  5955. .ops = &msm_be_ops,
  5956. },
  5957. {
  5958. .name = LPASS_BE_SLIMBUS_0_TX,
  5959. .stream_name = "Slimbus Capture",
  5960. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5961. .platform_name = "msm-pcm-routing",
  5962. .codec_name = "tasha_codec",
  5963. .codec_dai_name = "tasha_tx1",
  5964. .no_pcm = 1,
  5965. .dpcm_capture = 1,
  5966. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5967. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5968. .ignore_suspend = 1,
  5969. .ops = &msm_be_ops,
  5970. },
  5971. {
  5972. .name = LPASS_BE_SLIMBUS_1_RX,
  5973. .stream_name = "Slimbus1 Playback",
  5974. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5975. .platform_name = "msm-pcm-routing",
  5976. .codec_name = "tasha_codec",
  5977. .codec_dai_name = "tasha_mix_rx1",
  5978. .no_pcm = 1,
  5979. .dpcm_playback = 1,
  5980. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5981. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5982. .ops = &msm_be_ops,
  5983. /* dai link has playback support */
  5984. .ignore_pmdown_time = 1,
  5985. .ignore_suspend = 1,
  5986. },
  5987. {
  5988. .name = LPASS_BE_SLIMBUS_1_TX,
  5989. .stream_name = "Slimbus1 Capture",
  5990. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5991. .platform_name = "msm-pcm-routing",
  5992. .codec_name = "tasha_codec",
  5993. .codec_dai_name = "tasha_tx3",
  5994. .no_pcm = 1,
  5995. .dpcm_capture = 1,
  5996. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5997. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5998. .ops = &msm_be_ops,
  5999. .ignore_suspend = 1,
  6000. },
  6001. {
  6002. .name = LPASS_BE_SLIMBUS_2_RX,
  6003. .stream_name = "Slimbus2 Playback",
  6004. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6005. .platform_name = "msm-pcm-routing",
  6006. .codec_name = "tasha_codec",
  6007. .codec_dai_name = "tasha_rx2",
  6008. .no_pcm = 1,
  6009. .dpcm_playback = 1,
  6010. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6011. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6012. .ops = &msm_be_ops,
  6013. .ignore_pmdown_time = 1,
  6014. .ignore_suspend = 1,
  6015. },
  6016. {
  6017. .name = LPASS_BE_SLIMBUS_3_RX,
  6018. .stream_name = "Slimbus3 Playback",
  6019. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6020. .platform_name = "msm-pcm-routing",
  6021. .codec_name = "tasha_codec",
  6022. .codec_dai_name = "tasha_mix_rx1",
  6023. .no_pcm = 1,
  6024. .dpcm_playback = 1,
  6025. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6026. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6027. .ops = &msm_be_ops,
  6028. /* dai link has playback support */
  6029. .ignore_pmdown_time = 1,
  6030. .ignore_suspend = 1,
  6031. },
  6032. {
  6033. .name = LPASS_BE_SLIMBUS_3_TX,
  6034. .stream_name = "Slimbus3 Capture",
  6035. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6036. .platform_name = "msm-pcm-routing",
  6037. .codec_name = "tasha_codec",
  6038. .codec_dai_name = "tasha_tx1",
  6039. .no_pcm = 1,
  6040. .dpcm_capture = 1,
  6041. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6042. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6043. .ops = &msm_be_ops,
  6044. .ignore_suspend = 1,
  6045. },
  6046. {
  6047. .name = LPASS_BE_SLIMBUS_4_RX,
  6048. .stream_name = "Slimbus4 Playback",
  6049. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6050. .platform_name = "msm-pcm-routing",
  6051. .codec_name = "tasha_codec",
  6052. .codec_dai_name = "tasha_mix_rx1",
  6053. .no_pcm = 1,
  6054. .dpcm_playback = 1,
  6055. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6056. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6057. .ops = &msm_be_ops,
  6058. /* dai link has playback support */
  6059. .ignore_pmdown_time = 1,
  6060. .ignore_suspend = 1,
  6061. },
  6062. {
  6063. .name = LPASS_BE_SLIMBUS_5_RX,
  6064. .stream_name = "Slimbus5 Playback",
  6065. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6066. .platform_name = "msm-pcm-routing",
  6067. .codec_name = "tasha_codec",
  6068. .codec_dai_name = "tasha_rx3",
  6069. .no_pcm = 1,
  6070. .dpcm_playback = 1,
  6071. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6072. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6073. .ops = &msm_be_ops,
  6074. /* dai link has playback support */
  6075. .ignore_pmdown_time = 1,
  6076. .ignore_suspend = 1,
  6077. },
  6078. {
  6079. .name = LPASS_BE_SLIMBUS_6_RX,
  6080. .stream_name = "Slimbus6 Playback",
  6081. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6082. .platform_name = "msm-pcm-routing",
  6083. .codec_name = "tasha_codec",
  6084. .codec_dai_name = "tasha_rx4",
  6085. .no_pcm = 1,
  6086. .dpcm_playback = 1,
  6087. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6088. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6089. .ops = &msm_be_ops,
  6090. /* dai link has playback support */
  6091. .ignore_pmdown_time = 1,
  6092. .ignore_suspend = 1,
  6093. },
  6094. /* Slimbus VI Recording */
  6095. {
  6096. .name = LPASS_BE_SLIMBUS_TX_VI,
  6097. .stream_name = "Slimbus4 Capture",
  6098. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6099. .platform_name = "msm-pcm-routing",
  6100. .codec_name = "tasha_codec",
  6101. .codec_dai_name = "tasha_vifeedback",
  6102. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6103. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6104. .ops = &msm_be_ops,
  6105. .ignore_suspend = 1,
  6106. .no_pcm = 1,
  6107. .dpcm_capture = 1,
  6108. .ignore_pmdown_time = 1,
  6109. },
  6110. };
  6111. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6112. {
  6113. .name = LPASS_BE_SLIMBUS_7_RX,
  6114. .stream_name = "Slimbus7 Playback",
  6115. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6116. .platform_name = "msm-pcm-routing",
  6117. .codec_name = "btfmslim_slave",
  6118. /* BT codec driver determines capabilities based on
  6119. * dai name, bt codecdai name should always contains
  6120. * supported usecase information
  6121. */
  6122. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6123. .no_pcm = 1,
  6124. .dpcm_playback = 1,
  6125. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6126. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6127. .ops = &msm_wcn_ops,
  6128. /* dai link has playback support */
  6129. .ignore_pmdown_time = 1,
  6130. .ignore_suspend = 1,
  6131. },
  6132. {
  6133. .name = LPASS_BE_SLIMBUS_7_TX,
  6134. .stream_name = "Slimbus7 Capture",
  6135. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6136. .platform_name = "msm-pcm-routing",
  6137. .codec_name = "btfmslim_slave",
  6138. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6139. .no_pcm = 1,
  6140. .dpcm_capture = 1,
  6141. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6142. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6143. .ops = &msm_wcn_ops,
  6144. .ignore_suspend = 1,
  6145. },
  6146. {
  6147. .name = LPASS_BE_SLIMBUS_8_TX,
  6148. .stream_name = "Slimbus8 Capture",
  6149. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6150. .platform_name = "msm-pcm-routing",
  6151. .codec_name = "btfmslim_slave",
  6152. .codec_dai_name = "btfm_fm_slim_tx",
  6153. .no_pcm = 1,
  6154. .dpcm_capture = 1,
  6155. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6156. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6157. .init = &msm_wcn_init,
  6158. .ops = &msm_wcn_ops,
  6159. .ignore_suspend = 1,
  6160. },
  6161. };
  6162. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6163. {
  6164. .name = LPASS_BE_PRI_MI2S_RX,
  6165. .stream_name = "Primary MI2S Playback",
  6166. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6167. .platform_name = "msm-pcm-routing",
  6168. .codec_name = "msm-stub-codec.1",
  6169. .codec_dai_name = "msm-stub-rx",
  6170. .no_pcm = 1,
  6171. .dpcm_playback = 1,
  6172. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6173. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6174. .ops = &msm_mi2s_be_ops,
  6175. .ignore_suspend = 1,
  6176. .ignore_pmdown_time = 1,
  6177. },
  6178. {
  6179. .name = LPASS_BE_PRI_MI2S_TX,
  6180. .stream_name = "Primary MI2S Capture",
  6181. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6182. .platform_name = "msm-pcm-routing",
  6183. .codec_name = "msm-stub-codec.1",
  6184. .codec_dai_name = "msm-stub-tx",
  6185. .no_pcm = 1,
  6186. .dpcm_capture = 1,
  6187. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6188. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6189. .ops = &msm_mi2s_be_ops,
  6190. .ignore_suspend = 1,
  6191. },
  6192. {
  6193. .name = LPASS_BE_SEC_MI2S_RX,
  6194. .stream_name = "Secondary MI2S Playback",
  6195. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6196. .platform_name = "msm-pcm-routing",
  6197. .codec_name = "msm-stub-codec.1",
  6198. .codec_dai_name = "msm-stub-rx",
  6199. .no_pcm = 1,
  6200. .dpcm_playback = 1,
  6201. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6202. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6203. .ops = &msm_mi2s_be_ops,
  6204. .ignore_suspend = 1,
  6205. .ignore_pmdown_time = 1,
  6206. },
  6207. {
  6208. .name = LPASS_BE_SEC_MI2S_TX,
  6209. .stream_name = "Secondary MI2S Capture",
  6210. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6211. .platform_name = "msm-pcm-routing",
  6212. .codec_name = "msm-stub-codec.1",
  6213. .codec_dai_name = "msm-stub-tx",
  6214. .no_pcm = 1,
  6215. .dpcm_capture = 1,
  6216. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6217. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6218. .ops = &msm_mi2s_be_ops,
  6219. .ignore_suspend = 1,
  6220. },
  6221. {
  6222. .name = LPASS_BE_TERT_MI2S_RX,
  6223. .stream_name = "Tertiary MI2S Playback",
  6224. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6225. .platform_name = "msm-pcm-routing",
  6226. .codec_name = "msm-stub-codec.1",
  6227. .codec_dai_name = "msm-stub-rx",
  6228. .no_pcm = 1,
  6229. .dpcm_playback = 1,
  6230. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6231. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6232. .ops = &msm_mi2s_be_ops,
  6233. .ignore_suspend = 1,
  6234. .ignore_pmdown_time = 1,
  6235. },
  6236. {
  6237. .name = LPASS_BE_TERT_MI2S_TX,
  6238. .stream_name = "Tertiary MI2S Capture",
  6239. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6240. .platform_name = "msm-pcm-routing",
  6241. .codec_name = "msm-stub-codec.1",
  6242. .codec_dai_name = "msm-stub-tx",
  6243. .no_pcm = 1,
  6244. .dpcm_capture = 1,
  6245. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6246. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6247. .ops = &msm_mi2s_be_ops,
  6248. .ignore_suspend = 1,
  6249. },
  6250. {
  6251. .name = LPASS_BE_QUAT_MI2S_RX,
  6252. .stream_name = "Quaternary MI2S Playback",
  6253. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6254. .platform_name = "msm-pcm-routing",
  6255. .codec_name = "msm-stub-codec.1",
  6256. .codec_dai_name = "msm-stub-rx",
  6257. .no_pcm = 1,
  6258. .dpcm_playback = 1,
  6259. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6260. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6261. .ops = &msm_mi2s_be_ops,
  6262. .ignore_suspend = 1,
  6263. .ignore_pmdown_time = 1,
  6264. },
  6265. {
  6266. .name = LPASS_BE_QUAT_MI2S_TX,
  6267. .stream_name = "Quaternary MI2S Capture",
  6268. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6269. .platform_name = "msm-pcm-routing",
  6270. .codec_name = "msm-stub-codec.1",
  6271. .codec_dai_name = "msm-stub-tx",
  6272. .no_pcm = 1,
  6273. .dpcm_capture = 1,
  6274. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6275. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6276. .ops = &msm_mi2s_be_ops,
  6277. .ignore_suspend = 1,
  6278. },
  6279. {
  6280. .name = LPASS_BE_QUIN_MI2S_RX,
  6281. .stream_name = "Quinary MI2S Playback",
  6282. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6283. .platform_name = "msm-pcm-routing",
  6284. .codec_name = "msm-stub-codec.1",
  6285. .codec_dai_name = "msm-stub-rx",
  6286. .no_pcm = 1,
  6287. .dpcm_playback = 1,
  6288. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6289. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6290. .ops = &msm_mi2s_be_ops,
  6291. .ignore_suspend = 1,
  6292. .ignore_pmdown_time = 1,
  6293. },
  6294. {
  6295. .name = LPASS_BE_QUIN_MI2S_TX,
  6296. .stream_name = "Quinary MI2S Capture",
  6297. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6298. .platform_name = "msm-pcm-routing",
  6299. .codec_name = "msm-stub-codec.1",
  6300. .codec_dai_name = "msm-stub-tx",
  6301. .no_pcm = 1,
  6302. .dpcm_capture = 1,
  6303. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6304. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6305. .ops = &msm_mi2s_be_ops,
  6306. .ignore_suspend = 1,
  6307. },
  6308. };
  6309. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6310. /* Primary AUX PCM Backend DAI Links */
  6311. {
  6312. .name = LPASS_BE_AUXPCM_RX,
  6313. .stream_name = "AUX PCM Playback",
  6314. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6315. .platform_name = "msm-pcm-routing",
  6316. .codec_name = "msm-stub-codec.1",
  6317. .codec_dai_name = "msm-stub-rx",
  6318. .no_pcm = 1,
  6319. .dpcm_playback = 1,
  6320. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6321. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6322. .ignore_pmdown_time = 1,
  6323. .ignore_suspend = 1,
  6324. },
  6325. {
  6326. .name = LPASS_BE_AUXPCM_TX,
  6327. .stream_name = "AUX PCM Capture",
  6328. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6329. .platform_name = "msm-pcm-routing",
  6330. .codec_name = "msm-stub-codec.1",
  6331. .codec_dai_name = "msm-stub-tx",
  6332. .no_pcm = 1,
  6333. .dpcm_capture = 1,
  6334. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6335. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6336. .ignore_suspend = 1,
  6337. },
  6338. /* Secondary AUX PCM Backend DAI Links */
  6339. {
  6340. .name = LPASS_BE_SEC_AUXPCM_RX,
  6341. .stream_name = "Sec AUX PCM Playback",
  6342. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6343. .platform_name = "msm-pcm-routing",
  6344. .codec_name = "msm-stub-codec.1",
  6345. .codec_dai_name = "msm-stub-rx",
  6346. .no_pcm = 1,
  6347. .dpcm_playback = 1,
  6348. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6349. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6350. .ignore_pmdown_time = 1,
  6351. .ignore_suspend = 1,
  6352. },
  6353. {
  6354. .name = LPASS_BE_SEC_AUXPCM_TX,
  6355. .stream_name = "Sec AUX PCM Capture",
  6356. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6357. .platform_name = "msm-pcm-routing",
  6358. .codec_name = "msm-stub-codec.1",
  6359. .codec_dai_name = "msm-stub-tx",
  6360. .no_pcm = 1,
  6361. .dpcm_capture = 1,
  6362. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6363. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6364. .ignore_suspend = 1,
  6365. },
  6366. /* Tertiary AUX PCM Backend DAI Links */
  6367. {
  6368. .name = LPASS_BE_TERT_AUXPCM_RX,
  6369. .stream_name = "Tert AUX PCM Playback",
  6370. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6371. .platform_name = "msm-pcm-routing",
  6372. .codec_name = "msm-stub-codec.1",
  6373. .codec_dai_name = "msm-stub-rx",
  6374. .no_pcm = 1,
  6375. .dpcm_playback = 1,
  6376. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6377. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6378. .ignore_suspend = 1,
  6379. },
  6380. {
  6381. .name = LPASS_BE_TERT_AUXPCM_TX,
  6382. .stream_name = "Tert AUX PCM Capture",
  6383. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6384. .platform_name = "msm-pcm-routing",
  6385. .codec_name = "msm-stub-codec.1",
  6386. .codec_dai_name = "msm-stub-tx",
  6387. .no_pcm = 1,
  6388. .dpcm_capture = 1,
  6389. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6390. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6391. .ignore_suspend = 1,
  6392. },
  6393. /* Quaternary AUX PCM Backend DAI Links */
  6394. {
  6395. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6396. .stream_name = "Quat AUX PCM Playback",
  6397. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6398. .platform_name = "msm-pcm-routing",
  6399. .codec_name = "msm-stub-codec.1",
  6400. .codec_dai_name = "msm-stub-rx",
  6401. .no_pcm = 1,
  6402. .dpcm_playback = 1,
  6403. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6404. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6405. .ignore_pmdown_time = 1,
  6406. .ignore_suspend = 1,
  6407. },
  6408. {
  6409. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6410. .stream_name = "Quat AUX PCM Capture",
  6411. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6412. .platform_name = "msm-pcm-routing",
  6413. .codec_name = "msm-stub-codec.1",
  6414. .codec_dai_name = "msm-stub-tx",
  6415. .no_pcm = 1,
  6416. .dpcm_capture = 1,
  6417. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6418. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6419. .ignore_suspend = 1,
  6420. },
  6421. /* Quinary AUX PCM Backend DAI Links */
  6422. {
  6423. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6424. .stream_name = "Quin AUX PCM Playback",
  6425. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6426. .platform_name = "msm-pcm-routing",
  6427. .codec_name = "msm-stub-codec.1",
  6428. .codec_dai_name = "msm-stub-rx",
  6429. .no_pcm = 1,
  6430. .dpcm_playback = 1,
  6431. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6432. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6433. .ignore_pmdown_time = 1,
  6434. .ignore_suspend = 1,
  6435. },
  6436. {
  6437. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6438. .stream_name = "Quin AUX PCM Capture",
  6439. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6440. .platform_name = "msm-pcm-routing",
  6441. .codec_name = "msm-stub-codec.1",
  6442. .codec_dai_name = "msm-stub-tx",
  6443. .no_pcm = 1,
  6444. .dpcm_capture = 1,
  6445. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6446. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6447. .ignore_suspend = 1,
  6448. },
  6449. };
  6450. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6451. /* WSA CDC DMA Backend DAI Links */
  6452. {
  6453. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6454. .stream_name = "WSA CDC DMA0 Playback",
  6455. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6456. .platform_name = "msm-pcm-routing",
  6457. .codec_name = "bolero_codec",
  6458. .codec_dai_name = "wsa_macro_rx1",
  6459. .no_pcm = 1,
  6460. .dpcm_playback = 1,
  6461. .init = &msm_wsa_cdc_dma_init,
  6462. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6463. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6464. .ignore_pmdown_time = 1,
  6465. .ignore_suspend = 1,
  6466. .ops = &msm_cdc_dma_be_ops,
  6467. },
  6468. {
  6469. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6470. .stream_name = "WSA CDC DMA1 Playback",
  6471. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6472. .platform_name = "msm-pcm-routing",
  6473. .codec_name = "bolero_codec",
  6474. .codec_dai_name = "wsa_macro_rx_mix",
  6475. .no_pcm = 1,
  6476. .dpcm_playback = 1,
  6477. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6478. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6479. .ignore_pmdown_time = 1,
  6480. .ignore_suspend = 1,
  6481. .ops = &msm_cdc_dma_be_ops,
  6482. },
  6483. {
  6484. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6485. .stream_name = "WSA CDC DMA1 Capture",
  6486. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6487. .platform_name = "msm-pcm-routing",
  6488. .codec_name = "bolero_codec",
  6489. .codec_dai_name = "wsa_macro_echo",
  6490. .no_pcm = 1,
  6491. .dpcm_capture = 1,
  6492. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6493. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6494. .ignore_suspend = 1,
  6495. .ops = &msm_cdc_dma_be_ops,
  6496. },
  6497. };
  6498. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6499. {
  6500. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6501. .stream_name = "VA CDC DMA0 Capture",
  6502. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6503. .platform_name = "msm-pcm-routing",
  6504. .codec_name = "bolero_codec",
  6505. .codec_dai_name = "va_macro_tx1",
  6506. .no_pcm = 1,
  6507. .dpcm_capture = 1,
  6508. .init = &msm_va_cdc_dma_init,
  6509. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6510. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6511. .ignore_suspend = 1,
  6512. .ops = &msm_cdc_dma_be_ops,
  6513. },
  6514. {
  6515. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6516. .stream_name = "VA CDC DMA1 Capture",
  6517. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6518. .platform_name = "msm-pcm-routing",
  6519. .codec_name = "bolero_codec",
  6520. .codec_dai_name = "va_macro_tx2",
  6521. .no_pcm = 1,
  6522. .dpcm_capture = 1,
  6523. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6524. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6525. .ignore_suspend = 1,
  6526. .ops = &msm_cdc_dma_be_ops,
  6527. },
  6528. };
  6529. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6530. {
  6531. .name = LPASS_BE_PRI_SPDIF_RX,
  6532. .stream_name = "Primary SPDIF Playback",
  6533. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6534. .platform_name = "msm-pcm-routing",
  6535. .codec_name = "msm-stub-codec.1",
  6536. .codec_dai_name = "msm-stub-rx",
  6537. .no_pcm = 1,
  6538. .dpcm_playback = 1,
  6539. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6540. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6541. .ops = &msm_spdif_be_ops,
  6542. .ignore_suspend = 1,
  6543. .ignore_pmdown_time = 1,
  6544. },
  6545. {
  6546. .name = LPASS_BE_PRI_SPDIF_TX,
  6547. .stream_name = "Primary SPDIF Capture",
  6548. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6549. .platform_name = "msm-pcm-routing",
  6550. .codec_name = "msm-stub-codec.1",
  6551. .codec_dai_name = "msm-stub-tx",
  6552. .no_pcm = 1,
  6553. .dpcm_capture = 1,
  6554. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6555. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6556. .ops = &msm_spdif_be_ops,
  6557. .ignore_suspend = 1,
  6558. },
  6559. {
  6560. .name = LPASS_BE_SEC_SPDIF_RX,
  6561. .stream_name = "Secondary SPDIF Playback",
  6562. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6563. .platform_name = "msm-pcm-routing",
  6564. .codec_name = "msm-stub-codec.1",
  6565. .codec_dai_name = "msm-stub-rx",
  6566. .no_pcm = 1,
  6567. .dpcm_playback = 1,
  6568. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6569. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6570. .ops = &msm_spdif_be_ops,
  6571. .ignore_suspend = 1,
  6572. .ignore_pmdown_time = 1,
  6573. },
  6574. {
  6575. .name = LPASS_BE_SEC_SPDIF_TX,
  6576. .stream_name = "Secondary SPDIF Capture",
  6577. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6578. .platform_name = "msm-pcm-routing",
  6579. .codec_name = "msm-stub-codec.1",
  6580. .codec_dai_name = "msm-stub-tx",
  6581. .no_pcm = 1,
  6582. .dpcm_capture = 1,
  6583. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6584. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6585. .ops = &msm_spdif_be_ops,
  6586. .ignore_suspend = 1,
  6587. },
  6588. };
  6589. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6590. ARRAY_SIZE(msm_common_dai_links) +
  6591. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6592. ARRAY_SIZE(msm_common_be_dai_links) +
  6593. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6594. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6595. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6596. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6597. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6598. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6599. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6600. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6601. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6602. {
  6603. int ret = 0;
  6604. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6605. &service_nb);
  6606. if (ret < 0)
  6607. pr_err("%s: Audio notifier register failed ret = %d\n",
  6608. __func__, ret);
  6609. return ret;
  6610. }
  6611. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6612. struct snd_ctl_elem_value *ucontrol)
  6613. {
  6614. int ret = 0;
  6615. int port_id;
  6616. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6617. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6618. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6619. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6620. (vad_enable < 0) || (vad_enable > 1) ||
  6621. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6622. pr_err("%s: Invalid arguments\n", __func__);
  6623. ret = -EINVAL;
  6624. goto done;
  6625. }
  6626. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6627. vad_enable, preroll_config, vad_intf);
  6628. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6629. if (ret) {
  6630. pr_err("%s: Invalid vad interface\n", __func__);
  6631. goto done;
  6632. }
  6633. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6634. done:
  6635. return ret;
  6636. }
  6637. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6638. {
  6639. int ret = 0;
  6640. uint32_t tasha_codec = 0;
  6641. ret = afe_cal_init_hwdep(card);
  6642. if (ret) {
  6643. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6644. ret = 0;
  6645. }
  6646. /* tasha late probe when it is present */
  6647. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6648. &tasha_codec);
  6649. if (ret) {
  6650. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6651. ret = 0;
  6652. } else {
  6653. if (tasha_codec) {
  6654. ret = msm_snd_card_tasha_late_probe(card);
  6655. if (ret)
  6656. dev_err(card->dev, "%s: tasha late probe err\n",
  6657. __func__);
  6658. }
  6659. }
  6660. return ret;
  6661. }
  6662. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6663. .name = "qcs405-snd-card",
  6664. .controls = msm_snd_controls,
  6665. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6666. .late_probe = msm_snd_card_codec_late_probe,
  6667. };
  6668. static int msm_populate_dai_link_component_of_node(
  6669. struct snd_soc_card *card)
  6670. {
  6671. int i, index, ret = 0;
  6672. struct device *cdev = card->dev;
  6673. struct snd_soc_dai_link *dai_link = card->dai_link;
  6674. struct device_node *np;
  6675. if (!cdev) {
  6676. pr_err("%s: Sound card device memory NULL\n", __func__);
  6677. return -ENODEV;
  6678. }
  6679. for (i = 0; i < card->num_links; i++) {
  6680. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6681. continue;
  6682. /* populate platform_of_node for snd card dai links */
  6683. if (dai_link[i].platform_name &&
  6684. !dai_link[i].platform_of_node) {
  6685. index = of_property_match_string(cdev->of_node,
  6686. "asoc-platform-names",
  6687. dai_link[i].platform_name);
  6688. if (index < 0) {
  6689. pr_err("%s: No match found for platform name: %s\n",
  6690. __func__, dai_link[i].platform_name);
  6691. ret = index;
  6692. goto err;
  6693. }
  6694. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6695. index);
  6696. if (!np) {
  6697. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6698. __func__, dai_link[i].platform_name,
  6699. index);
  6700. ret = -ENODEV;
  6701. goto err;
  6702. }
  6703. dai_link[i].platform_of_node = np;
  6704. dai_link[i].platform_name = NULL;
  6705. }
  6706. /* populate cpu_of_node for snd card dai links */
  6707. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6708. index = of_property_match_string(cdev->of_node,
  6709. "asoc-cpu-names",
  6710. dai_link[i].cpu_dai_name);
  6711. if (index >= 0) {
  6712. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6713. index);
  6714. if (!np) {
  6715. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6716. __func__,
  6717. dai_link[i].cpu_dai_name);
  6718. ret = -ENODEV;
  6719. goto err;
  6720. }
  6721. dai_link[i].cpu_of_node = np;
  6722. dai_link[i].cpu_dai_name = NULL;
  6723. }
  6724. }
  6725. /* populate codec_of_node for snd card dai links */
  6726. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6727. index = of_property_match_string(cdev->of_node,
  6728. "asoc-codec-names",
  6729. dai_link[i].codec_name);
  6730. if (index < 0)
  6731. continue;
  6732. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6733. index);
  6734. if (!np) {
  6735. pr_err("%s: retrieving phandle for codec %s failed\n",
  6736. __func__, dai_link[i].codec_name);
  6737. ret = -ENODEV;
  6738. goto err;
  6739. }
  6740. dai_link[i].codec_of_node = np;
  6741. dai_link[i].codec_name = NULL;
  6742. }
  6743. }
  6744. err:
  6745. return ret;
  6746. }
  6747. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6748. /* FrontEnd DAI Links */
  6749. {
  6750. .name = "MSMSTUB Media1",
  6751. .stream_name = "MultiMedia1",
  6752. .cpu_dai_name = "MultiMedia1",
  6753. .platform_name = "msm-pcm-dsp.0",
  6754. .dynamic = 1,
  6755. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6756. .dpcm_playback = 1,
  6757. .dpcm_capture = 1,
  6758. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6759. SND_SOC_DPCM_TRIGGER_POST},
  6760. .codec_dai_name = "snd-soc-dummy-dai",
  6761. .codec_name = "snd-soc-dummy",
  6762. .ignore_suspend = 1,
  6763. /* this dainlink has playback support */
  6764. .ignore_pmdown_time = 1,
  6765. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6766. },
  6767. };
  6768. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6769. /* Backend DAI Links */
  6770. {
  6771. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6772. .stream_name = "VA CDC DMA0 Capture",
  6773. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6774. .platform_name = "msm-pcm-routing",
  6775. .codec_name = "bolero_codec",
  6776. .codec_dai_name = "va_macro_tx1",
  6777. .no_pcm = 1,
  6778. .dpcm_capture = 1,
  6779. .init = &msm_va_cdc_dma_init,
  6780. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6781. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6782. .ignore_suspend = 1,
  6783. .ops = &msm_cdc_dma_be_ops,
  6784. },
  6785. {
  6786. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6787. .stream_name = "VA CDC DMA1 Capture",
  6788. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6789. .platform_name = "msm-pcm-routing",
  6790. .codec_name = "bolero_codec",
  6791. .codec_dai_name = "va_macro_tx2",
  6792. .no_pcm = 1,
  6793. .dpcm_capture = 1,
  6794. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6795. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6796. .ignore_suspend = 1,
  6797. .ops = &msm_cdc_dma_be_ops,
  6798. },
  6799. };
  6800. static struct snd_soc_dai_link msm_stub_dai_links[
  6801. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6802. ARRAY_SIZE(msm_stub_be_dai_links)];
  6803. struct snd_soc_card snd_soc_card_stub_msm = {
  6804. .name = "qcs405-stub-snd-card",
  6805. };
  6806. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6807. { .compatible = "qcom,qcs405-asoc-snd",
  6808. .data = "codec"},
  6809. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6810. .data = "stub_codec"},
  6811. {},
  6812. };
  6813. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6814. {
  6815. struct snd_soc_card *card = NULL;
  6816. struct snd_soc_dai_link *dailink;
  6817. int total_links = 0;
  6818. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6819. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6820. uint32_t spdif_audio_intf = 0;
  6821. const struct of_device_id *match;
  6822. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6823. int rc = 0;
  6824. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6825. if (!match) {
  6826. dev_err(dev, "%s: No DT match found for sound card\n",
  6827. __func__);
  6828. return NULL;
  6829. }
  6830. if (!strcmp(match->data, "codec")) {
  6831. card = &snd_soc_card_qcs405_msm;
  6832. memcpy(msm_qcs405_dai_links + total_links,
  6833. msm_common_dai_links,
  6834. sizeof(msm_common_dai_links));
  6835. total_links += ARRAY_SIZE(msm_common_dai_links);
  6836. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6837. &wsa_bolero_codec);
  6838. if (rc) {
  6839. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6840. __func__);
  6841. } else {
  6842. if (wsa_bolero_codec) {
  6843. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6844. __func__);
  6845. memcpy(msm_qcs405_dai_links + total_links,
  6846. msm_bolero_fe_dai_links,
  6847. sizeof(msm_bolero_fe_dai_links));
  6848. total_links +=
  6849. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6850. }
  6851. }
  6852. memcpy(msm_qcs405_dai_links + total_links,
  6853. msm_common_misc_fe_dai_links,
  6854. sizeof(msm_common_misc_fe_dai_links));
  6855. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6856. memcpy(msm_qcs405_dai_links + total_links,
  6857. msm_common_be_dai_links,
  6858. sizeof(msm_common_be_dai_links));
  6859. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6860. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6861. &tasha_codec);
  6862. if (rc) {
  6863. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6864. __func__);
  6865. } else {
  6866. if (tasha_codec) {
  6867. memcpy(msm_qcs405_dai_links + total_links,
  6868. msm_tasha_be_dai_links,
  6869. sizeof(msm_tasha_be_dai_links));
  6870. total_links +=
  6871. ARRAY_SIZE(msm_tasha_be_dai_links);
  6872. }
  6873. }
  6874. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6875. &va_bolero_codec);
  6876. if (rc) {
  6877. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6878. __func__);
  6879. } else {
  6880. if (va_bolero_codec) {
  6881. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6882. __func__);
  6883. memcpy(msm_qcs405_dai_links + total_links,
  6884. msm_va_cdc_dma_be_dai_links,
  6885. sizeof(msm_va_cdc_dma_be_dai_links));
  6886. total_links +=
  6887. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6888. }
  6889. }
  6890. if (wsa_bolero_codec) {
  6891. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6892. __func__);
  6893. memcpy(msm_qcs405_dai_links + total_links,
  6894. msm_wsa_cdc_dma_be_dai_links,
  6895. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6896. total_links +=
  6897. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6898. }
  6899. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6900. &mi2s_audio_intf);
  6901. if (rc) {
  6902. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6903. __func__);
  6904. } else {
  6905. if (mi2s_audio_intf) {
  6906. memcpy(msm_qcs405_dai_links + total_links,
  6907. msm_mi2s_be_dai_links,
  6908. sizeof(msm_mi2s_be_dai_links));
  6909. total_links +=
  6910. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6911. }
  6912. }
  6913. rc = of_property_read_u32(dev->of_node,
  6914. "qcom,auxpcm-audio-intf",
  6915. &auxpcm_audio_intf);
  6916. if (rc) {
  6917. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6918. __func__);
  6919. } else {
  6920. if (auxpcm_audio_intf) {
  6921. memcpy(msm_qcs405_dai_links + total_links,
  6922. msm_auxpcm_be_dai_links,
  6923. sizeof(msm_auxpcm_be_dai_links));
  6924. total_links +=
  6925. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6926. }
  6927. }
  6928. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  6929. &spdif_audio_intf);
  6930. if (rc) {
  6931. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  6932. __func__);
  6933. } else {
  6934. if (spdif_audio_intf) {
  6935. memcpy(msm_qcs405_dai_links + total_links,
  6936. msm_spdif_be_dai_links,
  6937. sizeof(msm_spdif_be_dai_links));
  6938. total_links +=
  6939. ARRAY_SIZE(msm_spdif_be_dai_links);
  6940. /* enable spdif coax pins */
  6941. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  6942. spdif_pin_ctl =
  6943. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  6944. iowrite32(0xc0, spdif_cfg);
  6945. iowrite32(0x2220, spdif_pin_ctl);
  6946. }
  6947. }
  6948. dailink = msm_qcs405_dai_links;
  6949. } else if (!strcmp(match->data, "stub_codec")) {
  6950. card = &snd_soc_card_stub_msm;
  6951. memcpy(msm_stub_dai_links + total_links,
  6952. msm_stub_fe_dai_links,
  6953. sizeof(msm_stub_fe_dai_links));
  6954. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6955. memcpy(msm_stub_dai_links + total_links,
  6956. msm_stub_be_dai_links,
  6957. sizeof(msm_stub_be_dai_links));
  6958. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6959. dailink = msm_stub_dai_links;
  6960. }
  6961. if (card) {
  6962. card->dai_link = dailink;
  6963. card->num_links = total_links;
  6964. }
  6965. return card;
  6966. }
  6967. static int msm_wsa881x_init(struct snd_soc_component *component)
  6968. {
  6969. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6970. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6971. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6972. SPKR_L_BOOST, SPKR_L_VI};
  6973. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6974. SPKR_R_BOOST, SPKR_R_VI};
  6975. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6976. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6977. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6978. struct msm_asoc_mach_data *pdata;
  6979. struct snd_soc_dapm_context *dapm;
  6980. int ret = 0;
  6981. if (!codec) {
  6982. pr_err("%s codec is NULL\n", __func__);
  6983. return -EINVAL;
  6984. }
  6985. dapm = snd_soc_codec_get_dapm(codec);
  6986. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6987. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6988. __func__, codec->component.name);
  6989. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6990. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6991. &ch_rate[0], &spkleft_port_types[0]);
  6992. if (dapm->component) {
  6993. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6994. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6995. }
  6996. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6997. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6998. __func__, codec->component.name);
  6999. wsa881x_set_channel_map(codec, &spkright_ports[0],
  7000. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7001. &ch_rate[0], &spkright_port_types[0]);
  7002. if (dapm->component) {
  7003. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7004. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7005. }
  7006. } else {
  7007. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  7008. codec->component.name);
  7009. ret = -EINVAL;
  7010. goto err;
  7011. }
  7012. pdata = snd_soc_card_get_drvdata(component->card);
  7013. if (pdata && pdata->codec_root)
  7014. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7015. codec);
  7016. err:
  7017. return ret;
  7018. }
  7019. static int msm_init_wsa_dev(struct platform_device *pdev,
  7020. struct snd_soc_card *card)
  7021. {
  7022. struct device_node *wsa_of_node;
  7023. u32 wsa_max_devs;
  7024. u32 wsa_dev_cnt;
  7025. int i;
  7026. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7027. const char *wsa_auxdev_name_prefix[1];
  7028. char *dev_name_str = NULL;
  7029. int found = 0;
  7030. int ret = 0;
  7031. /* Get maximum WSA device count for this platform */
  7032. ret = of_property_read_u32(pdev->dev.of_node,
  7033. "qcom,wsa-max-devs", &wsa_max_devs);
  7034. if (ret) {
  7035. dev_info(&pdev->dev,
  7036. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7037. __func__, pdev->dev.of_node->full_name, ret);
  7038. card->num_aux_devs = 0;
  7039. return 0;
  7040. }
  7041. if (wsa_max_devs == 0) {
  7042. dev_warn(&pdev->dev,
  7043. "%s: Max WSA devices is 0 for this target?\n",
  7044. __func__);
  7045. card->num_aux_devs = 0;
  7046. return 0;
  7047. }
  7048. /* Get count of WSA device phandles for this platform */
  7049. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7050. "qcom,wsa-devs", NULL);
  7051. if (wsa_dev_cnt == -ENOENT) {
  7052. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7053. __func__);
  7054. goto err;
  7055. } else if (wsa_dev_cnt <= 0) {
  7056. dev_err(&pdev->dev,
  7057. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7058. __func__, wsa_dev_cnt);
  7059. ret = -EINVAL;
  7060. goto err;
  7061. }
  7062. /*
  7063. * Expect total phandles count to be NOT less than maximum possible
  7064. * WSA count. However, if it is less, then assign same value to
  7065. * max count as well.
  7066. */
  7067. if (wsa_dev_cnt < wsa_max_devs) {
  7068. dev_dbg(&pdev->dev,
  7069. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7070. __func__, wsa_max_devs, wsa_dev_cnt);
  7071. wsa_max_devs = wsa_dev_cnt;
  7072. }
  7073. /* Make sure prefix string passed for each WSA device */
  7074. ret = of_property_count_strings(pdev->dev.of_node,
  7075. "qcom,wsa-aux-dev-prefix");
  7076. if (ret != wsa_dev_cnt) {
  7077. dev_err(&pdev->dev,
  7078. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7079. __func__, wsa_dev_cnt, ret);
  7080. ret = -EINVAL;
  7081. goto err;
  7082. }
  7083. /*
  7084. * Alloc mem to store phandle and index info of WSA device, if already
  7085. * registered with ALSA core
  7086. */
  7087. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7088. sizeof(struct msm_wsa881x_dev_info),
  7089. GFP_KERNEL);
  7090. if (!wsa881x_dev_info) {
  7091. ret = -ENOMEM;
  7092. goto err;
  7093. }
  7094. /*
  7095. * search and check whether all WSA devices are already
  7096. * registered with ALSA core or not. If found a node, store
  7097. * the node and the index in a local array of struct for later
  7098. * use.
  7099. */
  7100. for (i = 0; i < wsa_dev_cnt; i++) {
  7101. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7102. "qcom,wsa-devs", i);
  7103. if (unlikely(!wsa_of_node)) {
  7104. /* we should not be here */
  7105. dev_err(&pdev->dev,
  7106. "%s: wsa dev node is not present\n",
  7107. __func__);
  7108. ret = -EINVAL;
  7109. goto err_free_dev_info;
  7110. }
  7111. if (soc_find_component(wsa_of_node, NULL)) {
  7112. /* WSA device registered with ALSA core */
  7113. wsa881x_dev_info[found].of_node = wsa_of_node;
  7114. wsa881x_dev_info[found].index = i;
  7115. found++;
  7116. if (found == wsa_max_devs)
  7117. break;
  7118. }
  7119. }
  7120. if (found < wsa_max_devs) {
  7121. dev_err(&pdev->dev,
  7122. "%s: failed to find %d components. Found only %d\n",
  7123. __func__, wsa_max_devs, found);
  7124. return -EPROBE_DEFER;
  7125. }
  7126. dev_info(&pdev->dev,
  7127. "%s: found %d wsa881x devices registered with ALSA core\n",
  7128. __func__, found);
  7129. card->num_aux_devs = wsa_max_devs;
  7130. card->num_configs = wsa_max_devs;
  7131. /* Alloc array of AUX devs struct */
  7132. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7133. sizeof(struct snd_soc_aux_dev),
  7134. GFP_KERNEL);
  7135. if (!msm_aux_dev) {
  7136. ret = -ENOMEM;
  7137. goto err_free_dev_info;
  7138. }
  7139. /* Alloc array of codec conf struct */
  7140. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7141. sizeof(struct snd_soc_codec_conf),
  7142. GFP_KERNEL);
  7143. if (!msm_codec_conf) {
  7144. ret = -ENOMEM;
  7145. goto err_free_aux_dev;
  7146. }
  7147. for (i = 0; i < card->num_aux_devs; i++) {
  7148. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7149. GFP_KERNEL);
  7150. if (!dev_name_str) {
  7151. ret = -ENOMEM;
  7152. goto err_free_cdc_conf;
  7153. }
  7154. ret = of_property_read_string_index(pdev->dev.of_node,
  7155. "qcom,wsa-aux-dev-prefix",
  7156. wsa881x_dev_info[i].index,
  7157. wsa_auxdev_name_prefix);
  7158. if (ret) {
  7159. dev_err(&pdev->dev,
  7160. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7161. __func__, ret);
  7162. ret = -EINVAL;
  7163. goto err_free_dev_name_str;
  7164. }
  7165. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7166. msm_aux_dev[i].name = dev_name_str;
  7167. msm_aux_dev[i].codec_name = NULL;
  7168. msm_aux_dev[i].codec_of_node =
  7169. wsa881x_dev_info[i].of_node;
  7170. msm_aux_dev[i].init = msm_wsa881x_init;
  7171. msm_codec_conf[i].dev_name = NULL;
  7172. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7173. msm_codec_conf[i].of_node =
  7174. wsa881x_dev_info[i].of_node;
  7175. }
  7176. card->codec_conf = msm_codec_conf;
  7177. card->aux_dev = msm_aux_dev;
  7178. return 0;
  7179. err_free_dev_name_str:
  7180. devm_kfree(&pdev->dev, dev_name_str);
  7181. err_free_cdc_conf:
  7182. devm_kfree(&pdev->dev, msm_codec_conf);
  7183. err_free_aux_dev:
  7184. devm_kfree(&pdev->dev, msm_aux_dev);
  7185. err_free_dev_info:
  7186. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7187. err:
  7188. return ret;
  7189. }
  7190. static int msm_csra66x0_init(struct snd_soc_component *component)
  7191. {
  7192. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7193. if (!codec) {
  7194. pr_err("%s codec is NULL\n", __func__);
  7195. return -EINVAL;
  7196. }
  7197. return 0;
  7198. }
  7199. static int msm_init_csra_dev(struct platform_device *pdev,
  7200. struct snd_soc_card *card)
  7201. {
  7202. struct device_node *csra_of_node;
  7203. u32 csra_max_devs;
  7204. u32 csra_dev_cnt;
  7205. char *dev_name_str = NULL;
  7206. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7207. const char *csra_auxdev_name_prefix[1];
  7208. int i;
  7209. int found = 0;
  7210. int ret = 0;
  7211. /* Get maximum CSRA device count for this platform */
  7212. ret = of_property_read_u32(pdev->dev.of_node,
  7213. "qcom,csra-max-devs", &csra_max_devs);
  7214. if (ret) {
  7215. dev_info(&pdev->dev,
  7216. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7217. __func__, pdev->dev.of_node->full_name, ret);
  7218. card->num_aux_devs = 0;
  7219. return 0;
  7220. }
  7221. if (csra_max_devs == 0) {
  7222. dev_warn(&pdev->dev,
  7223. "%s: Max CSRA devices is 0 for this target?\n",
  7224. __func__);
  7225. return 0;
  7226. }
  7227. /* Get count of CSRA device phandles for this platform */
  7228. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7229. "qcom,csra-devs", NULL);
  7230. if (csra_dev_cnt == -ENOENT) {
  7231. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7232. __func__);
  7233. goto err;
  7234. } else if (csra_dev_cnt <= 0) {
  7235. dev_err(&pdev->dev,
  7236. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7237. __func__, csra_dev_cnt);
  7238. ret = -EINVAL;
  7239. goto err;
  7240. }
  7241. /*
  7242. * Expect total phandles count to be NOT less than maximum possible
  7243. * CSRA count. However, if it is less, then assign same value to
  7244. * max count as well.
  7245. */
  7246. if (csra_dev_cnt < csra_max_devs) {
  7247. dev_dbg(&pdev->dev,
  7248. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7249. __func__, csra_max_devs, csra_dev_cnt);
  7250. csra_max_devs = csra_dev_cnt;
  7251. }
  7252. /* Make sure prefix string passed for each CSRA device */
  7253. ret = of_property_count_strings(pdev->dev.of_node,
  7254. "qcom,csra-aux-dev-prefix");
  7255. if (ret != csra_dev_cnt) {
  7256. dev_err(&pdev->dev,
  7257. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7258. __func__, csra_dev_cnt, ret);
  7259. ret = -EINVAL;
  7260. goto err;
  7261. }
  7262. /*
  7263. * Alloc mem to store phandle and index info of CSRA device, if already
  7264. * registered with ALSA core
  7265. */
  7266. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7267. sizeof(struct msm_csra66x0_dev_info),
  7268. GFP_KERNEL);
  7269. if (!csra66x0_dev_info) {
  7270. ret = -ENOMEM;
  7271. goto err;
  7272. }
  7273. /*
  7274. * search and check whether all CSRA devices are already
  7275. * registered with ALSA core or not. If found a node, store
  7276. * the node and the index in a local array of struct for later
  7277. * use.
  7278. */
  7279. for (i = 0; i < csra_dev_cnt; i++) {
  7280. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7281. "qcom,csra-devs", i);
  7282. if (unlikely(!csra_of_node)) {
  7283. /* we should not be here */
  7284. dev_err(&pdev->dev,
  7285. "%s: csra dev node is not present\n",
  7286. __func__);
  7287. ret = -EINVAL;
  7288. goto err_free_dev_info;
  7289. }
  7290. if (soc_find_component(csra_of_node, NULL)) {
  7291. /* CSRA device registered with ALSA core */
  7292. csra66x0_dev_info[found].of_node = csra_of_node;
  7293. csra66x0_dev_info[found].index = i;
  7294. found++;
  7295. if (found == csra_max_devs)
  7296. break;
  7297. }
  7298. }
  7299. if (found < csra_max_devs) {
  7300. dev_dbg(&pdev->dev,
  7301. "%s: failed to find %d components. Found only %d\n",
  7302. __func__, csra_max_devs, found);
  7303. return -EPROBE_DEFER;
  7304. }
  7305. dev_info(&pdev->dev,
  7306. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7307. __func__, found);
  7308. card->num_aux_devs = csra_max_devs;
  7309. card->num_configs = csra_max_devs;
  7310. /* Alloc array of AUX devs struct */
  7311. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7312. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7313. if (!msm_aux_dev) {
  7314. ret = -ENOMEM;
  7315. goto err_free_dev_info;
  7316. }
  7317. /* Alloc array of codec conf struct */
  7318. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7319. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7320. if (!msm_codec_conf) {
  7321. ret = -ENOMEM;
  7322. goto err_free_aux_dev;
  7323. }
  7324. for (i = 0; i < card->num_aux_devs; i++) {
  7325. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7326. GFP_KERNEL);
  7327. if (!dev_name_str) {
  7328. ret = -ENOMEM;
  7329. goto err_free_cdc_conf;
  7330. }
  7331. ret = of_property_read_string_index(pdev->dev.of_node,
  7332. "qcom,csra-aux-dev-prefix",
  7333. csra66x0_dev_info[i].index,
  7334. csra_auxdev_name_prefix);
  7335. if (ret) {
  7336. dev_err(&pdev->dev,
  7337. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7338. __func__, ret);
  7339. ret = -EINVAL;
  7340. goto err_free_dev_name_str;
  7341. }
  7342. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7343. msm_aux_dev[i].name = dev_name_str;
  7344. msm_aux_dev[i].codec_name = NULL;
  7345. msm_aux_dev[i].codec_of_node =
  7346. csra66x0_dev_info[i].of_node;
  7347. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7348. msm_codec_conf[i].dev_name = NULL;
  7349. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7350. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7351. }
  7352. card->codec_conf = msm_codec_conf;
  7353. card->aux_dev = msm_aux_dev;
  7354. return 0;
  7355. err_free_dev_name_str:
  7356. devm_kfree(&pdev->dev, dev_name_str);
  7357. err_free_cdc_conf:
  7358. devm_kfree(&pdev->dev, msm_codec_conf);
  7359. err_free_aux_dev:
  7360. devm_kfree(&pdev->dev, msm_aux_dev);
  7361. err_free_dev_info:
  7362. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7363. err:
  7364. return ret;
  7365. }
  7366. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7367. {
  7368. int count;
  7369. u32 mi2s_master_slave[MI2S_MAX];
  7370. int ret;
  7371. for (count = 0; count < MI2S_MAX; count++) {
  7372. mutex_init(&mi2s_intf_conf[count].lock);
  7373. mi2s_intf_conf[count].ref_cnt = 0;
  7374. }
  7375. ret = of_property_read_u32_array(pdev->dev.of_node,
  7376. "qcom,msm-mi2s-master",
  7377. mi2s_master_slave, MI2S_MAX);
  7378. if (ret) {
  7379. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7380. __func__);
  7381. } else {
  7382. for (count = 0; count < MI2S_MAX; count++) {
  7383. mi2s_intf_conf[count].msm_is_mi2s_master =
  7384. mi2s_master_slave[count];
  7385. }
  7386. }
  7387. }
  7388. static void msm_i2s_auxpcm_deinit(void)
  7389. {
  7390. int count;
  7391. for (count = 0; count < MI2S_MAX; count++) {
  7392. mutex_destroy(&mi2s_intf_conf[count].lock);
  7393. mi2s_intf_conf[count].ref_cnt = 0;
  7394. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7395. }
  7396. }
  7397. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7398. {
  7399. struct snd_soc_card *card;
  7400. struct msm_asoc_mach_data *pdata;
  7401. int ret;
  7402. u32 val;
  7403. if (!pdev->dev.of_node) {
  7404. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7405. return -EINVAL;
  7406. }
  7407. pdata = devm_kzalloc(&pdev->dev,
  7408. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7409. if (!pdata)
  7410. return -ENOMEM;
  7411. card = populate_snd_card_dailinks(&pdev->dev);
  7412. if (!card) {
  7413. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7414. ret = -EINVAL;
  7415. goto err;
  7416. }
  7417. card->dev = &pdev->dev;
  7418. platform_set_drvdata(pdev, card);
  7419. snd_soc_card_set_drvdata(card, pdata);
  7420. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7421. if (ret) {
  7422. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7423. ret);
  7424. goto err;
  7425. }
  7426. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7427. if (ret) {
  7428. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7429. ret);
  7430. goto err;
  7431. }
  7432. ret = msm_populate_dai_link_component_of_node(card);
  7433. if (ret) {
  7434. ret = -EPROBE_DEFER;
  7435. goto err;
  7436. }
  7437. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7438. if (ret) {
  7439. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7440. val = 0;
  7441. }
  7442. if (val) {
  7443. ret = msm_init_csra_dev(pdev, card);
  7444. if (ret)
  7445. goto err;
  7446. } else {
  7447. ret = msm_init_wsa_dev(pdev, card);
  7448. if (ret)
  7449. goto err;
  7450. }
  7451. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7452. "qcom,cdc-dmic01-gpios",
  7453. 0);
  7454. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7455. "qcom,cdc-dmic23-gpios",
  7456. 0);
  7457. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7458. "qcom,cdc-dmic45-gpios",
  7459. 0);
  7460. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7461. "qcom,cdc-dmic67-gpios",
  7462. 0);
  7463. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7464. if (ret == -EPROBE_DEFER) {
  7465. if (codec_reg_done)
  7466. ret = -EINVAL;
  7467. goto err;
  7468. } else if (ret) {
  7469. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7470. ret);
  7471. goto err;
  7472. }
  7473. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7474. spdev = pdev;
  7475. /* Parse pinctrl info from devicetree */
  7476. ret = msm_get_pinctrl(pdev);
  7477. if (!ret) {
  7478. pr_debug("%s: pinctrl parsing successful\n", __func__);
  7479. } else {
  7480. dev_dbg(&pdev->dev,
  7481. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  7482. __func__, ret);
  7483. ret = 0;
  7484. }
  7485. msm_i2s_auxpcm_init(pdev);
  7486. is_initial_boot = true;
  7487. return 0;
  7488. err:
  7489. msm_release_pinctrl(pdev);
  7490. return ret;
  7491. }
  7492. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7493. {
  7494. audio_notifier_deregister("qcs405");
  7495. msm_i2s_auxpcm_deinit();
  7496. msm_release_pinctrl(pdev);
  7497. return 0;
  7498. }
  7499. static struct platform_driver qcs405_asoc_machine_driver = {
  7500. .driver = {
  7501. .name = DRV_NAME,
  7502. .owner = THIS_MODULE,
  7503. .pm = &snd_soc_pm_ops,
  7504. .of_match_table = qcs405_asoc_machine_of_match,
  7505. },
  7506. .probe = msm_asoc_machine_probe,
  7507. .remove = msm_asoc_machine_remove,
  7508. };
  7509. module_platform_driver(qcs405_asoc_machine_driver);
  7510. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7511. MODULE_LICENSE("GPL v2");
  7512. MODULE_ALIAS("platform:" DRV_NAME);
  7513. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);