dp_tx.c 112 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #ifdef QCA_TX_LIMIT_CHECK
  63. /**
  64. * dp_tx_limit_check - Check if allocated tx descriptors reached
  65. * soc max limit and pdev max limit
  66. * @vdev: DP vdev handle
  67. *
  68. * Return: true if allocated tx descriptors reached max configured value, else
  69. * false
  70. */
  71. static inline bool
  72. dp_tx_limit_check(struct dp_vdev *vdev)
  73. {
  74. struct dp_pdev *pdev = vdev->pdev;
  75. struct dp_soc *soc = pdev->soc;
  76. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  77. soc->num_tx_allowed) {
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  79. "%s: queued packets are more than max tx, drop the frame",
  80. __func__);
  81. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  82. return true;
  83. }
  84. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  85. pdev->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. return false;
  93. }
  94. /**
  95. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  96. * @vdev: DP pdev handle
  97. *
  98. * Return: void
  99. */
  100. static inline void
  101. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  102. {
  103. struct dp_soc *soc = pdev->soc;
  104. qdf_atomic_inc(&pdev->num_tx_outstanding);
  105. qdf_atomic_inc(&soc->num_tx_outstanding);
  106. }
  107. /**
  108. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  109. * @vdev: DP pdev handle
  110. *
  111. * Return: void
  112. */
  113. static inline void
  114. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  115. {
  116. struct dp_soc *soc = pdev->soc;
  117. qdf_atomic_dec(&pdev->num_tx_outstanding);
  118. qdf_atomic_dec(&soc->num_tx_outstanding);
  119. }
  120. #else //QCA_TX_LIMIT_CHECK
  121. static inline bool
  122. dp_tx_limit_check(struct dp_vdev *vdev)
  123. {
  124. return false;
  125. }
  126. static inline void
  127. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  128. {
  129. }
  130. static inline void
  131. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  132. {
  133. }
  134. #endif //QCA_TX_LIMIT_CHECK
  135. #if defined(FEATURE_TSO)
  136. /**
  137. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  138. *
  139. * @soc - core txrx main context
  140. * @seg_desc - tso segment descriptor
  141. * @num_seg_desc - tso number segment descriptor
  142. */
  143. static void dp_tx_tso_unmap_segment(
  144. struct dp_soc *soc,
  145. struct qdf_tso_seg_elem_t *seg_desc,
  146. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  147. {
  148. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  149. if (qdf_unlikely(!seg_desc)) {
  150. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  151. __func__, __LINE__);
  152. qdf_assert(0);
  153. } else if (qdf_unlikely(!num_seg_desc)) {
  154. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  155. __func__, __LINE__);
  156. qdf_assert(0);
  157. } else {
  158. bool is_last_seg;
  159. /* no tso segment left to do dma unmap */
  160. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  161. return;
  162. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  163. true : false;
  164. qdf_nbuf_unmap_tso_segment(soc->osdev,
  165. seg_desc, is_last_seg);
  166. num_seg_desc->num_seg.tso_cmn_num_seg--;
  167. }
  168. }
  169. /**
  170. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  171. * back to the freelist
  172. *
  173. * @soc - soc device handle
  174. * @tx_desc - Tx software descriptor
  175. */
  176. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  177. struct dp_tx_desc_s *tx_desc)
  178. {
  179. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  180. if (qdf_unlikely(!tx_desc->tso_desc)) {
  181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  182. "%s %d TSO desc is NULL!",
  183. __func__, __LINE__);
  184. qdf_assert(0);
  185. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  186. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  187. "%s %d TSO num desc is NULL!",
  188. __func__, __LINE__);
  189. qdf_assert(0);
  190. } else {
  191. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  192. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  193. /* Add the tso num segment into the free list */
  194. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  195. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  196. tx_desc->tso_num_desc);
  197. tx_desc->tso_num_desc = NULL;
  198. }
  199. /* Add the tso segment into the free list*/
  200. dp_tx_tso_desc_free(soc,
  201. tx_desc->pool_id, tx_desc->tso_desc);
  202. tx_desc->tso_desc = NULL;
  203. }
  204. }
  205. #else
  206. static void dp_tx_tso_unmap_segment(
  207. struct dp_soc *soc,
  208. struct qdf_tso_seg_elem_t *seg_desc,
  209. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  210. {
  211. }
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. }
  216. #endif
  217. /**
  218. * dp_tx_desc_release() - Release Tx Descriptor
  219. * @tx_desc : Tx Descriptor
  220. * @desc_pool_id: Descriptor Pool ID
  221. *
  222. * Deallocate all resources attached to Tx descriptor and free the Tx
  223. * descriptor.
  224. *
  225. * Return:
  226. */
  227. static void
  228. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  229. {
  230. struct dp_pdev *pdev = tx_desc->pdev;
  231. struct dp_soc *soc;
  232. uint8_t comp_status = 0;
  233. qdf_assert(pdev);
  234. soc = pdev->soc;
  235. if (tx_desc->frm_type == dp_tx_frm_tso)
  236. dp_tx_tso_desc_release(soc, tx_desc);
  237. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  238. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  239. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  240. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  241. dp_tx_outstanding_dec(pdev);
  242. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  243. qdf_atomic_dec(&pdev->num_tx_exception);
  244. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  245. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  246. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  247. soc->hal_soc);
  248. else
  249. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  251. "Tx Completion Release desc %d status %d outstanding %d",
  252. tx_desc->id, comp_status,
  253. qdf_atomic_read(&pdev->num_tx_outstanding));
  254. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  255. return;
  256. }
  257. /**
  258. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  259. * @vdev: DP vdev Handle
  260. * @nbuf: skb
  261. * @msdu_info: msdu_info required to create HTT metadata
  262. *
  263. * Prepares and fills HTT metadata in the frame pre-header for special frames
  264. * that should be transmitted using varying transmit parameters.
  265. * There are 2 VDEV modes that currently needs this special metadata -
  266. * 1) Mesh Mode
  267. * 2) DSRC Mode
  268. *
  269. * Return: HTT metadata size
  270. *
  271. */
  272. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  273. struct dp_tx_msdu_info_s *msdu_info)
  274. {
  275. uint32_t *meta_data = msdu_info->meta_data;
  276. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  277. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  278. uint8_t htt_desc_size;
  279. /* Size rounded of multiple of 8 bytes */
  280. uint8_t htt_desc_size_aligned;
  281. uint8_t *hdr = NULL;
  282. /*
  283. * Metadata - HTT MSDU Extension header
  284. */
  285. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  286. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  287. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  288. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  289. meta_data[0])) {
  290. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  291. htt_desc_size_aligned)) {
  292. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  293. htt_desc_size_aligned);
  294. if (!nbuf) {
  295. /*
  296. * qdf_nbuf_realloc_headroom won't do skb_clone
  297. * as skb_realloc_headroom does. so, no free is
  298. * needed here.
  299. */
  300. DP_STATS_INC(vdev,
  301. tx_i.dropped.headroom_insufficient,
  302. 1);
  303. qdf_print(" %s[%d] skb_realloc_headroom failed",
  304. __func__, __LINE__);
  305. return 0;
  306. }
  307. }
  308. /* Fill and add HTT metaheader */
  309. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  310. if (!hdr) {
  311. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  312. "Error in filling HTT metadata");
  313. return 0;
  314. }
  315. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  316. } else if (vdev->opmode == wlan_op_mode_ocb) {
  317. /* Todo - Add support for DSRC */
  318. }
  319. return htt_desc_size_aligned;
  320. }
  321. /**
  322. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  323. * @tso_seg: TSO segment to process
  324. * @ext_desc: Pointer to MSDU extension descriptor
  325. *
  326. * Return: void
  327. */
  328. #if defined(FEATURE_TSO)
  329. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  330. void *ext_desc)
  331. {
  332. uint8_t num_frag;
  333. uint32_t tso_flags;
  334. /*
  335. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  336. * tcp_flag_mask
  337. *
  338. * Checksum enable flags are set in TCL descriptor and not in Extension
  339. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  340. */
  341. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  342. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  343. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  344. tso_seg->tso_flags.ip_len);
  345. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  346. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  347. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  348. uint32_t lo = 0;
  349. uint32_t hi = 0;
  350. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  351. (tso_seg->tso_frags[num_frag].length));
  352. qdf_dmaaddr_to_32s(
  353. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  354. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  355. tso_seg->tso_frags[num_frag].length);
  356. }
  357. return;
  358. }
  359. #else
  360. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  361. void *ext_desc)
  362. {
  363. return;
  364. }
  365. #endif
  366. #if defined(FEATURE_TSO)
  367. /**
  368. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  369. * allocated and free them
  370. *
  371. * @soc: soc handle
  372. * @free_seg: list of tso segments
  373. * @msdu_info: msdu descriptor
  374. *
  375. * Return - void
  376. */
  377. static void dp_tx_free_tso_seg_list(
  378. struct dp_soc *soc,
  379. struct qdf_tso_seg_elem_t *free_seg,
  380. struct dp_tx_msdu_info_s *msdu_info)
  381. {
  382. struct qdf_tso_seg_elem_t *next_seg;
  383. while (free_seg) {
  384. next_seg = free_seg->next;
  385. dp_tx_tso_desc_free(soc,
  386. msdu_info->tx_queue.desc_pool_id,
  387. free_seg);
  388. free_seg = next_seg;
  389. }
  390. }
  391. /**
  392. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  393. * allocated and free them
  394. *
  395. * @soc: soc handle
  396. * @free_num_seg: list of tso number segments
  397. * @msdu_info: msdu descriptor
  398. * Return - void
  399. */
  400. static void dp_tx_free_tso_num_seg_list(
  401. struct dp_soc *soc,
  402. struct qdf_tso_num_seg_elem_t *free_num_seg,
  403. struct dp_tx_msdu_info_s *msdu_info)
  404. {
  405. struct qdf_tso_num_seg_elem_t *next_num_seg;
  406. while (free_num_seg) {
  407. next_num_seg = free_num_seg->next;
  408. dp_tso_num_seg_free(soc,
  409. msdu_info->tx_queue.desc_pool_id,
  410. free_num_seg);
  411. free_num_seg = next_num_seg;
  412. }
  413. }
  414. /**
  415. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  416. * do dma unmap for each segment
  417. *
  418. * @soc: soc handle
  419. * @free_seg: list of tso segments
  420. * @num_seg_desc: tso number segment descriptor
  421. *
  422. * Return - void
  423. */
  424. static void dp_tx_unmap_tso_seg_list(
  425. struct dp_soc *soc,
  426. struct qdf_tso_seg_elem_t *free_seg,
  427. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  428. {
  429. struct qdf_tso_seg_elem_t *next_seg;
  430. if (qdf_unlikely(!num_seg_desc)) {
  431. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  432. return;
  433. }
  434. while (free_seg) {
  435. next_seg = free_seg->next;
  436. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  437. free_seg = next_seg;
  438. }
  439. }
  440. /**
  441. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  442. * free the tso segments descriptor and
  443. * tso num segments descriptor
  444. *
  445. * @soc: soc handle
  446. * @msdu_info: msdu descriptor
  447. * @tso_seg_unmap: flag to show if dma unmap is necessary
  448. *
  449. * Return - void
  450. */
  451. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  452. struct dp_tx_msdu_info_s *msdu_info,
  453. bool tso_seg_unmap)
  454. {
  455. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  456. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  457. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  458. tso_info->tso_num_seg_list;
  459. /* do dma unmap for each segment */
  460. if (tso_seg_unmap)
  461. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  462. /* free all tso number segment descriptor though looks only have 1 */
  463. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  464. /* free all tso segment descriptor */
  465. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  466. }
  467. /**
  468. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  469. * @vdev: virtual device handle
  470. * @msdu: network buffer
  471. * @msdu_info: meta data associated with the msdu
  472. *
  473. * Return: QDF_STATUS_SUCCESS success
  474. */
  475. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  476. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  477. {
  478. struct qdf_tso_seg_elem_t *tso_seg;
  479. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  480. struct dp_soc *soc = vdev->pdev->soc;
  481. struct qdf_tso_info_t *tso_info;
  482. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  483. tso_info = &msdu_info->u.tso_info;
  484. tso_info->curr_seg = NULL;
  485. tso_info->tso_seg_list = NULL;
  486. tso_info->num_segs = num_seg;
  487. msdu_info->frm_type = dp_tx_frm_tso;
  488. tso_info->tso_num_seg_list = NULL;
  489. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  490. while (num_seg) {
  491. tso_seg = dp_tx_tso_desc_alloc(
  492. soc, msdu_info->tx_queue.desc_pool_id);
  493. if (tso_seg) {
  494. tso_seg->next = tso_info->tso_seg_list;
  495. tso_info->tso_seg_list = tso_seg;
  496. num_seg--;
  497. } else {
  498. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  499. __func__);
  500. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  501. return QDF_STATUS_E_NOMEM;
  502. }
  503. }
  504. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  505. tso_num_seg = dp_tso_num_seg_alloc(soc,
  506. msdu_info->tx_queue.desc_pool_id);
  507. if (tso_num_seg) {
  508. tso_num_seg->next = tso_info->tso_num_seg_list;
  509. tso_info->tso_num_seg_list = tso_num_seg;
  510. } else {
  511. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  512. __func__);
  513. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  514. return QDF_STATUS_E_NOMEM;
  515. }
  516. msdu_info->num_seg =
  517. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  518. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  519. msdu_info->num_seg);
  520. if (!(msdu_info->num_seg)) {
  521. /*
  522. * Free allocated TSO seg desc and number seg desc,
  523. * do unmap for segments if dma map has done.
  524. */
  525. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  526. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  527. return QDF_STATUS_E_INVAL;
  528. }
  529. tso_info->curr_seg = tso_info->tso_seg_list;
  530. return QDF_STATUS_SUCCESS;
  531. }
  532. #else
  533. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  534. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  535. {
  536. return QDF_STATUS_E_NOMEM;
  537. }
  538. #endif
  539. /**
  540. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  541. * @vdev: DP Vdev handle
  542. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  543. * @desc_pool_id: Descriptor Pool ID
  544. *
  545. * Return:
  546. */
  547. static
  548. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  549. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  550. {
  551. uint8_t i;
  552. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  553. struct dp_tx_seg_info_s *seg_info;
  554. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  555. struct dp_soc *soc = vdev->pdev->soc;
  556. /* Allocate an extension descriptor */
  557. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  558. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  559. if (!msdu_ext_desc) {
  560. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  561. return NULL;
  562. }
  563. if (msdu_info->exception_fw &&
  564. qdf_unlikely(vdev->mesh_vdev)) {
  565. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  566. &msdu_info->meta_data[0],
  567. sizeof(struct htt_tx_msdu_desc_ext2_t));
  568. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  569. }
  570. switch (msdu_info->frm_type) {
  571. case dp_tx_frm_sg:
  572. case dp_tx_frm_me:
  573. case dp_tx_frm_raw:
  574. seg_info = msdu_info->u.sg_info.curr_seg;
  575. /* Update the buffer pointers in MSDU Extension Descriptor */
  576. for (i = 0; i < seg_info->frag_cnt; i++) {
  577. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  578. seg_info->frags[i].paddr_lo,
  579. seg_info->frags[i].paddr_hi,
  580. seg_info->frags[i].len);
  581. }
  582. break;
  583. case dp_tx_frm_tso:
  584. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  585. &cached_ext_desc[0]);
  586. break;
  587. default:
  588. break;
  589. }
  590. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  591. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  592. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  593. msdu_ext_desc->vaddr);
  594. return msdu_ext_desc;
  595. }
  596. /**
  597. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  598. *
  599. * @skb: skb to be traced
  600. * @msdu_id: msdu_id of the packet
  601. * @vdev_id: vdev_id of the packet
  602. *
  603. * Return: None
  604. */
  605. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  606. uint8_t vdev_id)
  607. {
  608. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  609. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  610. DPTRACE(qdf_dp_trace_ptr(skb,
  611. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  612. QDF_TRACE_DEFAULT_PDEV_ID,
  613. qdf_nbuf_data_addr(skb),
  614. sizeof(qdf_nbuf_data(skb)),
  615. msdu_id, vdev_id));
  616. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  617. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  618. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  619. msdu_id, QDF_TX));
  620. }
  621. /**
  622. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  623. * @vdev: DP vdev handle
  624. * @nbuf: skb
  625. * @desc_pool_id: Descriptor pool ID
  626. * @meta_data: Metadata to the fw
  627. * @tx_exc_metadata: Handle that holds exception path metadata
  628. * Allocate and prepare Tx descriptor with msdu information.
  629. *
  630. * Return: Pointer to Tx Descriptor on success,
  631. * NULL on failure
  632. */
  633. static
  634. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  635. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  636. struct dp_tx_msdu_info_s *msdu_info,
  637. struct cdp_tx_exception_metadata *tx_exc_metadata)
  638. {
  639. uint8_t align_pad;
  640. uint8_t is_exception = 0;
  641. uint8_t htt_hdr_size;
  642. qdf_ether_header_t *eh;
  643. struct dp_tx_desc_s *tx_desc;
  644. struct dp_pdev *pdev = vdev->pdev;
  645. struct dp_soc *soc = pdev->soc;
  646. if (dp_tx_limit_check(vdev))
  647. return NULL;
  648. /* Allocate software Tx descriptor */
  649. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  650. if (qdf_unlikely(!tx_desc)) {
  651. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  652. return NULL;
  653. }
  654. dp_tx_outstanding_inc(pdev);
  655. /* Initialize the SW tx descriptor */
  656. tx_desc->nbuf = nbuf;
  657. tx_desc->frm_type = dp_tx_frm_std;
  658. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  659. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  660. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  661. tx_desc->vdev = vdev;
  662. tx_desc->pdev = pdev;
  663. tx_desc->msdu_ext_desc = NULL;
  664. tx_desc->pkt_offset = 0;
  665. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  666. if (qdf_unlikely(vdev->multipass_en)) {
  667. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  668. goto failure;
  669. }
  670. /*
  671. * For special modes (vdev_type == ocb or mesh), data frames should be
  672. * transmitted using varying transmit parameters (tx spec) which include
  673. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  674. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  675. * These frames are sent as exception packets to firmware.
  676. *
  677. * HW requirement is that metadata should always point to a
  678. * 8-byte aligned address. So we add alignment pad to start of buffer.
  679. * HTT Metadata should be ensured to be multiple of 8-bytes,
  680. * to get 8-byte aligned start address along with align_pad added
  681. *
  682. * |-----------------------------|
  683. * | |
  684. * |-----------------------------| <-----Buffer Pointer Address given
  685. * | | ^ in HW descriptor (aligned)
  686. * | HTT Metadata | |
  687. * | | |
  688. * | | | Packet Offset given in descriptor
  689. * | | |
  690. * |-----------------------------| |
  691. * | Alignment Pad | v
  692. * |-----------------------------| <----- Actual buffer start address
  693. * | SKB Data | (Unaligned)
  694. * | |
  695. * | |
  696. * | |
  697. * | |
  698. * | |
  699. * |-----------------------------|
  700. */
  701. if (qdf_unlikely((msdu_info->exception_fw)) ||
  702. (vdev->opmode == wlan_op_mode_ocb) ||
  703. (tx_exc_metadata &&
  704. tx_exc_metadata->is_tx_sniffer)) {
  705. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  706. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  707. DP_STATS_INC(vdev,
  708. tx_i.dropped.headroom_insufficient, 1);
  709. goto failure;
  710. }
  711. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  713. "qdf_nbuf_push_head failed");
  714. goto failure;
  715. }
  716. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  717. msdu_info);
  718. if (htt_hdr_size == 0)
  719. goto failure;
  720. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  721. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  722. is_exception = 1;
  723. }
  724. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  725. qdf_nbuf_map(soc->osdev, nbuf,
  726. QDF_DMA_TO_DEVICE))) {
  727. /* Handle failure */
  728. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  729. "qdf_nbuf_map failed");
  730. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  731. goto failure;
  732. }
  733. if (qdf_unlikely(vdev->nawds_enabled)) {
  734. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  735. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  736. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  737. is_exception = 1;
  738. }
  739. }
  740. #if !TQM_BYPASS_WAR
  741. if (is_exception || tx_exc_metadata)
  742. #endif
  743. {
  744. /* Temporary WAR due to TQM VP issues */
  745. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  746. qdf_atomic_inc(&pdev->num_tx_exception);
  747. }
  748. return tx_desc;
  749. failure:
  750. dp_tx_desc_release(tx_desc, desc_pool_id);
  751. return NULL;
  752. }
  753. /**
  754. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  755. * @vdev: DP vdev handle
  756. * @nbuf: skb
  757. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  758. * @desc_pool_id : Descriptor Pool ID
  759. *
  760. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  761. * information. For frames wth fragments, allocate and prepare
  762. * an MSDU extension descriptor
  763. *
  764. * Return: Pointer to Tx Descriptor on success,
  765. * NULL on failure
  766. */
  767. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  768. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  769. uint8_t desc_pool_id)
  770. {
  771. struct dp_tx_desc_s *tx_desc;
  772. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  773. struct dp_pdev *pdev = vdev->pdev;
  774. struct dp_soc *soc = pdev->soc;
  775. if (dp_tx_limit_check(vdev))
  776. return NULL;
  777. /* Allocate software Tx descriptor */
  778. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  779. if (!tx_desc) {
  780. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  781. return NULL;
  782. }
  783. dp_tx_outstanding_inc(pdev);
  784. /* Initialize the SW tx descriptor */
  785. tx_desc->nbuf = nbuf;
  786. tx_desc->frm_type = msdu_info->frm_type;
  787. tx_desc->tx_encap_type = vdev->tx_encap_type;
  788. tx_desc->vdev = vdev;
  789. tx_desc->pdev = pdev;
  790. tx_desc->pkt_offset = 0;
  791. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  792. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  793. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  794. /* Handle scattered frames - TSO/SG/ME */
  795. /* Allocate and prepare an extension descriptor for scattered frames */
  796. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  797. if (!msdu_ext_desc) {
  798. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  799. "%s Tx Extension Descriptor Alloc Fail",
  800. __func__);
  801. goto failure;
  802. }
  803. #if TQM_BYPASS_WAR
  804. /* Temporary WAR due to TQM VP issues */
  805. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  806. qdf_atomic_inc(&pdev->num_tx_exception);
  807. #endif
  808. if (qdf_unlikely(msdu_info->exception_fw))
  809. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  810. tx_desc->msdu_ext_desc = msdu_ext_desc;
  811. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  812. return tx_desc;
  813. failure:
  814. dp_tx_desc_release(tx_desc, desc_pool_id);
  815. return NULL;
  816. }
  817. /**
  818. * dp_tx_prepare_raw() - Prepare RAW packet TX
  819. * @vdev: DP vdev handle
  820. * @nbuf: buffer pointer
  821. * @seg_info: Pointer to Segment info Descriptor to be prepared
  822. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  823. * descriptor
  824. *
  825. * Return:
  826. */
  827. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  828. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  829. {
  830. qdf_nbuf_t curr_nbuf = NULL;
  831. uint16_t total_len = 0;
  832. qdf_dma_addr_t paddr;
  833. int32_t i;
  834. int32_t mapped_buf_num = 0;
  835. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  836. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  837. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  838. /* Continue only if frames are of DATA type */
  839. if (!DP_FRAME_IS_DATA(qos_wh)) {
  840. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  842. "Pkt. recd is of not data type");
  843. goto error;
  844. }
  845. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  846. if (vdev->raw_mode_war &&
  847. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  848. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  849. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  850. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  851. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  852. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  853. QDF_DMA_TO_DEVICE)) {
  854. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  855. "%s dma map error ", __func__);
  856. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  857. mapped_buf_num = i;
  858. goto error;
  859. }
  860. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  861. seg_info->frags[i].paddr_lo = paddr;
  862. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  863. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  864. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  865. total_len += qdf_nbuf_len(curr_nbuf);
  866. }
  867. seg_info->frag_cnt = i;
  868. seg_info->total_len = total_len;
  869. seg_info->next = NULL;
  870. sg_info->curr_seg = seg_info;
  871. msdu_info->frm_type = dp_tx_frm_raw;
  872. msdu_info->num_seg = 1;
  873. return nbuf;
  874. error:
  875. i = 0;
  876. while (nbuf) {
  877. curr_nbuf = nbuf;
  878. if (i < mapped_buf_num) {
  879. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  880. i++;
  881. }
  882. nbuf = qdf_nbuf_next(nbuf);
  883. qdf_nbuf_free(curr_nbuf);
  884. }
  885. return NULL;
  886. }
  887. /**
  888. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  889. * @soc: DP soc handle
  890. * @nbuf: Buffer pointer
  891. *
  892. * unmap the chain of nbufs that belong to this RAW frame.
  893. *
  894. * Return: None
  895. */
  896. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  897. qdf_nbuf_t nbuf)
  898. {
  899. qdf_nbuf_t cur_nbuf = nbuf;
  900. do {
  901. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  902. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  903. } while (cur_nbuf);
  904. }
  905. /**
  906. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  907. * @soc: DP Soc Handle
  908. * @vdev: DP vdev handle
  909. * @tx_desc: Tx Descriptor Handle
  910. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  911. * @fw_metadata: Metadata to send to Target Firmware along with frame
  912. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  913. * @tx_exc_metadata: Handle that holds exception path meta data
  914. *
  915. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  916. * from software Tx descriptor
  917. *
  918. * Return:
  919. */
  920. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  921. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  922. uint16_t fw_metadata, uint8_t ring_id,
  923. struct cdp_tx_exception_metadata
  924. *tx_exc_metadata)
  925. {
  926. uint8_t type;
  927. uint16_t length;
  928. void *hal_tx_desc, *hal_tx_desc_cached;
  929. qdf_dma_addr_t dma_addr;
  930. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  931. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  932. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  933. tx_exc_metadata->sec_type : vdev->sec_type);
  934. /* Return Buffer Manager ID */
  935. uint8_t bm_id = ring_id;
  936. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  937. hal_tx_desc_cached = (void *) cached_desc;
  938. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  939. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  940. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  941. type = HAL_TX_BUF_TYPE_EXT_DESC;
  942. dma_addr = tx_desc->msdu_ext_desc->paddr;
  943. } else {
  944. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  945. type = HAL_TX_BUF_TYPE_BUFFER;
  946. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  947. }
  948. qdf_assert_always(dma_addr);
  949. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  950. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  951. dma_addr, bm_id, tx_desc->id,
  952. type, soc->hal_soc);
  953. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  954. return QDF_STATUS_E_RESOURCES;
  955. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  956. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  957. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  958. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  959. vdev->pdev->lmac_id);
  960. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  961. vdev->search_type);
  962. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  963. vdev->bss_ast_idx);
  964. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  965. vdev->dscp_tid_map_id);
  966. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  967. sec_type_map[sec_type]);
  968. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  969. (vdev->bss_ast_hash & 0xF));
  970. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  971. length, type, (uint64_t)dma_addr,
  972. tx_desc->pkt_offset, tx_desc->id);
  973. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  974. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  975. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  976. vdev->hal_desc_addr_search_flags);
  977. /* verify checksum offload configuration*/
  978. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  979. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  980. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  981. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  982. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  983. }
  984. if (tid != HTT_TX_EXT_TID_INVALID)
  985. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  986. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  987. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  988. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  989. /* Sync cached descriptor with HW */
  990. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  991. if (!hal_tx_desc) {
  992. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  993. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  994. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  995. return QDF_STATUS_E_RESOURCES;
  996. }
  997. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  998. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  999. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  1000. return QDF_STATUS_SUCCESS;
  1001. }
  1002. /**
  1003. * dp_cce_classify() - Classify the frame based on CCE rules
  1004. * @vdev: DP vdev handle
  1005. * @nbuf: skb
  1006. *
  1007. * Classify frames based on CCE rules
  1008. * Return: bool( true if classified,
  1009. * else false)
  1010. */
  1011. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1012. {
  1013. qdf_ether_header_t *eh = NULL;
  1014. uint16_t ether_type;
  1015. qdf_llc_t *llcHdr;
  1016. qdf_nbuf_t nbuf_clone = NULL;
  1017. qdf_dot3_qosframe_t *qos_wh = NULL;
  1018. /* for mesh packets don't do any classification */
  1019. if (qdf_unlikely(vdev->mesh_vdev))
  1020. return false;
  1021. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1022. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1023. ether_type = eh->ether_type;
  1024. llcHdr = (qdf_llc_t *)(nbuf->data +
  1025. sizeof(qdf_ether_header_t));
  1026. } else {
  1027. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1028. /* For encrypted packets don't do any classification */
  1029. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1030. return false;
  1031. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1032. if (qdf_unlikely(
  1033. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1034. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1035. ether_type = *(uint16_t *)(nbuf->data
  1036. + QDF_IEEE80211_4ADDR_HDR_LEN
  1037. + sizeof(qdf_llc_t)
  1038. - sizeof(ether_type));
  1039. llcHdr = (qdf_llc_t *)(nbuf->data +
  1040. QDF_IEEE80211_4ADDR_HDR_LEN);
  1041. } else {
  1042. ether_type = *(uint16_t *)(nbuf->data
  1043. + QDF_IEEE80211_3ADDR_HDR_LEN
  1044. + sizeof(qdf_llc_t)
  1045. - sizeof(ether_type));
  1046. llcHdr = (qdf_llc_t *)(nbuf->data +
  1047. QDF_IEEE80211_3ADDR_HDR_LEN);
  1048. }
  1049. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1050. && (ether_type ==
  1051. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1052. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1053. return true;
  1054. }
  1055. }
  1056. return false;
  1057. }
  1058. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1059. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1060. sizeof(*llcHdr));
  1061. nbuf_clone = qdf_nbuf_clone(nbuf);
  1062. if (qdf_unlikely(nbuf_clone)) {
  1063. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1064. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1065. qdf_nbuf_pull_head(nbuf_clone,
  1066. sizeof(qdf_net_vlanhdr_t));
  1067. }
  1068. }
  1069. } else {
  1070. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1071. nbuf_clone = qdf_nbuf_clone(nbuf);
  1072. if (qdf_unlikely(nbuf_clone)) {
  1073. qdf_nbuf_pull_head(nbuf_clone,
  1074. sizeof(qdf_net_vlanhdr_t));
  1075. }
  1076. }
  1077. }
  1078. if (qdf_unlikely(nbuf_clone))
  1079. nbuf = nbuf_clone;
  1080. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1081. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1082. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1083. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1084. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1085. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1086. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1087. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1088. if (qdf_unlikely(nbuf_clone))
  1089. qdf_nbuf_free(nbuf_clone);
  1090. return true;
  1091. }
  1092. if (qdf_unlikely(nbuf_clone))
  1093. qdf_nbuf_free(nbuf_clone);
  1094. return false;
  1095. }
  1096. /**
  1097. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1098. * @vdev: DP vdev handle
  1099. * @nbuf: skb
  1100. *
  1101. * Extract the DSCP or PCP information from frame and map into TID value.
  1102. *
  1103. * Return: void
  1104. */
  1105. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1106. struct dp_tx_msdu_info_s *msdu_info)
  1107. {
  1108. uint8_t tos = 0, dscp_tid_override = 0;
  1109. uint8_t *hdr_ptr, *L3datap;
  1110. uint8_t is_mcast = 0;
  1111. qdf_ether_header_t *eh = NULL;
  1112. qdf_ethervlan_header_t *evh = NULL;
  1113. uint16_t ether_type;
  1114. qdf_llc_t *llcHdr;
  1115. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1116. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1117. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1118. eh = (qdf_ether_header_t *)nbuf->data;
  1119. hdr_ptr = eh->ether_dhost;
  1120. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1121. } else {
  1122. qdf_dot3_qosframe_t *qos_wh =
  1123. (qdf_dot3_qosframe_t *) nbuf->data;
  1124. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1125. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1126. return;
  1127. }
  1128. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1129. ether_type = eh->ether_type;
  1130. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1131. /*
  1132. * Check if packet is dot3 or eth2 type.
  1133. */
  1134. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1135. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1136. sizeof(*llcHdr));
  1137. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1138. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1139. sizeof(*llcHdr);
  1140. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1141. + sizeof(*llcHdr) +
  1142. sizeof(qdf_net_vlanhdr_t));
  1143. } else {
  1144. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1145. sizeof(*llcHdr);
  1146. }
  1147. } else {
  1148. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1149. evh = (qdf_ethervlan_header_t *) eh;
  1150. ether_type = evh->ether_type;
  1151. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1152. }
  1153. }
  1154. /*
  1155. * Find priority from IP TOS DSCP field
  1156. */
  1157. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1158. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1159. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1160. /* Only for unicast frames */
  1161. if (!is_mcast) {
  1162. /* send it on VO queue */
  1163. msdu_info->tid = DP_VO_TID;
  1164. }
  1165. } else {
  1166. /*
  1167. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1168. * from TOS byte.
  1169. */
  1170. tos = ip->ip_tos;
  1171. dscp_tid_override = 1;
  1172. }
  1173. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1174. /* TODO
  1175. * use flowlabel
  1176. *igmpmld cases to be handled in phase 2
  1177. */
  1178. unsigned long ver_pri_flowlabel;
  1179. unsigned long pri;
  1180. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1181. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1182. DP_IPV6_PRIORITY_SHIFT;
  1183. tos = pri;
  1184. dscp_tid_override = 1;
  1185. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1186. msdu_info->tid = DP_VO_TID;
  1187. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1188. /* Only for unicast frames */
  1189. if (!is_mcast) {
  1190. /* send ucast arp on VO queue */
  1191. msdu_info->tid = DP_VO_TID;
  1192. }
  1193. }
  1194. /*
  1195. * Assign all MCAST packets to BE
  1196. */
  1197. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1198. if (is_mcast) {
  1199. tos = 0;
  1200. dscp_tid_override = 1;
  1201. }
  1202. }
  1203. if (dscp_tid_override == 1) {
  1204. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1205. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1206. }
  1207. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1208. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1209. return;
  1210. }
  1211. /**
  1212. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1213. * @vdev: DP vdev handle
  1214. * @nbuf: skb
  1215. *
  1216. * Software based TID classification is required when more than 2 DSCP-TID
  1217. * mapping tables are needed.
  1218. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1219. *
  1220. * Return: void
  1221. */
  1222. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1223. struct dp_tx_msdu_info_s *msdu_info)
  1224. {
  1225. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1226. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1227. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1228. return;
  1229. /* for mesh packets don't do any classification */
  1230. if (qdf_unlikely(vdev->mesh_vdev))
  1231. return;
  1232. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1233. }
  1234. #ifdef FEATURE_WLAN_TDLS
  1235. /**
  1236. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1237. * @tx_desc: TX descriptor
  1238. *
  1239. * Return: None
  1240. */
  1241. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1242. {
  1243. if (tx_desc->vdev) {
  1244. if (tx_desc->vdev->is_tdls_frame) {
  1245. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1246. tx_desc->vdev->is_tdls_frame = false;
  1247. }
  1248. }
  1249. }
  1250. /**
  1251. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1252. * @tx_desc: TX descriptor
  1253. * @vdev: datapath vdev handle
  1254. *
  1255. * Return: None
  1256. */
  1257. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1258. struct dp_vdev *vdev)
  1259. {
  1260. struct hal_tx_completion_status ts = {0};
  1261. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1262. if (qdf_unlikely(!vdev)) {
  1263. dp_err("vdev is null!");
  1264. return;
  1265. }
  1266. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1267. if (vdev->tx_non_std_data_callback.func) {
  1268. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1269. vdev->tx_non_std_data_callback.func(
  1270. vdev->tx_non_std_data_callback.ctxt,
  1271. nbuf, ts.status);
  1272. return;
  1273. }
  1274. }
  1275. #else
  1276. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1277. {
  1278. }
  1279. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1280. struct dp_vdev *vdev)
  1281. {
  1282. }
  1283. #endif
  1284. /**
  1285. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1286. * @vdev: DP vdev handle
  1287. * @nbuf: skb
  1288. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1289. * @meta_data: Metadata to the fw
  1290. * @tx_q: Tx queue to be used for this Tx frame
  1291. * @peer_id: peer_id of the peer in case of NAWDS frames
  1292. * @tx_exc_metadata: Handle that holds exception path metadata
  1293. *
  1294. * Return: NULL on success,
  1295. * nbuf when it fails to send
  1296. */
  1297. qdf_nbuf_t
  1298. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1299. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1300. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1301. {
  1302. struct dp_pdev *pdev = vdev->pdev;
  1303. struct dp_soc *soc = pdev->soc;
  1304. struct dp_tx_desc_s *tx_desc;
  1305. QDF_STATUS status;
  1306. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1307. hal_ring_handle_t hal_ring_hdl =
  1308. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1309. uint16_t htt_tcl_metadata = 0;
  1310. uint8_t tid = msdu_info->tid;
  1311. struct cdp_tid_tx_stats *tid_stats = NULL;
  1312. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1313. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1314. msdu_info, tx_exc_metadata);
  1315. if (!tx_desc) {
  1316. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1317. vdev, tx_q->desc_pool_id);
  1318. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1319. tid_stats = &pdev->stats.tid_stats.
  1320. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1321. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1322. return nbuf;
  1323. }
  1324. if (qdf_unlikely(soc->cce_disable)) {
  1325. if (dp_cce_classify(vdev, nbuf) == true) {
  1326. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1327. tid = DP_VO_TID;
  1328. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1329. }
  1330. }
  1331. dp_tx_update_tdls_flags(tx_desc);
  1332. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1333. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1334. "%s %d : HAL RING Access Failed -- %pK",
  1335. __func__, __LINE__, hal_ring_hdl);
  1336. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1337. tid_stats = &pdev->stats.tid_stats.
  1338. tid_tx_stats[tx_q->ring_id][tid];
  1339. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1340. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1341. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1342. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1343. goto fail_return;
  1344. }
  1345. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1346. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1347. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1348. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1349. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1350. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1351. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1352. peer_id);
  1353. } else
  1354. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1355. if (msdu_info->exception_fw) {
  1356. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1357. }
  1358. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1359. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1360. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1361. if (status != QDF_STATUS_SUCCESS) {
  1362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1363. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1364. __func__, tx_desc, tx_q->ring_id);
  1365. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1366. tid_stats = &pdev->stats.tid_stats.
  1367. tid_tx_stats[tx_q->ring_id][tid];
  1368. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1369. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1370. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1371. goto fail_return;
  1372. }
  1373. nbuf = NULL;
  1374. fail_return:
  1375. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1376. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1377. hif_pm_runtime_put(soc->hif_handle);
  1378. } else {
  1379. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1380. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1381. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1382. }
  1383. return nbuf;
  1384. }
  1385. /**
  1386. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1387. * @vdev: DP vdev handle
  1388. * @nbuf: skb
  1389. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1390. *
  1391. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1392. *
  1393. * Return: NULL on success,
  1394. * nbuf when it fails to send
  1395. */
  1396. #if QDF_LOCK_STATS
  1397. noinline
  1398. #else
  1399. #endif
  1400. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1401. struct dp_tx_msdu_info_s *msdu_info)
  1402. {
  1403. uint8_t i;
  1404. struct dp_pdev *pdev = vdev->pdev;
  1405. struct dp_soc *soc = pdev->soc;
  1406. struct dp_tx_desc_s *tx_desc;
  1407. bool is_cce_classified = false;
  1408. QDF_STATUS status;
  1409. uint16_t htt_tcl_metadata = 0;
  1410. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1411. hal_ring_handle_t hal_ring_hdl =
  1412. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1413. struct cdp_tid_tx_stats *tid_stats = NULL;
  1414. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1415. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1416. "%s %d : HAL RING Access Failed -- %pK",
  1417. __func__, __LINE__, hal_ring_hdl);
  1418. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1419. tid_stats = &pdev->stats.tid_stats.
  1420. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1421. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1422. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1423. return nbuf;
  1424. }
  1425. if (qdf_unlikely(soc->cce_disable)) {
  1426. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1427. if (is_cce_classified) {
  1428. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1429. msdu_info->tid = DP_VO_TID;
  1430. }
  1431. }
  1432. if (msdu_info->frm_type == dp_tx_frm_me)
  1433. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1434. i = 0;
  1435. /* Print statement to track i and num_seg */
  1436. /*
  1437. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1438. * descriptors using information in msdu_info
  1439. */
  1440. while (i < msdu_info->num_seg) {
  1441. /*
  1442. * Setup Tx descriptor for an MSDU, and MSDU extension
  1443. * descriptor
  1444. */
  1445. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1446. tx_q->desc_pool_id);
  1447. if (!tx_desc) {
  1448. if (msdu_info->frm_type == dp_tx_frm_me) {
  1449. dp_tx_me_free_buf(pdev,
  1450. (void *)(msdu_info->u.sg_info
  1451. .curr_seg->frags[0].vaddr));
  1452. i++;
  1453. continue;
  1454. }
  1455. goto done;
  1456. }
  1457. if (msdu_info->frm_type == dp_tx_frm_me) {
  1458. tx_desc->me_buffer =
  1459. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1460. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1461. }
  1462. if (is_cce_classified)
  1463. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1464. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1465. if (msdu_info->exception_fw) {
  1466. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1467. }
  1468. /*
  1469. * Enqueue the Tx MSDU descriptor to HW for transmit
  1470. */
  1471. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1472. htt_tcl_metadata, tx_q->ring_id, NULL);
  1473. if (status != QDF_STATUS_SUCCESS) {
  1474. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1475. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1476. __func__, tx_desc, tx_q->ring_id);
  1477. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1478. tid_stats = &pdev->stats.tid_stats.
  1479. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1480. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1481. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1482. if (msdu_info->frm_type == dp_tx_frm_me) {
  1483. i++;
  1484. continue;
  1485. }
  1486. goto done;
  1487. }
  1488. /*
  1489. * TODO
  1490. * if tso_info structure can be modified to have curr_seg
  1491. * as first element, following 2 blocks of code (for TSO and SG)
  1492. * can be combined into 1
  1493. */
  1494. /*
  1495. * For frames with multiple segments (TSO, ME), jump to next
  1496. * segment.
  1497. */
  1498. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1499. if (msdu_info->u.tso_info.curr_seg->next) {
  1500. msdu_info->u.tso_info.curr_seg =
  1501. msdu_info->u.tso_info.curr_seg->next;
  1502. /*
  1503. * If this is a jumbo nbuf, then increment the number of
  1504. * nbuf users for each additional segment of the msdu.
  1505. * This will ensure that the skb is freed only after
  1506. * receiving tx completion for all segments of an nbuf
  1507. */
  1508. qdf_nbuf_inc_users(nbuf);
  1509. /* Check with MCL if this is needed */
  1510. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1511. }
  1512. }
  1513. /*
  1514. * For Multicast-Unicast converted packets,
  1515. * each converted frame (for a client) is represented as
  1516. * 1 segment
  1517. */
  1518. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1519. (msdu_info->frm_type == dp_tx_frm_me)) {
  1520. if (msdu_info->u.sg_info.curr_seg->next) {
  1521. msdu_info->u.sg_info.curr_seg =
  1522. msdu_info->u.sg_info.curr_seg->next;
  1523. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1524. }
  1525. }
  1526. i++;
  1527. }
  1528. nbuf = NULL;
  1529. done:
  1530. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1531. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1532. hif_pm_runtime_put(soc->hif_handle);
  1533. } else {
  1534. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1535. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1536. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1537. }
  1538. return nbuf;
  1539. }
  1540. /**
  1541. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1542. * for SG frames
  1543. * @vdev: DP vdev handle
  1544. * @nbuf: skb
  1545. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1546. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1547. *
  1548. * Return: NULL on success,
  1549. * nbuf when it fails to send
  1550. */
  1551. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1552. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1553. {
  1554. uint32_t cur_frag, nr_frags;
  1555. qdf_dma_addr_t paddr;
  1556. struct dp_tx_sg_info_s *sg_info;
  1557. sg_info = &msdu_info->u.sg_info;
  1558. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1559. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1560. QDF_DMA_TO_DEVICE)) {
  1561. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1562. "dma map error");
  1563. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1564. qdf_nbuf_free(nbuf);
  1565. return NULL;
  1566. }
  1567. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1568. seg_info->frags[0].paddr_lo = paddr;
  1569. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1570. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1571. seg_info->frags[0].vaddr = (void *) nbuf;
  1572. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1573. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1574. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1576. "frag dma map error");
  1577. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1578. qdf_nbuf_free(nbuf);
  1579. return NULL;
  1580. }
  1581. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1582. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1583. seg_info->frags[cur_frag + 1].paddr_hi =
  1584. ((uint64_t) paddr) >> 32;
  1585. seg_info->frags[cur_frag + 1].len =
  1586. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1587. }
  1588. seg_info->frag_cnt = (cur_frag + 1);
  1589. seg_info->total_len = qdf_nbuf_len(nbuf);
  1590. seg_info->next = NULL;
  1591. sg_info->curr_seg = seg_info;
  1592. msdu_info->frm_type = dp_tx_frm_sg;
  1593. msdu_info->num_seg = 1;
  1594. return nbuf;
  1595. }
  1596. /**
  1597. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1598. * @vdev: DP vdev handle
  1599. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1600. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1601. *
  1602. * Return: NULL on failure,
  1603. * nbuf when extracted successfully
  1604. */
  1605. static
  1606. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1607. struct dp_tx_msdu_info_s *msdu_info,
  1608. uint16_t ppdu_cookie)
  1609. {
  1610. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1611. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1612. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1613. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1614. (msdu_info->meta_data[5], 1);
  1615. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1616. (msdu_info->meta_data[5], 1);
  1617. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1618. (msdu_info->meta_data[6], ppdu_cookie);
  1619. msdu_info->exception_fw = 1;
  1620. msdu_info->is_tx_sniffer = 1;
  1621. }
  1622. #ifdef MESH_MODE_SUPPORT
  1623. /**
  1624. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1625. and prepare msdu_info for mesh frames.
  1626. * @vdev: DP vdev handle
  1627. * @nbuf: skb
  1628. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1629. *
  1630. * Return: NULL on failure,
  1631. * nbuf when extracted successfully
  1632. */
  1633. static
  1634. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1635. struct dp_tx_msdu_info_s *msdu_info)
  1636. {
  1637. struct meta_hdr_s *mhdr;
  1638. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1639. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1640. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1641. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1642. msdu_info->exception_fw = 0;
  1643. goto remove_meta_hdr;
  1644. }
  1645. msdu_info->exception_fw = 1;
  1646. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1647. meta_data->host_tx_desc_pool = 1;
  1648. meta_data->update_peer_cache = 1;
  1649. meta_data->learning_frame = 1;
  1650. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1651. meta_data->power = mhdr->power;
  1652. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1653. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1654. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1655. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1656. meta_data->dyn_bw = 1;
  1657. meta_data->valid_pwr = 1;
  1658. meta_data->valid_mcs_mask = 1;
  1659. meta_data->valid_nss_mask = 1;
  1660. meta_data->valid_preamble_type = 1;
  1661. meta_data->valid_retries = 1;
  1662. meta_data->valid_bw_info = 1;
  1663. }
  1664. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1665. meta_data->encrypt_type = 0;
  1666. meta_data->valid_encrypt_type = 1;
  1667. meta_data->learning_frame = 0;
  1668. }
  1669. meta_data->valid_key_flags = 1;
  1670. meta_data->key_flags = (mhdr->keyix & 0x3);
  1671. remove_meta_hdr:
  1672. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1673. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1674. "qdf_nbuf_pull_head failed");
  1675. qdf_nbuf_free(nbuf);
  1676. return NULL;
  1677. }
  1678. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1680. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1681. " tid %d to_fw %d",
  1682. __func__, msdu_info->meta_data[0],
  1683. msdu_info->meta_data[1],
  1684. msdu_info->meta_data[2],
  1685. msdu_info->meta_data[3],
  1686. msdu_info->meta_data[4],
  1687. msdu_info->meta_data[5],
  1688. msdu_info->tid, msdu_info->exception_fw);
  1689. return nbuf;
  1690. }
  1691. #else
  1692. static
  1693. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1694. struct dp_tx_msdu_info_s *msdu_info)
  1695. {
  1696. return nbuf;
  1697. }
  1698. #endif
  1699. /**
  1700. * dp_check_exc_metadata() - Checks if parameters are valid
  1701. * @tx_exc - holds all exception path parameters
  1702. *
  1703. * Returns true when all the parameters are valid else false
  1704. *
  1705. */
  1706. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1707. {
  1708. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1709. HTT_INVALID_TID);
  1710. bool invalid_encap_type =
  1711. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1712. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1713. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1714. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1715. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1716. tx_exc->ppdu_cookie == 0);
  1717. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1718. invalid_cookie) {
  1719. return false;
  1720. }
  1721. return true;
  1722. }
  1723. /**
  1724. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1725. * @vap_dev: DP vdev handle
  1726. * @nbuf: skb
  1727. * @tx_exc_metadata: Handle that holds exception path meta data
  1728. *
  1729. * Entry point for Core Tx layer (DP_TX) invoked from
  1730. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1731. *
  1732. * Return: NULL on success,
  1733. * nbuf when it fails to send
  1734. */
  1735. qdf_nbuf_t
  1736. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1737. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1738. {
  1739. qdf_ether_header_t *eh = NULL;
  1740. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1741. struct dp_tx_msdu_info_s msdu_info;
  1742. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1743. if (!tx_exc_metadata)
  1744. goto fail;
  1745. msdu_info.tid = tx_exc_metadata->tid;
  1746. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1747. dp_verbose_debug("skb %pM", nbuf->data);
  1748. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1749. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1750. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1751. "Invalid parameters in exception path");
  1752. goto fail;
  1753. }
  1754. /* Basic sanity checks for unsupported packets */
  1755. /* MESH mode */
  1756. if (qdf_unlikely(vdev->mesh_vdev)) {
  1757. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1758. "Mesh mode is not supported in exception path");
  1759. goto fail;
  1760. }
  1761. /* TSO or SG */
  1762. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1763. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1764. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1765. "TSO and SG are not supported in exception path");
  1766. goto fail;
  1767. }
  1768. /* RAW */
  1769. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1771. "Raw frame is not supported in exception path");
  1772. goto fail;
  1773. }
  1774. /* Mcast enhancement*/
  1775. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1776. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1777. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1779. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1780. }
  1781. }
  1782. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1783. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1784. qdf_nbuf_len(nbuf));
  1785. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1786. tx_exc_metadata->ppdu_cookie);
  1787. }
  1788. /*
  1789. * Get HW Queue to use for this frame.
  1790. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1791. * dedicated for data and 1 for command.
  1792. * "queue_id" maps to one hardware ring.
  1793. * With each ring, we also associate a unique Tx descriptor pool
  1794. * to minimize lock contention for these resources.
  1795. */
  1796. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1797. /* Single linear frame */
  1798. /*
  1799. * If nbuf is a simple linear frame, use send_single function to
  1800. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1801. * SRNG. There is no need to setup a MSDU extension descriptor.
  1802. */
  1803. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1804. tx_exc_metadata->peer_id, tx_exc_metadata);
  1805. return nbuf;
  1806. fail:
  1807. dp_verbose_debug("pkt send failed");
  1808. return nbuf;
  1809. }
  1810. /**
  1811. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1812. * @vap_dev: DP vdev handle
  1813. * @nbuf: skb
  1814. *
  1815. * Entry point for Core Tx layer (DP_TX) invoked from
  1816. * hard_start_xmit in OSIF/HDD
  1817. *
  1818. * Return: NULL on success,
  1819. * nbuf when it fails to send
  1820. */
  1821. #ifdef MESH_MODE_SUPPORT
  1822. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1823. {
  1824. struct meta_hdr_s *mhdr;
  1825. qdf_nbuf_t nbuf_mesh = NULL;
  1826. qdf_nbuf_t nbuf_clone = NULL;
  1827. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1828. uint8_t no_enc_frame = 0;
  1829. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1830. if (!nbuf_mesh) {
  1831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1832. "qdf_nbuf_unshare failed");
  1833. return nbuf;
  1834. }
  1835. nbuf = nbuf_mesh;
  1836. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1837. if ((vdev->sec_type != cdp_sec_type_none) &&
  1838. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1839. no_enc_frame = 1;
  1840. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1841. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1842. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1843. !no_enc_frame) {
  1844. nbuf_clone = qdf_nbuf_clone(nbuf);
  1845. if (!nbuf_clone) {
  1846. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1847. "qdf_nbuf_clone failed");
  1848. return nbuf;
  1849. }
  1850. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1851. }
  1852. if (nbuf_clone) {
  1853. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1854. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1855. } else {
  1856. qdf_nbuf_free(nbuf_clone);
  1857. }
  1858. }
  1859. if (no_enc_frame)
  1860. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1861. else
  1862. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1863. nbuf = dp_tx_send(vap_dev, nbuf);
  1864. if ((!nbuf) && no_enc_frame) {
  1865. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1866. }
  1867. return nbuf;
  1868. }
  1869. #else
  1870. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1871. {
  1872. return dp_tx_send(vap_dev, nbuf);
  1873. }
  1874. #endif
  1875. /**
  1876. * dp_tx_send() - Transmit a frame on a given VAP
  1877. * @vap_dev: DP vdev handle
  1878. * @nbuf: skb
  1879. *
  1880. * Entry point for Core Tx layer (DP_TX) invoked from
  1881. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1882. * cases
  1883. *
  1884. * Return: NULL on success,
  1885. * nbuf when it fails to send
  1886. */
  1887. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1888. {
  1889. qdf_ether_header_t *eh = NULL;
  1890. struct dp_tx_msdu_info_s msdu_info;
  1891. struct dp_tx_seg_info_s seg_info;
  1892. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1893. uint16_t peer_id = HTT_INVALID_PEER;
  1894. qdf_nbuf_t nbuf_mesh = NULL;
  1895. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1896. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1897. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1898. dp_verbose_debug("skb %pM", nbuf->data);
  1899. /*
  1900. * Set Default Host TID value to invalid TID
  1901. * (TID override disabled)
  1902. */
  1903. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1904. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1905. if (qdf_unlikely(vdev->mesh_vdev)) {
  1906. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1907. &msdu_info);
  1908. if (!nbuf_mesh) {
  1909. dp_verbose_debug("Extracting mesh metadata failed");
  1910. return nbuf;
  1911. }
  1912. nbuf = nbuf_mesh;
  1913. }
  1914. /*
  1915. * Get HW Queue to use for this frame.
  1916. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1917. * dedicated for data and 1 for command.
  1918. * "queue_id" maps to one hardware ring.
  1919. * With each ring, we also associate a unique Tx descriptor pool
  1920. * to minimize lock contention for these resources.
  1921. */
  1922. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1923. /*
  1924. * TCL H/W supports 2 DSCP-TID mapping tables.
  1925. * Table 1 - Default DSCP-TID mapping table
  1926. * Table 2 - 1 DSCP-TID override table
  1927. *
  1928. * If we need a different DSCP-TID mapping for this vap,
  1929. * call tid_classify to extract DSCP/ToS from frame and
  1930. * map to a TID and store in msdu_info. This is later used
  1931. * to fill in TCL Input descriptor (per-packet TID override).
  1932. */
  1933. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1934. /*
  1935. * Classify the frame and call corresponding
  1936. * "prepare" function which extracts the segment (TSO)
  1937. * and fragmentation information (for TSO , SG, ME, or Raw)
  1938. * into MSDU_INFO structure which is later used to fill
  1939. * SW and HW descriptors.
  1940. */
  1941. if (qdf_nbuf_is_tso(nbuf)) {
  1942. dp_verbose_debug("TSO frame %pK", vdev);
  1943. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1944. qdf_nbuf_len(nbuf));
  1945. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1946. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1947. qdf_nbuf_len(nbuf));
  1948. return nbuf;
  1949. }
  1950. goto send_multiple;
  1951. }
  1952. /* SG */
  1953. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1954. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1955. if (!nbuf)
  1956. return NULL;
  1957. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1958. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1959. qdf_nbuf_len(nbuf));
  1960. goto send_multiple;
  1961. }
  1962. #ifdef ATH_SUPPORT_IQUE
  1963. /* Mcast to Ucast Conversion*/
  1964. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1965. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1966. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1967. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1968. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1969. DP_STATS_INC_PKT(vdev,
  1970. tx_i.mcast_en.mcast_pkt, 1,
  1971. qdf_nbuf_len(nbuf));
  1972. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1973. QDF_STATUS_SUCCESS) {
  1974. return NULL;
  1975. }
  1976. }
  1977. }
  1978. #endif
  1979. /* RAW */
  1980. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1981. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1982. if (!nbuf)
  1983. return NULL;
  1984. dp_verbose_debug("Raw frame %pK", vdev);
  1985. goto send_multiple;
  1986. }
  1987. /* Single linear frame */
  1988. /*
  1989. * If nbuf is a simple linear frame, use send_single function to
  1990. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1991. * SRNG. There is no need to setup a MSDU extension descriptor.
  1992. */
  1993. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1994. return nbuf;
  1995. send_multiple:
  1996. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1997. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  1998. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  1999. return nbuf;
  2000. }
  2001. /**
  2002. * dp_tx_reinject_handler() - Tx Reinject Handler
  2003. * @tx_desc: software descriptor head pointer
  2004. * @status : Tx completion status from HTT descriptor
  2005. *
  2006. * This function reinjects frames back to Target.
  2007. * Todo - Host queue needs to be added
  2008. *
  2009. * Return: none
  2010. */
  2011. static
  2012. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2013. {
  2014. struct dp_vdev *vdev;
  2015. struct dp_peer *peer = NULL;
  2016. uint32_t peer_id = HTT_INVALID_PEER;
  2017. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2018. qdf_nbuf_t nbuf_copy = NULL;
  2019. struct dp_tx_msdu_info_s msdu_info;
  2020. struct dp_peer *sa_peer = NULL;
  2021. struct dp_ast_entry *ast_entry = NULL;
  2022. struct dp_soc *soc = NULL;
  2023. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2024. #ifdef WDS_VENDOR_EXTENSION
  2025. int is_mcast = 0, is_ucast = 0;
  2026. int num_peers_3addr = 0;
  2027. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2028. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2029. #endif
  2030. vdev = tx_desc->vdev;
  2031. soc = vdev->pdev->soc;
  2032. qdf_assert(vdev);
  2033. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2034. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2035. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2036. "%s Tx reinject path", __func__);
  2037. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2038. qdf_nbuf_len(tx_desc->nbuf));
  2039. qdf_spin_lock_bh(&(soc->ast_lock));
  2040. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2041. (soc,
  2042. (uint8_t *)(eh->ether_shost),
  2043. vdev->pdev->pdev_id);
  2044. if (ast_entry)
  2045. sa_peer = ast_entry->peer;
  2046. qdf_spin_unlock_bh(&(soc->ast_lock));
  2047. #ifdef WDS_VENDOR_EXTENSION
  2048. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2049. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2050. } else {
  2051. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2052. }
  2053. is_ucast = !is_mcast;
  2054. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2055. if (peer->bss_peer)
  2056. continue;
  2057. /* Detect wds peers that use 3-addr framing for mcast.
  2058. * if there are any, the bss_peer is used to send the
  2059. * the mcast frame using 3-addr format. all wds enabled
  2060. * peers that use 4-addr framing for mcast frames will
  2061. * be duplicated and sent as 4-addr frames below.
  2062. */
  2063. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2064. num_peers_3addr = 1;
  2065. break;
  2066. }
  2067. }
  2068. #endif
  2069. if (qdf_unlikely(vdev->mesh_vdev)) {
  2070. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2071. } else {
  2072. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2073. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2074. #ifdef WDS_VENDOR_EXTENSION
  2075. /*
  2076. * . if 3-addr STA, then send on BSS Peer
  2077. * . if Peer WDS enabled and accept 4-addr mcast,
  2078. * send mcast on that peer only
  2079. * . if Peer WDS enabled and accept 4-addr ucast,
  2080. * send ucast on that peer only
  2081. */
  2082. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2083. (peer->wds_enabled &&
  2084. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2085. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2086. #else
  2087. ((peer->bss_peer &&
  2088. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2089. peer->nawds_enabled)) {
  2090. #endif
  2091. peer_id = DP_INVALID_PEER;
  2092. if (peer->nawds_enabled) {
  2093. peer_id = peer->peer_ids[0];
  2094. if (sa_peer == peer) {
  2095. QDF_TRACE(
  2096. QDF_MODULE_ID_DP,
  2097. QDF_TRACE_LEVEL_DEBUG,
  2098. " %s: multicast packet",
  2099. __func__);
  2100. DP_STATS_INC(peer,
  2101. tx.nawds_mcast_drop, 1);
  2102. continue;
  2103. }
  2104. }
  2105. nbuf_copy = qdf_nbuf_copy(nbuf);
  2106. if (!nbuf_copy) {
  2107. QDF_TRACE(QDF_MODULE_ID_DP,
  2108. QDF_TRACE_LEVEL_DEBUG,
  2109. FL("nbuf copy failed"));
  2110. break;
  2111. }
  2112. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2113. nbuf_copy,
  2114. &msdu_info,
  2115. peer_id,
  2116. NULL);
  2117. if (nbuf_copy) {
  2118. QDF_TRACE(QDF_MODULE_ID_DP,
  2119. QDF_TRACE_LEVEL_DEBUG,
  2120. FL("pkt send failed"));
  2121. qdf_nbuf_free(nbuf_copy);
  2122. } else {
  2123. if (peer_id != DP_INVALID_PEER)
  2124. DP_STATS_INC_PKT(peer,
  2125. tx.nawds_mcast,
  2126. 1, qdf_nbuf_len(nbuf));
  2127. }
  2128. }
  2129. }
  2130. }
  2131. if (vdev->nawds_enabled) {
  2132. peer_id = DP_INVALID_PEER;
  2133. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2134. 1, qdf_nbuf_len(nbuf));
  2135. nbuf = dp_tx_send_msdu_single(vdev,
  2136. nbuf,
  2137. &msdu_info,
  2138. peer_id, NULL);
  2139. if (nbuf) {
  2140. QDF_TRACE(QDF_MODULE_ID_DP,
  2141. QDF_TRACE_LEVEL_DEBUG,
  2142. FL("pkt send failed"));
  2143. qdf_nbuf_free(nbuf);
  2144. }
  2145. } else
  2146. qdf_nbuf_free(nbuf);
  2147. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2148. }
  2149. /**
  2150. * dp_tx_inspect_handler() - Tx Inspect Handler
  2151. * @tx_desc: software descriptor head pointer
  2152. * @status : Tx completion status from HTT descriptor
  2153. *
  2154. * Handles Tx frames sent back to Host for inspection
  2155. * (ProxyARP)
  2156. *
  2157. * Return: none
  2158. */
  2159. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2160. {
  2161. struct dp_soc *soc;
  2162. struct dp_pdev *pdev = tx_desc->pdev;
  2163. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2164. "%s Tx inspect path",
  2165. __func__);
  2166. qdf_assert(pdev);
  2167. soc = pdev->soc;
  2168. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2169. qdf_nbuf_len(tx_desc->nbuf));
  2170. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2171. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2172. }
  2173. #ifdef FEATURE_PERPKT_INFO
  2174. /**
  2175. * dp_get_completion_indication_for_stack() - send completion to stack
  2176. * @soc : dp_soc handle
  2177. * @pdev: dp_pdev handle
  2178. * @peer: dp peer handle
  2179. * @ts: transmit completion status structure
  2180. * @netbuf: Buffer pointer for free
  2181. *
  2182. * This function is used for indication whether buffer needs to be
  2183. * sent to stack for freeing or not
  2184. */
  2185. QDF_STATUS
  2186. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2187. struct dp_pdev *pdev,
  2188. struct dp_peer *peer,
  2189. struct hal_tx_completion_status *ts,
  2190. qdf_nbuf_t netbuf,
  2191. uint64_t time_latency)
  2192. {
  2193. struct tx_capture_hdr *ppdu_hdr;
  2194. uint16_t peer_id = ts->peer_id;
  2195. uint32_t ppdu_id = ts->ppdu_id;
  2196. uint8_t first_msdu = ts->first_msdu;
  2197. uint8_t last_msdu = ts->last_msdu;
  2198. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2199. !pdev->latency_capture_enable))
  2200. return QDF_STATUS_E_NOSUPPORT;
  2201. if (!peer) {
  2202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2203. FL("Peer Invalid"));
  2204. return QDF_STATUS_E_INVAL;
  2205. }
  2206. if (pdev->mcopy_mode) {
  2207. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2208. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2209. return QDF_STATUS_E_INVAL;
  2210. }
  2211. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2212. pdev->m_copy_id.tx_peer_id = peer_id;
  2213. }
  2214. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2216. FL("No headroom"));
  2217. return QDF_STATUS_E_NOMEM;
  2218. }
  2219. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2220. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2221. QDF_MAC_ADDR_SIZE);
  2222. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2223. QDF_MAC_ADDR_SIZE);
  2224. ppdu_hdr->ppdu_id = ppdu_id;
  2225. ppdu_hdr->peer_id = peer_id;
  2226. ppdu_hdr->first_msdu = first_msdu;
  2227. ppdu_hdr->last_msdu = last_msdu;
  2228. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2229. ppdu_hdr->tsf = ts->tsf;
  2230. ppdu_hdr->time_latency = time_latency;
  2231. }
  2232. return QDF_STATUS_SUCCESS;
  2233. }
  2234. /**
  2235. * dp_send_completion_to_stack() - send completion to stack
  2236. * @soc : dp_soc handle
  2237. * @pdev: dp_pdev handle
  2238. * @peer_id: peer_id of the peer for which completion came
  2239. * @ppdu_id: ppdu_id
  2240. * @netbuf: Buffer pointer for free
  2241. *
  2242. * This function is used to send completion to stack
  2243. * to free buffer
  2244. */
  2245. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2246. uint16_t peer_id, uint32_t ppdu_id,
  2247. qdf_nbuf_t netbuf)
  2248. {
  2249. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2250. netbuf, peer_id,
  2251. WDI_NO_VAL, pdev->pdev_id);
  2252. }
  2253. #else
  2254. static QDF_STATUS
  2255. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2256. struct dp_pdev *pdev,
  2257. struct dp_peer *peer,
  2258. struct hal_tx_completion_status *ts,
  2259. qdf_nbuf_t netbuf,
  2260. uint64_t time_latency)
  2261. {
  2262. return QDF_STATUS_E_NOSUPPORT;
  2263. }
  2264. static void
  2265. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2266. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2267. {
  2268. }
  2269. #endif
  2270. /**
  2271. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2272. * @soc: Soc handle
  2273. * @desc: software Tx descriptor to be processed
  2274. *
  2275. * Return: none
  2276. */
  2277. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2278. struct dp_tx_desc_s *desc)
  2279. {
  2280. struct dp_vdev *vdev = desc->vdev;
  2281. qdf_nbuf_t nbuf = desc->nbuf;
  2282. /* nbuf already freed in vdev detach path */
  2283. if (!nbuf)
  2284. return;
  2285. /* If it is TDLS mgmt, don't unmap or free the frame */
  2286. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2287. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2288. /* 0 : MSDU buffer, 1 : MLE */
  2289. if (desc->msdu_ext_desc) {
  2290. /* TSO free */
  2291. if (hal_tx_ext_desc_get_tso_enable(
  2292. desc->msdu_ext_desc->vaddr)) {
  2293. /* unmap eash TSO seg before free the nbuf */
  2294. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2295. desc->tso_num_desc);
  2296. qdf_nbuf_free(nbuf);
  2297. return;
  2298. }
  2299. }
  2300. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2301. if (qdf_unlikely(!vdev)) {
  2302. qdf_nbuf_free(nbuf);
  2303. return;
  2304. }
  2305. if (qdf_likely(!vdev->mesh_vdev))
  2306. qdf_nbuf_free(nbuf);
  2307. else {
  2308. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2309. qdf_nbuf_free(nbuf);
  2310. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2311. } else
  2312. vdev->osif_tx_free_ext((nbuf));
  2313. }
  2314. }
  2315. #ifdef MESH_MODE_SUPPORT
  2316. /**
  2317. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2318. * in mesh meta header
  2319. * @tx_desc: software descriptor head pointer
  2320. * @ts: pointer to tx completion stats
  2321. * Return: none
  2322. */
  2323. static
  2324. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2325. struct hal_tx_completion_status *ts)
  2326. {
  2327. struct meta_hdr_s *mhdr;
  2328. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2329. if (!tx_desc->msdu_ext_desc) {
  2330. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2331. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2332. "netbuf %pK offset %d",
  2333. netbuf, tx_desc->pkt_offset);
  2334. return;
  2335. }
  2336. }
  2337. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2338. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2339. "netbuf %pK offset %lu", netbuf,
  2340. sizeof(struct meta_hdr_s));
  2341. return;
  2342. }
  2343. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2344. mhdr->rssi = ts->ack_frame_rssi;
  2345. mhdr->channel = tx_desc->pdev->operating_channel;
  2346. }
  2347. #else
  2348. static
  2349. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2350. struct hal_tx_completion_status *ts)
  2351. {
  2352. }
  2353. #endif
  2354. /**
  2355. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2356. * to pass in correct fields
  2357. *
  2358. * @vdev: pdev handle
  2359. * @tx_desc: tx descriptor
  2360. * @tid: tid value
  2361. * @ring_id: TCL or WBM ring number for transmit path
  2362. * Return: none
  2363. */
  2364. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2365. struct dp_tx_desc_s *tx_desc,
  2366. uint8_t tid, uint8_t ring_id)
  2367. {
  2368. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2369. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2370. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2371. return;
  2372. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2373. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2374. timestamp_hw_enqueue = tx_desc->timestamp;
  2375. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2376. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2377. timestamp_hw_enqueue);
  2378. interframe_delay = (uint32_t)(timestamp_ingress -
  2379. vdev->prev_tx_enq_tstamp);
  2380. /*
  2381. * Delay in software enqueue
  2382. */
  2383. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2384. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2385. /*
  2386. * Delay between packet enqueued to HW and Tx completion
  2387. */
  2388. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2389. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2390. /*
  2391. * Update interframe delay stats calculated at hardstart receive point.
  2392. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2393. * interframe delay will not be calculate correctly for 1st frame.
  2394. * On the other side, this will help in avoiding extra per packet check
  2395. * of !vdev->prev_tx_enq_tstamp.
  2396. */
  2397. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2398. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2399. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2400. }
  2401. /**
  2402. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2403. * per wbm ring
  2404. *
  2405. * @tx_desc: software descriptor head pointer
  2406. * @ts: Tx completion status
  2407. * @peer: peer handle
  2408. * @ring_id: ring number
  2409. *
  2410. * Return: None
  2411. */
  2412. static inline void
  2413. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2414. struct hal_tx_completion_status *ts,
  2415. struct dp_peer *peer, uint8_t ring_id)
  2416. {
  2417. struct dp_pdev *pdev = peer->vdev->pdev;
  2418. struct dp_soc *soc = NULL;
  2419. uint8_t mcs, pkt_type;
  2420. uint8_t tid = ts->tid;
  2421. uint32_t length;
  2422. struct cdp_tid_tx_stats *tid_stats;
  2423. if (!pdev)
  2424. return;
  2425. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2426. tid = CDP_MAX_DATA_TIDS - 1;
  2427. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2428. soc = pdev->soc;
  2429. mcs = ts->mcs;
  2430. pkt_type = ts->pkt_type;
  2431. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2432. dp_err("Release source is not from TQM");
  2433. return;
  2434. }
  2435. length = qdf_nbuf_len(tx_desc->nbuf);
  2436. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2437. if (qdf_unlikely(pdev->delay_stats_flag))
  2438. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2439. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2440. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2441. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2442. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2443. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2444. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2445. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2446. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2447. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2448. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2449. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2450. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2451. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2452. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2453. /*
  2454. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2455. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2456. * are no completions for failed cases. Hence updating tx_failed from
  2457. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2458. * then this has to be removed
  2459. */
  2460. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2461. peer->stats.tx.dropped.fw_rem_notx +
  2462. peer->stats.tx.dropped.fw_rem_tx +
  2463. peer->stats.tx.dropped.age_out +
  2464. peer->stats.tx.dropped.fw_reason1 +
  2465. peer->stats.tx.dropped.fw_reason2 +
  2466. peer->stats.tx.dropped.fw_reason3;
  2467. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2468. tid_stats->tqm_status_cnt[ts->status]++;
  2469. }
  2470. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2471. return;
  2472. }
  2473. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2474. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2475. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2476. /*
  2477. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2478. * Return from here if HTT PPDU events are enabled.
  2479. */
  2480. if (!(soc->process_tx_status))
  2481. return;
  2482. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2483. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2484. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2485. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2486. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2487. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2488. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2489. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2490. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2491. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2492. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2493. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2494. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2495. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2496. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2497. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2498. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2499. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2500. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2501. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2502. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2503. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2504. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2505. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2506. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2507. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2508. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2509. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2510. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2511. &peer->stats, ts->peer_id,
  2512. UPDATE_PEER_STATS, pdev->pdev_id);
  2513. #endif
  2514. }
  2515. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2516. /**
  2517. * dp_tx_flow_pool_lock() - take flow pool lock
  2518. * @soc: core txrx main context
  2519. * @tx_desc: tx desc
  2520. *
  2521. * Return: None
  2522. */
  2523. static inline
  2524. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2525. struct dp_tx_desc_s *tx_desc)
  2526. {
  2527. struct dp_tx_desc_pool_s *pool;
  2528. uint8_t desc_pool_id;
  2529. desc_pool_id = tx_desc->pool_id;
  2530. pool = &soc->tx_desc[desc_pool_id];
  2531. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2532. }
  2533. /**
  2534. * dp_tx_flow_pool_unlock() - release flow pool lock
  2535. * @soc: core txrx main context
  2536. * @tx_desc: tx desc
  2537. *
  2538. * Return: None
  2539. */
  2540. static inline
  2541. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2542. struct dp_tx_desc_s *tx_desc)
  2543. {
  2544. struct dp_tx_desc_pool_s *pool;
  2545. uint8_t desc_pool_id;
  2546. desc_pool_id = tx_desc->pool_id;
  2547. pool = &soc->tx_desc[desc_pool_id];
  2548. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2549. }
  2550. #else
  2551. static inline
  2552. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2553. {
  2554. }
  2555. static inline
  2556. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2557. {
  2558. }
  2559. #endif
  2560. /**
  2561. * dp_tx_notify_completion() - Notify tx completion for this desc
  2562. * @soc: core txrx main context
  2563. * @tx_desc: tx desc
  2564. * @netbuf: buffer
  2565. *
  2566. * Return: none
  2567. */
  2568. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2569. struct dp_tx_desc_s *tx_desc,
  2570. qdf_nbuf_t netbuf)
  2571. {
  2572. void *osif_dev;
  2573. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2574. qdf_assert(tx_desc);
  2575. dp_tx_flow_pool_lock(soc, tx_desc);
  2576. if (!tx_desc->vdev ||
  2577. !tx_desc->vdev->osif_vdev) {
  2578. dp_tx_flow_pool_unlock(soc, tx_desc);
  2579. return;
  2580. }
  2581. osif_dev = tx_desc->vdev->osif_vdev;
  2582. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2583. dp_tx_flow_pool_unlock(soc, tx_desc);
  2584. if (tx_compl_cbk)
  2585. tx_compl_cbk(netbuf, osif_dev);
  2586. }
  2587. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2588. * @pdev: pdev handle
  2589. * @tid: tid value
  2590. * @txdesc_ts: timestamp from txdesc
  2591. * @ppdu_id: ppdu id
  2592. *
  2593. * Return: none
  2594. */
  2595. #ifdef FEATURE_PERPKT_INFO
  2596. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2597. struct dp_peer *peer,
  2598. uint8_t tid,
  2599. uint64_t txdesc_ts,
  2600. uint32_t ppdu_id)
  2601. {
  2602. uint64_t delta_ms;
  2603. struct cdp_tx_sojourn_stats *sojourn_stats;
  2604. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2605. return;
  2606. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2607. tid >= CDP_DATA_TID_MAX))
  2608. return;
  2609. if (qdf_unlikely(!pdev->sojourn_buf))
  2610. return;
  2611. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2612. qdf_nbuf_data(pdev->sojourn_buf);
  2613. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2614. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2615. txdesc_ts;
  2616. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2617. delta_ms);
  2618. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2619. sojourn_stats->num_msdus[tid] = 1;
  2620. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2621. peer->avg_sojourn_msdu[tid].internal;
  2622. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2623. pdev->sojourn_buf, HTT_INVALID_PEER,
  2624. WDI_NO_VAL, pdev->pdev_id);
  2625. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2626. sojourn_stats->num_msdus[tid] = 0;
  2627. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2628. }
  2629. #else
  2630. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2631. uint8_t tid,
  2632. uint64_t txdesc_ts,
  2633. uint32_t ppdu_id)
  2634. {
  2635. }
  2636. #endif
  2637. /**
  2638. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2639. * @soc: DP Soc handle
  2640. * @tx_desc: software Tx descriptor
  2641. * @ts : Tx completion status from HAL/HTT descriptor
  2642. *
  2643. * Return: none
  2644. */
  2645. static inline void
  2646. dp_tx_comp_process_desc(struct dp_soc *soc,
  2647. struct dp_tx_desc_s *desc,
  2648. struct hal_tx_completion_status *ts,
  2649. struct dp_peer *peer)
  2650. {
  2651. uint64_t time_latency = 0;
  2652. /*
  2653. * m_copy/tx_capture modes are not supported for
  2654. * scatter gather packets
  2655. */
  2656. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2657. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2658. desc->timestamp);
  2659. }
  2660. if (!(desc->msdu_ext_desc)) {
  2661. if (QDF_STATUS_SUCCESS ==
  2662. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2663. return;
  2664. }
  2665. if (QDF_STATUS_SUCCESS ==
  2666. dp_get_completion_indication_for_stack(soc,
  2667. desc->pdev,
  2668. peer, ts,
  2669. desc->nbuf,
  2670. time_latency)) {
  2671. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2672. QDF_DMA_TO_DEVICE);
  2673. dp_send_completion_to_stack(soc,
  2674. desc->pdev,
  2675. ts->peer_id,
  2676. ts->ppdu_id,
  2677. desc->nbuf);
  2678. return;
  2679. }
  2680. }
  2681. dp_tx_comp_free_buf(soc, desc);
  2682. }
  2683. /**
  2684. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2685. * @tx_desc: software descriptor head pointer
  2686. * @ts: Tx completion status
  2687. * @peer: peer handle
  2688. * @ring_id: ring number
  2689. *
  2690. * Return: none
  2691. */
  2692. static inline
  2693. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2694. struct hal_tx_completion_status *ts,
  2695. struct dp_peer *peer, uint8_t ring_id)
  2696. {
  2697. uint32_t length;
  2698. qdf_ether_header_t *eh;
  2699. struct dp_soc *soc = NULL;
  2700. struct dp_vdev *vdev = tx_desc->vdev;
  2701. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2702. if (!vdev || !nbuf) {
  2703. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2704. "invalid tx descriptor. vdev or nbuf NULL");
  2705. goto out;
  2706. }
  2707. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2708. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2709. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2710. QDF_TRACE_DEFAULT_PDEV_ID,
  2711. qdf_nbuf_data_addr(nbuf),
  2712. sizeof(qdf_nbuf_data(nbuf)),
  2713. tx_desc->id,
  2714. ts->status));
  2715. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2716. "-------------------- \n"
  2717. "Tx Completion Stats: \n"
  2718. "-------------------- \n"
  2719. "ack_frame_rssi = %d \n"
  2720. "first_msdu = %d \n"
  2721. "last_msdu = %d \n"
  2722. "msdu_part_of_amsdu = %d \n"
  2723. "rate_stats valid = %d \n"
  2724. "bw = %d \n"
  2725. "pkt_type = %d \n"
  2726. "stbc = %d \n"
  2727. "ldpc = %d \n"
  2728. "sgi = %d \n"
  2729. "mcs = %d \n"
  2730. "ofdma = %d \n"
  2731. "tones_in_ru = %d \n"
  2732. "tsf = %d \n"
  2733. "ppdu_id = %d \n"
  2734. "transmit_cnt = %d \n"
  2735. "tid = %d \n"
  2736. "peer_id = %d\n",
  2737. ts->ack_frame_rssi, ts->first_msdu,
  2738. ts->last_msdu, ts->msdu_part_of_amsdu,
  2739. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2740. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2741. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2742. ts->transmit_cnt, ts->tid, ts->peer_id);
  2743. soc = vdev->pdev->soc;
  2744. /* Update SoC level stats */
  2745. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2746. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2747. /* Update per-packet stats for mesh mode */
  2748. if (qdf_unlikely(vdev->mesh_vdev) &&
  2749. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2750. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2751. length = qdf_nbuf_len(nbuf);
  2752. /* Update peer level stats */
  2753. if (!peer) {
  2754. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2755. "peer is null or deletion in progress");
  2756. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2757. goto out;
  2758. }
  2759. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2760. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2761. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2762. if ((peer->vdev->tx_encap_type ==
  2763. htt_cmn_pkt_type_ethernet) &&
  2764. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2765. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2766. }
  2767. }
  2768. } else {
  2769. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2770. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2771. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2772. }
  2773. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2774. #ifdef QCA_SUPPORT_RDK_STATS
  2775. if (soc->wlanstats_enabled)
  2776. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2777. tx_desc->timestamp,
  2778. ts->ppdu_id);
  2779. #endif
  2780. out:
  2781. return;
  2782. }
  2783. /**
  2784. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2785. * @soc: core txrx main context
  2786. * @comp_head: software descriptor head pointer
  2787. * @ring_id: ring number
  2788. *
  2789. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2790. * and release the software descriptors after processing is complete
  2791. *
  2792. * Return: none
  2793. */
  2794. static void
  2795. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2796. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2797. {
  2798. struct dp_tx_desc_s *desc;
  2799. struct dp_tx_desc_s *next;
  2800. struct hal_tx_completion_status ts = {0};
  2801. struct dp_peer *peer;
  2802. qdf_nbuf_t netbuf;
  2803. desc = comp_head;
  2804. while (desc) {
  2805. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2806. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2807. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2808. netbuf = desc->nbuf;
  2809. /* check tx complete notification */
  2810. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2811. dp_tx_notify_completion(soc, desc, netbuf);
  2812. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2813. if (peer)
  2814. dp_peer_unref_del_find_by_id(peer);
  2815. next = desc->next;
  2816. dp_tx_desc_release(desc, desc->pool_id);
  2817. desc = next;
  2818. }
  2819. }
  2820. /**
  2821. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2822. * @tx_desc: software descriptor head pointer
  2823. * @status : Tx completion status from HTT descriptor
  2824. * @ring_id: ring number
  2825. *
  2826. * This function will process HTT Tx indication messages from Target
  2827. *
  2828. * Return: none
  2829. */
  2830. static
  2831. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2832. uint8_t ring_id)
  2833. {
  2834. uint8_t tx_status;
  2835. struct dp_pdev *pdev;
  2836. struct dp_vdev *vdev;
  2837. struct dp_soc *soc;
  2838. struct hal_tx_completion_status ts = {0};
  2839. uint32_t *htt_desc = (uint32_t *)status;
  2840. struct dp_peer *peer;
  2841. struct cdp_tid_tx_stats *tid_stats = NULL;
  2842. struct htt_soc *htt_handle;
  2843. qdf_assert(tx_desc->pdev);
  2844. pdev = tx_desc->pdev;
  2845. vdev = tx_desc->vdev;
  2846. soc = pdev->soc;
  2847. if (!vdev)
  2848. return;
  2849. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2850. htt_handle = (struct htt_soc *)soc->htt_handle;
  2851. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2852. switch (tx_status) {
  2853. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2854. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2855. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2856. {
  2857. uint8_t tid;
  2858. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2859. ts.peer_id =
  2860. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2861. htt_desc[2]);
  2862. ts.tid =
  2863. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2864. htt_desc[2]);
  2865. } else {
  2866. ts.peer_id = HTT_INVALID_PEER;
  2867. ts.tid = HTT_INVALID_TID;
  2868. }
  2869. ts.ppdu_id =
  2870. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2871. htt_desc[1]);
  2872. ts.ack_frame_rssi =
  2873. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2874. htt_desc[1]);
  2875. ts.first_msdu = 1;
  2876. ts.last_msdu = 1;
  2877. tid = ts.tid;
  2878. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2879. tid = CDP_MAX_DATA_TIDS - 1;
  2880. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2881. if (qdf_unlikely(pdev->delay_stats_flag))
  2882. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2883. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  2884. tid_stats->htt_status_cnt[tx_status]++;
  2885. }
  2886. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2887. if (qdf_likely(peer))
  2888. dp_peer_unref_del_find_by_id(peer);
  2889. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2890. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2891. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2892. break;
  2893. }
  2894. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2895. {
  2896. dp_tx_reinject_handler(tx_desc, status);
  2897. break;
  2898. }
  2899. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2900. {
  2901. dp_tx_inspect_handler(tx_desc, status);
  2902. break;
  2903. }
  2904. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2905. {
  2906. dp_tx_mec_handler(vdev, status);
  2907. break;
  2908. }
  2909. default:
  2910. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2911. "%s Invalid HTT tx_status %d\n",
  2912. __func__, tx_status);
  2913. break;
  2914. }
  2915. }
  2916. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2917. static inline
  2918. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2919. {
  2920. bool limit_hit = false;
  2921. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2922. limit_hit =
  2923. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2924. if (limit_hit)
  2925. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2926. return limit_hit;
  2927. }
  2928. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2929. {
  2930. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2931. }
  2932. #else
  2933. static inline
  2934. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2935. {
  2936. return false;
  2937. }
  2938. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2939. {
  2940. return false;
  2941. }
  2942. #endif
  2943. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2944. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  2945. uint32_t quota)
  2946. {
  2947. void *tx_comp_hal_desc;
  2948. uint8_t buffer_src;
  2949. uint8_t pool_id;
  2950. uint32_t tx_desc_id;
  2951. struct dp_tx_desc_s *tx_desc = NULL;
  2952. struct dp_tx_desc_s *head_desc = NULL;
  2953. struct dp_tx_desc_s *tail_desc = NULL;
  2954. uint32_t num_processed = 0;
  2955. uint32_t count = 0;
  2956. bool force_break = false;
  2957. DP_HIST_INIT();
  2958. more_data:
  2959. /* Re-initialize local variables to be re-used */
  2960. head_desc = NULL;
  2961. tail_desc = NULL;
  2962. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  2963. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2964. "%s %d : HAL RING Access Failed -- %pK",
  2965. __func__, __LINE__, hal_ring_hdl);
  2966. return 0;
  2967. }
  2968. /* Find head descriptor from completion ring */
  2969. while (qdf_likely(tx_comp_hal_desc =
  2970. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  2971. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2972. /* If this buffer was not released by TQM or FW, then it is not
  2973. * Tx completion indication, assert */
  2974. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2975. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2976. uint8_t wbm_internal_error;
  2977. QDF_TRACE(QDF_MODULE_ID_DP,
  2978. QDF_TRACE_LEVEL_FATAL,
  2979. "Tx comp release_src != TQM | FW but from %d",
  2980. buffer_src);
  2981. hal_dump_comp_desc(tx_comp_hal_desc);
  2982. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2983. /* When WBM sees NULL buffer_addr_info in any of
  2984. * ingress rings it sends an error indication,
  2985. * with wbm_internal_error=1, to a specific ring.
  2986. * The WBM2SW ring used to indicate these errors is
  2987. * fixed in HW, and that ring is being used as Tx
  2988. * completion ring. These errors are not related to
  2989. * Tx completions, and should just be ignored
  2990. */
  2991. wbm_internal_error =
  2992. hal_get_wbm_internal_error(tx_comp_hal_desc);
  2993. if (wbm_internal_error) {
  2994. QDF_TRACE(QDF_MODULE_ID_DP,
  2995. QDF_TRACE_LEVEL_ERROR,
  2996. "Tx comp wbm_internal_error!!!\n");
  2997. DP_STATS_INC(soc, tx.wbm_internal_error, 1);
  2998. continue;
  2999. } else {
  3000. qdf_assert_always(0);
  3001. }
  3002. }
  3003. /* Get descriptor id */
  3004. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3005. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3006. DP_TX_DESC_ID_POOL_OS;
  3007. /* Find Tx descriptor */
  3008. tx_desc = dp_tx_desc_find(soc, pool_id,
  3009. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3010. DP_TX_DESC_ID_PAGE_OS,
  3011. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3012. DP_TX_DESC_ID_OFFSET_OS);
  3013. /*
  3014. * If the descriptor is already freed in vdev_detach,
  3015. * continue to next descriptor
  3016. */
  3017. if (!tx_desc->vdev && !tx_desc->flags) {
  3018. QDF_TRACE(QDF_MODULE_ID_DP,
  3019. QDF_TRACE_LEVEL_INFO,
  3020. "Descriptor freed in vdev_detach %d",
  3021. tx_desc_id);
  3022. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3023. count++;
  3024. continue;
  3025. }
  3026. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3027. QDF_TRACE(QDF_MODULE_ID_DP,
  3028. QDF_TRACE_LEVEL_INFO,
  3029. "pdev in down state %d",
  3030. tx_desc_id);
  3031. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3032. count++;
  3033. dp_tx_comp_free_buf(soc, tx_desc);
  3034. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3035. continue;
  3036. }
  3037. /*
  3038. * If the release source is FW, process the HTT status
  3039. */
  3040. if (qdf_unlikely(buffer_src ==
  3041. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3042. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3043. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3044. htt_tx_status);
  3045. dp_tx_process_htt_completion(tx_desc,
  3046. htt_tx_status, ring_id);
  3047. } else {
  3048. /* Pool id is not matching. Error */
  3049. if (tx_desc->pool_id != pool_id) {
  3050. QDF_TRACE(QDF_MODULE_ID_DP,
  3051. QDF_TRACE_LEVEL_FATAL,
  3052. "Tx Comp pool id %d not matched %d",
  3053. pool_id, tx_desc->pool_id);
  3054. qdf_assert_always(0);
  3055. }
  3056. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3057. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3058. QDF_TRACE(QDF_MODULE_ID_DP,
  3059. QDF_TRACE_LEVEL_FATAL,
  3060. "Txdesc invalid, flgs = %x,id = %d",
  3061. tx_desc->flags, tx_desc_id);
  3062. qdf_assert_always(0);
  3063. }
  3064. /* First ring descriptor on the cycle */
  3065. if (!head_desc) {
  3066. head_desc = tx_desc;
  3067. tail_desc = tx_desc;
  3068. }
  3069. tail_desc->next = tx_desc;
  3070. tx_desc->next = NULL;
  3071. tail_desc = tx_desc;
  3072. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3073. /* Collect hw completion contents */
  3074. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3075. &tx_desc->comp, 1);
  3076. }
  3077. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3078. /*
  3079. * Processed packet count is more than given quota
  3080. * stop to processing
  3081. */
  3082. if (num_processed >= quota) {
  3083. force_break = true;
  3084. break;
  3085. }
  3086. count++;
  3087. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3088. break;
  3089. }
  3090. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3091. /* Process the reaped descriptors */
  3092. if (head_desc)
  3093. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3094. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3095. if (!force_break &&
  3096. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3097. hal_ring_hdl)) {
  3098. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3099. if (!hif_exec_should_yield(soc->hif_handle,
  3100. int_ctx->dp_intr_id))
  3101. goto more_data;
  3102. }
  3103. }
  3104. DP_TX_HIST_STATS_PER_PDEV();
  3105. return num_processed;
  3106. }
  3107. #ifdef FEATURE_WLAN_TDLS
  3108. /**
  3109. * dp_tx_non_std() - Allow the control-path SW to send data frames
  3110. *
  3111. * @data_vdev - which vdev should transmit the tx data frames
  3112. * @tx_spec - what non-standard handling to apply to the tx data frames
  3113. * @msdu_list - NULL-terminated list of tx MSDUs
  3114. *
  3115. * Return: NULL on success,
  3116. * nbuf when it fails to send
  3117. */
  3118. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  3119. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3120. {
  3121. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3122. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3123. vdev->is_tdls_frame = true;
  3124. return dp_tx_send(vdev_handle, msdu_list);
  3125. }
  3126. #endif
  3127. /**
  3128. * dp_tx_vdev_attach() - attach vdev to dp tx
  3129. * @vdev: virtual device instance
  3130. *
  3131. * Return: QDF_STATUS_SUCCESS: success
  3132. * QDF_STATUS_E_RESOURCES: Error return
  3133. */
  3134. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3135. {
  3136. /*
  3137. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3138. */
  3139. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3140. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3141. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3142. vdev->vdev_id);
  3143. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3144. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3145. /*
  3146. * Set HTT Extension Valid bit to 0 by default
  3147. */
  3148. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3149. dp_tx_vdev_update_search_flags(vdev);
  3150. return QDF_STATUS_SUCCESS;
  3151. }
  3152. #ifndef FEATURE_WDS
  3153. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3154. {
  3155. return false;
  3156. }
  3157. #endif
  3158. /**
  3159. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3160. * @vdev: virtual device instance
  3161. *
  3162. * Return: void
  3163. *
  3164. */
  3165. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3166. {
  3167. struct dp_soc *soc = vdev->pdev->soc;
  3168. /*
  3169. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3170. * for TDLS link
  3171. *
  3172. * Enable AddrY (SA based search) only for non-WDS STA and
  3173. * ProxySTA VAP (in HKv1) modes.
  3174. *
  3175. * In all other VAP modes, only DA based search should be
  3176. * enabled
  3177. */
  3178. if (vdev->opmode == wlan_op_mode_sta &&
  3179. vdev->tdls_link_connected)
  3180. vdev->hal_desc_addr_search_flags =
  3181. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3182. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3183. !dp_tx_da_search_override(vdev))
  3184. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3185. else
  3186. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3187. /* Set search type only when peer map v2 messaging is enabled
  3188. * as we will have the search index (AST hash) only when v2 is
  3189. * enabled
  3190. */
  3191. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3192. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3193. else
  3194. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3195. }
  3196. static inline bool
  3197. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3198. struct dp_vdev *vdev,
  3199. struct dp_tx_desc_s *tx_desc)
  3200. {
  3201. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3202. return false;
  3203. /*
  3204. * if vdev is given, then only check whether desc
  3205. * vdev match. if vdev is NULL, then check whether
  3206. * desc pdev match.
  3207. */
  3208. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3209. }
  3210. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3211. /**
  3212. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3213. *
  3214. * @soc: Handle to DP SoC structure
  3215. * @tx_desc: pointer of one TX desc
  3216. * @desc_pool_id: TX Desc pool id
  3217. */
  3218. static inline void
  3219. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3220. uint8_t desc_pool_id)
  3221. {
  3222. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3223. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3224. tx_desc->vdev = NULL;
  3225. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3226. }
  3227. /**
  3228. * dp_tx_desc_flush() - release resources associated
  3229. * to TX Desc
  3230. *
  3231. * @dp_pdev: Handle to DP pdev structure
  3232. * @vdev: virtual device instance
  3233. * NULL: no specific Vdev is required and check all allcated TX desc
  3234. * on this pdev.
  3235. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3236. *
  3237. * @force_free:
  3238. * true: flush the TX desc.
  3239. * false: only reset the Vdev in each allocated TX desc
  3240. * that associated to current Vdev.
  3241. *
  3242. * This function will go through the TX desc pool to flush
  3243. * the outstanding TX data or reset Vdev to NULL in associated TX
  3244. * Desc.
  3245. */
  3246. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3247. struct dp_vdev *vdev,
  3248. bool force_free)
  3249. {
  3250. uint8_t i;
  3251. uint32_t j;
  3252. uint32_t num_desc, page_id, offset;
  3253. uint16_t num_desc_per_page;
  3254. struct dp_soc *soc = pdev->soc;
  3255. struct dp_tx_desc_s *tx_desc = NULL;
  3256. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3257. if (!vdev && !force_free) {
  3258. dp_err("Reset TX desc vdev, Vdev param is required!");
  3259. return;
  3260. }
  3261. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3262. tx_desc_pool = &soc->tx_desc[i];
  3263. if (!(tx_desc_pool->pool_size) ||
  3264. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3265. !(tx_desc_pool->desc_pages.cacheable_pages))
  3266. continue;
  3267. num_desc = tx_desc_pool->pool_size;
  3268. num_desc_per_page =
  3269. tx_desc_pool->desc_pages.num_element_per_page;
  3270. for (j = 0; j < num_desc; j++) {
  3271. page_id = j / num_desc_per_page;
  3272. offset = j % num_desc_per_page;
  3273. if (qdf_unlikely(!(tx_desc_pool->
  3274. desc_pages.cacheable_pages)))
  3275. break;
  3276. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3277. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3278. /*
  3279. * Free TX desc if force free is
  3280. * required, otherwise only reset vdev
  3281. * in this TX desc.
  3282. */
  3283. if (force_free) {
  3284. dp_tx_comp_free_buf(soc, tx_desc);
  3285. dp_tx_desc_release(tx_desc, i);
  3286. } else {
  3287. dp_tx_desc_reset_vdev(soc, tx_desc,
  3288. i);
  3289. }
  3290. }
  3291. }
  3292. }
  3293. }
  3294. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3295. static inline void
  3296. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3297. uint8_t desc_pool_id)
  3298. {
  3299. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3300. tx_desc->vdev = NULL;
  3301. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3302. }
  3303. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3304. struct dp_vdev *vdev,
  3305. bool force_free)
  3306. {
  3307. uint8_t i, num_pool;
  3308. uint32_t j;
  3309. uint32_t num_desc, page_id, offset;
  3310. uint16_t num_desc_per_page;
  3311. struct dp_soc *soc = pdev->soc;
  3312. struct dp_tx_desc_s *tx_desc = NULL;
  3313. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3314. if (!vdev && !force_free) {
  3315. dp_err("Reset TX desc vdev, Vdev param is required!");
  3316. return;
  3317. }
  3318. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3319. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3320. for (i = 0; i < num_pool; i++) {
  3321. tx_desc_pool = &soc->tx_desc[i];
  3322. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3323. continue;
  3324. num_desc_per_page =
  3325. tx_desc_pool->desc_pages.num_element_per_page;
  3326. for (j = 0; j < num_desc; j++) {
  3327. page_id = j / num_desc_per_page;
  3328. offset = j % num_desc_per_page;
  3329. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3330. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3331. if (force_free) {
  3332. dp_tx_comp_free_buf(soc, tx_desc);
  3333. dp_tx_desc_release(tx_desc, i);
  3334. } else {
  3335. dp_tx_desc_reset_vdev(soc, tx_desc,
  3336. i);
  3337. }
  3338. }
  3339. }
  3340. }
  3341. }
  3342. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3343. /**
  3344. * dp_tx_vdev_detach() - detach vdev from dp tx
  3345. * @vdev: virtual device instance
  3346. *
  3347. * Return: QDF_STATUS_SUCCESS: success
  3348. * QDF_STATUS_E_RESOURCES: Error return
  3349. */
  3350. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3351. {
  3352. struct dp_pdev *pdev = vdev->pdev;
  3353. /* Reset TX desc associated to this Vdev as NULL */
  3354. dp_tx_desc_flush(pdev, vdev, false);
  3355. dp_tx_vdev_multipass_deinit(vdev);
  3356. return QDF_STATUS_SUCCESS;
  3357. }
  3358. /**
  3359. * dp_tx_pdev_attach() - attach pdev to dp tx
  3360. * @pdev: physical device instance
  3361. *
  3362. * Return: QDF_STATUS_SUCCESS: success
  3363. * QDF_STATUS_E_RESOURCES: Error return
  3364. */
  3365. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3366. {
  3367. struct dp_soc *soc = pdev->soc;
  3368. /* Initialize Flow control counters */
  3369. qdf_atomic_init(&pdev->num_tx_exception);
  3370. qdf_atomic_init(&pdev->num_tx_outstanding);
  3371. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3372. /* Initialize descriptors in TCL Ring */
  3373. hal_tx_init_data_ring(soc->hal_soc,
  3374. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3375. }
  3376. return QDF_STATUS_SUCCESS;
  3377. }
  3378. /**
  3379. * dp_tx_pdev_detach() - detach pdev from dp tx
  3380. * @pdev: physical device instance
  3381. *
  3382. * Return: QDF_STATUS_SUCCESS: success
  3383. * QDF_STATUS_E_RESOURCES: Error return
  3384. */
  3385. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3386. {
  3387. /* flush TX outstanding data per pdev */
  3388. dp_tx_desc_flush(pdev, NULL, true);
  3389. dp_tx_me_exit(pdev);
  3390. return QDF_STATUS_SUCCESS;
  3391. }
  3392. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3393. /* Pools will be allocated dynamically */
  3394. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3395. int num_desc)
  3396. {
  3397. uint8_t i;
  3398. for (i = 0; i < num_pool; i++) {
  3399. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3400. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3401. }
  3402. return 0;
  3403. }
  3404. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3405. {
  3406. uint8_t i;
  3407. for (i = 0; i < num_pool; i++)
  3408. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3409. }
  3410. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3411. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3412. int num_desc)
  3413. {
  3414. uint8_t i;
  3415. /* Allocate software Tx descriptor pools */
  3416. for (i = 0; i < num_pool; i++) {
  3417. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3418. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3419. "%s Tx Desc Pool alloc %d failed %pK",
  3420. __func__, i, soc);
  3421. return ENOMEM;
  3422. }
  3423. }
  3424. return 0;
  3425. }
  3426. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3427. {
  3428. uint8_t i;
  3429. for (i = 0; i < num_pool; i++) {
  3430. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3431. if (dp_tx_desc_pool_free(soc, i)) {
  3432. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3433. "%s Tx Desc Pool Free failed", __func__);
  3434. }
  3435. }
  3436. }
  3437. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3438. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3439. /**
  3440. * dp_tso_attach_wifi3() - TSO attach handler
  3441. * @txrx_soc: Opaque Dp handle
  3442. *
  3443. * Reserve TSO descriptor buffers
  3444. *
  3445. * Return: QDF_STATUS_E_FAILURE on failure or
  3446. * QDF_STATUS_SUCCESS on success
  3447. */
  3448. static
  3449. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3450. {
  3451. return dp_tso_soc_attach(txrx_soc);
  3452. }
  3453. /**
  3454. * dp_tso_detach_wifi3() - TSO Detach handler
  3455. * @txrx_soc: Opaque Dp handle
  3456. *
  3457. * Deallocate TSO descriptor buffers
  3458. *
  3459. * Return: QDF_STATUS_E_FAILURE on failure or
  3460. * QDF_STATUS_SUCCESS on success
  3461. */
  3462. static
  3463. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3464. {
  3465. return dp_tso_soc_detach(txrx_soc);
  3466. }
  3467. #else
  3468. static
  3469. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3470. {
  3471. return QDF_STATUS_SUCCESS;
  3472. }
  3473. static
  3474. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3475. {
  3476. return QDF_STATUS_SUCCESS;
  3477. }
  3478. #endif
  3479. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3480. {
  3481. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3482. uint8_t i;
  3483. uint8_t num_pool;
  3484. uint32_t num_desc;
  3485. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3486. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3487. for (i = 0; i < num_pool; i++)
  3488. dp_tx_tso_desc_pool_free(soc, i);
  3489. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3490. __func__, num_pool, num_desc);
  3491. for (i = 0; i < num_pool; i++)
  3492. dp_tx_tso_num_seg_pool_free(soc, i);
  3493. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3494. __func__, num_pool, num_desc);
  3495. return QDF_STATUS_SUCCESS;
  3496. }
  3497. /**
  3498. * dp_tso_attach() - TSO attach handler
  3499. * @txrx_soc: Opaque Dp handle
  3500. *
  3501. * Reserve TSO descriptor buffers
  3502. *
  3503. * Return: QDF_STATUS_E_FAILURE on failure or
  3504. * QDF_STATUS_SUCCESS on success
  3505. */
  3506. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3507. {
  3508. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3509. uint8_t i;
  3510. uint8_t num_pool;
  3511. uint32_t num_desc;
  3512. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3513. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3514. for (i = 0; i < num_pool; i++) {
  3515. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3516. dp_err("TSO Desc Pool alloc %d failed %pK",
  3517. i, soc);
  3518. return QDF_STATUS_E_FAILURE;
  3519. }
  3520. }
  3521. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3522. __func__, num_pool, num_desc);
  3523. for (i = 0; i < num_pool; i++) {
  3524. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3525. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3526. i, soc);
  3527. return QDF_STATUS_E_FAILURE;
  3528. }
  3529. }
  3530. return QDF_STATUS_SUCCESS;
  3531. }
  3532. /**
  3533. * dp_tx_soc_detach() - detach soc from dp tx
  3534. * @soc: core txrx main context
  3535. *
  3536. * This function will detach dp tx into main device context
  3537. * will free dp tx resource and initialize resources
  3538. *
  3539. * Return: QDF_STATUS_SUCCESS: success
  3540. * QDF_STATUS_E_RESOURCES: Error return
  3541. */
  3542. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3543. {
  3544. uint8_t num_pool;
  3545. uint16_t num_desc;
  3546. uint16_t num_ext_desc;
  3547. uint8_t i;
  3548. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3549. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3550. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3551. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3552. dp_tx_flow_control_deinit(soc);
  3553. dp_tx_delete_static_pools(soc, num_pool);
  3554. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3555. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3556. __func__, num_pool, num_desc);
  3557. for (i = 0; i < num_pool; i++) {
  3558. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3559. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3560. "%s Tx Ext Desc Pool Free failed",
  3561. __func__);
  3562. return QDF_STATUS_E_RESOURCES;
  3563. }
  3564. }
  3565. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3566. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3567. __func__, num_pool, num_ext_desc);
  3568. status = dp_tso_detach_wifi3(soc);
  3569. if (status != QDF_STATUS_SUCCESS)
  3570. return status;
  3571. return QDF_STATUS_SUCCESS;
  3572. }
  3573. /**
  3574. * dp_tx_soc_attach() - attach soc to dp tx
  3575. * @soc: core txrx main context
  3576. *
  3577. * This function will attach dp tx into main device context
  3578. * will allocate dp tx resource and initialize resources
  3579. *
  3580. * Return: QDF_STATUS_SUCCESS: success
  3581. * QDF_STATUS_E_RESOURCES: Error return
  3582. */
  3583. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3584. {
  3585. uint8_t i;
  3586. uint8_t num_pool;
  3587. uint32_t num_desc;
  3588. uint32_t num_ext_desc;
  3589. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3590. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3591. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3592. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3593. if (num_pool > MAX_TXDESC_POOLS)
  3594. goto fail;
  3595. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3596. goto fail;
  3597. dp_tx_flow_control_init(soc);
  3598. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3599. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3600. __func__, num_pool, num_desc);
  3601. /* Allocate extension tx descriptor pools */
  3602. for (i = 0; i < num_pool; i++) {
  3603. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3604. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3605. "MSDU Ext Desc Pool alloc %d failed %pK",
  3606. i, soc);
  3607. goto fail;
  3608. }
  3609. }
  3610. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3611. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3612. __func__, num_pool, num_ext_desc);
  3613. status = dp_tso_attach_wifi3((void *)soc);
  3614. if (status != QDF_STATUS_SUCCESS)
  3615. goto fail;
  3616. /* Initialize descriptors in TCL Rings */
  3617. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3618. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3619. hal_tx_init_data_ring(soc->hal_soc,
  3620. soc->tcl_data_ring[i].hal_srng);
  3621. }
  3622. }
  3623. /*
  3624. * todo - Add a runtime config option to enable this.
  3625. */
  3626. /*
  3627. * Due to multiple issues on NPR EMU, enable it selectively
  3628. * only for NPR EMU, should be removed, once NPR platforms
  3629. * are stable.
  3630. */
  3631. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3632. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3633. "%s HAL Tx init Success", __func__);
  3634. return QDF_STATUS_SUCCESS;
  3635. fail:
  3636. /* Detach will take care of freeing only allocated resources */
  3637. dp_tx_soc_detach(soc);
  3638. return QDF_STATUS_E_RESOURCES;
  3639. }