600416fa77
The current pll driver models the entire DP clock hierarchy using the clock framework. This creates unnecessary dependency between the dp driver and the clock driver and also limits the flexibility to dp driver when configuring the DP clocks. This change models these clocks as single nodes and provide full control to the dp driver and also minimizes the dependency on the clock driver. Change-Id: Id5221441ea33b576e7c543396a12cbeb7b44d319 Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
136 rader
3.0 KiB
C
136 rader
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DP_PLL_H
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#define __DP_PLL_H
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of_device.h>
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#include "dp_parser.h"
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#include "sde_dbg.h"
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#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL
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#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL
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#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL
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#define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL
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#define dp_pll_get_base(x) pll->io.x->io.base
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#define dp_pll_read(x, offset) ({ \
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readl_relaxed((dp_pll_get_base(x)) + (offset)); \
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})
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#define dp_pll_write(x, offset, data) ({ \
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DP_DEBUG(#offset", addr=0x%x, val=0x%x\n", \
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(dp_pll_get_base(x)) + (offset), (data)); \
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SDE_EVT32_VERBOSE((dp_pll_get_base(x)) + (offset), (data)); \
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writel_relaxed((data), (dp_pll_get_base(x)) + (offset)); \
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})
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enum dp_pll_revision {
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DP_PLL_UNKNOWN,
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DP_PLL_5NM_V1,
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DP_PLL_5NM_V2,
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};
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static inline const char *dp_pll_get_revision(enum dp_pll_revision rev)
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{
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switch (rev) {
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case DP_PLL_UNKNOWN: return "DP_PLL_UNKNOWN";
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case DP_PLL_5NM_V1: return "DP_PLL_5NM_V1";
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case DP_PLL_5NM_V2: return "DP_PLL_5NM_V2";
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default: return "???";
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}
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}
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struct dp_pll_io {
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struct dp_io_data *dp_phy;
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struct dp_io_data *dp_pll;
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struct dp_io_data *dp_ln_tx0;
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struct dp_io_data *dp_ln_tx1;
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struct dp_io_data *gdsc;
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};
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struct dp_pll_vco_clk {
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struct clk_hw hw;
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void *priv;
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};
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struct dp_pll {
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/* target pll revision information */
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u32 revision;
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/* save vco current rate */
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unsigned long vco_rate;
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/*
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* PLL index if multiple index are available. Eg. in case of
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* DSI we have 2 plls.
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*/
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uint32_t index;
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bool ssc_en;
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bool bonding_en;
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void *priv;
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struct platform_device *pdev;
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struct dp_parser *parser;
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struct dp_power *power;
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struct dp_aux *aux;
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struct dp_pll_io io;
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struct clk_onecell_data *clk_data;
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int (*pll_cfg)(struct dp_pll *pll, unsigned long rate);
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int (*pll_prepare)(struct dp_pll *pll);
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int (*pll_unprepare)(struct dp_pll *pll);
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};
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struct dp_pll_db {
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struct dp_pll *pll;
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/* lane and orientation settings */
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u8 lane_cnt;
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u8 orientation;
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/* COM PHY settings */
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u32 hsclk_sel;
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u32 dec_start_mode0;
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u32 div_frac_start1_mode0;
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u32 div_frac_start2_mode0;
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u32 div_frac_start3_mode0;
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u32 integloop_gain0_mode0;
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u32 integloop_gain1_mode0;
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u32 lock_cmp1_mode0;
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u32 lock_cmp2_mode0;
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u32 lock_cmp_en;
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u32 ssc_step_size1_mode0;
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u32 ssc_step_size2_mode0;
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/* PHY vco divider */
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u32 phy_vco_div;
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};
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static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw)
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{
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return container_of(hw, struct dp_pll_vco_clk, hw);
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}
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static inline bool is_gdsc_disabled(struct dp_pll *pll)
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{
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return (dp_pll_read(gdsc, 0x0) & BIT(31)) ? false : true;
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}
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int dp_pll_clock_register_5nm(struct dp_pll *pll);
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void dp_pll_clock_unregister_5nm(struct dp_pll *pll);
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struct dp_pll_in {
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struct platform_device *pdev;
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struct dp_aux *aux;
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struct dp_parser *parser;
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};
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struct dp_pll *dp_pll_get(struct dp_pll_in *in);
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void dp_pll_put(struct dp_pll *pll);
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#endif /* __DP_PLL_H */
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