dp_tx.c 175 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. #define DP_RETRY_COUNT 7
  63. #ifdef WLAN_PEER_JITTER
  64. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  65. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  66. #endif
  67. #ifdef QCA_DP_TX_FW_METADATA_V2
  68. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  69. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  80. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  82. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  84. #else
  85. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  86. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  97. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  98. HTT_TCL_METADATA_TYPE_PEER_BASED
  99. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  100. HTT_TCL_METADATA_TYPE_VDEV_BASED
  101. #endif
  102. #define DP_GET_HW_LINK_ID_FRM_PPDU_ID(PPDU_ID, LINK_ID_OFFSET, LINK_ID_BITS) \
  103. (((PPDU_ID) >> (LINK_ID_OFFSET)) & ((1 << (LINK_ID_BITS)) - 1))
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc: core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc: core txrx main context
  249. * @seg_desc: tso segment descriptor
  250. * @num_seg_desc: tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc: soc device handle
  283. * @tx_desc: Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. void
  327. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  328. {
  329. struct dp_pdev *pdev = tx_desc->pdev;
  330. struct dp_soc *soc;
  331. uint8_t comp_status = 0;
  332. qdf_assert(pdev);
  333. soc = pdev->soc;
  334. dp_tx_outstanding_dec(pdev);
  335. if (tx_desc->msdu_ext_desc) {
  336. if (tx_desc->frm_type == dp_tx_frm_tso)
  337. dp_tx_tso_desc_release(soc, tx_desc);
  338. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  339. dp_tx_me_free_buf(tx_desc->pdev,
  340. tx_desc->msdu_ext_desc->me_buffer);
  341. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  342. }
  343. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  344. qdf_atomic_dec(&soc->num_tx_exception);
  345. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  346. tx_desc->buffer_src)
  347. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  348. soc->hal_soc);
  349. else
  350. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  351. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  352. tx_desc->id, comp_status,
  353. qdf_atomic_read(&pdev->num_tx_outstanding));
  354. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  355. return;
  356. }
  357. /**
  358. * dp_tx_prepare_htt_metadata() - Prepare HTT metadata for special frames
  359. * @vdev: DP vdev Handle
  360. * @nbuf: skb
  361. * @msdu_info: msdu_info required to create HTT metadata
  362. *
  363. * Prepares and fills HTT metadata in the frame pre-header for special frames
  364. * that should be transmitted using varying transmit parameters.
  365. * There are 2 VDEV modes that currently needs this special metadata -
  366. * 1) Mesh Mode
  367. * 2) DSRC Mode
  368. *
  369. * Return: HTT metadata size
  370. *
  371. */
  372. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  373. struct dp_tx_msdu_info_s *msdu_info)
  374. {
  375. uint32_t *meta_data = msdu_info->meta_data;
  376. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  377. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  378. uint8_t htt_desc_size;
  379. /* Size rounded of multiple of 8 bytes */
  380. uint8_t htt_desc_size_aligned;
  381. uint8_t *hdr = NULL;
  382. /*
  383. * Metadata - HTT MSDU Extension header
  384. */
  385. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  386. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  387. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  388. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  389. meta_data[0]) ||
  390. msdu_info->exception_fw) {
  391. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  392. htt_desc_size_aligned)) {
  393. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  394. htt_desc_size_aligned);
  395. if (!nbuf) {
  396. /*
  397. * qdf_nbuf_realloc_headroom won't do skb_clone
  398. * as skb_realloc_headroom does. so, no free is
  399. * needed here.
  400. */
  401. DP_STATS_INC(vdev,
  402. tx_i.dropped.headroom_insufficient,
  403. 1);
  404. qdf_print(" %s[%d] skb_realloc_headroom failed",
  405. __func__, __LINE__);
  406. return 0;
  407. }
  408. }
  409. /* Fill and add HTT metaheader */
  410. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  411. if (!hdr) {
  412. dp_tx_err("Error in filling HTT metadata");
  413. return 0;
  414. }
  415. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  416. } else if (vdev->opmode == wlan_op_mode_ocb) {
  417. /* Todo - Add support for DSRC */
  418. }
  419. return htt_desc_size_aligned;
  420. }
  421. /**
  422. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  423. * @tso_seg: TSO segment to process
  424. * @ext_desc: Pointer to MSDU extension descriptor
  425. *
  426. * Return: void
  427. */
  428. #if defined(FEATURE_TSO)
  429. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  430. void *ext_desc)
  431. {
  432. uint8_t num_frag;
  433. uint32_t tso_flags;
  434. /*
  435. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  436. * tcp_flag_mask
  437. *
  438. * Checksum enable flags are set in TCL descriptor and not in Extension
  439. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  440. */
  441. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  442. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  443. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  444. tso_seg->tso_flags.ip_len);
  445. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  446. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  447. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  448. uint32_t lo = 0;
  449. uint32_t hi = 0;
  450. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  451. (tso_seg->tso_frags[num_frag].length));
  452. qdf_dmaaddr_to_32s(
  453. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  454. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  455. tso_seg->tso_frags[num_frag].length);
  456. }
  457. return;
  458. }
  459. #else
  460. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  461. void *ext_desc)
  462. {
  463. return;
  464. }
  465. #endif
  466. #if defined(FEATURE_TSO)
  467. /**
  468. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  469. * allocated and free them
  470. * @soc: soc handle
  471. * @free_seg: list of tso segments
  472. * @msdu_info: msdu descriptor
  473. *
  474. * Return: void
  475. */
  476. static void dp_tx_free_tso_seg_list(
  477. struct dp_soc *soc,
  478. struct qdf_tso_seg_elem_t *free_seg,
  479. struct dp_tx_msdu_info_s *msdu_info)
  480. {
  481. struct qdf_tso_seg_elem_t *next_seg;
  482. while (free_seg) {
  483. next_seg = free_seg->next;
  484. dp_tx_tso_desc_free(soc,
  485. msdu_info->tx_queue.desc_pool_id,
  486. free_seg);
  487. free_seg = next_seg;
  488. }
  489. }
  490. /**
  491. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  492. * allocated and free them
  493. * @soc: soc handle
  494. * @free_num_seg: list of tso number segments
  495. * @msdu_info: msdu descriptor
  496. *
  497. * Return: void
  498. */
  499. static void dp_tx_free_tso_num_seg_list(
  500. struct dp_soc *soc,
  501. struct qdf_tso_num_seg_elem_t *free_num_seg,
  502. struct dp_tx_msdu_info_s *msdu_info)
  503. {
  504. struct qdf_tso_num_seg_elem_t *next_num_seg;
  505. while (free_num_seg) {
  506. next_num_seg = free_num_seg->next;
  507. dp_tso_num_seg_free(soc,
  508. msdu_info->tx_queue.desc_pool_id,
  509. free_num_seg);
  510. free_num_seg = next_num_seg;
  511. }
  512. }
  513. /**
  514. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  515. * do dma unmap for each segment
  516. * @soc: soc handle
  517. * @free_seg: list of tso segments
  518. * @num_seg_desc: tso number segment descriptor
  519. *
  520. * Return: void
  521. */
  522. static void dp_tx_unmap_tso_seg_list(
  523. struct dp_soc *soc,
  524. struct qdf_tso_seg_elem_t *free_seg,
  525. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  526. {
  527. struct qdf_tso_seg_elem_t *next_seg;
  528. if (qdf_unlikely(!num_seg_desc)) {
  529. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  530. return;
  531. }
  532. while (free_seg) {
  533. next_seg = free_seg->next;
  534. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  535. free_seg = next_seg;
  536. }
  537. }
  538. #ifdef FEATURE_TSO_STATS
  539. /**
  540. * dp_tso_get_stats_idx() - Retrieve the tso packet id
  541. * @pdev: pdev handle
  542. *
  543. * Return: id
  544. */
  545. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  546. {
  547. uint32_t stats_idx;
  548. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  549. % CDP_MAX_TSO_PACKETS);
  550. return stats_idx;
  551. }
  552. #else
  553. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  554. {
  555. return 0;
  556. }
  557. #endif /* FEATURE_TSO_STATS */
  558. /**
  559. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  560. * free the tso segments descriptor and
  561. * tso num segments descriptor
  562. * @soc: soc handle
  563. * @msdu_info: msdu descriptor
  564. * @tso_seg_unmap: flag to show if dma unmap is necessary
  565. *
  566. * Return: void
  567. */
  568. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  569. struct dp_tx_msdu_info_s *msdu_info,
  570. bool tso_seg_unmap)
  571. {
  572. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  573. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  574. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  575. tso_info->tso_num_seg_list;
  576. /* do dma unmap for each segment */
  577. if (tso_seg_unmap)
  578. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  579. /* free all tso number segment descriptor though looks only have 1 */
  580. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  581. /* free all tso segment descriptor */
  582. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  583. }
  584. /**
  585. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  586. * @vdev: virtual device handle
  587. * @msdu: network buffer
  588. * @msdu_info: meta data associated with the msdu
  589. *
  590. * Return: QDF_STATUS_SUCCESS success
  591. */
  592. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  593. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  594. {
  595. struct qdf_tso_seg_elem_t *tso_seg;
  596. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  597. struct dp_soc *soc = vdev->pdev->soc;
  598. struct dp_pdev *pdev = vdev->pdev;
  599. struct qdf_tso_info_t *tso_info;
  600. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  601. tso_info = &msdu_info->u.tso_info;
  602. tso_info->curr_seg = NULL;
  603. tso_info->tso_seg_list = NULL;
  604. tso_info->num_segs = num_seg;
  605. msdu_info->frm_type = dp_tx_frm_tso;
  606. tso_info->tso_num_seg_list = NULL;
  607. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  608. while (num_seg) {
  609. tso_seg = dp_tx_tso_desc_alloc(
  610. soc, msdu_info->tx_queue.desc_pool_id);
  611. if (tso_seg) {
  612. tso_seg->next = tso_info->tso_seg_list;
  613. tso_info->tso_seg_list = tso_seg;
  614. num_seg--;
  615. } else {
  616. dp_err_rl("Failed to alloc tso seg desc");
  617. DP_STATS_INC_PKT(vdev->pdev,
  618. tso_stats.tso_no_mem_dropped, 1,
  619. qdf_nbuf_len(msdu));
  620. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  621. return QDF_STATUS_E_NOMEM;
  622. }
  623. }
  624. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  625. tso_num_seg = dp_tso_num_seg_alloc(soc,
  626. msdu_info->tx_queue.desc_pool_id);
  627. if (tso_num_seg) {
  628. tso_num_seg->next = tso_info->tso_num_seg_list;
  629. tso_info->tso_num_seg_list = tso_num_seg;
  630. } else {
  631. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  632. __func__);
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. msdu_info->num_seg =
  637. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  638. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  639. msdu_info->num_seg);
  640. if (!(msdu_info->num_seg)) {
  641. /*
  642. * Free allocated TSO seg desc and number seg desc,
  643. * do unmap for segments if dma map has done.
  644. */
  645. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  647. return QDF_STATUS_E_INVAL;
  648. }
  649. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  650. msdu, 0, DP_TX_DESC_MAP);
  651. tso_info->curr_seg = tso_info->tso_seg_list;
  652. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  653. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  654. msdu, msdu_info->num_seg);
  655. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  656. tso_info->msdu_stats_idx);
  657. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  658. return QDF_STATUS_SUCCESS;
  659. }
  660. #else
  661. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  662. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  663. {
  664. return QDF_STATUS_E_NOMEM;
  665. }
  666. #endif
  667. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  668. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  669. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  670. /**
  671. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  672. * @vdev: DP Vdev handle
  673. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  674. * @desc_pool_id: Descriptor Pool ID
  675. *
  676. * Return:
  677. */
  678. static
  679. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  680. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  681. {
  682. uint8_t i;
  683. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  684. struct dp_tx_seg_info_s *seg_info;
  685. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  686. struct dp_soc *soc = vdev->pdev->soc;
  687. /* Allocate an extension descriptor */
  688. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  689. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  690. if (!msdu_ext_desc) {
  691. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  692. return NULL;
  693. }
  694. if (msdu_info->exception_fw &&
  695. qdf_unlikely(vdev->mesh_vdev)) {
  696. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  697. &msdu_info->meta_data[0],
  698. sizeof(struct htt_tx_msdu_desc_ext2_t));
  699. qdf_atomic_inc(&soc->num_tx_exception);
  700. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  701. }
  702. switch (msdu_info->frm_type) {
  703. case dp_tx_frm_sg:
  704. case dp_tx_frm_me:
  705. case dp_tx_frm_raw:
  706. seg_info = msdu_info->u.sg_info.curr_seg;
  707. /* Update the buffer pointers in MSDU Extension Descriptor */
  708. for (i = 0; i < seg_info->frag_cnt; i++) {
  709. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  710. seg_info->frags[i].paddr_lo,
  711. seg_info->frags[i].paddr_hi,
  712. seg_info->frags[i].len);
  713. }
  714. break;
  715. case dp_tx_frm_tso:
  716. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  717. &cached_ext_desc[0]);
  718. break;
  719. default:
  720. break;
  721. }
  722. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  723. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  724. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  725. msdu_ext_desc->vaddr);
  726. return msdu_ext_desc;
  727. }
  728. /**
  729. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  730. * @soc: datapath SOC
  731. * @skb: skb to be traced
  732. * @msdu_id: msdu_id of the packet
  733. * @vdev_id: vdev_id of the packet
  734. *
  735. * Return: None
  736. */
  737. #ifdef DP_DISABLE_TX_PKT_TRACE
  738. static void dp_tx_trace_pkt(struct dp_soc *soc,
  739. qdf_nbuf_t skb, uint16_t msdu_id,
  740. uint8_t vdev_id)
  741. {
  742. }
  743. #else
  744. static void dp_tx_trace_pkt(struct dp_soc *soc,
  745. qdf_nbuf_t skb, uint16_t msdu_id,
  746. uint8_t vdev_id)
  747. {
  748. if (dp_is_tput_high(soc))
  749. return;
  750. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  751. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  752. DPTRACE(qdf_dp_trace_ptr(skb,
  753. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  754. QDF_TRACE_DEFAULT_PDEV_ID,
  755. qdf_nbuf_data_addr(skb),
  756. sizeof(qdf_nbuf_data(skb)),
  757. msdu_id, vdev_id, 0));
  758. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  759. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  760. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  761. msdu_id, QDF_TX));
  762. }
  763. #endif
  764. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  765. /**
  766. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  767. * exception by the upper layer (OS_IF)
  768. * @soc: DP soc handle
  769. * @nbuf: packet to be transmitted
  770. *
  771. * Return: 1 if the packet is marked as exception,
  772. * 0, if the packet is not marked as exception.
  773. */
  774. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  775. qdf_nbuf_t nbuf)
  776. {
  777. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  778. }
  779. #else
  780. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  781. qdf_nbuf_t nbuf)
  782. {
  783. return 0;
  784. }
  785. #endif
  786. #ifdef DP_TRAFFIC_END_INDICATION
  787. /**
  788. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  789. * as indication to fw to inform that
  790. * data stream has ended
  791. * @vdev: DP vdev handle
  792. * @nbuf: original buffer from network stack
  793. *
  794. * Return: NULL on failure,
  795. * nbuf on success
  796. */
  797. static inline qdf_nbuf_t
  798. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  799. qdf_nbuf_t nbuf)
  800. {
  801. /* Packet length should be enough to copy upto L3 header */
  802. uint8_t end_nbuf_len = 64;
  803. uint8_t htt_desc_size_aligned;
  804. uint8_t htt_desc_size;
  805. qdf_nbuf_t end_nbuf;
  806. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  807. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  808. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  809. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  810. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  811. if (!end_nbuf) {
  812. end_nbuf = qdf_nbuf_alloc(NULL,
  813. (htt_desc_size_aligned +
  814. end_nbuf_len),
  815. htt_desc_size_aligned,
  816. 8, false);
  817. if (!end_nbuf) {
  818. dp_err("Packet allocation failed");
  819. goto out;
  820. }
  821. } else {
  822. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  823. }
  824. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  825. end_nbuf_len);
  826. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  827. return end_nbuf;
  828. }
  829. out:
  830. return NULL;
  831. }
  832. /**
  833. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  834. * via exception path.
  835. * @vdev: DP vdev handle
  836. * @end_nbuf: skb to send as indication
  837. * @msdu_info: msdu_info of original nbuf
  838. * @peer_id: peer id
  839. *
  840. * Return: None
  841. */
  842. static inline void
  843. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  844. qdf_nbuf_t end_nbuf,
  845. struct dp_tx_msdu_info_s *msdu_info,
  846. uint16_t peer_id)
  847. {
  848. struct dp_tx_msdu_info_s e_msdu_info = {0};
  849. qdf_nbuf_t nbuf;
  850. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  851. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  852. e_msdu_info.tx_queue = msdu_info->tx_queue;
  853. e_msdu_info.tid = msdu_info->tid;
  854. e_msdu_info.exception_fw = 1;
  855. desc_ext->host_tx_desc_pool = 1;
  856. desc_ext->traffic_end_indication = 1;
  857. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  858. peer_id, NULL);
  859. if (nbuf) {
  860. dp_err("Traffic end indication packet tx failed");
  861. qdf_nbuf_free(nbuf);
  862. }
  863. }
  864. /**
  865. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  866. * mark it traffic end indication
  867. * packet.
  868. * @tx_desc: Tx descriptor pointer
  869. * @msdu_info: msdu_info structure pointer
  870. *
  871. * Return: None
  872. */
  873. static inline void
  874. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  875. struct dp_tx_msdu_info_s *msdu_info)
  876. {
  877. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  878. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  879. if (qdf_unlikely(desc_ext->traffic_end_indication))
  880. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  881. }
  882. /**
  883. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  884. * freeing which are associated
  885. * with traffic end indication
  886. * flagged descriptor.
  887. * @soc: dp soc handle
  888. * @desc: Tx descriptor pointer
  889. * @nbuf: buffer pointer
  890. *
  891. * Return: True if packet gets enqueued else false
  892. */
  893. static bool
  894. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  895. struct dp_tx_desc_s *desc,
  896. qdf_nbuf_t nbuf)
  897. {
  898. struct dp_vdev *vdev = NULL;
  899. if (qdf_unlikely((desc->flags &
  900. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  901. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  902. DP_MOD_ID_TX_COMP);
  903. if (vdev) {
  904. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  905. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  906. return true;
  907. }
  908. }
  909. return false;
  910. }
  911. /**
  912. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  913. * enable/disable status
  914. * @vdev: dp vdev handle
  915. *
  916. * Return: True if feature is enable else false
  917. */
  918. static inline bool
  919. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  920. {
  921. return qdf_unlikely(vdev->traffic_end_ind_en);
  922. }
  923. static inline qdf_nbuf_t
  924. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  925. struct dp_tx_msdu_info_s *msdu_info,
  926. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  927. {
  928. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  929. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  930. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  931. if (qdf_unlikely(end_nbuf))
  932. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  933. msdu_info, peer_id);
  934. return nbuf;
  935. }
  936. #else
  937. static inline qdf_nbuf_t
  938. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  939. qdf_nbuf_t nbuf)
  940. {
  941. return NULL;
  942. }
  943. static inline void
  944. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  945. qdf_nbuf_t end_nbuf,
  946. struct dp_tx_msdu_info_s *msdu_info,
  947. uint16_t peer_id)
  948. {}
  949. static inline void
  950. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  951. struct dp_tx_msdu_info_s *msdu_info)
  952. {}
  953. static inline bool
  954. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  955. struct dp_tx_desc_s *desc,
  956. qdf_nbuf_t nbuf)
  957. {
  958. return false;
  959. }
  960. static inline bool
  961. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  962. {
  963. return false;
  964. }
  965. static inline qdf_nbuf_t
  966. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  967. struct dp_tx_msdu_info_s *msdu_info,
  968. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  969. {
  970. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  971. }
  972. #endif
  973. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  974. static bool
  975. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  976. struct cdp_tx_exception_metadata *tx_exc_metadata)
  977. {
  978. if (soc->features.wds_ext_ast_override_enable &&
  979. tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  980. return true;
  981. return false;
  982. }
  983. #else
  984. static bool
  985. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  986. struct cdp_tx_exception_metadata *tx_exc_metadata)
  987. {
  988. return false;
  989. }
  990. #endif
  991. /**
  992. * dp_tx_prepare_desc_single() - Allocate and prepare Tx descriptor
  993. * @vdev: DP vdev handle
  994. * @nbuf: skb
  995. * @desc_pool_id: Descriptor pool ID
  996. * @msdu_info: Metadata to the fw
  997. * @tx_exc_metadata: Handle that holds exception path metadata
  998. *
  999. * Allocate and prepare Tx descriptor with msdu information.
  1000. *
  1001. * Return: Pointer to Tx Descriptor on success,
  1002. * NULL on failure
  1003. */
  1004. static
  1005. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1006. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1007. struct dp_tx_msdu_info_s *msdu_info,
  1008. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1009. {
  1010. uint8_t align_pad;
  1011. uint8_t is_exception = 0;
  1012. uint8_t htt_hdr_size;
  1013. struct dp_tx_desc_s *tx_desc;
  1014. struct dp_pdev *pdev = vdev->pdev;
  1015. struct dp_soc *soc = pdev->soc;
  1016. if (dp_tx_limit_check(vdev, nbuf))
  1017. return NULL;
  1018. /* Allocate software Tx descriptor */
  1019. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1020. if (qdf_unlikely(!tx_desc)) {
  1021. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1022. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1023. return NULL;
  1024. }
  1025. dp_tx_outstanding_inc(pdev);
  1026. /* Initialize the SW tx descriptor */
  1027. tx_desc->nbuf = nbuf;
  1028. tx_desc->frm_type = dp_tx_frm_std;
  1029. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1030. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1031. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1032. tx_desc->vdev_id = vdev->vdev_id;
  1033. tx_desc->pdev = pdev;
  1034. tx_desc->msdu_ext_desc = NULL;
  1035. tx_desc->pkt_offset = 0;
  1036. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1037. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1038. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1039. if (qdf_unlikely(vdev->multipass_en)) {
  1040. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1041. goto failure;
  1042. }
  1043. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1044. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1045. is_exception = 1;
  1046. /* for BE chipsets if wds extension was enbled will not mark FW
  1047. * in desc will mark ast index based search for ast index.
  1048. */
  1049. if (dp_tx_is_wds_ast_override_en(soc, tx_exc_metadata))
  1050. return tx_desc;
  1051. /*
  1052. * For special modes (vdev_type == ocb or mesh), data frames should be
  1053. * transmitted using varying transmit parameters (tx spec) which include
  1054. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1055. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1056. * These frames are sent as exception packets to firmware.
  1057. *
  1058. * HW requirement is that metadata should always point to a
  1059. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1060. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1061. * to get 8-byte aligned start address along with align_pad added
  1062. *
  1063. * |-----------------------------|
  1064. * | |
  1065. * |-----------------------------| <-----Buffer Pointer Address given
  1066. * | | ^ in HW descriptor (aligned)
  1067. * | HTT Metadata | |
  1068. * | | |
  1069. * | | | Packet Offset given in descriptor
  1070. * | | |
  1071. * |-----------------------------| |
  1072. * | Alignment Pad | v
  1073. * |-----------------------------| <----- Actual buffer start address
  1074. * | SKB Data | (Unaligned)
  1075. * | |
  1076. * | |
  1077. * | |
  1078. * | |
  1079. * | |
  1080. * |-----------------------------|
  1081. */
  1082. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1083. (vdev->opmode == wlan_op_mode_ocb) ||
  1084. (tx_exc_metadata &&
  1085. tx_exc_metadata->is_tx_sniffer)) {
  1086. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1087. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1088. DP_STATS_INC(vdev,
  1089. tx_i.dropped.headroom_insufficient, 1);
  1090. goto failure;
  1091. }
  1092. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1093. dp_tx_err("qdf_nbuf_push_head failed");
  1094. goto failure;
  1095. }
  1096. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1097. msdu_info);
  1098. if (htt_hdr_size == 0)
  1099. goto failure;
  1100. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1101. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1102. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1103. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1104. msdu_info);
  1105. is_exception = 1;
  1106. tx_desc->length -= tx_desc->pkt_offset;
  1107. }
  1108. #if !TQM_BYPASS_WAR
  1109. if (is_exception || tx_exc_metadata)
  1110. #endif
  1111. {
  1112. /* Temporary WAR due to TQM VP issues */
  1113. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1114. qdf_atomic_inc(&soc->num_tx_exception);
  1115. }
  1116. return tx_desc;
  1117. failure:
  1118. dp_tx_desc_release(tx_desc, desc_pool_id);
  1119. return NULL;
  1120. }
  1121. /**
  1122. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment
  1123. * frame
  1124. * @vdev: DP vdev handle
  1125. * @nbuf: skb
  1126. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1127. * @desc_pool_id : Descriptor Pool ID
  1128. *
  1129. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1130. * information. For frames with fragments, allocate and prepare
  1131. * an MSDU extension descriptor
  1132. *
  1133. * Return: Pointer to Tx Descriptor on success,
  1134. * NULL on failure
  1135. */
  1136. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1137. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1138. uint8_t desc_pool_id)
  1139. {
  1140. struct dp_tx_desc_s *tx_desc;
  1141. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1142. struct dp_pdev *pdev = vdev->pdev;
  1143. struct dp_soc *soc = pdev->soc;
  1144. if (dp_tx_limit_check(vdev, nbuf))
  1145. return NULL;
  1146. /* Allocate software Tx descriptor */
  1147. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1148. if (!tx_desc) {
  1149. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1150. return NULL;
  1151. }
  1152. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1153. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1154. dp_tx_outstanding_inc(pdev);
  1155. /* Initialize the SW tx descriptor */
  1156. tx_desc->nbuf = nbuf;
  1157. tx_desc->frm_type = msdu_info->frm_type;
  1158. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1159. tx_desc->vdev_id = vdev->vdev_id;
  1160. tx_desc->pdev = pdev;
  1161. tx_desc->pkt_offset = 0;
  1162. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1163. /* Handle scattered frames - TSO/SG/ME */
  1164. /* Allocate and prepare an extension descriptor for scattered frames */
  1165. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1166. if (!msdu_ext_desc) {
  1167. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1168. goto failure;
  1169. }
  1170. #if TQM_BYPASS_WAR
  1171. /* Temporary WAR due to TQM VP issues */
  1172. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1173. qdf_atomic_inc(&soc->num_tx_exception);
  1174. #endif
  1175. if (qdf_unlikely(msdu_info->exception_fw))
  1176. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1177. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1178. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1179. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1180. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1181. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1182. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1183. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1184. else
  1185. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1186. return tx_desc;
  1187. failure:
  1188. dp_tx_desc_release(tx_desc, desc_pool_id);
  1189. return NULL;
  1190. }
  1191. /**
  1192. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1193. * @vdev: DP vdev handle
  1194. * @nbuf: buffer pointer
  1195. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1196. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1197. * descriptor
  1198. *
  1199. * Return:
  1200. */
  1201. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1202. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1203. {
  1204. qdf_nbuf_t curr_nbuf = NULL;
  1205. uint16_t total_len = 0;
  1206. qdf_dma_addr_t paddr;
  1207. int32_t i;
  1208. int32_t mapped_buf_num = 0;
  1209. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1210. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1211. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1212. /* Continue only if frames are of DATA type */
  1213. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1214. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1215. dp_tx_debug("Pkt. recd is of not data type");
  1216. goto error;
  1217. }
  1218. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1219. if (vdev->raw_mode_war &&
  1220. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1221. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1222. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1223. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1224. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1225. /*
  1226. * Number of nbuf's must not exceed the size of the frags
  1227. * array in seg_info.
  1228. */
  1229. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1230. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1231. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1232. goto error;
  1233. }
  1234. if (QDF_STATUS_SUCCESS !=
  1235. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1236. curr_nbuf,
  1237. QDF_DMA_TO_DEVICE,
  1238. curr_nbuf->len)) {
  1239. dp_tx_err("%s dma map error ", __func__);
  1240. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1241. goto error;
  1242. }
  1243. /* Update the count of mapped nbuf's */
  1244. mapped_buf_num++;
  1245. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1246. seg_info->frags[i].paddr_lo = paddr;
  1247. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1248. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1249. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1250. total_len += qdf_nbuf_len(curr_nbuf);
  1251. }
  1252. seg_info->frag_cnt = i;
  1253. seg_info->total_len = total_len;
  1254. seg_info->next = NULL;
  1255. sg_info->curr_seg = seg_info;
  1256. msdu_info->frm_type = dp_tx_frm_raw;
  1257. msdu_info->num_seg = 1;
  1258. return nbuf;
  1259. error:
  1260. i = 0;
  1261. while (nbuf) {
  1262. curr_nbuf = nbuf;
  1263. if (i < mapped_buf_num) {
  1264. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1265. QDF_DMA_TO_DEVICE,
  1266. curr_nbuf->len);
  1267. i++;
  1268. }
  1269. nbuf = qdf_nbuf_next(nbuf);
  1270. qdf_nbuf_free(curr_nbuf);
  1271. }
  1272. return NULL;
  1273. }
  1274. /**
  1275. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1276. * @soc: DP soc handle
  1277. * @nbuf: Buffer pointer
  1278. *
  1279. * unmap the chain of nbufs that belong to this RAW frame.
  1280. *
  1281. * Return: None
  1282. */
  1283. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1284. qdf_nbuf_t nbuf)
  1285. {
  1286. qdf_nbuf_t cur_nbuf = nbuf;
  1287. do {
  1288. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1289. QDF_DMA_TO_DEVICE,
  1290. cur_nbuf->len);
  1291. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1292. } while (cur_nbuf);
  1293. }
  1294. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1295. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1296. qdf_nbuf_t nbuf)
  1297. {
  1298. qdf_nbuf_t nbuf_local;
  1299. struct dp_vdev *vdev_local = vdev_hdl;
  1300. do {
  1301. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1302. break;
  1303. nbuf_local = nbuf;
  1304. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1305. htt_cmn_pkt_type_raw))
  1306. break;
  1307. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1308. break;
  1309. else if (qdf_nbuf_is_tso((nbuf_local)))
  1310. break;
  1311. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1312. (nbuf_local),
  1313. NULL, 1, 0);
  1314. } while (0);
  1315. }
  1316. #endif
  1317. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1318. void dp_tx_update_stats(struct dp_soc *soc,
  1319. struct dp_tx_desc_s *tx_desc,
  1320. uint8_t ring_id)
  1321. {
  1322. uint32_t stats_len = dp_tx_get_pkt_len(tx_desc);
  1323. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1324. }
  1325. int
  1326. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1327. struct dp_tx_desc_s *tx_desc,
  1328. uint8_t tid,
  1329. struct dp_tx_msdu_info_s *msdu_info,
  1330. uint8_t ring_id)
  1331. {
  1332. struct dp_swlm *swlm = &soc->swlm;
  1333. union swlm_data swlm_query_data;
  1334. struct dp_swlm_tcl_data tcl_data;
  1335. QDF_STATUS status;
  1336. int ret;
  1337. if (!swlm->is_enabled)
  1338. return msdu_info->skip_hp_update;
  1339. tcl_data.nbuf = tx_desc->nbuf;
  1340. tcl_data.tid = tid;
  1341. tcl_data.ring_id = ring_id;
  1342. tcl_data.pkt_len = dp_tx_get_pkt_len(tx_desc);
  1343. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1344. swlm_query_data.tcl_data = &tcl_data;
  1345. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1346. if (QDF_IS_STATUS_ERROR(status)) {
  1347. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1348. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1349. return 0;
  1350. }
  1351. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1352. if (ret) {
  1353. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1354. } else {
  1355. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1356. }
  1357. return ret;
  1358. }
  1359. void
  1360. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1361. int coalesce)
  1362. {
  1363. if (coalesce)
  1364. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1365. else
  1366. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1367. }
  1368. static inline void
  1369. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1370. {
  1371. if (((i + 1) < msdu_info->num_seg))
  1372. msdu_info->skip_hp_update = 1;
  1373. else
  1374. msdu_info->skip_hp_update = 0;
  1375. }
  1376. static inline void
  1377. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1378. {
  1379. hal_ring_handle_t hal_ring_hdl =
  1380. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1381. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1382. dp_err("Fillmore: SRNG access start failed");
  1383. return;
  1384. }
  1385. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1386. }
  1387. static inline void
  1388. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1389. QDF_STATUS status,
  1390. struct dp_tx_msdu_info_s *msdu_info)
  1391. {
  1392. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1393. dp_flush_tcp_hp(soc,
  1394. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1395. }
  1396. }
  1397. #else
  1398. static inline void
  1399. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1400. {
  1401. }
  1402. static inline void
  1403. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1404. QDF_STATUS status,
  1405. struct dp_tx_msdu_info_s *msdu_info)
  1406. {
  1407. }
  1408. #endif
  1409. #ifdef FEATURE_RUNTIME_PM
  1410. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1411. {
  1412. int ret;
  1413. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1414. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1415. return ret;
  1416. }
  1417. void
  1418. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1419. hal_ring_handle_t hal_ring_hdl,
  1420. int coalesce)
  1421. {
  1422. int ret;
  1423. /*
  1424. * Avoid runtime get and put APIs under high throughput scenarios.
  1425. */
  1426. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1427. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1428. return;
  1429. }
  1430. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1431. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1432. if (hif_system_pm_state_check(soc->hif_handle)) {
  1433. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1434. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1435. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1436. } else {
  1437. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1438. }
  1439. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1440. } else {
  1441. dp_runtime_get(soc);
  1442. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1443. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1444. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1445. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1446. dp_runtime_put(soc);
  1447. }
  1448. }
  1449. #else
  1450. #ifdef DP_POWER_SAVE
  1451. void
  1452. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1453. hal_ring_handle_t hal_ring_hdl,
  1454. int coalesce)
  1455. {
  1456. if (hif_system_pm_state_check(soc->hif_handle)) {
  1457. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1458. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1459. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1460. } else {
  1461. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1462. }
  1463. }
  1464. #endif
  1465. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1466. {
  1467. return 0;
  1468. }
  1469. #endif
  1470. /**
  1471. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1472. * @vdev: DP vdev handle
  1473. * @nbuf: skb
  1474. * @msdu_info: msdu descriptor
  1475. *
  1476. * Extract the DSCP or PCP information from frame and map into TID value.
  1477. *
  1478. * Return: void
  1479. */
  1480. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1481. struct dp_tx_msdu_info_s *msdu_info)
  1482. {
  1483. uint8_t tos = 0, dscp_tid_override = 0;
  1484. uint8_t *hdr_ptr, *L3datap;
  1485. uint8_t is_mcast = 0;
  1486. qdf_ether_header_t *eh = NULL;
  1487. qdf_ethervlan_header_t *evh = NULL;
  1488. uint16_t ether_type;
  1489. qdf_llc_t *llcHdr;
  1490. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1491. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1492. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1493. eh = (qdf_ether_header_t *)nbuf->data;
  1494. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1495. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1496. } else {
  1497. qdf_dot3_qosframe_t *qos_wh =
  1498. (qdf_dot3_qosframe_t *) nbuf->data;
  1499. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1500. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1501. return;
  1502. }
  1503. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1504. ether_type = eh->ether_type;
  1505. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1506. /*
  1507. * Check if packet is dot3 or eth2 type.
  1508. */
  1509. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1510. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1511. sizeof(*llcHdr));
  1512. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1513. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1514. sizeof(*llcHdr);
  1515. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1516. + sizeof(*llcHdr) +
  1517. sizeof(qdf_net_vlanhdr_t));
  1518. } else {
  1519. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1520. sizeof(*llcHdr);
  1521. }
  1522. } else {
  1523. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1524. evh = (qdf_ethervlan_header_t *) eh;
  1525. ether_type = evh->ether_type;
  1526. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1527. }
  1528. }
  1529. /*
  1530. * Find priority from IP TOS DSCP field
  1531. */
  1532. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1533. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1534. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1535. /* Only for unicast frames */
  1536. if (!is_mcast) {
  1537. /* send it on VO queue */
  1538. msdu_info->tid = DP_VO_TID;
  1539. }
  1540. } else {
  1541. /*
  1542. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1543. * from TOS byte.
  1544. */
  1545. tos = ip->ip_tos;
  1546. dscp_tid_override = 1;
  1547. }
  1548. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1549. /* TODO
  1550. * use flowlabel
  1551. *igmpmld cases to be handled in phase 2
  1552. */
  1553. unsigned long ver_pri_flowlabel;
  1554. unsigned long pri;
  1555. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1556. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1557. DP_IPV6_PRIORITY_SHIFT;
  1558. tos = pri;
  1559. dscp_tid_override = 1;
  1560. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1561. msdu_info->tid = DP_VO_TID;
  1562. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1563. /* Only for unicast frames */
  1564. if (!is_mcast) {
  1565. /* send ucast arp on VO queue */
  1566. msdu_info->tid = DP_VO_TID;
  1567. }
  1568. }
  1569. /*
  1570. * Assign all MCAST packets to BE
  1571. */
  1572. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1573. if (is_mcast) {
  1574. tos = 0;
  1575. dscp_tid_override = 1;
  1576. }
  1577. }
  1578. if (dscp_tid_override == 1) {
  1579. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1580. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1581. }
  1582. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1583. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1584. return;
  1585. }
  1586. /**
  1587. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1588. * @vdev: DP vdev handle
  1589. * @nbuf: skb
  1590. * @msdu_info: msdu descriptor
  1591. *
  1592. * Software based TID classification is required when more than 2 DSCP-TID
  1593. * mapping tables are needed.
  1594. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1595. *
  1596. * Return: void
  1597. */
  1598. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1599. struct dp_tx_msdu_info_s *msdu_info)
  1600. {
  1601. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1602. /*
  1603. * skip_sw_tid_classification flag will set in below cases-
  1604. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1605. * 2. hlos_tid_override enabled for vdev
  1606. * 3. mesh mode enabled for vdev
  1607. */
  1608. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1609. /* Update tid in msdu_info from skb priority */
  1610. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1611. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1612. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1613. if (tid == DP_TX_INVALID_QOS_TAG)
  1614. return;
  1615. msdu_info->tid = tid;
  1616. return;
  1617. }
  1618. return;
  1619. }
  1620. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1621. }
  1622. #ifdef FEATURE_WLAN_TDLS
  1623. /**
  1624. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1625. * @soc: datapath SOC
  1626. * @vdev: datapath vdev
  1627. * @tx_desc: TX descriptor
  1628. *
  1629. * Return: None
  1630. */
  1631. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1632. struct dp_vdev *vdev,
  1633. struct dp_tx_desc_s *tx_desc)
  1634. {
  1635. if (vdev) {
  1636. if (vdev->is_tdls_frame) {
  1637. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1638. vdev->is_tdls_frame = false;
  1639. }
  1640. }
  1641. }
  1642. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1643. {
  1644. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1645. switch (soc->arch_id) {
  1646. case CDP_ARCH_TYPE_LI:
  1647. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1648. break;
  1649. case CDP_ARCH_TYPE_BE:
  1650. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1651. break;
  1652. case CDP_ARCH_TYPE_RH:
  1653. {
  1654. uint32_t *msg_word = (uint32_t *)htt_desc;
  1655. tx_status = HTT_TX_MSDU_INFO_RELEASE_REASON_GET(
  1656. *(msg_word + 3));
  1657. }
  1658. break;
  1659. default:
  1660. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1661. QDF_BUG(0);
  1662. }
  1663. return tx_status;
  1664. }
  1665. /**
  1666. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1667. * @soc: dp_soc handle
  1668. * @tx_desc: TX descriptor
  1669. *
  1670. * Return: None
  1671. */
  1672. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1673. struct dp_tx_desc_s *tx_desc)
  1674. {
  1675. uint8_t tx_status = 0;
  1676. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1677. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1678. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1679. DP_MOD_ID_TDLS);
  1680. if (qdf_unlikely(!vdev)) {
  1681. dp_err_rl("vdev is null!");
  1682. goto error;
  1683. }
  1684. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1685. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1686. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1687. if (vdev->tx_non_std_data_callback.func) {
  1688. qdf_nbuf_set_next(nbuf, NULL);
  1689. vdev->tx_non_std_data_callback.func(
  1690. vdev->tx_non_std_data_callback.ctxt,
  1691. nbuf, tx_status);
  1692. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1693. return;
  1694. } else {
  1695. dp_err_rl("callback func is null");
  1696. }
  1697. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1698. error:
  1699. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1700. qdf_nbuf_free(nbuf);
  1701. }
  1702. /**
  1703. * dp_tx_msdu_single_map() - do nbuf map
  1704. * @vdev: DP vdev handle
  1705. * @tx_desc: DP TX descriptor pointer
  1706. * @nbuf: skb pointer
  1707. *
  1708. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1709. * operation done in other component.
  1710. *
  1711. * Return: QDF_STATUS
  1712. */
  1713. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1714. struct dp_tx_desc_s *tx_desc,
  1715. qdf_nbuf_t nbuf)
  1716. {
  1717. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1718. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1719. nbuf,
  1720. QDF_DMA_TO_DEVICE,
  1721. nbuf->len);
  1722. else
  1723. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1724. QDF_DMA_TO_DEVICE);
  1725. }
  1726. #else
  1727. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1728. struct dp_vdev *vdev,
  1729. struct dp_tx_desc_s *tx_desc)
  1730. {
  1731. }
  1732. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1733. struct dp_tx_desc_s *tx_desc)
  1734. {
  1735. }
  1736. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1737. struct dp_tx_desc_s *tx_desc,
  1738. qdf_nbuf_t nbuf)
  1739. {
  1740. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1741. nbuf,
  1742. QDF_DMA_TO_DEVICE,
  1743. nbuf->len);
  1744. }
  1745. #endif
  1746. static inline
  1747. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1748. struct dp_tx_desc_s *tx_desc,
  1749. qdf_nbuf_t nbuf)
  1750. {
  1751. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1752. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1753. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1754. return 0;
  1755. return qdf_nbuf_mapped_paddr_get(nbuf);
  1756. }
  1757. static inline
  1758. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1759. {
  1760. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1761. desc->nbuf,
  1762. desc->dma_addr,
  1763. QDF_DMA_TO_DEVICE,
  1764. desc->length);
  1765. }
  1766. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1767. static inline bool
  1768. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1769. {
  1770. struct net_device *ingress_dev;
  1771. skb_frag_t *frag;
  1772. uint16_t buf_len = 0;
  1773. uint16_t linear_data_len = 0;
  1774. uint8_t *payload_addr = NULL;
  1775. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1776. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1777. dev_put(ingress_dev);
  1778. frag = &(skb_shinfo(nbuf)->frags[0]);
  1779. buf_len = skb_frag_size(frag);
  1780. payload_addr = (uint8_t *)skb_frag_address(frag);
  1781. linear_data_len = skb_headlen(nbuf);
  1782. buf_len += linear_data_len;
  1783. payload_addr = payload_addr - linear_data_len;
  1784. memcpy(payload_addr, nbuf->data, linear_data_len);
  1785. msdu_info->frm_type = dp_tx_frm_rmnet;
  1786. msdu_info->buf_len = buf_len;
  1787. msdu_info->payload_addr = payload_addr;
  1788. return true;
  1789. }
  1790. dev_put(ingress_dev);
  1791. return false;
  1792. }
  1793. static inline
  1794. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1795. struct dp_tx_desc_s *tx_desc)
  1796. {
  1797. qdf_dma_addr_t paddr;
  1798. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1799. tx_desc->length = msdu_info->buf_len;
  1800. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1801. (void *)(msdu_info->payload_addr +
  1802. msdu_info->buf_len));
  1803. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1804. return paddr;
  1805. }
  1806. #else
  1807. static inline bool
  1808. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1809. {
  1810. return false;
  1811. }
  1812. static inline
  1813. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1814. struct dp_tx_desc_s *tx_desc)
  1815. {
  1816. return 0;
  1817. }
  1818. #endif
  1819. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1820. static inline
  1821. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1822. struct dp_tx_desc_s *tx_desc,
  1823. qdf_nbuf_t nbuf)
  1824. {
  1825. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1826. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1827. (void *)(nbuf->data + nbuf->len));
  1828. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1829. } else {
  1830. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1831. }
  1832. }
  1833. static inline
  1834. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1835. struct dp_tx_desc_s *desc)
  1836. {
  1837. if (qdf_unlikely(!(desc->flags &
  1838. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1839. return dp_tx_nbuf_unmap_regular(soc, desc);
  1840. }
  1841. #else
  1842. static inline
  1843. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1844. struct dp_tx_desc_s *tx_desc,
  1845. qdf_nbuf_t nbuf)
  1846. {
  1847. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1848. }
  1849. static inline
  1850. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1851. struct dp_tx_desc_s *desc)
  1852. {
  1853. return dp_tx_nbuf_unmap_regular(soc, desc);
  1854. }
  1855. #endif
  1856. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1857. static inline
  1858. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1859. {
  1860. dp_tx_nbuf_unmap(soc, desc);
  1861. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1862. }
  1863. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1864. {
  1865. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1866. dp_tx_nbuf_unmap(soc, desc);
  1867. }
  1868. #else
  1869. static inline
  1870. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1871. {
  1872. }
  1873. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1874. {
  1875. dp_tx_nbuf_unmap(soc, desc);
  1876. }
  1877. #endif
  1878. #ifdef MESH_MODE_SUPPORT
  1879. /**
  1880. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1881. * @soc: datapath SOC
  1882. * @vdev: datapath vdev
  1883. * @tx_desc: TX descriptor
  1884. *
  1885. * Return: None
  1886. */
  1887. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1888. struct dp_vdev *vdev,
  1889. struct dp_tx_desc_s *tx_desc)
  1890. {
  1891. if (qdf_unlikely(vdev->mesh_vdev))
  1892. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1893. }
  1894. /**
  1895. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1896. * @soc: dp_soc handle
  1897. * @tx_desc: TX descriptor
  1898. * @delayed_free: delay the nbuf free
  1899. *
  1900. * Return: nbuf to be freed late
  1901. */
  1902. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1903. struct dp_tx_desc_s *tx_desc,
  1904. bool delayed_free)
  1905. {
  1906. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1907. struct dp_vdev *vdev = NULL;
  1908. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1909. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1910. if (vdev)
  1911. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1912. if (delayed_free)
  1913. return nbuf;
  1914. qdf_nbuf_free(nbuf);
  1915. } else {
  1916. if (vdev && vdev->osif_tx_free_ext) {
  1917. vdev->osif_tx_free_ext((nbuf));
  1918. } else {
  1919. if (delayed_free)
  1920. return nbuf;
  1921. qdf_nbuf_free(nbuf);
  1922. }
  1923. }
  1924. if (vdev)
  1925. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1926. return NULL;
  1927. }
  1928. #else
  1929. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1930. struct dp_vdev *vdev,
  1931. struct dp_tx_desc_s *tx_desc)
  1932. {
  1933. }
  1934. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1935. struct dp_tx_desc_s *tx_desc,
  1936. bool delayed_free)
  1937. {
  1938. return NULL;
  1939. }
  1940. #endif
  1941. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1942. {
  1943. struct dp_pdev *pdev = NULL;
  1944. struct dp_ast_entry *src_ast_entry = NULL;
  1945. struct dp_ast_entry *dst_ast_entry = NULL;
  1946. struct dp_soc *soc = NULL;
  1947. qdf_assert(vdev);
  1948. pdev = vdev->pdev;
  1949. qdf_assert(pdev);
  1950. soc = pdev->soc;
  1951. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1952. (soc, dstmac, vdev->pdev->pdev_id);
  1953. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1954. (soc, srcmac, vdev->pdev->pdev_id);
  1955. if (dst_ast_entry && src_ast_entry) {
  1956. if (dst_ast_entry->peer_id ==
  1957. src_ast_entry->peer_id)
  1958. return 1;
  1959. }
  1960. return 0;
  1961. }
  1962. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1963. defined(WLAN_MCAST_MLO)
  1964. /* MLO peer id for reinject*/
  1965. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1966. /* MLO vdev id inc offset */
  1967. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1968. #ifdef QCA_SUPPORT_WDS_EXTENDED
  1969. static inline bool
  1970. dp_tx_wds_ext_check(struct cdp_tx_exception_metadata *tx_exc_metadata)
  1971. {
  1972. if (tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  1973. return true;
  1974. return false;
  1975. }
  1976. #else
  1977. static inline bool
  1978. dp_tx_wds_ext_check(struct cdp_tx_exception_metadata *tx_exc_metadata)
  1979. {
  1980. return false;
  1981. }
  1982. #endif
  1983. static inline void
  1984. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  1985. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1986. {
  1987. /* wds ext enabled will not set the TO_FW bit */
  1988. if (dp_tx_wds_ext_check(tx_exc_metadata))
  1989. return;
  1990. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1991. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1992. qdf_atomic_inc(&soc->num_tx_exception);
  1993. }
  1994. }
  1995. static inline void
  1996. dp_tx_update_mcast_param(uint16_t peer_id,
  1997. uint16_t *htt_tcl_metadata,
  1998. struct dp_vdev *vdev,
  1999. struct dp_tx_msdu_info_s *msdu_info)
  2000. {
  2001. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  2002. *htt_tcl_metadata = 0;
  2003. DP_TX_TCL_METADATA_TYPE_SET(
  2004. *htt_tcl_metadata,
  2005. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  2006. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2007. msdu_info->gsn);
  2008. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2009. if (qdf_unlikely(vdev->nawds_enabled ||
  2010. dp_vdev_is_wds_ext_enabled(vdev)))
  2011. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2012. *htt_tcl_metadata, 1);
  2013. } else {
  2014. msdu_info->vdev_id = vdev->vdev_id;
  2015. }
  2016. }
  2017. #else
  2018. static inline void
  2019. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  2020. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2021. {
  2022. }
  2023. static inline void
  2024. dp_tx_update_mcast_param(uint16_t peer_id,
  2025. uint16_t *htt_tcl_metadata,
  2026. struct dp_vdev *vdev,
  2027. struct dp_tx_msdu_info_s *msdu_info)
  2028. {
  2029. }
  2030. #endif
  2031. #ifdef DP_TX_SW_DROP_STATS_INC
  2032. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2033. qdf_nbuf_t nbuf,
  2034. enum cdp_tx_sw_drop drop_code)
  2035. {
  2036. /* EAPOL Drop stats */
  2037. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2038. switch (drop_code) {
  2039. case TX_DESC_ERR:
  2040. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2041. break;
  2042. case TX_HAL_RING_ACCESS_ERR:
  2043. DP_STATS_INC(pdev,
  2044. eap_drop_stats.tx_hal_ring_access_err, 1);
  2045. break;
  2046. case TX_DMA_MAP_ERR:
  2047. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2048. break;
  2049. case TX_HW_ENQUEUE:
  2050. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2051. break;
  2052. case TX_SW_ENQUEUE:
  2053. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2054. break;
  2055. default:
  2056. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2057. break;
  2058. }
  2059. }
  2060. }
  2061. #else
  2062. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2063. qdf_nbuf_t nbuf,
  2064. enum cdp_tx_sw_drop drop_code)
  2065. {
  2066. }
  2067. #endif
  2068. qdf_nbuf_t
  2069. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2070. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2071. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2072. {
  2073. struct dp_pdev *pdev = vdev->pdev;
  2074. struct dp_soc *soc = pdev->soc;
  2075. struct dp_tx_desc_s *tx_desc;
  2076. QDF_STATUS status;
  2077. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2078. uint16_t htt_tcl_metadata = 0;
  2079. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2080. uint8_t tid = msdu_info->tid;
  2081. struct cdp_tid_tx_stats *tid_stats = NULL;
  2082. qdf_dma_addr_t paddr;
  2083. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2084. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2085. msdu_info, tx_exc_metadata);
  2086. if (!tx_desc) {
  2087. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2088. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2089. drop_code = TX_DESC_ERR;
  2090. goto fail_return;
  2091. }
  2092. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2093. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2094. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2095. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2096. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2097. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2098. DP_TCL_METADATA_TYPE_PEER_BASED);
  2099. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2100. peer_id);
  2101. dp_tx_bypass_reinjection(soc, tx_desc, tx_exc_metadata);
  2102. } else
  2103. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2104. if (msdu_info->exception_fw)
  2105. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2106. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2107. !pdev->enhanced_stats_en);
  2108. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2109. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2110. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2111. else
  2112. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2113. if (!paddr) {
  2114. /* Handle failure */
  2115. dp_err("qdf_nbuf_map failed");
  2116. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2117. drop_code = TX_DMA_MAP_ERR;
  2118. goto release_desc;
  2119. }
  2120. tx_desc->dma_addr = paddr;
  2121. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2122. tx_desc->id, DP_TX_DESC_MAP);
  2123. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2124. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2125. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2126. htt_tcl_metadata,
  2127. tx_exc_metadata, msdu_info);
  2128. if (status != QDF_STATUS_SUCCESS) {
  2129. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2130. tx_desc, tx_q->ring_id);
  2131. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2132. tx_desc->id, DP_TX_DESC_UNMAP);
  2133. dp_tx_nbuf_unmap(soc, tx_desc);
  2134. drop_code = TX_HW_ENQUEUE;
  2135. goto release_desc;
  2136. }
  2137. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2138. return NULL;
  2139. release_desc:
  2140. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2141. fail_return:
  2142. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2143. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2144. tid_stats = &pdev->stats.tid_stats.
  2145. tid_tx_stats[tx_q->ring_id][tid];
  2146. tid_stats->swdrop_cnt[drop_code]++;
  2147. return nbuf;
  2148. }
  2149. /**
  2150. * dp_tdls_tx_comp_free_buff() - Free non std buffer when TDLS flag is set
  2151. * @soc: Soc handle
  2152. * @desc: software Tx descriptor to be processed
  2153. *
  2154. * Return: 0 if Success
  2155. */
  2156. #ifdef FEATURE_WLAN_TDLS
  2157. static inline int
  2158. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2159. {
  2160. /* If it is TDLS mgmt, don't unmap or free the frame */
  2161. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2162. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2163. return 0;
  2164. }
  2165. return 1;
  2166. }
  2167. #else
  2168. static inline int
  2169. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2170. {
  2171. return 1;
  2172. }
  2173. #endif
  2174. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2175. bool delayed_free)
  2176. {
  2177. qdf_nbuf_t nbuf = desc->nbuf;
  2178. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2179. /* nbuf already freed in vdev detach path */
  2180. if (!nbuf)
  2181. return NULL;
  2182. if (!dp_tdls_tx_comp_free_buff(soc, desc))
  2183. return NULL;
  2184. /* 0 : MSDU buffer, 1 : MLE */
  2185. if (desc->msdu_ext_desc) {
  2186. /* TSO free */
  2187. if (hal_tx_ext_desc_get_tso_enable(
  2188. desc->msdu_ext_desc->vaddr)) {
  2189. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2190. desc->id, DP_TX_COMP_MSDU_EXT);
  2191. dp_tx_tso_seg_history_add(soc,
  2192. desc->msdu_ext_desc->tso_desc,
  2193. desc->nbuf, desc->id, type);
  2194. /* unmap eash TSO seg before free the nbuf */
  2195. dp_tx_tso_unmap_segment(soc,
  2196. desc->msdu_ext_desc->tso_desc,
  2197. desc->msdu_ext_desc->
  2198. tso_num_desc);
  2199. goto nbuf_free;
  2200. }
  2201. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2202. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2203. qdf_dma_addr_t iova;
  2204. uint32_t frag_len;
  2205. uint32_t i;
  2206. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2207. QDF_DMA_TO_DEVICE,
  2208. qdf_nbuf_headlen(nbuf));
  2209. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2210. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2211. &iova,
  2212. &frag_len);
  2213. if (!iova || !frag_len)
  2214. break;
  2215. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2216. QDF_DMA_TO_DEVICE);
  2217. }
  2218. goto nbuf_free;
  2219. }
  2220. }
  2221. /* If it's ME frame, dont unmap the cloned nbuf's */
  2222. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2223. goto nbuf_free;
  2224. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2225. dp_tx_unmap(soc, desc);
  2226. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2227. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2228. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2229. return NULL;
  2230. nbuf_free:
  2231. if (delayed_free)
  2232. return nbuf;
  2233. qdf_nbuf_free(nbuf);
  2234. return NULL;
  2235. }
  2236. /**
  2237. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2238. * @soc: DP soc handle
  2239. * @nbuf: skb
  2240. * @msdu_info: MSDU info
  2241. *
  2242. * Return: None
  2243. */
  2244. static inline void
  2245. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2246. struct dp_tx_msdu_info_s *msdu_info)
  2247. {
  2248. uint32_t cur_idx;
  2249. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2250. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2251. qdf_nbuf_headlen(nbuf));
  2252. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2253. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2254. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2255. seg->frags[cur_idx].paddr_hi) << 32),
  2256. seg->frags[cur_idx].len,
  2257. QDF_DMA_TO_DEVICE);
  2258. }
  2259. #if QDF_LOCK_STATS
  2260. noinline
  2261. #else
  2262. #endif
  2263. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2264. struct dp_tx_msdu_info_s *msdu_info)
  2265. {
  2266. uint32_t i;
  2267. struct dp_pdev *pdev = vdev->pdev;
  2268. struct dp_soc *soc = pdev->soc;
  2269. struct dp_tx_desc_s *tx_desc;
  2270. bool is_cce_classified = false;
  2271. QDF_STATUS status;
  2272. uint16_t htt_tcl_metadata = 0;
  2273. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2274. struct cdp_tid_tx_stats *tid_stats = NULL;
  2275. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2276. if (msdu_info->frm_type == dp_tx_frm_me)
  2277. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2278. i = 0;
  2279. /* Print statement to track i and num_seg */
  2280. /*
  2281. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2282. * descriptors using information in msdu_info
  2283. */
  2284. while (i < msdu_info->num_seg) {
  2285. /*
  2286. * Setup Tx descriptor for an MSDU, and MSDU extension
  2287. * descriptor
  2288. */
  2289. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2290. tx_q->desc_pool_id);
  2291. if (!tx_desc) {
  2292. if (msdu_info->frm_type == dp_tx_frm_me) {
  2293. prep_desc_fail++;
  2294. dp_tx_me_free_buf(pdev,
  2295. (void *)(msdu_info->u.sg_info
  2296. .curr_seg->frags[0].vaddr));
  2297. if (prep_desc_fail == msdu_info->num_seg) {
  2298. /*
  2299. * Unmap is needed only if descriptor
  2300. * preparation failed for all segments.
  2301. */
  2302. qdf_nbuf_unmap(soc->osdev,
  2303. msdu_info->u.sg_info.
  2304. curr_seg->nbuf,
  2305. QDF_DMA_TO_DEVICE);
  2306. }
  2307. /*
  2308. * Free the nbuf for the current segment
  2309. * and make it point to the next in the list.
  2310. * For me, there are as many segments as there
  2311. * are no of clients.
  2312. */
  2313. qdf_nbuf_free(msdu_info->u.sg_info
  2314. .curr_seg->nbuf);
  2315. if (msdu_info->u.sg_info.curr_seg->next) {
  2316. msdu_info->u.sg_info.curr_seg =
  2317. msdu_info->u.sg_info
  2318. .curr_seg->next;
  2319. nbuf = msdu_info->u.sg_info
  2320. .curr_seg->nbuf;
  2321. }
  2322. i++;
  2323. continue;
  2324. }
  2325. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2326. dp_tx_tso_seg_history_add(
  2327. soc,
  2328. msdu_info->u.tso_info.curr_seg,
  2329. nbuf, 0, DP_TX_DESC_UNMAP);
  2330. dp_tx_tso_unmap_segment(soc,
  2331. msdu_info->u.tso_info.
  2332. curr_seg,
  2333. msdu_info->u.tso_info.
  2334. tso_num_seg_list);
  2335. if (msdu_info->u.tso_info.curr_seg->next) {
  2336. msdu_info->u.tso_info.curr_seg =
  2337. msdu_info->u.tso_info.curr_seg->next;
  2338. i++;
  2339. continue;
  2340. }
  2341. }
  2342. if (msdu_info->frm_type == dp_tx_frm_sg)
  2343. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2344. goto done;
  2345. }
  2346. if (msdu_info->frm_type == dp_tx_frm_me) {
  2347. tx_desc->msdu_ext_desc->me_buffer =
  2348. (struct dp_tx_me_buf_t *)msdu_info->
  2349. u.sg_info.curr_seg->frags[0].vaddr;
  2350. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2351. }
  2352. if (is_cce_classified)
  2353. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2354. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2355. if (msdu_info->exception_fw) {
  2356. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2357. }
  2358. dp_tx_is_hp_update_required(i, msdu_info);
  2359. /*
  2360. * For frames with multiple segments (TSO, ME), jump to next
  2361. * segment.
  2362. */
  2363. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2364. if (msdu_info->u.tso_info.curr_seg->next) {
  2365. msdu_info->u.tso_info.curr_seg =
  2366. msdu_info->u.tso_info.curr_seg->next;
  2367. /*
  2368. * If this is a jumbo nbuf, then increment the
  2369. * number of nbuf users for each additional
  2370. * segment of the msdu. This will ensure that
  2371. * the skb is freed only after receiving tx
  2372. * completion for all segments of an nbuf
  2373. */
  2374. qdf_nbuf_inc_users(nbuf);
  2375. /* Check with MCL if this is needed */
  2376. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2377. */
  2378. }
  2379. }
  2380. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2381. &htt_tcl_metadata,
  2382. vdev,
  2383. msdu_info);
  2384. /*
  2385. * Enqueue the Tx MSDU descriptor to HW for transmit
  2386. */
  2387. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2388. htt_tcl_metadata,
  2389. NULL, msdu_info);
  2390. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2391. if (status != QDF_STATUS_SUCCESS) {
  2392. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2393. tx_desc, tx_q->ring_id);
  2394. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2395. tid_stats = &pdev->stats.tid_stats.
  2396. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2397. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2398. if (msdu_info->frm_type == dp_tx_frm_me) {
  2399. hw_enq_fail++;
  2400. if (hw_enq_fail == msdu_info->num_seg) {
  2401. /*
  2402. * Unmap is needed only if enqueue
  2403. * failed for all segments.
  2404. */
  2405. qdf_nbuf_unmap(soc->osdev,
  2406. msdu_info->u.sg_info.
  2407. curr_seg->nbuf,
  2408. QDF_DMA_TO_DEVICE);
  2409. }
  2410. /*
  2411. * Free the nbuf for the current segment
  2412. * and make it point to the next in the list.
  2413. * For me, there are as many segments as there
  2414. * are no of clients.
  2415. */
  2416. qdf_nbuf_free(msdu_info->u.sg_info
  2417. .curr_seg->nbuf);
  2418. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2419. if (msdu_info->u.sg_info.curr_seg->next) {
  2420. msdu_info->u.sg_info.curr_seg =
  2421. msdu_info->u.sg_info
  2422. .curr_seg->next;
  2423. nbuf = msdu_info->u.sg_info
  2424. .curr_seg->nbuf;
  2425. } else
  2426. break;
  2427. i++;
  2428. continue;
  2429. }
  2430. /*
  2431. * For TSO frames, the nbuf users increment done for
  2432. * the current segment has to be reverted, since the
  2433. * hw enqueue for this segment failed
  2434. */
  2435. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2436. msdu_info->u.tso_info.curr_seg) {
  2437. /*
  2438. * unmap and free current,
  2439. * retransmit remaining segments
  2440. */
  2441. dp_tx_comp_free_buf(soc, tx_desc, false);
  2442. i++;
  2443. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2444. continue;
  2445. }
  2446. if (msdu_info->frm_type == dp_tx_frm_sg)
  2447. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2448. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2449. goto done;
  2450. }
  2451. /*
  2452. * TODO
  2453. * if tso_info structure can be modified to have curr_seg
  2454. * as first element, following 2 blocks of code (for TSO and SG)
  2455. * can be combined into 1
  2456. */
  2457. /*
  2458. * For Multicast-Unicast converted packets,
  2459. * each converted frame (for a client) is represented as
  2460. * 1 segment
  2461. */
  2462. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2463. (msdu_info->frm_type == dp_tx_frm_me)) {
  2464. if (msdu_info->u.sg_info.curr_seg->next) {
  2465. msdu_info->u.sg_info.curr_seg =
  2466. msdu_info->u.sg_info.curr_seg->next;
  2467. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2468. } else
  2469. break;
  2470. }
  2471. i++;
  2472. }
  2473. nbuf = NULL;
  2474. done:
  2475. return nbuf;
  2476. }
  2477. /**
  2478. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2479. * for SG frames
  2480. * @vdev: DP vdev handle
  2481. * @nbuf: skb
  2482. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2483. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2484. *
  2485. * Return: NULL on success,
  2486. * nbuf when it fails to send
  2487. */
  2488. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2489. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2490. {
  2491. uint32_t cur_frag, nr_frags, i;
  2492. qdf_dma_addr_t paddr;
  2493. struct dp_tx_sg_info_s *sg_info;
  2494. sg_info = &msdu_info->u.sg_info;
  2495. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2496. if (QDF_STATUS_SUCCESS !=
  2497. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2498. QDF_DMA_TO_DEVICE,
  2499. qdf_nbuf_headlen(nbuf))) {
  2500. dp_tx_err("dma map error");
  2501. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2502. qdf_nbuf_free(nbuf);
  2503. return NULL;
  2504. }
  2505. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2506. seg_info->frags[0].paddr_lo = paddr;
  2507. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2508. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2509. seg_info->frags[0].vaddr = (void *) nbuf;
  2510. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2511. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2512. nbuf, 0,
  2513. QDF_DMA_TO_DEVICE,
  2514. cur_frag)) {
  2515. dp_tx_err("frag dma map error");
  2516. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2517. goto map_err;
  2518. }
  2519. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2520. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2521. seg_info->frags[cur_frag + 1].paddr_hi =
  2522. ((uint64_t) paddr) >> 32;
  2523. seg_info->frags[cur_frag + 1].len =
  2524. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2525. }
  2526. seg_info->frag_cnt = (cur_frag + 1);
  2527. seg_info->total_len = qdf_nbuf_len(nbuf);
  2528. seg_info->next = NULL;
  2529. sg_info->curr_seg = seg_info;
  2530. msdu_info->frm_type = dp_tx_frm_sg;
  2531. msdu_info->num_seg = 1;
  2532. return nbuf;
  2533. map_err:
  2534. /* restore paddr into nbuf before calling unmap */
  2535. qdf_nbuf_mapped_paddr_set(nbuf,
  2536. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2537. ((uint64_t)
  2538. seg_info->frags[0].paddr_hi) << 32));
  2539. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2540. QDF_DMA_TO_DEVICE,
  2541. seg_info->frags[0].len);
  2542. for (i = 1; i <= cur_frag; i++) {
  2543. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2544. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2545. seg_info->frags[i].paddr_hi) << 32),
  2546. seg_info->frags[i].len,
  2547. QDF_DMA_TO_DEVICE);
  2548. }
  2549. qdf_nbuf_free(nbuf);
  2550. return NULL;
  2551. }
  2552. /**
  2553. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2554. * @vdev: DP vdev handle
  2555. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2556. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2557. *
  2558. * Return: NULL on failure,
  2559. * nbuf when extracted successfully
  2560. */
  2561. static
  2562. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2563. struct dp_tx_msdu_info_s *msdu_info,
  2564. uint16_t ppdu_cookie)
  2565. {
  2566. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2567. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2568. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2569. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2570. (msdu_info->meta_data[5], 1);
  2571. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2572. (msdu_info->meta_data[5], 1);
  2573. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2574. (msdu_info->meta_data[6], ppdu_cookie);
  2575. msdu_info->exception_fw = 1;
  2576. msdu_info->is_tx_sniffer = 1;
  2577. }
  2578. #ifdef MESH_MODE_SUPPORT
  2579. /**
  2580. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2581. * and prepare msdu_info for mesh frames.
  2582. * @vdev: DP vdev handle
  2583. * @nbuf: skb
  2584. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2585. *
  2586. * Return: NULL on failure,
  2587. * nbuf when extracted successfully
  2588. */
  2589. static
  2590. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2591. struct dp_tx_msdu_info_s *msdu_info)
  2592. {
  2593. struct meta_hdr_s *mhdr;
  2594. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2595. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2596. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2597. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2598. msdu_info->exception_fw = 0;
  2599. goto remove_meta_hdr;
  2600. }
  2601. msdu_info->exception_fw = 1;
  2602. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2603. meta_data->host_tx_desc_pool = 1;
  2604. meta_data->update_peer_cache = 1;
  2605. meta_data->learning_frame = 1;
  2606. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2607. meta_data->power = mhdr->power;
  2608. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2609. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2610. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2611. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2612. meta_data->dyn_bw = 1;
  2613. meta_data->valid_pwr = 1;
  2614. meta_data->valid_mcs_mask = 1;
  2615. meta_data->valid_nss_mask = 1;
  2616. meta_data->valid_preamble_type = 1;
  2617. meta_data->valid_retries = 1;
  2618. meta_data->valid_bw_info = 1;
  2619. }
  2620. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2621. meta_data->encrypt_type = 0;
  2622. meta_data->valid_encrypt_type = 1;
  2623. meta_data->learning_frame = 0;
  2624. }
  2625. meta_data->valid_key_flags = 1;
  2626. meta_data->key_flags = (mhdr->keyix & 0x3);
  2627. remove_meta_hdr:
  2628. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2629. dp_tx_err("qdf_nbuf_pull_head failed");
  2630. qdf_nbuf_free(nbuf);
  2631. return NULL;
  2632. }
  2633. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2634. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2635. " tid %d to_fw %d",
  2636. msdu_info->meta_data[0],
  2637. msdu_info->meta_data[1],
  2638. msdu_info->meta_data[2],
  2639. msdu_info->meta_data[3],
  2640. msdu_info->meta_data[4],
  2641. msdu_info->meta_data[5],
  2642. msdu_info->tid, msdu_info->exception_fw);
  2643. return nbuf;
  2644. }
  2645. #else
  2646. static
  2647. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2648. struct dp_tx_msdu_info_s *msdu_info)
  2649. {
  2650. return nbuf;
  2651. }
  2652. #endif
  2653. /**
  2654. * dp_check_exc_metadata() - Checks if parameters are valid
  2655. * @tx_exc: holds all exception path parameters
  2656. *
  2657. * Return: true when all the parameters are valid else false
  2658. *
  2659. */
  2660. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2661. {
  2662. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2663. HTT_INVALID_TID);
  2664. bool invalid_encap_type =
  2665. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2666. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2667. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2668. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2669. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2670. tx_exc->ppdu_cookie == 0);
  2671. if (tx_exc->is_intrabss_fwd)
  2672. return true;
  2673. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2674. invalid_cookie) {
  2675. return false;
  2676. }
  2677. return true;
  2678. }
  2679. #ifdef ATH_SUPPORT_IQUE
  2680. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2681. {
  2682. qdf_ether_header_t *eh;
  2683. /* Mcast to Ucast Conversion*/
  2684. if (qdf_likely(!vdev->mcast_enhancement_en))
  2685. return true;
  2686. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2687. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2688. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2689. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2690. qdf_nbuf_set_next(nbuf, NULL);
  2691. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2692. qdf_nbuf_len(nbuf));
  2693. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2694. QDF_STATUS_SUCCESS) {
  2695. return false;
  2696. }
  2697. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2698. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2699. QDF_STATUS_SUCCESS) {
  2700. return false;
  2701. }
  2702. }
  2703. }
  2704. return true;
  2705. }
  2706. #else
  2707. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2708. {
  2709. return true;
  2710. }
  2711. #endif
  2712. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2713. /**
  2714. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2715. * @vdev: vdev handle
  2716. * @nbuf: skb
  2717. *
  2718. * Return: true if frame is dropped, false otherwise
  2719. */
  2720. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2721. {
  2722. /* Drop tx mcast and WDS Extended feature check */
  2723. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2724. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2725. qdf_nbuf_data(nbuf);
  2726. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2727. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2728. return true;
  2729. }
  2730. }
  2731. return false;
  2732. }
  2733. #else
  2734. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2735. {
  2736. return false;
  2737. }
  2738. #endif
  2739. /**
  2740. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2741. * @nbuf: qdf_nbuf_t
  2742. * @vdev: struct dp_vdev *
  2743. *
  2744. * Allow packet for processing only if it is for peer client which is
  2745. * connected with same vap. Drop packet if client is connected to
  2746. * different vap.
  2747. *
  2748. * Return: QDF_STATUS
  2749. */
  2750. static inline QDF_STATUS
  2751. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2752. {
  2753. struct dp_ast_entry *dst_ast_entry = NULL;
  2754. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2755. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2756. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2757. return QDF_STATUS_SUCCESS;
  2758. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2759. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2760. eh->ether_dhost,
  2761. vdev->vdev_id);
  2762. /* If there is no ast entry, return failure */
  2763. if (qdf_unlikely(!dst_ast_entry)) {
  2764. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2765. return QDF_STATUS_E_FAILURE;
  2766. }
  2767. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2768. return QDF_STATUS_SUCCESS;
  2769. }
  2770. /**
  2771. * dp_tx_nawds_handler() - NAWDS handler
  2772. *
  2773. * @soc: DP soc handle
  2774. * @vdev: DP vdev handle
  2775. * @msdu_info: msdu_info required to create HTT metadata
  2776. * @nbuf: skb
  2777. * @sa_peer_id:
  2778. *
  2779. * This API transfers the multicast frames with the peer id
  2780. * on NAWDS enabled peer.
  2781. *
  2782. * Return: none
  2783. */
  2784. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2785. struct dp_tx_msdu_info_s *msdu_info,
  2786. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2787. {
  2788. struct dp_peer *peer = NULL;
  2789. qdf_nbuf_t nbuf_clone = NULL;
  2790. uint16_t peer_id = DP_INVALID_PEER;
  2791. struct dp_txrx_peer *txrx_peer;
  2792. uint8_t link_id = 0;
  2793. /* This check avoids pkt forwarding which is entered
  2794. * in the ast table but still doesn't have valid peerid.
  2795. */
  2796. if (sa_peer_id == HTT_INVALID_PEER)
  2797. return;
  2798. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2799. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2800. txrx_peer = dp_get_txrx_peer(peer);
  2801. if (!txrx_peer)
  2802. continue;
  2803. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2804. peer_id = peer->peer_id;
  2805. if (!dp_peer_is_primary_link_peer(peer))
  2806. continue;
  2807. /* In the case of wds ext peer mcast traffic will be
  2808. * sent as part of VLAN interface
  2809. */
  2810. if (dp_peer_is_wds_ext_peer(txrx_peer))
  2811. continue;
  2812. /* Multicast packets needs to be
  2813. * dropped in case of intra bss forwarding
  2814. */
  2815. if (sa_peer_id == txrx_peer->peer_id) {
  2816. dp_tx_debug("multicast packet");
  2817. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2818. tx.nawds_mcast_drop,
  2819. 1, link_id);
  2820. continue;
  2821. }
  2822. nbuf_clone = qdf_nbuf_clone(nbuf);
  2823. if (!nbuf_clone) {
  2824. QDF_TRACE(QDF_MODULE_ID_DP,
  2825. QDF_TRACE_LEVEL_ERROR,
  2826. FL("nbuf clone failed"));
  2827. break;
  2828. }
  2829. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2830. msdu_info, peer_id,
  2831. NULL);
  2832. if (nbuf_clone) {
  2833. dp_tx_debug("pkt send failed");
  2834. qdf_nbuf_free(nbuf_clone);
  2835. } else {
  2836. if (peer_id != DP_INVALID_PEER)
  2837. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2838. tx.nawds_mcast,
  2839. 1, qdf_nbuf_len(nbuf), link_id);
  2840. }
  2841. }
  2842. }
  2843. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2844. }
  2845. #ifdef WLAN_MCAST_MLO
  2846. static inline bool
  2847. dp_tx_check_mesh_vdev(struct dp_vdev *vdev,
  2848. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2849. {
  2850. if (!tx_exc_metadata->is_mlo_mcast && qdf_unlikely(vdev->mesh_vdev))
  2851. return true;
  2852. return false;
  2853. }
  2854. #else
  2855. static inline bool
  2856. dp_tx_check_mesh_vdev(struct dp_vdev *vdev,
  2857. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2858. {
  2859. if (qdf_unlikely(vdev->mesh_vdev))
  2860. return true;
  2861. return false;
  2862. }
  2863. #endif
  2864. qdf_nbuf_t
  2865. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2866. qdf_nbuf_t nbuf,
  2867. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2868. {
  2869. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2870. struct dp_tx_msdu_info_s msdu_info;
  2871. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2872. DP_MOD_ID_TX_EXCEPTION);
  2873. if (qdf_unlikely(!vdev))
  2874. goto fail;
  2875. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2876. if (!tx_exc_metadata)
  2877. goto fail;
  2878. msdu_info.tid = tx_exc_metadata->tid;
  2879. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2880. QDF_MAC_ADDR_REF(nbuf->data));
  2881. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2882. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2883. dp_tx_err("Invalid parameters in exception path");
  2884. goto fail;
  2885. }
  2886. /* for peer based metadata check if peer is valid */
  2887. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2888. struct dp_peer *peer = NULL;
  2889. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2890. tx_exc_metadata->peer_id,
  2891. DP_MOD_ID_TX_EXCEPTION);
  2892. if (qdf_unlikely(!peer)) {
  2893. DP_STATS_INC(vdev,
  2894. tx_i.dropped.invalid_peer_id_in_exc_path,
  2895. 1);
  2896. goto fail;
  2897. }
  2898. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2899. }
  2900. /* Basic sanity checks for unsupported packets */
  2901. /* MESH mode */
  2902. if (dp_tx_check_mesh_vdev(vdev, tx_exc_metadata)) {
  2903. dp_tx_err("Mesh mode is not supported in exception path");
  2904. goto fail;
  2905. }
  2906. /*
  2907. * Classify the frame and call corresponding
  2908. * "prepare" function which extracts the segment (TSO)
  2909. * and fragmentation information (for TSO , SG, ME, or Raw)
  2910. * into MSDU_INFO structure which is later used to fill
  2911. * SW and HW descriptors.
  2912. */
  2913. if (qdf_nbuf_is_tso(nbuf)) {
  2914. dp_verbose_debug("TSO frame %pK", vdev);
  2915. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2916. qdf_nbuf_len(nbuf));
  2917. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2918. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2919. qdf_nbuf_len(nbuf));
  2920. goto fail;
  2921. }
  2922. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  2923. goto send_multiple;
  2924. }
  2925. /* SG */
  2926. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2927. struct dp_tx_seg_info_s seg_info = {0};
  2928. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2929. if (!nbuf)
  2930. goto fail;
  2931. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2932. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2933. qdf_nbuf_len(nbuf));
  2934. goto send_multiple;
  2935. }
  2936. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2937. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2938. qdf_nbuf_len(nbuf));
  2939. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2940. tx_exc_metadata->ppdu_cookie);
  2941. }
  2942. /*
  2943. * Get HW Queue to use for this frame.
  2944. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2945. * dedicated for data and 1 for command.
  2946. * "queue_id" maps to one hardware ring.
  2947. * With each ring, we also associate a unique Tx descriptor pool
  2948. * to minimize lock contention for these resources.
  2949. */
  2950. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2951. /*
  2952. * if the packet is mcast packet send through mlo_macst handler
  2953. * for all prnt_vdevs
  2954. */
  2955. if (soc->arch_ops.dp_tx_mlo_mcast_send) {
  2956. nbuf = soc->arch_ops.dp_tx_mlo_mcast_send(soc, vdev,
  2957. nbuf,
  2958. tx_exc_metadata);
  2959. if (!nbuf)
  2960. goto fail;
  2961. }
  2962. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2963. if (qdf_unlikely(vdev->nawds_enabled)) {
  2964. /*
  2965. * This is a multicast packet
  2966. */
  2967. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2968. tx_exc_metadata->peer_id);
  2969. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2970. 1, qdf_nbuf_len(nbuf));
  2971. }
  2972. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2973. DP_INVALID_PEER, NULL);
  2974. } else {
  2975. /*
  2976. * Check exception descriptors
  2977. */
  2978. if (dp_tx_exception_limit_check(vdev))
  2979. goto fail;
  2980. /* Single linear frame */
  2981. /*
  2982. * If nbuf is a simple linear frame, use send_single function to
  2983. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2984. * SRNG. There is no need to setup a MSDU extension descriptor.
  2985. */
  2986. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2987. tx_exc_metadata->peer_id,
  2988. tx_exc_metadata);
  2989. }
  2990. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2991. return nbuf;
  2992. send_multiple:
  2993. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2994. fail:
  2995. if (vdev)
  2996. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2997. dp_verbose_debug("pkt send failed");
  2998. return nbuf;
  2999. }
  3000. qdf_nbuf_t
  3001. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3002. uint8_t vdev_id, qdf_nbuf_t nbuf,
  3003. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3004. {
  3005. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3006. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3007. DP_MOD_ID_TX_EXCEPTION);
  3008. if (qdf_unlikely(!vdev))
  3009. goto fail;
  3010. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3011. == QDF_STATUS_E_FAILURE)) {
  3012. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3013. goto fail;
  3014. }
  3015. /* Unref count as it will again be taken inside dp_tx_exception */
  3016. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3017. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  3018. fail:
  3019. if (vdev)
  3020. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3021. dp_verbose_debug("pkt send failed");
  3022. return nbuf;
  3023. }
  3024. #ifdef MESH_MODE_SUPPORT
  3025. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3026. qdf_nbuf_t nbuf)
  3027. {
  3028. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3029. struct meta_hdr_s *mhdr;
  3030. qdf_nbuf_t nbuf_mesh = NULL;
  3031. qdf_nbuf_t nbuf_clone = NULL;
  3032. struct dp_vdev *vdev;
  3033. uint8_t no_enc_frame = 0;
  3034. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3035. if (!nbuf_mesh) {
  3036. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3037. "qdf_nbuf_unshare failed");
  3038. return nbuf;
  3039. }
  3040. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3041. if (!vdev) {
  3042. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3043. "vdev is NULL for vdev_id %d", vdev_id);
  3044. return nbuf;
  3045. }
  3046. nbuf = nbuf_mesh;
  3047. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3048. if ((vdev->sec_type != cdp_sec_type_none) &&
  3049. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3050. no_enc_frame = 1;
  3051. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3052. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3053. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3054. !no_enc_frame) {
  3055. nbuf_clone = qdf_nbuf_clone(nbuf);
  3056. if (!nbuf_clone) {
  3057. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3058. "qdf_nbuf_clone failed");
  3059. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3060. return nbuf;
  3061. }
  3062. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3063. }
  3064. if (nbuf_clone) {
  3065. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3066. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3067. } else {
  3068. qdf_nbuf_free(nbuf_clone);
  3069. }
  3070. }
  3071. if (no_enc_frame)
  3072. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3073. else
  3074. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3075. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3076. if ((!nbuf) && no_enc_frame) {
  3077. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3078. }
  3079. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3080. return nbuf;
  3081. }
  3082. #else
  3083. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3084. qdf_nbuf_t nbuf)
  3085. {
  3086. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3087. }
  3088. #endif
  3089. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3090. static inline
  3091. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3092. {
  3093. if (nbuf) {
  3094. qdf_prefetch(&nbuf->len);
  3095. qdf_prefetch(&nbuf->data);
  3096. }
  3097. }
  3098. #else
  3099. static inline
  3100. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3101. {
  3102. }
  3103. #endif
  3104. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3105. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3106. qdf_nbuf_t nbuf)
  3107. {
  3108. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3109. struct dp_vdev *vdev = NULL;
  3110. vdev = soc->vdev_id_map[vdev_id];
  3111. if (qdf_unlikely(!vdev))
  3112. return nbuf;
  3113. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3114. return nbuf;
  3115. }
  3116. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3117. qdf_nbuf_t nbuf,
  3118. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3119. {
  3120. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3121. }
  3122. #endif
  3123. #ifdef FEATURE_DIRECT_LINK
  3124. /**
  3125. * dp_vdev_tx_mark_to_fw() - Mark to_fw bit for the tx packet
  3126. * @nbuf: skb
  3127. * @vdev: DP vdev handle
  3128. *
  3129. * Return: None
  3130. */
  3131. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3132. {
  3133. if (qdf_unlikely(vdev->to_fw))
  3134. QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf) = 1;
  3135. }
  3136. #else
  3137. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3138. {
  3139. }
  3140. #endif
  3141. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3142. qdf_nbuf_t nbuf)
  3143. {
  3144. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3145. uint16_t peer_id = HTT_INVALID_PEER;
  3146. /*
  3147. * doing a memzero is causing additional function call overhead
  3148. * so doing static stack clearing
  3149. */
  3150. struct dp_tx_msdu_info_s msdu_info = {0};
  3151. struct dp_vdev *vdev = NULL;
  3152. qdf_nbuf_t end_nbuf = NULL;
  3153. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3154. return nbuf;
  3155. /*
  3156. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3157. * this in per packet path.
  3158. *
  3159. * As in this path vdev memory is already protected with netdev
  3160. * tx lock
  3161. */
  3162. vdev = soc->vdev_id_map[vdev_id];
  3163. if (qdf_unlikely(!vdev))
  3164. return nbuf;
  3165. dp_vdev_tx_mark_to_fw(nbuf, vdev);
  3166. /*
  3167. * Set Default Host TID value to invalid TID
  3168. * (TID override disabled)
  3169. */
  3170. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3171. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  3172. if (qdf_unlikely(vdev->mesh_vdev)) {
  3173. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3174. &msdu_info);
  3175. if (!nbuf_mesh) {
  3176. dp_verbose_debug("Extracting mesh metadata failed");
  3177. return nbuf;
  3178. }
  3179. nbuf = nbuf_mesh;
  3180. }
  3181. /*
  3182. * Get HW Queue to use for this frame.
  3183. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3184. * dedicated for data and 1 for command.
  3185. * "queue_id" maps to one hardware ring.
  3186. * With each ring, we also associate a unique Tx descriptor pool
  3187. * to minimize lock contention for these resources.
  3188. */
  3189. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3190. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3191. 1);
  3192. /*
  3193. * TCL H/W supports 2 DSCP-TID mapping tables.
  3194. * Table 1 - Default DSCP-TID mapping table
  3195. * Table 2 - 1 DSCP-TID override table
  3196. *
  3197. * If we need a different DSCP-TID mapping for this vap,
  3198. * call tid_classify to extract DSCP/ToS from frame and
  3199. * map to a TID and store in msdu_info. This is later used
  3200. * to fill in TCL Input descriptor (per-packet TID override).
  3201. */
  3202. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3203. /*
  3204. * Classify the frame and call corresponding
  3205. * "prepare" function which extracts the segment (TSO)
  3206. * and fragmentation information (for TSO , SG, ME, or Raw)
  3207. * into MSDU_INFO structure which is later used to fill
  3208. * SW and HW descriptors.
  3209. */
  3210. if (qdf_nbuf_is_tso(nbuf)) {
  3211. dp_verbose_debug("TSO frame %pK", vdev);
  3212. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3213. qdf_nbuf_len(nbuf));
  3214. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3215. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3216. qdf_nbuf_len(nbuf));
  3217. return nbuf;
  3218. }
  3219. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  3220. goto send_multiple;
  3221. }
  3222. /* SG */
  3223. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3224. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3225. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3226. return nbuf;
  3227. } else {
  3228. struct dp_tx_seg_info_s seg_info = {0};
  3229. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3230. goto send_single;
  3231. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3232. &msdu_info);
  3233. if (!nbuf)
  3234. return NULL;
  3235. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3236. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3237. qdf_nbuf_len(nbuf));
  3238. goto send_multiple;
  3239. }
  3240. }
  3241. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3242. return NULL;
  3243. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3244. return nbuf;
  3245. /* RAW */
  3246. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3247. struct dp_tx_seg_info_s seg_info = {0};
  3248. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3249. if (!nbuf)
  3250. return NULL;
  3251. dp_verbose_debug("Raw frame %pK", vdev);
  3252. goto send_multiple;
  3253. }
  3254. if (qdf_unlikely(vdev->nawds_enabled)) {
  3255. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3256. qdf_nbuf_data(nbuf);
  3257. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3258. uint16_t sa_peer_id = DP_INVALID_PEER;
  3259. if (!soc->ast_offload_support) {
  3260. struct dp_ast_entry *ast_entry = NULL;
  3261. qdf_spin_lock_bh(&soc->ast_lock);
  3262. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3263. (soc,
  3264. (uint8_t *)(eh->ether_shost),
  3265. vdev->pdev->pdev_id);
  3266. if (ast_entry)
  3267. sa_peer_id = ast_entry->peer_id;
  3268. qdf_spin_unlock_bh(&soc->ast_lock);
  3269. }
  3270. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3271. sa_peer_id);
  3272. }
  3273. peer_id = DP_INVALID_PEER;
  3274. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3275. 1, qdf_nbuf_len(nbuf));
  3276. }
  3277. send_single:
  3278. /* Single linear frame */
  3279. /*
  3280. * If nbuf is a simple linear frame, use send_single function to
  3281. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3282. * SRNG. There is no need to setup a MSDU extension descriptor.
  3283. */
  3284. dp_tx_prefetch_nbuf_data(nbuf);
  3285. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3286. peer_id, end_nbuf);
  3287. return nbuf;
  3288. send_multiple:
  3289. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3290. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3291. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3292. return nbuf;
  3293. }
  3294. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3295. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3296. {
  3297. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3298. struct dp_vdev *vdev = NULL;
  3299. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3300. return nbuf;
  3301. /*
  3302. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3303. * this in per packet path.
  3304. *
  3305. * As in this path vdev memory is already protected with netdev
  3306. * tx lock
  3307. */
  3308. vdev = soc->vdev_id_map[vdev_id];
  3309. if (qdf_unlikely(!vdev))
  3310. return nbuf;
  3311. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3312. == QDF_STATUS_E_FAILURE)) {
  3313. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3314. return nbuf;
  3315. }
  3316. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3317. }
  3318. #ifdef UMAC_SUPPORT_PROXY_ARP
  3319. /**
  3320. * dp_tx_proxy_arp() - Tx proxy arp handler
  3321. * @vdev: datapath vdev handle
  3322. * @nbuf: sk buffer
  3323. *
  3324. * Return: status
  3325. */
  3326. static inline
  3327. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3328. {
  3329. if (vdev->osif_proxy_arp)
  3330. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3331. /*
  3332. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3333. * osif_proxy_arp has a valid function pointer assigned
  3334. * to it
  3335. */
  3336. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3337. return QDF_STATUS_NOT_INITIALIZED;
  3338. }
  3339. #else
  3340. static inline
  3341. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3342. {
  3343. return QDF_STATUS_SUCCESS;
  3344. }
  3345. #endif
  3346. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  3347. !defined(CONFIG_MLO_SINGLE_DEV)
  3348. #ifdef WLAN_MCAST_MLO
  3349. static bool
  3350. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3351. struct dp_tx_desc_s *tx_desc,
  3352. qdf_nbuf_t nbuf,
  3353. uint8_t reinject_reason)
  3354. {
  3355. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3356. if (soc->arch_ops.dp_tx_mcast_handler)
  3357. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3358. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3359. return true;
  3360. }
  3361. return false;
  3362. }
  3363. #else /* WLAN_MCAST_MLO */
  3364. static inline bool
  3365. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3366. struct dp_tx_desc_s *tx_desc,
  3367. qdf_nbuf_t nbuf,
  3368. uint8_t reinject_reason)
  3369. {
  3370. return false;
  3371. }
  3372. #endif /* WLAN_MCAST_MLO */
  3373. #else
  3374. static inline bool
  3375. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3376. struct dp_tx_desc_s *tx_desc,
  3377. qdf_nbuf_t nbuf,
  3378. uint8_t reinject_reason)
  3379. {
  3380. return false;
  3381. }
  3382. #endif
  3383. void dp_tx_reinject_handler(struct dp_soc *soc,
  3384. struct dp_vdev *vdev,
  3385. struct dp_tx_desc_s *tx_desc,
  3386. uint8_t *status,
  3387. uint8_t reinject_reason)
  3388. {
  3389. struct dp_peer *peer = NULL;
  3390. uint32_t peer_id = HTT_INVALID_PEER;
  3391. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3392. qdf_nbuf_t nbuf_copy = NULL;
  3393. struct dp_tx_msdu_info_s msdu_info;
  3394. #ifdef WDS_VENDOR_EXTENSION
  3395. int is_mcast = 0, is_ucast = 0;
  3396. int num_peers_3addr = 0;
  3397. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3398. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3399. #endif
  3400. struct dp_txrx_peer *txrx_peer;
  3401. qdf_assert(vdev);
  3402. dp_tx_debug("Tx reinject path");
  3403. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3404. qdf_nbuf_len(tx_desc->nbuf));
  3405. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3406. return;
  3407. #ifdef WDS_VENDOR_EXTENSION
  3408. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3409. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3410. } else {
  3411. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3412. }
  3413. is_ucast = !is_mcast;
  3414. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3415. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3416. txrx_peer = dp_get_txrx_peer(peer);
  3417. if (!txrx_peer || txrx_peer->bss_peer)
  3418. continue;
  3419. /* Detect wds peers that use 3-addr framing for mcast.
  3420. * if there are any, the bss_peer is used to send the
  3421. * the mcast frame using 3-addr format. all wds enabled
  3422. * peers that use 4-addr framing for mcast frames will
  3423. * be duplicated and sent as 4-addr frames below.
  3424. */
  3425. if (!txrx_peer->wds_enabled ||
  3426. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3427. num_peers_3addr = 1;
  3428. break;
  3429. }
  3430. }
  3431. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3432. #endif
  3433. if (qdf_unlikely(vdev->mesh_vdev)) {
  3434. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3435. } else {
  3436. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3437. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3438. txrx_peer = dp_get_txrx_peer(peer);
  3439. if (!txrx_peer)
  3440. continue;
  3441. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3442. #ifdef WDS_VENDOR_EXTENSION
  3443. /*
  3444. * . if 3-addr STA, then send on BSS Peer
  3445. * . if Peer WDS enabled and accept 4-addr mcast,
  3446. * send mcast on that peer only
  3447. * . if Peer WDS enabled and accept 4-addr ucast,
  3448. * send ucast on that peer only
  3449. */
  3450. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3451. (txrx_peer->wds_enabled &&
  3452. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3453. (is_ucast &&
  3454. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3455. #else
  3456. (txrx_peer->bss_peer &&
  3457. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3458. #endif
  3459. peer_id = DP_INVALID_PEER;
  3460. nbuf_copy = qdf_nbuf_copy(nbuf);
  3461. if (!nbuf_copy) {
  3462. dp_tx_debug("nbuf copy failed");
  3463. break;
  3464. }
  3465. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3466. dp_tx_get_queue(vdev, nbuf,
  3467. &msdu_info.tx_queue);
  3468. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3469. nbuf_copy,
  3470. &msdu_info,
  3471. peer_id,
  3472. NULL);
  3473. if (nbuf_copy) {
  3474. dp_tx_debug("pkt send failed");
  3475. qdf_nbuf_free(nbuf_copy);
  3476. }
  3477. }
  3478. }
  3479. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3480. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3481. QDF_DMA_TO_DEVICE, nbuf->len);
  3482. qdf_nbuf_free(nbuf);
  3483. }
  3484. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3485. }
  3486. void dp_tx_inspect_handler(struct dp_soc *soc,
  3487. struct dp_vdev *vdev,
  3488. struct dp_tx_desc_s *tx_desc,
  3489. uint8_t *status)
  3490. {
  3491. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3492. "%s Tx inspect path",
  3493. __func__);
  3494. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3495. qdf_nbuf_len(tx_desc->nbuf));
  3496. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3497. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3498. }
  3499. #ifdef MESH_MODE_SUPPORT
  3500. /**
  3501. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3502. * in mesh meta header
  3503. * @tx_desc: software descriptor head pointer
  3504. * @ts: pointer to tx completion stats
  3505. * Return: none
  3506. */
  3507. static
  3508. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3509. struct hal_tx_completion_status *ts)
  3510. {
  3511. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3512. if (!tx_desc->msdu_ext_desc) {
  3513. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3514. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3515. "netbuf %pK offset %d",
  3516. netbuf, tx_desc->pkt_offset);
  3517. return;
  3518. }
  3519. }
  3520. }
  3521. #else
  3522. static
  3523. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3524. struct hal_tx_completion_status *ts)
  3525. {
  3526. }
  3527. #endif
  3528. #ifdef CONFIG_SAWF
  3529. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3530. struct dp_vdev *vdev,
  3531. struct dp_txrx_peer *txrx_peer,
  3532. struct dp_tx_desc_s *tx_desc,
  3533. struct hal_tx_completion_status *ts,
  3534. uint8_t tid)
  3535. {
  3536. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3537. ts, tid);
  3538. }
  3539. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3540. uint32_t nw_delay,
  3541. uint32_t sw_delay,
  3542. uint32_t hw_delay)
  3543. {
  3544. dp_peer_tid_delay_avg(tx_delay,
  3545. nw_delay,
  3546. sw_delay,
  3547. hw_delay);
  3548. }
  3549. #else
  3550. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3551. struct dp_vdev *vdev,
  3552. struct dp_txrx_peer *txrx_peer,
  3553. struct dp_tx_desc_s *tx_desc,
  3554. struct hal_tx_completion_status *ts,
  3555. uint8_t tid)
  3556. {
  3557. }
  3558. static inline void
  3559. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3560. uint32_t nw_delay, uint32_t sw_delay,
  3561. uint32_t hw_delay)
  3562. {
  3563. }
  3564. #endif
  3565. #ifdef QCA_PEER_EXT_STATS
  3566. #ifdef WLAN_CONFIG_TX_DELAY
  3567. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3568. struct dp_tx_desc_s *tx_desc,
  3569. struct hal_tx_completion_status *ts,
  3570. struct dp_vdev *vdev)
  3571. {
  3572. struct dp_soc *soc = vdev->pdev->soc;
  3573. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3574. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3575. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3576. if (!ts->valid)
  3577. return;
  3578. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3579. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3580. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3581. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3582. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3583. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3584. &fwhw_transmit_delay))
  3585. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3586. fwhw_transmit_delay);
  3587. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3588. fwhw_transmit_delay);
  3589. }
  3590. #else
  3591. /**
  3592. * dp_tx_compute_tid_delay() - Compute per TID delay
  3593. * @stats: Per TID delay stats
  3594. * @tx_desc: Software Tx descriptor
  3595. * @ts: Tx completion status
  3596. * @vdev: vdev
  3597. *
  3598. * Compute the software enqueue and hw enqueue delays and
  3599. * update the respective histograms
  3600. *
  3601. * Return: void
  3602. */
  3603. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3604. struct dp_tx_desc_s *tx_desc,
  3605. struct hal_tx_completion_status *ts,
  3606. struct dp_vdev *vdev)
  3607. {
  3608. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3609. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3610. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3611. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3612. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3613. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3614. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3615. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3616. timestamp_hw_enqueue);
  3617. /*
  3618. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3619. */
  3620. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3621. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3622. }
  3623. #endif
  3624. /**
  3625. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3626. * @txrx_peer: DP peer context
  3627. * @tx_desc: Tx software descriptor
  3628. * @ts: Tx completion status
  3629. * @ring_id: Rx CPU context ID/CPU_ID
  3630. *
  3631. * Update the peer extended stats. These are enhanced other
  3632. * delay stats per msdu level.
  3633. *
  3634. * Return: void
  3635. */
  3636. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3637. struct dp_tx_desc_s *tx_desc,
  3638. struct hal_tx_completion_status *ts,
  3639. uint8_t ring_id)
  3640. {
  3641. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3642. struct dp_soc *soc = NULL;
  3643. struct dp_peer_delay_stats *delay_stats = NULL;
  3644. uint8_t tid;
  3645. soc = pdev->soc;
  3646. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3647. return;
  3648. if (!txrx_peer->delay_stats)
  3649. return;
  3650. tid = ts->tid;
  3651. delay_stats = txrx_peer->delay_stats;
  3652. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3653. /*
  3654. * For non-TID packets use the TID 9
  3655. */
  3656. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3657. tid = CDP_MAX_DATA_TIDS - 1;
  3658. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3659. tx_desc, ts, txrx_peer->vdev);
  3660. }
  3661. #else
  3662. static inline
  3663. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3664. struct dp_tx_desc_s *tx_desc,
  3665. struct hal_tx_completion_status *ts,
  3666. uint8_t ring_id)
  3667. {
  3668. }
  3669. #endif
  3670. #ifdef WLAN_PEER_JITTER
  3671. /**
  3672. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3673. * @curr_delay: Current delay
  3674. * @prev_delay: Previous delay
  3675. * @avg_jitter: Average Jitter
  3676. * Return: Newly Computed Average Jitter
  3677. */
  3678. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3679. uint32_t prev_delay,
  3680. uint32_t avg_jitter)
  3681. {
  3682. uint32_t curr_jitter;
  3683. int32_t jitter_diff;
  3684. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3685. if (!avg_jitter)
  3686. return curr_jitter;
  3687. jitter_diff = curr_jitter - avg_jitter;
  3688. if (jitter_diff < 0)
  3689. avg_jitter = avg_jitter -
  3690. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3691. else
  3692. avg_jitter = avg_jitter +
  3693. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3694. return avg_jitter;
  3695. }
  3696. /**
  3697. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3698. * @curr_delay: Current delay
  3699. * @avg_delay: Average delay
  3700. * Return: Newly Computed Average Delay
  3701. */
  3702. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3703. uint32_t avg_delay)
  3704. {
  3705. int32_t delay_diff;
  3706. if (!avg_delay)
  3707. return curr_delay;
  3708. delay_diff = curr_delay - avg_delay;
  3709. if (delay_diff < 0)
  3710. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3711. DP_AVG_DELAY_WEIGHT_DENOM);
  3712. else
  3713. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3714. DP_AVG_DELAY_WEIGHT_DENOM);
  3715. return avg_delay;
  3716. }
  3717. #ifdef WLAN_CONFIG_TX_DELAY
  3718. /**
  3719. * dp_tx_compute_cur_delay() - get the current delay
  3720. * @soc: soc handle
  3721. * @vdev: vdev structure for data path state
  3722. * @ts: Tx completion status
  3723. * @curr_delay: current delay
  3724. * @tx_desc: tx descriptor
  3725. * Return: void
  3726. */
  3727. static
  3728. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3729. struct dp_vdev *vdev,
  3730. struct hal_tx_completion_status *ts,
  3731. uint32_t *curr_delay,
  3732. struct dp_tx_desc_s *tx_desc)
  3733. {
  3734. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3735. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3736. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3737. curr_delay);
  3738. return status;
  3739. }
  3740. #else
  3741. static
  3742. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3743. struct dp_vdev *vdev,
  3744. struct hal_tx_completion_status *ts,
  3745. uint32_t *curr_delay,
  3746. struct dp_tx_desc_s *tx_desc)
  3747. {
  3748. int64_t current_timestamp, timestamp_hw_enqueue;
  3749. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3750. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3751. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3752. return QDF_STATUS_SUCCESS;
  3753. }
  3754. #endif
  3755. /**
  3756. * dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3757. * @jitter: per tid per ring jitter stats
  3758. * @ts: Tx completion status
  3759. * @vdev: vdev structure for data path state
  3760. * @tx_desc: tx descriptor
  3761. * Return: void
  3762. */
  3763. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3764. struct hal_tx_completion_status *ts,
  3765. struct dp_vdev *vdev,
  3766. struct dp_tx_desc_s *tx_desc)
  3767. {
  3768. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3769. struct dp_soc *soc = vdev->pdev->soc;
  3770. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3771. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3772. jitter->tx_drop += 1;
  3773. return;
  3774. }
  3775. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3776. tx_desc);
  3777. if (QDF_IS_STATUS_SUCCESS(status)) {
  3778. avg_delay = jitter->tx_avg_delay;
  3779. avg_jitter = jitter->tx_avg_jitter;
  3780. prev_delay = jitter->tx_prev_delay;
  3781. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3782. prev_delay,
  3783. avg_jitter);
  3784. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3785. jitter->tx_avg_delay = avg_delay;
  3786. jitter->tx_avg_jitter = avg_jitter;
  3787. jitter->tx_prev_delay = curr_delay;
  3788. jitter->tx_total_success += 1;
  3789. } else if (status == QDF_STATUS_E_FAILURE) {
  3790. jitter->tx_avg_err += 1;
  3791. }
  3792. }
  3793. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3794. * @txrx_peer: DP peer context
  3795. * @tx_desc: Tx software descriptor
  3796. * @ts: Tx completion status
  3797. * @ring_id: Rx CPU context ID/CPU_ID
  3798. * Return: void
  3799. */
  3800. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3801. struct dp_tx_desc_s *tx_desc,
  3802. struct hal_tx_completion_status *ts,
  3803. uint8_t ring_id)
  3804. {
  3805. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3806. struct dp_soc *soc = pdev->soc;
  3807. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3808. uint8_t tid;
  3809. struct cdp_peer_tid_stats *rx_tid = NULL;
  3810. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3811. return;
  3812. tid = ts->tid;
  3813. jitter_stats = txrx_peer->jitter_stats;
  3814. qdf_assert_always(jitter_stats);
  3815. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3816. /*
  3817. * For non-TID packets use the TID 9
  3818. */
  3819. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3820. tid = CDP_MAX_DATA_TIDS - 1;
  3821. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3822. dp_tx_compute_tid_jitter(rx_tid,
  3823. ts, txrx_peer->vdev, tx_desc);
  3824. }
  3825. #else
  3826. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3827. struct dp_tx_desc_s *tx_desc,
  3828. struct hal_tx_completion_status *ts,
  3829. uint8_t ring_id)
  3830. {
  3831. }
  3832. #endif
  3833. #ifdef HW_TX_DELAY_STATS_ENABLE
  3834. /**
  3835. * dp_update_tx_delay_stats() - update the delay stats
  3836. * @vdev: vdev handle
  3837. * @delay: delay in ms or us based on the flag delay_in_us
  3838. * @tid: tid value
  3839. * @mode: type of tx delay mode
  3840. * @ring_id: ring number
  3841. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3842. *
  3843. * Return: none
  3844. */
  3845. static inline
  3846. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3847. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3848. {
  3849. struct cdp_tid_tx_stats *tstats =
  3850. &vdev->stats.tid_tx_stats[ring_id][tid];
  3851. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3852. delay_in_us);
  3853. }
  3854. #else
  3855. static inline
  3856. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3857. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3858. {
  3859. struct cdp_tid_tx_stats *tstats =
  3860. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3861. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3862. delay_in_us);
  3863. }
  3864. #endif
  3865. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3866. uint8_t tid, uint8_t ring_id)
  3867. {
  3868. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3869. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3870. uint32_t fwhw_transmit_delay_us;
  3871. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3872. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3873. return;
  3874. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3875. fwhw_transmit_delay_us =
  3876. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3877. qdf_ktime_to_us(tx_desc->timestamp);
  3878. /*
  3879. * Delay between packet enqueued to HW and Tx completion in us
  3880. */
  3881. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3882. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3883. ring_id, true);
  3884. /*
  3885. * For MCL, only enqueue to completion delay is required
  3886. * so return if the vdev flag is enabled.
  3887. */
  3888. return;
  3889. }
  3890. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3891. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3892. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3893. timestamp_hw_enqueue);
  3894. if (!timestamp_hw_enqueue)
  3895. return;
  3896. /*
  3897. * Delay between packet enqueued to HW and Tx completion in ms
  3898. */
  3899. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3900. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3901. false);
  3902. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3903. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3904. interframe_delay = (uint32_t)(timestamp_ingress -
  3905. vdev->prev_tx_enq_tstamp);
  3906. /*
  3907. * Delay in software enqueue
  3908. */
  3909. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3910. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3911. false);
  3912. /*
  3913. * Update interframe delay stats calculated at hardstart receive point.
  3914. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3915. * interframe delay will not be calculate correctly for 1st frame.
  3916. * On the other side, this will help in avoiding extra per packet check
  3917. * of !vdev->prev_tx_enq_tstamp.
  3918. */
  3919. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3920. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3921. false);
  3922. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3923. }
  3924. #ifdef DISABLE_DP_STATS
  3925. static
  3926. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3927. struct dp_txrx_peer *txrx_peer,
  3928. uint8_t link_id)
  3929. {
  3930. }
  3931. #else
  3932. static inline void
  3933. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer,
  3934. uint8_t link_id)
  3935. {
  3936. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3937. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3938. if (subtype != QDF_PROTO_INVALID)
  3939. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3940. 1, link_id);
  3941. }
  3942. #endif
  3943. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3944. #ifdef DP_PEER_EXTENDED_API
  3945. static inline uint8_t
  3946. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3947. {
  3948. return txrx_peer->mpdu_retry_threshold;
  3949. }
  3950. #else
  3951. static inline uint8_t
  3952. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3953. {
  3954. return 0;
  3955. }
  3956. #endif
  3957. /**
  3958. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3959. *
  3960. * @ts: Tx compltion status
  3961. * @txrx_peer: datapath txrx_peer handle
  3962. * @link_id: Link id
  3963. *
  3964. * Return: void
  3965. */
  3966. static inline void
  3967. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3968. struct dp_txrx_peer *txrx_peer, uint8_t link_id)
  3969. {
  3970. uint8_t mcs, pkt_type, dst_mcs_idx;
  3971. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  3972. mcs = ts->mcs;
  3973. pkt_type = ts->pkt_type;
  3974. /* do HW to SW pkt type conversion */
  3975. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3976. hal_2_dp_pkt_type_map[pkt_type]);
  3977. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3978. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3979. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3980. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3981. 1, link_id);
  3982. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1, link_id);
  3983. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1, link_id);
  3984. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi,
  3985. link_id);
  3986. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3987. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1,
  3988. link_id);
  3989. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc, link_id);
  3990. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc, link_id);
  3991. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1,
  3992. link_id);
  3993. if (ts->first_msdu) {
  3994. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3995. ts->transmit_cnt > 1, link_id);
  3996. if (!retry_threshold)
  3997. return;
  3998. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3999. qdf_do_div(ts->transmit_cnt,
  4000. retry_threshold),
  4001. ts->transmit_cnt > retry_threshold,
  4002. link_id);
  4003. }
  4004. }
  4005. #else
  4006. static inline void
  4007. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4008. struct dp_txrx_peer *txrx_peer, uint8_t link_id)
  4009. {
  4010. }
  4011. #endif
  4012. #if defined(WLAN_FEATURE_11BE_MLO) && defined(QCA_ENHANCED_STATS_SUPPORT)
  4013. static inline uint8_t
  4014. dp_tx_get_link_id_from_ppdu_id(struct dp_soc *soc,
  4015. struct hal_tx_completion_status *ts,
  4016. struct dp_txrx_peer *txrx_peer,
  4017. struct dp_vdev *vdev)
  4018. {
  4019. uint8_t hw_link_id = 0;
  4020. uint32_t ppdu_id;
  4021. uint8_t link_id_offset, link_id_bits;
  4022. if (!txrx_peer->is_mld_peer || !vdev->pdev->link_peer_stats)
  4023. return 0;
  4024. link_id_offset = soc->link_id_offset;
  4025. link_id_bits = soc->link_id_bits;
  4026. ppdu_id = ts->ppdu_id;
  4027. hw_link_id = ((DP_GET_HW_LINK_ID_FRM_PPDU_ID(ppdu_id, link_id_offset,
  4028. link_id_bits)) + 1);
  4029. if (hw_link_id > DP_MAX_MLO_LINKS) {
  4030. hw_link_id = 0;
  4031. DP_PEER_PER_PKT_STATS_INC(
  4032. txrx_peer,
  4033. tx.inval_link_id_pkt_cnt, 1, hw_link_id);
  4034. }
  4035. return hw_link_id;
  4036. }
  4037. #else
  4038. static inline uint8_t
  4039. dp_tx_get_link_id_from_ppdu_id(struct dp_soc *soc,
  4040. struct hal_tx_completion_status *ts,
  4041. struct dp_txrx_peer *txrx_peer,
  4042. struct dp_vdev *vdev)
  4043. {
  4044. return 0;
  4045. }
  4046. #endif
  4047. /**
  4048. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4049. * per wbm ring
  4050. *
  4051. * @tx_desc: software descriptor head pointer
  4052. * @ts: Tx completion status
  4053. * @txrx_peer: peer handle
  4054. * @ring_id: ring number
  4055. * @link_id: Link id
  4056. *
  4057. * Return: None
  4058. */
  4059. static inline void
  4060. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4061. struct hal_tx_completion_status *ts,
  4062. struct dp_txrx_peer *txrx_peer, uint8_t ring_id,
  4063. uint8_t link_id)
  4064. {
  4065. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4066. uint8_t tid = ts->tid;
  4067. uint32_t length;
  4068. struct cdp_tid_tx_stats *tid_stats;
  4069. if (!pdev)
  4070. return;
  4071. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4072. tid = CDP_MAX_DATA_TIDS - 1;
  4073. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4074. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4075. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4076. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1,
  4077. link_id);
  4078. return;
  4079. }
  4080. length = qdf_nbuf_len(tx_desc->nbuf);
  4081. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4082. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4083. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4084. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4085. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4086. tid_stats->tqm_status_cnt[ts->status]++;
  4087. }
  4088. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4089. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4090. ts->transmit_cnt > 1, link_id);
  4091. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4092. 1, ts->transmit_cnt > 2, link_id);
  4093. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma,
  4094. link_id);
  4095. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4096. ts->msdu_part_of_amsdu, link_id);
  4097. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4098. !ts->msdu_part_of_amsdu, link_id);
  4099. txrx_peer->stats[link_id].per_pkt_stats.tx.last_tx_ts =
  4100. qdf_system_ticks();
  4101. dp_tx_update_peer_extd_stats(ts, txrx_peer, link_id);
  4102. return;
  4103. }
  4104. /*
  4105. * tx_failed is ideally supposed to be updated from HTT ppdu
  4106. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4107. * hw limitation there are no completions for failed cases.
  4108. * Hence updating tx_failed from data path. Please note that
  4109. * if tx_failed is fixed to be from ppdu, then this has to be
  4110. * removed
  4111. */
  4112. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4113. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4114. ts->transmit_cnt > DP_RETRY_COUNT,
  4115. link_id);
  4116. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer, link_id);
  4117. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4118. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1,
  4119. link_id);
  4120. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4121. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4122. length, link_id);
  4123. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4124. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1,
  4125. link_id);
  4126. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4127. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1,
  4128. link_id);
  4129. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4130. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1,
  4131. link_id);
  4132. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4133. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1,
  4134. link_id);
  4135. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4136. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1,
  4137. link_id);
  4138. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4139. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4140. tx.dropped.fw_rem_queue_disable, 1,
  4141. link_id);
  4142. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4143. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4144. tx.dropped.fw_rem_no_match, 1,
  4145. link_id);
  4146. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4147. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4148. tx.dropped.drop_threshold, 1,
  4149. link_id);
  4150. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4151. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4152. tx.dropped.drop_link_desc_na, 1,
  4153. link_id);
  4154. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4155. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4156. tx.dropped.invalid_drop, 1,
  4157. link_id);
  4158. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4159. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4160. tx.dropped.mcast_vdev_drop, 1,
  4161. link_id);
  4162. } else {
  4163. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1,
  4164. link_id);
  4165. }
  4166. }
  4167. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4168. /**
  4169. * dp_tx_flow_pool_lock() - take flow pool lock
  4170. * @soc: core txrx main context
  4171. * @tx_desc: tx desc
  4172. *
  4173. * Return: None
  4174. */
  4175. static inline
  4176. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4177. struct dp_tx_desc_s *tx_desc)
  4178. {
  4179. struct dp_tx_desc_pool_s *pool;
  4180. uint8_t desc_pool_id;
  4181. desc_pool_id = tx_desc->pool_id;
  4182. pool = &soc->tx_desc[desc_pool_id];
  4183. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4184. }
  4185. /**
  4186. * dp_tx_flow_pool_unlock() - release flow pool lock
  4187. * @soc: core txrx main context
  4188. * @tx_desc: tx desc
  4189. *
  4190. * Return: None
  4191. */
  4192. static inline
  4193. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4194. struct dp_tx_desc_s *tx_desc)
  4195. {
  4196. struct dp_tx_desc_pool_s *pool;
  4197. uint8_t desc_pool_id;
  4198. desc_pool_id = tx_desc->pool_id;
  4199. pool = &soc->tx_desc[desc_pool_id];
  4200. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4201. }
  4202. #else
  4203. static inline
  4204. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4205. {
  4206. }
  4207. static inline
  4208. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4209. {
  4210. }
  4211. #endif
  4212. /**
  4213. * dp_tx_notify_completion() - Notify tx completion for this desc
  4214. * @soc: core txrx main context
  4215. * @vdev: datapath vdev handle
  4216. * @tx_desc: tx desc
  4217. * @netbuf: buffer
  4218. * @status: tx status
  4219. *
  4220. * Return: none
  4221. */
  4222. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4223. struct dp_vdev *vdev,
  4224. struct dp_tx_desc_s *tx_desc,
  4225. qdf_nbuf_t netbuf,
  4226. uint8_t status)
  4227. {
  4228. void *osif_dev;
  4229. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4230. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4231. qdf_assert(tx_desc);
  4232. if (!vdev ||
  4233. !vdev->osif_vdev) {
  4234. return;
  4235. }
  4236. osif_dev = vdev->osif_vdev;
  4237. tx_compl_cbk = vdev->tx_comp;
  4238. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4239. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4240. if (tx_compl_cbk)
  4241. tx_compl_cbk(netbuf, osif_dev, flag);
  4242. }
  4243. /**
  4244. * dp_tx_sojourn_stats_process() - Collect sojourn stats
  4245. * @pdev: pdev handle
  4246. * @txrx_peer: DP peer context
  4247. * @tid: tid value
  4248. * @txdesc_ts: timestamp from txdesc
  4249. * @ppdu_id: ppdu id
  4250. * @link_id: link id
  4251. *
  4252. * Return: none
  4253. */
  4254. #ifdef FEATURE_PERPKT_INFO
  4255. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4256. struct dp_txrx_peer *txrx_peer,
  4257. uint8_t tid,
  4258. uint64_t txdesc_ts,
  4259. uint32_t ppdu_id,
  4260. uint8_t link_id)
  4261. {
  4262. uint64_t delta_ms;
  4263. struct cdp_tx_sojourn_stats *sojourn_stats;
  4264. struct dp_peer *primary_link_peer = NULL;
  4265. struct dp_soc *link_peer_soc = NULL;
  4266. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4267. return;
  4268. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4269. tid >= CDP_DATA_TID_MAX))
  4270. return;
  4271. if (qdf_unlikely(!pdev->sojourn_buf))
  4272. return;
  4273. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4274. txrx_peer->peer_id,
  4275. DP_MOD_ID_TX_COMP);
  4276. if (qdf_unlikely(!primary_link_peer))
  4277. return;
  4278. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4279. qdf_nbuf_data(pdev->sojourn_buf);
  4280. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4281. sojourn_stats->cookie = (void *)
  4282. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4283. primary_link_peer);
  4284. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4285. txdesc_ts;
  4286. qdf_ewma_tx_lag_add(&txrx_peer->stats[link_id].per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4287. delta_ms);
  4288. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4289. sojourn_stats->num_msdus[tid] = 1;
  4290. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4291. txrx_peer->stats[link_id].
  4292. per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4293. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4294. pdev->sojourn_buf, HTT_INVALID_PEER,
  4295. WDI_NO_VAL, pdev->pdev_id);
  4296. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4297. sojourn_stats->num_msdus[tid] = 0;
  4298. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4299. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4300. }
  4301. #else
  4302. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4303. struct dp_txrx_peer *txrx_peer,
  4304. uint8_t tid,
  4305. uint64_t txdesc_ts,
  4306. uint32_t ppdu_id)
  4307. {
  4308. }
  4309. #endif
  4310. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4311. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4312. struct dp_tx_desc_s *desc,
  4313. struct hal_tx_completion_status *ts)
  4314. {
  4315. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4316. desc, ts->peer_id,
  4317. WDI_NO_VAL, desc->pdev->pdev_id);
  4318. }
  4319. #endif
  4320. void
  4321. dp_tx_comp_process_desc(struct dp_soc *soc,
  4322. struct dp_tx_desc_s *desc,
  4323. struct hal_tx_completion_status *ts,
  4324. struct dp_txrx_peer *txrx_peer)
  4325. {
  4326. uint64_t time_latency = 0;
  4327. uint16_t peer_id = DP_INVALID_PEER_ID;
  4328. /*
  4329. * m_copy/tx_capture modes are not supported for
  4330. * scatter gather packets
  4331. */
  4332. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4333. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4334. qdf_ktime_to_ms(desc->timestamp));
  4335. }
  4336. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4337. if (dp_tx_pkt_tracepoints_enabled())
  4338. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4339. desc->msdu_ext_desc ?
  4340. desc->msdu_ext_desc->tso_desc : NULL,
  4341. qdf_ktime_to_ms(desc->timestamp));
  4342. if (!(desc->msdu_ext_desc)) {
  4343. dp_tx_enh_unmap(soc, desc);
  4344. if (txrx_peer)
  4345. peer_id = txrx_peer->peer_id;
  4346. if (QDF_STATUS_SUCCESS ==
  4347. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4348. return;
  4349. }
  4350. if (QDF_STATUS_SUCCESS ==
  4351. dp_get_completion_indication_for_stack(soc,
  4352. desc->pdev,
  4353. txrx_peer, ts,
  4354. desc->nbuf,
  4355. time_latency)) {
  4356. dp_send_completion_to_stack(soc,
  4357. desc->pdev,
  4358. ts->peer_id,
  4359. ts->ppdu_id,
  4360. desc->nbuf);
  4361. return;
  4362. }
  4363. }
  4364. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4365. dp_tx_comp_free_buf(soc, desc, false);
  4366. }
  4367. #ifdef DISABLE_DP_STATS
  4368. /**
  4369. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4370. * @soc: core txrx main context
  4371. * @vdev: virtual device instance
  4372. * @tx_desc: tx desc
  4373. * @status: tx status
  4374. *
  4375. * Return: none
  4376. */
  4377. static inline
  4378. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4379. struct dp_vdev *vdev,
  4380. struct dp_tx_desc_s *tx_desc,
  4381. uint8_t status)
  4382. {
  4383. }
  4384. #else
  4385. static inline
  4386. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4387. struct dp_vdev *vdev,
  4388. struct dp_tx_desc_s *tx_desc,
  4389. uint8_t status)
  4390. {
  4391. void *osif_dev;
  4392. ol_txrx_stats_rx_fp stats_cbk;
  4393. uint8_t pkt_type;
  4394. qdf_assert(tx_desc);
  4395. if (!vdev ||
  4396. !vdev->osif_vdev ||
  4397. !vdev->stats_cb)
  4398. return;
  4399. osif_dev = vdev->osif_vdev;
  4400. stats_cbk = vdev->stats_cb;
  4401. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4402. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4403. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4404. &pkt_type);
  4405. }
  4406. #endif
  4407. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4408. /* Mask for bit29 ~ bit31 */
  4409. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4410. /* Timestamp value (unit us) if bit29 is set */
  4411. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4412. /**
  4413. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4414. * @ack_ts: OTA ack timestamp, unit us.
  4415. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4416. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4417. *
  4418. * this function will restore the bit29 ~ bit31 3 bits value for
  4419. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4420. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4421. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4422. *
  4423. * Return: the adjusted buffer_timestamp value
  4424. */
  4425. static inline
  4426. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4427. uint32_t enqueue_ts,
  4428. uint32_t base_delta_ts)
  4429. {
  4430. uint32_t ack_buffer_ts;
  4431. uint32_t ack_buffer_ts_bit29_31;
  4432. uint32_t adjusted_enqueue_ts;
  4433. /* corresponding buffer_timestamp value when receive OTA Ack */
  4434. ack_buffer_ts = ack_ts - base_delta_ts;
  4435. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4436. /* restore the bit29 ~ bit31 value */
  4437. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4438. /*
  4439. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4440. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4441. * should not be marked, otherwise extra 0x20000000 us is added to
  4442. * enqueue_ts.
  4443. */
  4444. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4445. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4446. return adjusted_enqueue_ts;
  4447. }
  4448. QDF_STATUS
  4449. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4450. uint32_t delta_tsf,
  4451. uint32_t *delay_us)
  4452. {
  4453. uint32_t buffer_ts;
  4454. uint32_t delay;
  4455. if (!delay_us)
  4456. return QDF_STATUS_E_INVAL;
  4457. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4458. if (!ts->valid)
  4459. return QDF_STATUS_E_INVAL;
  4460. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4461. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4462. * valid up to 29 bits.
  4463. */
  4464. buffer_ts = ts->buffer_timestamp << 10;
  4465. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4466. buffer_ts, delta_tsf);
  4467. delay = ts->tsf - buffer_ts - delta_tsf;
  4468. if (qdf_unlikely(delay & 0x80000000)) {
  4469. dp_err_rl("delay = 0x%x (-ve)\n"
  4470. "release_src = %d\n"
  4471. "ppdu_id = 0x%x\n"
  4472. "peer_id = 0x%x\n"
  4473. "tid = 0x%x\n"
  4474. "release_reason = %d\n"
  4475. "tsf = %u (0x%x)\n"
  4476. "buffer_timestamp = %u (0x%x)\n"
  4477. "delta_tsf = %u (0x%x)\n",
  4478. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4479. ts->tid, ts->status, ts->tsf, ts->tsf,
  4480. ts->buffer_timestamp, ts->buffer_timestamp,
  4481. delta_tsf, delta_tsf);
  4482. delay = 0;
  4483. goto end;
  4484. }
  4485. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4486. if (delay > 0x1000000) {
  4487. dp_info_rl("----------------------\n"
  4488. "Tx completion status:\n"
  4489. "----------------------\n"
  4490. "release_src = %d\n"
  4491. "ppdu_id = 0x%x\n"
  4492. "release_reason = %d\n"
  4493. "tsf = %u (0x%x)\n"
  4494. "buffer_timestamp = %u (0x%x)\n"
  4495. "delta_tsf = %u (0x%x)\n",
  4496. ts->release_src, ts->ppdu_id, ts->status,
  4497. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4498. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4499. return QDF_STATUS_E_FAILURE;
  4500. }
  4501. end:
  4502. *delay_us = delay;
  4503. return QDF_STATUS_SUCCESS;
  4504. }
  4505. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4506. uint32_t delta_tsf)
  4507. {
  4508. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4509. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4510. DP_MOD_ID_CDP);
  4511. if (!vdev) {
  4512. dp_err_rl("vdev %d does not exist", vdev_id);
  4513. return;
  4514. }
  4515. vdev->delta_tsf = delta_tsf;
  4516. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4517. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4518. }
  4519. #endif
  4520. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4521. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4522. uint8_t vdev_id, bool enable)
  4523. {
  4524. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4525. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4526. DP_MOD_ID_CDP);
  4527. if (!vdev) {
  4528. dp_err_rl("vdev %d does not exist", vdev_id);
  4529. return QDF_STATUS_E_FAILURE;
  4530. }
  4531. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4532. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4533. return QDF_STATUS_SUCCESS;
  4534. }
  4535. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4536. uint32_t *val)
  4537. {
  4538. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4539. struct dp_vdev *vdev;
  4540. uint32_t delay_accum;
  4541. uint32_t pkts_accum;
  4542. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4543. if (!vdev) {
  4544. dp_err_rl("vdev %d does not exist", vdev_id);
  4545. return QDF_STATUS_E_FAILURE;
  4546. }
  4547. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4548. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4549. return QDF_STATUS_E_FAILURE;
  4550. }
  4551. /* Average uplink delay based on current accumulated values */
  4552. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4553. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4554. *val = delay_accum / pkts_accum;
  4555. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4556. delay_accum, pkts_accum);
  4557. /* Reset accumulated values to 0 */
  4558. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4559. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4560. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4561. return QDF_STATUS_SUCCESS;
  4562. }
  4563. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4564. struct hal_tx_completion_status *ts)
  4565. {
  4566. uint32_t ul_delay;
  4567. if (qdf_unlikely(!vdev)) {
  4568. dp_info_rl("vdev is null or delete in progress");
  4569. return;
  4570. }
  4571. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4572. return;
  4573. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4574. vdev->delta_tsf,
  4575. &ul_delay)))
  4576. return;
  4577. ul_delay /= 1000; /* in unit of ms */
  4578. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4579. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4580. }
  4581. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4582. static inline
  4583. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4584. struct hal_tx_completion_status *ts)
  4585. {
  4586. }
  4587. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4588. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4589. struct dp_tx_desc_s *tx_desc,
  4590. struct hal_tx_completion_status *ts,
  4591. struct dp_txrx_peer *txrx_peer,
  4592. uint8_t ring_id)
  4593. {
  4594. uint32_t length;
  4595. qdf_ether_header_t *eh;
  4596. struct dp_vdev *vdev = NULL;
  4597. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4598. enum qdf_dp_tx_rx_status dp_status;
  4599. uint8_t link_id = 0;
  4600. if (!nbuf) {
  4601. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4602. goto out;
  4603. }
  4604. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4605. length = dp_tx_get_pkt_len(tx_desc);
  4606. dp_status = dp_tx_hw_to_qdf(ts->status);
  4607. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4608. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4609. QDF_TRACE_DEFAULT_PDEV_ID,
  4610. qdf_nbuf_data_addr(nbuf),
  4611. sizeof(qdf_nbuf_data(nbuf)),
  4612. tx_desc->id, ts->status, dp_status));
  4613. dp_tx_comp_debug("-------------------- \n"
  4614. "Tx Completion Stats: \n"
  4615. "-------------------- \n"
  4616. "ack_frame_rssi = %d \n"
  4617. "first_msdu = %d \n"
  4618. "last_msdu = %d \n"
  4619. "msdu_part_of_amsdu = %d \n"
  4620. "rate_stats valid = %d \n"
  4621. "bw = %d \n"
  4622. "pkt_type = %d \n"
  4623. "stbc = %d \n"
  4624. "ldpc = %d \n"
  4625. "sgi = %d \n"
  4626. "mcs = %d \n"
  4627. "ofdma = %d \n"
  4628. "tones_in_ru = %d \n"
  4629. "tsf = %d \n"
  4630. "ppdu_id = %d \n"
  4631. "transmit_cnt = %d \n"
  4632. "tid = %d \n"
  4633. "peer_id = %d\n"
  4634. "tx_status = %d\n",
  4635. ts->ack_frame_rssi, ts->first_msdu,
  4636. ts->last_msdu, ts->msdu_part_of_amsdu,
  4637. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4638. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4639. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4640. ts->transmit_cnt, ts->tid, ts->peer_id,
  4641. ts->status);
  4642. /* Update SoC level stats */
  4643. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4644. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4645. if (!txrx_peer) {
  4646. dp_info_rl("peer is null or deletion in progress");
  4647. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4648. goto out;
  4649. }
  4650. vdev = txrx_peer->vdev;
  4651. link_id = dp_tx_get_link_id_from_ppdu_id(soc, ts, txrx_peer, vdev);
  4652. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4653. dp_tx_update_uplink_delay(soc, vdev, ts);
  4654. /* check tx complete notification */
  4655. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4656. dp_tx_notify_completion(soc, vdev, tx_desc,
  4657. nbuf, ts->status);
  4658. /* Update per-packet stats for mesh mode */
  4659. if (qdf_unlikely(vdev->mesh_vdev) &&
  4660. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4661. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4662. /* Update peer level stats */
  4663. if (qdf_unlikely(txrx_peer->bss_peer &&
  4664. vdev->opmode == wlan_op_mode_ap)) {
  4665. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4666. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4667. length, link_id);
  4668. if (txrx_peer->vdev->tx_encap_type ==
  4669. htt_cmn_pkt_type_ethernet &&
  4670. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4671. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4672. tx.bcast, 1,
  4673. length, link_id);
  4674. }
  4675. }
  4676. } else {
  4677. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length,
  4678. link_id);
  4679. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4680. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4681. 1, length, link_id);
  4682. if (qdf_unlikely(txrx_peer->in_twt)) {
  4683. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4684. tx.tx_success_twt,
  4685. 1, length,
  4686. link_id);
  4687. }
  4688. }
  4689. }
  4690. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id, link_id);
  4691. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4692. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4693. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4694. ts, ts->tid);
  4695. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4696. #ifdef QCA_SUPPORT_RDK_STATS
  4697. if (soc->peerstats_enabled)
  4698. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4699. qdf_ktime_to_ms(tx_desc->timestamp),
  4700. ts->ppdu_id, link_id);
  4701. #endif
  4702. out:
  4703. return;
  4704. }
  4705. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4706. defined(QCA_ENHANCED_STATS_SUPPORT)
  4707. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4708. uint32_t length, uint8_t tx_status,
  4709. bool update)
  4710. {
  4711. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4712. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4713. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4714. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4715. }
  4716. }
  4717. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4718. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4719. uint32_t length, uint8_t tx_status,
  4720. bool update)
  4721. {
  4722. if (!txrx_peer->hw_txrx_stats_en) {
  4723. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4724. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4725. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4726. }
  4727. }
  4728. #else
  4729. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4730. uint32_t length, uint8_t tx_status,
  4731. bool update)
  4732. {
  4733. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4734. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4735. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4736. }
  4737. #endif
  4738. /**
  4739. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4740. * @next: descriptor of the nrxt buffer
  4741. *
  4742. * Return: none
  4743. */
  4744. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4745. static inline
  4746. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4747. {
  4748. qdf_nbuf_t nbuf = NULL;
  4749. if (next)
  4750. nbuf = next->nbuf;
  4751. if (nbuf)
  4752. qdf_prefetch(nbuf);
  4753. }
  4754. #else
  4755. static inline
  4756. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4757. {
  4758. }
  4759. #endif
  4760. /**
  4761. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4762. * @soc: core txrx main context
  4763. * @desc: software descriptor
  4764. *
  4765. * Return: true when packet is reinjected
  4766. */
  4767. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4768. defined(WLAN_MCAST_MLO) && !defined(CONFIG_MLO_SINGLE_DEV)
  4769. static inline bool
  4770. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4771. {
  4772. struct dp_vdev *vdev = NULL;
  4773. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4774. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4775. !soc->arch_ops.dp_tx_is_mcast_primary)
  4776. return false;
  4777. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4778. DP_MOD_ID_REINJECT);
  4779. if (qdf_unlikely(!vdev)) {
  4780. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4781. desc->id);
  4782. return false;
  4783. }
  4784. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4785. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4786. return false;
  4787. }
  4788. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4789. qdf_nbuf_len(desc->nbuf));
  4790. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4791. dp_tx_desc_release(desc, desc->pool_id);
  4792. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4793. return true;
  4794. }
  4795. return false;
  4796. }
  4797. #else
  4798. static inline bool
  4799. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4800. {
  4801. return false;
  4802. }
  4803. #endif
  4804. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4805. static inline void
  4806. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4807. {
  4808. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4809. }
  4810. static inline void
  4811. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4812. struct dp_tx_desc_s *desc)
  4813. {
  4814. qdf_nbuf_t nbuf = NULL;
  4815. nbuf = desc->nbuf;
  4816. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4817. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4818. else
  4819. qdf_nbuf_free(nbuf);
  4820. }
  4821. static inline void
  4822. dp_tx_nbuf_dev_queue_free_no_flag(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4823. qdf_nbuf_t nbuf)
  4824. {
  4825. if (!nbuf)
  4826. return;
  4827. if (nbuf->is_from_recycler)
  4828. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4829. else
  4830. qdf_nbuf_free(nbuf);
  4831. }
  4832. static inline void
  4833. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4834. {
  4835. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4836. }
  4837. #else
  4838. static inline void
  4839. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4840. {
  4841. }
  4842. static inline void
  4843. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4844. struct dp_tx_desc_s *desc)
  4845. {
  4846. qdf_nbuf_free(desc->nbuf);
  4847. }
  4848. static inline void
  4849. dp_tx_nbuf_dev_queue_free_no_flag(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4850. qdf_nbuf_t nbuf)
  4851. {
  4852. qdf_nbuf_free(nbuf);
  4853. }
  4854. static inline void
  4855. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4856. {
  4857. }
  4858. #endif
  4859. #ifdef WLAN_SUPPORT_PPEDS
  4860. static inline void
  4861. dp_tx_update_ppeds_tx_comp_stats(struct dp_soc *soc,
  4862. struct dp_txrx_peer *txrx_peer,
  4863. struct hal_tx_completion_status *ts,
  4864. struct dp_tx_desc_s *desc,
  4865. uint8_t ring_id)
  4866. {
  4867. uint8_t link_id = 0;
  4868. struct dp_vdev *vdev = NULL;
  4869. if (qdf_likely(txrx_peer)) {
  4870. dp_tx_update_peer_basic_stats(txrx_peer,
  4871. desc->length,
  4872. desc->tx_status,
  4873. false);
  4874. if (!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4875. hal_tx_comp_get_status(&desc->comp,
  4876. ts,
  4877. soc->hal_soc);
  4878. vdev = txrx_peer->vdev;
  4879. link_id = dp_tx_get_link_id_from_ppdu_id(soc,
  4880. ts,
  4881. txrx_peer,
  4882. vdev);
  4883. if (link_id < 1 || link_id > DP_MAX_MLO_LINKS)
  4884. link_id = 0;
  4885. dp_tx_update_peer_stats(desc, ts,
  4886. txrx_peer,
  4887. ring_id,
  4888. link_id);
  4889. }
  4890. }
  4891. }
  4892. #else
  4893. static inline void
  4894. dp_tx_update_ppeds_tx_comp_stats(struct dp_soc *soc,
  4895. struct dp_txrx_peer *txrx_peer,
  4896. struct hal_tx_completion_status *ts,
  4897. struct dp_tx_desc_s *desc,
  4898. uint8_t ring_id)
  4899. {
  4900. }
  4901. #endif
  4902. void
  4903. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4904. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4905. {
  4906. struct dp_tx_desc_s *desc;
  4907. struct dp_tx_desc_s *next;
  4908. struct hal_tx_completion_status ts;
  4909. struct dp_txrx_peer *txrx_peer = NULL;
  4910. uint16_t peer_id = DP_INVALID_PEER;
  4911. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4912. qdf_nbuf_queue_head_t h;
  4913. desc = comp_head;
  4914. dp_tx_nbuf_queue_head_init(&h);
  4915. while (desc) {
  4916. next = desc->next;
  4917. dp_tx_prefetch_next_nbuf_data(next);
  4918. if (peer_id != desc->peer_id) {
  4919. if (txrx_peer)
  4920. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4921. DP_MOD_ID_TX_COMP);
  4922. peer_id = desc->peer_id;
  4923. txrx_peer =
  4924. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4925. &txrx_ref_handle,
  4926. DP_MOD_ID_TX_COMP);
  4927. }
  4928. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4929. desc = next;
  4930. continue;
  4931. }
  4932. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4933. qdf_nbuf_t nbuf;
  4934. dp_tx_update_ppeds_tx_comp_stats(soc, txrx_peer, &ts,
  4935. desc, ring_id);
  4936. nbuf = dp_ppeds_tx_desc_free(soc, desc);
  4937. dp_tx_nbuf_dev_queue_free_no_flag(&h, nbuf);
  4938. desc = next;
  4939. continue;
  4940. }
  4941. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4942. struct dp_pdev *pdev = desc->pdev;
  4943. if (qdf_likely(txrx_peer))
  4944. dp_tx_update_peer_basic_stats(txrx_peer,
  4945. desc->length,
  4946. desc->tx_status,
  4947. false);
  4948. qdf_assert(pdev);
  4949. dp_tx_outstanding_dec(pdev);
  4950. /*
  4951. * Calling a QDF WRAPPER here is creating significant
  4952. * performance impact so avoided the wrapper call here
  4953. */
  4954. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4955. desc->id, DP_TX_COMP_UNMAP);
  4956. dp_tx_nbuf_unmap(soc, desc);
  4957. dp_tx_nbuf_dev_queue_free(&h, desc);
  4958. dp_tx_desc_free(soc, desc, desc->pool_id);
  4959. desc = next;
  4960. continue;
  4961. }
  4962. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4963. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4964. ring_id);
  4965. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4966. dp_tx_desc_release(desc, desc->pool_id);
  4967. desc = next;
  4968. }
  4969. dp_tx_nbuf_dev_kfree_list(&h);
  4970. if (txrx_peer)
  4971. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4972. }
  4973. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4974. static inline
  4975. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4976. int max_reap_limit)
  4977. {
  4978. bool limit_hit = false;
  4979. limit_hit =
  4980. (num_reaped >= max_reap_limit) ? true : false;
  4981. if (limit_hit)
  4982. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4983. return limit_hit;
  4984. }
  4985. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4986. {
  4987. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4988. }
  4989. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4990. {
  4991. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4992. return cfg->tx_comp_loop_pkt_limit;
  4993. }
  4994. #else
  4995. static inline
  4996. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4997. int max_reap_limit)
  4998. {
  4999. return false;
  5000. }
  5001. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5002. {
  5003. return false;
  5004. }
  5005. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5006. {
  5007. return 0;
  5008. }
  5009. #endif
  5010. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  5011. static inline int
  5012. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5013. int *max_reap_limit)
  5014. {
  5015. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  5016. max_reap_limit);
  5017. }
  5018. #else
  5019. static inline int
  5020. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5021. int *max_reap_limit)
  5022. {
  5023. return 0;
  5024. }
  5025. #endif
  5026. #ifdef DP_TX_TRACKING
  5027. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  5028. {
  5029. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  5030. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  5031. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  5032. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  5033. }
  5034. }
  5035. #endif
  5036. #ifndef WLAN_SOFTUMAC_SUPPORT
  5037. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  5038. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  5039. uint32_t quota)
  5040. {
  5041. void *tx_comp_hal_desc;
  5042. void *last_prefetched_hw_desc = NULL;
  5043. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  5044. hal_soc_handle_t hal_soc;
  5045. uint8_t buffer_src;
  5046. struct dp_tx_desc_s *tx_desc = NULL;
  5047. struct dp_tx_desc_s *head_desc = NULL;
  5048. struct dp_tx_desc_s *tail_desc = NULL;
  5049. uint32_t num_processed = 0;
  5050. uint32_t count;
  5051. uint32_t num_avail_for_reap = 0;
  5052. bool force_break = false;
  5053. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  5054. int max_reap_limit, ring_near_full;
  5055. uint32_t num_entries;
  5056. DP_HIST_INIT();
  5057. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  5058. more_data:
  5059. hal_soc = soc->hal_soc;
  5060. /* Re-initialize local variables to be re-used */
  5061. head_desc = NULL;
  5062. tail_desc = NULL;
  5063. count = 0;
  5064. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  5065. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  5066. &max_reap_limit);
  5067. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  5068. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  5069. return 0;
  5070. }
  5071. if (!num_avail_for_reap)
  5072. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  5073. hal_ring_hdl, 0);
  5074. if (num_avail_for_reap >= quota)
  5075. num_avail_for_reap = quota;
  5076. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  5077. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  5078. hal_ring_hdl,
  5079. num_avail_for_reap);
  5080. /* Find head descriptor from completion ring */
  5081. while (qdf_likely(num_avail_for_reap--)) {
  5082. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  5083. if (qdf_unlikely(!tx_comp_hal_desc))
  5084. break;
  5085. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  5086. tx_comp_hal_desc);
  5087. /* If this buffer was not released by TQM or FW, then it is not
  5088. * Tx completion indication, assert */
  5089. if (qdf_unlikely(buffer_src !=
  5090. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  5091. (qdf_unlikely(buffer_src !=
  5092. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  5093. uint8_t wbm_internal_error;
  5094. dp_err_rl(
  5095. "Tx comp release_src != TQM | FW but from %d",
  5096. buffer_src);
  5097. hal_dump_comp_desc(tx_comp_hal_desc);
  5098. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  5099. /* When WBM sees NULL buffer_addr_info in any of
  5100. * ingress rings it sends an error indication,
  5101. * with wbm_internal_error=1, to a specific ring.
  5102. * The WBM2SW ring used to indicate these errors is
  5103. * fixed in HW, and that ring is being used as Tx
  5104. * completion ring. These errors are not related to
  5105. * Tx completions, and should just be ignored
  5106. */
  5107. wbm_internal_error = hal_get_wbm_internal_error(
  5108. hal_soc,
  5109. tx_comp_hal_desc);
  5110. if (wbm_internal_error) {
  5111. dp_err_rl("Tx comp wbm_internal_error!!");
  5112. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5113. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5114. buffer_src)
  5115. dp_handle_wbm_internal_error(
  5116. soc,
  5117. tx_comp_hal_desc,
  5118. hal_tx_comp_get_buffer_type(
  5119. tx_comp_hal_desc));
  5120. } else {
  5121. dp_err_rl("Tx comp wbm_internal_error false");
  5122. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5123. }
  5124. continue;
  5125. }
  5126. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5127. tx_comp_hal_desc,
  5128. &tx_desc);
  5129. if (qdf_unlikely(!tx_desc)) {
  5130. dp_err("unable to retrieve tx_desc!");
  5131. hal_dump_comp_desc(tx_comp_hal_desc);
  5132. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  5133. QDF_BUG(0);
  5134. continue;
  5135. }
  5136. tx_desc->buffer_src = buffer_src;
  5137. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5138. goto add_to_pool2;
  5139. /*
  5140. * If the release source is FW, process the HTT status
  5141. */
  5142. if (qdf_unlikely(buffer_src ==
  5143. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5144. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5145. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5146. htt_tx_status);
  5147. /* Collect hw completion contents */
  5148. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5149. &tx_desc->comp, 1);
  5150. soc->arch_ops.dp_tx_process_htt_completion(
  5151. soc,
  5152. tx_desc,
  5153. htt_tx_status,
  5154. ring_id);
  5155. } else {
  5156. tx_desc->tx_status =
  5157. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5158. tx_desc->buffer_src = buffer_src;
  5159. /*
  5160. * If the fast completion mode is enabled extended
  5161. * metadata from descriptor is not copied
  5162. */
  5163. if (qdf_likely(tx_desc->flags &
  5164. DP_TX_DESC_FLAG_SIMPLE))
  5165. goto add_to_pool;
  5166. /*
  5167. * If the descriptor is already freed in vdev_detach,
  5168. * continue to next descriptor
  5169. */
  5170. if (qdf_unlikely
  5171. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5172. !tx_desc->flags)) {
  5173. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5174. tx_desc->id);
  5175. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5176. dp_tx_desc_check_corruption(tx_desc);
  5177. continue;
  5178. }
  5179. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5180. dp_tx_comp_info_rl("pdev in down state %d",
  5181. tx_desc->id);
  5182. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5183. dp_tx_comp_free_buf(soc, tx_desc, false);
  5184. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5185. goto next_desc;
  5186. }
  5187. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5188. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5189. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5190. tx_desc->flags, tx_desc->id);
  5191. qdf_assert_always(0);
  5192. }
  5193. /* Collect hw completion contents */
  5194. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5195. &tx_desc->comp, 1);
  5196. add_to_pool:
  5197. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5198. add_to_pool2:
  5199. /* First ring descriptor on the cycle */
  5200. if (!head_desc) {
  5201. head_desc = tx_desc;
  5202. tail_desc = tx_desc;
  5203. }
  5204. tail_desc->next = tx_desc;
  5205. tx_desc->next = NULL;
  5206. tail_desc = tx_desc;
  5207. }
  5208. next_desc:
  5209. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5210. /*
  5211. * Processed packet count is more than given quota
  5212. * stop to processing
  5213. */
  5214. count++;
  5215. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5216. num_avail_for_reap,
  5217. hal_ring_hdl,
  5218. &last_prefetched_hw_desc,
  5219. &last_prefetched_sw_desc);
  5220. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5221. break;
  5222. }
  5223. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5224. /* Process the reaped descriptors */
  5225. if (head_desc)
  5226. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5227. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5228. /*
  5229. * If we are processing in near-full condition, there are 3 scenario
  5230. * 1) Ring entries has reached critical state
  5231. * 2) Ring entries are still near high threshold
  5232. * 3) Ring entries are below the safe level
  5233. *
  5234. * One more loop will move the state to normal processing and yield
  5235. */
  5236. if (ring_near_full)
  5237. goto more_data;
  5238. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5239. if (num_processed >= quota)
  5240. force_break = true;
  5241. if (!force_break &&
  5242. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5243. hal_ring_hdl)) {
  5244. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5245. if (!hif_exec_should_yield(soc->hif_handle,
  5246. int_ctx->dp_intr_id))
  5247. goto more_data;
  5248. num_avail_for_reap =
  5249. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5250. hal_ring_hdl,
  5251. true);
  5252. if (qdf_unlikely(num_entries &&
  5253. (num_avail_for_reap >=
  5254. num_entries >> 1))) {
  5255. DP_STATS_INC(soc, tx.near_full, 1);
  5256. goto more_data;
  5257. }
  5258. }
  5259. }
  5260. DP_TX_HIST_STATS_PER_PDEV();
  5261. return num_processed;
  5262. }
  5263. #endif
  5264. #ifdef FEATURE_WLAN_TDLS
  5265. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5266. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5267. {
  5268. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5269. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5270. DP_MOD_ID_TDLS);
  5271. if (!vdev) {
  5272. dp_err("vdev handle for id %d is NULL", vdev_id);
  5273. return NULL;
  5274. }
  5275. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5276. vdev->is_tdls_frame = true;
  5277. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5278. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5279. }
  5280. #endif
  5281. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5282. {
  5283. int pdev_id;
  5284. /*
  5285. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5286. */
  5287. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5288. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5289. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5290. vdev->vdev_id);
  5291. pdev_id =
  5292. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5293. vdev->pdev->pdev_id);
  5294. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5295. /*
  5296. * Set HTT Extension Valid bit to 0 by default
  5297. */
  5298. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5299. dp_tx_vdev_update_search_flags(vdev);
  5300. return QDF_STATUS_SUCCESS;
  5301. }
  5302. #ifndef FEATURE_WDS
  5303. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5304. {
  5305. return false;
  5306. }
  5307. #endif
  5308. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5309. {
  5310. struct dp_soc *soc = vdev->pdev->soc;
  5311. /*
  5312. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5313. * for TDLS link
  5314. *
  5315. * Enable AddrY (SA based search) only for non-WDS STA and
  5316. * ProxySTA VAP (in HKv1) modes.
  5317. *
  5318. * In all other VAP modes, only DA based search should be
  5319. * enabled
  5320. */
  5321. if (vdev->opmode == wlan_op_mode_sta &&
  5322. vdev->tdls_link_connected)
  5323. vdev->hal_desc_addr_search_flags =
  5324. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5325. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5326. !dp_tx_da_search_override(vdev))
  5327. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5328. else
  5329. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5330. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5331. vdev->search_type = soc->sta_mode_search_policy;
  5332. else
  5333. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5334. }
  5335. static inline bool
  5336. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5337. struct dp_vdev *vdev,
  5338. struct dp_tx_desc_s *tx_desc)
  5339. {
  5340. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5341. return false;
  5342. /*
  5343. * if vdev is given, then only check whether desc
  5344. * vdev match. if vdev is NULL, then check whether
  5345. * desc pdev match.
  5346. */
  5347. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5348. (tx_desc->pdev == pdev);
  5349. }
  5350. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5351. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5352. bool force_free)
  5353. {
  5354. uint8_t i;
  5355. uint32_t j;
  5356. uint32_t num_desc, page_id, offset;
  5357. uint16_t num_desc_per_page;
  5358. struct dp_soc *soc = pdev->soc;
  5359. struct dp_tx_desc_s *tx_desc = NULL;
  5360. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5361. if (!vdev && !force_free) {
  5362. dp_err("Reset TX desc vdev, Vdev param is required!");
  5363. return;
  5364. }
  5365. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5366. tx_desc_pool = &soc->tx_desc[i];
  5367. if (!(tx_desc_pool->pool_size) ||
  5368. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5369. !(tx_desc_pool->desc_pages.cacheable_pages))
  5370. continue;
  5371. /*
  5372. * Add flow pool lock protection in case pool is freed
  5373. * due to all tx_desc is recycled when handle TX completion.
  5374. * this is not necessary when do force flush as:
  5375. * a. double lock will happen if dp_tx_desc_release is
  5376. * also trying to acquire it.
  5377. * b. dp interrupt has been disabled before do force TX desc
  5378. * flush in dp_pdev_deinit().
  5379. */
  5380. if (!force_free)
  5381. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5382. num_desc = tx_desc_pool->pool_size;
  5383. num_desc_per_page =
  5384. tx_desc_pool->desc_pages.num_element_per_page;
  5385. for (j = 0; j < num_desc; j++) {
  5386. page_id = j / num_desc_per_page;
  5387. offset = j % num_desc_per_page;
  5388. if (qdf_unlikely(!(tx_desc_pool->
  5389. desc_pages.cacheable_pages)))
  5390. break;
  5391. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5392. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5393. /*
  5394. * Free TX desc if force free is
  5395. * required, otherwise only reset vdev
  5396. * in this TX desc.
  5397. */
  5398. if (force_free) {
  5399. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5400. dp_tx_comp_free_buf(soc, tx_desc,
  5401. false);
  5402. dp_tx_desc_release(tx_desc, i);
  5403. } else {
  5404. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5405. }
  5406. }
  5407. }
  5408. if (!force_free)
  5409. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5410. }
  5411. }
  5412. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5413. /**
  5414. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5415. *
  5416. * @soc: Handle to DP soc structure
  5417. * @tx_desc: pointer of one TX desc
  5418. * @desc_pool_id: TX Desc pool id
  5419. */
  5420. static inline void
  5421. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5422. uint8_t desc_pool_id)
  5423. {
  5424. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5425. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5426. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5427. }
  5428. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5429. bool force_free)
  5430. {
  5431. uint8_t i, num_pool;
  5432. uint32_t j;
  5433. uint32_t num_desc, page_id, offset;
  5434. uint16_t num_desc_per_page;
  5435. struct dp_soc *soc = pdev->soc;
  5436. struct dp_tx_desc_s *tx_desc = NULL;
  5437. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5438. if (!vdev && !force_free) {
  5439. dp_err("Reset TX desc vdev, Vdev param is required!");
  5440. return;
  5441. }
  5442. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5443. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5444. for (i = 0; i < num_pool; i++) {
  5445. tx_desc_pool = &soc->tx_desc[i];
  5446. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5447. continue;
  5448. num_desc_per_page =
  5449. tx_desc_pool->desc_pages.num_element_per_page;
  5450. for (j = 0; j < num_desc; j++) {
  5451. page_id = j / num_desc_per_page;
  5452. offset = j % num_desc_per_page;
  5453. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5454. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5455. if (force_free) {
  5456. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5457. dp_tx_comp_free_buf(soc, tx_desc,
  5458. false);
  5459. dp_tx_desc_release(tx_desc, i);
  5460. } else {
  5461. dp_tx_desc_reset_vdev(soc, tx_desc,
  5462. i);
  5463. }
  5464. }
  5465. }
  5466. }
  5467. }
  5468. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5469. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5470. {
  5471. struct dp_pdev *pdev = vdev->pdev;
  5472. /* Reset TX desc associated to this Vdev as NULL */
  5473. dp_tx_desc_flush(pdev, vdev, false);
  5474. return QDF_STATUS_SUCCESS;
  5475. }
  5476. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5477. /* Pools will be allocated dynamically */
  5478. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5479. int num_desc)
  5480. {
  5481. uint8_t i;
  5482. for (i = 0; i < num_pool; i++) {
  5483. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5484. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5485. }
  5486. return QDF_STATUS_SUCCESS;
  5487. }
  5488. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5489. uint32_t num_desc)
  5490. {
  5491. return QDF_STATUS_SUCCESS;
  5492. }
  5493. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5494. {
  5495. }
  5496. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5497. {
  5498. uint8_t i;
  5499. for (i = 0; i < num_pool; i++)
  5500. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5501. }
  5502. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5503. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5504. uint32_t num_desc)
  5505. {
  5506. uint8_t i, count;
  5507. /* Allocate software Tx descriptor pools */
  5508. for (i = 0; i < num_pool; i++) {
  5509. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5510. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5511. FL("Tx Desc Pool alloc %d failed %pK"),
  5512. i, soc);
  5513. goto fail;
  5514. }
  5515. }
  5516. return QDF_STATUS_SUCCESS;
  5517. fail:
  5518. for (count = 0; count < i; count++)
  5519. dp_tx_desc_pool_free(soc, count);
  5520. return QDF_STATUS_E_NOMEM;
  5521. }
  5522. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5523. uint32_t num_desc)
  5524. {
  5525. uint8_t i;
  5526. for (i = 0; i < num_pool; i++) {
  5527. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5528. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5529. FL("Tx Desc Pool init %d failed %pK"),
  5530. i, soc);
  5531. return QDF_STATUS_E_NOMEM;
  5532. }
  5533. }
  5534. return QDF_STATUS_SUCCESS;
  5535. }
  5536. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5537. {
  5538. uint8_t i;
  5539. for (i = 0; i < num_pool; i++)
  5540. dp_tx_desc_pool_deinit(soc, i);
  5541. }
  5542. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5543. {
  5544. uint8_t i;
  5545. for (i = 0; i < num_pool; i++)
  5546. dp_tx_desc_pool_free(soc, i);
  5547. }
  5548. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5549. /**
  5550. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5551. * @soc: core txrx main context
  5552. * @num_pool: number of pools
  5553. *
  5554. */
  5555. static void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5556. {
  5557. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5558. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5559. }
  5560. /**
  5561. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5562. * @soc: core txrx main context
  5563. * @num_pool: number of pools
  5564. *
  5565. */
  5566. static void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5567. {
  5568. dp_tx_tso_desc_pool_free(soc, num_pool);
  5569. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5570. }
  5571. #ifndef WLAN_SOFTUMAC_SUPPORT
  5572. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5573. {
  5574. uint8_t num_pool;
  5575. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5576. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5577. dp_tx_ext_desc_pool_free(soc, num_pool);
  5578. dp_tx_delete_static_pools(soc, num_pool);
  5579. }
  5580. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5581. {
  5582. uint8_t num_pool;
  5583. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5584. dp_tx_flow_control_deinit(soc);
  5585. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5586. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5587. dp_tx_deinit_static_pools(soc, num_pool);
  5588. }
  5589. #else
  5590. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5591. {
  5592. uint8_t num_pool;
  5593. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5594. dp_tx_delete_static_pools(soc, num_pool);
  5595. }
  5596. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5597. {
  5598. uint8_t num_pool;
  5599. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5600. dp_tx_flow_control_deinit(soc);
  5601. dp_tx_deinit_static_pools(soc, num_pool);
  5602. }
  5603. #endif /*WLAN_SOFTUMAC_SUPPORT*/
  5604. /**
  5605. * dp_tx_tso_cmn_desc_pool_alloc() - TSO cmn desc pool allocator
  5606. * @soc: DP soc handle
  5607. * @num_pool: Number of pools
  5608. * @num_desc: Number of descriptors
  5609. *
  5610. * Reserve TSO descriptor buffers
  5611. *
  5612. * Return: QDF_STATUS_E_FAILURE on failure or
  5613. * QDF_STATUS_SUCCESS on success
  5614. */
  5615. static QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5616. uint8_t num_pool,
  5617. uint32_t num_desc)
  5618. {
  5619. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5620. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5621. return QDF_STATUS_E_FAILURE;
  5622. }
  5623. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5624. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5625. num_pool, soc);
  5626. return QDF_STATUS_E_FAILURE;
  5627. }
  5628. return QDF_STATUS_SUCCESS;
  5629. }
  5630. /**
  5631. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5632. * @soc: DP soc handle
  5633. * @num_pool: Number of pools
  5634. * @num_desc: Number of descriptors
  5635. *
  5636. * Initialize TSO descriptor pools
  5637. *
  5638. * Return: QDF_STATUS_E_FAILURE on failure or
  5639. * QDF_STATUS_SUCCESS on success
  5640. */
  5641. static QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5642. uint8_t num_pool,
  5643. uint32_t num_desc)
  5644. {
  5645. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5646. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5647. return QDF_STATUS_E_FAILURE;
  5648. }
  5649. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5650. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5651. num_pool, soc);
  5652. return QDF_STATUS_E_FAILURE;
  5653. }
  5654. return QDF_STATUS_SUCCESS;
  5655. }
  5656. #ifndef WLAN_SOFTUMAC_SUPPORT
  5657. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5658. {
  5659. uint8_t num_pool;
  5660. uint32_t num_desc;
  5661. uint32_t num_ext_desc;
  5662. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5663. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5664. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5665. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5666. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5667. __func__, num_pool, num_desc);
  5668. if ((num_pool > MAX_TXDESC_POOLS) ||
  5669. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5670. goto fail1;
  5671. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5672. goto fail1;
  5673. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5674. goto fail2;
  5675. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5676. return QDF_STATUS_SUCCESS;
  5677. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5678. goto fail3;
  5679. return QDF_STATUS_SUCCESS;
  5680. fail3:
  5681. dp_tx_ext_desc_pool_free(soc, num_pool);
  5682. fail2:
  5683. dp_tx_delete_static_pools(soc, num_pool);
  5684. fail1:
  5685. return QDF_STATUS_E_RESOURCES;
  5686. }
  5687. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5688. {
  5689. uint8_t num_pool;
  5690. uint32_t num_desc;
  5691. uint32_t num_ext_desc;
  5692. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5693. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5694. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5695. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5696. goto fail1;
  5697. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5698. goto fail2;
  5699. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5700. return QDF_STATUS_SUCCESS;
  5701. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5702. goto fail3;
  5703. dp_tx_flow_control_init(soc);
  5704. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5705. return QDF_STATUS_SUCCESS;
  5706. fail3:
  5707. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5708. fail2:
  5709. dp_tx_deinit_static_pools(soc, num_pool);
  5710. fail1:
  5711. return QDF_STATUS_E_RESOURCES;
  5712. }
  5713. #else
  5714. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5715. {
  5716. uint8_t num_pool;
  5717. uint32_t num_desc;
  5718. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5719. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5720. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5721. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5722. __func__, num_pool, num_desc);
  5723. if ((num_pool > MAX_TXDESC_POOLS) ||
  5724. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5725. return QDF_STATUS_E_RESOURCES;
  5726. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5727. return QDF_STATUS_E_RESOURCES;
  5728. return QDF_STATUS_SUCCESS;
  5729. }
  5730. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5731. {
  5732. uint8_t num_pool;
  5733. uint32_t num_desc;
  5734. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5735. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5736. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5737. return QDF_STATUS_E_RESOURCES;
  5738. dp_tx_flow_control_init(soc);
  5739. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5740. return QDF_STATUS_SUCCESS;
  5741. }
  5742. #endif
  5743. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5744. {
  5745. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5746. uint8_t num_pool;
  5747. uint32_t num_ext_desc;
  5748. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5749. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5750. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5751. return QDF_STATUS_E_FAILURE;
  5752. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5753. return QDF_STATUS_E_FAILURE;
  5754. return QDF_STATUS_SUCCESS;
  5755. }
  5756. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5757. {
  5758. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5759. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5760. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5761. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5762. return QDF_STATUS_SUCCESS;
  5763. }
  5764. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5765. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5766. enum qdf_pkt_timestamp_index index, uint64_t time,
  5767. qdf_nbuf_t nbuf)
  5768. {
  5769. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5770. uint64_t tsf_time;
  5771. if (vdev->get_tsf_time) {
  5772. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5773. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5774. }
  5775. }
  5776. }
  5777. void dp_pkt_get_timestamp(uint64_t *time)
  5778. {
  5779. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5780. *time = qdf_get_log_timestamp();
  5781. }
  5782. #endif