dp_power.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/pm_runtime.h>
  7. #include "dp_power.h"
  8. #include "dp_catalog.h"
  9. #include "dp_debug.h"
  10. #include "dp_pll.h"
  11. #define DP_CLIENT_NAME_SIZE 20
  12. #define XO_CLK_KHZ 19200
  13. struct dp_power_private {
  14. struct dp_parser *parser;
  15. struct dp_pll *pll;
  16. struct platform_device *pdev;
  17. struct clk *pixel_clk_rcg;
  18. struct clk *pixel_parent;
  19. struct clk *pixel1_clk_rcg;
  20. struct clk *xo_clk;
  21. struct dp_power dp_power;
  22. bool core_clks_on;
  23. bool link_clks_on;
  24. bool strm0_clks_on;
  25. bool strm1_clks_on;
  26. bool strm0_clks_parked;
  27. bool strm1_clks_parked;
  28. };
  29. static int dp_power_regulator_init(struct dp_power_private *power)
  30. {
  31. int rc = 0, i = 0, j = 0;
  32. struct platform_device *pdev;
  33. struct dp_parser *parser;
  34. parser = power->parser;
  35. pdev = power->pdev;
  36. for (i = DP_CORE_PM; !rc && (i < DP_MAX_PM); i++) {
  37. rc = msm_dss_get_vreg(&pdev->dev,
  38. parser->mp[i].vreg_config,
  39. parser->mp[i].num_vreg, 1);
  40. if (rc) {
  41. DP_ERR("failed to init vregs for %s\n",
  42. dp_parser_pm_name(i));
  43. for (j = i - 1; j >= DP_CORE_PM; j--) {
  44. msm_dss_get_vreg(&pdev->dev,
  45. parser->mp[j].vreg_config,
  46. parser->mp[j].num_vreg, 0);
  47. }
  48. goto error;
  49. }
  50. }
  51. error:
  52. return rc;
  53. }
  54. static void dp_power_regulator_deinit(struct dp_power_private *power)
  55. {
  56. int rc = 0, i = 0;
  57. struct platform_device *pdev;
  58. struct dp_parser *parser;
  59. parser = power->parser;
  60. pdev = power->pdev;
  61. for (i = DP_CORE_PM; (i < DP_MAX_PM); i++) {
  62. rc = msm_dss_get_vreg(&pdev->dev,
  63. parser->mp[i].vreg_config,
  64. parser->mp[i].num_vreg, 0);
  65. if (rc)
  66. DP_ERR("failed to deinit vregs for %s\n",
  67. dp_parser_pm_name(i));
  68. }
  69. }
  70. static int dp_power_regulator_ctrl(struct dp_power_private *power, bool enable)
  71. {
  72. int rc = 0, i = 0, j = 0;
  73. struct dp_parser *parser;
  74. parser = power->parser;
  75. for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
  76. /*
  77. * The DP_PLL_PM regulator is controlled by dp_display based
  78. * on the link configuration.
  79. */
  80. if (i == DP_PLL_PM) {
  81. DP_DEBUG("skipping: '%s' vregs for %s\n",
  82. enable ? "enable" : "disable",
  83. dp_parser_pm_name(i));
  84. continue;
  85. }
  86. rc = msm_dss_enable_vreg(
  87. parser->mp[i].vreg_config,
  88. parser->mp[i].num_vreg, enable);
  89. if (rc) {
  90. DP_ERR("failed to '%s' vregs for %s\n",
  91. enable ? "enable" : "disable",
  92. dp_parser_pm_name(i));
  93. if (enable) {
  94. for (j = i-1; j >= DP_CORE_PM; j--) {
  95. msm_dss_enable_vreg(
  96. parser->mp[j].vreg_config,
  97. parser->mp[j].num_vreg, 0);
  98. }
  99. }
  100. goto error;
  101. }
  102. }
  103. error:
  104. return rc;
  105. }
  106. static int dp_power_pinctrl_set(struct dp_power_private *power, bool active)
  107. {
  108. int rc = -EFAULT;
  109. struct pinctrl_state *pin_state;
  110. struct dp_parser *parser;
  111. parser = power->parser;
  112. if (IS_ERR_OR_NULL(parser->pinctrl.pin))
  113. return 0;
  114. if (parser->no_aux_switch && parser->lphw_hpd) {
  115. pin_state = active ? parser->pinctrl.state_hpd_ctrl
  116. : parser->pinctrl.state_hpd_tlmm;
  117. if (!IS_ERR_OR_NULL(pin_state)) {
  118. rc = pinctrl_select_state(parser->pinctrl.pin,
  119. pin_state);
  120. if (rc) {
  121. DP_ERR("cannot direct hpd line to %s\n",
  122. active ? "ctrl" : "tlmm");
  123. return rc;
  124. }
  125. }
  126. }
  127. if (parser->no_aux_switch)
  128. return 0;
  129. pin_state = active ? parser->pinctrl.state_active
  130. : parser->pinctrl.state_suspend;
  131. if (!IS_ERR_OR_NULL(pin_state)) {
  132. rc = pinctrl_select_state(parser->pinctrl.pin,
  133. pin_state);
  134. if (rc)
  135. DP_ERR("can not set %s pins\n",
  136. active ? "dp_active"
  137. : "dp_sleep");
  138. } else {
  139. DP_ERR("invalid '%s' pinstate\n",
  140. active ? "dp_active"
  141. : "dp_sleep");
  142. }
  143. return rc;
  144. }
  145. static void dp_power_clk_put(struct dp_power_private *power)
  146. {
  147. enum dp_pm_type module;
  148. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  149. struct dss_module_power *pm = &power->parser->mp[module];
  150. if (!pm->num_clk)
  151. continue;
  152. msm_dss_mmrm_deregister(&power->pdev->dev, pm);
  153. msm_dss_put_clk(pm->clk_config, pm->num_clk);
  154. }
  155. }
  156. static int dp_power_clk_init(struct dp_power_private *power, bool enable)
  157. {
  158. int rc = 0;
  159. struct device *dev;
  160. enum dp_pm_type module;
  161. dev = &power->pdev->dev;
  162. if (enable) {
  163. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  164. struct dss_module_power *pm =
  165. &power->parser->mp[module];
  166. if (!pm->num_clk)
  167. continue;
  168. rc = msm_dss_get_clk(dev, pm->clk_config, pm->num_clk);
  169. if (rc) {
  170. DP_ERR("failed to get %s clk. err=%d\n",
  171. dp_parser_pm_name(module), rc);
  172. goto exit;
  173. }
  174. }
  175. power->pixel_clk_rcg = clk_get(dev, "pixel_clk_rcg");
  176. if (IS_ERR(power->pixel_clk_rcg)) {
  177. DP_ERR("Unable to get DP pixel clk RCG: %ld\n",
  178. PTR_ERR(power->pixel_clk_rcg));
  179. rc = PTR_ERR(power->pixel_clk_rcg);
  180. power->pixel_clk_rcg = NULL;
  181. goto err_pixel_clk_rcg;
  182. }
  183. power->pixel_parent = clk_get(dev, "pixel_parent");
  184. if (IS_ERR(power->pixel_parent)) {
  185. DP_ERR("Unable to get DP pixel RCG parent: %d\n",
  186. PTR_ERR(power->pixel_parent));
  187. rc = PTR_ERR(power->pixel_parent);
  188. power->pixel_parent = NULL;
  189. goto err_pixel_parent;
  190. }
  191. power->xo_clk = clk_get(dev, "rpmh_cxo_clk");
  192. if (IS_ERR(power->xo_clk)) {
  193. DP_ERR("Unable to get XO clk: %d\n", PTR_ERR(power->xo_clk));
  194. rc = PTR_ERR(power->xo_clk);
  195. power->xo_clk = NULL;
  196. goto err_xo_clk;
  197. }
  198. if (power->parser->has_mst) {
  199. power->pixel1_clk_rcg = clk_get(dev, "pixel1_clk_rcg");
  200. if (IS_ERR(power->pixel1_clk_rcg)) {
  201. DP_ERR("Unable to get DP pixel1 clk RCG: %d\n",
  202. PTR_ERR(power->pixel1_clk_rcg));
  203. rc = PTR_ERR(power->pixel1_clk_rcg);
  204. power->pixel1_clk_rcg = NULL;
  205. goto err_pixel1_clk_rcg;
  206. }
  207. }
  208. } else {
  209. if (power->pixel1_clk_rcg)
  210. clk_put(power->pixel1_clk_rcg);
  211. if (power->pixel_parent)
  212. clk_put(power->pixel_parent);
  213. if (power->pixel_clk_rcg)
  214. clk_put(power->pixel_clk_rcg);
  215. dp_power_clk_put(power);
  216. }
  217. return rc;
  218. err_pixel1_clk_rcg:
  219. clk_put(power->xo_clk);
  220. err_xo_clk:
  221. clk_put(power->pixel_parent);
  222. err_pixel_parent:
  223. clk_put(power->pixel_clk_rcg);
  224. err_pixel_clk_rcg:
  225. dp_power_clk_put(power);
  226. exit:
  227. return rc;
  228. }
  229. static int dp_power_park_module(struct dp_power_private *power, enum dp_pm_type module)
  230. {
  231. struct dss_module_power *mp;
  232. struct clk *clk = NULL;
  233. int rc = 0;
  234. bool *parked;
  235. mp = &power->parser->mp[module];
  236. if (module == DP_STREAM0_PM) {
  237. clk = power->pixel_clk_rcg;
  238. parked = &power->strm0_clks_parked;
  239. } else if (module == DP_STREAM1_PM) {
  240. clk = power->pixel1_clk_rcg;
  241. parked = &power->strm1_clks_parked;
  242. } else {
  243. goto exit;
  244. }
  245. if (!clk) {
  246. DP_WARN("clk type %d not supported\n", module);
  247. rc = -EINVAL;
  248. goto exit;
  249. }
  250. if (!power->xo_clk) {
  251. rc = -EINVAL;
  252. goto exit;
  253. }
  254. if (*parked)
  255. goto exit;
  256. rc = clk_set_parent(clk, power->xo_clk);
  257. if (rc) {
  258. DP_ERR("unable to set xo parent on clk %d\n", module);
  259. goto exit;
  260. }
  261. mp->clk_config->rate = XO_CLK_KHZ;
  262. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  263. if (rc) {
  264. DP_ERR("failed to set clk rate.\n");
  265. goto exit;
  266. }
  267. *parked = true;
  268. exit:
  269. return rc;
  270. }
  271. static int dp_power_clk_set_rate(struct dp_power_private *power,
  272. enum dp_pm_type module, bool enable)
  273. {
  274. int rc = 0;
  275. struct dss_module_power *mp;
  276. if (!power) {
  277. DP_ERR("invalid power data\n");
  278. rc = -EINVAL;
  279. goto exit;
  280. }
  281. mp = &power->parser->mp[module];
  282. if (enable) {
  283. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  284. if (rc) {
  285. DP_ERR("failed to set clks rate.\n");
  286. goto exit;
  287. }
  288. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 1);
  289. if (rc) {
  290. DP_ERR("failed to enable clks\n");
  291. goto exit;
  292. }
  293. } else {
  294. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 0);
  295. if (rc) {
  296. DP_ERR("failed to disable clks\n");
  297. goto exit;
  298. }
  299. dp_power_park_module(power, module);
  300. }
  301. exit:
  302. return rc;
  303. }
  304. static int dp_power_clk_enable(struct dp_power *dp_power,
  305. enum dp_pm_type pm_type, bool enable)
  306. {
  307. int rc = 0;
  308. struct dss_module_power *mp;
  309. struct dp_power_private *power;
  310. if (!dp_power) {
  311. DP_ERR("invalid power data\n");
  312. rc = -EINVAL;
  313. goto error;
  314. }
  315. power = container_of(dp_power, struct dp_power_private, dp_power);
  316. mp = &power->parser->mp[pm_type];
  317. if (pm_type >= DP_MAX_PM) {
  318. DP_ERR("unsupported power module: %s\n",
  319. dp_parser_pm_name(pm_type));
  320. return -EINVAL;
  321. }
  322. if (enable) {
  323. if (pm_type == DP_CORE_PM && power->core_clks_on) {
  324. DP_DEBUG("core clks already enabled\n");
  325. return 0;
  326. }
  327. if ((pm_type == DP_STREAM0_PM) && (power->strm0_clks_on)) {
  328. DP_DEBUG("strm0 clks already enabled\n");
  329. return 0;
  330. }
  331. if ((pm_type == DP_STREAM1_PM) && (power->strm1_clks_on)) {
  332. DP_DEBUG("strm1 clks already enabled\n");
  333. return 0;
  334. }
  335. if ((pm_type == DP_CTRL_PM) && (!power->core_clks_on)) {
  336. DP_DEBUG("Need to enable core clks before link clks\n");
  337. rc = dp_power_clk_set_rate(power, pm_type, enable);
  338. if (rc) {
  339. DP_ERR("failed to enable clks: %s. err=%d\n",
  340. dp_parser_pm_name(DP_CORE_PM), rc);
  341. goto error;
  342. } else {
  343. power->core_clks_on = true;
  344. }
  345. }
  346. if (pm_type == DP_LINK_PM && power->link_clks_on) {
  347. DP_DEBUG("links clks already enabled\n");
  348. return 0;
  349. }
  350. }
  351. rc = dp_power_clk_set_rate(power, pm_type, enable);
  352. if (rc) {
  353. DP_ERR("failed to '%s' clks for: %s. err=%d\n",
  354. enable ? "enable" : "disable",
  355. dp_parser_pm_name(pm_type), rc);
  356. goto error;
  357. }
  358. if (pm_type == DP_CORE_PM)
  359. power->core_clks_on = enable;
  360. else if (pm_type == DP_STREAM0_PM)
  361. power->strm0_clks_on = enable;
  362. else if (pm_type == DP_STREAM1_PM)
  363. power->strm1_clks_on = enable;
  364. else if (pm_type == DP_LINK_PM)
  365. power->link_clks_on = enable;
  366. if (pm_type == DP_STREAM0_PM)
  367. power->strm0_clks_parked = false;
  368. if (pm_type == DP_STREAM1_PM)
  369. power->strm1_clks_parked = false;
  370. /*
  371. * This log is printed only when user connects or disconnects
  372. * a DP cable. As this is a user-action and not a frequent
  373. * usecase, it is not going to flood the kernel logs. Also,
  374. * helpful in debugging the NOC issues.
  375. */
  376. DP_INFO("core:%s link:%s strm0:%s strm1:%s\n",
  377. power->core_clks_on ? "on" : "off",
  378. power->link_clks_on ? "on" : "off",
  379. power->strm0_clks_on ? "on" : "off",
  380. power->strm1_clks_on ? "on" : "off");
  381. error:
  382. return rc;
  383. }
  384. static bool dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type)
  385. {
  386. struct dp_power_private *power;
  387. if (!dp_power) {
  388. DP_ERR("invalid power data\n");
  389. return false;
  390. }
  391. power = container_of(dp_power, struct dp_power_private, dp_power);
  392. if (pm_type == DP_LINK_PM)
  393. return power->link_clks_on;
  394. else if (pm_type == DP_CORE_PM)
  395. return power->core_clks_on;
  396. else if (pm_type == DP_STREAM0_PM)
  397. return power->strm0_clks_on;
  398. else if (pm_type == DP_STREAM1_PM)
  399. return power->strm1_clks_on;
  400. else
  401. return false;
  402. }
  403. static int dp_power_request_gpios(struct dp_power_private *power)
  404. {
  405. int rc = 0, i;
  406. struct device *dev;
  407. struct dss_module_power *mp;
  408. static const char * const gpio_names[] = {
  409. "aux_enable", "aux_sel", "usbplug_cc",
  410. };
  411. if (!power) {
  412. DP_ERR("invalid power data\n");
  413. return -EINVAL;
  414. }
  415. dev = &power->pdev->dev;
  416. mp = &power->parser->mp[DP_CORE_PM];
  417. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  418. unsigned int gpio = mp->gpio_config[i].gpio;
  419. if (gpio_is_valid(gpio)) {
  420. rc = gpio_request(gpio, gpio_names[i]);
  421. if (rc) {
  422. DP_ERR("request %s gpio failed, rc=%d\n",
  423. gpio_names[i], rc);
  424. goto error;
  425. }
  426. }
  427. }
  428. return 0;
  429. error:
  430. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  431. unsigned int gpio = mp->gpio_config[i].gpio;
  432. if (gpio_is_valid(gpio))
  433. gpio_free(gpio);
  434. }
  435. return rc;
  436. }
  437. static bool dp_power_find_gpio(const char *gpio1, const char *gpio2)
  438. {
  439. return !!strnstr(gpio1, gpio2, strlen(gpio1));
  440. }
  441. static void dp_power_set_gpio(struct dp_power_private *power, bool flip)
  442. {
  443. int i;
  444. struct dss_module_power *mp = &power->parser->mp[DP_CORE_PM];
  445. struct dss_gpio *config = mp->gpio_config;
  446. for (i = 0; i < mp->num_gpio; i++) {
  447. if (dp_power_find_gpio(config->gpio_name, "aux-sel"))
  448. config->value = flip;
  449. if (gpio_is_valid(config->gpio)) {
  450. DP_DEBUG("gpio %s, value %d\n", config->gpio_name,
  451. config->value);
  452. if (dp_power_find_gpio(config->gpio_name, "aux-en") ||
  453. dp_power_find_gpio(config->gpio_name, "aux-sel"))
  454. gpio_direction_output(config->gpio,
  455. config->value);
  456. else
  457. gpio_set_value(config->gpio, config->value);
  458. }
  459. config++;
  460. }
  461. }
  462. static int dp_power_config_gpios(struct dp_power_private *power, bool flip,
  463. bool enable)
  464. {
  465. int rc = 0, i;
  466. struct dss_module_power *mp;
  467. struct dss_gpio *config;
  468. if (power->parser->no_aux_switch)
  469. return 0;
  470. mp = &power->parser->mp[DP_CORE_PM];
  471. config = mp->gpio_config;
  472. if (enable) {
  473. rc = dp_power_request_gpios(power);
  474. if (rc) {
  475. DP_ERR("gpio request failed\n");
  476. return rc;
  477. }
  478. dp_power_set_gpio(power, flip);
  479. } else {
  480. for (i = 0; i < mp->num_gpio; i++) {
  481. if (gpio_is_valid(config[i].gpio)) {
  482. gpio_set_value(config[i].gpio, 0);
  483. gpio_free(config[i].gpio);
  484. }
  485. }
  486. }
  487. return 0;
  488. }
  489. static int dp_power_mmrm_init(struct dp_power *dp_power, struct sde_power_handle *phandle, void *dp,
  490. int (*dp_display_mmrm_callback)(struct mmrm_client_notifier_data *notifier_data))
  491. {
  492. int rc = 0;
  493. enum dp_pm_type module;
  494. struct dp_power_private *power = container_of(dp_power, struct dp_power_private, dp_power);
  495. struct device *dev = &power->pdev->dev;
  496. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  497. struct dss_module_power *pm = &power->parser->mp[module];
  498. if (!pm->num_clk)
  499. continue;
  500. rc = msm_dss_mmrm_register(dev, pm, dp_display_mmrm_callback,
  501. dp, &phandle->mmrm_enable);
  502. if (rc)
  503. DP_ERR("mmrm register failed rc=%d\n", rc);
  504. }
  505. return rc;
  506. }
  507. static int dp_power_client_init(struct dp_power *dp_power,
  508. struct sde_power_handle *phandle, struct drm_device *drm_dev)
  509. {
  510. int rc = 0;
  511. struct dp_power_private *power;
  512. if (!drm_dev) {
  513. DP_ERR("invalid drm_dev\n");
  514. return -EINVAL;
  515. }
  516. power = container_of(dp_power, struct dp_power_private, dp_power);
  517. rc = dp_power_regulator_init(power);
  518. if (rc) {
  519. DP_ERR("failed to init regulators\n");
  520. goto error_power;
  521. }
  522. rc = dp_power_clk_init(power, true);
  523. if (rc) {
  524. DP_ERR("failed to init clocks\n");
  525. goto error_clk;
  526. }
  527. dp_power->phandle = phandle;
  528. dp_power->drm_dev = drm_dev;
  529. return 0;
  530. error_clk:
  531. dp_power_regulator_deinit(power);
  532. error_power:
  533. return rc;
  534. }
  535. static void dp_power_client_deinit(struct dp_power *dp_power)
  536. {
  537. struct dp_power_private *power;
  538. if (!dp_power) {
  539. DP_ERR("invalid power data\n");
  540. return;
  541. }
  542. power = container_of(dp_power, struct dp_power_private, dp_power);
  543. dp_power_clk_init(power, false);
  544. dp_power_regulator_deinit(power);
  545. }
  546. static int dp_power_park_clocks(struct dp_power *dp_power)
  547. {
  548. int rc = 0;
  549. struct dp_power_private *power;
  550. if (!dp_power) {
  551. DP_ERR("invalid power data\n");
  552. return -EINVAL;
  553. }
  554. power = container_of(dp_power, struct dp_power_private, dp_power);
  555. rc = dp_power_park_module(power, DP_STREAM0_PM);
  556. if (rc) {
  557. DP_ERR("failed to park stream 0. err=%d\n", rc);
  558. goto error;
  559. }
  560. rc = dp_power_park_module(power, DP_STREAM1_PM);
  561. if (rc) {
  562. DP_ERR("failed to park stream 1. err=%d\n", rc);
  563. goto error;
  564. }
  565. error:
  566. return rc;
  567. }
  568. static int dp_power_set_pixel_clk_parent(struct dp_power *dp_power, u32 strm_id)
  569. {
  570. int rc = 0;
  571. struct dp_power_private *power;
  572. if (!dp_power || strm_id >= DP_STREAM_MAX) {
  573. DP_ERR("invalid power data. stream %d\n", strm_id);
  574. rc = -EINVAL;
  575. goto exit;
  576. }
  577. power = container_of(dp_power, struct dp_power_private, dp_power);
  578. if (strm_id == DP_STREAM_0) {
  579. if (power->pixel_clk_rcg && power->pixel_parent)
  580. rc = clk_set_parent(power->pixel_clk_rcg,
  581. power->pixel_parent);
  582. else
  583. DP_WARN("skipped for strm_id=%d\n", strm_id);
  584. } else if (strm_id == DP_STREAM_1) {
  585. if (power->pixel1_clk_rcg && power->pixel_parent)
  586. rc = clk_set_parent(power->pixel1_clk_rcg,
  587. power->pixel_parent);
  588. else
  589. DP_WARN("skipped for strm_id=%d\n", strm_id);
  590. }
  591. if (rc)
  592. DP_ERR("failed. strm_id=%d, rc=%d\n", strm_id, rc);
  593. exit:
  594. return rc;
  595. }
  596. static u64 dp_power_clk_get_rate(struct dp_power *dp_power, char *clk_name)
  597. {
  598. size_t i;
  599. enum dp_pm_type j;
  600. struct dss_module_power *mp;
  601. struct dp_power_private *power;
  602. bool clk_found = false;
  603. u64 rate = 0;
  604. if (!clk_name) {
  605. DP_ERR("invalid pointer for clk_name\n");
  606. return 0;
  607. }
  608. power = container_of(dp_power, struct dp_power_private, dp_power);
  609. mp = &dp_power->phandle->mp;
  610. for (i = 0; i < mp->num_clk; i++) {
  611. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  612. rate = clk_get_rate(mp->clk_config[i].clk);
  613. clk_found = true;
  614. break;
  615. }
  616. }
  617. for (j = DP_CORE_PM; j < DP_MAX_PM && !clk_found; j++) {
  618. mp = &power->parser->mp[j];
  619. for (i = 0; i < mp->num_clk; i++) {
  620. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  621. rate = clk_get_rate(mp->clk_config[i].clk);
  622. clk_found = true;
  623. break;
  624. }
  625. }
  626. }
  627. return rate;
  628. }
  629. static int dp_power_init(struct dp_power *dp_power, bool flip)
  630. {
  631. int rc = 0;
  632. struct dp_power_private *power;
  633. if (!dp_power) {
  634. DP_ERR("invalid power data\n");
  635. rc = -EINVAL;
  636. goto exit;
  637. }
  638. power = container_of(dp_power, struct dp_power_private, dp_power);
  639. rc = dp_power_regulator_ctrl(power, true);
  640. if (rc) {
  641. DP_ERR("failed to enable regulators\n");
  642. goto exit;
  643. }
  644. rc = dp_power_pinctrl_set(power, true);
  645. if (rc) {
  646. DP_ERR("failed to set pinctrl state\n");
  647. goto err_pinctrl;
  648. }
  649. rc = dp_power_config_gpios(power, flip, true);
  650. if (rc) {
  651. DP_ERR("failed to enable gpios\n");
  652. goto err_gpio;
  653. }
  654. rc = pm_runtime_get_sync(dp_power->drm_dev->dev);
  655. if (rc < 0) {
  656. DP_ERR("Power resource enable failed\n");
  657. goto err_sde_power;
  658. }
  659. rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
  660. if (rc) {
  661. DP_ERR("failed to enable DP core clocks\n");
  662. goto err_clk;
  663. }
  664. return 0;
  665. err_clk:
  666. pm_runtime_put_sync(dp_power->drm_dev->dev);
  667. err_sde_power:
  668. dp_power_config_gpios(power, flip, false);
  669. err_gpio:
  670. dp_power_pinctrl_set(power, false);
  671. err_pinctrl:
  672. dp_power_regulator_ctrl(power, false);
  673. exit:
  674. return rc;
  675. }
  676. static int dp_power_deinit(struct dp_power *dp_power)
  677. {
  678. int rc = 0;
  679. struct dp_power_private *power;
  680. if (!dp_power) {
  681. DP_ERR("invalid power data\n");
  682. rc = -EINVAL;
  683. goto exit;
  684. }
  685. power = container_of(dp_power, struct dp_power_private, dp_power);
  686. if (power->link_clks_on)
  687. dp_power_clk_enable(dp_power, DP_LINK_PM, false);
  688. dp_power_clk_enable(dp_power, DP_CORE_PM, false);
  689. pm_runtime_put_sync(dp_power->drm_dev->dev);
  690. dp_power_config_gpios(power, false, false);
  691. dp_power_pinctrl_set(power, false);
  692. dp_power_regulator_ctrl(power, false);
  693. exit:
  694. return rc;
  695. }
  696. struct dp_power *dp_power_get(struct dp_parser *parser, struct dp_pll *pll)
  697. {
  698. int rc = 0;
  699. struct dp_power_private *power;
  700. struct dp_power *dp_power;
  701. if (!parser || !pll) {
  702. DP_ERR("invalid input\n");
  703. rc = -EINVAL;
  704. goto error;
  705. }
  706. power = kzalloc(sizeof(*power), GFP_KERNEL);
  707. if (!power) {
  708. rc = -ENOMEM;
  709. goto error;
  710. }
  711. power->parser = parser;
  712. power->pll = pll;
  713. power->pdev = parser->pdev;
  714. dp_power = &power->dp_power;
  715. dp_power->init = dp_power_init;
  716. dp_power->deinit = dp_power_deinit;
  717. dp_power->clk_enable = dp_power_clk_enable;
  718. dp_power->clk_status = dp_power_clk_status;
  719. dp_power->set_pixel_clk_parent = dp_power_set_pixel_clk_parent;
  720. dp_power->park_clocks = dp_power_park_clocks;
  721. dp_power->clk_get_rate = dp_power_clk_get_rate;
  722. dp_power->power_client_init = dp_power_client_init;
  723. dp_power->power_client_deinit = dp_power_client_deinit;
  724. dp_power->power_mmrm_init = dp_power_mmrm_init;
  725. return dp_power;
  726. error:
  727. return ERR_PTR(rc);
  728. }
  729. void dp_power_put(struct dp_power *dp_power)
  730. {
  731. struct dp_power_private *power = NULL;
  732. if (!dp_power)
  733. return;
  734. power = container_of(dp_power, struct dp_power_private, dp_power);
  735. kfree(power);
  736. }