dp_rx_err.c 35 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "dp_types.h"
  19. #include "dp_rx.h"
  20. #include "dp_peer.h"
  21. #include "dp_internal.h"
  22. #include "hal_api.h"
  23. #include "qdf_trace.h"
  24. #include "qdf_nbuf.h"
  25. #ifdef CONFIG_MCL
  26. #include <cds_ieee80211_common.h>
  27. #else
  28. #include <linux/ieee80211.h>
  29. #endif
  30. #include "dp_rx_defrag.h"
  31. #include <enet.h> /* LLC_SNAP_HDR_LEN */
  32. #ifdef RX_DESC_DEBUG_CHECK
  33. static inline bool dp_rx_desc_check_magic(struct dp_rx_desc *rx_desc)
  34. {
  35. if (qdf_unlikely(rx_desc->magic != DP_RX_DESC_MAGIC)) {
  36. return false;
  37. }
  38. rx_desc->magic = 0;
  39. return true;
  40. }
  41. #else
  42. static inline bool dp_rx_desc_check_magic(struct dp_rx_desc *rx_desc)
  43. {
  44. return true;
  45. }
  46. #endif
  47. /**
  48. * dp_rx_link_desc_return() - Return a MPDU link descriptor to HW
  49. * (WBM), following error handling
  50. *
  51. * @soc: core DP main context
  52. * @ring_desc: opaque pointer to the REO error ring descriptor
  53. *
  54. * Return: QDF_STATUS
  55. */
  56. static QDF_STATUS
  57. dp_rx_link_desc_return(struct dp_soc *soc, void *ring_desc, uint8_t bm_action)
  58. {
  59. void *buf_addr_info = HAL_RX_REO_BUF_ADDR_INFO_GET(ring_desc);
  60. struct dp_srng *wbm_desc_rel_ring = &soc->wbm_desc_rel_ring;
  61. void *wbm_rel_srng = wbm_desc_rel_ring->hal_srng;
  62. void *hal_soc = soc->hal_soc;
  63. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  64. void *src_srng_desc;
  65. if (!wbm_rel_srng) {
  66. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  67. "WBM RELEASE RING not initialized");
  68. return status;
  69. }
  70. if (qdf_unlikely(hal_srng_access_start(hal_soc, wbm_rel_srng))) {
  71. /* TODO */
  72. /*
  73. * Need API to convert from hal_ring pointer to
  74. * Ring Type / Ring Id combo
  75. */
  76. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  77. FL("HAL RING Access For WBM Release SRNG Failed - %pK"),
  78. wbm_rel_srng);
  79. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  80. goto done;
  81. }
  82. src_srng_desc = hal_srng_src_get_next(hal_soc, wbm_rel_srng);
  83. if (qdf_likely(src_srng_desc)) {
  84. /* Return link descriptor through WBM ring (SW2WBM)*/
  85. hal_rx_msdu_link_desc_set(hal_soc,
  86. src_srng_desc, buf_addr_info, bm_action);
  87. status = QDF_STATUS_SUCCESS;
  88. } else {
  89. struct hal_srng *srng = (struct hal_srng *)wbm_rel_srng;
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  91. FL("WBM Release Ring (Id %d) Full"), srng->ring_id);
  92. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  93. "HP 0x%x Reap HP 0x%x TP 0x%x Cached TP 0x%x",
  94. *srng->u.src_ring.hp_addr, srng->u.src_ring.reap_hp,
  95. *srng->u.src_ring.tp_addr, srng->u.src_ring.cached_tp);
  96. }
  97. done:
  98. hal_srng_access_end(hal_soc, wbm_rel_srng);
  99. return status;
  100. }
  101. /**
  102. * dp_rx_msdus_drop() - Drops all MSDU's per MPDU
  103. *
  104. * @soc: core txrx main context
  105. * @ring_desc: opaque pointer to the REO error ring descriptor
  106. * @mpdu_desc_info: MPDU descriptor information from ring descriptor
  107. * @head: head of the local descriptor free-list
  108. * @tail: tail of the local descriptor free-list
  109. * @quota: No. of units (packets) that can be serviced in one shot.
  110. *
  111. * This function is used to drop all MSDU in an MPDU
  112. *
  113. * Return: uint32_t: No. of elements processed
  114. */
  115. static uint32_t dp_rx_msdus_drop(struct dp_soc *soc, void *ring_desc,
  116. struct hal_rx_mpdu_desc_info *mpdu_desc_info,
  117. union dp_rx_desc_list_elem_t **head,
  118. union dp_rx_desc_list_elem_t **tail,
  119. uint32_t quota)
  120. {
  121. uint32_t rx_bufs_used = 0;
  122. void *link_desc_va;
  123. struct hal_buf_info buf_info;
  124. struct hal_rx_msdu_list msdu_list; /* MSDU's per MPDU */
  125. int i;
  126. uint8_t *rx_tlv_hdr;
  127. uint32_t tid;
  128. hal_rx_reo_buf_paddr_get(ring_desc, &buf_info);
  129. link_desc_va = dp_rx_cookie_2_link_desc_va(soc, &buf_info);
  130. /* No UNMAP required -- this is "malloc_consistent" memory */
  131. hal_rx_msdu_list_get(link_desc_va, &msdu_list,
  132. &mpdu_desc_info->msdu_count);
  133. for (i = 0; (i < mpdu_desc_info->msdu_count) && quota--; i++) {
  134. struct dp_rx_desc *rx_desc =
  135. dp_rx_cookie_2_va_rxdma_buf(soc,
  136. msdu_list.sw_cookie[i]);
  137. qdf_assert(rx_desc);
  138. if (!dp_rx_desc_check_magic(rx_desc)) {
  139. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  140. FL("Invalid rx_desc cookie=%d"),
  141. msdu_list.sw_cookie[i]);
  142. return rx_bufs_used;
  143. }
  144. rx_bufs_used++;
  145. tid = hal_rx_mpdu_start_tid_get(rx_desc->rx_buf_start);
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "Packet received with PN error for tid :%d", tid);
  148. rx_tlv_hdr = qdf_nbuf_data(rx_desc->nbuf);
  149. if (hal_rx_encryption_info_valid(rx_tlv_hdr))
  150. hal_rx_print_pn(rx_tlv_hdr);
  151. /* Just free the buffers */
  152. qdf_nbuf_free(rx_desc->nbuf);
  153. dp_rx_add_to_free_desc_list(head, tail, rx_desc);
  154. }
  155. /* Return link descriptor through WBM ring (SW2WBM)*/
  156. dp_rx_link_desc_return(soc, ring_desc, HAL_BM_ACTION_PUT_IN_IDLE_LIST);
  157. return rx_bufs_used;
  158. }
  159. /**
  160. * dp_rx_pn_error_handle() - Handles PN check errors
  161. *
  162. * @soc: core txrx main context
  163. * @ring_desc: opaque pointer to the REO error ring descriptor
  164. * @mpdu_desc_info: MPDU descriptor information from ring descriptor
  165. * @head: head of the local descriptor free-list
  166. * @tail: tail of the local descriptor free-list
  167. * @quota: No. of units (packets) that can be serviced in one shot.
  168. *
  169. * This function implements PN error handling
  170. * If the peer is configured to ignore the PN check errors
  171. * or if DP feels, that this frame is still OK, the frame can be
  172. * re-injected back to REO to use some of the other features
  173. * of REO e.g. duplicate detection/routing to other cores
  174. *
  175. * Return: uint32_t: No. of elements processed
  176. */
  177. static uint32_t
  178. dp_rx_pn_error_handle(struct dp_soc *soc, void *ring_desc,
  179. struct hal_rx_mpdu_desc_info *mpdu_desc_info,
  180. union dp_rx_desc_list_elem_t **head,
  181. union dp_rx_desc_list_elem_t **tail,
  182. uint32_t quota)
  183. {
  184. uint16_t peer_id;
  185. uint32_t rx_bufs_used = 0;
  186. struct dp_peer *peer;
  187. bool peer_pn_policy = false;
  188. peer_id = DP_PEER_METADATA_PEER_ID_GET(
  189. mpdu_desc_info->peer_meta_data);
  190. peer = dp_peer_find_by_id(soc, peer_id);
  191. if (qdf_likely(peer)) {
  192. /*
  193. * TODO: Check for peer specific policies & set peer_pn_policy
  194. */
  195. }
  196. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  197. "Packet received with PN error");
  198. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  199. "discard rx due to PN error for peer %pK "
  200. "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
  201. peer,
  202. peer->mac_addr.raw[0], peer->mac_addr.raw[1],
  203. peer->mac_addr.raw[2], peer->mac_addr.raw[3],
  204. peer->mac_addr.raw[4], peer->mac_addr.raw[5]);
  205. /* No peer PN policy -- definitely drop */
  206. if (!peer_pn_policy)
  207. rx_bufs_used = dp_rx_msdus_drop(soc, ring_desc,
  208. mpdu_desc_info,
  209. head, tail, quota);
  210. return rx_bufs_used;
  211. }
  212. /**
  213. * dp_rx_2k_jump_handle() - Handles Sequence Number Jump by 2K
  214. *
  215. * @soc: core txrx main context
  216. * @ring_desc: opaque pointer to the REO error ring descriptor
  217. * @mpdu_desc_info: MPDU descriptor information from ring descriptor
  218. * @head: head of the local descriptor free-list
  219. * @tail: tail of the local descriptor free-list
  220. * @quota: No. of units (packets) that can be serviced in one shot.
  221. *
  222. * This function implements the error handling when sequence number
  223. * of the MPDU jumps suddenly by 2K.Today there are 2 cases that
  224. * need to be handled:
  225. * A) CSN (Current Sequence Number) = Last Valid SN (LSN) + 2K
  226. * B) CSN = LSN + 2K, but falls within a "BA sized window" of the SSN
  227. * For case A) the protocol stack is invoked to generate DELBA/DEAUTH frame
  228. * For case B), the frame is normally dropped, no more action is taken
  229. *
  230. * Return: uint32_t: No. of elements processed
  231. */
  232. static uint32_t
  233. dp_rx_2k_jump_handle(struct dp_soc *soc, void *ring_desc,
  234. struct hal_rx_mpdu_desc_info *mpdu_desc_info,
  235. union dp_rx_desc_list_elem_t **head,
  236. union dp_rx_desc_list_elem_t **tail,
  237. uint32_t quota)
  238. {
  239. return dp_rx_msdus_drop(soc, ring_desc, mpdu_desc_info,
  240. head, tail, quota);
  241. }
  242. static bool
  243. dp_rx_chain_msdus(struct dp_soc *soc, qdf_nbuf_t nbuf,
  244. struct dp_rx_desc *rx_desc, uint8_t mac_id)
  245. {
  246. bool mpdu_done = false;
  247. /* TODO: Currently only single radio is supported, hence
  248. * pdev hard coded to '0' index
  249. */
  250. struct dp_pdev *dp_pdev = soc->pdev_list[mac_id];
  251. if (hal_rx_msdu_end_first_msdu_get(rx_desc->rx_buf_start)) {
  252. qdf_nbuf_set_chfrag_start(rx_desc->nbuf, 1);
  253. dp_pdev->invalid_peer_head_msdu = NULL;
  254. dp_pdev->invalid_peer_tail_msdu = NULL;
  255. hal_rx_mon_hw_desc_get_mpdu_status(rx_desc->rx_buf_start,
  256. &(dp_pdev->ppdu_info.rx_status));
  257. }
  258. if (hal_rx_msdu_end_last_msdu_get(rx_desc->rx_buf_start)) {
  259. qdf_nbuf_set_chfrag_end(rx_desc->nbuf, 1);
  260. mpdu_done = true;
  261. }
  262. DP_RX_LIST_APPEND(dp_pdev->invalid_peer_head_msdu,
  263. dp_pdev->invalid_peer_tail_msdu,
  264. nbuf);
  265. return mpdu_done;
  266. }
  267. /**
  268. * dp_rx_null_q_desc_handle() - Function to handle NULL Queue
  269. * descriptor violation on either a
  270. * REO or WBM ring
  271. *
  272. * @soc: core DP main context
  273. * @rx_desc : pointer to the sw rx descriptor
  274. * @head: pointer to head of rx descriptors to be added to free list
  275. * @tail: pointer to tail of rx descriptors to be added to free list
  276. * quota: upper limit of descriptors that can be reaped
  277. *
  278. * This function handles NULL queue descriptor violations arising out
  279. * a missing REO queue for a given peer or a given TID. This typically
  280. * may happen if a packet is received on a QOS enabled TID before the
  281. * ADDBA negotiation for that TID, when the TID queue is setup. Or
  282. * it may also happen for MC/BC frames if they are not routed to the
  283. * non-QOS TID queue, in the absence of any other default TID queue.
  284. * This error can show up both in a REO destination or WBM release ring.
  285. *
  286. * Return: uint32_t: No. of Rx buffers reaped
  287. */
  288. static uint32_t
  289. dp_rx_null_q_desc_handle(struct dp_soc *soc, struct dp_rx_desc *rx_desc,
  290. union dp_rx_desc_list_elem_t **head,
  291. union dp_rx_desc_list_elem_t **tail,
  292. uint32_t quota)
  293. {
  294. uint32_t rx_bufs_used = 0;
  295. uint32_t pkt_len, l2_hdr_offset;
  296. uint16_t msdu_len;
  297. qdf_nbuf_t nbuf;
  298. struct dp_vdev *vdev;
  299. uint16_t peer_id = 0xFFFF;
  300. struct dp_peer *peer = NULL;
  301. uint32_t sgi, rate_mcs, tid;
  302. struct dp_ast_entry *ase;
  303. uint16_t sa_idx;
  304. uint8_t *data;
  305. uint8_t pool_id;
  306. rx_bufs_used++;
  307. nbuf = rx_desc->nbuf;
  308. qdf_nbuf_unmap_single(soc->osdev, nbuf,
  309. QDF_DMA_BIDIRECTIONAL);
  310. rx_desc->rx_buf_start = qdf_nbuf_data(nbuf);
  311. pool_id = rx_desc->pool_id;
  312. l2_hdr_offset =
  313. hal_rx_msdu_end_l3_hdr_padding_get(rx_desc->rx_buf_start);
  314. msdu_len = hal_rx_msdu_start_msdu_len_get(rx_desc->rx_buf_start);
  315. pkt_len = msdu_len + l2_hdr_offset + RX_PKT_TLVS_LEN;
  316. /* Set length in nbuf */
  317. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  318. /*
  319. * Check if DMA completed -- msdu_done is the last bit
  320. * to be written
  321. */
  322. if (!hal_rx_attn_msdu_done_get(rx_desc->rx_buf_start)) {
  323. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  324. FL("MSDU DONE failure"));
  325. hal_rx_dump_pkt_tlvs(rx_desc->rx_buf_start,
  326. QDF_TRACE_LEVEL_INFO);
  327. qdf_assert(0);
  328. }
  329. peer_id = hal_rx_mpdu_start_sw_peer_id_get(rx_desc->rx_buf_start);
  330. peer = dp_peer_find_by_id(soc, peer_id);
  331. if (!peer) {
  332. bool mpdu_done = false;
  333. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  334. FL("peer is NULL"));
  335. mpdu_done = dp_rx_chain_msdus(soc, nbuf, rx_desc, pool_id);
  336. if (mpdu_done)
  337. dp_rx_process_invalid_peer(soc, nbuf);
  338. dp_rx_add_to_free_desc_list(head, tail, rx_desc);
  339. return rx_bufs_used;
  340. }
  341. vdev = peer->vdev;
  342. if (!vdev) {
  343. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  344. FL("INVALID vdev %pK OR osif_rx"), vdev);
  345. /* Drop & free packet */
  346. qdf_nbuf_free(nbuf);
  347. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  348. goto fail;
  349. }
  350. sgi = hal_rx_msdu_start_sgi_get(rx_desc->rx_buf_start);
  351. rate_mcs = hal_rx_msdu_start_rate_mcs_get(rx_desc->rx_buf_start);
  352. tid = hal_rx_mpdu_start_tid_get(rx_desc->rx_buf_start);
  353. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  354. "%s: %d, SGI: %d, rate_mcs: %d, tid: %d",
  355. __func__, __LINE__, sgi, rate_mcs, tid);
  356. /*
  357. * Advance the packet start pointer by total size of
  358. * pre-header TLV's
  359. */
  360. qdf_nbuf_pull_head(nbuf, (l2_hdr_offset + RX_PKT_TLVS_LEN));
  361. /*
  362. * Multicast Echo Check is required only if vdev is STA and
  363. * received pkt is a multicast/broadcast pkt. otherwise
  364. * skip the MEC check.
  365. */
  366. if (vdev->opmode != wlan_op_mode_sta)
  367. goto skip_mec_check;
  368. if (!hal_rx_msdu_end_da_is_mcbc_get(rx_desc->rx_buf_start))
  369. goto skip_mec_check;
  370. data = qdf_nbuf_data(nbuf);
  371. /*
  372. * if the received pkts src mac addr matches with vdev
  373. * mac address then drop the pkt as it is looped back
  374. */
  375. if (!(memcmp(&data[DP_MAC_ADDR_LEN],
  376. vdev->mac_addr.raw,
  377. DP_MAC_ADDR_LEN))) {
  378. qdf_nbuf_free(nbuf);
  379. goto fail;
  380. }
  381. /* if the received pkts src mac addr matches with the
  382. * wired PCs MAC addr which is behind the STA or with
  383. * wireless STAs MAC addr which are behind the Repeater,
  384. * then drop the pkt as it is looped back
  385. */
  386. qdf_spin_lock_bh(&soc->ast_lock);
  387. if (hal_rx_msdu_end_sa_is_valid_get(rx_desc->rx_buf_start)) {
  388. sa_idx = hal_rx_msdu_end_sa_idx_get(rx_desc->rx_buf_start);
  389. if ((sa_idx < 0) || (sa_idx > (WLAN_UMAC_PSOC_MAX_PEERS * 2))) {
  390. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  391. "invalid sa_idx: %d", sa_idx);
  392. qdf_assert_always(0);
  393. }
  394. ase = soc->ast_table[sa_idx];
  395. } else
  396. ase = dp_peer_ast_hash_find(soc, &data[DP_MAC_ADDR_LEN], 0);
  397. if (ase) {
  398. if ((ase->type == CDP_TXRX_AST_TYPE_MEC) ||
  399. (ase->peer != peer)) {
  400. qdf_spin_unlock_bh(&soc->ast_lock);
  401. QDF_TRACE(QDF_MODULE_ID_DP,
  402. QDF_TRACE_LEVEL_INFO,
  403. "received pkt with same src mac %pM",
  404. &data[DP_MAC_ADDR_LEN]);
  405. qdf_nbuf_free(nbuf);
  406. goto fail;
  407. }
  408. }
  409. qdf_spin_unlock_bh(&soc->ast_lock);
  410. skip_mec_check:
  411. /* WDS Source Port Learning */
  412. if (qdf_likely(vdev->rx_decap_type == htt_cmn_pkt_type_ethernet))
  413. dp_rx_wds_srcport_learn(soc, rx_desc->rx_buf_start, peer, nbuf);
  414. if (hal_rx_mpdu_start_mpdu_qos_control_valid_get(
  415. rx_desc->rx_buf_start)) {
  416. /* TODO: Assuming that qos_control_valid also indicates
  417. * unicast. Should we check this?
  418. */
  419. if (peer &&
  420. peer->rx_tid[tid].hw_qdesc_vaddr_unaligned == NULL) {
  421. /* IEEE80211_SEQ_MAX indicates invalid start_seq */
  422. dp_rx_tid_setup_wifi3(peer, tid, 1, IEEE80211_SEQ_MAX);
  423. }
  424. }
  425. #ifdef QCA_WIFI_NAPIER_EMULATION /* Debug code, remove later */
  426. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  427. "%s: p_id %d msdu_len %d hdr_off %d",
  428. __func__, peer_id, msdu_len, l2_hdr_offset);
  429. print_hex_dump(KERN_ERR,
  430. "\t Pkt Data:", DUMP_PREFIX_NONE, 32, 4,
  431. qdf_nbuf_data(nbuf), 128, false);
  432. #endif /* NAPIER_EMULATION */
  433. if (qdf_unlikely(vdev->rx_decap_type == htt_cmn_pkt_type_raw)) {
  434. qdf_nbuf_set_next(nbuf, NULL);
  435. dp_rx_deliver_raw(vdev, nbuf, peer);
  436. } else {
  437. if (qdf_unlikely(peer->bss_peer)) {
  438. QDF_TRACE(QDF_MODULE_ID_DP,
  439. QDF_TRACE_LEVEL_INFO,
  440. FL("received pkt with same src MAC"));
  441. /* Drop & free packet */
  442. qdf_nbuf_free(nbuf);
  443. goto fail;
  444. }
  445. if (vdev->osif_rx) {
  446. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  447. FL("vdev %pK osif_rx %pK"), vdev,
  448. vdev->osif_rx);
  449. qdf_nbuf_set_next(nbuf, NULL);
  450. vdev->osif_rx(vdev->osif_vdev, nbuf);
  451. DP_STATS_INC(vdev->pdev, rx.to_stack.num, 1);
  452. } else {
  453. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  454. FL("INVALID vdev %pK OR osif_rx"), vdev);
  455. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  456. }
  457. }
  458. fail:
  459. dp_rx_add_to_free_desc_list(head, tail, rx_desc);
  460. return rx_bufs_used;
  461. }
  462. /**
  463. * dp_rx_err_deliver() - Function to deliver error frames to OS
  464. *
  465. * @soc: core DP main context
  466. * @rx_desc : pointer to the sw rx descriptor
  467. * @head: pointer to head of rx descriptors to be added to free list
  468. * @tail: pointer to tail of rx descriptors to be added to free list
  469. * quota: upper limit of descriptors that can be reaped
  470. *
  471. * Return: uint32_t: No. of Rx buffers reaped
  472. */
  473. static uint32_t
  474. dp_rx_err_deliver(struct dp_soc *soc, struct dp_rx_desc *rx_desc,
  475. union dp_rx_desc_list_elem_t **head,
  476. union dp_rx_desc_list_elem_t **tail,
  477. uint32_t quota)
  478. {
  479. uint32_t rx_bufs_used = 0;
  480. uint32_t pkt_len, l2_hdr_offset;
  481. uint16_t msdu_len;
  482. qdf_nbuf_t nbuf;
  483. struct dp_vdev *vdev;
  484. uint16_t peer_id = 0xFFFF;
  485. struct dp_peer *peer = NULL;
  486. rx_bufs_used++;
  487. nbuf = rx_desc->nbuf;
  488. qdf_nbuf_unmap_single(soc->osdev, nbuf,
  489. QDF_DMA_BIDIRECTIONAL);
  490. rx_desc->rx_buf_start = qdf_nbuf_data(nbuf);
  491. /*
  492. * Check if DMA completed -- msdu_done is the last bit
  493. * to be written
  494. */
  495. if (!hal_rx_attn_msdu_done_get(rx_desc->rx_buf_start)) {
  496. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  497. FL("MSDU DONE failure"));
  498. hal_rx_dump_pkt_tlvs(rx_desc->rx_buf_start,
  499. QDF_TRACE_LEVEL_INFO);
  500. qdf_assert(0);
  501. }
  502. peer_id = hal_rx_mpdu_start_sw_peer_id_get(rx_desc->rx_buf_start);
  503. peer = dp_peer_find_by_id(soc, peer_id);
  504. if (!peer) {
  505. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  506. FL("peer is NULL"));
  507. DP_STATS_INC_PKT(soc, rx.err.rx_invalid_peer, 1,
  508. qdf_nbuf_len(nbuf));
  509. /* Drop & free packet */
  510. qdf_nbuf_free(nbuf);
  511. goto fail;
  512. }
  513. vdev = peer->vdev;
  514. if (!vdev) {
  515. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  516. FL("INVALID vdev %pK OR osif_rx"), vdev);
  517. /* Drop & free packet */
  518. qdf_nbuf_free(nbuf);
  519. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  520. goto fail;
  521. }
  522. /* Drop & free packet if mesh mode not enabled */
  523. if (!vdev->mesh_vdev) {
  524. qdf_nbuf_free(nbuf);
  525. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  526. goto fail;
  527. }
  528. l2_hdr_offset =
  529. hal_rx_msdu_end_l3_hdr_padding_get(rx_desc->rx_buf_start);
  530. msdu_len =
  531. hal_rx_msdu_start_msdu_len_get(rx_desc->rx_buf_start);
  532. pkt_len = msdu_len + l2_hdr_offset + RX_PKT_TLVS_LEN;
  533. /* Set length in nbuf */
  534. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  535. qdf_nbuf_set_next(nbuf, NULL);
  536. /*
  537. * Advance the packet start pointer by total size of
  538. * pre-header TLV's
  539. */
  540. qdf_nbuf_pull_head(nbuf, (l2_hdr_offset + RX_PKT_TLVS_LEN));
  541. qdf_nbuf_set_chfrag_start(nbuf, 1);
  542. qdf_nbuf_set_chfrag_end(nbuf, 1);
  543. if (dp_rx_filter_mesh_packets(vdev, nbuf,
  544. rx_desc->rx_buf_start)
  545. == QDF_STATUS_SUCCESS) {
  546. QDF_TRACE(QDF_MODULE_ID_DP,
  547. QDF_TRACE_LEVEL_INFO_MED,
  548. FL("mesh pkt filtered"));
  549. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  550. 1);
  551. qdf_nbuf_free(nbuf);
  552. goto fail;
  553. }
  554. dp_rx_fill_mesh_stats(vdev, nbuf, rx_desc->rx_buf_start, peer);
  555. if (qdf_unlikely(vdev->rx_decap_type == htt_cmn_pkt_type_raw)) {
  556. dp_rx_deliver_raw(vdev, nbuf, peer);
  557. } else {
  558. DP_STATS_INC(vdev->pdev, rx.to_stack.num, 1);
  559. vdev->osif_rx(vdev->osif_vdev, nbuf);
  560. }
  561. fail:
  562. dp_rx_add_to_free_desc_list(head, tail, rx_desc);
  563. return rx_bufs_used;
  564. }
  565. /**
  566. * dp_rx_process_mic_error(): Function to pass mic error indication to umac
  567. * @soc: DP SOC handle
  568. * @rx_desc : pointer to the sw rx descriptor
  569. * @head: pointer to head of rx descriptors to be added to free list
  570. * @tail: pointer to tail of rx descriptors to be added to free list
  571. *
  572. * return: void
  573. */
  574. static void
  575. dp_rx_process_mic_error(struct dp_soc *soc, struct dp_rx_desc *rx_desc,
  576. union dp_rx_desc_list_elem_t **head,
  577. union dp_rx_desc_list_elem_t **tail)
  578. {
  579. struct dp_vdev *vdev = NULL;
  580. struct dp_pdev *pdev = NULL;
  581. struct ol_if_ops *tops = NULL;
  582. qdf_nbuf_t nbuf;
  583. struct ieee80211_frame *wh;
  584. uint8_t *rx_pkt_hdr;
  585. uint8_t *rx_tlv_hdr;
  586. uint8_t i;
  587. nbuf = rx_desc->nbuf;
  588. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  589. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  590. if (!hal_rx_msdu_end_first_msdu_get(rx_tlv_hdr))
  591. goto fail;
  592. rx_pkt_hdr = hal_rx_pkt_hdr_get(qdf_nbuf_data(nbuf));
  593. wh = (struct ieee80211_frame *)rx_pkt_hdr;
  594. for (i = 0; i < MAX_PDEV_CNT; i++) {
  595. pdev = soc->pdev_list[i];
  596. if (!pdev) {
  597. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  598. "PDEV not found");
  599. continue;
  600. }
  601. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  602. if (qdf_mem_cmp(wh->i_addr1, vdev->mac_addr.raw,
  603. DP_MAC_ADDR_LEN) == 0) {
  604. goto out;
  605. }
  606. }
  607. }
  608. if (!vdev) {
  609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  610. "VDEV not found");
  611. goto fail;
  612. }
  613. out:
  614. tops = pdev->soc->cdp_soc.ol_ops;
  615. if (tops->rx_mic_error)
  616. tops->rx_mic_error(pdev->osif_pdev, vdev->vdev_id, wh);
  617. fail:
  618. qdf_nbuf_free(rx_desc->nbuf);
  619. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  620. &tail[rx_desc->pool_id], rx_desc);
  621. return;
  622. }
  623. /**
  624. * dp_rx_err_process() - Processes error frames routed to REO error ring
  625. *
  626. * @soc: core txrx main context
  627. * @hal_ring: opaque pointer to the HAL Rx Error Ring, which will be serviced
  628. * @quota: No. of units (packets) that can be serviced in one shot.
  629. *
  630. * This function implements error processing and top level demultiplexer
  631. * for all the frames routed to REO error ring.
  632. *
  633. * Return: uint32_t: No. of elements processed
  634. */
  635. uint32_t
  636. dp_rx_err_process(struct dp_soc *soc, void *hal_ring, uint32_t quota)
  637. {
  638. void *hal_soc;
  639. void *ring_desc;
  640. union dp_rx_desc_list_elem_t *head = NULL;
  641. union dp_rx_desc_list_elem_t *tail = NULL;
  642. uint32_t rx_bufs_used = 0;
  643. uint8_t buf_type;
  644. uint8_t error, rbm;
  645. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  646. struct hal_buf_info hbi;
  647. struct dp_pdev *dp_pdev;
  648. struct dp_srng *dp_rxdma_srng;
  649. struct rx_desc_pool *rx_desc_pool;
  650. uint32_t cookie = 0;
  651. void *link_desc_va;
  652. struct hal_rx_msdu_list msdu_list; /* MSDU's per MPDU */
  653. uint16_t num_msdus;
  654. /* Debug -- Remove later */
  655. qdf_assert(soc && hal_ring);
  656. hal_soc = soc->hal_soc;
  657. /* Debug -- Remove later */
  658. qdf_assert(hal_soc);
  659. if (qdf_unlikely(hal_srng_access_start(hal_soc, hal_ring))) {
  660. /* TODO */
  661. /*
  662. * Need API to convert from hal_ring pointer to
  663. * Ring Type / Ring Id combo
  664. */
  665. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  666. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  667. FL("HAL RING Access Failed -- %pK"), hal_ring);
  668. goto done;
  669. }
  670. while (qdf_likely(quota-- && (ring_desc =
  671. hal_srng_dst_get_next(hal_soc, hal_ring)))) {
  672. DP_STATS_INC(soc, rx.err_ring_pkts, 1);
  673. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  674. qdf_assert(error == HAL_REO_ERROR_DETECTED);
  675. buf_type = HAL_RX_REO_BUF_TYPE_GET(ring_desc);
  676. /*
  677. * For REO error ring, expect only MSDU LINK DESC
  678. */
  679. qdf_assert_always(buf_type == HAL_RX_REO_MSDU_LINK_DESC_TYPE);
  680. cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  681. /*
  682. * check for the magic number in the sw cookie
  683. */
  684. qdf_assert_always((cookie >> LINK_DESC_ID_SHIFT) &
  685. LINK_DESC_ID_START);
  686. /*
  687. * Check if the buffer is to be processed on this processor
  688. */
  689. rbm = hal_rx_ret_buf_manager_get(ring_desc);
  690. hal_rx_reo_buf_paddr_get(ring_desc, &hbi);
  691. link_desc_va = dp_rx_cookie_2_link_desc_va(soc, &hbi);
  692. hal_rx_msdu_list_get(link_desc_va, &msdu_list, &num_msdus);
  693. if (qdf_unlikely(msdu_list.rbm[0] != HAL_RX_BUF_RBM_SW3_BM)) {
  694. /* TODO */
  695. /* Call appropriate handler */
  696. DP_STATS_INC(soc, rx.err.invalid_rbm, 1);
  697. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  698. FL("Invalid RBM %d"), rbm);
  699. /* Return link descriptor through WBM ring (SW2WBM)*/
  700. dp_rx_link_desc_return(soc, ring_desc,
  701. HAL_BM_ACTION_RELEASE_MSDU_LIST);
  702. continue;
  703. }
  704. /* Get the MPDU DESC info */
  705. hal_rx_mpdu_desc_info_get(ring_desc, &mpdu_desc_info);
  706. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_FRAGMENT) {
  707. /* TODO */
  708. rx_bufs_used += dp_rx_frag_handle(soc,
  709. ring_desc, &mpdu_desc_info,
  710. &head, &tail, quota);
  711. DP_STATS_INC(soc, rx.rx_frags, 1);
  712. continue;
  713. }
  714. if (hal_rx_reo_is_pn_error(ring_desc)) {
  715. /* TOD0 */
  716. DP_STATS_INC(soc,
  717. rx.err.
  718. reo_error[HAL_REO_ERR_PN_CHECK_FAILED],
  719. 1);
  720. rx_bufs_used += dp_rx_pn_error_handle(soc,
  721. ring_desc, &mpdu_desc_info,
  722. &head, &tail, quota);
  723. continue;
  724. }
  725. if (hal_rx_reo_is_2k_jump(ring_desc)) {
  726. /* TOD0 */
  727. DP_STATS_INC(soc,
  728. rx.err.
  729. reo_error[HAL_REO_ERR_REGULAR_FRAME_2K_JUMP],
  730. 1);
  731. rx_bufs_used += dp_rx_2k_jump_handle(soc,
  732. ring_desc, &mpdu_desc_info,
  733. &head, &tail, quota);
  734. continue;
  735. }
  736. }
  737. done:
  738. hal_srng_access_end(hal_soc, hal_ring);
  739. /* Assume MAC id = 0, owner = 0 */
  740. if (rx_bufs_used) {
  741. dp_pdev = soc->pdev_list[0];
  742. dp_rxdma_srng = &dp_pdev->rx_refill_buf_ring;
  743. rx_desc_pool = &soc->rx_desc_buf[0];
  744. dp_rx_buffers_replenish(soc, 0, dp_rxdma_srng, rx_desc_pool,
  745. rx_bufs_used, &head, &tail, HAL_RX_BUF_RBM_SW3_BM);
  746. }
  747. return rx_bufs_used; /* Assume no scale factor for now */
  748. }
  749. /**
  750. * dp_rx_wbm_err_process() - Processes error frames routed to WBM release ring
  751. *
  752. * @soc: core txrx main context
  753. * @hal_ring: opaque pointer to the HAL Rx Error Ring, which will be serviced
  754. * @quota: No. of units (packets) that can be serviced in one shot.
  755. *
  756. * This function implements error processing and top level demultiplexer
  757. * for all the frames routed to WBM2HOST sw release ring.
  758. *
  759. * Return: uint32_t: No. of elements processed
  760. */
  761. uint32_t
  762. dp_rx_wbm_err_process(struct dp_soc *soc, void *hal_ring, uint32_t quota)
  763. {
  764. void *hal_soc;
  765. void *ring_desc;
  766. struct dp_rx_desc *rx_desc;
  767. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT] = { NULL };
  768. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT] = { NULL };
  769. uint32_t rx_bufs_used[MAX_PDEV_CNT] = { 0 };
  770. uint32_t rx_bufs_reaped = 0;
  771. uint8_t buf_type, rbm;
  772. uint8_t wbm_err_src;
  773. uint32_t rx_buf_cookie;
  774. uint8_t mac_id;
  775. struct dp_pdev *dp_pdev;
  776. struct dp_srng *dp_rxdma_srng;
  777. struct rx_desc_pool *rx_desc_pool;
  778. uint8_t pool_id;
  779. /* Debug -- Remove later */
  780. qdf_assert(soc && hal_ring);
  781. hal_soc = soc->hal_soc;
  782. /* Debug -- Remove later */
  783. qdf_assert(hal_soc);
  784. if (qdf_unlikely(hal_srng_access_start(hal_soc, hal_ring))) {
  785. /* TODO */
  786. /*
  787. * Need API to convert from hal_ring pointer to
  788. * Ring Type / Ring Id combo
  789. */
  790. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  791. FL("HAL RING Access Failed -- %pK"), hal_ring);
  792. goto done;
  793. }
  794. while (qdf_likely(quota-- && (ring_desc =
  795. hal_srng_dst_get_next(hal_soc, hal_ring)))) {
  796. /* XXX */
  797. wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(ring_desc);
  798. qdf_assert((wbm_err_src == HAL_RX_WBM_ERR_SRC_RXDMA) ||
  799. (wbm_err_src == HAL_RX_WBM_ERR_SRC_REO));
  800. /*
  801. * Check if the buffer is to be processed on this processor
  802. */
  803. rbm = hal_rx_ret_buf_manager_get(ring_desc);
  804. if (qdf_unlikely(rbm != HAL_RX_BUF_RBM_SW3_BM)) {
  805. /* TODO */
  806. /* Call appropriate handler */
  807. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  808. FL("Invalid RBM %d"), rbm);
  809. continue;
  810. }
  811. rx_buf_cookie = HAL_RX_WBM_BUF_COOKIE_GET(ring_desc);
  812. rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, rx_buf_cookie);
  813. qdf_assert(rx_desc);
  814. if (!dp_rx_desc_check_magic(rx_desc)) {
  815. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  816. FL("Invalid rx_desc cookie=%d"),
  817. rx_buf_cookie);
  818. continue;
  819. }
  820. pool_id = rx_desc->pool_id;
  821. /* XXX */
  822. buf_type = HAL_RX_WBM_BUF_TYPE_GET(ring_desc);
  823. /*
  824. * For WBM ring, expect only MSDU buffers
  825. */
  826. qdf_assert_always(buf_type == HAL_RX_WBM_BUF_TYPE_REL_BUF);
  827. if (wbm_err_src == HAL_RX_WBM_ERR_SRC_REO) {
  828. uint8_t push_reason =
  829. HAL_RX_WBM_REO_PUSH_REASON_GET(ring_desc);
  830. if (push_reason == HAL_RX_WBM_REO_PSH_RSN_ERROR) {
  831. uint8_t reo_error_code =
  832. HAL_RX_WBM_REO_ERROR_CODE_GET(ring_desc);
  833. DP_STATS_INC(soc, rx.err.reo_error[
  834. reo_error_code], 1);
  835. switch (reo_error_code) {
  836. /*
  837. * Handling for packets which have NULL REO
  838. * queue descriptor
  839. */
  840. case HAL_REO_ERR_QUEUE_DESC_ADDR_0:
  841. QDF_TRACE(QDF_MODULE_ID_DP,
  842. QDF_TRACE_LEVEL_WARN,
  843. "Got pkt with REO ERROR: %d",
  844. reo_error_code);
  845. rx_bufs_used[pool_id] +=
  846. dp_rx_null_q_desc_handle(soc,
  847. rx_desc,
  848. &head[pool_id],
  849. &tail[pool_id], quota);
  850. continue;
  851. /* TODO */
  852. /* Add per error code accounting */
  853. default:
  854. QDF_TRACE(QDF_MODULE_ID_DP,
  855. QDF_TRACE_LEVEL_DEBUG,
  856. "REO error %d detected",
  857. reo_error_code);
  858. }
  859. }
  860. } else if (wbm_err_src == HAL_RX_WBM_ERR_SRC_RXDMA) {
  861. uint8_t push_reason =
  862. HAL_RX_WBM_RXDMA_PUSH_REASON_GET(ring_desc);
  863. if (push_reason == HAL_RX_WBM_RXDMA_PSH_RSN_ERROR) {
  864. uint8_t rxdma_error_code =
  865. HAL_RX_WBM_RXDMA_ERROR_CODE_GET(ring_desc);
  866. DP_STATS_INC(soc, rx.err.rxdma_error[
  867. rxdma_error_code], 1);
  868. switch (rxdma_error_code) {
  869. case HAL_RXDMA_ERR_UNENCRYPTED:
  870. rx_bufs_used[pool_id] +=
  871. dp_rx_err_deliver(soc,
  872. rx_desc,
  873. &head[pool_id],
  874. &tail[pool_id],
  875. quota);
  876. continue;
  877. case HAL_RXDMA_ERR_TKIP_MIC:
  878. dp_rx_process_mic_error(soc,
  879. rx_desc,
  880. &head[pool_id],
  881. &tail[pool_id]);
  882. rx_bufs_used[pool_id]++;
  883. continue;
  884. case HAL_RXDMA_ERR_DECRYPT:
  885. QDF_TRACE(QDF_MODULE_ID_DP,
  886. QDF_TRACE_LEVEL_DEBUG,
  887. "Packet received with Decrypt error");
  888. break;
  889. default:
  890. QDF_TRACE(QDF_MODULE_ID_DP,
  891. QDF_TRACE_LEVEL_DEBUG,
  892. "RXDMA error %d",
  893. rxdma_error_code);
  894. }
  895. }
  896. } else {
  897. /* Should not come here */
  898. qdf_assert(0);
  899. }
  900. rx_bufs_used[rx_desc->pool_id]++;
  901. qdf_nbuf_unmap_single(soc->osdev, rx_desc->nbuf,
  902. QDF_DMA_BIDIRECTIONAL);
  903. rx_desc->rx_buf_start = qdf_nbuf_data(rx_desc->nbuf);
  904. hal_rx_dump_pkt_tlvs(rx_desc->rx_buf_start,
  905. QDF_TRACE_LEVEL_DEBUG);
  906. qdf_nbuf_free(rx_desc->nbuf);
  907. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  908. &tail[rx_desc->pool_id], rx_desc);
  909. }
  910. done:
  911. hal_srng_access_end(hal_soc, hal_ring);
  912. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  913. if (rx_bufs_used[mac_id]) {
  914. dp_pdev = soc->pdev_list[mac_id];
  915. dp_rxdma_srng = &dp_pdev->rx_refill_buf_ring;
  916. rx_desc_pool = &soc->rx_desc_buf[mac_id];
  917. dp_rx_buffers_replenish(soc, mac_id, dp_rxdma_srng,
  918. rx_desc_pool, rx_bufs_used[mac_id],
  919. &head[mac_id], &tail[mac_id],
  920. HAL_RX_BUF_RBM_SW3_BM);
  921. rx_bufs_reaped += rx_bufs_used[mac_id];
  922. }
  923. }
  924. return rx_bufs_reaped; /* Assume no scale factor for now */
  925. }
  926. /**
  927. * dp_rx_err_mpdu_pop() - extract the MSDU's from link descs
  928. *
  929. * @soc: core DP main context
  930. * @mac_id: mac id which is one of 3 mac_ids
  931. * @rxdma_dst_ring_desc: void pointer to monitor link descriptor buf addr info
  932. * @head: head of descs list to be freed
  933. * @tail: tail of decs list to be freed
  934. * Return: number of msdu in MPDU to be popped
  935. */
  936. static inline uint32_t
  937. dp_rx_err_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
  938. void *rxdma_dst_ring_desc,
  939. union dp_rx_desc_list_elem_t **head,
  940. union dp_rx_desc_list_elem_t **tail)
  941. {
  942. void *rx_msdu_link_desc;
  943. qdf_nbuf_t msdu;
  944. qdf_nbuf_t last;
  945. struct hal_rx_msdu_list msdu_list;
  946. uint16_t num_msdus;
  947. struct hal_buf_info buf_info;
  948. void *p_buf_addr_info;
  949. void *p_last_buf_addr_info;
  950. uint32_t rx_bufs_used = 0;
  951. uint32_t msdu_cnt;
  952. uint32_t i;
  953. uint8_t push_reason;
  954. uint8_t rxdma_error_code = 0;
  955. uint8_t bm_action = HAL_BM_ACTION_PUT_IN_IDLE_LIST;
  956. struct dp_pdev *pdev = soc->pdev_list[mac_id];
  957. msdu = 0;
  958. last = NULL;
  959. hal_rx_reo_ent_buf_paddr_get(rxdma_dst_ring_desc, &buf_info,
  960. &p_last_buf_addr_info, &msdu_cnt);
  961. push_reason =
  962. hal_rx_reo_ent_rxdma_push_reason_get(rxdma_dst_ring_desc);
  963. if (push_reason == HAL_RX_WBM_RXDMA_PSH_RSN_ERROR) {
  964. rxdma_error_code =
  965. hal_rx_reo_ent_rxdma_error_code_get(rxdma_dst_ring_desc);
  966. }
  967. do {
  968. rx_msdu_link_desc =
  969. dp_rx_cookie_2_link_desc_va(soc, &buf_info);
  970. qdf_assert(rx_msdu_link_desc);
  971. hal_rx_msdu_list_get(rx_msdu_link_desc, &msdu_list, &num_msdus);
  972. if (msdu_list.sw_cookie[0] != HAL_RX_COOKIE_SPECIAL) {
  973. /* if the msdus belongs to NSS offloaded radio &&
  974. * the rbm is not SW3_BM then return the msdu_link
  975. * descriptor without freeing the msdus (nbufs). let
  976. * these buffers be given to NSS completion ring for
  977. * NSS to free them.
  978. * else iterate through the msdu link desc list and
  979. * free each msdu in the list.
  980. */
  981. if (msdu_list.rbm[0] != HAL_RX_BUF_RBM_SW3_BM &&
  982. wlan_cfg_get_dp_pdev_nss_enabled(
  983. pdev->wlan_cfg_ctx))
  984. bm_action = HAL_BM_ACTION_RELEASE_MSDU_LIST;
  985. else {
  986. for (i = 0; i < num_msdus; i++) {
  987. struct dp_rx_desc *rx_desc =
  988. dp_rx_cookie_2_va_rxdma_buf(soc,
  989. msdu_list.sw_cookie[i]);
  990. qdf_assert(rx_desc);
  991. msdu = rx_desc->nbuf;
  992. qdf_nbuf_unmap_single(soc->osdev, msdu,
  993. QDF_DMA_FROM_DEVICE);
  994. QDF_TRACE(QDF_MODULE_ID_DP,
  995. QDF_TRACE_LEVEL_DEBUG,
  996. "[%s][%d] msdu_nbuf=%pK \n",
  997. __func__, __LINE__, msdu);
  998. qdf_nbuf_free(msdu);
  999. rx_bufs_used++;
  1000. dp_rx_add_to_free_desc_list(head,
  1001. tail, rx_desc);
  1002. }
  1003. }
  1004. } else {
  1005. rxdma_error_code = HAL_RXDMA_ERR_WAR;
  1006. }
  1007. hal_rx_mon_next_link_desc_get(rx_msdu_link_desc, &buf_info,
  1008. &p_buf_addr_info);
  1009. dp_rx_link_desc_return(soc, p_last_buf_addr_info, bm_action);
  1010. p_last_buf_addr_info = p_buf_addr_info;
  1011. } while (buf_info.paddr);
  1012. DP_STATS_INC(soc, rx.err.rxdma_error[rxdma_error_code], 1);
  1013. if (rxdma_error_code == HAL_RXDMA_ERR_DECRYPT) {
  1014. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1015. "Packet received with Decrypt error");
  1016. }
  1017. return rx_bufs_used;
  1018. }
  1019. /**
  1020. * dp_rxdma_err_process() - RxDMA error processing functionality
  1021. *
  1022. * @soc: core txrx main contex
  1023. * @mac_id: mac id which is one of 3 mac_ids
  1024. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  1025. * @quota: No. of units (packets) that can be serviced in one shot.
  1026. * Return: num of buffers processed
  1027. */
  1028. uint32_t
  1029. dp_rxdma_err_process(struct dp_soc *soc, uint32_t mac_id, uint32_t quota)
  1030. {
  1031. struct dp_pdev *pdev = soc->pdev_list[mac_id];
  1032. uint8_t pdev_id;
  1033. void *hal_soc;
  1034. void *rxdma_dst_ring_desc;
  1035. void *err_dst_srng;
  1036. union dp_rx_desc_list_elem_t *head = NULL;
  1037. union dp_rx_desc_list_elem_t *tail = NULL;
  1038. struct dp_srng *dp_rxdma_srng;
  1039. struct rx_desc_pool *rx_desc_pool;
  1040. uint32_t work_done = 0;
  1041. uint32_t rx_bufs_used = 0;
  1042. #ifdef DP_INTR_POLL_BASED
  1043. if (!pdev)
  1044. return 0;
  1045. #endif
  1046. pdev_id = pdev->pdev_id;
  1047. err_dst_srng = pdev->rxdma_err_dst_ring.hal_srng;
  1048. if (!err_dst_srng) {
  1049. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1050. "%s %d : HAL Monitor Destination Ring Init \
  1051. Failed -- %pK\n",
  1052. __func__, __LINE__, err_dst_srng);
  1053. return 0;
  1054. }
  1055. hal_soc = soc->hal_soc;
  1056. qdf_assert(hal_soc);
  1057. if (qdf_unlikely(hal_srng_access_start(hal_soc, err_dst_srng))) {
  1058. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1059. "%s %d : HAL Monitor Destination Ring Init \
  1060. Failed -- %pK\n",
  1061. __func__, __LINE__, err_dst_srng);
  1062. return 0;
  1063. }
  1064. while (qdf_likely(quota-- && (rxdma_dst_ring_desc =
  1065. hal_srng_dst_get_next(hal_soc, err_dst_srng)))) {
  1066. rx_bufs_used += dp_rx_err_mpdu_pop(soc, mac_id,
  1067. rxdma_dst_ring_desc,
  1068. &head, &tail);
  1069. }
  1070. hal_srng_access_end(hal_soc, err_dst_srng);
  1071. if (rx_bufs_used) {
  1072. dp_rxdma_srng = &pdev->rx_refill_buf_ring;
  1073. rx_desc_pool = &soc->rx_desc_buf[mac_id];
  1074. dp_rx_buffers_replenish(soc, pdev_id, dp_rxdma_srng,
  1075. rx_desc_pool, rx_bufs_used, &head, &tail,
  1076. HAL_RX_BUF_RBM_SW3_BM);
  1077. work_done += rx_bufs_used;
  1078. }
  1079. return work_done;
  1080. }