hfi.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/delay.h>
  7. #include <linux/slab.h>
  8. #include <linux/random.h>
  9. #include <asm/errno.h>
  10. #include <linux/timer.h>
  11. #include <media/cam_icp.h>
  12. #include <linux/iopoll.h>
  13. #include "cam_io_util.h"
  14. #include "hfi_reg.h"
  15. #include "hfi_sys_defs.h"
  16. #include "hfi_session_defs.h"
  17. #include "hfi_intf.h"
  18. #include "cam_icp_hw_mgr_intf.h"
  19. #include "cam_debug_util.h"
  20. #include "cam_compat.h"
  21. #define HFI_VERSION_INFO_MAJOR_VAL 1
  22. #define HFI_VERSION_INFO_MINOR_VAL 1
  23. #define HFI_VERSION_INFO_STEP_VAL 0
  24. #define HFI_VERSION_INFO_STEP_VAL 0
  25. #define HFI_VERSION_INFO_MAJOR_BMSK 0xFF000000
  26. #define HFI_VERSION_INFO_MAJOR_SHFT 24
  27. #define HFI_VERSION_INFO_MINOR_BMSK 0xFFFF00
  28. #define HFI_VERSION_INFO_MINOR_SHFT 8
  29. #define HFI_VERSION_INFO_STEP_BMSK 0xFF
  30. #define HFI_VERSION_INFO_STEP_SHFT 0
  31. /* TO DO Lower timeout value */
  32. #define HFI_POLL_DELAY_US 10
  33. #define HFI_POLL_TIMEOUT_US 1500000
  34. static struct hfi_info *g_hfi;
  35. unsigned int g_icp_mmu_hdl;
  36. static DEFINE_MUTEX(hfi_cmd_q_mutex);
  37. static DEFINE_MUTEX(hfi_msg_q_mutex);
  38. static void hfi_irq_raise(struct hfi_info *hfi)
  39. {
  40. if (hfi->ops.irq_raise)
  41. hfi->ops.irq_raise(hfi->priv);
  42. }
  43. static void hfi_irq_enable(struct hfi_info *hfi)
  44. {
  45. if (hfi->ops.irq_enable)
  46. hfi->ops.irq_enable(hfi->priv);
  47. }
  48. static void __iomem *hfi_iface_addr(struct hfi_info *hfi)
  49. {
  50. void __iomem *ret = NULL;
  51. if (hfi->ops.iface_addr)
  52. ret = hfi->ops.iface_addr(hfi->priv);
  53. return IS_ERR_OR_NULL(ret) ? NULL : ret;
  54. }
  55. static void hfi_queue_dump(uint32_t *dwords, int count)
  56. {
  57. int i;
  58. int rows;
  59. int remaining;
  60. rows = count / 4;
  61. remaining = count % 4;
  62. for (i = 0; i < rows; i++, dwords += 4)
  63. CAM_DBG(CAM_HFI,
  64. "word[%04d]: 0x%08x 0x%08x 0x%08x 0x%08x",
  65. i * 4, dwords[0], dwords[1], dwords[2], dwords[3]);
  66. if (remaining == 1)
  67. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x", rows * 4, dwords[0]);
  68. else if (remaining == 2)
  69. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x",
  70. rows * 4, dwords[0], dwords[1]);
  71. else if (remaining == 3)
  72. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x 0x%08x",
  73. rows * 4, dwords[0], dwords[1], dwords[2]);
  74. }
  75. void cam_hfi_mini_dump(struct hfi_mini_dump_info *dst)
  76. {
  77. struct hfi_mem_info *hfi_mem = &g_hfi->map;
  78. struct hfi_qtbl *qtbl;
  79. struct hfi_q_hdr *q_hdr;
  80. uint32_t *dwords;
  81. int num_dwords;
  82. if (!hfi_mem) {
  83. CAM_ERR(CAM_HFI, "hfi mem info NULL... unable to dump queues");
  84. return;
  85. }
  86. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  87. q_hdr = &qtbl->q_hdr[Q_CMD];
  88. dwords = (uint32_t *)hfi_mem->cmd_q.kva;
  89. num_dwords = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  90. memcpy(dst->cmd_q, dwords, ICP_CMD_Q_SIZE_IN_BYTES);
  91. q_hdr = &qtbl->q_hdr[Q_MSG];
  92. dwords = (uint32_t *)hfi_mem->msg_q.kva;
  93. memcpy(dst->msg_q, dwords, ICP_CMD_Q_SIZE_IN_BYTES);
  94. dst->msg_q_state = g_hfi->msg_q_state;
  95. dst->cmd_q_state = g_hfi->cmd_q_state;
  96. }
  97. void cam_hfi_queue_dump(void)
  98. {
  99. struct hfi_mem_info *hfi_mem = &g_hfi->map;
  100. struct hfi_qtbl *qtbl;
  101. struct hfi_q_hdr *q_hdr;
  102. uint32_t *dwords;
  103. int num_dwords;
  104. if (!hfi_mem) {
  105. CAM_ERR(CAM_HFI, "hfi mem info NULL... unable to dump queues");
  106. return;
  107. }
  108. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  109. CAM_DBG(CAM_HFI,
  110. "qtbl header: version=0x%08x tbl_size=%u numq=%u qhdr_size=%u",
  111. qtbl->q_tbl_hdr.qtbl_version,
  112. qtbl->q_tbl_hdr.qtbl_size,
  113. qtbl->q_tbl_hdr.qtbl_num_q,
  114. qtbl->q_tbl_hdr.qtbl_qhdr_size);
  115. q_hdr = &qtbl->q_hdr[Q_CMD];
  116. CAM_DBG(CAM_HFI,
  117. "cmd_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  118. hfi_mem->cmd_q.iova,
  119. q_hdr->qhdr_q_size,
  120. q_hdr->qhdr_read_idx,
  121. q_hdr->qhdr_write_idx);
  122. dwords = (uint32_t *)hfi_mem->cmd_q.kva;
  123. num_dwords = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  124. hfi_queue_dump(dwords, num_dwords);
  125. q_hdr = &qtbl->q_hdr[Q_MSG];
  126. CAM_DBG(CAM_HFI,
  127. "msg_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  128. hfi_mem->msg_q.iova,
  129. q_hdr->qhdr_q_size,
  130. q_hdr->qhdr_read_idx,
  131. q_hdr->qhdr_write_idx);
  132. dwords = (uint32_t *)hfi_mem->msg_q.kva;
  133. num_dwords = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  134. hfi_queue_dump(dwords, num_dwords);
  135. }
  136. int hfi_write_cmd(void *cmd_ptr)
  137. {
  138. uint32_t size_in_words, empty_space, new_write_idx, read_idx, temp;
  139. uint32_t *write_q, *write_ptr;
  140. struct hfi_qtbl *q_tbl;
  141. struct hfi_q_hdr *q;
  142. int rc = 0;
  143. if (!cmd_ptr) {
  144. CAM_ERR(CAM_HFI, "command is null");
  145. return -EINVAL;
  146. }
  147. mutex_lock(&hfi_cmd_q_mutex);
  148. if (!g_hfi) {
  149. CAM_ERR(CAM_HFI, "HFI interface not setup");
  150. rc = -ENODEV;
  151. goto err;
  152. }
  153. if (g_hfi->hfi_state != HFI_READY ||
  154. !g_hfi->cmd_q_state) {
  155. CAM_ERR(CAM_HFI, "HFI state: %u, cmd q state: %u",
  156. g_hfi->hfi_state, g_hfi->cmd_q_state);
  157. rc = -ENODEV;
  158. goto err;
  159. }
  160. q_tbl = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  161. q = &q_tbl->q_hdr[Q_CMD];
  162. write_q = (uint32_t *)g_hfi->map.cmd_q.kva;
  163. size_in_words = (*(uint32_t *)cmd_ptr) >> BYTE_WORD_SHIFT;
  164. if (!size_in_words) {
  165. CAM_DBG(CAM_HFI, "failed");
  166. rc = -EINVAL;
  167. goto err;
  168. }
  169. read_idx = q->qhdr_read_idx;
  170. empty_space = (q->qhdr_write_idx >= read_idx) ?
  171. (q->qhdr_q_size - (q->qhdr_write_idx - read_idx)) :
  172. (read_idx - q->qhdr_write_idx);
  173. if (empty_space <= size_in_words) {
  174. CAM_ERR(CAM_HFI, "failed: empty space %u, size_in_words %u",
  175. empty_space, size_in_words);
  176. rc = -EIO;
  177. goto err;
  178. }
  179. new_write_idx = q->qhdr_write_idx + size_in_words;
  180. write_ptr = (uint32_t *)(write_q + q->qhdr_write_idx);
  181. if (new_write_idx < q->qhdr_q_size) {
  182. memcpy(write_ptr, (uint8_t *)cmd_ptr,
  183. size_in_words << BYTE_WORD_SHIFT);
  184. } else {
  185. new_write_idx -= q->qhdr_q_size;
  186. temp = (size_in_words - new_write_idx) << BYTE_WORD_SHIFT;
  187. memcpy(write_ptr, (uint8_t *)cmd_ptr, temp);
  188. memcpy(write_q, (uint8_t *)cmd_ptr + temp,
  189. new_write_idx << BYTE_WORD_SHIFT);
  190. }
  191. /*
  192. * To make sure command data in a command queue before
  193. * updating write index
  194. */
  195. wmb();
  196. q->qhdr_write_idx = new_write_idx;
  197. /*
  198. * Before raising interrupt make sure command data is ready for
  199. * firmware to process
  200. */
  201. wmb();
  202. hfi_irq_raise(g_hfi);
  203. /* Ensure HOST2ICP trigger is received by FW */
  204. wmb();
  205. err:
  206. mutex_unlock(&hfi_cmd_q_mutex);
  207. return rc;
  208. }
  209. int hfi_read_message(uint32_t *pmsg, uint8_t q_id,
  210. uint32_t *words_read)
  211. {
  212. struct hfi_qtbl *q_tbl_ptr;
  213. struct hfi_q_hdr *q;
  214. uint32_t new_read_idx, size_in_words, word_diff, temp;
  215. uint32_t *read_q, *read_ptr, *write_ptr;
  216. uint32_t size_upper_bound = 0;
  217. int rc = 0;
  218. if (!pmsg) {
  219. CAM_ERR(CAM_HFI, "Invalid msg");
  220. return -EINVAL;
  221. }
  222. if (q_id > Q_DBG) {
  223. CAM_ERR(CAM_HFI, "Invalid q :%u", q_id);
  224. return -EINVAL;
  225. }
  226. mutex_lock(&hfi_msg_q_mutex);
  227. if (!g_hfi) {
  228. CAM_ERR(CAM_HFI, "hfi not set up yet");
  229. rc = -ENODEV;
  230. goto err;
  231. }
  232. if ((g_hfi->hfi_state != HFI_READY) ||
  233. !g_hfi->msg_q_state) {
  234. CAM_ERR(CAM_HFI, "hfi state: %u, msg q state: %u",
  235. g_hfi->hfi_state, g_hfi->msg_q_state);
  236. rc = -ENODEV;
  237. goto err;
  238. }
  239. q_tbl_ptr = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  240. q = &q_tbl_ptr->q_hdr[q_id];
  241. if (q->qhdr_read_idx == q->qhdr_write_idx) {
  242. CAM_DBG(CAM_HFI, "Q not ready, state:%u, r idx:%u, w idx:%u",
  243. g_hfi->hfi_state, q->qhdr_read_idx, q->qhdr_write_idx);
  244. rc = -EIO;
  245. goto err;
  246. }
  247. if (q_id == Q_MSG) {
  248. read_q = (uint32_t *)g_hfi->map.msg_q.kva;
  249. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS;
  250. } else {
  251. read_q = (uint32_t *)g_hfi->map.dbg_q.kva;
  252. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_IN_WORDS;
  253. }
  254. read_ptr = (uint32_t *)(read_q + q->qhdr_read_idx);
  255. write_ptr = (uint32_t *)(read_q + q->qhdr_write_idx);
  256. if (write_ptr > read_ptr)
  257. size_in_words = write_ptr - read_ptr;
  258. else {
  259. word_diff = read_ptr - write_ptr;
  260. if (q_id == Q_MSG)
  261. size_in_words = (ICP_MSG_Q_SIZE_IN_BYTES >>
  262. BYTE_WORD_SHIFT) - word_diff;
  263. else
  264. size_in_words = (ICP_DBG_Q_SIZE_IN_BYTES >>
  265. BYTE_WORD_SHIFT) - word_diff;
  266. }
  267. if ((size_in_words == 0) ||
  268. (size_in_words > size_upper_bound)) {
  269. CAM_ERR(CAM_HFI, "invalid HFI message packet size - 0x%08x",
  270. size_in_words << BYTE_WORD_SHIFT);
  271. q->qhdr_read_idx = q->qhdr_write_idx;
  272. rc = -EIO;
  273. goto err;
  274. }
  275. new_read_idx = q->qhdr_read_idx + size_in_words;
  276. if (new_read_idx < q->qhdr_q_size) {
  277. memcpy(pmsg, read_ptr, size_in_words << BYTE_WORD_SHIFT);
  278. } else {
  279. new_read_idx -= q->qhdr_q_size;
  280. temp = (size_in_words - new_read_idx) << BYTE_WORD_SHIFT;
  281. memcpy(pmsg, read_ptr, temp);
  282. memcpy((uint8_t *)pmsg + temp, read_q,
  283. new_read_idx << BYTE_WORD_SHIFT);
  284. }
  285. q->qhdr_read_idx = new_read_idx;
  286. *words_read = size_in_words;
  287. /* Memory Barrier to make sure message
  288. * queue parameters are updated after read
  289. */
  290. wmb();
  291. err:
  292. mutex_unlock(&hfi_msg_q_mutex);
  293. return rc;
  294. }
  295. int hfi_cmd_ubwc_config(uint32_t *ubwc_cfg)
  296. {
  297. uint8_t *prop;
  298. struct hfi_cmd_prop *dbg_prop;
  299. uint32_t size = 0;
  300. size = sizeof(struct hfi_cmd_prop) +
  301. sizeof(struct hfi_cmd_ubwc_cfg);
  302. CAM_DBG(CAM_HFI,
  303. "size of ubwc %u, ubwc_cfg [rd-0x%x,wr-0x%x]",
  304. size, ubwc_cfg[0], ubwc_cfg[1]);
  305. prop = kzalloc(size, GFP_KERNEL);
  306. if (!prop)
  307. return -ENOMEM;
  308. dbg_prop = (struct hfi_cmd_prop *)prop;
  309. dbg_prop->size = size;
  310. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  311. dbg_prop->num_prop = 1;
  312. dbg_prop->prop_data[0] = HFI_PROP_SYS_UBWC_CFG;
  313. dbg_prop->prop_data[1] = ubwc_cfg[0];
  314. dbg_prop->prop_data[2] = ubwc_cfg[1];
  315. hfi_write_cmd(prop);
  316. kfree(prop);
  317. return 0;
  318. }
  319. int hfi_cmd_ubwc_config_ext(uint32_t *ubwc_ipe_cfg,
  320. uint32_t *ubwc_bps_cfg)
  321. {
  322. uint8_t *prop;
  323. struct hfi_cmd_prop *dbg_prop;
  324. uint32_t size = 0;
  325. size = sizeof(struct hfi_cmd_prop) +
  326. sizeof(struct hfi_cmd_ubwc_cfg_ext);
  327. CAM_DBG(CAM_HFI,
  328. "size of ubwc %u, ubwc_ipe_cfg[rd-0x%x,wr-0x%x] ubwc_bps_cfg[rd-0x%x,wr-0x%x]",
  329. size, ubwc_ipe_cfg[0], ubwc_ipe_cfg[1],
  330. ubwc_bps_cfg[0], ubwc_bps_cfg[1]);
  331. prop = kzalloc(size, GFP_KERNEL);
  332. if (!prop)
  333. return -ENOMEM;
  334. dbg_prop = (struct hfi_cmd_prop *)prop;
  335. dbg_prop->size = size;
  336. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  337. dbg_prop->num_prop = 1;
  338. dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG_EX;
  339. dbg_prop->prop_data[1] = ubwc_bps_cfg[0];
  340. dbg_prop->prop_data[2] = ubwc_bps_cfg[1];
  341. dbg_prop->prop_data[3] = ubwc_ipe_cfg[0];
  342. dbg_prop->prop_data[4] = ubwc_ipe_cfg[1];
  343. hfi_write_cmd(prop);
  344. kfree(prop);
  345. return 0;
  346. }
  347. int hfi_enable_ipe_bps_pc(bool enable, uint32_t core_info)
  348. {
  349. uint8_t *prop;
  350. struct hfi_cmd_prop *dbg_prop;
  351. uint32_t size = 0;
  352. size = sizeof(struct hfi_cmd_prop) +
  353. sizeof(struct hfi_ipe_bps_pc);
  354. prop = kzalloc(size, GFP_KERNEL);
  355. if (!prop)
  356. return -ENOMEM;
  357. dbg_prop = (struct hfi_cmd_prop *)prop;
  358. dbg_prop->size = size;
  359. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  360. dbg_prop->num_prop = 1;
  361. dbg_prop->prop_data[0] = HFI_PROP_SYS_IPEBPS_PC;
  362. dbg_prop->prop_data[1] = enable;
  363. dbg_prop->prop_data[2] = core_info;
  364. hfi_write_cmd(prop);
  365. kfree(prop);
  366. return 0;
  367. }
  368. int hfi_set_debug_level(u64 icp_dbg_type, uint32_t lvl)
  369. {
  370. uint8_t *prop;
  371. struct hfi_cmd_prop *dbg_prop;
  372. uint32_t size = 0, val;
  373. val = HFI_DEBUG_MSG_LOW |
  374. HFI_DEBUG_MSG_MEDIUM |
  375. HFI_DEBUG_MSG_HIGH |
  376. HFI_DEBUG_MSG_ERROR |
  377. HFI_DEBUG_MSG_FATAL |
  378. HFI_DEBUG_MSG_PERF |
  379. HFI_DEBUG_CFG_WFI |
  380. HFI_DEBUG_CFG_ARM9WD;
  381. if (lvl > val)
  382. return -EINVAL;
  383. if (g_hfi)
  384. g_hfi->dbg_lvl = lvl;
  385. size = sizeof(struct hfi_cmd_prop) +
  386. sizeof(struct hfi_debug);
  387. prop = kzalloc(size, GFP_KERNEL);
  388. if (!prop)
  389. return -ENOMEM;
  390. dbg_prop = (struct hfi_cmd_prop *)prop;
  391. dbg_prop->size = size;
  392. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  393. dbg_prop->num_prop = 1;
  394. dbg_prop->prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  395. dbg_prop->prop_data[1] = lvl;
  396. dbg_prop->prop_data[2] = icp_dbg_type;
  397. hfi_write_cmd(prop);
  398. kfree(prop);
  399. return 0;
  400. }
  401. int hfi_set_fw_dump_level(uint32_t lvl)
  402. {
  403. uint8_t *prop = NULL;
  404. struct hfi_cmd_prop *fw_dump_level_switch_prop = NULL;
  405. uint32_t size = 0;
  406. CAM_DBG(CAM_HFI, "fw dump ENTER");
  407. size = sizeof(struct hfi_cmd_prop) + sizeof(lvl);
  408. prop = kzalloc(size, GFP_KERNEL);
  409. if (!prop)
  410. return -ENOMEM;
  411. fw_dump_level_switch_prop = (struct hfi_cmd_prop *)prop;
  412. fw_dump_level_switch_prop->size = size;
  413. fw_dump_level_switch_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  414. fw_dump_level_switch_prop->num_prop = 1;
  415. fw_dump_level_switch_prop->prop_data[0] = HFI_PROP_SYS_FW_DUMP_CFG;
  416. fw_dump_level_switch_prop->prop_data[1] = lvl;
  417. CAM_DBG(CAM_HFI, "prop->size = %d\n"
  418. "prop->pkt_type = %d\n"
  419. "prop->num_prop = %d\n"
  420. "prop->prop_data[0] = %d\n"
  421. "prop->prop_data[1] = %d\n",
  422. fw_dump_level_switch_prop->size,
  423. fw_dump_level_switch_prop->pkt_type,
  424. fw_dump_level_switch_prop->num_prop,
  425. fw_dump_level_switch_prop->prop_data[0],
  426. fw_dump_level_switch_prop->prop_data[1]);
  427. hfi_write_cmd(prop);
  428. kfree(prop);
  429. return 0;
  430. }
  431. int hfi_send_freq_info(int32_t freq)
  432. {
  433. uint8_t *prop = NULL;
  434. struct hfi_cmd_prop *dbg_prop = NULL;
  435. uint32_t size = 0;
  436. if (!g_hfi) {
  437. CAM_ERR(CAM_HFI, "HFI interface not setup");
  438. return -ENODEV;
  439. }
  440. if (!(g_hfi->dbg_lvl & HFI_DEBUG_MSG_PERF))
  441. return -EINVAL;
  442. size = sizeof(struct hfi_cmd_prop) + sizeof(freq);
  443. prop = kzalloc(size, GFP_KERNEL);
  444. if (!prop)
  445. return -ENOMEM;
  446. dbg_prop = (struct hfi_cmd_prop *)prop;
  447. dbg_prop->size = size;
  448. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  449. dbg_prop->num_prop = 1;
  450. dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_ICP_HW_FREQUENCY;
  451. dbg_prop->prop_data[1] = freq;
  452. CAM_DBG(CAM_HFI, "prop->size = %d\n"
  453. "prop->pkt_type = %d\n"
  454. "prop->num_prop = %d\n"
  455. "prop->prop_data[0] = %d\n"
  456. "prop->prop_data[1] = %d\n"
  457. "dbg_lvl = 0x%x\n",
  458. dbg_prop->size,
  459. dbg_prop->pkt_type,
  460. dbg_prop->num_prop,
  461. dbg_prop->prop_data[0],
  462. dbg_prop->prop_data[1],
  463. g_hfi->dbg_lvl);
  464. hfi_write_cmd(prop);
  465. kfree(prop);
  466. return 0;
  467. }
  468. void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size)
  469. {
  470. switch (type) {
  471. case HFI_CMD_SYS_INIT: {
  472. struct hfi_cmd_sys_init init;
  473. memset(&init, 0, sizeof(init));
  474. init.size = sizeof(struct hfi_cmd_sys_init);
  475. init.pkt_type = type;
  476. hfi_write_cmd(&init);
  477. }
  478. break;
  479. case HFI_CMD_SYS_PC_PREP: {
  480. struct hfi_cmd_pc_prep prep;
  481. prep.size = sizeof(struct hfi_cmd_pc_prep);
  482. prep.pkt_type = type;
  483. hfi_write_cmd(&prep);
  484. }
  485. break;
  486. case HFI_CMD_SYS_SET_PROPERTY: {
  487. struct hfi_cmd_prop prop;
  488. if ((uint32_t)data == (uint32_t)HFI_PROP_SYS_DEBUG_CFG) {
  489. prop.size = sizeof(struct hfi_cmd_prop);
  490. prop.pkt_type = type;
  491. prop.num_prop = 1;
  492. prop.prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  493. hfi_write_cmd(&prop);
  494. }
  495. }
  496. break;
  497. case HFI_CMD_SYS_GET_PROPERTY:
  498. break;
  499. case HFI_CMD_SYS_PING: {
  500. struct hfi_cmd_ping_pkt ping;
  501. ping.size = sizeof(struct hfi_cmd_ping_pkt);
  502. ping.pkt_type = type;
  503. ping.user_data = (uint64_t)data;
  504. hfi_write_cmd(&ping);
  505. }
  506. break;
  507. case HFI_CMD_SYS_RESET: {
  508. struct hfi_cmd_sys_reset_pkt reset;
  509. reset.size = sizeof(struct hfi_cmd_sys_reset_pkt);
  510. reset.pkt_type = type;
  511. reset.user_data = (uint64_t)data;
  512. hfi_write_cmd(&reset);
  513. }
  514. break;
  515. case HFI_CMD_IPEBPS_CREATE_HANDLE: {
  516. struct hfi_cmd_create_handle handle;
  517. handle.size = sizeof(struct hfi_cmd_create_handle);
  518. handle.pkt_type = type;
  519. handle.handle_type = (uint32_t)data;
  520. handle.user_data1 = 0;
  521. hfi_write_cmd(&handle);
  522. }
  523. break;
  524. case HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT:
  525. break;
  526. default:
  527. CAM_ERR(CAM_HFI, "command not supported :%d", type);
  528. break;
  529. }
  530. }
  531. int hfi_get_hw_caps(void *query_buf)
  532. {
  533. int i = 0;
  534. struct cam_icp_query_cap_cmd *query_cmd = NULL;
  535. if (!query_buf) {
  536. CAM_ERR(CAM_HFI, "query buf is NULL");
  537. return -EINVAL;
  538. }
  539. query_cmd = (struct cam_icp_query_cap_cmd *)query_buf;
  540. query_cmd->fw_version.major = 0x12;
  541. query_cmd->fw_version.minor = 0x12;
  542. query_cmd->fw_version.revision = 0x12;
  543. query_cmd->api_version.major = 0x13;
  544. query_cmd->api_version.minor = 0x13;
  545. query_cmd->api_version.revision = 0x13;
  546. query_cmd->num_ipe = 2;
  547. query_cmd->num_bps = 1;
  548. for (i = 0; i < CAM_ICP_DEV_TYPE_MAX; i++) {
  549. query_cmd->dev_ver[i].dev_type = i;
  550. query_cmd->dev_ver[i].hw_ver.major = 0x34 + i;
  551. query_cmd->dev_ver[i].hw_ver.minor = 0x34 + i;
  552. query_cmd->dev_ver[i].hw_ver.incr = 0x34 + i;
  553. }
  554. return 0;
  555. }
  556. int cam_hfi_resume(struct hfi_mem_info *hfi_mem)
  557. {
  558. int rc = 0;
  559. uint32_t fw_version, status = 0;
  560. void __iomem *icp_base = hfi_iface_addr(g_hfi);
  561. if (!icp_base) {
  562. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  563. return -EINVAL;
  564. }
  565. if (cam_common_read_poll_timeout(icp_base +
  566. HFI_REG_ICP_HOST_INIT_RESPONSE,
  567. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
  568. 0x1, ICP_INIT_RESP_SUCCESS, &status)) {
  569. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  570. status);
  571. return -ETIMEDOUT;
  572. }
  573. hfi_irq_enable(g_hfi);
  574. fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION);
  575. CAM_DBG(CAM_HFI, "fw version : [%x]", fw_version);
  576. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova, icp_base + HFI_REG_QTBL_PTR);
  577. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  578. icp_base + HFI_REG_SFR_PTR);
  579. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  580. icp_base + HFI_REG_SHARED_MEM_PTR);
  581. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  582. icp_base + HFI_REG_SHARED_MEM_SIZE);
  583. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  584. icp_base + HFI_REG_SECONDARY_HEAP_PTR);
  585. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  586. icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
  587. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  588. icp_base + HFI_REG_QDSS_IOVA);
  589. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  590. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  591. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  592. icp_base + HFI_REG_IO_REGION_IOVA);
  593. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  594. icp_base + HFI_REG_IO_REGION_SIZE);
  595. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  596. icp_base + HFI_REG_IO2_REGION_IOVA);
  597. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  598. icp_base + HFI_REG_IO2_REGION_SIZE);
  599. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.iova,
  600. icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
  601. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
  602. icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
  603. CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  604. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  605. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  606. CAM_DBG(CAM_HFI, "FwUncached : [0x%x 0x%x] Shared [0x%x 0x%x]",
  607. hfi_mem->fw_uncached.iova, hfi_mem->fw_uncached.len,
  608. hfi_mem->shmem.iova, hfi_mem->shmem.len);
  609. CAM_DBG(CAM_HFI, "SecHeap : [0x%x 0x%x] QDSS [0x%x 0x%x]",
  610. hfi_mem->sec_heap.iova, hfi_mem->sec_heap.len,
  611. hfi_mem->qdss.iova, hfi_mem->qdss.len);
  612. CAM_DBG(CAM_HFI, "QTbl : [0x%x 0x%x] Sfr [0x%x 0x%x]",
  613. hfi_mem->qtbl.iova, hfi_mem->qtbl.len,
  614. hfi_mem->sfr_buf.iova, hfi_mem->sfr_buf.len);
  615. return rc;
  616. }
  617. int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
  618. void *priv, uint8_t event_driven_mode)
  619. {
  620. int rc = 0;
  621. uint32_t status = 0;
  622. struct hfi_qtbl *qtbl;
  623. struct hfi_qtbl_hdr *qtbl_hdr;
  624. struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr;
  625. struct sfr_buf *sfr_buffer;
  626. void __iomem *icp_base;
  627. if (!hfi_mem || !hfi_ops || !priv) {
  628. CAM_ERR(CAM_HFI,
  629. "invalid arg: hfi_mem=%pK hfi_ops=%pK priv=%pK",
  630. hfi_mem, hfi_ops, priv);
  631. return -EINVAL;
  632. }
  633. mutex_lock(&hfi_cmd_q_mutex);
  634. mutex_lock(&hfi_msg_q_mutex);
  635. if (!g_hfi) {
  636. g_hfi = kzalloc(sizeof(struct hfi_info), GFP_KERNEL);
  637. if (!g_hfi) {
  638. rc = -ENOMEM;
  639. goto alloc_fail;
  640. }
  641. }
  642. if (g_hfi->hfi_state != HFI_DEINIT) {
  643. CAM_ERR(CAM_HFI, "hfi_init: invalid state");
  644. rc = -EINVAL;
  645. goto regions_fail;
  646. }
  647. memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map));
  648. g_hfi->hfi_state = HFI_DEINIT;
  649. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  650. qtbl_hdr = &qtbl->q_tbl_hdr;
  651. qtbl_hdr->qtbl_version = 0xFFFFFFFF;
  652. qtbl_hdr->qtbl_size = sizeof(struct hfi_qtbl);
  653. qtbl_hdr->qtbl_qhdr0_offset = sizeof(struct hfi_qtbl_hdr);
  654. qtbl_hdr->qtbl_qhdr_size = sizeof(struct hfi_q_hdr);
  655. qtbl_hdr->qtbl_num_q = ICP_HFI_NUMBER_OF_QS;
  656. qtbl_hdr->qtbl_num_active_q = ICP_HFI_NUMBER_OF_QS;
  657. /* setup host-to-firmware command queue */
  658. cmd_q_hdr = &qtbl->q_hdr[Q_CMD];
  659. cmd_q_hdr->qhdr_status = QHDR_ACTIVE;
  660. cmd_q_hdr->qhdr_start_addr = hfi_mem->cmd_q.iova;
  661. cmd_q_hdr->qhdr_q_size = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  662. cmd_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  663. cmd_q_hdr->qhdr_pkt_drop_cnt = RESET;
  664. cmd_q_hdr->qhdr_read_idx = RESET;
  665. cmd_q_hdr->qhdr_write_idx = RESET;
  666. /* setup firmware-to-Host message queue */
  667. msg_q_hdr = &qtbl->q_hdr[Q_MSG];
  668. msg_q_hdr->qhdr_status = QHDR_ACTIVE;
  669. msg_q_hdr->qhdr_start_addr = hfi_mem->msg_q.iova;
  670. msg_q_hdr->qhdr_q_size = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  671. msg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  672. msg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  673. msg_q_hdr->qhdr_read_idx = RESET;
  674. msg_q_hdr->qhdr_write_idx = RESET;
  675. /* setup firmware-to-Host message queue */
  676. dbg_q_hdr = &qtbl->q_hdr[Q_DBG];
  677. dbg_q_hdr->qhdr_status = QHDR_ACTIVE;
  678. dbg_q_hdr->qhdr_start_addr = hfi_mem->dbg_q.iova;
  679. dbg_q_hdr->qhdr_q_size = ICP_DBG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  680. dbg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  681. dbg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  682. dbg_q_hdr->qhdr_read_idx = RESET;
  683. dbg_q_hdr->qhdr_write_idx = RESET;
  684. sfr_buffer = (struct sfr_buf *)hfi_mem->sfr_buf.kva;
  685. sfr_buffer->size = ICP_MSG_SFR_SIZE_IN_BYTES;
  686. switch (event_driven_mode) {
  687. case INTR_MODE:
  688. cmd_q_hdr->qhdr_type = Q_CMD;
  689. cmd_q_hdr->qhdr_rx_wm = SET;
  690. cmd_q_hdr->qhdr_tx_wm = SET;
  691. cmd_q_hdr->qhdr_rx_req = SET;
  692. cmd_q_hdr->qhdr_tx_req = RESET;
  693. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  694. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  695. msg_q_hdr->qhdr_type = Q_MSG;
  696. msg_q_hdr->qhdr_rx_wm = SET;
  697. msg_q_hdr->qhdr_tx_wm = SET;
  698. msg_q_hdr->qhdr_rx_req = SET;
  699. msg_q_hdr->qhdr_tx_req = RESET;
  700. msg_q_hdr->qhdr_rx_irq_status = RESET;
  701. msg_q_hdr->qhdr_tx_irq_status = RESET;
  702. dbg_q_hdr->qhdr_type = Q_DBG;
  703. dbg_q_hdr->qhdr_rx_wm = SET;
  704. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  705. dbg_q_hdr->qhdr_rx_req = RESET;
  706. dbg_q_hdr->qhdr_tx_req = RESET;
  707. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  708. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  709. break;
  710. case POLL_MODE:
  711. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_POLL_MODE_2 |
  712. RX_EVENT_POLL_MODE_2;
  713. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_POLL_MODE_2 |
  714. RX_EVENT_POLL_MODE_2;
  715. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_POLL_MODE_2 |
  716. RX_EVENT_POLL_MODE_2;
  717. break;
  718. case WM_MODE:
  719. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_DRIVEN_MODE_2 |
  720. RX_EVENT_DRIVEN_MODE_2;
  721. cmd_q_hdr->qhdr_rx_wm = SET;
  722. cmd_q_hdr->qhdr_tx_wm = SET;
  723. cmd_q_hdr->qhdr_rx_req = RESET;
  724. cmd_q_hdr->qhdr_tx_req = SET;
  725. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  726. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  727. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_DRIVEN_MODE_2 |
  728. RX_EVENT_DRIVEN_MODE_2;
  729. msg_q_hdr->qhdr_rx_wm = SET;
  730. msg_q_hdr->qhdr_tx_wm = SET;
  731. msg_q_hdr->qhdr_rx_req = SET;
  732. msg_q_hdr->qhdr_tx_req = RESET;
  733. msg_q_hdr->qhdr_rx_irq_status = RESET;
  734. msg_q_hdr->qhdr_tx_irq_status = RESET;
  735. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_DRIVEN_MODE_2 |
  736. RX_EVENT_DRIVEN_MODE_2;
  737. dbg_q_hdr->qhdr_rx_wm = SET;
  738. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  739. dbg_q_hdr->qhdr_rx_req = RESET;
  740. dbg_q_hdr->qhdr_tx_req = RESET;
  741. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  742. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  743. break;
  744. default:
  745. CAM_ERR(CAM_HFI, "Invalid event driven mode :%u",
  746. event_driven_mode);
  747. break;
  748. }
  749. g_hfi->ops = *hfi_ops;
  750. g_hfi->priv = priv;
  751. icp_base = hfi_iface_addr(g_hfi);
  752. if (!icp_base) {
  753. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  754. rc = -EINVAL;
  755. goto regions_fail;
  756. }
  757. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova,
  758. icp_base + HFI_REG_QTBL_PTR);
  759. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  760. icp_base + HFI_REG_SFR_PTR);
  761. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  762. icp_base + HFI_REG_SHARED_MEM_PTR);
  763. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  764. icp_base + HFI_REG_SHARED_MEM_SIZE);
  765. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  766. icp_base + HFI_REG_SECONDARY_HEAP_PTR);
  767. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  768. icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
  769. cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
  770. icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
  771. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  772. icp_base + HFI_REG_QDSS_IOVA);
  773. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  774. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  775. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  776. icp_base + HFI_REG_IO_REGION_IOVA);
  777. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  778. icp_base + HFI_REG_IO_REGION_SIZE);
  779. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  780. icp_base + HFI_REG_IO2_REGION_IOVA);
  781. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  782. icp_base + HFI_REG_IO2_REGION_SIZE);
  783. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.iova,
  784. icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
  785. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
  786. icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
  787. CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  788. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  789. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  790. CAM_DBG(CAM_HFI, "FwUncached : [0x%x 0x%x] Shared [0x%x 0x%x]",
  791. hfi_mem->fw_uncached.iova, hfi_mem->fw_uncached.len,
  792. hfi_mem->shmem.iova, hfi_mem->shmem.len);
  793. CAM_DBG(CAM_HFI, "SecHeap : [0x%x 0x%x] QDSS [0x%x 0x%x]",
  794. hfi_mem->sec_heap.iova, hfi_mem->sec_heap.len,
  795. hfi_mem->qdss.iova, hfi_mem->qdss.len);
  796. CAM_DBG(CAM_HFI, "QTbl : [0x%x 0x%x] Sfr [0x%x 0x%x]",
  797. hfi_mem->qtbl.iova, hfi_mem->qtbl.len,
  798. hfi_mem->sfr_buf.iova, hfi_mem->sfr_buf.len);
  799. if (cam_common_read_poll_timeout(icp_base +
  800. HFI_REG_ICP_HOST_INIT_RESPONSE,
  801. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
  802. 0x1, ICP_INIT_RESP_SUCCESS, &status)) {
  803. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  804. status);
  805. rc = -ETIMEDOUT;
  806. goto regions_fail;
  807. }
  808. CAM_DBG(CAM_HFI, "ICP fw version: 0x%x",
  809. cam_io_r(icp_base + HFI_REG_FW_VERSION));
  810. g_hfi->hfi_state = HFI_READY;
  811. g_hfi->cmd_q_state = true;
  812. g_hfi->msg_q_state = true;
  813. hfi_irq_enable(g_hfi);
  814. mutex_unlock(&hfi_cmd_q_mutex);
  815. mutex_unlock(&hfi_msg_q_mutex);
  816. return rc;
  817. regions_fail:
  818. kfree(g_hfi);
  819. g_hfi = NULL;
  820. alloc_fail:
  821. mutex_unlock(&hfi_cmd_q_mutex);
  822. mutex_unlock(&hfi_msg_q_mutex);
  823. return rc;
  824. }
  825. void cam_hfi_deinit(void)
  826. {
  827. mutex_lock(&hfi_cmd_q_mutex);
  828. mutex_lock(&hfi_msg_q_mutex);
  829. if (!g_hfi) {
  830. CAM_ERR(CAM_HFI, "hfi path not established yet");
  831. goto err;
  832. }
  833. g_hfi->cmd_q_state = false;
  834. g_hfi->msg_q_state = false;
  835. cam_free_clear((void *)g_hfi);
  836. g_hfi = NULL;
  837. err:
  838. mutex_unlock(&hfi_cmd_q_mutex);
  839. mutex_unlock(&hfi_msg_q_mutex);
  840. }