hfi_command.h 5.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef __H_HFI_COMMAND_H__
  7. #define __H_HFI_COMMAND_H__
  8. //todo: DP: remove below headers
  9. #include <linux/types.h>
  10. #include <linux/bits.h>
  11. #define HFI_VIDEO_ARCH_LX 0x1
  12. struct hfi_header {
  13. u32 size;
  14. u32 session_id;
  15. u32 header_id;
  16. u32 reserved[4];
  17. u32 num_packets;
  18. };
  19. struct hfi_packet {
  20. u32 size;
  21. u32 type;
  22. u32 flags;
  23. u32 payload_info;
  24. u32 port;
  25. u32 packet_id;
  26. u32 reserved[2];
  27. };
  28. struct hfi_buffer {
  29. u32 type;
  30. u32 index;
  31. u64 base_address;
  32. u32 addr_offset;
  33. u32 buffer_size;
  34. u32 data_offset;
  35. u32 data_size;
  36. u64 timestamp;
  37. u32 flags;
  38. u32 reserved[5];
  39. };
  40. enum hfi_packet_host_flags {
  41. HFI_HOST_FLAGS_NONE = 0x00000000,
  42. HFI_HOST_FLAGS_INTR_REQUIRED = 0x00000001,
  43. HFI_HOST_FLAGS_RESPONSE_REQUIRED = 0x00000002,
  44. HFI_HOST_FLAGS_NON_DISCARDABLE = 0x00000004,
  45. HFI_HOST_FLAGS_GET_PROPERTY = 0x00000008,
  46. };
  47. enum hfi_packet_firmware_flags {
  48. HFI_FW_FLAGS_NONE = 0x00000000,
  49. HFI_FW_FLAGS_SUCCESS = 0x00000001,
  50. HFI_FW_FLAGS_INFORMATION = 0x00000002,
  51. HFI_FW_FLAGS_SESSION_ERROR = 0x00000004,
  52. HFI_FW_FLAGS_SYSTEM_ERROR = 0x00000008,
  53. };
  54. enum hfi_packet_payload_info {
  55. HFI_PAYLOAD_NONE = 0x00000000,
  56. HFI_PAYLOAD_U32 = 0x00000001,
  57. HFI_PAYLOAD_S32 = 0x00000002,
  58. HFI_PAYLOAD_U64 = 0x00000003,
  59. HFI_PAYLOAD_S64 = 0x00000004,
  60. HFI_PAYLOAD_STRUCTURE = 0x00000005,
  61. HFI_PAYLOAD_BLOB = 0x00000006,
  62. HFI_PAYLOAD_STRING = 0x00000007,
  63. HFI_PAYLOAD_Q16 = 0x00000008,
  64. HFI_PAYLOAD_U32_ENUM = 0x00000009,
  65. HFI_PAYLOAD_32_PACKED = 0x0000000a,
  66. HFI_PAYLOAD_U32_ARRAY = 0x0000000b,
  67. HFI_PAYLOAD_S32_ARRAY = 0x0000000c,
  68. HFI_PAYLOAD_64_PACKED = 0x0000000d,
  69. };
  70. enum hfi_packet_port_type {
  71. HFI_PORT_NONE = 0x00000000,
  72. HFI_PORT_BITSTREAM = 0x00000001,
  73. HFI_PORT_RAW = 0x00000002,
  74. };
  75. enum hfi_buffer_type {
  76. HFI_BUFFER_BITSTREAM = 0x00000001,
  77. HFI_BUFFER_RAW = 0x00000002,
  78. HFI_BUFFER_METADATA = 0x00000003,
  79. HFI_BUFFER_SUBCACHE = 0x00000004,
  80. HFI_BUFFER_PARTIAL_DATA = 0x00000005,
  81. HFI_BUFFER_DPB = 0x00000006,
  82. HFI_BUFFER_BIN = 0x00000007,
  83. HFI_BUFFER_LINE = 0x00000008,
  84. HFI_BUFFER_ARP = 0x00000009,
  85. HFI_BUFFER_COMV = 0x0000000A,
  86. HFI_BUFFER_NON_COMV = 0x0000000B,
  87. HFI_BUFFER_PERSIST = 0x0000000C,
  88. HFI_BUFFER_VPSS = 0x0000000D,
  89. };
  90. enum hfi_buffer_host_flags {
  91. HFI_BUF_HOST_FLAG_NONE = 0x00000000,
  92. HFI_BUF_HOST_FLAG_RELEASE = 0x00000001,
  93. HFI_BUF_HOST_FLAG_READONLY = 0x00000010,
  94. HFI_BUF_HOST_FLAG_CODEC_CONFIG = 0x00000100,
  95. HFI_BUF_HOST_FLAGS_CB_NON_SECURE = 0x00000200,
  96. HFI_BUF_HOST_FLAGS_CB_SECURE_PIXEL = 0x00000400,
  97. HFI_BUF_HOST_FLAGS_CB_SECURE_BITSTREAM = 0x00000800,
  98. HFI_BUF_HOST_FLAGS_CB_SECURE_NON_PIXEL = 0x00001000,
  99. HFI_BUF_HOST_FLAGS_CB_NON_SECURE_PIXEL = 0x00002000,
  100. };
  101. enum hfi_buffer_firmware_flags {
  102. HFI_BUF_FW_FLAG_NONE = 0x00000000,
  103. HFI_BUF_FW_FLAG_RELEASE_DONE = 0x00000001,
  104. HFI_BUF_FW_FLAG_READONLY = 0x00000010,
  105. HFI_BUF_FW_FLAG_CODEC_CONFIG = 0x00000100,
  106. HFI_BUF_FW_FLAG_LAST = 0x10000000,
  107. HFI_BUF_FW_FLAG_PSC_LAST = 0x20000000,
  108. };
  109. enum hfi_metapayload_header_flags {
  110. HFI_METADATA_FLAGS_NONE = 0x00000000,
  111. HFI_METADATA_FLAGS_TOP_FIELD = 0x00000001,
  112. HFI_METADATA_FLAGS_BOTTOM_FIELD = 0x00000002,
  113. };
  114. struct metabuf_header {
  115. u32 count;
  116. u32 size;
  117. u32 version;
  118. u32 reserved[5];
  119. };
  120. struct metapayload_header {
  121. u32 type;
  122. u32 size;
  123. u32 version;
  124. u32 offset;
  125. u32 flags;
  126. u32 reserved[3];
  127. };
  128. enum hfi_property_mode_type {
  129. HFI_MODE_NONE = 0x00000000,
  130. HFI_MODE_PORT_SETTINGS_CHANGE = 0x00000001,
  131. HFI_MODE_PROPERTY = 0x00000002,
  132. HFI_MODE_METADATA = 0x00000004,
  133. HFI_MODE_DYNAMIC_METADATA = 0x00000005,
  134. };
  135. enum hfi_reserve_type {
  136. HFI_RESERVE_START = 0x1,
  137. HFI_RESERVE_STOP = 0x2,
  138. };
  139. #define HFI_CMD_BEGIN 0x01000000
  140. #define HFI_CMD_INIT 0x01000001
  141. #define HFI_CMD_POWER_COLLAPSE 0x01000002
  142. #define HFI_CMD_OPEN 0x01000003
  143. #define HFI_CMD_CLOSE 0x01000004
  144. #define HFI_CMD_START 0x01000005
  145. #define HFI_CMD_STOP 0x01000006
  146. #define HFI_CMD_DRAIN 0x01000007
  147. #define HFI_CMD_RESUME 0x01000008
  148. #define HFI_CMD_BUFFER 0x01000009
  149. #define HFI_CMD_DELIVERY_MODE 0x0100000A
  150. #define HFI_CMD_SUBSCRIBE_MODE 0x0100000B
  151. #define HFI_CMD_SETTINGS_CHANGE 0x0100000C
  152. #define HFI_SSR_TYPE_SW_ERR_FATAL 0x1
  153. #define HFI_SSR_TYPE_SW_DIV_BY_ZERO 0x2
  154. #define HFI_SSR_TYPE_CPU_WDOG_IRQ 0x3
  155. #define HFI_SSR_TYPE_NOC_ERROR 0x4
  156. #define HFI_BITMASK_HW_CLIENT_ID 0x000000f0
  157. #define HFI_BITMASK_SSR_TYPE 0x0000000f
  158. #define HFI_CMD_SSR 0x0100000D
  159. #define HFI_STABILITY_TYPE_VCODEC_HUNG 0x1
  160. #define HFI_STABILITY_TYPE_ENC_BUFFER_FULL 0x2
  161. #define HFI_BITMASK_STABILITY_TYPE 0x0000000f
  162. #define HFI_CMD_STABILITY 0x0100000E
  163. #define HFI_CMD_RESERVE 0x0100000F
  164. #define HFI_CMD_FLUSH 0x01000010
  165. #define HFI_CMD_PAUSE 0x01000011
  166. #define HFI_CMD_END 0x01FFFFFF
  167. #endif //__H_HFI_COMMAND_H__