msm_cvp_platform.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/debugfs.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/init.h>
  8. #include <linux/ioctl.h>
  9. #include <linux/list.h>
  10. #include <linux/module.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/types.h>
  15. #include <linux/version.h>
  16. #include <linux/io.h>
  17. #include <linux/of_fdt.h>
  18. #include "msm_cvp_internal.h"
  19. #include "msm_cvp_debug.h"
  20. #include "cvp_hfi_api.h"
  21. #include "cvp_hfi.h"
  22. #define UBWC_CONFIG(mco, mlo, hbo, bslo, bso, rs, mc, ml, hbb, bsl, bsp) \
  23. { \
  24. .override_bit_info.max_channel_override = mco, \
  25. .override_bit_info.mal_length_override = mlo, \
  26. .override_bit_info.hb_override = hbo, \
  27. .override_bit_info.bank_swzl_level_override = bslo, \
  28. .override_bit_info.bank_spreading_override = bso, \
  29. .override_bit_info.reserved = rs, \
  30. .max_channels = mc, \
  31. .mal_length = ml, \
  32. .highest_bank_bit = hbb, \
  33. .bank_swzl_level = bsl, \
  34. .bank_spreading = bsp, \
  35. }
  36. static struct msm_cvp_common_data default_common_data[] = {
  37. {
  38. .key = "qcom,never-unload-fw",
  39. .value = 1,
  40. },
  41. };
  42. static struct msm_cvp_common_data sm8450_common_data[] = {
  43. {
  44. .key = "qcom,auto-pil",
  45. .value = 1,
  46. },
  47. {
  48. .key = "qcom,never-unload-fw",
  49. .value = 1,
  50. },
  51. {
  52. .key = "qcom,sw-power-collapse",
  53. .value = 1,
  54. },
  55. {
  56. .key = "qcom,domain-attr-non-fatal-faults",
  57. .value = 0,
  58. },
  59. {
  60. .key = "qcom,max-secure-instances",
  61. .value = 2, /*
  62. * As per design driver allows 3rd
  63. * instance as well since the secure
  64. * flags were updated later for the
  65. * current instance. Hence total
  66. * secure sessions would be
  67. * max-secure-instances + 1.
  68. */
  69. },
  70. {
  71. .key = "qcom,max-ssr-allowed",
  72. .value = 1, /*
  73. * Maxinum number of SSR before BUG_ON
  74. */
  75. },
  76. {
  77. .key = "qcom,power-collapse-delay",
  78. .value = 3000,
  79. },
  80. {
  81. .key = "qcom,hw-resp-timeout",
  82. .value = 2000,
  83. },
  84. {
  85. .key = "qcom,dsp-resp-timeout",
  86. .value = 1000,
  87. },
  88. {
  89. .key = "qcom,debug-timeout",
  90. .value = 0,
  91. },
  92. {
  93. .key = "qcom,dsp-enabled",
  94. .value = 1,
  95. }
  96. };
  97. static struct msm_cvp_common_data sm8550_common_data[] = {
  98. {
  99. .key = "qcom,auto-pil",
  100. .value = 0,
  101. },
  102. {
  103. .key = "qcom,never-unload-fw",
  104. .value = 1,
  105. },
  106. {
  107. .key = "qcom,sw-power-collapse",
  108. .value = 0,
  109. },
  110. {
  111. .key = "qcom,domain-attr-non-fatal-faults",
  112. .value = 0,
  113. },
  114. {
  115. .key = "qcom,max-secure-instances",
  116. .value = 2, /*
  117. * As per design driver allows 3rd
  118. * instance as well since the secure
  119. * flags were updated later for the
  120. * current instance. Hence total
  121. * secure sessions would be
  122. * max-secure-instances + 1.
  123. */
  124. },
  125. {
  126. .key = "qcom,max-ssr-allowed",
  127. .value = 1, /*
  128. * Maxinum number of SSR before BUG_ON
  129. */
  130. },
  131. {
  132. .key = "qcom,power-collapse-delay",
  133. .value = 3000,
  134. },
  135. {
  136. .key = "qcom,hw-resp-timeout",
  137. .value = 2000,
  138. },
  139. {
  140. .key = "qcom,dsp-resp-timeout",
  141. .value = 1000,
  142. },
  143. {
  144. .key = "qcom,debug-timeout",
  145. .value = 0,
  146. },
  147. {
  148. .key = "qcom,dsp-enabled",
  149. .value = 0,
  150. }
  151. };
  152. /* Default UBWC config for LPDDR5 */
  153. static struct msm_cvp_ubwc_config_data kona_ubwc_data[] = {
  154. UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 16, 0, 0),
  155. };
  156. static struct msm_cvp_qos_setting waipio_noc_qos = {
  157. .axi_qos = 0x99,
  158. .prioritylut_low = 0x22222222,
  159. .prioritylut_high = 0x33333333,
  160. .urgency_low = 0x1022,
  161. .dangerlut_low = 0x0,
  162. .safelut_low = 0xffff,
  163. };
  164. static struct msm_cvp_platform_data default_data = {
  165. .common_data = default_common_data,
  166. .common_data_length = ARRAY_SIZE(default_common_data),
  167. .sku_version = 0,
  168. .vpu_ver = VPU_VERSION_5,
  169. .ubwc_config = 0x0,
  170. .noc_qos = 0x0,
  171. };
  172. static struct msm_cvp_platform_data sm8450_data = {
  173. .common_data = sm8450_common_data,
  174. .common_data_length = ARRAY_SIZE(sm8450_common_data),
  175. .sku_version = 0,
  176. .vpu_ver = VPU_VERSION_5,
  177. .ubwc_config = kona_ubwc_data,
  178. .noc_qos = &waipio_noc_qos,
  179. };
  180. static struct msm_cvp_platform_data sm8550_data = {
  181. .common_data = sm8550_common_data,
  182. .common_data_length = ARRAY_SIZE(sm8550_common_data),
  183. .sku_version = 0,
  184. .vpu_ver = VPU_VERSION_5,
  185. .ubwc_config = kona_ubwc_data,
  186. .noc_qos = 0x0,
  187. };
  188. static const struct of_device_id msm_cvp_dt_match[] = {
  189. {
  190. .compatible = "qcom,waipio-cvp",
  191. .data = &sm8450_data,
  192. },
  193. {
  194. .compatible = "qcom,kailua-cvp",
  195. .data = &sm8550_data,
  196. },
  197. {},
  198. };
  199. const struct msm_cvp_hfi_defs cvp_hfi_defs[] = {
  200. {
  201. .size = HFI_DFS_CONFIG_CMD_SIZE,
  202. .type = HFI_CMD_SESSION_CVP_DFS_CONFIG,
  203. .is_config_pkt = true,
  204. .resp = HAL_NO_RESP,
  205. },
  206. {
  207. .size = HFI_DFS_FRAME_CMD_SIZE,
  208. .type = HFI_CMD_SESSION_CVP_DFS_FRAME,
  209. .is_config_pkt = false,
  210. .resp = HAL_NO_RESP,
  211. },
  212. {
  213. .size = 0xFFFFFFFF,
  214. .type = HFI_CMD_SESSION_CVP_SGM_OF_CONFIG,
  215. .is_config_pkt = true,
  216. .resp = HAL_NO_RESP,
  217. },
  218. {
  219. .size = 0xFFFFFFFF,
  220. .type = HFI_CMD_SESSION_CVP_SGM_OF_FRAME,
  221. .is_config_pkt = false,
  222. .resp = HAL_NO_RESP,
  223. },
  224. {
  225. .size = 0xFFFFFFFF,
  226. .type = HFI_CMD_SESSION_CVP_WARP_NCC_CONFIG,
  227. .is_config_pkt = true,
  228. .resp = HAL_NO_RESP,
  229. },
  230. {
  231. .size = 0xFFFFFFFF,
  232. .type = HFI_CMD_SESSION_CVP_WARP_NCC_FRAME,
  233. .is_config_pkt = false,
  234. .resp = HAL_NO_RESP,
  235. },
  236. {
  237. .size = 0xFFFFFFFF,
  238. .type = HFI_CMD_SESSION_CVP_WARP_CONFIG,
  239. .is_config_pkt = true,
  240. .resp = HAL_NO_RESP,
  241. },
  242. {
  243. .size = 0xFFFFFFFF,
  244. .type = HFI_CMD_SESSION_CVP_WARP_DS_PARAMS,
  245. .is_config_pkt = true,
  246. .resp = HAL_NO_RESP,
  247. },
  248. {
  249. .size = 0xFFFFFFFF,
  250. .type = HFI_CMD_SESSION_CVP_WARP_FRAME,
  251. .is_config_pkt = false,
  252. .resp = HAL_NO_RESP,
  253. },
  254. {
  255. .size = HFI_DMM_CONFIG_CMD_SIZE,
  256. .type = HFI_CMD_SESSION_CVP_DMM_CONFIG,
  257. .is_config_pkt = true,
  258. .resp = HAL_NO_RESP,
  259. },
  260. {
  261. .size = 0xFFFFFFFF,
  262. .type = HFI_CMD_SESSION_CVP_DMM_PARAMS,
  263. .is_config_pkt = true,
  264. .resp = HAL_NO_RESP,
  265. },
  266. {
  267. .size = HFI_DMM_FRAME_CMD_SIZE,
  268. .type = HFI_CMD_SESSION_CVP_DMM_FRAME,
  269. .is_config_pkt = false,
  270. .resp = HAL_NO_RESP,
  271. },
  272. {
  273. .size = HFI_PERSIST_CMD_SIZE,
  274. .type = HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS,
  275. .is_config_pkt = true,
  276. .resp = HAL_NO_RESP,
  277. },
  278. {
  279. .size = 0xffffffff,
  280. .type = HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS,
  281. .is_config_pkt = true,
  282. .resp = HAL_NO_RESP,
  283. },
  284. {
  285. .size = HFI_DS_CMD_SIZE,
  286. .type = HFI_CMD_SESSION_CVP_DS,
  287. .is_config_pkt = false,
  288. .resp = HAL_NO_RESP,
  289. },
  290. {
  291. .size = HFI_OF_CONFIG_CMD_SIZE,
  292. .type = HFI_CMD_SESSION_CVP_CV_TME_CONFIG,
  293. .is_config_pkt = true,
  294. .resp = HAL_NO_RESP,
  295. },
  296. {
  297. .size = HFI_OF_FRAME_CMD_SIZE,
  298. .type = HFI_CMD_SESSION_CVP_CV_TME_FRAME,
  299. .is_config_pkt = false,
  300. .resp = HAL_NO_RESP,
  301. },
  302. {
  303. .size = HFI_ODT_CONFIG_CMD_SIZE,
  304. .type = HFI_CMD_SESSION_CVP_CV_ODT_CONFIG,
  305. .is_config_pkt = true,
  306. .resp = HAL_NO_RESP,
  307. },
  308. {
  309. .size = HFI_ODT_FRAME_CMD_SIZE,
  310. .type = HFI_CMD_SESSION_CVP_CV_ODT_FRAME,
  311. .is_config_pkt = false,
  312. .resp = HAL_NO_RESP,
  313. },
  314. {
  315. .size = HFI_OD_CONFIG_CMD_SIZE,
  316. .type = HFI_CMD_SESSION_CVP_CV_OD_CONFIG,
  317. .is_config_pkt = true,
  318. .resp = HAL_NO_RESP,
  319. },
  320. {
  321. .size = HFI_OD_FRAME_CMD_SIZE,
  322. .type = HFI_CMD_SESSION_CVP_CV_OD_FRAME,
  323. .is_config_pkt = false,
  324. .resp = HAL_NO_RESP,
  325. },
  326. {
  327. .size = HFI_NCC_CONFIG_CMD_SIZE,
  328. .type = HFI_CMD_SESSION_CVP_NCC_CONFIG,
  329. .is_config_pkt = true,
  330. .resp = HAL_NO_RESP,
  331. },
  332. {
  333. .size = HFI_NCC_FRAME_CMD_SIZE,
  334. .type = HFI_CMD_SESSION_CVP_NCC_FRAME,
  335. .is_config_pkt = false,
  336. .resp = HAL_NO_RESP,
  337. },
  338. {
  339. .size = HFI_ICA_CONFIG_CMD_SIZE,
  340. .type = HFI_CMD_SESSION_CVP_ICA_CONFIG,
  341. .is_config_pkt = true,
  342. .resp = HAL_NO_RESP,
  343. },
  344. {
  345. .size = HFI_ICA_FRAME_CMD_SIZE,
  346. .type = HFI_CMD_SESSION_CVP_ICA_FRAME,
  347. .is_config_pkt = false,
  348. .resp = HAL_NO_RESP,
  349. },
  350. {
  351. .size = HFI_HCD_CONFIG_CMD_SIZE,
  352. .type = HFI_CMD_SESSION_CVP_HCD_CONFIG,
  353. .is_config_pkt = true,
  354. .resp = HAL_NO_RESP,
  355. },
  356. {
  357. .size = HFI_HCD_FRAME_CMD_SIZE,
  358. .type = HFI_CMD_SESSION_CVP_HCD_FRAME,
  359. .is_config_pkt = false,
  360. .resp = HAL_NO_RESP,
  361. },
  362. {
  363. .size = HFI_DCM_CONFIG_CMD_SIZE,
  364. .type = HFI_CMD_SESSION_CVP_DC_CONFIG,
  365. .is_config_pkt = true,
  366. .resp = HAL_NO_RESP,
  367. },
  368. {
  369. .size = HFI_DCM_FRAME_CMD_SIZE,
  370. .type = HFI_CMD_SESSION_CVP_DC_FRAME,
  371. .is_config_pkt = false,
  372. .resp = HAL_NO_RESP,
  373. },
  374. {
  375. .size = HFI_DCM_CONFIG_CMD_SIZE,
  376. .type = HFI_CMD_SESSION_CVP_DCM_CONFIG,
  377. .is_config_pkt = true,
  378. .resp = HAL_NO_RESP,
  379. },
  380. {
  381. .size = HFI_DCM_FRAME_CMD_SIZE,
  382. .type = HFI_CMD_SESSION_CVP_DCM_FRAME,
  383. .is_config_pkt = false,
  384. .resp = HAL_NO_RESP,
  385. },
  386. {
  387. .size = HFI_PYS_HCD_CONFIG_CMD_SIZE,
  388. .type = HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG,
  389. .is_config_pkt = true,
  390. .resp = HAL_NO_RESP,
  391. },
  392. {
  393. .size = HFI_PYS_HCD_FRAME_CMD_SIZE,
  394. .type = HFI_CMD_SESSION_CVP_PYS_HCD_FRAME,
  395. .is_config_pkt = false,
  396. .resp = HAL_NO_RESP,
  397. },
  398. {
  399. .size = 0xFFFFFFFF,
  400. .type = HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS,
  401. .is_config_pkt = true,
  402. .resp = HAL_NO_RESP,
  403. },
  404. {
  405. .size = 0xFFFFFFFF,
  406. .type = HFI_CMD_SESSION_CVP_SET_SNAPSHOT_BUFFERS,
  407. .is_config_pkt = true,
  408. .resp = HAL_NO_RESP,
  409. },
  410. {
  411. .size = 0xFFFFFFFF,
  412. .type = HFI_CMD_SESSION_CVP_RELEASE_SNAPSHOT_BUFFERS,
  413. .is_config_pkt = true,
  414. .resp = HAL_NO_RESP,
  415. },
  416. {
  417. .size = 0xFFFFFFFF,
  418. .type = HFI_CMD_SESSION_CVP_SET_SNAPSHOT_MODE,
  419. .is_config_pkt = true,
  420. .resp = HAL_NO_RESP,
  421. },
  422. {
  423. .size = 0xFFFFFFFF,
  424. .type = HFI_CMD_SESSION_CVP_SNAPSHOT_WRITE_DONE,
  425. .is_config_pkt = true,
  426. .resp = HAL_NO_RESP,
  427. },
  428. {
  429. .size = 0xFFFFFFFF,
  430. .type = HFI_CMD_SESSION_CVP_FD_CONFIG,
  431. .is_config_pkt = true,
  432. .resp = HAL_NO_RESP,
  433. },
  434. {
  435. .size = 0xFFFFFFFF,
  436. .type = HFI_CMD_SESSION_CVP_FD_FRAME,
  437. .is_config_pkt = false,
  438. .resp = HAL_NO_RESP,
  439. },
  440. };
  441. int get_pkt_array_size(void)
  442. {
  443. return ARRAY_SIZE(cvp_hfi_defs);
  444. }
  445. int get_pkt_index(struct cvp_hal_session_cmd_pkt *hdr)
  446. {
  447. int i;
  448. for (i = 0; i < get_pkt_array_size(); i++)
  449. if (cvp_hfi_defs[i].type == hdr->packet_type)
  450. return i;
  451. return -EINVAL;
  452. }
  453. MODULE_DEVICE_TABLE(of, msm_cvp_dt_match);
  454. int cvp_of_fdt_get_ddrtype(void)
  455. {
  456. #ifdef FIXED_DDR_TYPE
  457. /* of_fdt_get_ddrtype() is usually unavailable during pre-sil */
  458. return DDR_TYPE_LPDDR5;
  459. #else
  460. return of_fdt_get_ddrtype();
  461. #endif
  462. }
  463. void *cvp_get_drv_data(struct device *dev)
  464. {
  465. struct msm_cvp_platform_data *driver_data;
  466. const struct of_device_id *match;
  467. uint32_t ddr_type = DDR_TYPE_LPDDR5;
  468. driver_data = &default_data;
  469. if (!IS_ENABLED(CONFIG_OF) || !dev->of_node)
  470. goto exit;
  471. match = of_match_node(msm_cvp_dt_match, dev->of_node);
  472. if (!match)
  473. return NULL;
  474. driver_data = (struct msm_cvp_platform_data *)match->data;
  475. if (!strcmp(match->compatible, "qcom,waipio-cvp")) {
  476. ddr_type = cvp_of_fdt_get_ddrtype();
  477. if (ddr_type == -ENOENT) {
  478. dprintk(CVP_ERR,
  479. "Failed to get ddr type, use LPDDR5\n");
  480. }
  481. if (driver_data->ubwc_config &&
  482. (ddr_type == DDR_TYPE_LPDDR4 ||
  483. ddr_type == DDR_TYPE_LPDDR4X))
  484. driver_data->ubwc_config->highest_bank_bit = 15;
  485. dprintk(CVP_CORE, "DDR Type 0x%x hbb 0x%x\n",
  486. ddr_type, driver_data->ubwc_config ?
  487. driver_data->ubwc_config->highest_bank_bit : -1);
  488. }
  489. exit:
  490. return driver_data;
  491. }