dp_rx.h 40 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425
  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _DP_RX_H
  19. #define _DP_RX_H
  20. #include "hal_rx.h"
  21. #include "dp_tx.h"
  22. #include "dp_peer.h"
  23. #include "dp_internal.h"
  24. #ifdef RXDMA_OPTIMIZATION
  25. #ifndef RX_DATA_BUFFER_ALIGNMENT
  26. #define RX_DATA_BUFFER_ALIGNMENT 128
  27. #endif
  28. #ifndef RX_MONITOR_BUFFER_ALIGNMENT
  29. #define RX_MONITOR_BUFFER_ALIGNMENT 128
  30. #endif
  31. #else /* RXDMA_OPTIMIZATION */
  32. #define RX_DATA_BUFFER_ALIGNMENT 4
  33. #define RX_MONITOR_BUFFER_ALIGNMENT 4
  34. #endif /* RXDMA_OPTIMIZATION */
  35. #ifdef QCA_HOST2FW_RXBUF_RING
  36. #define DP_WBM2SW_RBM HAL_RX_BUF_RBM_SW1_BM
  37. /* RBM value used for re-injecting defragmented packets into REO */
  38. #define DP_DEFRAG_RBM HAL_RX_BUF_RBM_SW3_BM
  39. #else
  40. #define DP_WBM2SW_RBM HAL_RX_BUF_RBM_SW3_BM
  41. #define DP_DEFRAG_RBM DP_WBM2SW_RBM
  42. #endif /* QCA_HOST2FW_RXBUF_RING */
  43. #define RX_BUFFER_RESERVATION 0
  44. #define DP_PEER_METADATA_PEER_ID_MASK 0x0000ffff
  45. #define DP_PEER_METADATA_PEER_ID_SHIFT 0
  46. #define DP_PEER_METADATA_VDEV_ID_MASK 0x003f0000
  47. #define DP_PEER_METADATA_VDEV_ID_SHIFT 16
  48. #define DP_PEER_METADATA_PEER_ID_GET(_peer_metadata) \
  49. (((_peer_metadata) & DP_PEER_METADATA_PEER_ID_MASK) \
  50. >> DP_PEER_METADATA_PEER_ID_SHIFT)
  51. #define DP_PEER_METADATA_VDEV_ID_GET(_peer_metadata) \
  52. (((_peer_metadata) & DP_PEER_METADATA_VDEV_ID_MASK) \
  53. >> DP_PEER_METADATA_VDEV_ID_SHIFT)
  54. #define DP_RX_DESC_MAGIC 0xdec0de
  55. /**
  56. * enum dp_rx_desc_state
  57. *
  58. * @RX_DESC_REPLENISH: rx desc replenished
  59. * @RX_DESC_FREELIST: rx desc in freelist
  60. */
  61. enum dp_rx_desc_state {
  62. RX_DESC_REPLENISHED,
  63. RX_DESC_IN_FREELIST,
  64. };
  65. /**
  66. * struct dp_rx_desc_dbg_info
  67. *
  68. * @freelist_caller: name of the function that put the
  69. * the rx desc in freelist
  70. * @freelist_ts: timestamp when the rx desc is put in
  71. * a freelist
  72. * @replenish_caller: name of the function that last
  73. * replenished the rx desc
  74. * @replenish_ts: last replenish timestamp
  75. */
  76. struct dp_rx_desc_dbg_info {
  77. char freelist_caller[QDF_MEM_FUNC_NAME_SIZE];
  78. uint64_t freelist_ts;
  79. char replenish_caller[QDF_MEM_FUNC_NAME_SIZE];
  80. uint64_t replenish_ts;
  81. };
  82. /**
  83. * struct dp_rx_desc
  84. *
  85. * @nbuf : VA of the "skb" posted
  86. * @rx_buf_start : VA of the original Rx buffer, before
  87. * movement of any skb->data pointer
  88. * @cookie : index into the sw array which holds
  89. * the sw Rx descriptors
  90. * Cookie space is 21 bits:
  91. * lower 18 bits -- index
  92. * upper 3 bits -- pool_id
  93. * @pool_id : pool Id for which this allocated.
  94. * Can only be used if there is no flow
  95. * steering
  96. * @in_use rx_desc is in use
  97. * @unmapped used to mark rx_desc an unmapped if the corresponding
  98. * nbuf is already unmapped
  99. */
  100. struct dp_rx_desc {
  101. qdf_nbuf_t nbuf;
  102. uint8_t *rx_buf_start;
  103. uint32_t cookie;
  104. uint8_t pool_id;
  105. #ifdef RX_DESC_DEBUG_CHECK
  106. uint32_t magic;
  107. struct dp_rx_desc_dbg_info *dbg_info;
  108. #endif
  109. uint8_t in_use:1,
  110. unmapped:1;
  111. };
  112. /* RX Descriptor Multi Page memory alloc related */
  113. #define DP_RX_DESC_OFFSET_NUM_BITS 8
  114. #define DP_RX_DESC_PAGE_ID_NUM_BITS 8
  115. #define DP_RX_DESC_POOL_ID_NUM_BITS 4
  116. #define DP_RX_DESC_PAGE_ID_SHIFT DP_RX_DESC_OFFSET_NUM_BITS
  117. #define DP_RX_DESC_POOL_ID_SHIFT \
  118. (DP_RX_DESC_OFFSET_NUM_BITS + DP_RX_DESC_PAGE_ID_NUM_BITS)
  119. #define RX_DESC_MULTI_PAGE_COOKIE_POOL_ID_MASK \
  120. (((1 << DP_RX_DESC_POOL_ID_NUM_BITS) - 1) << DP_RX_DESC_POOL_ID_SHIFT)
  121. #define RX_DESC_MULTI_PAGE_COOKIE_PAGE_ID_MASK \
  122. (((1 << DP_RX_DESC_PAGE_ID_NUM_BITS) - 1) << \
  123. DP_RX_DESC_PAGE_ID_SHIFT)
  124. #define RX_DESC_MULTI_PAGE_COOKIE_OFFSET_MASK \
  125. ((1 << DP_RX_DESC_OFFSET_NUM_BITS) - 1)
  126. #define DP_RX_DESC_MULTI_PAGE_COOKIE_GET_POOL_ID(_cookie) \
  127. (((_cookie) & RX_DESC_MULTI_PAGE_COOKIE_POOL_ID_MASK) >> \
  128. DP_RX_DESC_POOL_ID_SHIFT)
  129. #define DP_RX_DESC_MULTI_PAGE_COOKIE_GET_PAGE_ID(_cookie) \
  130. (((_cookie) & RX_DESC_MULTI_PAGE_COOKIE_PAGE_ID_MASK) >> \
  131. DP_RX_DESC_PAGE_ID_SHIFT)
  132. #define DP_RX_DESC_MULTI_PAGE_COOKIE_GET_OFFSET(_cookie) \
  133. ((_cookie) & RX_DESC_MULTI_PAGE_COOKIE_OFFSET_MASK)
  134. #define RX_DESC_COOKIE_INDEX_SHIFT 0
  135. #define RX_DESC_COOKIE_INDEX_MASK 0x3ffff /* 18 bits */
  136. #define RX_DESC_COOKIE_POOL_ID_SHIFT 18
  137. #define RX_DESC_COOKIE_POOL_ID_MASK 0x1c0000
  138. #define DP_RX_DESC_COOKIE_MAX \
  139. (RX_DESC_COOKIE_INDEX_MASK | RX_DESC_COOKIE_POOL_ID_MASK)
  140. #define DP_RX_DESC_COOKIE_POOL_ID_GET(_cookie) \
  141. (((_cookie) & RX_DESC_COOKIE_POOL_ID_MASK) >> \
  142. RX_DESC_COOKIE_POOL_ID_SHIFT)
  143. #define DP_RX_DESC_COOKIE_INDEX_GET(_cookie) \
  144. (((_cookie) & RX_DESC_COOKIE_INDEX_MASK) >> \
  145. RX_DESC_COOKIE_INDEX_SHIFT)
  146. #define FRAME_MASK_IPV4_ARP 1
  147. #define FRAME_MASK_IPV4_DHCP 2
  148. #define FRAME_MASK_IPV4_EAPOL 4
  149. #define FRAME_MASK_IPV6_DHCP 8
  150. #define dp_rx_add_to_free_desc_list(head, tail, new) \
  151. __dp_rx_add_to_free_desc_list(head, tail, new, __func__)
  152. #define dp_rx_buffers_replenish(soc, mac_id, rxdma_srng, rx_desc_pool, \
  153. num_buffers, desc_list, tail) \
  154. __dp_rx_buffers_replenish(soc, mac_id, rxdma_srng, rx_desc_pool, \
  155. num_buffers, desc_list, tail, __func__)
  156. #ifdef DP_RX_SPECIAL_FRAME_NEED
  157. /**
  158. * dp_rx_is_special_frame() - check is RX frame special needed
  159. *
  160. * @nbuf: RX skb pointer
  161. * @frame_mask: the mask for speical frame needed
  162. *
  163. * Check is RX frame wanted matched with mask
  164. *
  165. * Return: true - special frame needed, false - no
  166. */
  167. static inline
  168. bool dp_rx_is_special_frame(qdf_nbuf_t nbuf, uint32_t frame_mask)
  169. {
  170. if (((frame_mask & FRAME_MASK_IPV4_ARP) &&
  171. qdf_nbuf_is_ipv4_arp_pkt(nbuf)) ||
  172. ((frame_mask & FRAME_MASK_IPV4_DHCP) &&
  173. qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) ||
  174. ((frame_mask & FRAME_MASK_IPV4_EAPOL) &&
  175. qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) ||
  176. ((frame_mask & FRAME_MASK_IPV6_DHCP) &&
  177. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))
  178. return true;
  179. return false;
  180. }
  181. /**
  182. * dp_rx_deliver_special_frame() - Deliver the RX special frame to stack
  183. * if matches mask
  184. *
  185. * @soc: Datapath soc handler
  186. * @peer: pointer to DP peer
  187. * @nbuf: pointer to the skb of RX frame
  188. * @frame_mask: the mask for speical frame needed
  189. * @rx_tlv_hdr: start of rx tlv header
  190. *
  191. * note: Msdu_len must have been stored in QDF_NBUF_CB_RX_PKT_LEN(nbuf) and
  192. * single nbuf is expected.
  193. *
  194. * return: true - nbuf has been delivered to stack, false - not.
  195. */
  196. bool dp_rx_deliver_special_frame(struct dp_soc *soc, struct dp_peer *peer,
  197. qdf_nbuf_t nbuf, uint32_t frame_mask,
  198. uint8_t *rx_tlv_hdr);
  199. #else
  200. static inline
  201. bool dp_rx_is_special_frame(qdf_nbuf_t nbuf, uint32_t frame_mask)
  202. {
  203. return false;
  204. }
  205. static inline
  206. bool dp_rx_deliver_special_frame(struct dp_soc *soc, struct dp_peer *peer,
  207. qdf_nbuf_t nbuf, uint32_t frame_mask,
  208. uint8_t *rx_tlv_hdr)
  209. {
  210. return false;
  211. }
  212. #endif
  213. /* DOC: Offset to obtain LLC hdr
  214. *
  215. * In the case of Wifi parse error
  216. * to reach LLC header from beginning
  217. * of VLAN tag we need to skip 8 bytes.
  218. * Vlan_tag(4)+length(2)+length added
  219. * by HW(2) = 8 bytes.
  220. */
  221. #define DP_SKIP_VLAN 8
  222. /**
  223. * struct dp_rx_cached_buf - rx cached buffer
  224. * @list: linked list node
  225. * @buf: skb buffer
  226. */
  227. struct dp_rx_cached_buf {
  228. qdf_list_node_t node;
  229. qdf_nbuf_t buf;
  230. };
  231. /*
  232. *dp_rx_xor_block() - xor block of data
  233. *@b: destination data block
  234. *@a: source data block
  235. *@len: length of the data to process
  236. *
  237. *Returns: None
  238. */
  239. static inline void dp_rx_xor_block(uint8_t *b, const uint8_t *a, qdf_size_t len)
  240. {
  241. qdf_size_t i;
  242. for (i = 0; i < len; i++)
  243. b[i] ^= a[i];
  244. }
  245. /*
  246. *dp_rx_rotl() - rotate the bits left
  247. *@val: unsigned integer input value
  248. *@bits: number of bits
  249. *
  250. *Returns: Integer with left rotated by number of 'bits'
  251. */
  252. static inline uint32_t dp_rx_rotl(uint32_t val, int bits)
  253. {
  254. return (val << bits) | (val >> (32 - bits));
  255. }
  256. /*
  257. *dp_rx_rotr() - rotate the bits right
  258. *@val: unsigned integer input value
  259. *@bits: number of bits
  260. *
  261. *Returns: Integer with right rotated by number of 'bits'
  262. */
  263. static inline uint32_t dp_rx_rotr(uint32_t val, int bits)
  264. {
  265. return (val >> bits) | (val << (32 - bits));
  266. }
  267. /*
  268. * dp_set_rx_queue() - set queue_mapping in skb
  269. * @nbuf: skb
  270. * @queue_id: rx queue_id
  271. *
  272. * Return: void
  273. */
  274. #ifdef QCA_OL_RX_MULTIQ_SUPPORT
  275. static inline void dp_set_rx_queue(qdf_nbuf_t nbuf, uint8_t queue_id)
  276. {
  277. qdf_nbuf_record_rx_queue(nbuf, queue_id);
  278. return;
  279. }
  280. #else
  281. static inline void dp_set_rx_queue(qdf_nbuf_t nbuf, uint8_t queue_id)
  282. {
  283. }
  284. #endif
  285. /*
  286. *dp_rx_xswap() - swap the bits left
  287. *@val: unsigned integer input value
  288. *
  289. *Returns: Integer with bits swapped
  290. */
  291. static inline uint32_t dp_rx_xswap(uint32_t val)
  292. {
  293. return ((val & 0x00ff00ff) << 8) | ((val & 0xff00ff00) >> 8);
  294. }
  295. /*
  296. *dp_rx_get_le32_split() - get little endian 32 bits split
  297. *@b0: byte 0
  298. *@b1: byte 1
  299. *@b2: byte 2
  300. *@b3: byte 3
  301. *
  302. *Returns: Integer with split little endian 32 bits
  303. */
  304. static inline uint32_t dp_rx_get_le32_split(uint8_t b0, uint8_t b1, uint8_t b2,
  305. uint8_t b3)
  306. {
  307. return b0 | (b1 << 8) | (b2 << 16) | (b3 << 24);
  308. }
  309. /*
  310. *dp_rx_get_le32() - get little endian 32 bits
  311. *@b0: byte 0
  312. *@b1: byte 1
  313. *@b2: byte 2
  314. *@b3: byte 3
  315. *
  316. *Returns: Integer with little endian 32 bits
  317. */
  318. static inline uint32_t dp_rx_get_le32(const uint8_t *p)
  319. {
  320. return dp_rx_get_le32_split(p[0], p[1], p[2], p[3]);
  321. }
  322. /*
  323. * dp_rx_put_le32() - put little endian 32 bits
  324. * @p: destination char array
  325. * @v: source 32-bit integer
  326. *
  327. * Returns: None
  328. */
  329. static inline void dp_rx_put_le32(uint8_t *p, uint32_t v)
  330. {
  331. p[0] = (v) & 0xff;
  332. p[1] = (v >> 8) & 0xff;
  333. p[2] = (v >> 16) & 0xff;
  334. p[3] = (v >> 24) & 0xff;
  335. }
  336. /* Extract michal mic block of data */
  337. #define dp_rx_michael_block(l, r) \
  338. do { \
  339. r ^= dp_rx_rotl(l, 17); \
  340. l += r; \
  341. r ^= dp_rx_xswap(l); \
  342. l += r; \
  343. r ^= dp_rx_rotl(l, 3); \
  344. l += r; \
  345. r ^= dp_rx_rotr(l, 2); \
  346. l += r; \
  347. } while (0)
  348. /**
  349. * struct dp_rx_desc_list_elem_t
  350. *
  351. * @next : Next pointer to form free list
  352. * @rx_desc : DP Rx descriptor
  353. */
  354. union dp_rx_desc_list_elem_t {
  355. union dp_rx_desc_list_elem_t *next;
  356. struct dp_rx_desc rx_desc;
  357. };
  358. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  359. /**
  360. * dp_rx_desc_find() - find dp rx descriptor from page ID and offset
  361. * @page_id: Page ID
  362. * @offset: Offset of the descriptor element
  363. *
  364. * Return: RX descriptor element
  365. */
  366. union dp_rx_desc_list_elem_t *dp_rx_desc_find(uint16_t page_id, uint16_t offset,
  367. struct rx_desc_pool *rx_pool);
  368. static inline
  369. struct dp_rx_desc *dp_get_rx_desc_from_cookie(struct dp_soc *soc,
  370. struct rx_desc_pool *pool,
  371. uint32_t cookie)
  372. {
  373. uint8_t pool_id = DP_RX_DESC_MULTI_PAGE_COOKIE_GET_POOL_ID(cookie);
  374. uint16_t page_id = DP_RX_DESC_MULTI_PAGE_COOKIE_GET_PAGE_ID(cookie);
  375. uint8_t offset = DP_RX_DESC_MULTI_PAGE_COOKIE_GET_OFFSET(cookie);
  376. struct rx_desc_pool *rx_desc_pool;
  377. union dp_rx_desc_list_elem_t *rx_desc_elem;
  378. if (qdf_unlikely(pool_id >= MAX_RXDESC_POOLS))
  379. return NULL;
  380. rx_desc_pool = &pool[pool_id];
  381. rx_desc_elem = (union dp_rx_desc_list_elem_t *)
  382. (rx_desc_pool->desc_pages.cacheable_pages[page_id] +
  383. rx_desc_pool->elem_size * offset);
  384. return &rx_desc_elem->rx_desc;
  385. }
  386. /**
  387. * dp_rx_cookie_2_va_rxdma_buf() - Converts cookie to a virtual address of
  388. * the Rx descriptor on Rx DMA source ring buffer
  389. * @soc: core txrx main context
  390. * @cookie: cookie used to lookup virtual address
  391. *
  392. * Return: Pointer to the Rx descriptor
  393. */
  394. static inline
  395. struct dp_rx_desc *dp_rx_cookie_2_va_rxdma_buf(struct dp_soc *soc,
  396. uint32_t cookie)
  397. {
  398. return dp_get_rx_desc_from_cookie(soc, &soc->rx_desc_buf[0], cookie);
  399. }
  400. /**
  401. * dp_rx_cookie_2_va_mon_buf() - Converts cookie to a virtual address of
  402. * the Rx descriptor on monitor ring buffer
  403. * @soc: core txrx main context
  404. * @cookie: cookie used to lookup virtual address
  405. *
  406. * Return: Pointer to the Rx descriptor
  407. */
  408. static inline
  409. struct dp_rx_desc *dp_rx_cookie_2_va_mon_buf(struct dp_soc *soc,
  410. uint32_t cookie)
  411. {
  412. return dp_get_rx_desc_from_cookie(soc, &soc->rx_desc_mon[0], cookie);
  413. }
  414. /**
  415. * dp_rx_cookie_2_va_mon_status() - Converts cookie to a virtual address of
  416. * the Rx descriptor on monitor status ring buffer
  417. * @soc: core txrx main context
  418. * @cookie: cookie used to lookup virtual address
  419. *
  420. * Return: Pointer to the Rx descriptor
  421. */
  422. static inline
  423. struct dp_rx_desc *dp_rx_cookie_2_va_mon_status(struct dp_soc *soc,
  424. uint32_t cookie)
  425. {
  426. return dp_get_rx_desc_from_cookie(soc, &soc->rx_desc_status[0], cookie);
  427. }
  428. #else
  429. void dp_rx_desc_pool_init(struct dp_soc *soc, uint32_t pool_id,
  430. uint32_t pool_size,
  431. struct rx_desc_pool *rx_desc_pool);
  432. /**
  433. * dp_rx_cookie_2_va_rxdma_buf() - Converts cookie to a virtual address of
  434. * the Rx descriptor on Rx DMA source ring buffer
  435. * @soc: core txrx main context
  436. * @cookie: cookie used to lookup virtual address
  437. *
  438. * Return: void *: Virtual Address of the Rx descriptor
  439. */
  440. static inline
  441. void *dp_rx_cookie_2_va_rxdma_buf(struct dp_soc *soc, uint32_t cookie)
  442. {
  443. uint8_t pool_id = DP_RX_DESC_COOKIE_POOL_ID_GET(cookie);
  444. uint16_t index = DP_RX_DESC_COOKIE_INDEX_GET(cookie);
  445. struct rx_desc_pool *rx_desc_pool;
  446. if (qdf_unlikely(pool_id >= MAX_RXDESC_POOLS))
  447. return NULL;
  448. rx_desc_pool = &soc->rx_desc_buf[pool_id];
  449. if (qdf_unlikely(index >= rx_desc_pool->pool_size))
  450. return NULL;
  451. return &(soc->rx_desc_buf[pool_id].array[index].rx_desc);
  452. }
  453. /**
  454. * dp_rx_cookie_2_va_mon_buf() - Converts cookie to a virtual address of
  455. * the Rx descriptor on monitor ring buffer
  456. * @soc: core txrx main context
  457. * @cookie: cookie used to lookup virtual address
  458. *
  459. * Return: void *: Virtual Address of the Rx descriptor
  460. */
  461. static inline
  462. void *dp_rx_cookie_2_va_mon_buf(struct dp_soc *soc, uint32_t cookie)
  463. {
  464. uint8_t pool_id = DP_RX_DESC_COOKIE_POOL_ID_GET(cookie);
  465. uint16_t index = DP_RX_DESC_COOKIE_INDEX_GET(cookie);
  466. /* TODO */
  467. /* Add sanity for pool_id & index */
  468. return &(soc->rx_desc_mon[pool_id].array[index].rx_desc);
  469. }
  470. /**
  471. * dp_rx_cookie_2_va_mon_status() - Converts cookie to a virtual address of
  472. * the Rx descriptor on monitor status ring buffer
  473. * @soc: core txrx main context
  474. * @cookie: cookie used to lookup virtual address
  475. *
  476. * Return: void *: Virtual Address of the Rx descriptor
  477. */
  478. static inline
  479. void *dp_rx_cookie_2_va_mon_status(struct dp_soc *soc, uint32_t cookie)
  480. {
  481. uint8_t pool_id = DP_RX_DESC_COOKIE_POOL_ID_GET(cookie);
  482. uint16_t index = DP_RX_DESC_COOKIE_INDEX_GET(cookie);
  483. /* TODO */
  484. /* Add sanity for pool_id & index */
  485. return &(soc->rx_desc_status[pool_id].array[index].rx_desc);
  486. }
  487. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  488. #ifdef DP_RX_DESC_COOKIE_INVALIDATE
  489. static inline QDF_STATUS
  490. dp_rx_cookie_check_and_invalidate(hal_ring_desc_t ring_desc)
  491. {
  492. if (qdf_unlikely(HAL_RX_REO_BUF_COOKIE_INVALID_GET(ring_desc)))
  493. return QDF_STATUS_E_FAILURE;
  494. HAL_RX_REO_BUF_COOKIE_INVALID_SET(ring_desc);
  495. return QDF_STATUS_SUCCESS;
  496. }
  497. #else
  498. static inline QDF_STATUS
  499. dp_rx_cookie_check_and_invalidate(hal_ring_desc_t ring_desc)
  500. {
  501. return QDF_STATUS_SUCCESS;
  502. }
  503. #endif
  504. QDF_STATUS dp_rx_desc_pool_is_allocated(struct rx_desc_pool *rx_desc_pool);
  505. QDF_STATUS dp_rx_desc_pool_alloc(struct dp_soc *soc,
  506. uint32_t pool_size,
  507. struct rx_desc_pool *rx_desc_pool);
  508. void dp_rx_desc_pool_init(struct dp_soc *soc, uint32_t pool_id,
  509. uint32_t pool_size,
  510. struct rx_desc_pool *rx_desc_pool);
  511. void dp_rx_pdev_mon_buf_buffers_free(struct dp_pdev *pdev, uint32_t mac_id);
  512. void dp_rx_add_desc_list_to_free_list(struct dp_soc *soc,
  513. union dp_rx_desc_list_elem_t **local_desc_list,
  514. union dp_rx_desc_list_elem_t **tail,
  515. uint16_t pool_id,
  516. struct rx_desc_pool *rx_desc_pool);
  517. uint16_t dp_rx_get_free_desc_list(struct dp_soc *soc, uint32_t pool_id,
  518. struct rx_desc_pool *rx_desc_pool,
  519. uint16_t num_descs,
  520. union dp_rx_desc_list_elem_t **desc_list,
  521. union dp_rx_desc_list_elem_t **tail);
  522. QDF_STATUS dp_rx_pdev_desc_pool_alloc(struct dp_pdev *pdev);
  523. void dp_rx_pdev_desc_pool_free(struct dp_pdev *pdev);
  524. QDF_STATUS dp_rx_pdev_desc_pool_init(struct dp_pdev *pdev);
  525. void dp_rx_pdev_desc_pool_deinit(struct dp_pdev *pdev);
  526. void dp_rx_desc_pool_deinit(struct dp_soc *soc,
  527. struct rx_desc_pool *rx_desc_pool);
  528. QDF_STATUS dp_rx_pdev_attach(struct dp_pdev *pdev);
  529. QDF_STATUS dp_rx_pdev_buffers_alloc(struct dp_pdev *pdev);
  530. void dp_rx_pdev_buffers_free(struct dp_pdev *pdev);
  531. void dp_rx_pdev_detach(struct dp_pdev *pdev);
  532. void dp_print_napi_stats(struct dp_soc *soc);
  533. /**
  534. * dp_rx_vdev_detach() - detach vdev from dp rx
  535. * @vdev: virtual device instance
  536. *
  537. * Return: QDF_STATUS_SUCCESS: success
  538. * QDF_STATUS_E_RESOURCES: Error return
  539. */
  540. QDF_STATUS dp_rx_vdev_detach(struct dp_vdev *vdev);
  541. uint32_t
  542. dp_rx_process(struct dp_intr *int_ctx, hal_ring_handle_t hal_ring_hdl,
  543. uint8_t reo_ring_num,
  544. uint32_t quota);
  545. /**
  546. * dp_rx_err_process() - Processes error frames routed to REO error ring
  547. * @int_ctx: pointer to DP interrupt context
  548. * @soc: core txrx main context
  549. * @hal_ring: opaque pointer to the HAL Rx Error Ring, which will be serviced
  550. * @quota: No. of units (packets) that can be serviced in one shot.
  551. *
  552. * This function implements error processing and top level demultiplexer
  553. * for all the frames routed to REO error ring.
  554. *
  555. * Return: uint32_t: No. of elements processed
  556. */
  557. uint32_t dp_rx_err_process(struct dp_intr *int_ctx, struct dp_soc *soc,
  558. hal_ring_handle_t hal_ring_hdl, uint32_t quota);
  559. /**
  560. * dp_rx_wbm_err_process() - Processes error frames routed to WBM release ring
  561. * @int_ctx: pointer to DP interrupt context
  562. * @soc: core txrx main context
  563. * @hal_ring: opaque pointer to the HAL Rx Error Ring, which will be serviced
  564. * @quota: No. of units (packets) that can be serviced in one shot.
  565. *
  566. * This function implements error processing and top level demultiplexer
  567. * for all the frames routed to WBM2HOST sw release ring.
  568. *
  569. * Return: uint32_t: No. of elements processed
  570. */
  571. uint32_t
  572. dp_rx_wbm_err_process(struct dp_intr *int_ctx, struct dp_soc *soc,
  573. hal_ring_handle_t hal_ring_hdl, uint32_t quota);
  574. /**
  575. * dp_rx_sg_create() - create a frag_list for MSDUs which are spread across
  576. * multiple nbufs.
  577. * @nbuf: pointer to the first msdu of an amsdu.
  578. *
  579. * This function implements the creation of RX frag_list for cases
  580. * where an MSDU is spread across multiple nbufs.
  581. *
  582. * Return: returns the head nbuf which contains complete frag_list.
  583. */
  584. qdf_nbuf_t dp_rx_sg_create(qdf_nbuf_t nbuf);
  585. /*
  586. * dp_rx_desc_nbuf_and_pool_free() - free the sw rx desc pool called during
  587. * de-initialization of wifi module.
  588. *
  589. * @soc: core txrx main context
  590. * @pool_id: pool_id which is one of 3 mac_ids
  591. * @rx_desc_pool: rx descriptor pool pointer
  592. *
  593. * Return: None
  594. */
  595. void dp_rx_desc_nbuf_and_pool_free(struct dp_soc *soc, uint32_t pool_id,
  596. struct rx_desc_pool *rx_desc_pool);
  597. /*
  598. * dp_rx_desc_nbuf_free() - free the sw rx desc nbufs called during
  599. * de-initialization of wifi module.
  600. *
  601. * @soc: core txrx main context
  602. * @pool_id: pool_id which is one of 3 mac_ids
  603. * @rx_desc_pool: rx descriptor pool pointer
  604. *
  605. * Return: None
  606. */
  607. void dp_rx_desc_nbuf_free(struct dp_soc *soc,
  608. struct rx_desc_pool *rx_desc_pool);
  609. /*
  610. * dp_rx_desc_pool_free() - free the sw rx desc array called during
  611. * de-initialization of wifi module.
  612. *
  613. * @soc: core txrx main context
  614. * @rx_desc_pool: rx descriptor pool pointer
  615. *
  616. * Return: None
  617. */
  618. void dp_rx_desc_pool_free(struct dp_soc *soc,
  619. struct rx_desc_pool *rx_desc_pool);
  620. void dp_rx_deliver_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf_list,
  621. struct dp_peer *peer);
  622. #ifdef RX_DESC_DEBUG_CHECK
  623. /*
  624. * dp_rx_desc_alloc_dbg_info() - Alloc memory for rx descriptor debug
  625. * structure
  626. * @rx_desc: rx descriptor pointer
  627. *
  628. * Return: None
  629. */
  630. static inline
  631. void dp_rx_desc_alloc_dbg_info(struct dp_rx_desc *rx_desc)
  632. {
  633. rx_desc->dbg_info = qdf_mem_malloc(sizeof(struct dp_rx_desc_dbg_info));
  634. }
  635. /*
  636. * dp_rx_desc_free_dbg_info() - Free rx descriptor debug
  637. * structure memory
  638. * @rx_desc: rx descriptor pointer
  639. *
  640. * Return: None
  641. */
  642. static inline
  643. void dp_rx_desc_free_dbg_info(struct dp_rx_desc *rx_desc)
  644. {
  645. qdf_mem_free(rx_desc->dbg_info);
  646. }
  647. /*
  648. * dp_rx_desc_update_dbg_info() - Update rx descriptor debug info
  649. * structure memory
  650. * @rx_desc: rx descriptor pointer
  651. *
  652. * Return: None
  653. */
  654. static
  655. void dp_rx_desc_update_dbg_info(struct dp_rx_desc *rx_desc,
  656. const char *func_name, uint8_t flag)
  657. {
  658. struct dp_rx_desc_dbg_info *info = rx_desc->dbg_info;
  659. if (!info)
  660. return;
  661. if (flag == RX_DESC_REPLENISHED) {
  662. qdf_str_lcopy(info->replenish_caller, func_name,
  663. QDF_MEM_FUNC_NAME_SIZE);
  664. info->replenish_ts = qdf_get_log_timestamp();
  665. } else {
  666. qdf_str_lcopy(info->freelist_caller, func_name,
  667. QDF_MEM_FUNC_NAME_SIZE);
  668. info->freelist_ts = qdf_get_log_timestamp();
  669. }
  670. }
  671. #else
  672. static inline
  673. void dp_rx_desc_alloc_dbg_info(struct dp_rx_desc *rx_desc)
  674. {
  675. }
  676. static inline
  677. void dp_rx_desc_free_dbg_info(struct dp_rx_desc *rx_desc)
  678. {
  679. }
  680. static inline
  681. void dp_rx_desc_update_dbg_info(struct dp_rx_desc *rx_desc,
  682. const char *func_name, uint8_t flag)
  683. {
  684. }
  685. #endif /* RX_DESC_DEBUG_CHECK */
  686. /**
  687. * dp_rx_add_to_free_desc_list() - Adds to a local free descriptor list
  688. *
  689. * @head: pointer to the head of local free list
  690. * @tail: pointer to the tail of local free list
  691. * @new: new descriptor that is added to the free list
  692. * @func_name: caller func name
  693. *
  694. * Return: void:
  695. */
  696. static inline
  697. void __dp_rx_add_to_free_desc_list(union dp_rx_desc_list_elem_t **head,
  698. union dp_rx_desc_list_elem_t **tail,
  699. struct dp_rx_desc *new, const char *func_name)
  700. {
  701. qdf_assert(head && new);
  702. new->nbuf = NULL;
  703. new->in_use = 0;
  704. ((union dp_rx_desc_list_elem_t *)new)->next = *head;
  705. *head = (union dp_rx_desc_list_elem_t *)new;
  706. /* reset tail if head->next is NULL */
  707. if (!*tail || !(*head)->next)
  708. *tail = *head;
  709. dp_rx_desc_update_dbg_info(new, func_name, RX_DESC_IN_FREELIST);
  710. }
  711. uint8_t dp_rx_process_invalid_peer(struct dp_soc *soc, qdf_nbuf_t nbuf,
  712. uint8_t mac_id);
  713. void dp_rx_process_invalid_peer_wrapper(struct dp_soc *soc,
  714. qdf_nbuf_t mpdu, bool mpdu_done, uint8_t mac_id);
  715. void dp_rx_process_mic_error(struct dp_soc *soc, qdf_nbuf_t nbuf,
  716. uint8_t *rx_tlv_hdr, struct dp_peer *peer);
  717. void dp_2k_jump_handle(struct dp_soc *soc, qdf_nbuf_t nbuf, uint8_t *rx_tlv_hdr,
  718. uint16_t peer_id, uint8_t tid);
  719. #define DP_RX_LIST_APPEND(head, tail, elem) \
  720. do { \
  721. if (!(head)) { \
  722. (head) = (elem); \
  723. QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(head) = 1;\
  724. } else { \
  725. qdf_nbuf_set_next((tail), (elem)); \
  726. QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(head)++; \
  727. } \
  728. (tail) = (elem); \
  729. qdf_nbuf_set_next((tail), NULL); \
  730. } while (0)
  731. #define DP_RX_MERGE_TWO_LIST(phead, ptail, chead, ctail) \
  732. do { \
  733. if (!(phead)) { \
  734. (phead) = (chead); \
  735. } else { \
  736. qdf_nbuf_set_next((ptail), (chead)); \
  737. QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(phead) += \
  738. QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(chead); \
  739. } \
  740. (ptail) = (ctail); \
  741. qdf_nbuf_set_next((ptail), NULL); \
  742. } while (0)
  743. /*for qcn9000 emulation the pcie is complete phy and no address restrictions*/
  744. #if !defined(BUILD_X86) || defined(QCA_WIFI_QCN9000)
  745. static inline int check_x86_paddr(struct dp_soc *dp_soc, qdf_nbuf_t *rx_netbuf,
  746. qdf_dma_addr_t *paddr, struct rx_desc_pool *rx_desc_pool)
  747. {
  748. return QDF_STATUS_SUCCESS;
  749. }
  750. #else
  751. #define MAX_RETRY 100
  752. static inline int check_x86_paddr(struct dp_soc *dp_soc, qdf_nbuf_t *rx_netbuf,
  753. qdf_dma_addr_t *paddr, struct rx_desc_pool *rx_desc_pool)
  754. {
  755. uint32_t nbuf_retry = 0;
  756. int32_t ret;
  757. const uint32_t x86_phy_addr = 0x50000000;
  758. /*
  759. * in M2M emulation platforms (x86) the memory below 0x50000000
  760. * is reserved for target use, so any memory allocated in this
  761. * region should not be used by host
  762. */
  763. do {
  764. if (qdf_likely(*paddr > x86_phy_addr))
  765. return QDF_STATUS_SUCCESS;
  766. else {
  767. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  768. "phy addr %pK exceeded 0x50000000 trying again",
  769. paddr);
  770. nbuf_retry++;
  771. if ((*rx_netbuf)) {
  772. qdf_nbuf_unmap_single(dp_soc->osdev, *rx_netbuf,
  773. QDF_DMA_FROM_DEVICE);
  774. /* Not freeing buffer intentionally.
  775. * Observed that same buffer is getting
  776. * re-allocated resulting in longer load time
  777. * WMI init timeout.
  778. * This buffer is anyway not useful so skip it.
  779. **/
  780. }
  781. *rx_netbuf = qdf_nbuf_alloc(dp_soc->osdev,
  782. rx_desc_pool->buf_size,
  783. RX_BUFFER_RESERVATION,
  784. rx_desc_pool->buf_alignment,
  785. FALSE);
  786. if (qdf_unlikely(!(*rx_netbuf)))
  787. return QDF_STATUS_E_FAILURE;
  788. ret = qdf_nbuf_map_single(dp_soc->osdev, *rx_netbuf,
  789. QDF_DMA_FROM_DEVICE);
  790. if (qdf_unlikely(ret == QDF_STATUS_E_FAILURE)) {
  791. qdf_nbuf_free(*rx_netbuf);
  792. *rx_netbuf = NULL;
  793. continue;
  794. }
  795. *paddr = qdf_nbuf_get_frag_paddr(*rx_netbuf, 0);
  796. }
  797. } while (nbuf_retry < MAX_RETRY);
  798. if ((*rx_netbuf)) {
  799. qdf_nbuf_unmap_single(dp_soc->osdev, *rx_netbuf,
  800. QDF_DMA_FROM_DEVICE);
  801. qdf_nbuf_free(*rx_netbuf);
  802. }
  803. return QDF_STATUS_E_FAILURE;
  804. }
  805. #endif
  806. /**
  807. * dp_rx_cookie_2_link_desc_va() - Converts cookie to a virtual address of
  808. * the MSDU Link Descriptor
  809. * @soc: core txrx main context
  810. * @buf_info: buf_info includes cookie that is used to lookup
  811. * virtual address of link descriptor after deriving the page id
  812. * and the offset or index of the desc on the associatde page.
  813. *
  814. * This is the VA of the link descriptor, that HAL layer later uses to
  815. * retrieve the list of MSDU's for a given MPDU.
  816. *
  817. * Return: void *: Virtual Address of the Rx descriptor
  818. */
  819. static inline
  820. void *dp_rx_cookie_2_link_desc_va(struct dp_soc *soc,
  821. struct hal_buf_info *buf_info)
  822. {
  823. void *link_desc_va;
  824. struct qdf_mem_multi_page_t *pages;
  825. uint16_t page_id = LINK_DESC_COOKIE_PAGE_ID(buf_info->sw_cookie);
  826. pages = &soc->link_desc_pages;
  827. if (!pages)
  828. return NULL;
  829. if (qdf_unlikely(page_id >= pages->num_pages))
  830. return NULL;
  831. link_desc_va = pages->dma_pages[page_id].page_v_addr_start +
  832. (buf_info->paddr - pages->dma_pages[page_id].page_p_addr);
  833. return link_desc_va;
  834. }
  835. /**
  836. * dp_rx_cookie_2_mon_link_desc_va() - Converts cookie to a virtual address of
  837. * the MSDU Link Descriptor
  838. * @pdev: core txrx pdev context
  839. * @buf_info: buf_info includes cookie that used to lookup virtual address of
  840. * link descriptor. Normally this is just an index into a per pdev array.
  841. *
  842. * This is the VA of the link descriptor in monitor mode destination ring,
  843. * that HAL layer later uses to retrieve the list of MSDU's for a given MPDU.
  844. *
  845. * Return: void *: Virtual Address of the Rx descriptor
  846. */
  847. static inline
  848. void *dp_rx_cookie_2_mon_link_desc_va(struct dp_pdev *pdev,
  849. struct hal_buf_info *buf_info,
  850. int mac_id)
  851. {
  852. void *link_desc_va;
  853. struct qdf_mem_multi_page_t *pages;
  854. uint16_t page_id = LINK_DESC_COOKIE_PAGE_ID(buf_info->sw_cookie);
  855. pages = &pdev->soc->mon_link_desc_pages[mac_id];
  856. if (!pages)
  857. return NULL;
  858. if (qdf_unlikely(page_id >= pages->num_pages))
  859. return NULL;
  860. link_desc_va = pages->dma_pages[page_id].page_v_addr_start +
  861. (buf_info->paddr - pages->dma_pages[page_id].page_p_addr);
  862. return link_desc_va;
  863. }
  864. /**
  865. * dp_rx_defrag_concat() - Concatenate the fragments
  866. *
  867. * @dst: destination pointer to the buffer
  868. * @src: source pointer from where the fragment payload is to be copied
  869. *
  870. * Return: QDF_STATUS
  871. */
  872. static inline QDF_STATUS dp_rx_defrag_concat(qdf_nbuf_t dst, qdf_nbuf_t src)
  873. {
  874. /*
  875. * Inside qdf_nbuf_cat, if it is necessary to reallocate dst
  876. * to provide space for src, the headroom portion is copied from
  877. * the original dst buffer to the larger new dst buffer.
  878. * (This is needed, because the headroom of the dst buffer
  879. * contains the rx desc.)
  880. */
  881. if (!qdf_nbuf_cat(dst, src)) {
  882. /*
  883. * qdf_nbuf_cat does not free the src memory.
  884. * Free src nbuf before returning
  885. * For failure case the caller takes of freeing the nbuf
  886. */
  887. qdf_nbuf_free(src);
  888. return QDF_STATUS_SUCCESS;
  889. }
  890. return QDF_STATUS_E_DEFRAG_ERROR;
  891. }
  892. #ifndef FEATURE_WDS
  893. static inline QDF_STATUS dp_rx_ast_set_active(struct dp_soc *soc, uint16_t sa_idx, bool is_active)
  894. {
  895. return QDF_STATUS_SUCCESS;
  896. }
  897. static inline void
  898. dp_rx_wds_srcport_learn(struct dp_soc *soc,
  899. uint8_t *rx_tlv_hdr,
  900. struct dp_peer *ta_peer,
  901. qdf_nbuf_t nbuf,
  902. struct hal_rx_msdu_metadata msdu_metadata)
  903. {
  904. }
  905. #endif
  906. /*
  907. * dp_rx_desc_dump() - dump the sw rx descriptor
  908. *
  909. * @rx_desc: sw rx descriptor
  910. */
  911. static inline void dp_rx_desc_dump(struct dp_rx_desc *rx_desc)
  912. {
  913. dp_info("rx_desc->nbuf: %pK, rx_desc->cookie: %d, rx_desc->pool_id: %d, rx_desc->in_use: %d, rx_desc->unmapped: %d",
  914. rx_desc->nbuf, rx_desc->cookie, rx_desc->pool_id,
  915. rx_desc->in_use, rx_desc->unmapped);
  916. }
  917. /*
  918. * check_qwrap_multicast_loopback() - Check if rx packet is a loopback packet.
  919. * In qwrap mode, packets originated from
  920. * any vdev should not loopback and
  921. * should be dropped.
  922. * @vdev: vdev on which rx packet is received
  923. * @nbuf: rx pkt
  924. *
  925. */
  926. #if ATH_SUPPORT_WRAP
  927. static inline bool check_qwrap_multicast_loopback(struct dp_vdev *vdev,
  928. qdf_nbuf_t nbuf)
  929. {
  930. struct dp_vdev *psta_vdev;
  931. struct dp_pdev *pdev = vdev->pdev;
  932. uint8_t *data = qdf_nbuf_data(nbuf);
  933. if (qdf_unlikely(vdev->proxysta_vdev)) {
  934. /* In qwrap isolation mode, allow loopback packets as all
  935. * packets go to RootAP and Loopback on the mpsta.
  936. */
  937. if (vdev->isolation_vdev)
  938. return false;
  939. TAILQ_FOREACH(psta_vdev, &pdev->vdev_list, vdev_list_elem) {
  940. if (qdf_unlikely(psta_vdev->proxysta_vdev &&
  941. !qdf_mem_cmp(psta_vdev->mac_addr.raw,
  942. &data[QDF_MAC_ADDR_SIZE],
  943. QDF_MAC_ADDR_SIZE))) {
  944. /* Drop packet if source address is equal to
  945. * any of the vdev addresses.
  946. */
  947. return true;
  948. }
  949. }
  950. }
  951. return false;
  952. }
  953. #else
  954. static inline bool check_qwrap_multicast_loopback(struct dp_vdev *vdev,
  955. qdf_nbuf_t nbuf)
  956. {
  957. return false;
  958. }
  959. #endif
  960. #if defined(WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG) ||\
  961. defined(WLAN_SUPPORT_RX_TAG_STATISTICS) ||\
  962. defined(WLAN_SUPPORT_RX_FLOW_TAG)
  963. #include "dp_rx_tag.h"
  964. #endif
  965. #ifndef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG
  966. /**
  967. * dp_rx_update_protocol_tag() - Reads CCE metadata from the RX MSDU end TLV
  968. * and set the corresponding tag in QDF packet
  969. * @soc: core txrx main context
  970. * @vdev: vdev on which the packet is received
  971. * @nbuf: QDF pkt buffer on which the protocol tag should be set
  972. * @rx_tlv_hdr: rBbase address where the RX TLVs starts
  973. * @ring_index: REO ring number, not used for error & monitor ring
  974. * @is_reo_exception: flag to indicate if rx from REO ring or exception ring
  975. * @is_update_stats: flag to indicate whether to update stats or not
  976. * Return: void
  977. */
  978. static inline void
  979. dp_rx_update_protocol_tag(struct dp_soc *soc, struct dp_vdev *vdev,
  980. qdf_nbuf_t nbuf, uint8_t *rx_tlv_hdr,
  981. uint16_t ring_index,
  982. bool is_reo_exception, bool is_update_stats)
  983. {
  984. }
  985. #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */
  986. #ifndef WLAN_SUPPORT_RX_FLOW_TAG
  987. /**
  988. * dp_rx_update_flow_tag() - Reads FSE metadata from the RX MSDU end TLV
  989. * and set the corresponding tag in QDF packet
  990. * @soc: core txrx main context
  991. * @vdev: vdev on which the packet is received
  992. * @nbuf: QDF pkt buffer on which the protocol tag should be set
  993. * @rx_tlv_hdr: base address where the RX TLVs starts
  994. * @is_update_stats: flag to indicate whether to update stats or not
  995. *
  996. * Return: void
  997. */
  998. static inline void
  999. dp_rx_update_flow_tag(struct dp_soc *soc, struct dp_vdev *vdev,
  1000. qdf_nbuf_t nbuf, uint8_t *rx_tlv_hdr, bool update_stats)
  1001. {
  1002. }
  1003. #endif /* WLAN_SUPPORT_RX_FLOW_TAG */
  1004. #if !defined(WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG) &&\
  1005. !defined(WLAN_SUPPORT_RX_FLOW_TAG)
  1006. /**
  1007. * dp_rx_mon_update_protocol_flow_tag() - Performs necessary checks for monitor
  1008. * mode and then tags appropriate packets
  1009. * @soc: core txrx main context
  1010. * @vdev: pdev on which packet is received
  1011. * @msdu: QDF packet buffer on which the protocol tag should be set
  1012. * @rx_desc: base address where the RX TLVs start
  1013. * Return: void
  1014. */
  1015. static inline
  1016. void dp_rx_mon_update_protocol_flow_tag(struct dp_soc *soc,
  1017. struct dp_pdev *dp_pdev,
  1018. qdf_nbuf_t msdu, void *rx_desc)
  1019. {
  1020. }
  1021. #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG || WLAN_SUPPORT_RX_FLOW_TAG */
  1022. /*
  1023. * dp_rx_buffers_replenish() - replenish rxdma ring with rx nbufs
  1024. * called during dp rx initialization
  1025. * and at the end of dp_rx_process.
  1026. *
  1027. * @soc: core txrx main context
  1028. * @mac_id: mac_id which is one of 3 mac_ids
  1029. * @dp_rxdma_srng: dp rxdma circular ring
  1030. * @rx_desc_pool: Pointer to free Rx descriptor pool
  1031. * @num_req_buffers: number of buffer to be replenished
  1032. * @desc_list: list of descs if called from dp_rx_process
  1033. * or NULL during dp rx initialization or out of buffer
  1034. * interrupt.
  1035. * @tail: tail of descs list
  1036. * @func_name: name of the caller function
  1037. * Return: return success or failure
  1038. */
  1039. QDF_STATUS __dp_rx_buffers_replenish(struct dp_soc *dp_soc, uint32_t mac_id,
  1040. struct dp_srng *dp_rxdma_srng,
  1041. struct rx_desc_pool *rx_desc_pool,
  1042. uint32_t num_req_buffers,
  1043. union dp_rx_desc_list_elem_t **desc_list,
  1044. union dp_rx_desc_list_elem_t **tail,
  1045. const char *func_name);
  1046. /*
  1047. * dp_pdev_rx_buffers_attach() - replenish rxdma ring with rx nbufs
  1048. * called during dp rx initialization
  1049. *
  1050. * @soc: core txrx main context
  1051. * @mac_id: mac_id which is one of 3 mac_ids
  1052. * @dp_rxdma_srng: dp rxdma circular ring
  1053. * @rx_desc_pool: Pointer to free Rx descriptor pool
  1054. * @num_req_buffers: number of buffer to be replenished
  1055. *
  1056. * Return: return success or failure
  1057. */
  1058. QDF_STATUS
  1059. dp_pdev_rx_buffers_attach(struct dp_soc *dp_soc, uint32_t mac_id,
  1060. struct dp_srng *dp_rxdma_srng,
  1061. struct rx_desc_pool *rx_desc_pool,
  1062. uint32_t num_req_buffers);
  1063. /**
  1064. * dp_rx_link_desc_return() - Return a MPDU link descriptor to HW
  1065. * (WBM), following error handling
  1066. *
  1067. * @soc: core DP main context
  1068. * @buf_addr_info: opaque pointer to the REO error ring descriptor
  1069. * @buf_addr_info: void pointer to the buffer_addr_info
  1070. * @bm_action: put to idle_list or release to msdu_list
  1071. *
  1072. * Return: QDF_STATUS_E_FAILURE for failure else QDF_STATUS_SUCCESS
  1073. */
  1074. QDF_STATUS
  1075. dp_rx_link_desc_return(struct dp_soc *soc, hal_ring_desc_t ring_desc,
  1076. uint8_t bm_action);
  1077. /**
  1078. * dp_rx_link_desc_return_by_addr - Return a MPDU link descriptor to
  1079. * (WBM) by address
  1080. *
  1081. * @soc: core DP main context
  1082. * @link_desc_addr: link descriptor addr
  1083. *
  1084. * Return: QDF_STATUS_E_FAILURE for failure else QDF_STATUS_SUCCESS
  1085. */
  1086. QDF_STATUS
  1087. dp_rx_link_desc_return_by_addr(struct dp_soc *soc,
  1088. hal_buff_addrinfo_t link_desc_addr,
  1089. uint8_t bm_action);
  1090. /**
  1091. * dp_rxdma_err_process() - RxDMA error processing functionality
  1092. * @soc: core txrx main contex
  1093. * @mac_id: mac id which is one of 3 mac_ids
  1094. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  1095. * @quota: No. of units (packets) that can be serviced in one shot.
  1096. *
  1097. * Return: num of buffers processed
  1098. */
  1099. uint32_t
  1100. dp_rxdma_err_process(struct dp_intr *int_ctx, struct dp_soc *soc,
  1101. uint32_t mac_id, uint32_t quota);
  1102. void dp_rx_fill_mesh_stats(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1103. uint8_t *rx_tlv_hdr, struct dp_peer *peer);
  1104. QDF_STATUS dp_rx_filter_mesh_packets(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1105. uint8_t *rx_tlv_hdr);
  1106. int dp_wds_rx_policy_check(uint8_t *rx_tlv_hdr, struct dp_vdev *vdev,
  1107. struct dp_peer *peer);
  1108. qdf_nbuf_t
  1109. dp_rx_nbuf_prepare(struct dp_soc *soc, struct dp_pdev *pdev);
  1110. /*
  1111. * dp_rx_dump_info_and_assert() - dump RX Ring info and Rx Desc info
  1112. *
  1113. * @soc: core txrx main context
  1114. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  1115. * @ring_desc: opaque pointer to the RX ring descriptor
  1116. * @rx_desc: host rs descriptor
  1117. *
  1118. * Return: void
  1119. */
  1120. void dp_rx_dump_info_and_assert(struct dp_soc *soc,
  1121. hal_ring_handle_t hal_ring_hdl,
  1122. hal_ring_desc_t ring_desc,
  1123. struct dp_rx_desc *rx_desc);
  1124. void dp_rx_compute_delay(struct dp_vdev *vdev, qdf_nbuf_t nbuf);
  1125. #ifdef QCA_PEER_EXT_STATS
  1126. void dp_rx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  1127. qdf_nbuf_t nbuf);
  1128. #endif /* QCA_PEER_EXT_STATS */
  1129. #ifdef RX_DESC_DEBUG_CHECK
  1130. /**
  1131. * dp_rx_desc_check_magic() - check the magic value in dp_rx_desc
  1132. * @rx_desc: rx descriptor pointer
  1133. *
  1134. * Return: true, if magic is correct, else false.
  1135. */
  1136. static inline bool dp_rx_desc_check_magic(struct dp_rx_desc *rx_desc)
  1137. {
  1138. if (qdf_unlikely(rx_desc->magic != DP_RX_DESC_MAGIC))
  1139. return false;
  1140. rx_desc->magic = 0;
  1141. return true;
  1142. }
  1143. /**
  1144. * dp_rx_desc_prep() - prepare rx desc
  1145. * @rx_desc: rx descriptor pointer to be prepared
  1146. * @nbuf: nbuf to be associated with rx_desc
  1147. *
  1148. * Note: assumption is that we are associating a nbuf which is mapped
  1149. *
  1150. * Return: none
  1151. */
  1152. static inline void dp_rx_desc_prep(struct dp_rx_desc *rx_desc, qdf_nbuf_t nbuf)
  1153. {
  1154. rx_desc->magic = DP_RX_DESC_MAGIC;
  1155. rx_desc->nbuf = nbuf;
  1156. rx_desc->unmapped = 0;
  1157. }
  1158. #else
  1159. static inline bool dp_rx_desc_check_magic(struct dp_rx_desc *rx_desc)
  1160. {
  1161. return true;
  1162. }
  1163. static inline void dp_rx_desc_prep(struct dp_rx_desc *rx_desc, qdf_nbuf_t nbuf)
  1164. {
  1165. rx_desc->nbuf = nbuf;
  1166. rx_desc->unmapped = 0;
  1167. }
  1168. #endif /* RX_DESC_DEBUG_CHECK */
  1169. void dp_rx_process_rxdma_err(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1170. uint8_t *rx_tlv_hdr, struct dp_peer *peer,
  1171. uint8_t err_code, uint8_t mac_id);
  1172. #ifndef QCA_MULTIPASS_SUPPORT
  1173. static inline
  1174. bool dp_rx_multipass_process(struct dp_peer *peer, qdf_nbuf_t nbuf, uint8_t tid)
  1175. {
  1176. return false;
  1177. }
  1178. #else
  1179. bool dp_rx_multipass_process(struct dp_peer *peer, qdf_nbuf_t nbuf,
  1180. uint8_t tid);
  1181. #endif
  1182. #ifndef WLAN_RX_PKT_CAPTURE_ENH
  1183. static inline
  1184. QDF_STATUS dp_peer_set_rx_capture_enabled(struct dp_pdev *pdev,
  1185. struct dp_peer *peer_handle,
  1186. bool value, uint8_t *mac_addr)
  1187. {
  1188. return QDF_STATUS_SUCCESS;
  1189. }
  1190. #endif
  1191. /**
  1192. * dp_rx_deliver_to_stack() - deliver pkts to network stack
  1193. * Caller to hold peer refcount and check for valid peer
  1194. * @soc: soc
  1195. * @vdev: vdev
  1196. * @peer: peer
  1197. * @nbuf_head: skb list head
  1198. * @nbuf_tail: skb list tail
  1199. *
  1200. * Return: None
  1201. */
  1202. void dp_rx_deliver_to_stack(struct dp_soc *soc,
  1203. struct dp_vdev *vdev,
  1204. struct dp_peer *peer,
  1205. qdf_nbuf_t nbuf_head,
  1206. qdf_nbuf_t nbuf_tail);
  1207. #ifdef QCA_OL_RX_LOCK_LESS_ACCESS
  1208. /*
  1209. * dp_rx_ring_access_start()- Wrapper function to log access start of a hal ring
  1210. * @int_ctx: pointer to DP interrupt context
  1211. * @dp_soc - DP soc structure pointer
  1212. * @hal_ring_hdl - HAL ring handle
  1213. *
  1214. * Return: 0 on success; error on failure
  1215. */
  1216. static inline int
  1217. dp_rx_srng_access_start(struct dp_intr *int_ctx, struct dp_soc *soc,
  1218. hal_ring_handle_t hal_ring_hdl)
  1219. {
  1220. return hal_srng_access_start_unlocked(soc->hal_soc, hal_ring_hdl);
  1221. }
  1222. /*
  1223. * dp_rx_ring_access_end()- Wrapper function to log access end of a hal ring
  1224. * @int_ctx: pointer to DP interrupt context
  1225. * @dp_soc - DP soc structure pointer
  1226. * @hal_ring_hdl - HAL ring handle
  1227. *
  1228. * Return - None
  1229. */
  1230. static inline void
  1231. dp_rx_srng_access_end(struct dp_intr *int_ctx, struct dp_soc *soc,
  1232. hal_ring_handle_t hal_ring_hdl)
  1233. {
  1234. hal_srng_access_end_unlocked(soc->hal_soc, hal_ring_hdl);
  1235. }
  1236. #else
  1237. static inline int
  1238. dp_rx_srng_access_start(struct dp_intr *int_ctx, struct dp_soc *soc,
  1239. hal_ring_handle_t hal_ring_hdl)
  1240. {
  1241. return dp_srng_access_start(int_ctx, soc, hal_ring_hdl);
  1242. }
  1243. static inline void
  1244. dp_rx_srng_access_end(struct dp_intr *int_ctx, struct dp_soc *soc,
  1245. hal_ring_handle_t hal_ring_hdl)
  1246. {
  1247. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  1248. }
  1249. #endif
  1250. /*
  1251. * dp_rx_wbm_sg_list_reset() - Initialize sg list
  1252. *
  1253. * This api should be called at soc init and afterevery sg processing.
  1254. *@soc: DP SOC handle
  1255. */
  1256. static inline void dp_rx_wbm_sg_list_reset(struct dp_soc *soc)
  1257. {
  1258. if (soc) {
  1259. soc->wbm_sg_param.wbm_is_first_msdu_in_sg = false;
  1260. soc->wbm_sg_param.wbm_sg_nbuf_head = NULL;
  1261. soc->wbm_sg_param.wbm_sg_nbuf_tail = NULL;
  1262. soc->wbm_sg_param.wbm_sg_desc_msdu_len = 0;
  1263. }
  1264. }
  1265. /*
  1266. * dp_rx_wbm_sg_list_deinit() - De-initialize sg list
  1267. *
  1268. * This api should be called in down path, to avoid any leak.
  1269. *@soc: DP SOC handle
  1270. */
  1271. static inline void dp_rx_wbm_sg_list_deinit(struct dp_soc *soc)
  1272. {
  1273. if (soc) {
  1274. if (soc->wbm_sg_param.wbm_sg_nbuf_head)
  1275. qdf_nbuf_list_free(soc->wbm_sg_param.wbm_sg_nbuf_head);
  1276. dp_rx_wbm_sg_list_reset(soc);
  1277. }
  1278. }
  1279. #endif /* _DP_RX_H */