sde_kms.c 120 KB

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  1. /*
  2. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include <linux/qcom-iommu-util.h>
  52. #include "soc/qcom/secure_buffer.h"
  53. #include <linux/qtee_shmbridge.h>
  54. #include <linux/haven/hh_irq_lend.h>
  55. #define CREATE_TRACE_POINTS
  56. #include "sde_trace.h"
  57. /* defines for secure channel call */
  58. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  59. #define MDP_DEVICE_ID 0x1A
  60. #define DEMURA_REGION_NAME_MAX 32
  61. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  62. static const char * const iommu_ports[] = {
  63. "mdp_0",
  64. };
  65. /**
  66. * Controls size of event log buffer. Specified as a power of 2.
  67. */
  68. #define SDE_EVTLOG_SIZE 1024
  69. /*
  70. * To enable overall DRM driver logging
  71. * # echo 0x2 > /sys/module/drm/parameters/debug
  72. *
  73. * To enable DRM driver h/w logging
  74. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  75. *
  76. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  77. */
  78. #define SDE_DEBUGFS_DIR "msm_sde"
  79. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  80. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  81. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  82. /**
  83. * sdecustom - enable certain driver customizations for sde clients
  84. * Enabling this modifies the standard DRM behavior slightly and assumes
  85. * that the clients have specific knowledge about the modifications that
  86. * are involved, so don't enable this unless you know what you're doing.
  87. *
  88. * Parts of the driver that are affected by this setting may be located by
  89. * searching for invocations of the 'sde_is_custom_client()' function.
  90. *
  91. * This is disabled by default.
  92. */
  93. static bool sdecustom = true;
  94. module_param(sdecustom, bool, 0400);
  95. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  96. static int sde_kms_hw_init(struct msm_kms *kms);
  97. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  98. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  99. static int _sde_kms_register_events(struct msm_kms *kms,
  100. struct drm_mode_object *obj, u32 event, bool en);
  101. bool sde_is_custom_client(void)
  102. {
  103. return sdecustom;
  104. }
  105. #ifdef CONFIG_DEBUG_FS
  106. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  107. {
  108. struct msm_drm_private *priv;
  109. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  110. return NULL;
  111. priv = sde_kms->dev->dev_private;
  112. return priv->debug_root;
  113. }
  114. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  115. {
  116. void *p;
  117. int rc;
  118. void *debugfs_root;
  119. p = sde_hw_util_get_log_mask_ptr();
  120. if (!sde_kms || !p)
  121. return -EINVAL;
  122. debugfs_root = sde_debugfs_get_root(sde_kms);
  123. if (!debugfs_root)
  124. return -EINVAL;
  125. /* allow debugfs_root to be NULL */
  126. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  127. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  128. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  129. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  130. if (rc) {
  131. SDE_ERROR("failed to init perf %d\n", rc);
  132. return rc;
  133. }
  134. sde_rm_debugfs_init(&sde_kms->rm, debugfs_root);
  135. if (sde_kms->catalog->qdss_count)
  136. debugfs_create_u32("qdss", 0600, debugfs_root,
  137. (u32 *)&sde_kms->qdss_enabled);
  138. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  139. (u32 *)&sde_kms->pm_suspend_clk_dump);
  140. return 0;
  141. }
  142. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  143. {
  144. struct sde_kms *sde_kms = to_sde_kms(kms);
  145. /* don't need to NULL check debugfs_root */
  146. if (sde_kms) {
  147. sde_debugfs_vbif_destroy(sde_kms);
  148. sde_debugfs_core_irq_destroy(sde_kms);
  149. }
  150. }
  151. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  152. {
  153. int i;
  154. struct device *dev = sde_kms->dev->dev;
  155. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  156. for (i = 0; i < sde_kms->dsi_display_count; i++)
  157. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  158. return 0;
  159. }
  160. #else
  161. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  162. {
  163. return 0;
  164. }
  165. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  166. {
  167. }
  168. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  169. {
  170. return 0;
  171. }
  172. #endif
  173. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  174. struct drm_crtc *crtc)
  175. {
  176. struct drm_encoder *encoder;
  177. struct drm_device *dev;
  178. int ret;
  179. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  180. SDE_ERROR("invalid params\n");
  181. return;
  182. }
  183. if (!crtc->state->enable) {
  184. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  185. return;
  186. }
  187. if (!crtc->state->active) {
  188. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  189. return;
  190. }
  191. dev = crtc->dev;
  192. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  193. if (encoder->crtc != crtc)
  194. continue;
  195. /*
  196. * Video Mode - Wait for VSYNC
  197. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  198. * complete
  199. */
  200. SDE_EVT32_VERBOSE(DRMID(crtc));
  201. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  202. if (ret && ret != -EWOULDBLOCK) {
  203. SDE_ERROR(
  204. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  205. crtc->base.id, encoder->base.id, ret);
  206. break;
  207. }
  208. }
  209. }
  210. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  211. struct drm_crtc *crtc, bool enable)
  212. {
  213. struct drm_device *dev;
  214. struct msm_drm_private *priv;
  215. struct sde_mdss_cfg *sde_cfg;
  216. struct drm_plane *plane;
  217. int i, ret;
  218. dev = sde_kms->dev;
  219. priv = dev->dev_private;
  220. sde_cfg = sde_kms->catalog;
  221. ret = sde_vbif_halt_xin_mask(sde_kms,
  222. sde_cfg->sui_block_xin_mask, enable);
  223. if (ret) {
  224. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  225. return ret;
  226. }
  227. if (enable) {
  228. for (i = 0; i < priv->num_planes; i++) {
  229. plane = priv->planes[i];
  230. sde_plane_secure_ctrl_xin_client(plane, crtc);
  231. }
  232. }
  233. return 0;
  234. }
  235. /**
  236. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  237. * @sde_kms: Pointer to sde_kms struct
  238. * @vimd: switch the stage 2 translation to this VMID
  239. */
  240. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  241. {
  242. struct device dummy = {};
  243. dma_addr_t dma_handle;
  244. uint32_t num_sids;
  245. uint32_t *sec_sid;
  246. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  247. int ret = 0, i;
  248. struct qtee_shm shm;
  249. bool qtee_en = qtee_shmbridge_is_enabled();
  250. phys_addr_t mem_addr;
  251. u64 mem_size;
  252. num_sids = sde_cfg->sec_sid_mask_count;
  253. if (!num_sids) {
  254. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  255. return -EINVAL;
  256. }
  257. if (qtee_en) {
  258. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  259. &shm);
  260. if (ret)
  261. return -ENOMEM;
  262. sec_sid = (uint32_t *) shm.vaddr;
  263. mem_addr = shm.paddr;
  264. /**
  265. * SMMUSecureModeSwitch requires the size to be number of SID's
  266. * but shm allocates size in pages. Modify the args as per
  267. * client requirement.
  268. */
  269. mem_size = sizeof(uint32_t) * num_sids;
  270. } else {
  271. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  272. if (!sec_sid)
  273. return -ENOMEM;
  274. mem_addr = virt_to_phys(sec_sid);
  275. mem_size = sizeof(uint32_t) * num_sids;
  276. }
  277. for (i = 0; i < num_sids; i++) {
  278. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  279. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  280. }
  281. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  282. if (ret) {
  283. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  284. goto map_error;
  285. }
  286. set_dma_ops(&dummy, NULL);
  287. dma_handle = dma_map_single(&dummy, sec_sid,
  288. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  289. if (dma_mapping_error(&dummy, dma_handle)) {
  290. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  291. vmid);
  292. goto map_error;
  293. }
  294. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  295. vmid, num_sids, qtee_en);
  296. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  297. mem_size, vmid);
  298. if (ret)
  299. SDE_ERROR("Error:scm_call2, vmid %d, ret%d\n",
  300. vmid, ret);
  301. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  302. vmid, qtee_en, num_sids, ret);
  303. dma_unmap_single(&dummy, dma_handle,
  304. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  305. map_error:
  306. if (qtee_en)
  307. qtee_shmbridge_free_shm(&shm);
  308. else
  309. kfree(sec_sid);
  310. return ret;
  311. }
  312. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  313. {
  314. u32 ret;
  315. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  316. return 0;
  317. /* detach_all_contexts */
  318. ret = sde_kms_mmu_detach(sde_kms, false);
  319. if (ret) {
  320. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  321. goto mmu_error;
  322. }
  323. ret = _sde_kms_scm_call(sde_kms, vmid);
  324. if (ret) {
  325. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  326. goto scm_error;
  327. }
  328. return 0;
  329. scm_error:
  330. sde_kms_mmu_attach(sde_kms, false);
  331. mmu_error:
  332. atomic_dec(&sde_kms->detach_all_cb);
  333. return ret;
  334. }
  335. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  336. u32 old_vmid)
  337. {
  338. u32 ret;
  339. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  340. return 0;
  341. ret = _sde_kms_scm_call(sde_kms, vmid);
  342. if (ret) {
  343. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  344. goto scm_error;
  345. }
  346. /* attach_all_contexts */
  347. ret = sde_kms_mmu_attach(sde_kms, false);
  348. if (ret) {
  349. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  350. goto mmu_error;
  351. }
  352. return 0;
  353. mmu_error:
  354. _sde_kms_scm_call(sde_kms, old_vmid);
  355. scm_error:
  356. atomic_inc(&sde_kms->detach_all_cb);
  357. return ret;
  358. }
  359. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  360. {
  361. u32 ret;
  362. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  363. return 0;
  364. /* detach secure_context */
  365. ret = sde_kms_mmu_detach(sde_kms, true);
  366. if (ret) {
  367. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  368. goto mmu_error;
  369. }
  370. ret = _sde_kms_scm_call(sde_kms, vmid);
  371. if (ret) {
  372. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  373. goto scm_error;
  374. }
  375. return 0;
  376. scm_error:
  377. sde_kms_mmu_attach(sde_kms, true);
  378. mmu_error:
  379. atomic_dec(&sde_kms->detach_sec_cb);
  380. return ret;
  381. }
  382. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  383. u32 old_vmid)
  384. {
  385. u32 ret;
  386. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  387. return 0;
  388. ret = _sde_kms_scm_call(sde_kms, vmid);
  389. if (ret) {
  390. goto scm_error;
  391. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  392. }
  393. ret = sde_kms_mmu_attach(sde_kms, true);
  394. if (ret) {
  395. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  396. goto mmu_error;
  397. }
  398. return 0;
  399. mmu_error:
  400. _sde_kms_scm_call(sde_kms, old_vmid);
  401. scm_error:
  402. atomic_inc(&sde_kms->detach_sec_cb);
  403. return ret;
  404. }
  405. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  406. struct drm_crtc *crtc, bool enable)
  407. {
  408. int ret;
  409. if (enable) {
  410. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  411. if (ret < 0) {
  412. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  413. return ret;
  414. }
  415. sde_crtc_misr_setup(crtc, true, 1);
  416. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  417. if (ret) {
  418. sde_crtc_misr_setup(crtc, false, 0);
  419. pm_runtime_put_sync(sde_kms->dev->dev);
  420. return ret;
  421. }
  422. } else {
  423. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  424. sde_crtc_misr_setup(crtc, false, 0);
  425. pm_runtime_put_sync(sde_kms->dev->dev);
  426. }
  427. return 0;
  428. }
  429. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  430. bool post_commit)
  431. {
  432. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  433. int old_smmu_state = smmu_state->state;
  434. int ret = 0;
  435. u32 vmid;
  436. if (!sde_kms || !crtc) {
  437. SDE_ERROR("invalid argument(s)\n");
  438. return -EINVAL;
  439. }
  440. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  441. post_commit, smmu_state->sui_misr_state,
  442. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  443. if ((!smmu_state->transition_type) ||
  444. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  445. /* Bail out */
  446. return 0;
  447. /* enable sui misr if requested, before the transition */
  448. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  449. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  450. if (ret) {
  451. smmu_state->sui_misr_state = NONE;
  452. goto end;
  453. }
  454. }
  455. mutex_lock(&sde_kms->secure_transition_lock);
  456. switch (smmu_state->state) {
  457. case DETACH_ALL_REQ:
  458. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  459. if (!ret)
  460. smmu_state->state = DETACHED;
  461. break;
  462. case ATTACH_ALL_REQ:
  463. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  464. VMID_CP_SEC_DISPLAY);
  465. if (!ret) {
  466. smmu_state->state = ATTACHED;
  467. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  468. }
  469. break;
  470. case DETACH_SEC_REQ:
  471. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  472. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  473. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  474. if (!ret)
  475. smmu_state->state = DETACHED_SEC;
  476. break;
  477. case ATTACH_SEC_REQ:
  478. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  479. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  480. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  481. if (!ret) {
  482. smmu_state->state = ATTACHED;
  483. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  484. }
  485. break;
  486. default:
  487. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  488. DRMID(crtc), smmu_state->state,
  489. smmu_state->transition_type);
  490. ret = -EINVAL;
  491. break;
  492. }
  493. mutex_unlock(&sde_kms->secure_transition_lock);
  494. /* disable sui misr if requested, after the transition */
  495. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  496. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  497. if (ret)
  498. goto end;
  499. }
  500. end:
  501. smmu_state->transition_error = false;
  502. if (ret) {
  503. smmu_state->transition_error = true;
  504. SDE_ERROR(
  505. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  506. DRMID(crtc), old_smmu_state, smmu_state->state,
  507. smmu_state->secure_level, ret);
  508. smmu_state->state = smmu_state->prev_state;
  509. smmu_state->secure_level = smmu_state->prev_secure_level;
  510. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  511. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  512. }
  513. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  514. DRMID(crtc), old_smmu_state, smmu_state->state,
  515. smmu_state->secure_level, ret);
  516. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  517. smmu_state->transition_type,
  518. smmu_state->transition_error,
  519. smmu_state->secure_level, smmu_state->prev_secure_level,
  520. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  521. smmu_state->sui_misr_state = NONE;
  522. smmu_state->transition_type = NONE;
  523. return ret;
  524. }
  525. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  526. struct drm_atomic_state *state)
  527. {
  528. struct drm_crtc *crtc;
  529. struct drm_crtc_state *old_crtc_state;
  530. struct drm_plane_state *old_plane_state, *new_plane_state;
  531. struct drm_plane *plane;
  532. struct drm_plane_state *plane_state;
  533. struct sde_kms *sde_kms = to_sde_kms(kms);
  534. struct drm_device *dev = sde_kms->dev;
  535. int i, ops = 0, ret = 0;
  536. bool old_valid_fb = false;
  537. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  538. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  539. if (!crtc->state || !crtc->state->active)
  540. continue;
  541. /*
  542. * It is safe to assume only one active crtc,
  543. * and compatible translation modes on the
  544. * planes staged on this crtc.
  545. * otherwise validation would have failed.
  546. * For this CRTC,
  547. */
  548. /*
  549. * 1. Check if old state on the CRTC has planes
  550. * staged with valid fbs
  551. */
  552. for_each_old_plane_in_state(state, plane, plane_state, i) {
  553. if (!plane_state->crtc)
  554. continue;
  555. if (plane_state->fb) {
  556. old_valid_fb = true;
  557. break;
  558. }
  559. }
  560. /*
  561. * 2.Get the operations needed to be performed before
  562. * secure transition can be initiated.
  563. */
  564. ops = sde_crtc_get_secure_transition_ops(crtc,
  565. old_crtc_state, old_valid_fb);
  566. if (ops < 0) {
  567. SDE_ERROR("invalid secure operations %x\n", ops);
  568. return ops;
  569. }
  570. if (!ops) {
  571. smmu_state->transition_error = false;
  572. goto no_ops;
  573. }
  574. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  575. crtc->base.id, ops, crtc->state);
  576. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  577. /* 3. Perform operations needed for secure transition */
  578. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  579. SDE_DEBUG("wait_for_transfer_done\n");
  580. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  581. }
  582. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  583. SDE_DEBUG("cleanup planes\n");
  584. drm_atomic_helper_cleanup_planes(dev, state);
  585. for_each_oldnew_plane_in_state(state, plane,
  586. old_plane_state, new_plane_state, i)
  587. sde_plane_destroy_fb(old_plane_state);
  588. }
  589. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  590. SDE_DEBUG("secure ctrl\n");
  591. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  592. }
  593. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  594. SDE_DEBUG("prepare planes %d",
  595. crtc->state->plane_mask);
  596. drm_atomic_crtc_for_each_plane(plane,
  597. crtc) {
  598. const struct drm_plane_helper_funcs *funcs;
  599. plane_state = plane->state;
  600. funcs = plane->helper_private;
  601. SDE_DEBUG("psde:%d FB[%u]\n",
  602. plane->base.id,
  603. plane->fb->base.id);
  604. if (!funcs)
  605. continue;
  606. if (funcs->prepare_fb(plane, plane_state)) {
  607. ret = funcs->prepare_fb(plane,
  608. plane_state);
  609. if (ret)
  610. return ret;
  611. }
  612. }
  613. }
  614. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  615. SDE_DEBUG("secure operations completed\n");
  616. }
  617. no_ops:
  618. return 0;
  619. }
  620. static int _sde_kms_release_shared_buffer(unsigned int mem_addr,
  621. unsigned int splash_buffer_size,
  622. unsigned int ramdump_base,
  623. unsigned int ramdump_buffer_size)
  624. {
  625. unsigned long pfn_start, pfn_end, pfn_idx;
  626. int ret = 0;
  627. if (!mem_addr || !splash_buffer_size) {
  628. SDE_ERROR("invalid params\n");
  629. return -EINVAL;
  630. }
  631. /* leave ramdump memory only if base address matches */
  632. if (ramdump_base == mem_addr &&
  633. ramdump_buffer_size <= splash_buffer_size) {
  634. mem_addr += ramdump_buffer_size;
  635. splash_buffer_size -= ramdump_buffer_size;
  636. }
  637. pfn_start = mem_addr >> PAGE_SHIFT;
  638. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  639. ret = memblock_free(mem_addr, splash_buffer_size);
  640. if (ret) {
  641. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  642. return ret;
  643. }
  644. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  645. free_reserved_page(pfn_to_page(pfn_idx));
  646. return ret;
  647. }
  648. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  649. struct sde_splash_mem *splash)
  650. {
  651. struct msm_mmu *mmu = NULL;
  652. int ret = 0;
  653. if (!sde_kms->aspace[0]) {
  654. SDE_ERROR("aspace not found for sde kms node\n");
  655. return -EINVAL;
  656. }
  657. mmu = sde_kms->aspace[0]->mmu;
  658. if (!mmu) {
  659. SDE_ERROR("mmu not found for aspace\n");
  660. return -EINVAL;
  661. }
  662. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  663. SDE_ERROR("invalid input params for map\n");
  664. return -EINVAL;
  665. }
  666. if (!splash->ref_cnt) {
  667. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  668. splash->splash_buf_base,
  669. splash->splash_buf_size,
  670. IOMMU_READ | IOMMU_NOEXEC);
  671. if (ret)
  672. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  673. }
  674. splash->ref_cnt++;
  675. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  676. splash->splash_buf_base,
  677. splash->splash_buf_size,
  678. splash->ref_cnt);
  679. return ret;
  680. }
  681. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  682. {
  683. int i = 0;
  684. int ret = 0;
  685. struct sde_splash_mem *region;
  686. if (!sde_kms)
  687. return -EINVAL;
  688. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  689. region = sde_kms->splash_data.splash_display[i].splash;
  690. ret = _sde_kms_splash_mem_get(sde_kms, region);
  691. if (ret)
  692. return ret;
  693. /* Demura is optional and need not exist */
  694. region = sde_kms->splash_data.splash_display[i].demura;
  695. if (region) {
  696. ret = _sde_kms_splash_mem_get(sde_kms, region);
  697. if (ret)
  698. return ret;
  699. }
  700. }
  701. return ret;
  702. }
  703. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  704. struct sde_splash_mem *splash)
  705. {
  706. struct msm_mmu *mmu = NULL;
  707. int rc = 0;
  708. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  709. SDE_ERROR("invalid params\n");
  710. return -EINVAL;
  711. }
  712. mmu = sde_kms->aspace[0]->mmu;
  713. if (!splash || !splash->ref_cnt ||
  714. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  715. return -EINVAL;
  716. splash->ref_cnt--;
  717. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  718. splash->splash_buf_base, splash->ref_cnt);
  719. if (!splash->ref_cnt) {
  720. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  721. splash->splash_buf_size);
  722. rc = _sde_kms_release_shared_buffer(splash->splash_buf_base,
  723. splash->splash_buf_size, splash->ramdump_base,
  724. splash->ramdump_size);
  725. splash->splash_buf_base = 0;
  726. splash->splash_buf_size = 0;
  727. }
  728. return rc;
  729. }
  730. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  731. {
  732. int i = 0;
  733. int ret = 0, failure = 0;
  734. struct sde_splash_mem *region;
  735. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  736. return -EINVAL;
  737. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  738. region = sde_kms->splash_data.splash_display[i].splash;
  739. ret = _sde_kms_splash_mem_put(sde_kms, region);
  740. if (ret) {
  741. failure = 1;
  742. pr_err("Error unmapping splash mem for display %d\n",
  743. i);
  744. }
  745. /* Demura is optional and need not exist */
  746. region = sde_kms->splash_data.splash_display[i].demura;
  747. if (region) {
  748. ret = _sde_kms_splash_mem_put(sde_kms, region);
  749. if (ret) {
  750. failure = 1;
  751. pr_err("Error unmapping demura mem for display %d\n",
  752. i);
  753. }
  754. }
  755. }
  756. if (failure)
  757. ret = -EINVAL;
  758. return ret;
  759. }
  760. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  761. struct drm_connector_state *conn_state)
  762. {
  763. int lp_mode, blank;
  764. if (crtc_state->active)
  765. lp_mode = sde_connector_get_property(conn_state,
  766. CONNECTOR_PROP_LP);
  767. else
  768. lp_mode = SDE_MODE_DPMS_OFF;
  769. switch (lp_mode) {
  770. case SDE_MODE_DPMS_ON:
  771. blank = DRM_PANEL_BLANK_UNBLANK;
  772. break;
  773. case SDE_MODE_DPMS_LP1:
  774. case SDE_MODE_DPMS_LP2:
  775. blank = DRM_PANEL_BLANK_LP;
  776. break;
  777. case SDE_MODE_DPMS_OFF:
  778. default:
  779. blank = DRM_PANEL_BLANK_POWERDOWN;
  780. break;
  781. }
  782. return blank;
  783. }
  784. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  785. unsigned long event)
  786. {
  787. struct drm_connector *connector;
  788. struct drm_connector_state *old_conn_state;
  789. struct drm_crtc_state *old_crtc_state;
  790. struct drm_crtc *crtc;
  791. struct sde_connector *c_conn;
  792. int i, old_mode, new_mode, old_fps, new_fps;
  793. for_each_old_connector_in_state(old_state, connector,
  794. old_conn_state, i) {
  795. crtc = connector->state->crtc ? connector->state->crtc :
  796. old_conn_state->crtc;
  797. if (!crtc)
  798. continue;
  799. new_fps = drm_mode_vrefresh(&crtc->state->mode);
  800. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  801. if (old_conn_state->crtc) {
  802. old_crtc_state = drm_atomic_get_existing_crtc_state(
  803. old_state, old_conn_state->crtc);
  804. old_fps = drm_mode_vrefresh(&old_crtc_state->mode);
  805. old_mode = _sde_kms_get_blank(old_crtc_state,
  806. old_conn_state);
  807. } else {
  808. old_fps = 0;
  809. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  810. }
  811. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  812. c_conn = to_sde_connector(connector);
  813. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  814. c_conn->panel, crtc->state->active,
  815. old_conn_state->crtc, event);
  816. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  817. old_mode, new_mode, old_fps, new_fps);
  818. /* If suspend resume and fps change are happening
  819. * at the same time, give preference to power mode
  820. * changes rather than fps change.
  821. */
  822. if ((old_mode == new_mode) && (old_fps != new_fps))
  823. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  824. }
  825. }
  826. }
  827. static struct drm_crtc *sde_kms_vm_get_vm_crtc(
  828. struct drm_atomic_state *state)
  829. {
  830. int i;
  831. enum sde_crtc_vm_req vm_req = VM_REQ_NONE;
  832. struct drm_crtc *crtc, *vm_crtc = NULL;
  833. struct drm_crtc_state *new_cstate, *old_cstate;
  834. struct sde_crtc_state *vm_cstate;
  835. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  836. if (!new_cstate->active && !old_cstate->active)
  837. continue;
  838. vm_cstate = to_sde_crtc_state(new_cstate);
  839. vm_req = sde_crtc_get_property(vm_cstate,
  840. CRTC_PROP_VM_REQ_STATE);
  841. if (vm_req != VM_REQ_NONE) {
  842. SDE_DEBUG("valid vm request:%d found on crtc-%d\n",
  843. vm_req, crtc->base.id);
  844. vm_crtc = crtc;
  845. break;
  846. }
  847. }
  848. return vm_crtc;
  849. }
  850. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  851. struct drm_atomic_state *state)
  852. {
  853. struct drm_device *ddev;
  854. struct drm_crtc *crtc;
  855. struct drm_crtc_state *new_cstate;
  856. struct drm_encoder *encoder;
  857. struct drm_connector *connector;
  858. struct sde_vm_ops *vm_ops;
  859. struct sde_crtc_state *cstate;
  860. enum sde_crtc_vm_req vm_req;
  861. int rc = 0;
  862. ddev = sde_kms->dev;
  863. vm_ops = sde_vm_get_ops(sde_kms);
  864. if (!vm_ops)
  865. return -EINVAL;
  866. crtc = sde_kms_vm_get_vm_crtc(state);
  867. if (!crtc)
  868. return 0;
  869. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  870. cstate = to_sde_crtc_state(new_cstate);
  871. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  872. if (vm_req != VM_REQ_ACQUIRE)
  873. return 0;
  874. /* enable MDSS irq line */
  875. sde_irq_update(&sde_kms->base, true);
  876. /* clear the stale IRQ status bits */
  877. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  878. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  879. /* enable the display path IRQ's */
  880. drm_for_each_encoder_mask(encoder, crtc->dev,
  881. crtc->state->encoder_mask) {
  882. if (sde_encoder_in_clone_mode(encoder))
  883. continue;
  884. sde_encoder_irq_control(encoder, true);
  885. }
  886. /* Schedule ESD work */
  887. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  888. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  889. sde_connector_schedule_status_work(connector, true);
  890. /* enable vblank events */
  891. drm_crtc_vblank_on(crtc);
  892. /* handle non-SDE pre_acquire */
  893. if (vm_ops->vm_client_post_acquire)
  894. rc = vm_ops->vm_client_post_acquire(sde_kms);
  895. return rc;
  896. }
  897. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  898. struct drm_atomic_state *state)
  899. {
  900. struct drm_device *ddev;
  901. struct drm_plane *plane;
  902. struct drm_crtc *crtc;
  903. struct drm_crtc_state *new_cstate;
  904. struct sde_crtc_state *cstate;
  905. enum sde_crtc_vm_req vm_req;
  906. ddev = sde_kms->dev;
  907. crtc = sde_kms_vm_get_vm_crtc(state);
  908. if (!crtc)
  909. return 0;
  910. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  911. cstate = to_sde_crtc_state(new_cstate);
  912. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  913. if (vm_req != VM_REQ_ACQUIRE)
  914. return 0;
  915. /* Clear the stale IRQ status bits */
  916. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  917. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  918. /* Program the SID's for the trusted VM */
  919. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  920. sde_plane_set_sid(plane, 1);
  921. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  922. return 0;
  923. }
  924. static void sde_kms_prepare_commit(struct msm_kms *kms,
  925. struct drm_atomic_state *state)
  926. {
  927. struct sde_kms *sde_kms;
  928. struct msm_drm_private *priv;
  929. struct drm_device *dev;
  930. struct drm_encoder *encoder;
  931. struct drm_crtc *crtc;
  932. struct drm_crtc_state *cstate;
  933. struct sde_vm_ops *vm_ops;
  934. int i, rc;
  935. if (!kms)
  936. return;
  937. sde_kms = to_sde_kms(kms);
  938. dev = sde_kms->dev;
  939. if (!dev || !dev->dev_private)
  940. return;
  941. priv = dev->dev_private;
  942. SDE_ATRACE_BEGIN("prepare_commit");
  943. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  944. if (rc < 0) {
  945. SDE_ERROR("failed to enable power resources %d\n", rc);
  946. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  947. goto end;
  948. }
  949. if (sde_kms->first_kickoff) {
  950. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  951. sde_kms->first_kickoff = false;
  952. }
  953. for_each_new_crtc_in_state(state, crtc, cstate, i) {
  954. drm_for_each_encoder_mask(encoder, dev, cstate->encoder_mask) {
  955. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  956. SDE_ERROR("crtc:%d, initiating hw reset\n",
  957. DRMID(crtc));
  958. sde_encoder_needs_hw_reset(encoder);
  959. sde_crtc_set_needs_hw_reset(crtc);
  960. }
  961. }
  962. }
  963. /*
  964. * NOTE: for secure use cases we want to apply the new HW
  965. * configuration only after completing preparation for secure
  966. * transitions prepare below if any transtions is required.
  967. */
  968. sde_kms_prepare_secure_transition(kms, state);
  969. vm_ops = sde_vm_get_ops(sde_kms);
  970. if (!vm_ops)
  971. goto end_vm;
  972. if (vm_ops->vm_prepare_commit)
  973. vm_ops->vm_prepare_commit(sde_kms, state);
  974. end_vm:
  975. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  976. end:
  977. SDE_ATRACE_END("prepare_commit");
  978. }
  979. static void sde_kms_commit(struct msm_kms *kms,
  980. struct drm_atomic_state *old_state)
  981. {
  982. struct sde_kms *sde_kms;
  983. struct drm_crtc *crtc;
  984. struct drm_crtc_state *old_crtc_state;
  985. int i;
  986. if (!kms || !old_state)
  987. return;
  988. sde_kms = to_sde_kms(kms);
  989. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  990. SDE_ERROR("power resource is not enabled\n");
  991. return;
  992. }
  993. SDE_ATRACE_BEGIN("sde_kms_commit");
  994. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  995. if (crtc->state->active) {
  996. SDE_EVT32(DRMID(crtc), old_state);
  997. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  998. }
  999. }
  1000. SDE_ATRACE_END("sde_kms_commit");
  1001. }
  1002. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  1003. struct sde_splash_display *splash_display)
  1004. {
  1005. if (!sde_kms || !splash_display ||
  1006. !sde_kms->splash_data.num_splash_displays)
  1007. return;
  1008. if (sde_kms->splash_data.num_splash_regions) {
  1009. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  1010. if (splash_display->demura)
  1011. _sde_kms_splash_mem_put(sde_kms,
  1012. splash_display->demura);
  1013. }
  1014. sde_kms->splash_data.num_splash_displays--;
  1015. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  1016. sde_kms->splash_data.num_splash_displays);
  1017. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  1018. }
  1019. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  1020. struct drm_crtc *crtc)
  1021. {
  1022. struct msm_drm_private *priv;
  1023. struct sde_splash_display *splash_display;
  1024. int i;
  1025. if (!sde_kms || !crtc)
  1026. return;
  1027. priv = sde_kms->dev->dev_private;
  1028. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1029. return;
  1030. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1031. sde_kms->splash_data.num_splash_displays);
  1032. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1033. splash_display = &sde_kms->splash_data.splash_display[i];
  1034. if (splash_display->encoder &&
  1035. crtc == splash_display->encoder->crtc)
  1036. break;
  1037. }
  1038. if (i >= MAX_DSI_DISPLAYS)
  1039. return;
  1040. if (splash_display->cont_splash_enabled) {
  1041. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1042. splash_display, false);
  1043. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1044. }
  1045. /* remove the votes if all displays are done with splash */
  1046. if (!sde_kms->splash_data.num_splash_displays) {
  1047. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1048. sde_power_data_bus_set_quota(&priv->phandle, i,
  1049. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1050. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1051. pm_runtime_put_sync(sde_kms->dev->dev);
  1052. }
  1053. }
  1054. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1055. struct drm_atomic_state *state)
  1056. {
  1057. struct sde_vm_ops *vm_ops;
  1058. struct drm_device *ddev;
  1059. struct drm_crtc *crtc;
  1060. struct drm_plane *plane;
  1061. struct drm_encoder *encoder;
  1062. struct sde_crtc_state *cstate;
  1063. struct drm_crtc_state *new_cstate;
  1064. enum sde_crtc_vm_req vm_req;
  1065. int rc = 0;
  1066. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1067. return -EINVAL;
  1068. vm_ops = sde_vm_get_ops(sde_kms);
  1069. ddev = sde_kms->dev;
  1070. crtc = sde_kms_vm_get_vm_crtc(state);
  1071. if (!crtc)
  1072. return 0;
  1073. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1074. cstate = to_sde_crtc_state(new_cstate);
  1075. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1076. if (vm_req != VM_REQ_RELEASE)
  1077. return 0;
  1078. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1079. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1080. drm_for_each_encoder_mask(encoder, crtc->dev,
  1081. crtc->state->encoder_mask) {
  1082. if (sde_encoder_in_clone_mode(encoder))
  1083. continue;
  1084. sde_encoder_irq_control(encoder, false);
  1085. }
  1086. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1087. sde_plane_set_sid(plane, 0);
  1088. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1089. sde_vm_lock(sde_kms);
  1090. if (vm_ops->vm_release)
  1091. rc = vm_ops->vm_release(sde_kms);
  1092. sde_vm_unlock(sde_kms);
  1093. return rc;
  1094. }
  1095. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1096. struct drm_atomic_state *state)
  1097. {
  1098. struct drm_device *ddev;
  1099. struct drm_crtc *crtc;
  1100. struct drm_encoder *encoder;
  1101. struct drm_connector *connector;
  1102. int rc = 0;
  1103. ddev = sde_kms->dev;
  1104. crtc = sde_kms_vm_get_vm_crtc(state);
  1105. if (!crtc)
  1106. return 0;
  1107. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1108. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1109. /* disable ESD work */
  1110. list_for_each_entry(connector,
  1111. &ddev->mode_config.connector_list, head) {
  1112. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1113. sde_connector_schedule_status_work(connector, false);
  1114. }
  1115. /* disable SDE irq's */
  1116. drm_for_each_encoder_mask(encoder, crtc->dev,
  1117. crtc->state->encoder_mask) {
  1118. if (sde_encoder_in_clone_mode(encoder))
  1119. continue;
  1120. sde_encoder_irq_control(encoder, false);
  1121. }
  1122. /* disable IRQ line */
  1123. sde_irq_update(&sde_kms->base, false);
  1124. /* disable vblank events */
  1125. drm_crtc_vblank_off(crtc);
  1126. /* reset sw state */
  1127. sde_crtc_reset_sw_state(crtc);
  1128. return rc;
  1129. }
  1130. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1131. struct drm_atomic_state *state)
  1132. {
  1133. struct sde_vm_ops *vm_ops;
  1134. struct sde_crtc_state *cstate;
  1135. struct drm_crtc *crtc;
  1136. struct drm_crtc_state *new_cstate;
  1137. enum sde_crtc_vm_req vm_req;
  1138. int rc = 0;
  1139. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1140. return -EINVAL;
  1141. vm_ops = sde_vm_get_ops(sde_kms);
  1142. crtc = sde_kms_vm_get_vm_crtc(state);
  1143. if (!crtc)
  1144. return 0;
  1145. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1146. cstate = to_sde_crtc_state(new_cstate);
  1147. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1148. if (vm_req != VM_REQ_RELEASE)
  1149. return 0;
  1150. /* handle SDE pre-release */
  1151. rc = sde_kms_vm_pre_release(sde_kms, state);
  1152. if (rc) {
  1153. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1154. goto exit;
  1155. }
  1156. /* properly handoff color processing features */
  1157. sde_cp_crtc_vm_primary_handoff(crtc);
  1158. /* handle non-SDE clients pre-release */
  1159. if (vm_ops->vm_client_pre_release) {
  1160. rc = vm_ops->vm_client_pre_release(sde_kms);
  1161. if (rc) {
  1162. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1163. rc);
  1164. goto exit;
  1165. }
  1166. }
  1167. sde_vm_lock(sde_kms);
  1168. /* release HW */
  1169. if (vm_ops->vm_release) {
  1170. rc = vm_ops->vm_release(sde_kms);
  1171. if (rc)
  1172. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1173. }
  1174. sde_vm_unlock(sde_kms);
  1175. exit:
  1176. return rc;
  1177. }
  1178. static void sde_kms_complete_commit(struct msm_kms *kms,
  1179. struct drm_atomic_state *old_state)
  1180. {
  1181. struct sde_kms *sde_kms;
  1182. struct msm_drm_private *priv;
  1183. struct drm_crtc *crtc;
  1184. struct drm_crtc_state *old_crtc_state;
  1185. struct drm_connector *connector;
  1186. struct drm_connector_state *old_conn_state;
  1187. struct msm_display_conn_params params;
  1188. struct sde_vm_ops *vm_ops;
  1189. int i, rc = 0;
  1190. if (!kms || !old_state)
  1191. return;
  1192. sde_kms = to_sde_kms(kms);
  1193. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1194. return;
  1195. priv = sde_kms->dev->dev_private;
  1196. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1197. SDE_ERROR("power resource is not enabled\n");
  1198. return;
  1199. }
  1200. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1201. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1202. sde_crtc_complete_commit(crtc, old_crtc_state);
  1203. /* complete secure transitions if any */
  1204. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1205. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1206. }
  1207. for_each_old_connector_in_state(old_state, connector,
  1208. old_conn_state, i) {
  1209. struct sde_connector *c_conn;
  1210. c_conn = to_sde_connector(connector);
  1211. if (!c_conn->ops.post_kickoff)
  1212. continue;
  1213. memset(&params, 0, sizeof(params));
  1214. sde_connector_complete_qsync_commit(connector, &params);
  1215. rc = c_conn->ops.post_kickoff(connector, &params);
  1216. if (rc) {
  1217. pr_err("Connector Post kickoff failed rc=%d\n",
  1218. rc);
  1219. }
  1220. }
  1221. vm_ops = sde_vm_get_ops(sde_kms);
  1222. if (vm_ops && vm_ops->vm_post_commit) {
  1223. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1224. if (rc)
  1225. SDE_ERROR("vm post commit failed, rc = %d\n",
  1226. rc);
  1227. }
  1228. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1229. pm_runtime_put_sync(sde_kms->dev->dev);
  1230. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1231. _sde_kms_release_splash_resource(sde_kms, crtc);
  1232. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1233. SDE_ATRACE_END("sde_kms_complete_commit");
  1234. }
  1235. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1236. struct drm_crtc *crtc)
  1237. {
  1238. struct drm_encoder *encoder;
  1239. struct drm_device *dev;
  1240. int ret;
  1241. bool cwb_disabling;
  1242. if (!kms || !crtc || !crtc->state) {
  1243. SDE_ERROR("invalid params\n");
  1244. return;
  1245. }
  1246. dev = crtc->dev;
  1247. if (!crtc->state->enable) {
  1248. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1249. return;
  1250. }
  1251. if (!crtc->state->active) {
  1252. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1253. return;
  1254. }
  1255. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1256. SDE_ERROR("power resource is not enabled\n");
  1257. return;
  1258. }
  1259. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1260. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1261. cwb_disabling = false;
  1262. if (encoder->crtc != crtc) {
  1263. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1264. crtc);
  1265. if (!cwb_disabling)
  1266. continue;
  1267. }
  1268. /*
  1269. * Wait for post-flush if necessary to delay before
  1270. * plane_cleanup. For example, wait for vsync in case of video
  1271. * mode panels. This may be a no-op for command mode panels.
  1272. */
  1273. SDE_EVT32_VERBOSE(DRMID(crtc));
  1274. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1275. if (ret && ret != -EWOULDBLOCK) {
  1276. SDE_ERROR("wait for commit done returned %d\n", ret);
  1277. sde_crtc_request_frame_reset(crtc);
  1278. break;
  1279. }
  1280. sde_crtc_complete_flip(crtc, NULL);
  1281. if (cwb_disabling)
  1282. sde_encoder_virt_reset(encoder);
  1283. }
  1284. sde_crtc_static_cache_read_kickoff(crtc);
  1285. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1286. }
  1287. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1288. struct drm_atomic_state *old_state)
  1289. {
  1290. struct drm_crtc *crtc;
  1291. struct drm_crtc_state *old_crtc_state;
  1292. int i, rc;
  1293. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1294. SDE_ERROR("invalid argument(s)\n");
  1295. return;
  1296. }
  1297. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1298. retry:
  1299. /* attempt to acquire ww mutex for connection */
  1300. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1301. old_state->acquire_ctx);
  1302. if (rc == -EDEADLK) {
  1303. drm_modeset_backoff(old_state->acquire_ctx);
  1304. goto retry;
  1305. }
  1306. /* old_state actually contains updated crtc pointers */
  1307. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1308. if (crtc->state->active || crtc->state->active_changed)
  1309. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1310. }
  1311. SDE_ATRACE_END("sde_kms_prepare_fence");
  1312. }
  1313. /**
  1314. * _sde_kms_get_displays - query for underlying display handles and cache them
  1315. * @sde_kms: Pointer to sde kms structure
  1316. * Returns: Zero on success
  1317. */
  1318. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1319. {
  1320. int rc = -ENOMEM;
  1321. if (!sde_kms) {
  1322. SDE_ERROR("invalid sde kms\n");
  1323. return -EINVAL;
  1324. }
  1325. /* dsi */
  1326. sde_kms->dsi_displays = NULL;
  1327. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1328. if (sde_kms->dsi_display_count) {
  1329. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1330. sizeof(void *),
  1331. GFP_KERNEL);
  1332. if (!sde_kms->dsi_displays) {
  1333. SDE_ERROR("failed to allocate dsi displays\n");
  1334. goto exit_deinit_dsi;
  1335. }
  1336. sde_kms->dsi_display_count =
  1337. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1338. sde_kms->dsi_display_count);
  1339. }
  1340. /* wb */
  1341. sde_kms->wb_displays = NULL;
  1342. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1343. if (sde_kms->wb_display_count) {
  1344. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1345. sizeof(void *),
  1346. GFP_KERNEL);
  1347. if (!sde_kms->wb_displays) {
  1348. SDE_ERROR("failed to allocate wb displays\n");
  1349. goto exit_deinit_wb;
  1350. }
  1351. sde_kms->wb_display_count =
  1352. wb_display_get_displays(sde_kms->wb_displays,
  1353. sde_kms->wb_display_count);
  1354. }
  1355. /* dp */
  1356. sde_kms->dp_displays = NULL;
  1357. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1358. if (sde_kms->dp_display_count) {
  1359. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1360. sizeof(void *), GFP_KERNEL);
  1361. if (!sde_kms->dp_displays) {
  1362. SDE_ERROR("failed to allocate dp displays\n");
  1363. goto exit_deinit_dp;
  1364. }
  1365. sde_kms->dp_display_count =
  1366. dp_display_get_displays(sde_kms->dp_displays,
  1367. sde_kms->dp_display_count);
  1368. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1369. }
  1370. return 0;
  1371. exit_deinit_dp:
  1372. kfree(sde_kms->dp_displays);
  1373. sde_kms->dp_stream_count = 0;
  1374. sde_kms->dp_display_count = 0;
  1375. sde_kms->dp_displays = NULL;
  1376. exit_deinit_wb:
  1377. kfree(sde_kms->wb_displays);
  1378. sde_kms->wb_display_count = 0;
  1379. sde_kms->wb_displays = NULL;
  1380. exit_deinit_dsi:
  1381. kfree(sde_kms->dsi_displays);
  1382. sde_kms->dsi_display_count = 0;
  1383. sde_kms->dsi_displays = NULL;
  1384. return rc;
  1385. }
  1386. /**
  1387. * _sde_kms_release_displays - release cache of underlying display handles
  1388. * @sde_kms: Pointer to sde kms structure
  1389. */
  1390. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1391. {
  1392. if (!sde_kms) {
  1393. SDE_ERROR("invalid sde kms\n");
  1394. return;
  1395. }
  1396. kfree(sde_kms->wb_displays);
  1397. sde_kms->wb_displays = NULL;
  1398. sde_kms->wb_display_count = 0;
  1399. kfree(sde_kms->dsi_displays);
  1400. sde_kms->dsi_displays = NULL;
  1401. sde_kms->dsi_display_count = 0;
  1402. }
  1403. /**
  1404. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1405. * for underlying displays
  1406. * @dev: Pointer to drm device structure
  1407. * @priv: Pointer to private drm device data
  1408. * @sde_kms: Pointer to sde kms structure
  1409. * Returns: Zero on success
  1410. */
  1411. static int _sde_kms_setup_displays(struct drm_device *dev,
  1412. struct msm_drm_private *priv,
  1413. struct sde_kms *sde_kms)
  1414. {
  1415. static const struct sde_connector_ops dsi_ops = {
  1416. .set_info_blob = dsi_conn_set_info_blob,
  1417. .detect = dsi_conn_detect,
  1418. .get_modes = dsi_connector_get_modes,
  1419. .pre_destroy = dsi_connector_put_modes,
  1420. .mode_valid = dsi_conn_mode_valid,
  1421. .get_info = dsi_display_get_info,
  1422. .set_backlight = dsi_display_set_backlight,
  1423. .soft_reset = dsi_display_soft_reset,
  1424. .pre_kickoff = dsi_conn_pre_kickoff,
  1425. .clk_ctrl = dsi_display_clk_ctrl,
  1426. .set_power = dsi_display_set_power,
  1427. .get_mode_info = dsi_conn_get_mode_info,
  1428. .get_dst_format = dsi_display_get_dst_format,
  1429. .post_kickoff = dsi_conn_post_kickoff,
  1430. .check_status = dsi_display_check_status,
  1431. .enable_event = dsi_conn_enable_event,
  1432. .cmd_transfer = dsi_display_cmd_transfer,
  1433. .cont_splash_config = dsi_display_cont_splash_config,
  1434. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1435. .get_panel_vfp = dsi_display_get_panel_vfp,
  1436. .get_default_lms = dsi_display_get_default_lms,
  1437. .cmd_receive = dsi_display_cmd_receive,
  1438. .install_properties = NULL,
  1439. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1440. .set_dyn_bit_clk = dsi_conn_set_dyn_bit_clk,
  1441. .get_qsync_min_fps = dsi_display_get_qsync_min_fps,
  1442. .prepare_commit = dsi_conn_prepare_commit,
  1443. };
  1444. static const struct sde_connector_ops wb_ops = {
  1445. .post_init = sde_wb_connector_post_init,
  1446. .set_info_blob = sde_wb_connector_set_info_blob,
  1447. .detect = sde_wb_connector_detect,
  1448. .get_modes = sde_wb_connector_get_modes,
  1449. .set_property = sde_wb_connector_set_property,
  1450. .get_info = sde_wb_get_info,
  1451. .soft_reset = NULL,
  1452. .get_mode_info = sde_wb_get_mode_info,
  1453. .get_dst_format = NULL,
  1454. .check_status = NULL,
  1455. .cmd_transfer = NULL,
  1456. .cont_splash_config = NULL,
  1457. .cont_splash_res_disable = NULL,
  1458. .get_panel_vfp = NULL,
  1459. .cmd_receive = NULL,
  1460. .install_properties = NULL,
  1461. .set_dyn_bit_clk = NULL,
  1462. .set_allowed_mode_switch = NULL,
  1463. };
  1464. static const struct sde_connector_ops dp_ops = {
  1465. .post_init = dp_connector_post_init,
  1466. .detect = dp_connector_detect,
  1467. .get_modes = dp_connector_get_modes,
  1468. .atomic_check = dp_connector_atomic_check,
  1469. .mode_valid = dp_connector_mode_valid,
  1470. .get_info = dp_connector_get_info,
  1471. .get_mode_info = dp_connector_get_mode_info,
  1472. .post_open = dp_connector_post_open,
  1473. .check_status = NULL,
  1474. .set_colorspace = dp_connector_set_colorspace,
  1475. .config_hdr = dp_connector_config_hdr,
  1476. .cmd_transfer = NULL,
  1477. .cont_splash_config = NULL,
  1478. .cont_splash_res_disable = NULL,
  1479. .get_panel_vfp = NULL,
  1480. .update_pps = dp_connector_update_pps,
  1481. .cmd_receive = NULL,
  1482. .install_properties = dp_connector_install_properties,
  1483. .set_allowed_mode_switch = NULL,
  1484. .set_dyn_bit_clk = NULL,
  1485. };
  1486. struct msm_display_info info;
  1487. struct drm_encoder *encoder;
  1488. void *display, *connector;
  1489. int i, max_encoders;
  1490. int rc = 0;
  1491. u32 dsc_count = 0, mixer_count = 0;
  1492. u32 max_dp_dsc_count, max_dp_mixer_count;
  1493. if (!dev || !priv || !sde_kms) {
  1494. SDE_ERROR("invalid argument(s)\n");
  1495. return -EINVAL;
  1496. }
  1497. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1498. sde_kms->dp_display_count +
  1499. sde_kms->dp_stream_count;
  1500. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1501. max_encoders = ARRAY_SIZE(priv->encoders);
  1502. SDE_ERROR("capping number of displays to %d", max_encoders);
  1503. }
  1504. /* wb */
  1505. for (i = 0; i < sde_kms->wb_display_count &&
  1506. priv->num_encoders < max_encoders; ++i) {
  1507. display = sde_kms->wb_displays[i];
  1508. encoder = NULL;
  1509. memset(&info, 0x0, sizeof(info));
  1510. rc = sde_wb_get_info(NULL, &info, display);
  1511. if (rc) {
  1512. SDE_ERROR("wb get_info %d failed\n", i);
  1513. continue;
  1514. }
  1515. encoder = sde_encoder_init(dev, &info);
  1516. if (IS_ERR_OR_NULL(encoder)) {
  1517. SDE_ERROR("encoder init failed for wb %d\n", i);
  1518. continue;
  1519. }
  1520. rc = sde_wb_drm_init(display, encoder);
  1521. if (rc) {
  1522. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1523. sde_encoder_destroy(encoder);
  1524. continue;
  1525. }
  1526. connector = sde_connector_init(dev,
  1527. encoder,
  1528. 0,
  1529. display,
  1530. &wb_ops,
  1531. DRM_CONNECTOR_POLL_HPD,
  1532. DRM_MODE_CONNECTOR_VIRTUAL);
  1533. if (connector) {
  1534. priv->encoders[priv->num_encoders++] = encoder;
  1535. priv->connectors[priv->num_connectors++] = connector;
  1536. } else {
  1537. SDE_ERROR("wb %d connector init failed\n", i);
  1538. sde_wb_drm_deinit(display);
  1539. sde_encoder_destroy(encoder);
  1540. }
  1541. }
  1542. /* dsi */
  1543. for (i = 0; i < sde_kms->dsi_display_count &&
  1544. priv->num_encoders < max_encoders; ++i) {
  1545. display = sde_kms->dsi_displays[i];
  1546. encoder = NULL;
  1547. memset(&info, 0x0, sizeof(info));
  1548. rc = dsi_display_get_info(NULL, &info, display);
  1549. if (rc) {
  1550. SDE_ERROR("dsi get_info %d failed\n", i);
  1551. continue;
  1552. }
  1553. encoder = sde_encoder_init(dev, &info);
  1554. if (IS_ERR_OR_NULL(encoder)) {
  1555. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1556. continue;
  1557. }
  1558. rc = dsi_display_drm_bridge_init(display, encoder);
  1559. if (rc) {
  1560. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1561. sde_encoder_destroy(encoder);
  1562. continue;
  1563. }
  1564. connector = sde_connector_init(dev,
  1565. encoder,
  1566. dsi_display_get_drm_panel(display),
  1567. display,
  1568. &dsi_ops,
  1569. DRM_CONNECTOR_POLL_HPD,
  1570. DRM_MODE_CONNECTOR_DSI);
  1571. if (connector) {
  1572. priv->encoders[priv->num_encoders++] = encoder;
  1573. priv->connectors[priv->num_connectors++] = connector;
  1574. } else {
  1575. SDE_ERROR("dsi %d connector init failed\n", i);
  1576. dsi_display_drm_bridge_deinit(display);
  1577. sde_encoder_destroy(encoder);
  1578. continue;
  1579. }
  1580. rc = dsi_display_drm_ext_bridge_init(display,
  1581. encoder, connector);
  1582. if (rc) {
  1583. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1584. dsi_display_drm_bridge_deinit(display);
  1585. sde_connector_destroy(connector);
  1586. sde_encoder_destroy(encoder);
  1587. }
  1588. dsc_count += info.dsc_count;
  1589. mixer_count += info.lm_count;
  1590. }
  1591. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1592. sde_kms->catalog->mixer_count - mixer_count : 0;
  1593. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1594. sde_kms->catalog->dsc_count - dsc_count : 0;
  1595. /* dp */
  1596. for (i = 0; i < sde_kms->dp_display_count &&
  1597. priv->num_encoders < max_encoders; ++i) {
  1598. int idx;
  1599. display = sde_kms->dp_displays[i];
  1600. encoder = NULL;
  1601. memset(&info, 0x0, sizeof(info));
  1602. rc = dp_connector_get_info(NULL, &info, display);
  1603. if (rc) {
  1604. SDE_ERROR("dp get_info %d failed\n", i);
  1605. continue;
  1606. }
  1607. encoder = sde_encoder_init(dev, &info);
  1608. if (IS_ERR_OR_NULL(encoder)) {
  1609. SDE_ERROR("dp encoder init failed %d\n", i);
  1610. continue;
  1611. }
  1612. rc = dp_drm_bridge_init(display, encoder,
  1613. max_dp_mixer_count, max_dp_dsc_count);
  1614. if (rc) {
  1615. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1616. sde_encoder_destroy(encoder);
  1617. continue;
  1618. }
  1619. connector = sde_connector_init(dev,
  1620. encoder,
  1621. NULL,
  1622. display,
  1623. &dp_ops,
  1624. DRM_CONNECTOR_POLL_HPD,
  1625. DRM_MODE_CONNECTOR_DisplayPort);
  1626. if (connector) {
  1627. priv->encoders[priv->num_encoders++] = encoder;
  1628. priv->connectors[priv->num_connectors++] = connector;
  1629. } else {
  1630. SDE_ERROR("dp %d connector init failed\n", i);
  1631. dp_drm_bridge_deinit(display);
  1632. sde_encoder_destroy(encoder);
  1633. }
  1634. /* update display cap to MST_MODE for DP MST encoders */
  1635. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1636. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1637. priv->num_encoders < max_encoders; idx++) {
  1638. info.h_tile_instance[0] = idx;
  1639. encoder = sde_encoder_init(dev, &info);
  1640. if (IS_ERR_OR_NULL(encoder)) {
  1641. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1642. continue;
  1643. }
  1644. rc = dp_mst_drm_bridge_init(display, encoder);
  1645. if (rc) {
  1646. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1647. i, rc);
  1648. sde_encoder_destroy(encoder);
  1649. continue;
  1650. }
  1651. priv->encoders[priv->num_encoders++] = encoder;
  1652. }
  1653. }
  1654. return 0;
  1655. }
  1656. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1657. {
  1658. struct msm_drm_private *priv;
  1659. int i;
  1660. if (!sde_kms) {
  1661. SDE_ERROR("invalid sde_kms\n");
  1662. return;
  1663. } else if (!sde_kms->dev) {
  1664. SDE_ERROR("invalid dev\n");
  1665. return;
  1666. } else if (!sde_kms->dev->dev_private) {
  1667. SDE_ERROR("invalid dev_private\n");
  1668. return;
  1669. }
  1670. priv = sde_kms->dev->dev_private;
  1671. for (i = 0; i < priv->num_crtcs; i++)
  1672. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1673. priv->num_crtcs = 0;
  1674. for (i = 0; i < priv->num_planes; i++)
  1675. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1676. priv->num_planes = 0;
  1677. for (i = 0; i < priv->num_connectors; i++)
  1678. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1679. priv->num_connectors = 0;
  1680. for (i = 0; i < priv->num_encoders; i++)
  1681. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1682. priv->num_encoders = 0;
  1683. _sde_kms_release_displays(sde_kms);
  1684. }
  1685. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1686. {
  1687. struct drm_device *dev;
  1688. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1689. struct drm_crtc *crtc;
  1690. struct msm_drm_private *priv;
  1691. struct sde_mdss_cfg *catalog;
  1692. int primary_planes_idx = 0, i, ret;
  1693. int max_crtc_count;
  1694. u32 sspp_id[MAX_PLANES];
  1695. u32 master_plane_id[MAX_PLANES];
  1696. u32 num_virt_planes = 0;
  1697. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1698. SDE_ERROR("invalid sde_kms\n");
  1699. return -EINVAL;
  1700. }
  1701. dev = sde_kms->dev;
  1702. priv = dev->dev_private;
  1703. catalog = sde_kms->catalog;
  1704. ret = sde_core_irq_domain_add(sde_kms);
  1705. if (ret)
  1706. goto fail_irq;
  1707. /*
  1708. * Query for underlying display drivers, and create connectors,
  1709. * bridges and encoders for them.
  1710. */
  1711. if (!_sde_kms_get_displays(sde_kms))
  1712. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1713. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1714. /* Create the planes */
  1715. for (i = 0; i < catalog->sspp_count; i++) {
  1716. bool primary = true;
  1717. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1718. || primary_planes_idx >= max_crtc_count)
  1719. primary = false;
  1720. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1721. (1UL << max_crtc_count) - 1, 0);
  1722. if (IS_ERR(plane)) {
  1723. SDE_ERROR("sde_plane_init failed\n");
  1724. ret = PTR_ERR(plane);
  1725. goto fail;
  1726. }
  1727. priv->planes[priv->num_planes++] = plane;
  1728. if (primary)
  1729. primary_planes[primary_planes_idx++] = plane;
  1730. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1731. sde_is_custom_client()) {
  1732. int priority =
  1733. catalog->sspp[i].sblk->smart_dma_priority;
  1734. sspp_id[priority - 1] = catalog->sspp[i].id;
  1735. master_plane_id[priority - 1] = plane->base.id;
  1736. num_virt_planes++;
  1737. }
  1738. }
  1739. /* Initialize smart DMA virtual planes */
  1740. for (i = 0; i < num_virt_planes; i++) {
  1741. plane = sde_plane_init(dev, sspp_id[i], false,
  1742. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1743. if (IS_ERR(plane)) {
  1744. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1745. ret = PTR_ERR(plane);
  1746. goto fail;
  1747. }
  1748. priv->planes[priv->num_planes++] = plane;
  1749. }
  1750. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1751. /* Create one CRTC per encoder */
  1752. for (i = 0; i < max_crtc_count; i++) {
  1753. crtc = sde_crtc_init(dev, primary_planes[i]);
  1754. if (IS_ERR(crtc)) {
  1755. ret = PTR_ERR(crtc);
  1756. goto fail;
  1757. }
  1758. priv->crtcs[priv->num_crtcs++] = crtc;
  1759. }
  1760. if (sde_is_custom_client()) {
  1761. /* All CRTCs are compatible with all planes */
  1762. for (i = 0; i < priv->num_planes; i++)
  1763. priv->planes[i]->possible_crtcs =
  1764. (1 << priv->num_crtcs) - 1;
  1765. }
  1766. /* All CRTCs are compatible with all encoders */
  1767. for (i = 0; i < priv->num_encoders; i++)
  1768. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1769. return 0;
  1770. fail:
  1771. _sde_kms_drm_obj_destroy(sde_kms);
  1772. fail_irq:
  1773. sde_core_irq_domain_fini(sde_kms);
  1774. return ret;
  1775. }
  1776. /**
  1777. * sde_kms_timeline_status - provides current timeline status
  1778. * This API should be called without mode config lock.
  1779. * @dev: Pointer to drm device
  1780. */
  1781. void sde_kms_timeline_status(struct drm_device *dev)
  1782. {
  1783. struct drm_crtc *crtc;
  1784. struct drm_connector *conn;
  1785. struct drm_connector_list_iter conn_iter;
  1786. if (!dev) {
  1787. SDE_ERROR("invalid drm device node\n");
  1788. return;
  1789. }
  1790. drm_for_each_crtc(crtc, dev)
  1791. sde_crtc_timeline_status(crtc);
  1792. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1793. /*
  1794. *Probably locked from last close dumping status anyway
  1795. */
  1796. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1797. drm_connector_list_iter_begin(dev, &conn_iter);
  1798. drm_for_each_connector_iter(conn, &conn_iter)
  1799. sde_conn_timeline_status(conn);
  1800. drm_connector_list_iter_end(&conn_iter);
  1801. return;
  1802. }
  1803. mutex_lock(&dev->mode_config.mutex);
  1804. drm_connector_list_iter_begin(dev, &conn_iter);
  1805. drm_for_each_connector_iter(conn, &conn_iter)
  1806. sde_conn_timeline_status(conn);
  1807. drm_connector_list_iter_end(&conn_iter);
  1808. mutex_unlock(&dev->mode_config.mutex);
  1809. }
  1810. static int sde_kms_postinit(struct msm_kms *kms)
  1811. {
  1812. struct sde_kms *sde_kms = to_sde_kms(kms);
  1813. struct drm_device *dev;
  1814. struct drm_crtc *crtc;
  1815. int rc;
  1816. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1817. SDE_ERROR("invalid sde_kms\n");
  1818. return -EINVAL;
  1819. }
  1820. dev = sde_kms->dev;
  1821. rc = _sde_debugfs_init(sde_kms);
  1822. if (rc)
  1823. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1824. drm_for_each_crtc(crtc, dev)
  1825. sde_crtc_post_init(dev, crtc);
  1826. return rc;
  1827. }
  1828. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1829. struct drm_encoder *encoder)
  1830. {
  1831. return rate;
  1832. }
  1833. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1834. struct platform_device *pdev)
  1835. {
  1836. struct drm_device *dev;
  1837. struct msm_drm_private *priv;
  1838. struct sde_vm_ops *vm_ops;
  1839. int i;
  1840. if (!sde_kms || !pdev)
  1841. return;
  1842. dev = sde_kms->dev;
  1843. if (!dev)
  1844. return;
  1845. priv = dev->dev_private;
  1846. if (!priv)
  1847. return;
  1848. if (sde_kms->genpd_init) {
  1849. sde_kms->genpd_init = false;
  1850. pm_genpd_remove(&sde_kms->genpd);
  1851. of_genpd_del_provider(pdev->dev.of_node);
  1852. }
  1853. vm_ops = sde_vm_get_ops(sde_kms);
  1854. if (vm_ops && vm_ops->vm_deinit)
  1855. vm_ops->vm_deinit(sde_kms, vm_ops);
  1856. if (sde_kms->hw_intr)
  1857. sde_hw_intr_destroy(sde_kms->hw_intr);
  1858. sde_kms->hw_intr = NULL;
  1859. if (sde_kms->power_event)
  1860. sde_power_handle_unregister_event(
  1861. &priv->phandle, sde_kms->power_event);
  1862. _sde_kms_release_displays(sde_kms);
  1863. _sde_kms_unmap_all_splash_regions(sde_kms);
  1864. if (sde_kms->catalog) {
  1865. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1866. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1867. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1868. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1869. }
  1870. }
  1871. if (sde_kms->rm_init)
  1872. sde_rm_destroy(&sde_kms->rm);
  1873. sde_kms->rm_init = false;
  1874. if (sde_kms->catalog)
  1875. sde_hw_catalog_deinit(sde_kms->catalog);
  1876. sde_kms->catalog = NULL;
  1877. if (sde_kms->sid)
  1878. msm_iounmap(pdev, sde_kms->sid);
  1879. sde_kms->sid = NULL;
  1880. if (sde_kms->reg_dma)
  1881. msm_iounmap(pdev, sde_kms->reg_dma);
  1882. sde_kms->reg_dma = NULL;
  1883. if (sde_kms->vbif[VBIF_NRT])
  1884. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1885. sde_kms->vbif[VBIF_NRT] = NULL;
  1886. if (sde_kms->vbif[VBIF_RT])
  1887. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1888. sde_kms->vbif[VBIF_RT] = NULL;
  1889. if (sde_kms->mmio)
  1890. msm_iounmap(pdev, sde_kms->mmio);
  1891. sde_kms->mmio = NULL;
  1892. sde_reg_dma_deinit();
  1893. _sde_kms_mmu_destroy(sde_kms);
  1894. }
  1895. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1896. {
  1897. int i;
  1898. if (!sde_kms)
  1899. return -EINVAL;
  1900. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1901. struct msm_mmu *mmu;
  1902. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1903. if (!aspace)
  1904. continue;
  1905. mmu = sde_kms->aspace[i]->mmu;
  1906. if (secure_only &&
  1907. !aspace->mmu->funcs->is_domain_secure(mmu))
  1908. continue;
  1909. /* cleanup aspace before detaching */
  1910. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1911. SDE_DEBUG("Detaching domain:%d\n", i);
  1912. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1913. ARRAY_SIZE(iommu_ports));
  1914. aspace->domain_attached = false;
  1915. }
  1916. return 0;
  1917. }
  1918. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1919. {
  1920. int i;
  1921. if (!sde_kms)
  1922. return -EINVAL;
  1923. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1924. struct msm_mmu *mmu;
  1925. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1926. if (!aspace)
  1927. continue;
  1928. mmu = sde_kms->aspace[i]->mmu;
  1929. if (secure_only &&
  1930. !aspace->mmu->funcs->is_domain_secure(mmu))
  1931. continue;
  1932. SDE_DEBUG("Attaching domain:%d\n", i);
  1933. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1934. ARRAY_SIZE(iommu_ports));
  1935. aspace->domain_attached = true;
  1936. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1937. }
  1938. return 0;
  1939. }
  1940. static void sde_kms_destroy(struct msm_kms *kms)
  1941. {
  1942. struct sde_kms *sde_kms;
  1943. struct drm_device *dev;
  1944. if (!kms) {
  1945. SDE_ERROR("invalid kms\n");
  1946. return;
  1947. }
  1948. sde_kms = to_sde_kms(kms);
  1949. dev = sde_kms->dev;
  1950. if (!dev || !dev->dev) {
  1951. SDE_ERROR("invalid device\n");
  1952. return;
  1953. }
  1954. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1955. kfree(sde_kms);
  1956. }
  1957. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1958. struct drm_atomic_state *state)
  1959. {
  1960. struct drm_device *dev = sde_kms->dev;
  1961. struct drm_plane *plane;
  1962. struct drm_plane_state *plane_state;
  1963. struct drm_crtc *crtc;
  1964. struct drm_crtc_state *crtc_state;
  1965. struct drm_connector *conn;
  1966. struct drm_connector_state *conn_state;
  1967. struct drm_connector_list_iter conn_iter;
  1968. int ret = 0;
  1969. drm_for_each_plane(plane, dev) {
  1970. plane_state = drm_atomic_get_plane_state(state, plane);
  1971. if (IS_ERR(plane_state)) {
  1972. ret = PTR_ERR(plane_state);
  1973. SDE_ERROR("error %d getting plane %d state\n",
  1974. ret, DRMID(plane));
  1975. return ret;
  1976. }
  1977. ret = sde_plane_helper_reset_custom_properties(plane,
  1978. plane_state);
  1979. if (ret) {
  1980. SDE_ERROR("error %d resetting plane props %d\n",
  1981. ret, DRMID(plane));
  1982. return ret;
  1983. }
  1984. }
  1985. drm_for_each_crtc(crtc, dev) {
  1986. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1987. if (IS_ERR(crtc_state)) {
  1988. ret = PTR_ERR(crtc_state);
  1989. SDE_ERROR("error %d getting crtc %d state\n",
  1990. ret, DRMID(crtc));
  1991. return ret;
  1992. }
  1993. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1994. if (ret) {
  1995. SDE_ERROR("error %d resetting crtc props %d\n",
  1996. ret, DRMID(crtc));
  1997. return ret;
  1998. }
  1999. }
  2000. drm_connector_list_iter_begin(dev, &conn_iter);
  2001. drm_for_each_connector_iter(conn, &conn_iter) {
  2002. conn_state = drm_atomic_get_connector_state(state, conn);
  2003. if (IS_ERR(conn_state)) {
  2004. ret = PTR_ERR(conn_state);
  2005. SDE_ERROR("error %d getting connector %d state\n",
  2006. ret, DRMID(conn));
  2007. return ret;
  2008. }
  2009. ret = sde_connector_helper_reset_custom_properties(conn,
  2010. conn_state);
  2011. if (ret) {
  2012. SDE_ERROR("error %d resetting connector props %d\n",
  2013. ret, DRMID(conn));
  2014. return ret;
  2015. }
  2016. }
  2017. drm_connector_list_iter_end(&conn_iter);
  2018. return ret;
  2019. }
  2020. static void sde_kms_lastclose(struct msm_kms *kms)
  2021. {
  2022. struct sde_kms *sde_kms;
  2023. struct drm_device *dev;
  2024. struct drm_atomic_state *state;
  2025. struct drm_modeset_acquire_ctx ctx;
  2026. int ret;
  2027. if (!kms) {
  2028. SDE_ERROR("invalid argument\n");
  2029. return;
  2030. }
  2031. sde_kms = to_sde_kms(kms);
  2032. dev = sde_kms->dev;
  2033. drm_modeset_acquire_init(&ctx, 0);
  2034. state = drm_atomic_state_alloc(dev);
  2035. if (!state) {
  2036. ret = -ENOMEM;
  2037. goto out_ctx;
  2038. }
  2039. state->acquire_ctx = &ctx;
  2040. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  2041. retry:
  2042. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2043. if (ret)
  2044. goto out_state;
  2045. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2046. if (ret)
  2047. goto out_state;
  2048. ret = drm_atomic_commit(state);
  2049. out_state:
  2050. if (ret == -EDEADLK)
  2051. goto backoff;
  2052. drm_atomic_state_put(state);
  2053. out_ctx:
  2054. drm_modeset_drop_locks(&ctx);
  2055. drm_modeset_acquire_fini(&ctx);
  2056. if (ret)
  2057. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2058. SDE_EVT32(ret, SDE_EVTLOG_FUNC_EXIT);
  2059. return;
  2060. backoff:
  2061. drm_atomic_state_clear(state);
  2062. drm_modeset_backoff(&ctx);
  2063. SDE_EVT32(ret, SDE_EVTLOG_FUNC_CASE1);
  2064. goto retry;
  2065. }
  2066. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2067. struct drm_atomic_state *state)
  2068. {
  2069. struct sde_kms *sde_kms;
  2070. struct drm_device *dev;
  2071. struct drm_crtc *crtc;
  2072. struct drm_encoder *encoder;
  2073. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2074. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2075. uint32_t crtc_encoder_cnt = 0;
  2076. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2077. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2078. struct sde_vm_ops *vm_ops;
  2079. bool vm_req_active = false;
  2080. enum sde_crtc_idle_pc_state idle_pc_state;
  2081. struct sde_mdss_cfg *catalog;
  2082. int rc = 0;
  2083. struct sde_connector *sde_conn;
  2084. struct dsi_display *dsi_display;
  2085. struct drm_connector *connector;
  2086. struct drm_connector_state *new_connstate;
  2087. if (!kms || !state)
  2088. return -EINVAL;
  2089. sde_kms = to_sde_kms(kms);
  2090. dev = sde_kms->dev;
  2091. catalog = sde_kms->catalog;
  2092. vm_ops = sde_vm_get_ops(sde_kms);
  2093. if (!vm_ops)
  2094. return 0;
  2095. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw ||
  2096. !vm_ops->vm_acquire)
  2097. return -EINVAL;
  2098. sde_vm_lock(sde_kms);
  2099. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2100. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2101. if (!new_cstate->active && !old_cstate->active)
  2102. continue;
  2103. new_state = to_sde_crtc_state(new_cstate);
  2104. new_vm_req = sde_crtc_get_property(new_state,
  2105. CRTC_PROP_VM_REQ_STATE);
  2106. old_state = to_sde_crtc_state(old_cstate);
  2107. old_vm_req = sde_crtc_get_property(old_state,
  2108. CRTC_PROP_VM_REQ_STATE);
  2109. /*
  2110. * No active request if the transition is from
  2111. * VM_REQ_NONE to VM_REQ_NONE
  2112. */
  2113. if (old_vm_req || new_vm_req) {
  2114. rc = vm_ops->vm_request_valid(sde_kms,
  2115. old_vm_req, new_vm_req);
  2116. if (rc) {
  2117. SDE_ERROR(
  2118. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2119. old_vm_req, new_vm_req,
  2120. vm_ops->vm_owns_hw(sde_kms), rc);
  2121. goto end;
  2122. } else if (old_vm_req == VM_REQ_ACQUIRE &&
  2123. new_vm_req == VM_REQ_NONE) {
  2124. SDE_DEBUG(
  2125. "VM transition valid; ignore further checks\n");
  2126. } else {
  2127. vm_req_active = true;
  2128. }
  2129. }
  2130. idle_pc_state = sde_crtc_get_property(new_state,
  2131. CRTC_PROP_IDLE_PC_STATE);
  2132. active_crtc = crtc;
  2133. active_cstate = new_cstate;
  2134. commit_crtc_cnt++;
  2135. }
  2136. /* return early if no active vm request */
  2137. if (!vm_req_active)
  2138. goto end;
  2139. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2140. if (!crtc->state->active)
  2141. continue;
  2142. global_crtc_cnt++;
  2143. global_active_crtc = crtc;
  2144. }
  2145. if (active_crtc) {
  2146. drm_for_each_encoder_mask(encoder, active_crtc->dev,
  2147. active_cstate->encoder_mask)
  2148. crtc_encoder_cnt++;
  2149. }
  2150. SDE_EVT32(old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2151. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d\n", old_vm_req,
  2152. new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2153. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2154. int conn_mask = active_cstate->connector_mask;
  2155. if (drm_connector_mask(connector) & conn_mask) {
  2156. sde_conn = to_sde_connector(connector);
  2157. dsi_display = (struct dsi_display *) sde_conn->display;
  2158. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i,
  2159. dsi_display->type,
  2160. dsi_display->trusted_vm_env);
  2161. SDE_DEBUG(
  2162. "VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d,",
  2163. dsi_display->name, DRMID(connector),
  2164. DRMID(active_crtc), dsi_display->type,
  2165. dsi_display->trusted_vm_env);
  2166. break;
  2167. }
  2168. }
  2169. /* Check for single crtc commits only on valid VM requests */
  2170. if (active_crtc && global_active_crtc &&
  2171. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2172. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2173. active_crtc != global_active_crtc)) {
  2174. SDE_ERROR(
  2175. "VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2176. catalog->max_trusted_vm_displays,
  2177. commit_crtc_cnt, global_crtc_cnt, DRMID(active_crtc),
  2178. DRMID(global_active_crtc));
  2179. rc = -E2BIG;
  2180. goto end;
  2181. } else if ((new_vm_req == VM_REQ_RELEASE) &&
  2182. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2183. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2184. /*
  2185. * disable idle-pc before releasing the HW
  2186. * allow only specified number of encoders on a given crtc
  2187. */
  2188. SDE_ERROR(
  2189. "VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2190. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC,
  2191. crtc_encoder_cnt);
  2192. rc = -EINVAL;
  2193. goto end;
  2194. }
  2195. if ((new_vm_req == VM_REQ_ACQUIRE) && !vm_ops->vm_owns_hw(sde_kms)) {
  2196. rc = vm_ops->vm_acquire(sde_kms);
  2197. if (rc) {
  2198. SDE_ERROR(
  2199. "VM acquire failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2200. old_vm_req, new_vm_req,
  2201. vm_ops->vm_owns_hw(sde_kms), rc);
  2202. goto end;
  2203. }
  2204. if (vm_ops->vm_resource_init)
  2205. rc = vm_ops->vm_resource_init(sde_kms, state);
  2206. }
  2207. end:
  2208. sde_vm_unlock(sde_kms);
  2209. return rc;
  2210. }
  2211. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2212. struct drm_atomic_state *state)
  2213. {
  2214. struct sde_kms *sde_kms;
  2215. struct drm_device *dev;
  2216. struct drm_crtc *crtc;
  2217. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2218. struct drm_crtc_state *crtc_state;
  2219. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2220. bool sec_session = false, global_sec_session = false;
  2221. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2222. int i;
  2223. if (!kms || !state) {
  2224. return -EINVAL;
  2225. SDE_ERROR("invalid arguments\n");
  2226. }
  2227. sde_kms = to_sde_kms(kms);
  2228. dev = sde_kms->dev;
  2229. /* iterate state object for active secure/non-secure crtc */
  2230. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2231. if (!crtc_state->active)
  2232. continue;
  2233. active_crtc_cnt++;
  2234. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2235. &fb_sec, &fb_sec_dir);
  2236. if (fb_sec_dir)
  2237. sec_session = true;
  2238. cur_crtc = crtc;
  2239. }
  2240. /* iterate global list for active and secure/non-secure crtc */
  2241. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2242. if (!crtc->state->active)
  2243. continue;
  2244. global_active_crtc_cnt++;
  2245. /* update only when crtc is not the same as current crtc */
  2246. if (crtc != cur_crtc) {
  2247. fb_ns = fb_sec = fb_sec_dir = 0;
  2248. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2249. &fb_sec, &fb_sec_dir);
  2250. if (fb_sec_dir)
  2251. global_sec_session = true;
  2252. global_crtc = crtc;
  2253. }
  2254. }
  2255. if (!global_sec_session && !sec_session)
  2256. return 0;
  2257. /*
  2258. * - fail crtc commit, if secure-camera/secure-ui session is
  2259. * in-progress in any other display
  2260. * - fail secure-camera/secure-ui crtc commit, if any other display
  2261. * session is in-progress
  2262. */
  2263. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2264. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2265. SDE_ERROR(
  2266. "crtc%d secure check failed global_active:%d active:%d\n",
  2267. cur_crtc ? cur_crtc->base.id : -1,
  2268. global_active_crtc_cnt, active_crtc_cnt);
  2269. return -EPERM;
  2270. /*
  2271. * As only one crtc is allowed during secure session, the crtc
  2272. * in this commit should match with the global crtc
  2273. */
  2274. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2275. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2276. cur_crtc->base.id, sec_session,
  2277. global_crtc->base.id, global_sec_session);
  2278. return -EPERM;
  2279. }
  2280. return 0;
  2281. }
  2282. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2283. struct drm_atomic_state *state)
  2284. {
  2285. struct drm_crtc *crtc;
  2286. struct drm_crtc_state *new_cstate;
  2287. struct sde_crtc_state *cstate;
  2288. struct sde_vm_ops *vm_ops;
  2289. enum sde_crtc_vm_req vm_req;
  2290. struct sde_kms *sde_kms = to_sde_kms(kms);
  2291. vm_ops = sde_vm_get_ops(sde_kms);
  2292. if (!vm_ops)
  2293. return;
  2294. crtc = sde_kms_vm_get_vm_crtc(state);
  2295. if (!crtc)
  2296. return;
  2297. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  2298. cstate = to_sde_crtc_state(new_cstate);
  2299. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2300. if (vm_req != VM_REQ_ACQUIRE)
  2301. return;
  2302. sde_vm_lock(sde_kms);
  2303. if (vm_ops->vm_acquire_fail_handler)
  2304. vm_ops->vm_acquire_fail_handler(sde_kms);
  2305. sde_vm_unlock(sde_kms);
  2306. }
  2307. static int sde_kms_atomic_check(struct msm_kms *kms,
  2308. struct drm_atomic_state *state)
  2309. {
  2310. struct sde_kms *sde_kms;
  2311. struct drm_device *dev;
  2312. int ret;
  2313. if (!kms || !state)
  2314. return -EINVAL;
  2315. sde_kms = to_sde_kms(kms);
  2316. dev = sde_kms->dev;
  2317. SDE_ATRACE_BEGIN("atomic_check");
  2318. if (sde_kms_is_suspend_blocked(dev)) {
  2319. SDE_DEBUG("suspended, skip atomic_check\n");
  2320. ret = -EBUSY;
  2321. goto end;
  2322. }
  2323. ret = sde_kms_check_vm_request(kms, state);
  2324. if (ret) {
  2325. SDE_ERROR("vm switch request checks failed\n");
  2326. goto end;
  2327. }
  2328. ret = drm_atomic_helper_check(dev, state);
  2329. if (ret)
  2330. goto vm_clean_up;
  2331. /*
  2332. * Check if any secure transition(moving CRTC between secure and
  2333. * non-secure state and vice-versa) is allowed or not. when moving
  2334. * to secure state, planes with fb_mode set to dir_translated only can
  2335. * be staged on the CRTC, and only one CRTC can be active during
  2336. * Secure state
  2337. */
  2338. ret = sde_kms_check_secure_transition(kms, state);
  2339. if (ret)
  2340. goto vm_clean_up;
  2341. goto end;
  2342. vm_clean_up:
  2343. sde_kms_vm_res_release(kms, state);
  2344. end:
  2345. SDE_ATRACE_END("atomic_check");
  2346. return ret;
  2347. }
  2348. static struct msm_gem_address_space*
  2349. _sde_kms_get_address_space(struct msm_kms *kms,
  2350. unsigned int domain)
  2351. {
  2352. struct sde_kms *sde_kms;
  2353. if (!kms) {
  2354. SDE_ERROR("invalid kms\n");
  2355. return NULL;
  2356. }
  2357. sde_kms = to_sde_kms(kms);
  2358. if (!sde_kms) {
  2359. SDE_ERROR("invalid sde_kms\n");
  2360. return NULL;
  2361. }
  2362. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2363. return NULL;
  2364. return (sde_kms->aspace[domain] &&
  2365. sde_kms->aspace[domain]->domain_attached) ?
  2366. sde_kms->aspace[domain] : NULL;
  2367. }
  2368. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2369. unsigned int domain)
  2370. {
  2371. struct sde_kms *sde_kms;
  2372. struct msm_gem_address_space *aspace;
  2373. if (!kms) {
  2374. SDE_ERROR("invalid kms\n");
  2375. return NULL;
  2376. }
  2377. sde_kms = to_sde_kms(kms);
  2378. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2379. SDE_ERROR("invalid params\n");
  2380. return NULL;
  2381. }
  2382. aspace = _sde_kms_get_address_space(kms, domain);
  2383. return (aspace && aspace->domain_attached) ?
  2384. msm_gem_get_aspace_device(aspace) : NULL;
  2385. }
  2386. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2387. {
  2388. struct drm_device *dev = NULL;
  2389. struct sde_kms *sde_kms = NULL;
  2390. struct drm_connector *connector = NULL;
  2391. struct drm_connector_list_iter conn_iter;
  2392. struct sde_connector *sde_conn = NULL;
  2393. if (!kms) {
  2394. SDE_ERROR("invalid kms\n");
  2395. return;
  2396. }
  2397. sde_kms = to_sde_kms(kms);
  2398. dev = sde_kms->dev;
  2399. if (!dev) {
  2400. SDE_ERROR("invalid device\n");
  2401. return;
  2402. }
  2403. if (!dev->mode_config.poll_enabled)
  2404. return;
  2405. mutex_lock(&dev->mode_config.mutex);
  2406. drm_connector_list_iter_begin(dev, &conn_iter);
  2407. drm_for_each_connector_iter(connector, &conn_iter) {
  2408. /* Only handle HPD capable connectors. */
  2409. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2410. continue;
  2411. sde_conn = to_sde_connector(connector);
  2412. if (sde_conn->ops.post_open)
  2413. sde_conn->ops.post_open(&sde_conn->base,
  2414. sde_conn->display);
  2415. }
  2416. drm_connector_list_iter_end(&conn_iter);
  2417. mutex_unlock(&dev->mode_config.mutex);
  2418. }
  2419. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2420. struct sde_splash_display *splash_display,
  2421. struct drm_crtc *crtc)
  2422. {
  2423. struct msm_drm_private *priv;
  2424. struct drm_plane *plane;
  2425. struct sde_splash_mem *splash;
  2426. struct sde_splash_mem *demura;
  2427. struct sde_plane_state *pstate;
  2428. enum sde_sspp plane_id;
  2429. bool is_virtual;
  2430. int i, j;
  2431. if (!sde_kms || !splash_display || !crtc) {
  2432. SDE_ERROR("invalid input args\n");
  2433. return -EINVAL;
  2434. }
  2435. priv = sde_kms->dev->dev_private;
  2436. for (i = 0; i < priv->num_planes; i++) {
  2437. plane = priv->planes[i];
  2438. plane_id = sde_plane_pipe(plane);
  2439. is_virtual = is_sde_plane_virtual(plane);
  2440. splash = splash_display->splash;
  2441. demura = splash_display->demura;
  2442. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2443. if ((plane_id != splash_display->pipes[j].sspp) ||
  2444. (splash_display->pipes[j].is_virtual
  2445. != is_virtual))
  2446. continue;
  2447. if (splash && sde_plane_validate_src_addr(plane,
  2448. splash->splash_buf_base,
  2449. splash->splash_buf_size)) {
  2450. if (!demura || sde_plane_validate_src_addr(
  2451. plane, demura->splash_buf_base,
  2452. demura->splash_buf_size)) {
  2453. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2454. plane_id, DRMID(crtc));
  2455. }
  2456. }
  2457. plane->state->crtc = crtc;
  2458. crtc->state->plane_mask |= drm_plane_mask(plane);
  2459. pstate = to_sde_plane_state(plane->state);
  2460. pstate->cont_splash_populated = true;
  2461. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2462. DRMID(crtc), plane_id, is_virtual);
  2463. }
  2464. }
  2465. return 0;
  2466. }
  2467. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2468. struct dsi_display *dsi_display)
  2469. {
  2470. void *display;
  2471. struct drm_encoder *encoder = NULL;
  2472. struct msm_display_info info;
  2473. struct drm_device *dev;
  2474. struct sde_kms *sde_kms;
  2475. struct drm_connector_list_iter conn_iter;
  2476. struct drm_connector *connector = NULL;
  2477. struct sde_connector *sde_conn = NULL;
  2478. int rc = 0;
  2479. sde_kms = to_sde_kms(kms);
  2480. dev = sde_kms->dev;
  2481. display = dsi_display;
  2482. if (dsi_display) {
  2483. if (dsi_display->bridge->base.encoder) {
  2484. encoder = dsi_display->bridge->base.encoder;
  2485. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2486. }
  2487. memset(&info, 0x0, sizeof(info));
  2488. rc = dsi_display_get_info(NULL, &info, display);
  2489. if (rc) {
  2490. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2491. __func__, rc);
  2492. encoder = NULL;
  2493. }
  2494. }
  2495. drm_connector_list_iter_begin(dev, &conn_iter);
  2496. drm_for_each_connector_iter(connector, &conn_iter) {
  2497. struct drm_encoder *c_encoder;
  2498. drm_connector_for_each_possible_encoder(connector,
  2499. c_encoder)
  2500. break;
  2501. if (!c_encoder) {
  2502. SDE_ERROR("c_encoder not found\n");
  2503. return -EINVAL;
  2504. }
  2505. /**
  2506. * Inform cont_splash is disabled to each interface/connector.
  2507. * This is currently supported for DSI interface.
  2508. */
  2509. sde_conn = to_sde_connector(connector);
  2510. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2511. if (!dsi_display || !encoder) {
  2512. sde_conn->ops.cont_splash_res_disable
  2513. (sde_conn->display);
  2514. } else if (c_encoder->base.id == encoder->base.id) {
  2515. /**
  2516. * This handles dual DSI
  2517. * configuration where one DSI
  2518. * interface has cont_splash
  2519. * enabled and the other doesn't.
  2520. */
  2521. sde_conn->ops.cont_splash_res_disable
  2522. (sde_conn->display);
  2523. break;
  2524. }
  2525. }
  2526. }
  2527. drm_connector_list_iter_end(&conn_iter);
  2528. return 0;
  2529. }
  2530. static int sde_kms_vm_trusted_cont_splash_res_init(struct sde_kms *sde_kms)
  2531. {
  2532. int i;
  2533. void *display;
  2534. struct dsi_display *dsi_display;
  2535. struct drm_encoder *encoder;
  2536. if (!sde_kms)
  2537. return -EINVAL;
  2538. if (!sde_in_trusted_vm(sde_kms))
  2539. return 0;
  2540. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  2541. display = sde_kms->dsi_displays[i];
  2542. dsi_display = (struct dsi_display *)display;
  2543. if (!dsi_display->bridge->base.encoder) {
  2544. SDE_ERROR("no encoder on dsi display:%d", i);
  2545. return -EINVAL;
  2546. }
  2547. encoder = dsi_display->bridge->base.encoder;
  2548. encoder->possible_crtcs = 1 << i;
  2549. SDE_DEBUG(
  2550. "dsi-display:%d encoder id[%d]=%d name=%s crtcs=%x\n", i,
  2551. encoder->index, encoder->base.id,
  2552. encoder->name, encoder->possible_crtcs);
  2553. }
  2554. return 0;
  2555. }
  2556. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2557. struct sde_kms *sde_kms, struct drm_connector *connector,
  2558. struct drm_atomic_state *state)
  2559. {
  2560. struct drm_display_mode *mode, *cur_mode = NULL;
  2561. struct drm_crtc *crtc;
  2562. struct drm_crtc_state *new_cstate, *old_cstate;
  2563. u32 i = 0;
  2564. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2565. list_for_each_entry(mode, &connector->modes, head) {
  2566. if (mode->type & DRM_MODE_TYPE_PREFERRED) {
  2567. cur_mode = mode;
  2568. break;
  2569. }
  2570. }
  2571. } else if (state) {
  2572. /* get the mode from first atomic_check phase for trusted_vm*/
  2573. for_each_oldnew_crtc_in_state(state, crtc, old_cstate,
  2574. new_cstate, i) {
  2575. if (!new_cstate->active && !old_cstate->active)
  2576. continue;
  2577. list_for_each_entry(mode, &connector->modes, head) {
  2578. if (drm_mode_equal(&new_cstate->mode, mode)) {
  2579. cur_mode = mode;
  2580. break;
  2581. }
  2582. }
  2583. }
  2584. }
  2585. return cur_mode;
  2586. }
  2587. static int sde_kms_cont_splash_config(struct msm_kms *kms,
  2588. struct drm_atomic_state *state)
  2589. {
  2590. void *display;
  2591. struct dsi_display *dsi_display;
  2592. struct msm_display_info info;
  2593. struct drm_encoder *encoder = NULL;
  2594. struct drm_crtc *crtc = NULL;
  2595. int i, rc = 0;
  2596. struct drm_display_mode *drm_mode = NULL;
  2597. struct drm_device *dev;
  2598. struct msm_drm_private *priv;
  2599. struct sde_kms *sde_kms;
  2600. struct drm_connector_list_iter conn_iter;
  2601. struct drm_connector *connector = NULL;
  2602. struct sde_connector *sde_conn = NULL;
  2603. struct sde_splash_display *splash_display;
  2604. if (!kms) {
  2605. SDE_ERROR("invalid kms\n");
  2606. return -EINVAL;
  2607. }
  2608. sde_kms = to_sde_kms(kms);
  2609. dev = sde_kms->dev;
  2610. if (!dev) {
  2611. SDE_ERROR("invalid device\n");
  2612. return -EINVAL;
  2613. }
  2614. rc = sde_kms_vm_trusted_cont_splash_res_init(sde_kms);
  2615. if (rc) {
  2616. SDE_ERROR("failed vm cont splash resource init, rc=%d", rc);
  2617. return -EINVAL;
  2618. }
  2619. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2620. && (!sde_kms->splash_data.num_splash_regions)) ||
  2621. !sde_kms->splash_data.num_splash_displays) {
  2622. DRM_INFO("cont_splash feature not enabled\n");
  2623. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2624. return rc;
  2625. }
  2626. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2627. sde_kms->splash_data.num_splash_displays,
  2628. sde_kms->dsi_display_count);
  2629. /* dsi */
  2630. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2631. struct sde_crtc_state *cstate;
  2632. struct sde_connector_state *conn_state;
  2633. display = sde_kms->dsi_displays[i];
  2634. dsi_display = (struct dsi_display *)display;
  2635. splash_display = &sde_kms->splash_data.splash_display[i];
  2636. if (!splash_display->cont_splash_enabled) {
  2637. SDE_DEBUG("display->name = %s splash not enabled\n",
  2638. dsi_display->name);
  2639. sde_kms_inform_cont_splash_res_disable(kms,
  2640. dsi_display);
  2641. continue;
  2642. }
  2643. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2644. if (dsi_display->bridge->base.encoder) {
  2645. encoder = dsi_display->bridge->base.encoder;
  2646. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2647. }
  2648. memset(&info, 0x0, sizeof(info));
  2649. rc = dsi_display_get_info(NULL, &info, display);
  2650. if (rc) {
  2651. SDE_ERROR("dsi get_info %d failed\n", i);
  2652. encoder = NULL;
  2653. continue;
  2654. }
  2655. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2656. ((info.is_connected) ? "true" : "false"),
  2657. info.display_type);
  2658. if (!encoder) {
  2659. SDE_ERROR("encoder not initialized\n");
  2660. return -EINVAL;
  2661. }
  2662. priv = sde_kms->dev->dev_private;
  2663. encoder->crtc = priv->crtcs[i];
  2664. crtc = encoder->crtc;
  2665. splash_display->encoder = encoder;
  2666. SDE_DEBUG("for dsi-display:%d crtc id[%d]:%d enc id[%d]:%d\n",
  2667. i, crtc->index, crtc->base.id, encoder->index,
  2668. encoder->base.id);
  2669. mutex_lock(&dev->mode_config.mutex);
  2670. drm_connector_list_iter_begin(dev, &conn_iter);
  2671. drm_for_each_connector_iter(connector, &conn_iter) {
  2672. struct drm_encoder *c_encoder;
  2673. drm_connector_for_each_possible_encoder(connector,
  2674. c_encoder)
  2675. break;
  2676. if (!c_encoder) {
  2677. SDE_ERROR("c_encoder not found\n");
  2678. mutex_unlock(&dev->mode_config.mutex);
  2679. return -EINVAL;
  2680. }
  2681. /**
  2682. * SDE_KMS doesn't attach more than one encoder to
  2683. * a DSI connector. So it is safe to check only with
  2684. * the first encoder entry. Revisit this logic if we
  2685. * ever have to support continuous splash for
  2686. * external displays in MST configuration.
  2687. */
  2688. if (c_encoder->base.id == encoder->base.id)
  2689. break;
  2690. }
  2691. drm_connector_list_iter_end(&conn_iter);
  2692. if (!connector) {
  2693. SDE_ERROR("connector not initialized\n");
  2694. mutex_unlock(&dev->mode_config.mutex);
  2695. return -EINVAL;
  2696. }
  2697. mutex_unlock(&dev->mode_config.mutex);
  2698. crtc->state->encoder_mask = drm_encoder_mask(encoder);
  2699. crtc->state->connector_mask = drm_connector_mask(connector);
  2700. connector->state->crtc = crtc;
  2701. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state);
  2702. if (!drm_mode) {
  2703. SDE_ERROR("drm_mode not found; handoff_type:%d\n",
  2704. sde_kms->splash_data.type);
  2705. return -EINVAL;
  2706. }
  2707. SDE_DEBUG(
  2708. "drm_mode->name:%s, type:0x%x, flags:0x%x, handoff_type:%d\n",
  2709. drm_mode->name, drm_mode->type,
  2710. drm_mode->flags, sde_kms->splash_data.type);
  2711. /* Update CRTC drm structure */
  2712. crtc->state->active = true;
  2713. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2714. if (rc) {
  2715. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2716. return rc;
  2717. }
  2718. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2719. drm_mode_copy(&crtc->mode, drm_mode);
  2720. cstate = to_sde_crtc_state(crtc->state);
  2721. cstate->cont_splash_populated = true;
  2722. /* Update encoder structure */
  2723. sde_encoder_update_caps_for_cont_splash(encoder,
  2724. splash_display, true);
  2725. sde_crtc_update_cont_splash_settings(crtc);
  2726. sde_conn = to_sde_connector(connector);
  2727. if (sde_conn && sde_conn->ops.cont_splash_config)
  2728. sde_conn->ops.cont_splash_config(sde_conn->display);
  2729. conn_state = to_sde_connector_state(connector->state);
  2730. conn_state->cont_splash_populated = true;
  2731. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2732. splash_display, crtc);
  2733. if (rc) {
  2734. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2735. return rc;
  2736. }
  2737. }
  2738. return rc;
  2739. }
  2740. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2741. {
  2742. struct sde_kms *sde_kms;
  2743. if (!kms) {
  2744. SDE_ERROR("invalid kms\n");
  2745. return false;
  2746. }
  2747. sde_kms = to_sde_kms(kms);
  2748. return sde_kms->splash_data.num_splash_displays;
  2749. }
  2750. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2751. const struct drm_display_mode *mode,
  2752. const struct msm_resource_caps_info *res, u32 *num_lm)
  2753. {
  2754. struct sde_kms *sde_kms;
  2755. s64 mode_clock_hz = 0;
  2756. s64 max_mdp_clock_hz = 0;
  2757. s64 max_lm_width = 0;
  2758. s64 hdisplay_fp = 0;
  2759. s64 htotal_fp = 0;
  2760. s64 vtotal_fp = 0;
  2761. s64 vrefresh_fp = 0;
  2762. s64 mdp_fudge_factor = 0;
  2763. s64 num_lm_fp = 0;
  2764. s64 lm_clk_fp = 0;
  2765. s64 lm_width_fp = 0;
  2766. int rc = 0;
  2767. if (!num_lm) {
  2768. SDE_ERROR("invalid num_lm pointer\n");
  2769. return -EINVAL;
  2770. }
  2771. /* default to 1 layer mixer */
  2772. *num_lm = 1;
  2773. if (!kms || !mode || !res) {
  2774. SDE_ERROR("invalid input args\n");
  2775. return -EINVAL;
  2776. }
  2777. sde_kms = to_sde_kms(kms);
  2778. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2779. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2780. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2781. htotal_fp = drm_int2fixp(mode->htotal);
  2782. vtotal_fp = drm_int2fixp(mode->vtotal);
  2783. vrefresh_fp = drm_int2fixp(drm_mode_vrefresh(mode));
  2784. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2785. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2786. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2787. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2788. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2789. if (mode_clock_hz > max_mdp_clock_hz ||
  2790. hdisplay_fp > max_lm_width) {
  2791. *num_lm = 0;
  2792. do {
  2793. *num_lm += 2;
  2794. num_lm_fp = drm_int2fixp(*num_lm);
  2795. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2796. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2797. if (*num_lm > 4) {
  2798. rc = -EINVAL;
  2799. goto error;
  2800. }
  2801. } while (lm_clk_fp > max_mdp_clock_hz ||
  2802. lm_width_fp > max_lm_width);
  2803. mode_clock_hz = lm_clk_fp;
  2804. }
  2805. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u max_clk=%llu\n",
  2806. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  2807. *num_lm, drm_fixp2int(mode_clock_hz),
  2808. sde_kms->perf.max_core_clk_rate);
  2809. return 0;
  2810. error:
  2811. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2812. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u max_clk=%llu\n",
  2813. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  2814. *num_lm, drm_fixp2int(mode_clock_hz),
  2815. sde_kms->perf.max_core_clk_rate);
  2816. return rc;
  2817. }
  2818. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2819. u32 hdisplay, u32 *num_dsc)
  2820. {
  2821. struct sde_kms *sde_kms;
  2822. uint32_t max_dsc_width;
  2823. if (!num_dsc) {
  2824. SDE_ERROR("invalid num_dsc pointer\n");
  2825. return -EINVAL;
  2826. }
  2827. *num_dsc = 0;
  2828. if (!kms || !hdisplay) {
  2829. SDE_ERROR("invalid input args\n");
  2830. return -EINVAL;
  2831. }
  2832. sde_kms = to_sde_kms(kms);
  2833. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2834. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2835. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2836. hdisplay, max_dsc_width,
  2837. *num_dsc);
  2838. return 0;
  2839. }
  2840. static void _sde_kms_null_commit(struct drm_device *dev,
  2841. struct drm_encoder *enc)
  2842. {
  2843. struct drm_modeset_acquire_ctx ctx;
  2844. struct drm_connector *conn = NULL;
  2845. struct drm_connector *tmp_conn = NULL;
  2846. struct drm_connector_list_iter conn_iter;
  2847. struct drm_atomic_state *state = NULL;
  2848. struct drm_crtc_state *crtc_state = NULL;
  2849. struct drm_connector_state *conn_state = NULL;
  2850. int retry_cnt = 0;
  2851. int ret = 0;
  2852. drm_modeset_acquire_init(&ctx, 0);
  2853. retry:
  2854. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2855. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2856. drm_modeset_backoff(&ctx);
  2857. retry_cnt++;
  2858. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2859. goto retry;
  2860. } else if (WARN_ON(ret)) {
  2861. goto end;
  2862. }
  2863. state = drm_atomic_state_alloc(dev);
  2864. if (!state) {
  2865. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2866. goto end;
  2867. }
  2868. state->acquire_ctx = &ctx;
  2869. drm_connector_list_iter_begin(dev, &conn_iter);
  2870. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2871. if (enc == tmp_conn->state->best_encoder) {
  2872. conn = tmp_conn;
  2873. break;
  2874. }
  2875. }
  2876. drm_connector_list_iter_end(&conn_iter);
  2877. if (!conn) {
  2878. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2879. goto end;
  2880. }
  2881. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2882. conn_state = drm_atomic_get_connector_state(state, conn);
  2883. if (IS_ERR(conn_state)) {
  2884. SDE_ERROR("error %d getting connector %d state\n",
  2885. ret, DRMID(conn));
  2886. goto end;
  2887. }
  2888. crtc_state->active = true;
  2889. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2890. if (ret)
  2891. SDE_ERROR("error %d setting the crtc\n", ret);
  2892. ret = drm_atomic_commit(state);
  2893. if (ret)
  2894. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2895. end:
  2896. if (state)
  2897. drm_atomic_state_put(state);
  2898. drm_modeset_drop_locks(&ctx);
  2899. drm_modeset_acquire_fini(&ctx);
  2900. }
  2901. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2902. const int32_t connector_id)
  2903. {
  2904. struct drm_connector_list_iter conn_iter;
  2905. struct drm_connector *conn;
  2906. struct drm_encoder *drm_enc;
  2907. drm_connector_list_iter_begin(dev, &conn_iter);
  2908. drm_for_each_connector_iter(conn, &conn_iter) {
  2909. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2910. connector_id != conn->base.id)
  2911. continue;
  2912. if (conn->state && conn->state->best_encoder)
  2913. drm_enc = conn->state->best_encoder;
  2914. else
  2915. drm_enc = conn->encoder;
  2916. if (drm_enc)
  2917. sde_encoder_early_wakeup(drm_enc);
  2918. }
  2919. drm_connector_list_iter_end(&conn_iter);
  2920. }
  2921. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2922. struct device *dev)
  2923. {
  2924. int i, ret, crtc_id = 0;
  2925. struct drm_device *ddev = dev_get_drvdata(dev);
  2926. struct drm_connector *conn;
  2927. struct drm_connector_list_iter conn_iter;
  2928. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2929. drm_connector_list_iter_begin(ddev, &conn_iter);
  2930. drm_for_each_connector_iter(conn, &conn_iter) {
  2931. uint64_t lp;
  2932. lp = sde_connector_get_lp(conn);
  2933. if (lp != SDE_MODE_DPMS_LP2)
  2934. continue;
  2935. if (sde_encoder_in_clone_mode(conn->encoder))
  2936. continue;
  2937. ret = sde_encoder_wait_for_event(conn->encoder,
  2938. MSM_ENC_TX_COMPLETE);
  2939. if (ret && ret != -EWOULDBLOCK) {
  2940. SDE_ERROR(
  2941. "[conn: %d] wait for commit done returned %d\n",
  2942. conn->base.id, ret);
  2943. } else if (!ret) {
  2944. crtc_id = drm_crtc_index(conn->state->crtc);
  2945. if (priv->event_thread[crtc_id].thread)
  2946. kthread_flush_worker(
  2947. &priv->event_thread[crtc_id].worker);
  2948. sde_encoder_idle_request(conn->encoder);
  2949. }
  2950. }
  2951. drm_connector_list_iter_end(&conn_iter);
  2952. for (i = 0; i < priv->num_crtcs; i++) {
  2953. if (priv->disp_thread[i].thread)
  2954. kthread_flush_worker(
  2955. &priv->disp_thread[i].worker);
  2956. if (priv->event_thread[i].thread)
  2957. kthread_flush_worker(
  2958. &priv->event_thread[i].worker);
  2959. }
  2960. kthread_flush_worker(&priv->pp_event_worker);
  2961. }
  2962. struct msm_display_mode *sde_kms_get_msm_mode(struct drm_crtc_state *c_state)
  2963. {
  2964. return sde_crtc_get_msm_mode(c_state);
  2965. }
  2966. static int sde_kms_pm_suspend(struct device *dev)
  2967. {
  2968. struct drm_device *ddev;
  2969. struct drm_modeset_acquire_ctx ctx;
  2970. struct drm_connector *conn;
  2971. struct drm_encoder *enc;
  2972. struct drm_connector_list_iter conn_iter;
  2973. struct drm_atomic_state *state = NULL;
  2974. struct sde_kms *sde_kms;
  2975. int ret = 0, num_crtcs = 0;
  2976. if (!dev)
  2977. return -EINVAL;
  2978. ddev = dev_get_drvdata(dev);
  2979. if (!ddev || !ddev_to_msm_kms(ddev))
  2980. return -EINVAL;
  2981. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2982. SDE_EVT32(0);
  2983. /* disable hot-plug polling */
  2984. drm_kms_helper_poll_disable(ddev);
  2985. /* if a display stuck in CS trigger a null commit to complete handoff */
  2986. drm_for_each_encoder(enc, ddev) {
  2987. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2988. _sde_kms_null_commit(ddev, enc);
  2989. }
  2990. /* acquire modeset lock(s) */
  2991. drm_modeset_acquire_init(&ctx, 0);
  2992. retry:
  2993. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2994. if (ret)
  2995. goto unlock;
  2996. /* save current state for resume */
  2997. if (sde_kms->suspend_state)
  2998. drm_atomic_state_put(sde_kms->suspend_state);
  2999. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  3000. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  3001. ret = PTR_ERR(sde_kms->suspend_state);
  3002. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  3003. sde_kms->suspend_state = NULL;
  3004. goto unlock;
  3005. }
  3006. /* create atomic state to disable all CRTCs */
  3007. state = drm_atomic_state_alloc(ddev);
  3008. if (!state) {
  3009. ret = -ENOMEM;
  3010. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  3011. goto unlock;
  3012. }
  3013. state->acquire_ctx = &ctx;
  3014. drm_connector_list_iter_begin(ddev, &conn_iter);
  3015. drm_for_each_connector_iter(conn, &conn_iter) {
  3016. struct drm_crtc_state *crtc_state;
  3017. uint64_t lp;
  3018. if (!conn->state || !conn->state->crtc ||
  3019. conn->dpms != DRM_MODE_DPMS_ON ||
  3020. sde_encoder_in_clone_mode(conn->encoder))
  3021. continue;
  3022. lp = sde_connector_get_lp(conn);
  3023. if (lp == SDE_MODE_DPMS_LP1) {
  3024. /* transition LP1->LP2 on pm suspend */
  3025. ret = sde_connector_set_property_for_commit(conn, state,
  3026. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  3027. if (ret) {
  3028. DRM_ERROR("failed to set lp2 for conn %d\n",
  3029. conn->base.id);
  3030. drm_connector_list_iter_end(&conn_iter);
  3031. goto unlock;
  3032. }
  3033. }
  3034. if (lp != SDE_MODE_DPMS_LP2) {
  3035. /* force CRTC to be inactive */
  3036. crtc_state = drm_atomic_get_crtc_state(state,
  3037. conn->state->crtc);
  3038. if (IS_ERR_OR_NULL(crtc_state)) {
  3039. DRM_ERROR("failed to get crtc %d state\n",
  3040. conn->state->crtc->base.id);
  3041. drm_connector_list_iter_end(&conn_iter);
  3042. goto unlock;
  3043. }
  3044. if (lp != SDE_MODE_DPMS_LP1)
  3045. crtc_state->active = false;
  3046. ++num_crtcs;
  3047. }
  3048. }
  3049. drm_connector_list_iter_end(&conn_iter);
  3050. /* check for nothing to do */
  3051. if (num_crtcs == 0) {
  3052. DRM_DEBUG("all crtcs are already in the off state\n");
  3053. sde_kms->suspend_block = true;
  3054. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3055. goto unlock;
  3056. }
  3057. /* commit the "disable all" state */
  3058. ret = drm_atomic_commit(state);
  3059. if (ret < 0) {
  3060. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  3061. goto unlock;
  3062. }
  3063. sde_kms->suspend_block = true;
  3064. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3065. unlock:
  3066. if (state) {
  3067. drm_atomic_state_put(state);
  3068. state = NULL;
  3069. }
  3070. if (ret == -EDEADLK) {
  3071. drm_modeset_backoff(&ctx);
  3072. goto retry;
  3073. }
  3074. drm_modeset_drop_locks(&ctx);
  3075. drm_modeset_acquire_fini(&ctx);
  3076. /*
  3077. * pm runtime driver avoids multiple runtime_suspend API call by
  3078. * checking runtime_status. However, this call helps when there is a
  3079. * race condition between pm_suspend call and doze_suspend/power_off
  3080. * commit. It removes the extra vote from suspend and adds it back
  3081. * later to allow power collapse during pm_suspend call
  3082. */
  3083. pm_runtime_put_sync(dev);
  3084. pm_runtime_get_noresume(dev);
  3085. /* dump clock state before entering suspend */
  3086. if (sde_kms->pm_suspend_clk_dump)
  3087. _sde_kms_dump_clks_state(sde_kms);
  3088. return ret;
  3089. }
  3090. static int sde_kms_pm_resume(struct device *dev)
  3091. {
  3092. struct drm_device *ddev;
  3093. struct sde_kms *sde_kms;
  3094. struct drm_modeset_acquire_ctx ctx;
  3095. int ret, i;
  3096. if (!dev)
  3097. return -EINVAL;
  3098. ddev = dev_get_drvdata(dev);
  3099. if (!ddev || !ddev_to_msm_kms(ddev))
  3100. return -EINVAL;
  3101. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3102. SDE_EVT32(sde_kms->suspend_state != NULL);
  3103. drm_mode_config_reset(ddev);
  3104. drm_modeset_acquire_init(&ctx, 0);
  3105. retry:
  3106. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3107. if (ret == -EDEADLK) {
  3108. drm_modeset_backoff(&ctx);
  3109. goto retry;
  3110. } else if (WARN_ON(ret)) {
  3111. goto end;
  3112. }
  3113. sde_kms->suspend_block = false;
  3114. if (sde_kms->suspend_state) {
  3115. sde_kms->suspend_state->acquire_ctx = &ctx;
  3116. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3117. ret = drm_atomic_helper_commit_duplicated_state(
  3118. sde_kms->suspend_state, &ctx);
  3119. if (ret != -EDEADLK)
  3120. break;
  3121. drm_modeset_backoff(&ctx);
  3122. }
  3123. if (ret < 0)
  3124. DRM_ERROR("failed to restore state, %d\n", ret);
  3125. drm_atomic_state_put(sde_kms->suspend_state);
  3126. sde_kms->suspend_state = NULL;
  3127. }
  3128. end:
  3129. drm_modeset_drop_locks(&ctx);
  3130. drm_modeset_acquire_fini(&ctx);
  3131. /* enable hot-plug polling */
  3132. drm_kms_helper_poll_enable(ddev);
  3133. return 0;
  3134. }
  3135. static const struct msm_kms_funcs kms_funcs = {
  3136. .hw_init = sde_kms_hw_init,
  3137. .postinit = sde_kms_postinit,
  3138. .irq_preinstall = sde_irq_preinstall,
  3139. .irq_postinstall = sde_irq_postinstall,
  3140. .irq_uninstall = sde_irq_uninstall,
  3141. .irq = sde_irq,
  3142. .lastclose = sde_kms_lastclose,
  3143. .prepare_fence = sde_kms_prepare_fence,
  3144. .prepare_commit = sde_kms_prepare_commit,
  3145. .commit = sde_kms_commit,
  3146. .complete_commit = sde_kms_complete_commit,
  3147. .get_msm_mode = sde_kms_get_msm_mode,
  3148. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3149. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3150. .check_modified_format = sde_format_check_modified_format,
  3151. .atomic_check = sde_kms_atomic_check,
  3152. .get_format = sde_get_msm_format,
  3153. .round_pixclk = sde_kms_round_pixclk,
  3154. .display_early_wakeup = sde_kms_display_early_wakeup,
  3155. .pm_suspend = sde_kms_pm_suspend,
  3156. .pm_resume = sde_kms_pm_resume,
  3157. .destroy = sde_kms_destroy,
  3158. .debugfs_destroy = sde_kms_debugfs_destroy,
  3159. .cont_splash_config = sde_kms_cont_splash_config,
  3160. .register_events = _sde_kms_register_events,
  3161. .get_address_space = _sde_kms_get_address_space,
  3162. .get_address_space_device = _sde_kms_get_address_space_device,
  3163. .postopen = _sde_kms_post_open,
  3164. .check_for_splash = sde_kms_check_for_splash,
  3165. .get_mixer_count = sde_kms_get_mixer_count,
  3166. .get_dsc_count = sde_kms_get_dsc_count,
  3167. };
  3168. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3169. {
  3170. int i;
  3171. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3172. if (!sde_kms->aspace[i])
  3173. continue;
  3174. msm_gem_address_space_put(sde_kms->aspace[i]);
  3175. sde_kms->aspace[i] = NULL;
  3176. }
  3177. return 0;
  3178. }
  3179. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3180. {
  3181. struct msm_mmu *mmu;
  3182. int i, ret;
  3183. int early_map = 0;
  3184. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3185. return -EINVAL;
  3186. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3187. struct msm_gem_address_space *aspace;
  3188. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3189. if (IS_ERR(mmu)) {
  3190. ret = PTR_ERR(mmu);
  3191. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3192. i, ret);
  3193. continue;
  3194. }
  3195. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3196. mmu, "sde");
  3197. if (IS_ERR(aspace)) {
  3198. ret = PTR_ERR(aspace);
  3199. mmu->funcs->destroy(mmu);
  3200. goto fail;
  3201. }
  3202. sde_kms->aspace[i] = aspace;
  3203. aspace->domain_attached = true;
  3204. /* Mapping splash memory block */
  3205. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3206. sde_kms->splash_data.num_splash_regions) {
  3207. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3208. if (ret) {
  3209. SDE_ERROR("failed to map ret:%d\n", ret);
  3210. goto early_map_fail;
  3211. }
  3212. }
  3213. /*
  3214. * disable early-map which would have been enabled during
  3215. * bootup by smmu through the device-tree hint for cont-spash
  3216. */
  3217. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3218. &early_map);
  3219. if (ret) {
  3220. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3221. ret, early_map);
  3222. goto early_map_fail;
  3223. }
  3224. }
  3225. sde_kms->base.aspace = sde_kms->aspace[0];
  3226. return 0;
  3227. early_map_fail:
  3228. _sde_kms_unmap_all_splash_regions(sde_kms);
  3229. fail:
  3230. _sde_kms_mmu_destroy(sde_kms);
  3231. return ret;
  3232. }
  3233. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3234. {
  3235. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3236. return;
  3237. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3238. }
  3239. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3240. {
  3241. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3242. return;
  3243. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3244. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3245. sde_kms->catalog);
  3246. }
  3247. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3248. {
  3249. struct sde_vbif_set_qos_params qos_params;
  3250. struct sde_mdss_cfg *catalog;
  3251. if (!sde_kms->catalog)
  3252. return;
  3253. catalog = sde_kms->catalog;
  3254. memset(&qos_params, 0, sizeof(qos_params));
  3255. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3256. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3257. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3258. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3259. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3260. }
  3261. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3262. {
  3263. struct sde_hw_uidle *uidle;
  3264. if (!sde_kms) {
  3265. SDE_ERROR("invalid kms\n");
  3266. return -EINVAL;
  3267. }
  3268. uidle = sde_kms->hw_uidle;
  3269. if (uidle && uidle->ops.active_override_enable)
  3270. uidle->ops.active_override_enable(uidle, enable);
  3271. return 0;
  3272. }
  3273. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3274. {
  3275. struct device *cpu_dev;
  3276. int cpu = 0;
  3277. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3278. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3279. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3280. return;
  3281. }
  3282. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3283. cpu_dev = get_cpu_device(cpu);
  3284. if (!cpu_dev) {
  3285. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3286. cpu);
  3287. continue;
  3288. }
  3289. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3290. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3291. cpu_irq_latency);
  3292. else
  3293. dev_pm_qos_add_request(cpu_dev,
  3294. &sde_kms->pm_qos_irq_req[cpu],
  3295. DEV_PM_QOS_RESUME_LATENCY,
  3296. cpu_irq_latency);
  3297. }
  3298. }
  3299. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3300. {
  3301. struct device *cpu_dev;
  3302. int cpu = 0;
  3303. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3304. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3305. return;
  3306. }
  3307. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3308. cpu_dev = get_cpu_device(cpu);
  3309. if (!cpu_dev) {
  3310. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3311. cpu);
  3312. continue;
  3313. }
  3314. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3315. dev_pm_qos_remove_request(
  3316. &sde_kms->pm_qos_irq_req[cpu]);
  3317. }
  3318. }
  3319. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3320. {
  3321. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3322. mutex_lock(&priv->phandle.phandle_lock);
  3323. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3324. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3325. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3326. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3327. mutex_unlock(&priv->phandle.phandle_lock);
  3328. }
  3329. static void sde_kms_irq_affinity_notify(
  3330. struct irq_affinity_notify *affinity_notify,
  3331. const cpumask_t *mask)
  3332. {
  3333. struct msm_drm_private *priv;
  3334. struct sde_kms *sde_kms = container_of(affinity_notify,
  3335. struct sde_kms, affinity_notify);
  3336. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3337. return;
  3338. priv = sde_kms->dev->dev_private;
  3339. mutex_lock(&priv->phandle.phandle_lock);
  3340. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3341. // save irq cpu mask
  3342. sde_kms->irq_cpu_mask = *mask;
  3343. // request vote with updated irq cpu mask
  3344. if (atomic_read(&sde_kms->irq_vote_count))
  3345. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3346. mutex_unlock(&priv->phandle.phandle_lock);
  3347. }
  3348. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3349. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3350. {
  3351. struct sde_kms *sde_kms = usr;
  3352. struct msm_kms *msm_kms;
  3353. msm_kms = &sde_kms->base;
  3354. if (!sde_kms)
  3355. return;
  3356. SDE_DEBUG("event_type:%d\n", event_type);
  3357. SDE_EVT32_VERBOSE(event_type);
  3358. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3359. sde_irq_update(msm_kms, true);
  3360. sde_kms->first_kickoff = true;
  3361. /**
  3362. * Rotator sid needs to be programmed since uefi doesn't
  3363. * configure it during continuous splash
  3364. */
  3365. sde_kms_init_rot_sid_hw(sde_kms);
  3366. if (sde_kms->splash_data.num_splash_displays ||
  3367. sde_in_trusted_vm(sde_kms))
  3368. return;
  3369. sde_vbif_init_memtypes(sde_kms);
  3370. sde_kms_init_shared_hw(sde_kms);
  3371. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3372. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3373. sde_irq_update(msm_kms, false);
  3374. sde_kms->first_kickoff = false;
  3375. if (sde_in_trusted_vm(sde_kms))
  3376. return;
  3377. _sde_kms_active_override(sde_kms, true);
  3378. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3379. sde_vbif_axi_halt_request(sde_kms);
  3380. }
  3381. }
  3382. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3383. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3384. {
  3385. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3386. int rc = -EINVAL;
  3387. SDE_DEBUG("\n");
  3388. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3389. if (rc > 0)
  3390. rc = 0;
  3391. SDE_EVT32(rc, genpd->device_count);
  3392. return rc;
  3393. }
  3394. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3395. {
  3396. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3397. SDE_DEBUG("\n");
  3398. pm_runtime_put_sync(sde_kms->dev->dev);
  3399. SDE_EVT32(genpd->device_count);
  3400. return 0;
  3401. }
  3402. static int _sde_kms_get_demura_plane_data(struct sde_splash_data *data)
  3403. {
  3404. int i = 0;
  3405. int ret = 0;
  3406. int count = 0;
  3407. struct device_node *parent, *node;
  3408. struct resource r;
  3409. char node_name[DEMURA_REGION_NAME_MAX];
  3410. struct sde_splash_mem *mem;
  3411. struct sde_splash_display *splash_display;
  3412. if (!data->num_splash_displays) {
  3413. SDE_DEBUG("no splash displays. skipping\n");
  3414. return 0;
  3415. }
  3416. /**
  3417. * It is expected that each active demura block will have
  3418. * its own memory region defined.
  3419. */
  3420. parent = of_find_node_by_path("/reserved-memory");
  3421. for (i = 0; i < data->num_splash_displays; i++) {
  3422. splash_display = &data->splash_display[i];
  3423. snprintf(&node_name[0], DEMURA_REGION_NAME_MAX,
  3424. "demura_region_%d", i);
  3425. splash_display->demura = NULL;
  3426. node = of_find_node_by_name(parent, node_name);
  3427. if (!node) {
  3428. SDE_DEBUG("no Demura node %s! disp count: %d\n",
  3429. node_name, data->num_splash_displays);
  3430. continue;
  3431. } else if (of_address_to_resource(node, i, &r)) {
  3432. SDE_ERROR("invalid data for:%s\n", node_name);
  3433. ret = -EINVAL;
  3434. break;
  3435. }
  3436. mem = &data->demura_mem[i];
  3437. mem->splash_buf_base = (unsigned long)r.start;
  3438. mem->splash_buf_size = (r.end - r.start) + 1;
  3439. if (!mem->splash_buf_base && !mem->splash_buf_size) {
  3440. SDE_DEBUG("dummy splash mem for disp %d. Skipping\n",
  3441. (i+1));
  3442. continue;
  3443. } else if (!mem->splash_buf_base || !mem->splash_buf_size) {
  3444. SDE_ERROR("mem for disp %d invalid: add:%lx size:%lx\n",
  3445. (i+1), mem->splash_buf_base,
  3446. mem->splash_buf_size);
  3447. continue;
  3448. }
  3449. mem->ref_cnt = 0;
  3450. splash_display->demura = mem;
  3451. count++;
  3452. SDE_DEBUG("demura mem for disp:%d add:%lx size:%x\n", (i + 1),
  3453. mem->splash_buf_base,
  3454. mem->splash_buf_size);
  3455. }
  3456. if (!ret && !count)
  3457. SDE_DEBUG("no demura regions for cont. splash found!\n");
  3458. return ret;
  3459. }
  3460. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  3461. {
  3462. int i = 0;
  3463. int ret = 0;
  3464. struct device_node *parent, *node, *node1;
  3465. struct resource r, r1;
  3466. const char *node_name = "splash_region";
  3467. struct sde_splash_mem *mem;
  3468. bool share_splash_mem = false;
  3469. int num_displays, num_regions;
  3470. struct sde_splash_display *splash_display;
  3471. if (!data)
  3472. return -EINVAL;
  3473. memset(data, 0, sizeof(*data));
  3474. parent = of_find_node_by_path("/reserved-memory");
  3475. if (!parent) {
  3476. SDE_ERROR("failed to find reserved-memory node\n");
  3477. return -EINVAL;
  3478. }
  3479. node = of_find_node_by_name(parent, node_name);
  3480. if (!node) {
  3481. SDE_DEBUG("failed to find node %s\n", node_name);
  3482. return -EINVAL;
  3483. }
  3484. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3485. if (!node1)
  3486. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3487. /**
  3488. * Support sharing a single splash memory for all the built in displays
  3489. * and also independent splash region per displays. Incase of
  3490. * independent splash region for each connected display, dtsi node of
  3491. * cont_splash_region should be collection of all memory regions
  3492. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3493. */
  3494. num_displays = dsi_display_get_num_of_displays();
  3495. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3496. data->num_splash_displays = num_displays;
  3497. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3498. if (num_displays > num_regions) {
  3499. share_splash_mem = true;
  3500. pr_info(":%d displays share same splash buf\n", num_displays);
  3501. }
  3502. for (i = 0; i < num_displays; i++) {
  3503. splash_display = &data->splash_display[i];
  3504. if (!i || !share_splash_mem) {
  3505. if (of_address_to_resource(node, i, &r)) {
  3506. SDE_ERROR("invalid data for:%s\n", node_name);
  3507. return -EINVAL;
  3508. }
  3509. mem = &data->splash_mem[i];
  3510. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3511. SDE_DEBUG("failed to find ramdump memory\n");
  3512. mem->ramdump_base = 0;
  3513. mem->ramdump_size = 0;
  3514. } else {
  3515. mem->ramdump_base = (unsigned long)r1.start;
  3516. mem->ramdump_size = (r1.end - r1.start) + 1;
  3517. }
  3518. mem->splash_buf_base = (unsigned long)r.start;
  3519. mem->splash_buf_size = (r.end - r.start) + 1;
  3520. mem->ref_cnt = 0;
  3521. splash_display->splash = mem;
  3522. data->num_splash_regions++;
  3523. } else {
  3524. data->splash_display[i].splash = &data->splash_mem[0];
  3525. }
  3526. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3527. splash_display->splash->splash_buf_base,
  3528. splash_display->splash->splash_buf_size);
  3529. }
  3530. data->type = SDE_SPLASH_HANDOFF;
  3531. ret = _sde_kms_get_demura_plane_data(data);
  3532. return ret;
  3533. }
  3534. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3535. struct platform_device *platformdev)
  3536. {
  3537. int rc = -EINVAL;
  3538. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3539. if (IS_ERR(sde_kms->mmio)) {
  3540. rc = PTR_ERR(sde_kms->mmio);
  3541. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3542. sde_kms->mmio = NULL;
  3543. goto error;
  3544. }
  3545. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3546. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3547. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3548. sde_kms->mmio_len, SDE_DBG_SDE);
  3549. if (rc)
  3550. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3551. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys", "vbif_phys");
  3552. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3553. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3554. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3555. sde_kms->vbif[VBIF_RT] = NULL;
  3556. goto error;
  3557. }
  3558. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev, "vbif_phys");
  3559. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3560. sde_kms->vbif_len[VBIF_RT], SDE_DBG_VBIF_RT);
  3561. if (rc)
  3562. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3563. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys", "vbif_nrt_phys");
  3564. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3565. sde_kms->vbif[VBIF_NRT] = NULL;
  3566. SDE_DEBUG("VBIF NRT is not defined");
  3567. } else {
  3568. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev, "vbif_nrt_phys");
  3569. }
  3570. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys", "regdma_phys");
  3571. if (IS_ERR(sde_kms->reg_dma)) {
  3572. sde_kms->reg_dma = NULL;
  3573. SDE_DEBUG("REG_DMA is not defined");
  3574. } else {
  3575. sde_kms->reg_dma_len = msm_iomap_size(platformdev, "regdma_phys");
  3576. rc = sde_dbg_reg_register_base("reg_dma", sde_kms->reg_dma,
  3577. sde_kms->reg_dma_len, SDE_DBG_LUTDMA);
  3578. if (rc)
  3579. SDE_ERROR("dbg base register reg_dma failed: %d\n", rc);
  3580. }
  3581. sde_kms->sid = msm_ioremap(platformdev, "sid_phys", "sid_phys");
  3582. if (IS_ERR(sde_kms->sid)) {
  3583. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3584. sde_kms->sid = NULL;
  3585. } else {
  3586. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3587. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3588. sde_kms->sid_len, SDE_DBG_SID);
  3589. if (rc)
  3590. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3591. }
  3592. error:
  3593. return rc;
  3594. }
  3595. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3596. struct sde_kms *sde_kms)
  3597. {
  3598. int rc = 0;
  3599. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3600. sde_kms->genpd.name = dev->unique;
  3601. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3602. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3603. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3604. if (rc < 0) {
  3605. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3606. sde_kms->genpd.name, rc);
  3607. return rc;
  3608. }
  3609. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3610. &sde_kms->genpd);
  3611. if (rc < 0) {
  3612. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3613. sde_kms->genpd.name, rc);
  3614. pm_genpd_remove(&sde_kms->genpd);
  3615. return rc;
  3616. }
  3617. sde_kms->genpd_init = true;
  3618. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3619. }
  3620. return rc;
  3621. }
  3622. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3623. struct drm_device *dev,
  3624. struct msm_drm_private *priv)
  3625. {
  3626. struct sde_rm *rm = NULL;
  3627. int i, rc = -EINVAL;
  3628. sde_kms->catalog = sde_hw_catalog_init(dev);
  3629. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3630. rc = PTR_ERR(sde_kms->catalog);
  3631. if (!sde_kms->catalog)
  3632. rc = -EINVAL;
  3633. SDE_ERROR("catalog init failed: %d\n", rc);
  3634. sde_kms->catalog = NULL;
  3635. goto power_error;
  3636. }
  3637. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3638. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3639. /* initialize power domain if defined */
  3640. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3641. if (rc) {
  3642. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3643. goto genpd_err;
  3644. }
  3645. rc = _sde_kms_mmu_init(sde_kms);
  3646. if (rc) {
  3647. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3648. goto power_error;
  3649. }
  3650. /* Initialize reg dma block which is a singleton */
  3651. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3652. sde_kms->dev);
  3653. if (rc) {
  3654. SDE_ERROR("failed: reg dma init failed\n");
  3655. goto power_error;
  3656. }
  3657. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3658. rm = &sde_kms->rm;
  3659. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3660. sde_kms->dev);
  3661. if (rc) {
  3662. SDE_ERROR("rm init failed: %d\n", rc);
  3663. goto power_error;
  3664. }
  3665. sde_kms->rm_init = true;
  3666. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3667. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3668. rc = PTR_ERR(sde_kms->hw_intr);
  3669. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3670. sde_kms->hw_intr = NULL;
  3671. goto hw_intr_init_err;
  3672. }
  3673. /*
  3674. * Attempt continuous splash handoff only if reserved
  3675. * splash memory is found & release resources on any error
  3676. * in finding display hw config in splash
  3677. */
  3678. if (sde_kms->splash_data.num_splash_regions) {
  3679. struct sde_splash_display *display;
  3680. int ret, display_count =
  3681. sde_kms->splash_data.num_splash_displays;
  3682. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3683. &sde_kms->splash_data, sde_kms->catalog);
  3684. for (i = 0; i < display_count; i++) {
  3685. display = &sde_kms->splash_data.splash_display[i];
  3686. /*
  3687. * free splash region on resource init failure and
  3688. * cont-splash disabled case
  3689. */
  3690. if (!display->cont_splash_enabled || ret)
  3691. _sde_kms_free_splash_display_data(
  3692. sde_kms, display);
  3693. }
  3694. }
  3695. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3696. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3697. rc = PTR_ERR(sde_kms->hw_mdp);
  3698. if (!sde_kms->hw_mdp)
  3699. rc = -EINVAL;
  3700. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3701. sde_kms->hw_mdp = NULL;
  3702. goto power_error;
  3703. }
  3704. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3705. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3706. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3707. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3708. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3709. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3710. if (!sde_kms->hw_vbif[vbif_idx])
  3711. rc = -EINVAL;
  3712. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3713. sde_kms->hw_vbif[vbif_idx] = NULL;
  3714. goto power_error;
  3715. }
  3716. }
  3717. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3718. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3719. sde_kms->mmio_len, sde_kms->catalog);
  3720. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3721. rc = PTR_ERR(sde_kms->hw_uidle);
  3722. if (!sde_kms->hw_uidle)
  3723. rc = -EINVAL;
  3724. /* uidle is optional, so do not make it a fatal error */
  3725. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3726. sde_kms->hw_uidle = NULL;
  3727. rc = 0;
  3728. }
  3729. } else {
  3730. sde_kms->hw_uidle = NULL;
  3731. }
  3732. if (sde_kms->sid) {
  3733. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3734. sde_kms->sid_len, sde_kms->catalog);
  3735. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3736. rc = PTR_ERR(sde_kms->hw_sid);
  3737. SDE_ERROR("failed to init sid %d\n", rc);
  3738. sde_kms->hw_sid = NULL;
  3739. goto power_error;
  3740. }
  3741. }
  3742. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3743. &priv->phandle, "core_clk");
  3744. if (rc) {
  3745. SDE_ERROR("failed to init perf %d\n", rc);
  3746. goto perf_err;
  3747. }
  3748. /*
  3749. * set the disable_immediate flag when driver supports the precise vsync
  3750. * timestamp as the DRM hooks for vblank timestamp/counters would be set
  3751. * based on the feature
  3752. */
  3753. if (sde_kms->catalog->has_precise_vsync_ts)
  3754. dev->vblank_disable_immediate = true;
  3755. /*
  3756. * _sde_kms_drm_obj_init should create the DRM related objects
  3757. * i.e. CRTCs, planes, encoders, connectors and so forth
  3758. */
  3759. rc = _sde_kms_drm_obj_init(sde_kms);
  3760. if (rc) {
  3761. SDE_ERROR("modeset init failed: %d\n", rc);
  3762. goto drm_obj_init_err;
  3763. }
  3764. return 0;
  3765. genpd_err:
  3766. drm_obj_init_err:
  3767. sde_core_perf_destroy(&sde_kms->perf);
  3768. hw_intr_init_err:
  3769. perf_err:
  3770. power_error:
  3771. return rc;
  3772. }
  3773. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3774. {
  3775. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3776. int rc = 0;
  3777. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3778. if (rc) {
  3779. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3780. return rc;
  3781. }
  3782. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3783. if (rc) {
  3784. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3785. return rc;
  3786. }
  3787. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3788. if (rc) {
  3789. SDE_ERROR("failed to get io irq for KMS");
  3790. return rc;
  3791. }
  3792. return rc;
  3793. }
  3794. static int sde_kms_hw_init(struct msm_kms *kms)
  3795. {
  3796. struct sde_kms *sde_kms;
  3797. struct drm_device *dev;
  3798. struct msm_drm_private *priv;
  3799. struct platform_device *platformdev;
  3800. int i, irq_num, rc = -EINVAL;
  3801. if (!kms) {
  3802. SDE_ERROR("invalid kms\n");
  3803. goto end;
  3804. }
  3805. sde_kms = to_sde_kms(kms);
  3806. dev = sde_kms->dev;
  3807. if (!dev || !dev->dev) {
  3808. SDE_ERROR("invalid device\n");
  3809. goto end;
  3810. }
  3811. platformdev = to_platform_device(dev->dev);
  3812. priv = dev->dev_private;
  3813. if (!priv) {
  3814. SDE_ERROR("invalid private data\n");
  3815. goto end;
  3816. }
  3817. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3818. if (rc)
  3819. goto error;
  3820. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  3821. if (rc)
  3822. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3823. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3824. if (rc)
  3825. goto error;
  3826. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3827. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3828. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3829. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3830. mutex_init(&sde_kms->secure_transition_lock);
  3831. atomic_set(&sde_kms->detach_sec_cb, 0);
  3832. atomic_set(&sde_kms->detach_all_cb, 0);
  3833. atomic_set(&sde_kms->irq_vote_count, 0);
  3834. /*
  3835. * Support format modifiers for compression etc.
  3836. */
  3837. dev->mode_config.allow_fb_modifiers = true;
  3838. /*
  3839. * Handle (re)initializations during power enable
  3840. */
  3841. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3842. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3843. SDE_POWER_EVENT_POST_ENABLE |
  3844. SDE_POWER_EVENT_PRE_DISABLE,
  3845. sde_kms_handle_power_event, sde_kms, "kms");
  3846. if (sde_kms->splash_data.num_splash_displays) {
  3847. SDE_DEBUG("Skipping MDP Resources disable\n");
  3848. } else {
  3849. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3850. sde_power_data_bus_set_quota(&priv->phandle, i,
  3851. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3852. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3853. pm_runtime_put_sync(sde_kms->dev->dev);
  3854. }
  3855. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3856. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3857. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3858. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3859. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3860. if (sde_in_trusted_vm(sde_kms))
  3861. rc = sde_vm_trusted_init(sde_kms);
  3862. else
  3863. rc = sde_vm_primary_init(sde_kms);
  3864. if (rc) {
  3865. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3866. goto error;
  3867. }
  3868. return 0;
  3869. error:
  3870. _sde_kms_hw_destroy(sde_kms, platformdev);
  3871. end:
  3872. return rc;
  3873. }
  3874. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3875. {
  3876. struct msm_drm_private *priv;
  3877. struct sde_kms *sde_kms;
  3878. if (!dev || !dev->dev_private) {
  3879. SDE_ERROR("drm device node invalid\n");
  3880. return ERR_PTR(-EINVAL);
  3881. }
  3882. priv = dev->dev_private;
  3883. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3884. if (!sde_kms) {
  3885. SDE_ERROR("failed to allocate sde kms\n");
  3886. return ERR_PTR(-ENOMEM);
  3887. }
  3888. msm_kms_init(&sde_kms->base, &kms_funcs);
  3889. sde_kms->dev = dev;
  3890. return &sde_kms->base;
  3891. }
  3892. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3893. {
  3894. struct dsi_display *display;
  3895. struct sde_splash_display *handoff_display;
  3896. int i;
  3897. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3898. handoff_display = &sde_kms->splash_data.splash_display[i];
  3899. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3900. if (handoff_display->cont_splash_enabled)
  3901. _sde_kms_free_splash_display_data(sde_kms,
  3902. handoff_display);
  3903. dsi_display_set_active_state(display, false);
  3904. }
  3905. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3906. }
  3907. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms,
  3908. struct drm_atomic_state *state)
  3909. {
  3910. struct drm_device *dev;
  3911. struct msm_drm_private *priv;
  3912. struct sde_splash_display *handoff_display;
  3913. struct dsi_display *display;
  3914. int ret, i;
  3915. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3916. SDE_ERROR("invalid params\n");
  3917. return -EINVAL;
  3918. }
  3919. dev = sde_kms->dev;
  3920. priv = dev->dev_private;
  3921. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3922. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3923. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3924. &sde_kms->splash_data, sde_kms->catalog);
  3925. if (ret) {
  3926. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  3927. return -EINVAL;
  3928. }
  3929. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3930. handoff_display = &sde_kms->splash_data.splash_display[i];
  3931. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3932. if (!handoff_display->cont_splash_enabled || ret)
  3933. _sde_kms_free_splash_display_data(sde_kms,
  3934. handoff_display);
  3935. else
  3936. dsi_display_set_active_state(display, true);
  3937. }
  3938. if (sde_kms->splash_data.num_splash_displays != 1) {
  3939. SDE_ERROR("no. of displays not supported:%d\n",
  3940. sde_kms->splash_data.num_splash_displays);
  3941. goto error;
  3942. }
  3943. ret = sde_kms_cont_splash_config(&sde_kms->base, state);
  3944. if (ret) {
  3945. SDE_ERROR("error in setting handoff configs\n");
  3946. goto error;
  3947. }
  3948. /**
  3949. * fill-in vote for the continuous splash hanodff path, which will be
  3950. * removed on the successful first commit.
  3951. */
  3952. pm_runtime_get_sync(sde_kms->dev->dev);
  3953. return 0;
  3954. error:
  3955. return ret;
  3956. }
  3957. static int _sde_kms_register_events(struct msm_kms *kms,
  3958. struct drm_mode_object *obj, u32 event, bool en)
  3959. {
  3960. int ret = 0;
  3961. struct drm_crtc *crtc = NULL;
  3962. struct drm_connector *conn = NULL;
  3963. struct sde_kms *sde_kms = NULL;
  3964. struct sde_vm_ops *vm_ops;
  3965. if (!kms || !obj) {
  3966. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3967. return -EINVAL;
  3968. }
  3969. sde_kms = to_sde_kms(kms);
  3970. /* check vm ownership, if event registration requires HW access */
  3971. switch (obj->type) {
  3972. case DRM_MODE_OBJECT_CRTC:
  3973. vm_ops = sde_vm_get_ops(sde_kms);
  3974. sde_vm_lock(sde_kms);
  3975. if (vm_ops && vm_ops->vm_owns_hw
  3976. && !vm_ops->vm_owns_hw(sde_kms)) {
  3977. sde_vm_unlock(sde_kms);
  3978. SDE_DEBUG("HW is owned by other VM\n");
  3979. return -EACCES;
  3980. }
  3981. crtc = obj_to_crtc(obj);
  3982. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3983. sde_vm_unlock(sde_kms);
  3984. break;
  3985. case DRM_MODE_OBJECT_CONNECTOR:
  3986. conn = obj_to_connector(obj);
  3987. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3988. en);
  3989. break;
  3990. }
  3991. return ret;
  3992. }
  3993. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3994. {
  3995. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3996. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3997. }