android_kernel_samsung_sm8650-modules/hw/qcn9000/rfa_from_wsi_seq_hwiobase.h

/*
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

///////////////////////////////////////////////////////////////////////////////////////////////
//
///////////////////////////////////////////////////////////////////////////////////////////////
//
// rfa_from_wsi_seq_hwiobase.h : automatically generated by Autoseq  3.1 1/17/2019 
// User Name:pbechana
//
// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////

#ifndef __RFA_FROM_WSI_SEQ_BASE_H__
#define __RFA_FROM_WSI_SEQ_BASE_H__

#ifdef SCALE_INCLUDES
	#include "HALhwio.h"
#else
	#include "msmhwio.h"
#endif


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_from_wsi
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_RFA_FROM_WSI_AO_SYSCTRL_OFFSET                           0x00001000
#define SEQ_RFA_FROM_WSI_AO_TLMM_OFFSET                              0x00001400
#define SEQ_RFA_FROM_WSI_AO_OVERRIDE_REG_OFFSET                      0x00001800
#define SEQ_RFA_FROM_WSI_CM_TLMM_OFFSET                              0x00002000
#define SEQ_RFA_FROM_WSI_CM_TRC_OFFSET                               0x00002200
#define SEQ_RFA_FROM_WSI_HZ_COEX_LTE_REG_OFFSET                      0x00007000
#define SEQ_RFA_FROM_WSI_PMU_OFFSET                                  0x0000b000
#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_OFFSET                  0x0000c000
#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x0000eb00
#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x0000c000
#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x00010000
#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET                              0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET                          0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET                     0x00014240
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET                     0x000142c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET                       0x00014300
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET                  0x00014400
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET                      0x00014480
#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET                       0x00014800
#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET                      0x00014c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_OFFSET                        0x00015000
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET                0x00015400
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET                 0x00016000
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET               0x00016040
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET               0x00016100
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET                 0x00016140
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET               0x00016180
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET                 0x000161c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET                 0x00016280
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET                 0x00016800
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET               0x00016840
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET               0x00016900
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET                 0x00016940
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET               0x00016980
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET                 0x000169c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET                 0x00016a80
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BS_OFFSET                 0x00017000
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_CLBS_OFFSET               0x00017040
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BIST_OFFSET               0x00017100
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_PC_OFFSET                 0x00017140
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_KVCO_OFFSET               0x00017180
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_AC_OFFSET                 0x000171c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_LO_OFFSET                 0x00017280
#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET               0x00017c00
#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET                               0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET                        0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET          0x0001e800
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET                        0x0001e980
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET         0x0001e9c0
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET                   0x0001eac0
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TX_OFFSET                         0x0001ec00
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RX_CH0_OFFSET                     0x0001f000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RX_CH1_OFFSET                     0x0001f200
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET                   0x0001fc00
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET                 0x0001fc40
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET                   0x0001fc80
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET                   0x0001fcc0
#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET                               0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET                  0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH0_OFFSET                0x00020400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH0_OFFSET                0x00020800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET                0x00021000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET                0x00021300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET                 0x00022000
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH0_OFFSET               0x00022400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH0_OFFSET                 0x00022580
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET  0x000225c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET            0x000226c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET        0x00022734
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH0_OFFSET                 0x00022740
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x00022800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET  0x00022840
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x00022880
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET  0x000228c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET     0x00022900
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET        0x0002299c
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET                 0x00024000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET                  0x00028000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH0_OFFSET                0x00028400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH0_OFFSET                0x00028800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET                0x00029000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET                0x00029300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET                 0x0002a000
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH0_OFFSET               0x0002a400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH0_OFFSET                 0x0002a580
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET  0x0002a5c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET            0x0002a6c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET        0x0002a734
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH0_OFFSET                 0x0002a740
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x0002a800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET  0x0002a840
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x0002a880
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET  0x0002a8c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET     0x0002a900
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET        0x0002a99c
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET                 0x0002c000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET                  0x00030000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH1_OFFSET                0x00030400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH1_OFFSET                0x00030800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET                0x00031000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET                0x00031300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET                 0x00032000
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH1_OFFSET               0x00032400
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_OFFSET                      0x00032500
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH1_OFFSET                 0x00032580
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET  0x000325c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET            0x000326c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET        0x00032734
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH1_OFFSET                 0x00032740
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x00032800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET  0x00032840
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x00032880
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET  0x000328c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET     0x00032900
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET        0x0003299c
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_CAL_CORE_OFFSET                   0x00032c00
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET                 0x00034000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET                  0x00038000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET                0x00038400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH1_OFFSET                0x00038800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET                0x00039000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET                0x00039300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET                 0x0003a000
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH1_OFFSET               0x0003a400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH1_OFFSET                 0x0003a580
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET  0x0003a5c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET            0x0003a6c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET        0x0003a734
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH1_OFFSET                 0x0003a740
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x0003a800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET  0x0003a840
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x0003a880
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET  0x0003a8c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET     0x0003a900
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET        0x0003a99c
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET                 0x0003c000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block security_control_bt
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_SECURITY_CONTROL_BT_BT_SECURITY_CONTROL_CORE_OFFSET      0x00002b00
#define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_RAW_FUSE_OFFSET            0x00000000
#define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_CORR_FUSE_OFFSET           0x00004000


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_cmn
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_RFA_CMN_AON_OFFSET                                       0x00000000
#define SEQ_RFA_CMN_AON_XFEM_OFFSET                                  0x00000240
#define SEQ_RFA_CMN_AON_COEX_OFFSET                                  0x000002c0
#define SEQ_RFA_CMN_RFFE_M_OFFSET                                    0x00000300
#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET                               0x00000400
#define SEQ_RFA_CMN_RFA_OTP_OFFSET                                   0x00000480
#define SEQ_RFA_CMN_CLKGEN_OFFSET                                    0x00000800
#define SEQ_RFA_CMN_BTFMPLL_OFFSET                                   0x00000c00
#define SEQ_RFA_CMN_BBPLL_OFFSET                                     0x00001000
#define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET                             0x00001400
#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET                              0x00002000
#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET                            0x00002040
#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET                            0x00002100
#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET                              0x00002140
#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET                            0x00002180
#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET                              0x000021c0
#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET                              0x00002280
#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET                              0x00002800
#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET                            0x00002840
#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET                            0x00002900
#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET                              0x00002940
#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET                            0x00002980
#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET                              0x000029c0
#define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET                              0x00002a80
#define SEQ_RFA_CMN_WL_SYNTH2_BS_OFFSET                              0x00003000
#define SEQ_RFA_CMN_WL_SYNTH2_CLBS_OFFSET                            0x00003040
#define SEQ_RFA_CMN_WL_SYNTH2_BIST_OFFSET                            0x00003100
#define SEQ_RFA_CMN_WL_SYNTH2_PC_OFFSET                              0x00003140
#define SEQ_RFA_CMN_WL_SYNTH2_KVCO_OFFSET                            0x00003180
#define SEQ_RFA_CMN_WL_SYNTH2_AC_OFFSET                              0x000031c0
#define SEQ_RFA_CMN_WL_SYNTH2_LO_OFFSET                              0x00003280
#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET                            0x00003c00


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_bt
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_RFA_BT_BT_TOP_OFFSET                                     0x00000000
#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET                       0x00002800
#define SEQ_RFA_BT_BT_DAC_OFFSET                                     0x00002980
#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET                      0x000029c0
#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET                                0x00002ac0
#define SEQ_RFA_BT_BT_TX_OFFSET                                      0x00002c00
#define SEQ_RFA_BT_BT_RX_CH0_OFFSET                                  0x00003000
#define SEQ_RFA_BT_BT_RX_CH1_OFFSET                                  0x00003200
#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET                                0x00003c00
#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET                              0x00003c40
#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET                                0x00003c80
#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET                                0x00003cc0


///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_wl
///////////////////////////////////////////////////////////////////////////////////////////////

#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET                               0x00000000
#define SEQ_RFA_WL_WL_RXBB_2G_CH0_OFFSET                             0x00000400
#define SEQ_RFA_WL_WL_TXBB_2G_CH0_OFFSET                             0x00000800
#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET                             0x00001000
#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET                             0x00001300
#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET                              0x00002000
#define SEQ_RFA_WL_RBIST_TX_2G_CH0_OFFSET                            0x00002400
#define SEQ_RFA_WL_WL_DAC_2G_CH0_OFFSET                              0x00002580
#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET               0x000025c0
#define SEQ_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET                         0x000026c0
#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET                     0x00002734
#define SEQ_RFA_WL_WL_ADC_2G_CH0_OFFSET                              0x00002740
#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET              0x00002800
#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET               0x00002840
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET              0x00002880
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET               0x000028c0
#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET                  0x00002900
#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET                     0x0000299c
#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET                              0x00004000
#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET                               0x00008000
#define SEQ_RFA_WL_WL_RXBB_5G_CH0_OFFSET                             0x00008400
#define SEQ_RFA_WL_WL_TXBB_5G_CH0_OFFSET                             0x00008800
#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET                             0x00009000
#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET                             0x00009300
#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET                              0x0000a000
#define SEQ_RFA_WL_RBIST_TX_5G_CH0_OFFSET                            0x0000a400
#define SEQ_RFA_WL_WL_DAC_5G_CH0_OFFSET                              0x0000a580
#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET               0x0000a5c0
#define SEQ_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET                         0x0000a6c0
#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET                     0x0000a734
#define SEQ_RFA_WL_WL_ADC_5G_CH0_OFFSET                              0x0000a740
#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET              0x0000a800
#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET               0x0000a840
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET              0x0000a880
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET               0x0000a8c0
#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET                  0x0000a900
#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET                     0x0000a99c
#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET                              0x0000c000
#define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET                               0x00010000
#define SEQ_RFA_WL_WL_RXBB_2G_CH1_OFFSET                             0x00010400
#define SEQ_RFA_WL_WL_TXBB_2G_CH1_OFFSET                             0x00010800
#define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET                             0x00011000
#define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET                             0x00011300
#define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET                              0x00012000
#define SEQ_RFA_WL_RBIST_TX_2G_CH1_OFFSET                            0x00012400
#define SEQ_RFA_WL_RBIST_RX_OFFSET                                   0x00012500
#define SEQ_RFA_WL_WL_DAC_2G_CH1_OFFSET                              0x00012580
#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET               0x000125c0
#define SEQ_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET                         0x000126c0
#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET                     0x00012734
#define SEQ_RFA_WL_WL_ADC_2G_CH1_OFFSET                              0x00012740
#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET              0x00012800
#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET               0x00012840
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET              0x00012880
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET               0x000128c0
#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET                  0x00012900
#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET                     0x0001299c
#define SEQ_RFA_WL_WL_CAL_CORE_OFFSET                                0x00012c00
#define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET                              0x00014000
#define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET                               0x00018000
#define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET                             0x00018400
#define SEQ_RFA_WL_WL_TXBB_5G_CH1_OFFSET                             0x00018800
#define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET                             0x00019000
#define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET                             0x00019300
#define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET                              0x0001a000
#define SEQ_RFA_WL_RBIST_TX_5G_CH1_OFFSET                            0x0001a400
#define SEQ_RFA_WL_WL_DAC_5G_CH1_OFFSET                              0x0001a580
#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET               0x0001a5c0
#define SEQ_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET                         0x0001a6c0
#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET                     0x0001a734
#define SEQ_RFA_WL_WL_ADC_5G_CH1_OFFSET                              0x0001a740
#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET              0x0001a800
#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET               0x0001a840
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET              0x0001a880
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET               0x0001a8c0
#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET                  0x0001a900
#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET                     0x0001a99c
#define SEQ_RFA_WL_WL_MEM_5G_CH1_OFFSET                              0x0001c000


#endif