qcs405.c 245 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <dsp/q6afe-v2.h>
  25. #include <dsp/q6core.h>
  26. #include <dsp/msm_mdf.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include <asoc/msm-cdc-pinctrl.h>
  30. #include "codecs/wcd9335.h"
  31. #include "codecs/wsa881x.h"
  32. #include "codecs/csra66x0/csra66x0.h"
  33. #include <dt-bindings/sound/audio-codec-port-types.h>
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include "codecs/bolero/wsa-macro.h"
  36. #define DRV_NAME "qcs405-asoc-snd"
  37. #define __CHIPSET__ "QCS405 "
  38. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  39. #define DEV_NAME_STR_LEN 32
  40. #define SAMPLING_RATE_8KHZ 8000
  41. #define SAMPLING_RATE_11P025KHZ 11025
  42. #define SAMPLING_RATE_16KHZ 16000
  43. #define SAMPLING_RATE_22P05KHZ 22050
  44. #define SAMPLING_RATE_32KHZ 32000
  45. #define SAMPLING_RATE_44P1KHZ 44100
  46. #define SAMPLING_RATE_48KHZ 48000
  47. #define SAMPLING_RATE_88P2KHZ 88200
  48. #define SAMPLING_RATE_96KHZ 96000
  49. #define SAMPLING_RATE_176P4KHZ 176400
  50. #define SAMPLING_RATE_192KHZ 192000
  51. #define SAMPLING_RATE_352P8KHZ 352800
  52. #define SAMPLING_RATE_384KHZ 384000
  53. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  54. #define TLMM_EAST_SPARE 0x07BA0000
  55. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 4
  60. #define TDM_CHANNEL_MAX 8
  61. #define BT_SLIM_TX SLIM_TX_9
  62. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  63. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  64. enum {
  65. SLIM_RX_0 = 0,
  66. SLIM_RX_1,
  67. SLIM_RX_2,
  68. SLIM_RX_3,
  69. SLIM_RX_4,
  70. SLIM_RX_5,
  71. SLIM_RX_6,
  72. SLIM_RX_7,
  73. SLIM_RX_MAX,
  74. };
  75. enum {
  76. SLIM_TX_0 = 0,
  77. SLIM_TX_1,
  78. SLIM_TX_2,
  79. SLIM_TX_3,
  80. SLIM_TX_4,
  81. SLIM_TX_5,
  82. SLIM_TX_6,
  83. SLIM_TX_7,
  84. SLIM_TX_8,
  85. SLIM_TX_9,
  86. SLIM_TX_MAX,
  87. };
  88. enum {
  89. PRIM_MI2S = 0,
  90. SEC_MI2S,
  91. TERT_MI2S,
  92. QUAT_MI2S,
  93. QUIN_MI2S,
  94. SEN_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. PRIM_AUX_PCM = 0,
  99. SEC_AUX_PCM,
  100. TERT_AUX_PCM,
  101. QUAT_AUX_PCM,
  102. QUIN_AUX_PCM,
  103. SEN_AUX_PCM,
  104. AUX_PCM_MAX,
  105. };
  106. enum {
  107. WSA_CDC_DMA_RX_0 = 0,
  108. WSA_CDC_DMA_RX_1,
  109. CDC_DMA_RX_MAX,
  110. };
  111. enum {
  112. WSA_CDC_DMA_TX_0 = 0,
  113. WSA_CDC_DMA_TX_1,
  114. WSA_CDC_DMA_TX_2,
  115. VA_CDC_DMA_TX_0,
  116. VA_CDC_DMA_TX_1,
  117. CDC_DMA_TX_MAX,
  118. };
  119. enum {
  120. PRIM_SPDIF_RX = 0,
  121. SEC_SPDIF_RX,
  122. SPDIF_RX_MAX,
  123. };
  124. enum {
  125. PRIM_SPDIF_TX = 0,
  126. SEC_SPDIF_TX,
  127. SPDIF_TX_MAX,
  128. };
  129. struct mi2s_conf {
  130. struct mutex lock;
  131. u32 ref_cnt;
  132. u32 msm_is_mi2s_master;
  133. };
  134. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  135. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  136. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  137. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  138. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  141. };
  142. struct dev_config {
  143. u32 sample_rate;
  144. u32 bit_format;
  145. u32 channels;
  146. };
  147. struct msm_wsa881x_dev_info {
  148. struct device_node *of_node;
  149. u32 index;
  150. };
  151. struct msm_csra66x0_dev_info {
  152. struct device_node *of_node;
  153. u32 index;
  154. };
  155. struct msm_asoc_mach_data {
  156. struct snd_info_entry *codec_root;
  157. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  161. struct device_node *lineout_booster_gpio_p; /* used by pinctrl API */
  162. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  163. int dmic_01_gpio_cnt;
  164. int dmic_23_gpio_cnt;
  165. int dmic_45_gpio_cnt;
  166. int dmic_67_gpio_cnt;
  167. struct regulator *tdm_micb_supply;
  168. u32 tdm_micb_voltage;
  169. u32 tdm_micb_current;
  170. bool codec_is_csra;
  171. };
  172. struct msm_asoc_wcd93xx_codec {
  173. void* (*get_afe_config_fn)(struct snd_soc_component *component,
  174. enum afe_config_type config_type);
  175. };
  176. static const char *const pin_states[] = {"sleep", "i2s-active",
  177. "tdm-active"};
  178. enum {
  179. TDM_0 = 0,
  180. TDM_1,
  181. TDM_2,
  182. TDM_3,
  183. TDM_4,
  184. TDM_5,
  185. TDM_6,
  186. TDM_7,
  187. TDM_PORT_MAX,
  188. };
  189. enum {
  190. TDM_PRI = 0,
  191. TDM_SEC,
  192. TDM_TERT,
  193. TDM_QUAT,
  194. TDM_QUIN,
  195. TDM_INTERFACE_MAX,
  196. };
  197. struct tdm_port {
  198. u32 mode;
  199. u32 channel;
  200. };
  201. /* TDM default config */
  202. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  203. { /* PRI TDM */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  212. },
  213. { /* SEC TDM */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  222. },
  223. { /* TERT TDM */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  232. },
  233. { /* QUAT TDM */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  242. },
  243. { /* QUIN TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  252. }
  253. };
  254. /* TDM default config */
  255. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  256. { /* PRI TDM */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  265. },
  266. { /* SEC TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  275. },
  276. { /* TERT TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  285. },
  286. { /* QUAT TDM */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  295. },
  296. { /* QUIN TDM */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  305. }
  306. };
  307. /* Default configuration of slimbus channels */
  308. static struct dev_config slim_rx_cfg[] = {
  309. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. };
  318. static struct dev_config slim_tx_cfg[] = {
  319. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  328. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. };
  330. /* Default configuration of Codec DMA Interface Tx */
  331. static struct dev_config cdc_dma_rx_cfg[] = {
  332. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. };
  335. /* Default configuration of Codec DMA Interface Rx */
  336. static struct dev_config cdc_dma_tx_cfg[] = {
  337. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  339. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  340. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  341. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  342. };
  343. static struct dev_config usb_rx_cfg = {
  344. .sample_rate = SAMPLING_RATE_48KHZ,
  345. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  346. .channels = 2,
  347. };
  348. static struct dev_config usb_tx_cfg = {
  349. .sample_rate = SAMPLING_RATE_48KHZ,
  350. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  351. .channels = 1,
  352. };
  353. static struct dev_config proxy_rx_cfg = {
  354. .sample_rate = SAMPLING_RATE_48KHZ,
  355. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  356. .channels = 2,
  357. };
  358. /* Default configuration of MI2S channels */
  359. static struct dev_config mi2s_rx_cfg[] = {
  360. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  361. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  362. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  363. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  364. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  365. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  366. };
  367. /* Default configuration of SPDIF channels */
  368. static struct dev_config spdif_rx_cfg[] = {
  369. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. };
  372. static struct dev_config spdif_tx_cfg[] = {
  373. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  375. };
  376. static struct dev_config mi2s_tx_cfg[] = {
  377. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  381. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  382. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  383. };
  384. static struct dev_config aux_pcm_rx_cfg[] = {
  385. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  391. };
  392. static struct dev_config aux_pcm_tx_cfg[] = {
  393. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. };
  400. static int msm_vi_feed_tx_ch = 2;
  401. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  402. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  403. "Five", "Six", "Seven",
  404. "Eight"};
  405. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  406. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  407. "S32_LE"};
  408. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  409. "KHZ_32", "KHZ_44P1", "KHZ_48",
  410. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  411. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  412. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  413. "KHZ_44P1", "KHZ_48",
  414. "KHZ_88P2", "KHZ_96"};
  415. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  416. "Five", "Six", "Seven",
  417. "Eight"};
  418. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  419. "Six", "Seven", "Eight"};
  420. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  421. "KHZ_16", "KHZ_22P05",
  422. "KHZ_32", "KHZ_44P1", "KHZ_48",
  423. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  424. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  425. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  426. "Five", "Six", "Seven", "Eight"};
  427. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  428. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  429. "KHZ_48", "KHZ_176P4",
  430. "KHZ_352P8"};
  431. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  432. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  433. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  434. "KHZ_48", "KHZ_96", "KHZ_192", "KHZ_384"};
  435. static const char *const mi2s_ch_text[] = {
  436. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  437. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  438. "Fourteen", "Fifteen", "Sixteen"
  439. };
  440. static const char *const qos_text[] = {"Disable", "Enable"};
  441. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  442. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  443. "Five", "Six", "Seven",
  444. "Eight"};
  445. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  446. "KHZ_16", "KHZ_22P05",
  447. "KHZ_32", "KHZ_44P1", "KHZ_48",
  448. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  449. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  450. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  451. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  452. "KHZ_192"};
  453. static const char *spdif_ch_text[] = {"One", "Two"};
  454. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  455. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  540. cdc_dma_sample_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  542. cdc_dma_sample_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  544. cdc_dma_sample_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  546. cdc_dma_sample_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  548. cdc_dma_sample_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  550. cdc_dma_sample_rate_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  552. cdc_dma_sample_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  559. static struct platform_device *spdev;
  560. static bool is_initial_boot;
  561. static bool codec_reg_done;
  562. static struct snd_soc_aux_dev *msm_aux_dev;
  563. static struct snd_soc_codec_conf *msm_codec_conf;
  564. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  565. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  566. int enable, bool dapm);
  567. static int msm_wsa881x_init(struct snd_soc_component *component);
  568. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  569. struct snd_ctl_elem_value *ucontrol);
  570. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  571. {"MIC BIAS1", NULL, "MCLK TX"},
  572. {"MIC BIAS2", NULL, "MCLK TX"},
  573. {"MIC BIAS3", NULL, "MCLK TX"},
  574. {"MIC BIAS4", NULL, "MCLK TX"},
  575. };
  576. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  577. {
  578. AFE_API_VERSION_I2S_CONFIG,
  579. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  580. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  581. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  582. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  583. 0,
  584. },
  585. {
  586. AFE_API_VERSION_I2S_CONFIG,
  587. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  588. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  589. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  590. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  591. 0,
  592. },
  593. {
  594. AFE_API_VERSION_I2S_CONFIG,
  595. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  596. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  597. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  598. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  599. 0,
  600. },
  601. {
  602. AFE_API_VERSION_I2S_CONFIG,
  603. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  604. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  605. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  606. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  607. 0,
  608. },
  609. {
  610. AFE_API_VERSION_I2S_CONFIG,
  611. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  612. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  613. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  614. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  615. 0,
  616. },
  617. {
  618. AFE_API_VERSION_I2S_CONFIG,
  619. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  620. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  621. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  622. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  623. 0,
  624. }
  625. };
  626. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  627. static int msm_island_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  628. {
  629. *port_id = 0xFFFF;
  630. switch (be_id) {
  631. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  632. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  633. break;
  634. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  635. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  636. break;
  637. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  638. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  639. break;
  640. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  641. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  642. break;
  643. default:
  644. return -EINVAL;
  645. }
  646. return 0;
  647. }
  648. static int qcs405_send_island_vad_config(int32_t be_id)
  649. {
  650. int rc = 0;
  651. int port_id = 0xFFFF;
  652. rc = msm_island_vad_get_portid_from_beid(be_id, &port_id);
  653. if (rc) {
  654. pr_debug("%s: Invalid island interface\n", __func__);
  655. } else {
  656. /*
  657. * send island mode config
  658. * This should be the first configuration
  659. */
  660. rc = afe_send_port_island_mode(port_id);
  661. if (rc) {
  662. pr_err("%s: afe send island mode failed %d\n",
  663. __func__, rc);
  664. return rc;
  665. }
  666. rc = afe_send_port_vad_cfg_params(port_id);
  667. if (rc) {
  668. pr_err("%s: afe send vad config failed %d\n",
  669. __func__, rc);
  670. return rc;
  671. }
  672. }
  673. return 0;
  674. }
  675. static int slim_get_sample_rate_val(int sample_rate)
  676. {
  677. int sample_rate_val = 0;
  678. switch (sample_rate) {
  679. case SAMPLING_RATE_8KHZ:
  680. sample_rate_val = 0;
  681. break;
  682. case SAMPLING_RATE_16KHZ:
  683. sample_rate_val = 1;
  684. break;
  685. case SAMPLING_RATE_32KHZ:
  686. sample_rate_val = 2;
  687. break;
  688. case SAMPLING_RATE_44P1KHZ:
  689. sample_rate_val = 3;
  690. break;
  691. case SAMPLING_RATE_48KHZ:
  692. sample_rate_val = 4;
  693. break;
  694. case SAMPLING_RATE_88P2KHZ:
  695. sample_rate_val = 5;
  696. break;
  697. case SAMPLING_RATE_96KHZ:
  698. sample_rate_val = 6;
  699. break;
  700. case SAMPLING_RATE_176P4KHZ:
  701. sample_rate_val = 7;
  702. break;
  703. case SAMPLING_RATE_192KHZ:
  704. sample_rate_val = 8;
  705. break;
  706. case SAMPLING_RATE_352P8KHZ:
  707. sample_rate_val = 9;
  708. break;
  709. case SAMPLING_RATE_384KHZ:
  710. sample_rate_val = 10;
  711. break;
  712. default:
  713. sample_rate_val = 4;
  714. break;
  715. }
  716. return sample_rate_val;
  717. }
  718. static int slim_get_sample_rate(int value)
  719. {
  720. int sample_rate = 0;
  721. switch (value) {
  722. case 0:
  723. sample_rate = SAMPLING_RATE_8KHZ;
  724. break;
  725. case 1:
  726. sample_rate = SAMPLING_RATE_16KHZ;
  727. break;
  728. case 2:
  729. sample_rate = SAMPLING_RATE_32KHZ;
  730. break;
  731. case 3:
  732. sample_rate = SAMPLING_RATE_44P1KHZ;
  733. break;
  734. case 4:
  735. sample_rate = SAMPLING_RATE_48KHZ;
  736. break;
  737. case 5:
  738. sample_rate = SAMPLING_RATE_88P2KHZ;
  739. break;
  740. case 6:
  741. sample_rate = SAMPLING_RATE_96KHZ;
  742. break;
  743. case 7:
  744. sample_rate = SAMPLING_RATE_176P4KHZ;
  745. break;
  746. case 8:
  747. sample_rate = SAMPLING_RATE_192KHZ;
  748. break;
  749. case 9:
  750. sample_rate = SAMPLING_RATE_352P8KHZ;
  751. break;
  752. case 10:
  753. sample_rate = SAMPLING_RATE_384KHZ;
  754. break;
  755. default:
  756. sample_rate = SAMPLING_RATE_48KHZ;
  757. break;
  758. }
  759. return sample_rate;
  760. }
  761. static int slim_get_bit_format_val(int bit_format)
  762. {
  763. int val = 0;
  764. switch (bit_format) {
  765. case SNDRV_PCM_FORMAT_S32_LE:
  766. val = 3;
  767. break;
  768. case SNDRV_PCM_FORMAT_S24_3LE:
  769. val = 2;
  770. break;
  771. case SNDRV_PCM_FORMAT_S24_LE:
  772. val = 1;
  773. break;
  774. case SNDRV_PCM_FORMAT_S16_LE:
  775. default:
  776. val = 0;
  777. break;
  778. }
  779. return val;
  780. }
  781. static int slim_get_bit_format(int val)
  782. {
  783. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  784. switch (val) {
  785. case 0:
  786. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  787. break;
  788. case 1:
  789. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  790. break;
  791. case 2:
  792. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  793. break;
  794. case 3:
  795. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  796. break;
  797. default:
  798. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  799. break;
  800. }
  801. return bit_fmt;
  802. }
  803. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  804. {
  805. int port_id = 0;
  806. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  807. port_id = SLIM_RX_0;
  808. } else if (strnstr(kcontrol->id.name,
  809. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  810. port_id = SLIM_RX_2;
  811. } else if (strnstr(kcontrol->id.name,
  812. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  813. port_id = SLIM_RX_5;
  814. } else if (strnstr(kcontrol->id.name,
  815. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  816. port_id = SLIM_RX_6;
  817. } else if (strnstr(kcontrol->id.name,
  818. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  819. port_id = SLIM_TX_0;
  820. } else if (strnstr(kcontrol->id.name,
  821. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  822. port_id = SLIM_TX_1;
  823. } else {
  824. pr_err("%s: unsupported channel: %s",
  825. __func__, kcontrol->id.name);
  826. return -EINVAL;
  827. }
  828. return port_id;
  829. }
  830. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  831. struct snd_ctl_elem_value *ucontrol)
  832. {
  833. int ch_num = slim_get_port_idx(kcontrol);
  834. if (ch_num < 0)
  835. return ch_num;
  836. ucontrol->value.enumerated.item[0] =
  837. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  838. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  839. ch_num, slim_rx_cfg[ch_num].sample_rate,
  840. ucontrol->value.enumerated.item[0]);
  841. return 0;
  842. }
  843. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  844. struct snd_ctl_elem_value *ucontrol)
  845. {
  846. int ch_num = slim_get_port_idx(kcontrol);
  847. if (ch_num < 0)
  848. return ch_num;
  849. slim_rx_cfg[ch_num].sample_rate =
  850. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  851. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  852. ch_num, slim_rx_cfg[ch_num].sample_rate,
  853. ucontrol->value.enumerated.item[0]);
  854. return 0;
  855. }
  856. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  857. struct snd_ctl_elem_value *ucontrol)
  858. {
  859. int ch_num = slim_get_port_idx(kcontrol);
  860. if (ch_num < 0)
  861. return ch_num;
  862. ucontrol->value.enumerated.item[0] =
  863. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  864. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  865. ch_num, slim_tx_cfg[ch_num].sample_rate,
  866. ucontrol->value.enumerated.item[0]);
  867. return 0;
  868. }
  869. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  870. struct snd_ctl_elem_value *ucontrol)
  871. {
  872. int sample_rate = 0;
  873. int ch_num = slim_get_port_idx(kcontrol);
  874. if (ch_num < 0)
  875. return ch_num;
  876. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  877. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  878. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  879. __func__, sample_rate);
  880. return -EINVAL;
  881. }
  882. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  883. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  884. ch_num, slim_tx_cfg[ch_num].sample_rate,
  885. ucontrol->value.enumerated.item[0]);
  886. return 0;
  887. }
  888. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  889. struct snd_ctl_elem_value *ucontrol)
  890. {
  891. int ch_num = slim_get_port_idx(kcontrol);
  892. if (ch_num < 0)
  893. return ch_num;
  894. ucontrol->value.enumerated.item[0] =
  895. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  896. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  897. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  898. ucontrol->value.enumerated.item[0]);
  899. return 0;
  900. }
  901. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  902. struct snd_ctl_elem_value *ucontrol)
  903. {
  904. int ch_num = slim_get_port_idx(kcontrol);
  905. if (ch_num < 0)
  906. return ch_num;
  907. slim_rx_cfg[ch_num].bit_format =
  908. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  909. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  910. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  911. ucontrol->value.enumerated.item[0]);
  912. return 0;
  913. }
  914. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  915. struct snd_ctl_elem_value *ucontrol)
  916. {
  917. int ch_num = slim_get_port_idx(kcontrol);
  918. if (ch_num < 0)
  919. return ch_num;
  920. ucontrol->value.enumerated.item[0] =
  921. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  922. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  923. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  924. ucontrol->value.enumerated.item[0]);
  925. return 0;
  926. }
  927. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  928. struct snd_ctl_elem_value *ucontrol)
  929. {
  930. int ch_num = slim_get_port_idx(kcontrol);
  931. if (ch_num < 0)
  932. return ch_num;
  933. slim_tx_cfg[ch_num].bit_format =
  934. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  935. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  936. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  937. ucontrol->value.enumerated.item[0]);
  938. return 0;
  939. }
  940. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  941. struct snd_ctl_elem_value *ucontrol)
  942. {
  943. int ch_num = slim_get_port_idx(kcontrol);
  944. if (ch_num < 0)
  945. return ch_num;
  946. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  947. ch_num, slim_rx_cfg[ch_num].channels);
  948. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  949. return 0;
  950. }
  951. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  952. struct snd_ctl_elem_value *ucontrol)
  953. {
  954. int ch_num = slim_get_port_idx(kcontrol);
  955. if (ch_num < 0)
  956. return ch_num;
  957. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  958. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  959. ch_num, slim_rx_cfg[ch_num].channels);
  960. return 1;
  961. }
  962. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  963. struct snd_ctl_elem_value *ucontrol)
  964. {
  965. int ch_num = slim_get_port_idx(kcontrol);
  966. if (ch_num < 0)
  967. return ch_num;
  968. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  969. ch_num, slim_tx_cfg[ch_num].channels);
  970. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  971. return 0;
  972. }
  973. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  974. struct snd_ctl_elem_value *ucontrol)
  975. {
  976. int ch_num = slim_get_port_idx(kcontrol);
  977. if (ch_num < 0)
  978. return ch_num;
  979. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  980. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  981. ch_num, slim_tx_cfg[ch_num].channels);
  982. return 1;
  983. }
  984. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  985. struct snd_ctl_elem_value *ucontrol)
  986. {
  987. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  988. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  989. ucontrol->value.integer.value[0]);
  990. return 0;
  991. }
  992. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  993. struct snd_ctl_elem_value *ucontrol)
  994. {
  995. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  996. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  997. return 1;
  998. }
  999. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  1000. struct snd_ctl_elem_value *ucontrol)
  1001. {
  1002. /*
  1003. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  1004. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  1005. * value.
  1006. */
  1007. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  1008. case SAMPLING_RATE_96KHZ:
  1009. ucontrol->value.integer.value[0] = 5;
  1010. break;
  1011. case SAMPLING_RATE_88P2KHZ:
  1012. ucontrol->value.integer.value[0] = 4;
  1013. break;
  1014. case SAMPLING_RATE_48KHZ:
  1015. ucontrol->value.integer.value[0] = 3;
  1016. break;
  1017. case SAMPLING_RATE_44P1KHZ:
  1018. ucontrol->value.integer.value[0] = 2;
  1019. break;
  1020. case SAMPLING_RATE_16KHZ:
  1021. ucontrol->value.integer.value[0] = 1;
  1022. break;
  1023. case SAMPLING_RATE_8KHZ:
  1024. default:
  1025. ucontrol->value.integer.value[0] = 0;
  1026. break;
  1027. }
  1028. pr_debug("%s: sample rate = %d", __func__,
  1029. slim_rx_cfg[SLIM_RX_7].sample_rate);
  1030. return 0;
  1031. }
  1032. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  1033. struct snd_ctl_elem_value *ucontrol)
  1034. {
  1035. switch (ucontrol->value.integer.value[0]) {
  1036. case 1:
  1037. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1038. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1039. break;
  1040. case 2:
  1041. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1042. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1043. break;
  1044. case 3:
  1045. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1046. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1047. break;
  1048. case 4:
  1049. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1050. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1051. break;
  1052. case 5:
  1053. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1054. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1055. break;
  1056. case 0:
  1057. default:
  1058. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1059. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1060. break;
  1061. }
  1062. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1063. __func__,
  1064. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1065. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1066. ucontrol->value.enumerated.item[0]);
  1067. return 0;
  1068. }
  1069. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1070. struct snd_ctl_elem_value *ucontrol)
  1071. {
  1072. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1073. case SAMPLING_RATE_96KHZ:
  1074. ucontrol->value.integer.value[0] = 5;
  1075. break;
  1076. case SAMPLING_RATE_88P2KHZ:
  1077. ucontrol->value.integer.value[0] = 4;
  1078. break;
  1079. case SAMPLING_RATE_48KHZ:
  1080. ucontrol->value.integer.value[0] = 3;
  1081. break;
  1082. case SAMPLING_RATE_44P1KHZ:
  1083. ucontrol->value.integer.value[0] = 2;
  1084. break;
  1085. case SAMPLING_RATE_16KHZ:
  1086. ucontrol->value.integer.value[0] = 1;
  1087. break;
  1088. case SAMPLING_RATE_8KHZ:
  1089. default:
  1090. ucontrol->value.integer.value[0] = 0;
  1091. break;
  1092. }
  1093. pr_debug("%s: sample rate = %d", __func__,
  1094. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1095. return 0;
  1096. }
  1097. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1098. struct snd_ctl_elem_value *ucontrol)
  1099. {
  1100. switch (ucontrol->value.integer.value[0]) {
  1101. case 1:
  1102. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1103. break;
  1104. case 2:
  1105. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1106. break;
  1107. case 3:
  1108. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1109. break;
  1110. case 4:
  1111. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1112. break;
  1113. case 5:
  1114. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1115. break;
  1116. case 0:
  1117. default:
  1118. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1119. break;
  1120. }
  1121. pr_debug("%s: sample rate = %d, value = %d\n",
  1122. __func__,
  1123. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1124. ucontrol->value.enumerated.item[0]);
  1125. return 0;
  1126. }
  1127. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1128. {
  1129. int idx = 0;
  1130. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1131. sizeof("WSA_CDC_DMA_RX_0")))
  1132. idx = WSA_CDC_DMA_RX_0;
  1133. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1134. sizeof("WSA_CDC_DMA_RX_0")))
  1135. idx = WSA_CDC_DMA_RX_1;
  1136. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1137. sizeof("WSA_CDC_DMA_TX_0")))
  1138. idx = WSA_CDC_DMA_TX_0;
  1139. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1140. sizeof("WSA_CDC_DMA_TX_1")))
  1141. idx = WSA_CDC_DMA_TX_1;
  1142. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1143. sizeof("WSA_CDC_DMA_TX_2")))
  1144. idx = WSA_CDC_DMA_TX_2;
  1145. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1146. sizeof("VA_CDC_DMA_TX_0")))
  1147. idx = VA_CDC_DMA_TX_0;
  1148. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1149. sizeof("VA_CDC_DMA_TX_1")))
  1150. idx = VA_CDC_DMA_TX_1;
  1151. else {
  1152. pr_err("%s: unsupported port: %s\n",
  1153. __func__, kcontrol->id.name);
  1154. return -EINVAL;
  1155. }
  1156. return idx;
  1157. }
  1158. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1159. struct snd_ctl_elem_value *ucontrol)
  1160. {
  1161. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1162. if (ch_num < 0)
  1163. return ch_num;
  1164. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1165. cdc_dma_rx_cfg[ch_num].channels - 1);
  1166. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1167. return 0;
  1168. }
  1169. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1170. struct snd_ctl_elem_value *ucontrol)
  1171. {
  1172. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1173. if (ch_num < 0)
  1174. return ch_num;
  1175. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1176. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1177. cdc_dma_rx_cfg[ch_num].channels);
  1178. return 1;
  1179. }
  1180. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1181. struct snd_ctl_elem_value *ucontrol)
  1182. {
  1183. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1184. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1185. case SNDRV_PCM_FORMAT_S32_LE:
  1186. ucontrol->value.integer.value[0] = 3;
  1187. break;
  1188. case SNDRV_PCM_FORMAT_S24_3LE:
  1189. ucontrol->value.integer.value[0] = 2;
  1190. break;
  1191. case SNDRV_PCM_FORMAT_S24_LE:
  1192. ucontrol->value.integer.value[0] = 1;
  1193. break;
  1194. case SNDRV_PCM_FORMAT_S16_LE:
  1195. default:
  1196. ucontrol->value.integer.value[0] = 0;
  1197. break;
  1198. }
  1199. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1200. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1201. ucontrol->value.integer.value[0]);
  1202. return 0;
  1203. }
  1204. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1205. struct snd_ctl_elem_value *ucontrol)
  1206. {
  1207. int rc = 0;
  1208. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1209. switch (ucontrol->value.integer.value[0]) {
  1210. case 3:
  1211. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1212. break;
  1213. case 2:
  1214. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1215. break;
  1216. case 1:
  1217. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1218. break;
  1219. case 0:
  1220. default:
  1221. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1222. break;
  1223. }
  1224. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1225. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1226. ucontrol->value.integer.value[0]);
  1227. return rc;
  1228. }
  1229. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1230. {
  1231. int sample_rate_val = 0;
  1232. switch (sample_rate) {
  1233. case SAMPLING_RATE_8KHZ:
  1234. sample_rate_val = 0;
  1235. break;
  1236. case SAMPLING_RATE_11P025KHZ:
  1237. sample_rate_val = 1;
  1238. break;
  1239. case SAMPLING_RATE_16KHZ:
  1240. sample_rate_val = 2;
  1241. break;
  1242. case SAMPLING_RATE_22P05KHZ:
  1243. sample_rate_val = 3;
  1244. break;
  1245. case SAMPLING_RATE_32KHZ:
  1246. sample_rate_val = 4;
  1247. break;
  1248. case SAMPLING_RATE_44P1KHZ:
  1249. sample_rate_val = 5;
  1250. break;
  1251. case SAMPLING_RATE_48KHZ:
  1252. sample_rate_val = 6;
  1253. break;
  1254. case SAMPLING_RATE_88P2KHZ:
  1255. sample_rate_val = 7;
  1256. break;
  1257. case SAMPLING_RATE_96KHZ:
  1258. sample_rate_val = 8;
  1259. break;
  1260. case SAMPLING_RATE_176P4KHZ:
  1261. sample_rate_val = 9;
  1262. break;
  1263. case SAMPLING_RATE_192KHZ:
  1264. sample_rate_val = 10;
  1265. break;
  1266. case SAMPLING_RATE_352P8KHZ:
  1267. sample_rate_val = 11;
  1268. break;
  1269. case SAMPLING_RATE_384KHZ:
  1270. sample_rate_val = 12;
  1271. break;
  1272. default:
  1273. sample_rate_val = 6;
  1274. break;
  1275. }
  1276. return sample_rate_val;
  1277. }
  1278. static int cdc_dma_get_sample_rate(int value)
  1279. {
  1280. int sample_rate = 0;
  1281. switch (value) {
  1282. case 0:
  1283. sample_rate = SAMPLING_RATE_8KHZ;
  1284. break;
  1285. case 1:
  1286. sample_rate = SAMPLING_RATE_11P025KHZ;
  1287. break;
  1288. case 2:
  1289. sample_rate = SAMPLING_RATE_16KHZ;
  1290. break;
  1291. case 3:
  1292. sample_rate = SAMPLING_RATE_22P05KHZ;
  1293. break;
  1294. case 4:
  1295. sample_rate = SAMPLING_RATE_32KHZ;
  1296. break;
  1297. case 5:
  1298. sample_rate = SAMPLING_RATE_44P1KHZ;
  1299. break;
  1300. case 6:
  1301. sample_rate = SAMPLING_RATE_48KHZ;
  1302. break;
  1303. case 7:
  1304. sample_rate = SAMPLING_RATE_88P2KHZ;
  1305. break;
  1306. case 8:
  1307. sample_rate = SAMPLING_RATE_96KHZ;
  1308. break;
  1309. case 9:
  1310. sample_rate = SAMPLING_RATE_176P4KHZ;
  1311. break;
  1312. case 10:
  1313. sample_rate = SAMPLING_RATE_192KHZ;
  1314. break;
  1315. case 11:
  1316. sample_rate = SAMPLING_RATE_352P8KHZ;
  1317. break;
  1318. case 12:
  1319. sample_rate = SAMPLING_RATE_384KHZ;
  1320. break;
  1321. default:
  1322. sample_rate = SAMPLING_RATE_48KHZ;
  1323. break;
  1324. }
  1325. return sample_rate;
  1326. }
  1327. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1328. struct snd_ctl_elem_value *ucontrol)
  1329. {
  1330. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1331. if (ch_num < 0)
  1332. return ch_num;
  1333. ucontrol->value.enumerated.item[0] =
  1334. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1335. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1336. cdc_dma_rx_cfg[ch_num].sample_rate);
  1337. return 0;
  1338. }
  1339. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1340. struct snd_ctl_elem_value *ucontrol)
  1341. {
  1342. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1343. if (ch_num < 0)
  1344. return ch_num;
  1345. cdc_dma_rx_cfg[ch_num].sample_rate =
  1346. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1347. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1348. __func__, ucontrol->value.enumerated.item[0],
  1349. cdc_dma_rx_cfg[ch_num].sample_rate);
  1350. return 0;
  1351. }
  1352. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1353. struct snd_ctl_elem_value *ucontrol)
  1354. {
  1355. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1356. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1357. cdc_dma_tx_cfg[ch_num].channels);
  1358. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1359. return 0;
  1360. }
  1361. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1362. struct snd_ctl_elem_value *ucontrol)
  1363. {
  1364. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1365. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1366. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1367. cdc_dma_tx_cfg[ch_num].channels);
  1368. return 1;
  1369. }
  1370. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1371. struct snd_ctl_elem_value *ucontrol)
  1372. {
  1373. int sample_rate_val;
  1374. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1375. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1376. case SAMPLING_RATE_384KHZ:
  1377. sample_rate_val = 12;
  1378. break;
  1379. case SAMPLING_RATE_352P8KHZ:
  1380. sample_rate_val = 11;
  1381. break;
  1382. case SAMPLING_RATE_192KHZ:
  1383. sample_rate_val = 10;
  1384. break;
  1385. case SAMPLING_RATE_176P4KHZ:
  1386. sample_rate_val = 9;
  1387. break;
  1388. case SAMPLING_RATE_96KHZ:
  1389. sample_rate_val = 8;
  1390. break;
  1391. case SAMPLING_RATE_88P2KHZ:
  1392. sample_rate_val = 7;
  1393. break;
  1394. case SAMPLING_RATE_48KHZ:
  1395. sample_rate_val = 6;
  1396. break;
  1397. case SAMPLING_RATE_44P1KHZ:
  1398. sample_rate_val = 5;
  1399. break;
  1400. case SAMPLING_RATE_32KHZ:
  1401. sample_rate_val = 4;
  1402. break;
  1403. case SAMPLING_RATE_22P05KHZ:
  1404. sample_rate_val = 3;
  1405. break;
  1406. case SAMPLING_RATE_16KHZ:
  1407. sample_rate_val = 2;
  1408. break;
  1409. case SAMPLING_RATE_11P025KHZ:
  1410. sample_rate_val = 1;
  1411. break;
  1412. case SAMPLING_RATE_8KHZ:
  1413. sample_rate_val = 0;
  1414. break;
  1415. default:
  1416. sample_rate_val = 6;
  1417. break;
  1418. }
  1419. ucontrol->value.integer.value[0] = sample_rate_val;
  1420. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1421. cdc_dma_tx_cfg[ch_num].sample_rate);
  1422. return 0;
  1423. }
  1424. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1425. struct snd_ctl_elem_value *ucontrol)
  1426. {
  1427. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1428. switch (ucontrol->value.integer.value[0]) {
  1429. case 12:
  1430. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1431. break;
  1432. case 11:
  1433. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1434. break;
  1435. case 10:
  1436. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1437. break;
  1438. case 9:
  1439. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1440. break;
  1441. case 8:
  1442. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1443. break;
  1444. case 7:
  1445. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1446. break;
  1447. case 6:
  1448. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1449. break;
  1450. case 5:
  1451. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1452. break;
  1453. case 4:
  1454. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1455. break;
  1456. case 3:
  1457. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1458. break;
  1459. case 2:
  1460. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1461. break;
  1462. case 1:
  1463. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1464. break;
  1465. case 0:
  1466. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1467. break;
  1468. default:
  1469. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1470. break;
  1471. }
  1472. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1473. __func__, ucontrol->value.integer.value[0],
  1474. cdc_dma_tx_cfg[ch_num].sample_rate);
  1475. return 0;
  1476. }
  1477. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1478. struct snd_ctl_elem_value *ucontrol)
  1479. {
  1480. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1481. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1482. case SNDRV_PCM_FORMAT_S32_LE:
  1483. ucontrol->value.integer.value[0] = 3;
  1484. break;
  1485. case SNDRV_PCM_FORMAT_S24_3LE:
  1486. ucontrol->value.integer.value[0] = 2;
  1487. break;
  1488. case SNDRV_PCM_FORMAT_S24_LE:
  1489. ucontrol->value.integer.value[0] = 1;
  1490. break;
  1491. case SNDRV_PCM_FORMAT_S16_LE:
  1492. default:
  1493. ucontrol->value.integer.value[0] = 0;
  1494. break;
  1495. }
  1496. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1497. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1498. ucontrol->value.integer.value[0]);
  1499. return 0;
  1500. }
  1501. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1502. struct snd_ctl_elem_value *ucontrol)
  1503. {
  1504. int rc = 0;
  1505. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1506. switch (ucontrol->value.integer.value[0]) {
  1507. case 3:
  1508. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1509. break;
  1510. case 2:
  1511. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1512. break;
  1513. case 1:
  1514. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1515. break;
  1516. case 0:
  1517. default:
  1518. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1519. break;
  1520. }
  1521. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1522. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1523. ucontrol->value.integer.value[0]);
  1524. return rc;
  1525. }
  1526. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1527. struct snd_ctl_elem_value *ucontrol)
  1528. {
  1529. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1530. usb_rx_cfg.channels);
  1531. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1532. return 0;
  1533. }
  1534. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1535. struct snd_ctl_elem_value *ucontrol)
  1536. {
  1537. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1538. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1539. return 1;
  1540. }
  1541. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1542. struct snd_ctl_elem_value *ucontrol)
  1543. {
  1544. int sample_rate_val;
  1545. switch (usb_rx_cfg.sample_rate) {
  1546. case SAMPLING_RATE_384KHZ:
  1547. sample_rate_val = 12;
  1548. break;
  1549. case SAMPLING_RATE_352P8KHZ:
  1550. sample_rate_val = 11;
  1551. break;
  1552. case SAMPLING_RATE_192KHZ:
  1553. sample_rate_val = 10;
  1554. break;
  1555. case SAMPLING_RATE_176P4KHZ:
  1556. sample_rate_val = 9;
  1557. break;
  1558. case SAMPLING_RATE_96KHZ:
  1559. sample_rate_val = 8;
  1560. break;
  1561. case SAMPLING_RATE_88P2KHZ:
  1562. sample_rate_val = 7;
  1563. break;
  1564. case SAMPLING_RATE_48KHZ:
  1565. sample_rate_val = 6;
  1566. break;
  1567. case SAMPLING_RATE_44P1KHZ:
  1568. sample_rate_val = 5;
  1569. break;
  1570. case SAMPLING_RATE_32KHZ:
  1571. sample_rate_val = 4;
  1572. break;
  1573. case SAMPLING_RATE_22P05KHZ:
  1574. sample_rate_val = 3;
  1575. break;
  1576. case SAMPLING_RATE_16KHZ:
  1577. sample_rate_val = 2;
  1578. break;
  1579. case SAMPLING_RATE_11P025KHZ:
  1580. sample_rate_val = 1;
  1581. break;
  1582. case SAMPLING_RATE_8KHZ:
  1583. default:
  1584. sample_rate_val = 0;
  1585. break;
  1586. }
  1587. ucontrol->value.integer.value[0] = sample_rate_val;
  1588. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1589. usb_rx_cfg.sample_rate);
  1590. return 0;
  1591. }
  1592. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1593. struct snd_ctl_elem_value *ucontrol)
  1594. {
  1595. switch (ucontrol->value.integer.value[0]) {
  1596. case 12:
  1597. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1598. break;
  1599. case 11:
  1600. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1601. break;
  1602. case 10:
  1603. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1604. break;
  1605. case 9:
  1606. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1607. break;
  1608. case 8:
  1609. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1610. break;
  1611. case 7:
  1612. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1613. break;
  1614. case 6:
  1615. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1616. break;
  1617. case 5:
  1618. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1619. break;
  1620. case 4:
  1621. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1622. break;
  1623. case 3:
  1624. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1625. break;
  1626. case 2:
  1627. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1628. break;
  1629. case 1:
  1630. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1631. break;
  1632. case 0:
  1633. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1634. break;
  1635. default:
  1636. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1637. break;
  1638. }
  1639. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1640. __func__, ucontrol->value.integer.value[0],
  1641. usb_rx_cfg.sample_rate);
  1642. return 0;
  1643. }
  1644. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1645. struct snd_ctl_elem_value *ucontrol)
  1646. {
  1647. switch (usb_rx_cfg.bit_format) {
  1648. case SNDRV_PCM_FORMAT_S32_LE:
  1649. ucontrol->value.integer.value[0] = 3;
  1650. break;
  1651. case SNDRV_PCM_FORMAT_S24_3LE:
  1652. ucontrol->value.integer.value[0] = 2;
  1653. break;
  1654. case SNDRV_PCM_FORMAT_S24_LE:
  1655. ucontrol->value.integer.value[0] = 1;
  1656. break;
  1657. case SNDRV_PCM_FORMAT_S16_LE:
  1658. default:
  1659. ucontrol->value.integer.value[0] = 0;
  1660. break;
  1661. }
  1662. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1663. __func__, usb_rx_cfg.bit_format,
  1664. ucontrol->value.integer.value[0]);
  1665. return 0;
  1666. }
  1667. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1668. struct snd_ctl_elem_value *ucontrol)
  1669. {
  1670. int rc = 0;
  1671. switch (ucontrol->value.integer.value[0]) {
  1672. case 3:
  1673. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1674. break;
  1675. case 2:
  1676. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1677. break;
  1678. case 1:
  1679. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1680. break;
  1681. case 0:
  1682. default:
  1683. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1684. break;
  1685. }
  1686. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1687. __func__, usb_rx_cfg.bit_format,
  1688. ucontrol->value.integer.value[0]);
  1689. return rc;
  1690. }
  1691. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1692. struct snd_ctl_elem_value *ucontrol)
  1693. {
  1694. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1695. usb_tx_cfg.channels);
  1696. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1697. return 0;
  1698. }
  1699. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1700. struct snd_ctl_elem_value *ucontrol)
  1701. {
  1702. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1703. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1704. return 1;
  1705. }
  1706. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1707. struct snd_ctl_elem_value *ucontrol)
  1708. {
  1709. int sample_rate_val;
  1710. switch (usb_tx_cfg.sample_rate) {
  1711. case SAMPLING_RATE_384KHZ:
  1712. sample_rate_val = 12;
  1713. break;
  1714. case SAMPLING_RATE_352P8KHZ:
  1715. sample_rate_val = 11;
  1716. break;
  1717. case SAMPLING_RATE_192KHZ:
  1718. sample_rate_val = 10;
  1719. break;
  1720. case SAMPLING_RATE_176P4KHZ:
  1721. sample_rate_val = 9;
  1722. break;
  1723. case SAMPLING_RATE_96KHZ:
  1724. sample_rate_val = 8;
  1725. break;
  1726. case SAMPLING_RATE_88P2KHZ:
  1727. sample_rate_val = 7;
  1728. break;
  1729. case SAMPLING_RATE_48KHZ:
  1730. sample_rate_val = 6;
  1731. break;
  1732. case SAMPLING_RATE_44P1KHZ:
  1733. sample_rate_val = 5;
  1734. break;
  1735. case SAMPLING_RATE_32KHZ:
  1736. sample_rate_val = 4;
  1737. break;
  1738. case SAMPLING_RATE_22P05KHZ:
  1739. sample_rate_val = 3;
  1740. break;
  1741. case SAMPLING_RATE_16KHZ:
  1742. sample_rate_val = 2;
  1743. break;
  1744. case SAMPLING_RATE_11P025KHZ:
  1745. sample_rate_val = 1;
  1746. break;
  1747. case SAMPLING_RATE_8KHZ:
  1748. sample_rate_val = 0;
  1749. break;
  1750. default:
  1751. sample_rate_val = 6;
  1752. break;
  1753. }
  1754. ucontrol->value.integer.value[0] = sample_rate_val;
  1755. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1756. usb_tx_cfg.sample_rate);
  1757. return 0;
  1758. }
  1759. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1760. struct snd_ctl_elem_value *ucontrol)
  1761. {
  1762. switch (ucontrol->value.integer.value[0]) {
  1763. case 12:
  1764. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1765. break;
  1766. case 11:
  1767. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1768. break;
  1769. case 10:
  1770. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1771. break;
  1772. case 9:
  1773. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1774. break;
  1775. case 8:
  1776. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1777. break;
  1778. case 7:
  1779. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1780. break;
  1781. case 6:
  1782. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1783. break;
  1784. case 5:
  1785. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1786. break;
  1787. case 4:
  1788. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1789. break;
  1790. case 3:
  1791. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1792. break;
  1793. case 2:
  1794. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1795. break;
  1796. case 1:
  1797. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1798. break;
  1799. case 0:
  1800. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1801. break;
  1802. default:
  1803. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1804. break;
  1805. }
  1806. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1807. __func__, ucontrol->value.integer.value[0],
  1808. usb_tx_cfg.sample_rate);
  1809. return 0;
  1810. }
  1811. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1812. struct snd_ctl_elem_value *ucontrol)
  1813. {
  1814. switch (usb_tx_cfg.bit_format) {
  1815. case SNDRV_PCM_FORMAT_S32_LE:
  1816. ucontrol->value.integer.value[0] = 3;
  1817. break;
  1818. case SNDRV_PCM_FORMAT_S24_3LE:
  1819. ucontrol->value.integer.value[0] = 2;
  1820. break;
  1821. case SNDRV_PCM_FORMAT_S24_LE:
  1822. ucontrol->value.integer.value[0] = 1;
  1823. break;
  1824. case SNDRV_PCM_FORMAT_S16_LE:
  1825. default:
  1826. ucontrol->value.integer.value[0] = 0;
  1827. break;
  1828. }
  1829. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1830. __func__, usb_tx_cfg.bit_format,
  1831. ucontrol->value.integer.value[0]);
  1832. return 0;
  1833. }
  1834. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1835. struct snd_ctl_elem_value *ucontrol)
  1836. {
  1837. int rc = 0;
  1838. switch (ucontrol->value.integer.value[0]) {
  1839. case 3:
  1840. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1841. break;
  1842. case 2:
  1843. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1844. break;
  1845. case 1:
  1846. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1847. break;
  1848. case 0:
  1849. default:
  1850. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1851. break;
  1852. }
  1853. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1854. __func__, usb_tx_cfg.bit_format,
  1855. ucontrol->value.integer.value[0]);
  1856. return rc;
  1857. }
  1858. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1859. struct snd_ctl_elem_value *ucontrol)
  1860. {
  1861. pr_debug("%s: proxy_rx channels = %d\n",
  1862. __func__, proxy_rx_cfg.channels);
  1863. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1864. return 0;
  1865. }
  1866. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1867. struct snd_ctl_elem_value *ucontrol)
  1868. {
  1869. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1870. pr_debug("%s: proxy_rx channels = %d\n",
  1871. __func__, proxy_rx_cfg.channels);
  1872. return 1;
  1873. }
  1874. static int tdm_get_sample_rate(int value)
  1875. {
  1876. int sample_rate = 0;
  1877. switch (value) {
  1878. case 0:
  1879. sample_rate = SAMPLING_RATE_8KHZ;
  1880. break;
  1881. case 1:
  1882. sample_rate = SAMPLING_RATE_16KHZ;
  1883. break;
  1884. case 2:
  1885. sample_rate = SAMPLING_RATE_32KHZ;
  1886. break;
  1887. case 3:
  1888. sample_rate = SAMPLING_RATE_48KHZ;
  1889. break;
  1890. case 4:
  1891. sample_rate = SAMPLING_RATE_176P4KHZ;
  1892. break;
  1893. case 5:
  1894. sample_rate = SAMPLING_RATE_352P8KHZ;
  1895. break;
  1896. default:
  1897. sample_rate = SAMPLING_RATE_48KHZ;
  1898. break;
  1899. }
  1900. return sample_rate;
  1901. }
  1902. static int aux_pcm_get_sample_rate(int value)
  1903. {
  1904. int sample_rate;
  1905. switch (value) {
  1906. case 1:
  1907. sample_rate = SAMPLING_RATE_16KHZ;
  1908. break;
  1909. case 0:
  1910. default:
  1911. sample_rate = SAMPLING_RATE_8KHZ;
  1912. break;
  1913. }
  1914. return sample_rate;
  1915. }
  1916. static int tdm_get_sample_rate_val(int sample_rate)
  1917. {
  1918. int sample_rate_val = 0;
  1919. switch (sample_rate) {
  1920. case SAMPLING_RATE_8KHZ:
  1921. sample_rate_val = 0;
  1922. break;
  1923. case SAMPLING_RATE_16KHZ:
  1924. sample_rate_val = 1;
  1925. break;
  1926. case SAMPLING_RATE_32KHZ:
  1927. sample_rate_val = 2;
  1928. break;
  1929. case SAMPLING_RATE_48KHZ:
  1930. sample_rate_val = 3;
  1931. break;
  1932. case SAMPLING_RATE_176P4KHZ:
  1933. sample_rate_val = 4;
  1934. break;
  1935. case SAMPLING_RATE_352P8KHZ:
  1936. sample_rate_val = 5;
  1937. break;
  1938. default:
  1939. sample_rate_val = 3;
  1940. break;
  1941. }
  1942. return sample_rate_val;
  1943. }
  1944. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1945. {
  1946. int sample_rate_val;
  1947. switch (sample_rate) {
  1948. case SAMPLING_RATE_16KHZ:
  1949. sample_rate_val = 1;
  1950. break;
  1951. case SAMPLING_RATE_8KHZ:
  1952. default:
  1953. sample_rate_val = 0;
  1954. break;
  1955. }
  1956. return sample_rate_val;
  1957. }
  1958. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1959. struct tdm_port *port)
  1960. {
  1961. if (port) {
  1962. if (strnstr(kcontrol->id.name, "PRI",
  1963. sizeof(kcontrol->id.name))) {
  1964. port->mode = TDM_PRI;
  1965. } else if (strnstr(kcontrol->id.name, "SEC",
  1966. sizeof(kcontrol->id.name))) {
  1967. port->mode = TDM_SEC;
  1968. } else if (strnstr(kcontrol->id.name, "TERT",
  1969. sizeof(kcontrol->id.name))) {
  1970. port->mode = TDM_TERT;
  1971. } else if (strnstr(kcontrol->id.name, "QUAT",
  1972. sizeof(kcontrol->id.name))) {
  1973. port->mode = TDM_QUAT;
  1974. } else if (strnstr(kcontrol->id.name, "QUIN",
  1975. sizeof(kcontrol->id.name))) {
  1976. port->mode = TDM_QUIN;
  1977. } else {
  1978. pr_err("%s: unsupported mode in: %s",
  1979. __func__, kcontrol->id.name);
  1980. return -EINVAL;
  1981. }
  1982. if (strnstr(kcontrol->id.name, "RX_0",
  1983. sizeof(kcontrol->id.name)) ||
  1984. strnstr(kcontrol->id.name, "TX_0",
  1985. sizeof(kcontrol->id.name))) {
  1986. port->channel = TDM_0;
  1987. } else if (strnstr(kcontrol->id.name, "RX_1",
  1988. sizeof(kcontrol->id.name)) ||
  1989. strnstr(kcontrol->id.name, "TX_1",
  1990. sizeof(kcontrol->id.name))) {
  1991. port->channel = TDM_1;
  1992. } else if (strnstr(kcontrol->id.name, "RX_2",
  1993. sizeof(kcontrol->id.name)) ||
  1994. strnstr(kcontrol->id.name, "TX_2",
  1995. sizeof(kcontrol->id.name))) {
  1996. port->channel = TDM_2;
  1997. } else if (strnstr(kcontrol->id.name, "RX_3",
  1998. sizeof(kcontrol->id.name)) ||
  1999. strnstr(kcontrol->id.name, "TX_3",
  2000. sizeof(kcontrol->id.name))) {
  2001. port->channel = TDM_3;
  2002. } else if (strnstr(kcontrol->id.name, "RX_4",
  2003. sizeof(kcontrol->id.name)) ||
  2004. strnstr(kcontrol->id.name, "TX_4",
  2005. sizeof(kcontrol->id.name))) {
  2006. port->channel = TDM_4;
  2007. } else if (strnstr(kcontrol->id.name, "RX_5",
  2008. sizeof(kcontrol->id.name)) ||
  2009. strnstr(kcontrol->id.name, "TX_5",
  2010. sizeof(kcontrol->id.name))) {
  2011. port->channel = TDM_5;
  2012. } else if (strnstr(kcontrol->id.name, "RX_6",
  2013. sizeof(kcontrol->id.name)) ||
  2014. strnstr(kcontrol->id.name, "TX_6",
  2015. sizeof(kcontrol->id.name))) {
  2016. port->channel = TDM_6;
  2017. } else if (strnstr(kcontrol->id.name, "RX_7",
  2018. sizeof(kcontrol->id.name)) ||
  2019. strnstr(kcontrol->id.name, "TX_7",
  2020. sizeof(kcontrol->id.name))) {
  2021. port->channel = TDM_7;
  2022. } else {
  2023. pr_err("%s: unsupported channel in: %s",
  2024. __func__, kcontrol->id.name);
  2025. return -EINVAL;
  2026. }
  2027. } else
  2028. return -EINVAL;
  2029. return 0;
  2030. }
  2031. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2032. struct snd_ctl_elem_value *ucontrol)
  2033. {
  2034. struct tdm_port port;
  2035. int ret = tdm_get_port_idx(kcontrol, &port);
  2036. if (ret) {
  2037. pr_err("%s: unsupported control: %s",
  2038. __func__, kcontrol->id.name);
  2039. } else {
  2040. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2041. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  2042. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2043. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2044. ucontrol->value.enumerated.item[0]);
  2045. }
  2046. return ret;
  2047. }
  2048. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2049. struct snd_ctl_elem_value *ucontrol)
  2050. {
  2051. struct tdm_port port;
  2052. int ret = tdm_get_port_idx(kcontrol, &port);
  2053. if (ret) {
  2054. pr_err("%s: unsupported control: %s",
  2055. __func__, kcontrol->id.name);
  2056. } else {
  2057. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2058. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2059. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2060. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2061. ucontrol->value.enumerated.item[0]);
  2062. }
  2063. return ret;
  2064. }
  2065. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2066. struct snd_ctl_elem_value *ucontrol)
  2067. {
  2068. struct tdm_port port;
  2069. int ret = tdm_get_port_idx(kcontrol, &port);
  2070. if (ret) {
  2071. pr_err("%s: unsupported control: %s",
  2072. __func__, kcontrol->id.name);
  2073. } else {
  2074. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2075. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2076. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2077. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2078. ucontrol->value.enumerated.item[0]);
  2079. }
  2080. return ret;
  2081. }
  2082. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2083. struct snd_ctl_elem_value *ucontrol)
  2084. {
  2085. struct tdm_port port;
  2086. int ret = tdm_get_port_idx(kcontrol, &port);
  2087. if (ret) {
  2088. pr_err("%s: unsupported control: %s",
  2089. __func__, kcontrol->id.name);
  2090. } else {
  2091. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2092. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2093. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2094. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2095. ucontrol->value.enumerated.item[0]);
  2096. }
  2097. return ret;
  2098. }
  2099. static int tdm_get_format(int value)
  2100. {
  2101. int format = 0;
  2102. switch (value) {
  2103. case 0:
  2104. format = SNDRV_PCM_FORMAT_S16_LE;
  2105. break;
  2106. case 1:
  2107. format = SNDRV_PCM_FORMAT_S24_LE;
  2108. break;
  2109. case 2:
  2110. format = SNDRV_PCM_FORMAT_S32_LE;
  2111. break;
  2112. default:
  2113. format = SNDRV_PCM_FORMAT_S16_LE;
  2114. break;
  2115. }
  2116. return format;
  2117. }
  2118. static int tdm_get_format_val(int format)
  2119. {
  2120. int value = 0;
  2121. switch (format) {
  2122. case SNDRV_PCM_FORMAT_S16_LE:
  2123. value = 0;
  2124. break;
  2125. case SNDRV_PCM_FORMAT_S24_LE:
  2126. value = 1;
  2127. break;
  2128. case SNDRV_PCM_FORMAT_S32_LE:
  2129. value = 2;
  2130. break;
  2131. default:
  2132. value = 0;
  2133. break;
  2134. }
  2135. return value;
  2136. }
  2137. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2138. struct snd_ctl_elem_value *ucontrol)
  2139. {
  2140. struct tdm_port port;
  2141. int ret = tdm_get_port_idx(kcontrol, &port);
  2142. if (ret) {
  2143. pr_err("%s: unsupported control: %s",
  2144. __func__, kcontrol->id.name);
  2145. } else {
  2146. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2147. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2148. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2149. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2150. ucontrol->value.enumerated.item[0]);
  2151. }
  2152. return ret;
  2153. }
  2154. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2155. struct snd_ctl_elem_value *ucontrol)
  2156. {
  2157. struct tdm_port port;
  2158. int ret = tdm_get_port_idx(kcontrol, &port);
  2159. if (ret) {
  2160. pr_err("%s: unsupported control: %s",
  2161. __func__, kcontrol->id.name);
  2162. } else {
  2163. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2164. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2165. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2166. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2167. ucontrol->value.enumerated.item[0]);
  2168. }
  2169. return ret;
  2170. }
  2171. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2172. struct snd_ctl_elem_value *ucontrol)
  2173. {
  2174. struct tdm_port port;
  2175. int ret = tdm_get_port_idx(kcontrol, &port);
  2176. if (ret) {
  2177. pr_err("%s: unsupported control: %s",
  2178. __func__, kcontrol->id.name);
  2179. } else {
  2180. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2181. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2182. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2183. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2184. ucontrol->value.enumerated.item[0]);
  2185. }
  2186. return ret;
  2187. }
  2188. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2189. struct snd_ctl_elem_value *ucontrol)
  2190. {
  2191. struct tdm_port port;
  2192. int ret = tdm_get_port_idx(kcontrol, &port);
  2193. if (ret) {
  2194. pr_err("%s: unsupported control: %s",
  2195. __func__, kcontrol->id.name);
  2196. } else {
  2197. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2198. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2199. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2200. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2201. ucontrol->value.enumerated.item[0]);
  2202. }
  2203. return ret;
  2204. }
  2205. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2206. struct snd_ctl_elem_value *ucontrol)
  2207. {
  2208. struct tdm_port port;
  2209. int ret = tdm_get_port_idx(kcontrol, &port);
  2210. if (ret) {
  2211. pr_err("%s: unsupported control: %s",
  2212. __func__, kcontrol->id.name);
  2213. } else {
  2214. ucontrol->value.enumerated.item[0] =
  2215. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2216. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2217. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2218. ucontrol->value.enumerated.item[0]);
  2219. }
  2220. return ret;
  2221. }
  2222. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2223. struct snd_ctl_elem_value *ucontrol)
  2224. {
  2225. struct tdm_port port;
  2226. int ret = tdm_get_port_idx(kcontrol, &port);
  2227. if (ret) {
  2228. pr_err("%s: unsupported control: %s",
  2229. __func__, kcontrol->id.name);
  2230. } else {
  2231. tdm_rx_cfg[port.mode][port.channel].channels =
  2232. ucontrol->value.enumerated.item[0] + 1;
  2233. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2234. tdm_rx_cfg[port.mode][port.channel].channels,
  2235. ucontrol->value.enumerated.item[0] + 1);
  2236. }
  2237. return ret;
  2238. }
  2239. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2240. struct snd_ctl_elem_value *ucontrol)
  2241. {
  2242. struct tdm_port port;
  2243. int ret = tdm_get_port_idx(kcontrol, &port);
  2244. if (ret) {
  2245. pr_err("%s: unsupported control: %s",
  2246. __func__, kcontrol->id.name);
  2247. } else {
  2248. ucontrol->value.enumerated.item[0] =
  2249. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2250. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2251. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2252. ucontrol->value.enumerated.item[0]);
  2253. }
  2254. return ret;
  2255. }
  2256. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2257. struct snd_ctl_elem_value *ucontrol)
  2258. {
  2259. struct tdm_port port;
  2260. int ret = tdm_get_port_idx(kcontrol, &port);
  2261. if (ret) {
  2262. pr_err("%s: unsupported control: %s",
  2263. __func__, kcontrol->id.name);
  2264. } else {
  2265. tdm_tx_cfg[port.mode][port.channel].channels =
  2266. ucontrol->value.enumerated.item[0] + 1;
  2267. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2268. tdm_tx_cfg[port.mode][port.channel].channels,
  2269. ucontrol->value.enumerated.item[0] + 1);
  2270. }
  2271. return ret;
  2272. }
  2273. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2274. {
  2275. int idx;
  2276. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2277. sizeof("PRIM_AUX_PCM")))
  2278. idx = PRIM_AUX_PCM;
  2279. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2280. sizeof("SEC_AUX_PCM")))
  2281. idx = SEC_AUX_PCM;
  2282. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2283. sizeof("TERT_AUX_PCM")))
  2284. idx = TERT_AUX_PCM;
  2285. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2286. sizeof("QUAT_AUX_PCM")))
  2287. idx = QUAT_AUX_PCM;
  2288. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2289. sizeof("QUIN_AUX_PCM")))
  2290. idx = QUIN_AUX_PCM;
  2291. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2292. sizeof("SENN_AUX_PCM")))
  2293. idx = SEN_AUX_PCM;
  2294. else {
  2295. pr_err("%s: unsupported port: %s",
  2296. __func__, kcontrol->id.name);
  2297. idx = -EINVAL;
  2298. }
  2299. return idx;
  2300. }
  2301. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2302. struct snd_ctl_elem_value *ucontrol)
  2303. {
  2304. int idx = aux_pcm_get_port_idx(kcontrol);
  2305. if (idx < 0)
  2306. return idx;
  2307. aux_pcm_rx_cfg[idx].sample_rate =
  2308. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2309. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2310. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2311. ucontrol->value.enumerated.item[0]);
  2312. return 0;
  2313. }
  2314. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2315. struct snd_ctl_elem_value *ucontrol)
  2316. {
  2317. int idx = aux_pcm_get_port_idx(kcontrol);
  2318. if (idx < 0)
  2319. return idx;
  2320. ucontrol->value.enumerated.item[0] =
  2321. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2322. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2323. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2324. ucontrol->value.enumerated.item[0]);
  2325. return 0;
  2326. }
  2327. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2328. struct snd_ctl_elem_value *ucontrol)
  2329. {
  2330. int idx = aux_pcm_get_port_idx(kcontrol);
  2331. if (idx < 0)
  2332. return idx;
  2333. aux_pcm_tx_cfg[idx].sample_rate =
  2334. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2335. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2336. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2337. ucontrol->value.enumerated.item[0]);
  2338. return 0;
  2339. }
  2340. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2341. struct snd_ctl_elem_value *ucontrol)
  2342. {
  2343. int idx = aux_pcm_get_port_idx(kcontrol);
  2344. if (idx < 0)
  2345. return idx;
  2346. ucontrol->value.enumerated.item[0] =
  2347. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2348. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2349. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2350. ucontrol->value.enumerated.item[0]);
  2351. return 0;
  2352. }
  2353. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2354. {
  2355. int idx;
  2356. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2357. sizeof("PRIM_MI2S_RX")))
  2358. idx = PRIM_MI2S;
  2359. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2360. sizeof("SEC_MI2S_RX")))
  2361. idx = SEC_MI2S;
  2362. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2363. sizeof("TERT_MI2S_RX")))
  2364. idx = TERT_MI2S;
  2365. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2366. sizeof("QUAT_MI2S_RX")))
  2367. idx = QUAT_MI2S;
  2368. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2369. sizeof("QUIN_MI2S_RX")))
  2370. idx = QUIN_MI2S;
  2371. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2372. sizeof("SEN_MI2S_RX")))
  2373. idx = SEN_MI2S;
  2374. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2375. sizeof("PRIM_MI2S_TX")))
  2376. idx = PRIM_MI2S;
  2377. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2378. sizeof("SEC_MI2S_TX")))
  2379. idx = SEC_MI2S;
  2380. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2381. sizeof("TERT_MI2S_TX")))
  2382. idx = TERT_MI2S;
  2383. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2384. sizeof("QUAT_MI2S_TX")))
  2385. idx = QUAT_MI2S;
  2386. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2387. sizeof("QUIN_MI2S_TX")))
  2388. idx = QUIN_MI2S;
  2389. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2390. sizeof("SEN_MI2S_TX")))
  2391. idx = SEN_MI2S;
  2392. else {
  2393. pr_err("%s: unsupported channel: %s",
  2394. __func__, kcontrol->id.name);
  2395. idx = -EINVAL;
  2396. }
  2397. return idx;
  2398. }
  2399. static int mi2s_get_sample_rate_val(int sample_rate)
  2400. {
  2401. int sample_rate_val;
  2402. switch (sample_rate) {
  2403. case SAMPLING_RATE_8KHZ:
  2404. sample_rate_val = 0;
  2405. break;
  2406. case SAMPLING_RATE_11P025KHZ:
  2407. sample_rate_val = 1;
  2408. break;
  2409. case SAMPLING_RATE_16KHZ:
  2410. sample_rate_val = 2;
  2411. break;
  2412. case SAMPLING_RATE_22P05KHZ:
  2413. sample_rate_val = 3;
  2414. break;
  2415. case SAMPLING_RATE_32KHZ:
  2416. sample_rate_val = 4;
  2417. break;
  2418. case SAMPLING_RATE_44P1KHZ:
  2419. sample_rate_val = 5;
  2420. break;
  2421. case SAMPLING_RATE_48KHZ:
  2422. sample_rate_val = 6;
  2423. break;
  2424. case SAMPLING_RATE_96KHZ:
  2425. sample_rate_val = 7;
  2426. break;
  2427. case SAMPLING_RATE_192KHZ:
  2428. sample_rate_val = 8;
  2429. break;
  2430. case SAMPLING_RATE_384KHZ:
  2431. sample_rate_val = 9;
  2432. break;
  2433. default:
  2434. sample_rate_val = 6;
  2435. break;
  2436. }
  2437. return sample_rate_val;
  2438. }
  2439. static int mi2s_get_sample_rate(int value)
  2440. {
  2441. int sample_rate;
  2442. switch (value) {
  2443. case 0:
  2444. sample_rate = SAMPLING_RATE_8KHZ;
  2445. break;
  2446. case 1:
  2447. sample_rate = SAMPLING_RATE_11P025KHZ;
  2448. break;
  2449. case 2:
  2450. sample_rate = SAMPLING_RATE_16KHZ;
  2451. break;
  2452. case 3:
  2453. sample_rate = SAMPLING_RATE_22P05KHZ;
  2454. break;
  2455. case 4:
  2456. sample_rate = SAMPLING_RATE_32KHZ;
  2457. break;
  2458. case 5:
  2459. sample_rate = SAMPLING_RATE_44P1KHZ;
  2460. break;
  2461. case 6:
  2462. sample_rate = SAMPLING_RATE_48KHZ;
  2463. break;
  2464. case 7:
  2465. sample_rate = SAMPLING_RATE_96KHZ;
  2466. break;
  2467. case 8:
  2468. sample_rate = SAMPLING_RATE_192KHZ;
  2469. break;
  2470. case 9:
  2471. sample_rate = SAMPLING_RATE_384KHZ;
  2472. break;
  2473. default:
  2474. sample_rate = SAMPLING_RATE_48KHZ;
  2475. break;
  2476. }
  2477. return sample_rate;
  2478. }
  2479. static int mi2s_auxpcm_get_format(int value)
  2480. {
  2481. int format;
  2482. switch (value) {
  2483. case 0:
  2484. format = SNDRV_PCM_FORMAT_S16_LE;
  2485. break;
  2486. case 1:
  2487. format = SNDRV_PCM_FORMAT_S24_LE;
  2488. break;
  2489. case 2:
  2490. format = SNDRV_PCM_FORMAT_S24_3LE;
  2491. break;
  2492. case 3:
  2493. format = SNDRV_PCM_FORMAT_S32_LE;
  2494. break;
  2495. default:
  2496. format = SNDRV_PCM_FORMAT_S16_LE;
  2497. break;
  2498. }
  2499. return format;
  2500. }
  2501. static int mi2s_auxpcm_get_format_value(int format)
  2502. {
  2503. int value;
  2504. switch (format) {
  2505. case SNDRV_PCM_FORMAT_S16_LE:
  2506. value = 0;
  2507. break;
  2508. case SNDRV_PCM_FORMAT_S24_LE:
  2509. value = 1;
  2510. break;
  2511. case SNDRV_PCM_FORMAT_S24_3LE:
  2512. value = 2;
  2513. break;
  2514. case SNDRV_PCM_FORMAT_S32_LE:
  2515. value = 3;
  2516. break;
  2517. default:
  2518. value = 0;
  2519. break;
  2520. }
  2521. return value;
  2522. }
  2523. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2524. struct snd_ctl_elem_value *ucontrol)
  2525. {
  2526. int idx = mi2s_get_port_idx(kcontrol);
  2527. if (idx < 0)
  2528. return idx;
  2529. mi2s_rx_cfg[idx].sample_rate =
  2530. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2531. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2532. idx, mi2s_rx_cfg[idx].sample_rate,
  2533. ucontrol->value.enumerated.item[0]);
  2534. return 0;
  2535. }
  2536. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2537. struct snd_ctl_elem_value *ucontrol)
  2538. {
  2539. int idx = mi2s_get_port_idx(kcontrol);
  2540. if (idx < 0)
  2541. return idx;
  2542. ucontrol->value.enumerated.item[0] =
  2543. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2544. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2545. idx, mi2s_rx_cfg[idx].sample_rate,
  2546. ucontrol->value.enumerated.item[0]);
  2547. return 0;
  2548. }
  2549. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2550. struct snd_ctl_elem_value *ucontrol)
  2551. {
  2552. int idx = mi2s_get_port_idx(kcontrol);
  2553. if (idx < 0)
  2554. return idx;
  2555. mi2s_tx_cfg[idx].sample_rate =
  2556. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2557. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2558. idx, mi2s_tx_cfg[idx].sample_rate,
  2559. ucontrol->value.enumerated.item[0]);
  2560. return 0;
  2561. }
  2562. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2563. struct snd_ctl_elem_value *ucontrol)
  2564. {
  2565. int idx = mi2s_get_port_idx(kcontrol);
  2566. if (idx < 0)
  2567. return idx;
  2568. ucontrol->value.enumerated.item[0] =
  2569. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2570. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2571. idx, mi2s_tx_cfg[idx].sample_rate,
  2572. ucontrol->value.enumerated.item[0]);
  2573. return 0;
  2574. }
  2575. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2576. struct snd_ctl_elem_value *ucontrol)
  2577. {
  2578. int idx = mi2s_get_port_idx(kcontrol);
  2579. if (idx < 0)
  2580. return idx;
  2581. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2582. idx, mi2s_rx_cfg[idx].channels);
  2583. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2584. return 0;
  2585. }
  2586. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2587. struct snd_ctl_elem_value *ucontrol)
  2588. {
  2589. int idx = mi2s_get_port_idx(kcontrol);
  2590. if (idx < 0)
  2591. return idx;
  2592. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2593. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2594. idx, mi2s_rx_cfg[idx].channels);
  2595. return 1;
  2596. }
  2597. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2598. struct snd_ctl_elem_value *ucontrol)
  2599. {
  2600. int idx = mi2s_get_port_idx(kcontrol);
  2601. if (idx < 0)
  2602. return idx;
  2603. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2604. idx, mi2s_tx_cfg[idx].channels);
  2605. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2606. return 0;
  2607. }
  2608. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2609. struct snd_ctl_elem_value *ucontrol)
  2610. {
  2611. int idx = mi2s_get_port_idx(kcontrol);
  2612. if (idx < 0)
  2613. return idx;
  2614. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2615. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2616. idx, mi2s_tx_cfg[idx].channels);
  2617. return 1;
  2618. }
  2619. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2620. struct snd_ctl_elem_value *ucontrol)
  2621. {
  2622. int idx = mi2s_get_port_idx(kcontrol);
  2623. if (idx < 0)
  2624. return idx;
  2625. ucontrol->value.enumerated.item[0] =
  2626. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2627. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2628. idx, mi2s_rx_cfg[idx].bit_format,
  2629. ucontrol->value.enumerated.item[0]);
  2630. return 0;
  2631. }
  2632. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2633. struct snd_ctl_elem_value *ucontrol)
  2634. {
  2635. struct msm_asoc_mach_data *pdata = NULL;
  2636. struct snd_soc_component *component = NULL;
  2637. struct snd_soc_card *card = NULL;
  2638. int idx = mi2s_get_port_idx(kcontrol);
  2639. component = snd_soc_kcontrol_component(kcontrol);
  2640. card = kcontrol->private_data;
  2641. pdata = snd_soc_card_get_drvdata(card);
  2642. if (idx < 0)
  2643. return idx;
  2644. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2645. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2646. {
  2647. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2648. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2649. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2650. ucontrol->value.enumerated.item[0]);
  2651. } else {
  2652. mi2s_rx_cfg[idx].bit_format =
  2653. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2654. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2655. idx, mi2s_rx_cfg[idx].bit_format,
  2656. ucontrol->value.enumerated.item[0]);
  2657. }
  2658. return 0;
  2659. }
  2660. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2661. struct snd_ctl_elem_value *ucontrol)
  2662. {
  2663. int idx = mi2s_get_port_idx(kcontrol);
  2664. if (idx < 0)
  2665. return idx;
  2666. ucontrol->value.enumerated.item[0] =
  2667. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2668. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2669. idx, mi2s_tx_cfg[idx].bit_format,
  2670. ucontrol->value.enumerated.item[0]);
  2671. return 0;
  2672. }
  2673. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2674. struct snd_ctl_elem_value *ucontrol)
  2675. {
  2676. int idx = mi2s_get_port_idx(kcontrol);
  2677. if (idx < 0)
  2678. return idx;
  2679. mi2s_tx_cfg[idx].bit_format =
  2680. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2681. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2682. idx, mi2s_tx_cfg[idx].bit_format,
  2683. ucontrol->value.enumerated.item[0]);
  2684. return 0;
  2685. }
  2686. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2687. struct snd_ctl_elem_value *ucontrol)
  2688. {
  2689. int idx = aux_pcm_get_port_idx(kcontrol);
  2690. if (idx < 0)
  2691. return idx;
  2692. ucontrol->value.enumerated.item[0] =
  2693. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2694. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2695. idx, aux_pcm_rx_cfg[idx].bit_format,
  2696. ucontrol->value.enumerated.item[0]);
  2697. return 0;
  2698. }
  2699. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2700. struct snd_ctl_elem_value *ucontrol)
  2701. {
  2702. int idx = aux_pcm_get_port_idx(kcontrol);
  2703. if (idx < 0)
  2704. return idx;
  2705. aux_pcm_rx_cfg[idx].bit_format =
  2706. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2707. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2708. idx, aux_pcm_rx_cfg[idx].bit_format,
  2709. ucontrol->value.enumerated.item[0]);
  2710. return 0;
  2711. }
  2712. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2713. struct snd_ctl_elem_value *ucontrol)
  2714. {
  2715. int idx = aux_pcm_get_port_idx(kcontrol);
  2716. if (idx < 0)
  2717. return idx;
  2718. ucontrol->value.enumerated.item[0] =
  2719. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2720. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2721. idx, aux_pcm_tx_cfg[idx].bit_format,
  2722. ucontrol->value.enumerated.item[0]);
  2723. return 0;
  2724. }
  2725. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2726. struct snd_ctl_elem_value *ucontrol)
  2727. {
  2728. int idx = aux_pcm_get_port_idx(kcontrol);
  2729. if (idx < 0)
  2730. return idx;
  2731. aux_pcm_tx_cfg[idx].bit_format =
  2732. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2733. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2734. idx, aux_pcm_tx_cfg[idx].bit_format,
  2735. ucontrol->value.enumerated.item[0]);
  2736. return 0;
  2737. }
  2738. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2739. {
  2740. int idx;
  2741. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2742. sizeof("PRIM_SPDIF_RX")))
  2743. idx = PRIM_SPDIF_RX;
  2744. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2745. sizeof("SEC_SPDIF_RX")))
  2746. idx = SEC_SPDIF_RX;
  2747. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2748. sizeof("PRIM_SPDIF_TX")))
  2749. idx = PRIM_SPDIF_TX;
  2750. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2751. sizeof("SEC_SPDIF_TX")))
  2752. idx = SEC_SPDIF_TX;
  2753. else {
  2754. pr_err("%s: unsupported channel: %s",
  2755. __func__, kcontrol->id.name);
  2756. idx = -EINVAL;
  2757. }
  2758. return idx;
  2759. }
  2760. static int spdif_get_sample_rate_val(int sample_rate)
  2761. {
  2762. int sample_rate_val;
  2763. switch (sample_rate) {
  2764. case SAMPLING_RATE_32KHZ:
  2765. sample_rate_val = 0;
  2766. break;
  2767. case SAMPLING_RATE_44P1KHZ:
  2768. sample_rate_val = 1;
  2769. break;
  2770. case SAMPLING_RATE_48KHZ:
  2771. sample_rate_val = 2;
  2772. break;
  2773. case SAMPLING_RATE_88P2KHZ:
  2774. sample_rate_val = 3;
  2775. break;
  2776. case SAMPLING_RATE_96KHZ:
  2777. sample_rate_val = 4;
  2778. break;
  2779. case SAMPLING_RATE_176P4KHZ:
  2780. sample_rate_val = 5;
  2781. break;
  2782. case SAMPLING_RATE_192KHZ:
  2783. sample_rate_val = 6;
  2784. break;
  2785. default:
  2786. sample_rate_val = 2;
  2787. break;
  2788. }
  2789. return sample_rate_val;
  2790. }
  2791. static int spdif_get_sample_rate(int value)
  2792. {
  2793. int sample_rate;
  2794. switch (value) {
  2795. case 0:
  2796. sample_rate = SAMPLING_RATE_32KHZ;
  2797. break;
  2798. case 1:
  2799. sample_rate = SAMPLING_RATE_44P1KHZ;
  2800. break;
  2801. case 2:
  2802. sample_rate = SAMPLING_RATE_48KHZ;
  2803. break;
  2804. case 3:
  2805. sample_rate = SAMPLING_RATE_88P2KHZ;
  2806. break;
  2807. case 4:
  2808. sample_rate = SAMPLING_RATE_96KHZ;
  2809. break;
  2810. case 5:
  2811. sample_rate = SAMPLING_RATE_176P4KHZ;
  2812. break;
  2813. case 6:
  2814. sample_rate = SAMPLING_RATE_192KHZ;
  2815. break;
  2816. default:
  2817. sample_rate = SAMPLING_RATE_48KHZ;
  2818. break;
  2819. }
  2820. return sample_rate;
  2821. }
  2822. static int spdif_get_format(int value)
  2823. {
  2824. int format;
  2825. switch (value) {
  2826. case 0:
  2827. format = SNDRV_PCM_FORMAT_S16_LE;
  2828. break;
  2829. case 1:
  2830. format = SNDRV_PCM_FORMAT_S24_LE;
  2831. break;
  2832. default:
  2833. format = SNDRV_PCM_FORMAT_S16_LE;
  2834. break;
  2835. }
  2836. return format;
  2837. }
  2838. static int spdif_get_format_value(int format)
  2839. {
  2840. int value;
  2841. switch (format) {
  2842. case SNDRV_PCM_FORMAT_S16_LE:
  2843. value = 0;
  2844. break;
  2845. case SNDRV_PCM_FORMAT_S24_LE:
  2846. value = 1;
  2847. break;
  2848. default:
  2849. value = 0;
  2850. break;
  2851. }
  2852. return value;
  2853. }
  2854. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2855. struct snd_ctl_elem_value *ucontrol)
  2856. {
  2857. int idx = spdif_get_port_idx(kcontrol);
  2858. if (idx < 0)
  2859. return idx;
  2860. spdif_rx_cfg[idx].sample_rate =
  2861. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2862. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2863. idx, spdif_rx_cfg[idx].sample_rate,
  2864. ucontrol->value.enumerated.item[0]);
  2865. return 0;
  2866. }
  2867. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2868. struct snd_ctl_elem_value *ucontrol)
  2869. {
  2870. int idx = spdif_get_port_idx(kcontrol);
  2871. if (idx < 0)
  2872. return idx;
  2873. ucontrol->value.enumerated.item[0] =
  2874. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2875. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2876. idx, spdif_rx_cfg[idx].sample_rate,
  2877. ucontrol->value.enumerated.item[0]);
  2878. return 0;
  2879. }
  2880. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2881. struct snd_ctl_elem_value *ucontrol)
  2882. {
  2883. int idx = spdif_get_port_idx(kcontrol);
  2884. if (idx < 0)
  2885. return idx;
  2886. spdif_tx_cfg[idx].sample_rate =
  2887. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2888. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2889. idx, spdif_tx_cfg[idx].sample_rate,
  2890. ucontrol->value.enumerated.item[0]);
  2891. return 0;
  2892. }
  2893. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2894. struct snd_ctl_elem_value *ucontrol)
  2895. {
  2896. int idx = spdif_get_port_idx(kcontrol);
  2897. if (idx < 0)
  2898. return idx;
  2899. ucontrol->value.enumerated.item[0] =
  2900. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2901. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2902. idx, spdif_tx_cfg[idx].sample_rate,
  2903. ucontrol->value.enumerated.item[0]);
  2904. return 0;
  2905. }
  2906. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2907. struct snd_ctl_elem_value *ucontrol)
  2908. {
  2909. int idx = spdif_get_port_idx(kcontrol);
  2910. if (idx < 0)
  2911. return idx;
  2912. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2913. idx, spdif_rx_cfg[idx].channels);
  2914. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2915. return 0;
  2916. }
  2917. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2918. struct snd_ctl_elem_value *ucontrol)
  2919. {
  2920. int idx = spdif_get_port_idx(kcontrol);
  2921. if (idx < 0)
  2922. return idx;
  2923. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2924. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2925. idx, spdif_rx_cfg[idx].channels);
  2926. return 1;
  2927. }
  2928. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2929. struct snd_ctl_elem_value *ucontrol)
  2930. {
  2931. int idx = spdif_get_port_idx(kcontrol);
  2932. if (idx < 0)
  2933. return idx;
  2934. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2935. idx, spdif_tx_cfg[idx].channels);
  2936. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2937. return 0;
  2938. }
  2939. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2940. struct snd_ctl_elem_value *ucontrol)
  2941. {
  2942. int idx = spdif_get_port_idx(kcontrol);
  2943. if (idx < 0)
  2944. return idx;
  2945. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2946. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2947. idx, spdif_tx_cfg[idx].channels);
  2948. return 1;
  2949. }
  2950. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2951. struct snd_ctl_elem_value *ucontrol)
  2952. {
  2953. int idx = spdif_get_port_idx(kcontrol);
  2954. if (idx < 0)
  2955. return idx;
  2956. ucontrol->value.enumerated.item[0] =
  2957. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2958. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2959. idx, spdif_rx_cfg[idx].bit_format,
  2960. ucontrol->value.enumerated.item[0]);
  2961. return 0;
  2962. }
  2963. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2964. struct snd_ctl_elem_value *ucontrol)
  2965. {
  2966. int idx = spdif_get_port_idx(kcontrol);
  2967. if (idx < 0)
  2968. return idx;
  2969. spdif_rx_cfg[idx].bit_format =
  2970. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2971. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2972. idx, spdif_rx_cfg[idx].bit_format,
  2973. ucontrol->value.enumerated.item[0]);
  2974. return 0;
  2975. }
  2976. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2977. struct snd_ctl_elem_value *ucontrol)
  2978. {
  2979. int idx = spdif_get_port_idx(kcontrol);
  2980. if (idx < 0)
  2981. return idx;
  2982. ucontrol->value.enumerated.item[0] =
  2983. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2984. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2985. idx, spdif_tx_cfg[idx].bit_format,
  2986. ucontrol->value.enumerated.item[0]);
  2987. return 0;
  2988. }
  2989. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2990. struct snd_ctl_elem_value *ucontrol)
  2991. {
  2992. int idx = spdif_get_port_idx(kcontrol);
  2993. if (idx < 0)
  2994. return idx;
  2995. spdif_tx_cfg[idx].bit_format =
  2996. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2997. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2998. idx, spdif_tx_cfg[idx].bit_format,
  2999. ucontrol->value.enumerated.item[0]);
  3000. return 0;
  3001. }
  3002. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  3003. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  3004. slim_rx_ch_get, slim_rx_ch_put),
  3005. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  3006. slim_rx_ch_get, slim_rx_ch_put),
  3007. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  3008. slim_tx_ch_get, slim_tx_ch_put),
  3009. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  3010. slim_tx_ch_get, slim_tx_ch_put),
  3011. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  3012. slim_rx_ch_get, slim_rx_ch_put),
  3013. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  3014. slim_rx_ch_get, slim_rx_ch_put),
  3015. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  3016. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3017. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  3018. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3019. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  3020. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3021. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  3022. slim_tx_bit_format_get, slim_tx_bit_format_put),
  3023. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  3024. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3025. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  3026. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3027. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  3028. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  3029. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  3030. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3031. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  3032. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3033. };
  3034. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  3035. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  3036. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3037. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  3038. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3039. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  3040. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3041. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3042. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3043. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3044. va_cdc_dma_tx_0_sample_rate,
  3045. cdc_dma_tx_sample_rate_get,
  3046. cdc_dma_tx_sample_rate_put),
  3047. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3048. va_cdc_dma_tx_1_sample_rate,
  3049. cdc_dma_tx_sample_rate_get,
  3050. cdc_dma_tx_sample_rate_put),
  3051. };
  3052. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3053. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3054. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3055. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3056. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3057. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3058. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3059. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3060. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3061. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3062. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3063. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3064. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3065. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3066. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3067. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3068. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3069. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3070. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3071. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3072. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3073. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3074. wsa_cdc_dma_rx_0_sample_rate,
  3075. cdc_dma_rx_sample_rate_get,
  3076. cdc_dma_rx_sample_rate_put),
  3077. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3078. wsa_cdc_dma_rx_1_sample_rate,
  3079. cdc_dma_rx_sample_rate_get,
  3080. cdc_dma_rx_sample_rate_put),
  3081. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3082. wsa_cdc_dma_tx_0_sample_rate,
  3083. cdc_dma_tx_sample_rate_get,
  3084. cdc_dma_tx_sample_rate_put),
  3085. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3086. wsa_cdc_dma_tx_1_sample_rate,
  3087. cdc_dma_tx_sample_rate_get,
  3088. cdc_dma_tx_sample_rate_put),
  3089. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3090. wsa_cdc_dma_tx_2_sample_rate,
  3091. cdc_dma_tx_sample_rate_get,
  3092. cdc_dma_tx_sample_rate_put),
  3093. };
  3094. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3095. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3096. msm_bt_sample_rate_sink_get,
  3097. msm_bt_sample_rate_sink_put),
  3098. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3099. msm_bt_sample_rate_get,
  3100. msm_bt_sample_rate_put),
  3101. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3102. msm_bt_sample_rate_get,
  3103. msm_bt_sample_rate_put),
  3104. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3105. proxy_rx_ch_get, proxy_rx_ch_put),
  3106. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3107. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3108. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3109. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3110. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3111. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3112. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3113. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3114. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3115. usb_audio_rx_sample_rate_get,
  3116. usb_audio_rx_sample_rate_put),
  3117. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3118. usb_audio_tx_sample_rate_get,
  3119. usb_audio_tx_sample_rate_put),
  3120. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3121. tdm_rx_sample_rate_get,
  3122. tdm_rx_sample_rate_put),
  3123. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3124. tdm_tx_sample_rate_get,
  3125. tdm_tx_sample_rate_put),
  3126. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3127. tdm_rx_format_get,
  3128. tdm_rx_format_put),
  3129. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3130. tdm_tx_format_get,
  3131. tdm_tx_format_put),
  3132. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3133. tdm_rx_ch_get,
  3134. tdm_rx_ch_put),
  3135. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3136. tdm_tx_ch_get,
  3137. tdm_tx_ch_put),
  3138. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3139. tdm_rx_sample_rate_get,
  3140. tdm_rx_sample_rate_put),
  3141. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3142. tdm_tx_sample_rate_get,
  3143. tdm_tx_sample_rate_put),
  3144. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3145. tdm_rx_format_get,
  3146. tdm_rx_format_put),
  3147. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3148. tdm_tx_format_get,
  3149. tdm_tx_format_put),
  3150. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3151. tdm_rx_ch_get,
  3152. tdm_rx_ch_put),
  3153. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3154. tdm_tx_ch_get,
  3155. tdm_tx_ch_put),
  3156. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3157. tdm_rx_sample_rate_get,
  3158. tdm_rx_sample_rate_put),
  3159. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3160. tdm_tx_sample_rate_get,
  3161. tdm_tx_sample_rate_put),
  3162. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3163. tdm_rx_format_get,
  3164. tdm_rx_format_put),
  3165. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3166. tdm_tx_format_get,
  3167. tdm_tx_format_put),
  3168. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3169. tdm_rx_ch_get,
  3170. tdm_rx_ch_put),
  3171. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3172. tdm_tx_ch_get,
  3173. tdm_tx_ch_put),
  3174. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3175. tdm_rx_sample_rate_get,
  3176. tdm_rx_sample_rate_put),
  3177. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3178. tdm_tx_sample_rate_get,
  3179. tdm_tx_sample_rate_put),
  3180. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3181. tdm_rx_format_get,
  3182. tdm_rx_format_put),
  3183. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3184. tdm_tx_format_get,
  3185. tdm_tx_format_put),
  3186. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3187. tdm_rx_ch_get,
  3188. tdm_rx_ch_put),
  3189. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3190. tdm_tx_ch_get,
  3191. tdm_tx_ch_put),
  3192. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3193. tdm_rx_sample_rate_get,
  3194. tdm_rx_sample_rate_put),
  3195. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3196. tdm_tx_sample_rate_get,
  3197. tdm_tx_sample_rate_put),
  3198. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3199. tdm_rx_format_get,
  3200. tdm_rx_format_put),
  3201. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3202. tdm_tx_format_get,
  3203. tdm_tx_format_put),
  3204. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3205. tdm_rx_ch_get,
  3206. tdm_rx_ch_put),
  3207. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3208. tdm_tx_ch_get,
  3209. tdm_tx_ch_put),
  3210. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3211. aux_pcm_rx_sample_rate_get,
  3212. aux_pcm_rx_sample_rate_put),
  3213. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3214. aux_pcm_rx_sample_rate_get,
  3215. aux_pcm_rx_sample_rate_put),
  3216. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3217. aux_pcm_rx_sample_rate_get,
  3218. aux_pcm_rx_sample_rate_put),
  3219. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3220. aux_pcm_rx_sample_rate_get,
  3221. aux_pcm_rx_sample_rate_put),
  3222. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3223. aux_pcm_rx_sample_rate_get,
  3224. aux_pcm_rx_sample_rate_put),
  3225. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3226. aux_pcm_tx_sample_rate_get,
  3227. aux_pcm_tx_sample_rate_put),
  3228. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3229. aux_pcm_tx_sample_rate_get,
  3230. aux_pcm_tx_sample_rate_put),
  3231. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3232. aux_pcm_tx_sample_rate_get,
  3233. aux_pcm_tx_sample_rate_put),
  3234. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3235. aux_pcm_tx_sample_rate_get,
  3236. aux_pcm_tx_sample_rate_put),
  3237. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3238. aux_pcm_tx_sample_rate_get,
  3239. aux_pcm_tx_sample_rate_put),
  3240. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3241. aux_pcm_tx_sample_rate_get,
  3242. aux_pcm_tx_sample_rate_put),
  3243. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3244. mi2s_rx_sample_rate_get,
  3245. mi2s_rx_sample_rate_put),
  3246. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3247. mi2s_rx_sample_rate_get,
  3248. mi2s_rx_sample_rate_put),
  3249. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3250. mi2s_rx_sample_rate_get,
  3251. mi2s_rx_sample_rate_put),
  3252. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3253. mi2s_rx_sample_rate_get,
  3254. mi2s_rx_sample_rate_put),
  3255. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3256. mi2s_rx_sample_rate_get,
  3257. mi2s_rx_sample_rate_put),
  3258. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3259. mi2s_rx_sample_rate_get,
  3260. mi2s_rx_sample_rate_put),
  3261. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3262. mi2s_tx_sample_rate_get,
  3263. mi2s_tx_sample_rate_put),
  3264. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3265. mi2s_tx_sample_rate_get,
  3266. mi2s_tx_sample_rate_put),
  3267. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3268. mi2s_tx_sample_rate_get,
  3269. mi2s_tx_sample_rate_put),
  3270. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3271. mi2s_tx_sample_rate_get,
  3272. mi2s_tx_sample_rate_put),
  3273. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3274. mi2s_tx_sample_rate_get,
  3275. mi2s_tx_sample_rate_put),
  3276. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3277. mi2s_tx_sample_rate_get,
  3278. mi2s_tx_sample_rate_put),
  3279. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3280. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3281. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3282. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3283. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3284. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3285. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3286. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3287. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3288. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3289. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3290. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3291. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3292. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3293. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3294. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3295. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3296. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3297. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3298. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3299. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3300. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3301. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3302. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3303. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3304. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3305. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3306. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3307. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3308. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3309. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3310. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3311. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3312. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3313. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3314. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3315. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3316. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3317. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3318. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3319. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3320. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3321. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3322. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3323. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3324. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3325. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3326. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3327. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3328. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3329. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3330. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3331. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3332. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3333. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3334. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3335. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3336. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3337. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3338. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3339. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3340. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3341. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3342. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3343. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3344. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3345. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3346. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3347. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3348. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3349. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3350. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3351. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3352. msm_snd_vad_cfg_put),
  3353. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3354. msm_spdif_rx_sample_rate_get,
  3355. msm_spdif_rx_sample_rate_put),
  3356. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3357. msm_spdif_tx_sample_rate_get,
  3358. msm_spdif_tx_sample_rate_put),
  3359. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3360. msm_spdif_rx_sample_rate_get,
  3361. msm_spdif_rx_sample_rate_put),
  3362. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3363. msm_spdif_tx_sample_rate_get,
  3364. msm_spdif_tx_sample_rate_put),
  3365. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3366. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3367. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3368. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3369. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3370. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3371. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3372. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3373. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3374. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3375. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3376. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3377. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3378. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3379. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3380. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3381. };
  3382. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  3383. int enable, bool dapm)
  3384. {
  3385. int ret = 0;
  3386. if (!strcmp(component.name, "tasha_codec")) {
  3387. ret = tasha_cdc_mclk_enable(component, enable, dapm);
  3388. } else {
  3389. dev_err(component->dev, "%s: unknown codec to enable ext clk\n",
  3390. __func__);
  3391. ret = -EINVAL;
  3392. }
  3393. return ret;
  3394. }
  3395. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_component *component,
  3396. int enable, bool dapm)
  3397. {
  3398. int ret = 0;
  3399. if (!strcmp(component.name, "tasha_codec")) {
  3400. ret = tasha_cdc_mclk_tx_enable(component, enable, dapm);
  3401. } else {
  3402. dev_err(component->dev, "%s: unknown codec to enable TX ext clk\n",
  3403. __func__);
  3404. ret = -EINVAL;
  3405. }
  3406. return ret;
  3407. }
  3408. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3409. struct snd_kcontrol *kcontrol, int event)
  3410. {
  3411. struct snd_soc_component *component =
  3412. snd_soc_dapm_to_component(w->dapm);
  3413. pr_debug("%s: event = %d\n", __func__, event);
  3414. switch (event) {
  3415. case SND_SOC_DAPM_PRE_PMU:
  3416. return msm_snd_enable_codec_ext_tx_clk(component, 1, true);
  3417. case SND_SOC_DAPM_POST_PMD:
  3418. return msm_snd_enable_codec_ext_tx_clk(component, 0, true);
  3419. }
  3420. return 0;
  3421. }
  3422. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3423. struct snd_kcontrol *kcontrol, int event)
  3424. {
  3425. struct snd_soc_component *component =
  3426. snd_soc_dapm_to_component(w->dapm);
  3427. pr_debug("%s: event = %d\n", __func__, event);
  3428. switch (event) {
  3429. case SND_SOC_DAPM_PRE_PMU:
  3430. return msm_snd_enable_codec_ext_clk(component, 1, true);
  3431. case SND_SOC_DAPM_POST_PMD:
  3432. return msm_snd_enable_codec_ext_clk(component, 0, true);
  3433. }
  3434. return 0;
  3435. }
  3436. static int msm_lineout_booster_ctrl_event(struct snd_soc_dapm_widget *w,
  3437. struct snd_kcontrol *k, int event)
  3438. {
  3439. struct snd_soc_component *component =
  3440. snd_soc_dapm_to_component(w->dapm);
  3441. struct snd_soc_card *card = component->card;
  3442. struct msm_asoc_mach_data *pdata =
  3443. snd_soc_card_get_drvdata(card);
  3444. pr_debug("%s: event = %d\n", __func__, event);
  3445. switch (event) {
  3446. case SND_SOC_DAPM_POST_PMU:
  3447. msm_cdc_pinctrl_select_active_state(
  3448. pdata->lineout_booster_gpio_p);
  3449. break;
  3450. case SND_SOC_DAPM_PRE_PMD:
  3451. msm_cdc_pinctrl_select_sleep_state(
  3452. pdata->lineout_booster_gpio_p);
  3453. break;
  3454. }
  3455. return 0;
  3456. }
  3457. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3458. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3459. msm_mclk_event,
  3460. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3461. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3462. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3463. SND_SOC_DAPM_SPK("lineout booster", msm_lineout_booster_ctrl_event),
  3464. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3465. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3466. };
  3467. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3468. struct snd_kcontrol *kcontrol, int event)
  3469. {
  3470. struct msm_asoc_mach_data *pdata = NULL;
  3471. struct snd_soc_component *component =
  3472. snd_soc_dapm_to_component(w->dapm);
  3473. int ret = 0;
  3474. uint32_t dmic_idx;
  3475. int *dmic_gpio_cnt;
  3476. struct device_node *dmic_gpio;
  3477. char *wname;
  3478. wname = strpbrk(w->name, "01234567");
  3479. if (!wname) {
  3480. dev_err(component->dev, "%s: widget not found\n", __func__);
  3481. return -EINVAL;
  3482. }
  3483. ret = kstrtouint(wname, 10, &dmic_idx);
  3484. if (ret < 0) {
  3485. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3486. __func__);
  3487. return -EINVAL;
  3488. }
  3489. pdata = snd_soc_card_get_drvdata(component->card);
  3490. switch (dmic_idx) {
  3491. case 0:
  3492. case 1:
  3493. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3494. dmic_gpio = pdata->dmic_01_gpio_p;
  3495. break;
  3496. case 2:
  3497. case 3:
  3498. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3499. dmic_gpio = pdata->dmic_23_gpio_p;
  3500. break;
  3501. case 4:
  3502. case 5:
  3503. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3504. dmic_gpio = pdata->dmic_45_gpio_p;
  3505. break;
  3506. case 6:
  3507. case 7:
  3508. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3509. dmic_gpio = pdata->dmic_67_gpio_p;
  3510. break;
  3511. default:
  3512. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3513. __func__);
  3514. return -EINVAL;
  3515. }
  3516. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3517. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3518. switch (event) {
  3519. case SND_SOC_DAPM_PRE_PMU:
  3520. (*dmic_gpio_cnt)++;
  3521. if (*dmic_gpio_cnt == 1) {
  3522. ret = msm_cdc_pinctrl_select_active_state(
  3523. dmic_gpio);
  3524. if (ret < 0) {
  3525. dev_err(component->dev, "%s: gpio set cannot be activated %sd\n",
  3526. __func__, "dmic_gpio");
  3527. return ret;
  3528. }
  3529. }
  3530. break;
  3531. case SND_SOC_DAPM_POST_PMD:
  3532. (*dmic_gpio_cnt)--;
  3533. if (*dmic_gpio_cnt == 0) {
  3534. ret = msm_cdc_pinctrl_select_sleep_state(
  3535. dmic_gpio);
  3536. if (ret < 0) {
  3537. dev_err(component->dev, "%s: gpio set cannot be de-activated %sd\n",
  3538. __func__, "dmic_gpio");
  3539. return ret;
  3540. }
  3541. }
  3542. break;
  3543. default:
  3544. dev_err(component->dev, "%s: invalid DAPM event %d\n",
  3545. __func__, event);
  3546. return -EINVAL;
  3547. }
  3548. return 0;
  3549. }
  3550. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3551. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3552. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3553. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3554. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3555. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3556. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3557. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3558. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3559. };
  3560. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3561. };
  3562. static inline int param_is_mask(int p)
  3563. {
  3564. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3565. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3566. }
  3567. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3568. int n)
  3569. {
  3570. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3571. }
  3572. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3573. unsigned int bit)
  3574. {
  3575. if (bit >= SNDRV_MASK_MAX)
  3576. return;
  3577. if (param_is_mask(n)) {
  3578. struct snd_mask *m = param_to_mask(p, n);
  3579. m->bits[0] = 0;
  3580. m->bits[1] = 0;
  3581. m->bits[bit >> 5] |= (1 << (bit & 31));
  3582. }
  3583. }
  3584. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3585. {
  3586. int ch_id = 0;
  3587. switch (be_id) {
  3588. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3589. ch_id = SLIM_RX_0;
  3590. break;
  3591. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3592. ch_id = SLIM_RX_1;
  3593. break;
  3594. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3595. ch_id = SLIM_RX_2;
  3596. break;
  3597. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3598. ch_id = SLIM_RX_3;
  3599. break;
  3600. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3601. ch_id = SLIM_RX_4;
  3602. break;
  3603. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3604. ch_id = SLIM_RX_6;
  3605. break;
  3606. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3607. ch_id = SLIM_TX_0;
  3608. break;
  3609. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3610. ch_id = SLIM_TX_3;
  3611. break;
  3612. default:
  3613. ch_id = SLIM_RX_0;
  3614. break;
  3615. }
  3616. return ch_id;
  3617. }
  3618. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3619. {
  3620. int idx = 0;
  3621. switch (be_id) {
  3622. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3623. idx = WSA_CDC_DMA_RX_0;
  3624. break;
  3625. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3626. idx = WSA_CDC_DMA_TX_0;
  3627. break;
  3628. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3629. idx = WSA_CDC_DMA_RX_1;
  3630. break;
  3631. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3632. idx = WSA_CDC_DMA_TX_1;
  3633. break;
  3634. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3635. idx = WSA_CDC_DMA_TX_2;
  3636. break;
  3637. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3638. idx = VA_CDC_DMA_TX_0;
  3639. break;
  3640. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3641. idx = VA_CDC_DMA_TX_1;
  3642. break;
  3643. default:
  3644. idx = VA_CDC_DMA_TX_0;
  3645. break;
  3646. }
  3647. return idx;
  3648. }
  3649. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3650. struct snd_pcm_hw_params *params)
  3651. {
  3652. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3653. struct snd_interval *rate = hw_param_interval(params,
  3654. SNDRV_PCM_HW_PARAM_RATE);
  3655. struct snd_interval *channels = hw_param_interval(params,
  3656. SNDRV_PCM_HW_PARAM_CHANNELS);
  3657. int rc = 0;
  3658. int idx;
  3659. void *config = NULL;
  3660. struct snd_soc_component *component = NULL;
  3661. pr_debug("%s: format = %d, rate = %d\n",
  3662. __func__, params_format(params), params_rate(params));
  3663. switch (dai_link->id) {
  3664. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3665. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3666. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3667. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3668. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3669. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3670. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3671. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3672. slim_rx_cfg[idx].bit_format);
  3673. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3674. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3675. break;
  3676. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3677. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3678. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3679. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3680. slim_tx_cfg[idx].bit_format);
  3681. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3682. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3683. break;
  3684. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3685. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3686. slim_tx_cfg[1].bit_format);
  3687. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3688. channels->min = channels->max = slim_tx_cfg[1].channels;
  3689. break;
  3690. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3691. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3692. SNDRV_PCM_FORMAT_S32_LE);
  3693. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3694. channels->min = channels->max = msm_vi_feed_tx_ch;
  3695. break;
  3696. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3697. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3698. slim_rx_cfg[5].bit_format);
  3699. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3700. channels->min = channels->max = slim_rx_cfg[5].channels;
  3701. break;
  3702. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3703. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  3704. if (!component) {
  3705. pr_err("%s: component is NULL\n", __func__);
  3706. return -EINVAL;
  3707. }
  3708. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3709. channels->min = channels->max = 1;
  3710. config = msm_codec_fn.get_afe_config_fn(component,
  3711. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3712. if (config) {
  3713. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3714. config, SLIMBUS_5_TX);
  3715. if (rc)
  3716. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3717. __func__, rc);
  3718. }
  3719. break;
  3720. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3721. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3722. slim_rx_cfg[SLIM_RX_7].bit_format);
  3723. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3724. channels->min = channels->max =
  3725. slim_rx_cfg[SLIM_RX_7].channels;
  3726. break;
  3727. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3728. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3729. channels->min = channels->max =
  3730. slim_tx_cfg[SLIM_TX_7].channels;
  3731. break;
  3732. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3733. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3734. channels->min = channels->max =
  3735. slim_tx_cfg[SLIM_TX_8].channels;
  3736. break;
  3737. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  3738. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3739. slim_tx_cfg[SLIM_TX_9].bit_format);
  3740. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  3741. channels->min = channels->max =
  3742. slim_tx_cfg[SLIM_TX_9].channels;
  3743. break;
  3744. case MSM_BACKEND_DAI_USB_RX:
  3745. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3746. usb_rx_cfg.bit_format);
  3747. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3748. channels->min = channels->max = usb_rx_cfg.channels;
  3749. break;
  3750. case MSM_BACKEND_DAI_USB_TX:
  3751. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3752. usb_tx_cfg.bit_format);
  3753. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3754. channels->min = channels->max = usb_tx_cfg.channels;
  3755. break;
  3756. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3757. channels->min = channels->max = proxy_rx_cfg.channels;
  3758. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3759. break;
  3760. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3761. channels->min = channels->max =
  3762. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3763. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3764. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3765. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3766. break;
  3767. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3768. channels->min = channels->max =
  3769. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3770. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3771. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3772. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3773. break;
  3774. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3775. channels->min = channels->max =
  3776. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3777. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3778. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3779. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3780. break;
  3781. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3782. channels->min = channels->max =
  3783. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3784. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3785. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3786. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3787. break;
  3788. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3789. channels->min = channels->max =
  3790. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3791. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3792. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3793. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3794. break;
  3795. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3796. channels->min = channels->max =
  3797. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3798. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3799. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3800. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3801. break;
  3802. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3803. channels->min = channels->max =
  3804. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3805. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3806. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3807. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3808. break;
  3809. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3810. channels->min = channels->max =
  3811. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3812. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3813. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3814. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3815. break;
  3816. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3817. channels->min = channels->max =
  3818. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3819. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3820. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3821. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3822. break;
  3823. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3824. channels->min = channels->max =
  3825. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3826. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3827. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3828. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3829. break;
  3830. case MSM_BACKEND_DAI_AUXPCM_RX:
  3831. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3832. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3833. rate->min = rate->max =
  3834. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3835. channels->min = channels->max =
  3836. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3837. break;
  3838. case MSM_BACKEND_DAI_AUXPCM_TX:
  3839. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3840. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3841. rate->min = rate->max =
  3842. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3843. channels->min = channels->max =
  3844. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3845. break;
  3846. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3847. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3848. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3849. rate->min = rate->max =
  3850. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3851. channels->min = channels->max =
  3852. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3853. break;
  3854. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3855. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3856. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3857. rate->min = rate->max =
  3858. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3859. channels->min = channels->max =
  3860. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3861. break;
  3862. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3863. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3864. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3865. rate->min = rate->max =
  3866. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3867. channels->min = channels->max =
  3868. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3869. break;
  3870. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3871. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3872. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3873. rate->min = rate->max =
  3874. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3875. channels->min = channels->max =
  3876. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3877. break;
  3878. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3879. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3880. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3881. rate->min = rate->max =
  3882. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3883. channels->min = channels->max =
  3884. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3885. break;
  3886. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3887. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3888. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3889. rate->min = rate->max =
  3890. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3891. channels->min = channels->max =
  3892. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3893. break;
  3894. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3895. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3896. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3897. rate->min = rate->max =
  3898. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3899. channels->min = channels->max =
  3900. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3901. break;
  3902. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3903. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3904. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3905. rate->min = rate->max =
  3906. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3907. channels->min = channels->max =
  3908. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3909. break;
  3910. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3911. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3912. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3913. rate->min = rate->max =
  3914. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3915. channels->min = channels->max =
  3916. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3917. break;
  3918. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3919. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3920. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3921. rate->min = rate->max =
  3922. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3923. channels->min = channels->max =
  3924. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3925. break;
  3926. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3927. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3928. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3929. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3930. channels->min = channels->max =
  3931. mi2s_rx_cfg[PRIM_MI2S].channels;
  3932. break;
  3933. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3934. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3935. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3936. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3937. channels->min = channels->max =
  3938. mi2s_tx_cfg[PRIM_MI2S].channels;
  3939. break;
  3940. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3941. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3942. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3943. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3944. channels->min = channels->max =
  3945. mi2s_rx_cfg[SEC_MI2S].channels;
  3946. break;
  3947. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3948. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3949. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3950. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3951. channels->min = channels->max =
  3952. mi2s_tx_cfg[SEC_MI2S].channels;
  3953. break;
  3954. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3955. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3956. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3957. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3958. channels->min = channels->max =
  3959. mi2s_rx_cfg[TERT_MI2S].channels;
  3960. break;
  3961. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3962. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3963. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3964. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3965. channels->min = channels->max =
  3966. mi2s_tx_cfg[TERT_MI2S].channels;
  3967. break;
  3968. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3969. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3970. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3971. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3972. channels->min = channels->max =
  3973. mi2s_rx_cfg[QUAT_MI2S].channels;
  3974. break;
  3975. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3976. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3977. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3978. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3979. channels->min = channels->max =
  3980. mi2s_tx_cfg[QUAT_MI2S].channels;
  3981. break;
  3982. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3983. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3984. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3985. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3986. channels->min = channels->max =
  3987. mi2s_rx_cfg[QUIN_MI2S].channels;
  3988. break;
  3989. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3990. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3991. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3992. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3993. channels->min = channels->max =
  3994. mi2s_tx_cfg[QUIN_MI2S].channels;
  3995. break;
  3996. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3997. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3998. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3999. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  4000. channels->min = channels->max =
  4001. mi2s_rx_cfg[SEN_MI2S].channels;
  4002. break;
  4003. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4004. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4005. mi2s_tx_cfg[SEN_MI2S].bit_format);
  4006. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  4007. channels->min = channels->max =
  4008. mi2s_tx_cfg[SEN_MI2S].channels;
  4009. break;
  4010. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4011. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4012. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4013. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4014. cdc_dma_rx_cfg[idx].bit_format);
  4015. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  4016. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  4017. break;
  4018. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4019. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4020. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4021. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4022. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4023. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4024. cdc_dma_tx_cfg[idx].bit_format);
  4025. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  4026. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  4027. break;
  4028. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4029. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4030. SNDRV_PCM_FORMAT_S32_LE);
  4031. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  4032. channels->min = channels->max = msm_vi_feed_tx_ch;
  4033. break;
  4034. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  4035. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4036. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  4037. rate->min = rate->max =
  4038. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  4039. channels->min = channels->max =
  4040. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  4041. break;
  4042. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  4043. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4044. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  4045. rate->min = rate->max =
  4046. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  4047. channels->min = channels->max =
  4048. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  4049. break;
  4050. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  4051. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4052. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  4053. rate->min = rate->max =
  4054. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  4055. channels->min = channels->max =
  4056. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4057. break;
  4058. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4059. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4060. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4061. rate->min = rate->max =
  4062. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4063. channels->min = channels->max =
  4064. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4065. break;
  4066. default:
  4067. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4068. break;
  4069. }
  4070. return rc;
  4071. }
  4072. static int msm_afe_set_config(struct snd_soc_component *component)
  4073. {
  4074. int ret = 0;
  4075. void *config_data = NULL;
  4076. if (!msm_codec_fn.get_afe_config_fn) {
  4077. dev_err(component->dev, "%s: codec get afe config not init'ed\n",
  4078. __func__);
  4079. return -EINVAL;
  4080. }
  4081. config_data = msm_codec_fn.get_afe_config_fn(component,
  4082. AFE_CDC_REGISTERS_CONFIG);
  4083. if (config_data) {
  4084. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4085. if (ret) {
  4086. dev_err(component->dev,
  4087. "%s: Failed to set codec registers config %d\n",
  4088. __func__, ret);
  4089. return ret;
  4090. }
  4091. }
  4092. config_data = msm_codec_fn.get_afe_config_fn(component,
  4093. AFE_CDC_REGISTER_PAGE_CONFIG);
  4094. if (config_data) {
  4095. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4096. 0);
  4097. if (ret)
  4098. dev_err(component->dev,
  4099. "%s: Failed to set cdc register page config\n",
  4100. __func__);
  4101. }
  4102. config_data = msm_codec_fn.get_afe_config_fn(component,
  4103. AFE_SLIMBUS_SLAVE_CONFIG);
  4104. if (config_data) {
  4105. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4106. if (ret) {
  4107. dev_err(component->dev,
  4108. "%s: Failed to set slimbus slave config %d\n",
  4109. __func__, ret);
  4110. return ret;
  4111. }
  4112. }
  4113. return 0;
  4114. }
  4115. static void msm_afe_clear_config(void)
  4116. {
  4117. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4118. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4119. }
  4120. static int msm_adsp_power_up_config(struct snd_soc_component *component,
  4121. struct snd_card *card)
  4122. {
  4123. int ret = 0;
  4124. unsigned long timeout;
  4125. int adsp_ready = 0;
  4126. bool snd_card_online = 0;
  4127. timeout = jiffies +
  4128. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4129. do {
  4130. if (!snd_card_online) {
  4131. snd_card_online = snd_card_is_online_state(card);
  4132. pr_debug("%s: Sound card is %s\n", __func__,
  4133. snd_card_online ? "Online" : "Offline");
  4134. }
  4135. if (!adsp_ready) {
  4136. adsp_ready = q6core_is_adsp_ready();
  4137. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4138. adsp_ready ? "ready" : "not ready");
  4139. }
  4140. if (snd_card_online && adsp_ready)
  4141. break;
  4142. /*
  4143. * Sound card/ADSP will be coming up after subsystem restart and
  4144. * it might not be fully up when the control reaches
  4145. * here. So, wait for 50msec before checking ADSP state
  4146. */
  4147. msleep(50);
  4148. } while (time_after(timeout, jiffies));
  4149. if (!snd_card_online || !adsp_ready) {
  4150. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4151. __func__,
  4152. snd_card_online ? "Online" : "Offline",
  4153. adsp_ready ? "ready" : "not ready");
  4154. ret = -ETIMEDOUT;
  4155. goto err;
  4156. }
  4157. ret = msm_afe_set_config(component);
  4158. if (ret)
  4159. pr_err("%s: Failed to set AFE config. err %d\n",
  4160. __func__, ret);
  4161. return 0;
  4162. err:
  4163. return ret;
  4164. }
  4165. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4166. unsigned long opcode, void *ptr)
  4167. {
  4168. int ret;
  4169. struct snd_soc_card *card = NULL;
  4170. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4171. struct snd_soc_pcm_runtime *rtd;
  4172. struct snd_soc_dai *codec_dai;
  4173. struct snd_soc_component *component;
  4174. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4175. switch (opcode) {
  4176. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4177. /*
  4178. * Use flag to ignore initial boot notifications
  4179. * On initial boot msm_adsp_power_up_config is
  4180. * called on init. There is no need to clear
  4181. * and set the config again on initial boot.
  4182. */
  4183. if (is_initial_boot)
  4184. break;
  4185. msm_afe_clear_config();
  4186. break;
  4187. case AUDIO_NOTIFIER_SERVICE_UP:
  4188. if (is_initial_boot) {
  4189. is_initial_boot = false;
  4190. break;
  4191. }
  4192. if (!spdev)
  4193. return -EINVAL;
  4194. card = platform_get_drvdata(spdev);
  4195. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4196. if (!rtd) {
  4197. dev_err(card->dev,
  4198. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4199. __func__, be_dl_name);
  4200. ret = -EINVAL;
  4201. goto err;
  4202. }
  4203. codec_dai = rtd->codec_dai;
  4204. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec"))
  4205. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4206. ret = msm_adsp_power_up_config(component, card->snd_card);
  4207. if (ret < 0) {
  4208. dev_err(card->dev,
  4209. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4210. __func__, ret);
  4211. goto err;
  4212. }
  4213. break;
  4214. default:
  4215. break;
  4216. }
  4217. err:
  4218. return NOTIFY_OK;
  4219. }
  4220. static struct notifier_block service_nb = {
  4221. .notifier_call = qcs405_notifier_service_cb,
  4222. .priority = -INT_MAX,
  4223. };
  4224. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4225. {
  4226. int ret = 0;
  4227. void *config_data;
  4228. struct snd_soc_component *component;
  4229. struct snd_soc_dapm_context *dapm;
  4230. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4231. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4232. struct snd_card *card;
  4233. struct msm_asoc_mach_data *pdata =
  4234. snd_soc_card_get_drvdata(rtd->card);
  4235. /*
  4236. * Codec SLIMBUS configuration
  4237. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4238. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4239. * TX14, TX15, TX16
  4240. */
  4241. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4242. 151, 152, 153, 154, 155, 156};
  4243. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4244. 134, 135, 136, 137, 138, 139,
  4245. 140, 141, 142, 143};
  4246. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4247. rtd->pmdown_time = 0;
  4248. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) {
  4249. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4250. dapm = snd_soc_component_get_dapm(component);
  4251. }
  4252. ret = snd_soc_add_component_controls(component, msm_snd_sb_controls,
  4253. ARRAY_SIZE(msm_snd_sb_controls));
  4254. if (ret < 0) {
  4255. pr_err("%s: add_codec_controls failed, err %d\n",
  4256. __func__, ret);
  4257. return ret;
  4258. }
  4259. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4260. ARRAY_SIZE(msm_dapm_widgets));
  4261. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4262. ARRAY_SIZE(wcd_audio_paths));
  4263. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4264. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4265. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4266. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4267. snd_soc_dapm_sync(dapm);
  4268. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4269. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4270. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4271. ret = msm_adsp_power_up_config(component, rtd->card->snd_card);
  4272. if (ret) {
  4273. dev_err(component->dev, "%s: Failed to set AFE config %d\n",
  4274. __func__, ret);
  4275. goto err;
  4276. }
  4277. config_data = msm_codec_fn.get_afe_config_fn(component,
  4278. AFE_AANC_VERSION);
  4279. if (config_data) {
  4280. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4281. if (ret) {
  4282. dev_err(component->dev, "%s: Failed to set aanc version %d\n",
  4283. __func__, ret);
  4284. goto err;
  4285. }
  4286. }
  4287. card = rtd->card->snd_card;
  4288. if (!pdata->codec_root)
  4289. pdata->codec_root = snd_info_create_subdir(card->module,
  4290. "codecs", card->proc_root);
  4291. if (!pdata->codec_root) {
  4292. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4293. __func__);
  4294. ret = 0;
  4295. goto err;
  4296. }
  4297. tasha_codec_info_create_codec_entry(pdata->codec_root, component);
  4298. codec_reg_done = true;
  4299. return 0;
  4300. err:
  4301. return ret;
  4302. }
  4303. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4304. {
  4305. int ret = 0;
  4306. struct snd_soc_component *component;
  4307. struct snd_soc_dapm_context *dapm;
  4308. struct snd_card *card;
  4309. struct msm_asoc_mach_data *pdata =
  4310. snd_soc_card_get_drvdata(rtd->card);
  4311. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4312. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4313. if (!component) {
  4314. pr_err("%s: component is NULL\n", __func__);
  4315. return -EINVAL;
  4316. }
  4317. dapm = snd_soc_component_get_dapm(component);
  4318. ret = snd_soc_add_component_controls(component, msm_snd_va_controls,
  4319. ARRAY_SIZE(msm_snd_va_controls));
  4320. if (ret < 0) {
  4321. dev_err(component->dev, "%s: add_component_controls for va failed, err %d\n",
  4322. __func__, ret);
  4323. return ret;
  4324. }
  4325. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4326. ARRAY_SIZE(msm_va_dapm_widgets));
  4327. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4328. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4329. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4330. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4331. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4332. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4333. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4334. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4335. snd_soc_dapm_sync(dapm);
  4336. card = rtd->card->snd_card;
  4337. if (!pdata->codec_root)
  4338. pdata->codec_root = snd_info_create_subdir(card->module,
  4339. "codecs", card->proc_root);
  4340. if (!pdata->codec_root) {
  4341. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4342. __func__);
  4343. ret = 0;
  4344. goto done;
  4345. }
  4346. bolero_info_create_codec_entry(pdata->codec_root, component);
  4347. done:
  4348. return ret;
  4349. }
  4350. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4351. {
  4352. int ret = 0;
  4353. struct snd_soc_component *component = NULL;
  4354. struct snd_soc_dapm_context *dapm = NULL;
  4355. struct snd_soc_component *aux_comp = NULL;
  4356. struct snd_card *card = NULL;
  4357. struct msm_asoc_mach_data *pdata =
  4358. snd_soc_card_get_drvdata(rtd->card);
  4359. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4360. if (!component) {
  4361. pr_err("%s: component is NULL\n", __func__);
  4362. return -EINVAL;
  4363. }
  4364. dapm = snd_soc_component_get_dapm(component);
  4365. ret = snd_soc_add_component_controls(component, msm_snd_wsa_controls,
  4366. ARRAY_SIZE(msm_snd_wsa_controls));
  4367. if (ret < 0) {
  4368. dev_err(component->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4369. __func__, ret);
  4370. return ret;
  4371. }
  4372. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4373. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4374. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4375. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4376. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4377. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4378. snd_soc_dapm_sync(dapm);
  4379. /*
  4380. * Send speaker configuration only for WSA8810.
  4381. * Default configuration is for WSA8815.
  4382. */
  4383. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4384. __func__, rtd->card->num_aux_devs);
  4385. if (rtd->card->num_aux_devs &&
  4386. !list_empty(&rtd->card->component_dev_list)) {
  4387. aux_comp = list_first_entry(
  4388. &rtd->card->component_dev_list,
  4389. struct snd_soc_component,
  4390. card_aux_list);
  4391. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4392. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4393. wsa_macro_set_spkr_mode(component,
  4394. WSA_MACRO_SPKR_MODE_1);
  4395. wsa_macro_set_spkr_gain_offset(component,
  4396. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4397. }
  4398. }
  4399. card = rtd->card->snd_card;
  4400. if (!pdata->codec_root)
  4401. pdata->codec_root = snd_info_create_subdir(card->module,
  4402. "codecs", card->proc_root);
  4403. if (!pdata->codec_root) {
  4404. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  4405. __func__);
  4406. ret = 0;
  4407. goto done;
  4408. }
  4409. bolero_info_create_codec_entry(pdata->codec_root, component);
  4410. done:
  4411. return ret;
  4412. }
  4413. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4414. {
  4415. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4416. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  4417. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4418. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4419. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4420. }
  4421. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4422. struct snd_pcm_hw_params *params)
  4423. {
  4424. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4425. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4426. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4427. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4428. int ret = 0;
  4429. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4430. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4431. u32 user_set_tx_ch = 0;
  4432. u32 rx_ch_count;
  4433. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4434. ret = snd_soc_dai_get_channel_map(codec_dai,
  4435. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4436. if (ret < 0) {
  4437. pr_err("%s: failed to get codec chan map, err:%d\n",
  4438. __func__, ret);
  4439. goto err;
  4440. }
  4441. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4442. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4443. slim_rx_cfg[5].channels);
  4444. rx_ch_count = slim_rx_cfg[5].channels;
  4445. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4446. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4447. slim_rx_cfg[2].channels);
  4448. rx_ch_count = slim_rx_cfg[2].channels;
  4449. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4450. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4451. slim_rx_cfg[6].channels);
  4452. rx_ch_count = slim_rx_cfg[6].channels;
  4453. } else {
  4454. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4455. slim_rx_cfg[0].channels);
  4456. rx_ch_count = slim_rx_cfg[0].channels;
  4457. }
  4458. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4459. rx_ch_count, rx_ch);
  4460. if (ret < 0) {
  4461. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4462. __func__, ret);
  4463. goto err;
  4464. }
  4465. } else {
  4466. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4467. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4468. ret = snd_soc_dai_get_channel_map(codec_dai,
  4469. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4470. if (ret < 0) {
  4471. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4472. __func__, ret);
  4473. goto err;
  4474. }
  4475. /* For <codec>_tx1 case */
  4476. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4477. user_set_tx_ch = slim_tx_cfg[0].channels;
  4478. /* For <codec>_tx3 case */
  4479. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4480. user_set_tx_ch = slim_tx_cfg[1].channels;
  4481. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4482. user_set_tx_ch = msm_vi_feed_tx_ch;
  4483. else
  4484. user_set_tx_ch = tx_ch_cnt;
  4485. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4486. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4487. tx_ch_cnt, dai_link->id);
  4488. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4489. user_set_tx_ch, tx_ch, 0, 0);
  4490. if (ret < 0)
  4491. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4492. __func__, ret);
  4493. }
  4494. err:
  4495. return ret;
  4496. }
  4497. static int msm_snd_auxpcm_startup(struct snd_pcm_substream *substream)
  4498. {
  4499. int ret = 0;
  4500. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4501. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4502. ret = qcs405_send_island_vad_config(dai_link->id);
  4503. if (ret) {
  4504. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4505. __func__, ret);
  4506. }
  4507. return ret;
  4508. }
  4509. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4510. {
  4511. int ret = 0;
  4512. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4513. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4514. ret = qcs405_send_island_vad_config(dai_link->id);
  4515. if (ret) {
  4516. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4517. __func__, ret);
  4518. }
  4519. return ret;
  4520. }
  4521. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4522. struct snd_pcm_hw_params *params)
  4523. {
  4524. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4525. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4526. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4527. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4528. int ret = 0;
  4529. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4530. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4531. u32 user_set_tx_ch = 0;
  4532. u32 user_set_rx_ch = 0;
  4533. u32 ch_id;
  4534. ret = snd_soc_dai_get_channel_map(codec_dai,
  4535. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4536. &rx_ch_cdc_dma);
  4537. if (ret < 0) {
  4538. pr_err("%s: failed to get codec chan map, err:%d\n",
  4539. __func__, ret);
  4540. goto err;
  4541. }
  4542. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4543. switch (dai_link->id) {
  4544. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4545. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4546. {
  4547. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4548. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4549. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4550. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4551. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4552. user_set_rx_ch, &rx_ch_cdc_dma);
  4553. if (ret < 0) {
  4554. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4555. __func__, ret);
  4556. goto err;
  4557. }
  4558. }
  4559. break;
  4560. }
  4561. } else {
  4562. switch (dai_link->id) {
  4563. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4564. {
  4565. user_set_tx_ch = msm_vi_feed_tx_ch;
  4566. }
  4567. break;
  4568. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4569. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4570. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4571. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4572. {
  4573. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4574. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4575. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4576. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4577. }
  4578. break;
  4579. }
  4580. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4581. &tx_ch_cdc_dma, 0, 0);
  4582. if (ret < 0) {
  4583. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4584. __func__, ret);
  4585. goto err;
  4586. }
  4587. }
  4588. err:
  4589. return ret;
  4590. }
  4591. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4592. struct snd_pcm_hw_params *params)
  4593. {
  4594. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4595. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4596. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4597. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4598. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4599. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4600. int ret;
  4601. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4602. codec_dai->name, codec_dai->id);
  4603. ret = snd_soc_dai_get_channel_map(codec_dai,
  4604. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4605. if (ret) {
  4606. dev_err(rtd->dev,
  4607. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4608. __func__, ret);
  4609. goto err;
  4610. }
  4611. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4612. __func__, tx_ch_cnt, dai_link->id);
  4613. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4614. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4615. if (ret)
  4616. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4617. __func__, ret);
  4618. err:
  4619. return ret;
  4620. }
  4621. static int msm_get_port_id(int be_id)
  4622. {
  4623. int afe_port_id;
  4624. switch (be_id) {
  4625. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4626. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4627. break;
  4628. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4629. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4630. break;
  4631. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4632. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4633. break;
  4634. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4635. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4636. break;
  4637. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4638. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4639. break;
  4640. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4641. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4642. break;
  4643. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4644. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4645. break;
  4646. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4647. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4648. break;
  4649. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4650. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4651. break;
  4652. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4653. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4654. break;
  4655. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4656. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  4657. break;
  4658. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4659. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  4660. break;
  4661. default:
  4662. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4663. afe_port_id = -EINVAL;
  4664. }
  4665. return afe_port_id;
  4666. }
  4667. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4668. {
  4669. u32 bit_per_sample;
  4670. switch (bit_format) {
  4671. case SNDRV_PCM_FORMAT_S32_LE:
  4672. case SNDRV_PCM_FORMAT_S24_3LE:
  4673. case SNDRV_PCM_FORMAT_S24_LE:
  4674. bit_per_sample = 32;
  4675. break;
  4676. case SNDRV_PCM_FORMAT_S16_LE:
  4677. default:
  4678. bit_per_sample = 16;
  4679. break;
  4680. }
  4681. return bit_per_sample;
  4682. }
  4683. static void update_mi2s_clk_val(int dai_id, int stream)
  4684. {
  4685. u32 bit_per_sample;
  4686. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4687. bit_per_sample =
  4688. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4689. mi2s_clk[dai_id].clk_freq_in_hz =
  4690. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4691. } else {
  4692. bit_per_sample =
  4693. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4694. mi2s_clk[dai_id].clk_freq_in_hz =
  4695. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4696. }
  4697. }
  4698. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4699. {
  4700. int ret = 0;
  4701. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4702. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4703. int port_id = 0;
  4704. int index = cpu_dai->id;
  4705. port_id = msm_get_port_id(rtd->dai_link->id);
  4706. if (port_id < 0) {
  4707. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4708. ret = port_id;
  4709. goto err;
  4710. }
  4711. if (enable) {
  4712. update_mi2s_clk_val(index, substream->stream);
  4713. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4714. mi2s_clk[index].clk_freq_in_hz);
  4715. }
  4716. mi2s_clk[index].enable = enable;
  4717. ret = afe_set_lpass_clock_v2(port_id,
  4718. &mi2s_clk[index]);
  4719. if (ret < 0) {
  4720. dev_err(rtd->card->dev,
  4721. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4722. __func__, port_id, ret);
  4723. goto err;
  4724. }
  4725. err:
  4726. return ret;
  4727. }
  4728. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4729. struct snd_pcm_hw_params *params)
  4730. {
  4731. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4732. struct snd_interval *rate = hw_param_interval(params,
  4733. SNDRV_PCM_HW_PARAM_RATE);
  4734. struct snd_interval *channels = hw_param_interval(params,
  4735. SNDRV_PCM_HW_PARAM_CHANNELS);
  4736. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4737. channels->min = channels->max =
  4738. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4739. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4740. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4741. rate->min = rate->max =
  4742. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4743. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4744. channels->min = channels->max =
  4745. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4746. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4747. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4748. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4749. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4750. channels->min = channels->max =
  4751. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4752. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4753. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4754. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4755. } else {
  4756. pr_err("%s: dai id 0x%x not supported\n",
  4757. __func__, cpu_dai->id);
  4758. return -EINVAL;
  4759. }
  4760. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4761. __func__, cpu_dai->id, channels->max, rate->max,
  4762. params_format(params));
  4763. return 0;
  4764. }
  4765. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4766. struct snd_pcm_hw_params *params)
  4767. {
  4768. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4769. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4770. int ret = 0;
  4771. int slot_width = 32;
  4772. int channels, slots = 8;
  4773. unsigned int slot_mask, rate, clk_freq;
  4774. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4775. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4776. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4777. switch (cpu_dai->id) {
  4778. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4779. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4780. break;
  4781. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4782. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4783. break;
  4784. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4785. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4786. break;
  4787. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4788. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4789. break;
  4790. case AFE_PORT_ID_QUINARY_TDM_RX:
  4791. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4792. break;
  4793. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4794. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4795. break;
  4796. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4797. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4798. break;
  4799. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4800. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4801. break;
  4802. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4803. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4804. break;
  4805. case AFE_PORT_ID_QUINARY_TDM_TX:
  4806. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4807. break;
  4808. default:
  4809. pr_err("%s: dai id 0x%x not supported\n",
  4810. __func__, cpu_dai->id);
  4811. return -EINVAL;
  4812. }
  4813. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4814. /*2 slot config - bits 0 and 1 set for the first two slots */
  4815. slot_mask = 0x0000FFFF >> (16-channels);
  4816. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4817. __func__, slot_width, slots);
  4818. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4819. slots, slot_width);
  4820. if (ret < 0) {
  4821. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4822. __func__, ret);
  4823. goto end;
  4824. }
  4825. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4826. 0, NULL, channels, slot_offset);
  4827. if (ret < 0) {
  4828. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4829. __func__, ret);
  4830. goto end;
  4831. }
  4832. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4833. /*2 slot config - bits 0 and 1 set for the first two slots */
  4834. slot_mask = 0x0000FFFF >> (16-channels);
  4835. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4836. __func__, slot_width, slots);
  4837. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4838. slots, slot_width);
  4839. if (ret < 0) {
  4840. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4841. __func__, ret);
  4842. goto end;
  4843. }
  4844. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4845. channels, slot_offset, 0, NULL);
  4846. if (ret < 0) {
  4847. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4848. __func__, ret);
  4849. goto end;
  4850. }
  4851. } else {
  4852. ret = -EINVAL;
  4853. pr_err("%s: invalid use case, err:%d\n",
  4854. __func__, ret);
  4855. goto end;
  4856. }
  4857. rate = params_rate(params);
  4858. clk_freq = rate * slot_width * slots;
  4859. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4860. if (ret < 0)
  4861. pr_err("%s: failed to set tdm clk, err:%d\n",
  4862. __func__, ret);
  4863. end:
  4864. return ret;
  4865. }
  4866. static int msm_get_tdm_mode(u32 port_id)
  4867. {
  4868. u32 tdm_mode;
  4869. switch (port_id) {
  4870. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4871. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4872. tdm_mode = TDM_PRI;
  4873. break;
  4874. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4875. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4876. tdm_mode = TDM_SEC;
  4877. break;
  4878. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4879. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4880. tdm_mode = TDM_TERT;
  4881. break;
  4882. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4883. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4884. tdm_mode = TDM_QUAT;
  4885. break;
  4886. case AFE_PORT_ID_QUINARY_TDM_RX:
  4887. case AFE_PORT_ID_QUINARY_TDM_TX:
  4888. tdm_mode = TDM_QUIN;
  4889. break;
  4890. default:
  4891. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4892. tdm_mode = -EINVAL;
  4893. }
  4894. return tdm_mode;
  4895. }
  4896. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4897. {
  4898. int ret = 0;
  4899. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4900. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4901. struct snd_soc_card *card = rtd->card;
  4902. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4903. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4904. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4905. if (tdm_mode >= TDM_INTERFACE_MAX) {
  4906. ret = -EINVAL;
  4907. pr_err("%s: Invalid TDM interface %d\n",
  4908. __func__, ret);
  4909. return ret;
  4910. }
  4911. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4912. ret = msm_cdc_pinctrl_select_active_state(
  4913. pdata->mi2s_gpio_p[tdm_mode]);
  4914. if (ret)
  4915. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4916. __func__, ret);
  4917. }
  4918. /* Enable Mic bias for TDM Mics */
  4919. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4920. if (pdata->tdm_micb_supply) {
  4921. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  4922. pdata->tdm_micb_voltage,
  4923. pdata->tdm_micb_voltage);
  4924. if (ret) {
  4925. pr_err("%s: Setting voltage failed, err = %d\n",
  4926. __func__, ret);
  4927. return ret;
  4928. }
  4929. ret = regulator_set_load(pdata->tdm_micb_supply,
  4930. pdata->tdm_micb_current);
  4931. if (ret) {
  4932. pr_err("%s: Setting current failed, err = %d\n",
  4933. __func__, ret);
  4934. return ret;
  4935. }
  4936. ret = regulator_enable(pdata->tdm_micb_supply);
  4937. if (ret) {
  4938. pr_err("%s: regulator enable failed, err = %d\n",
  4939. __func__, ret);
  4940. return ret;
  4941. }
  4942. }
  4943. }
  4944. ret = qcs405_send_island_vad_config(dai_link->id);
  4945. if (ret) {
  4946. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4947. __func__, ret);
  4948. return ret;
  4949. }
  4950. return ret;
  4951. }
  4952. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4953. {
  4954. int ret = 0;
  4955. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4956. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4957. struct snd_soc_card *card = rtd->card;
  4958. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4959. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4960. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4961. if (pdata->tdm_micb_supply) {
  4962. ret = regulator_disable(pdata->tdm_micb_supply);
  4963. if (ret)
  4964. pr_err("%s: regulator disable failed, err = %d\n",
  4965. __func__, ret);
  4966. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  4967. pdata->tdm_micb_voltage);
  4968. regulator_set_load(pdata->tdm_micb_supply, 0);
  4969. }
  4970. }
  4971. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4972. ret = msm_cdc_pinctrl_select_sleep_state(
  4973. pdata->mi2s_gpio_p[tdm_mode]);
  4974. if (ret)
  4975. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4976. __func__, ret);
  4977. }
  4978. }
  4979. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4980. .hw_params = qcs405_tdm_snd_hw_params,
  4981. .startup = qcs405_tdm_snd_startup,
  4982. .shutdown = qcs405_tdm_snd_shutdown
  4983. };
  4984. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4985. {
  4986. cpumask_t mask;
  4987. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4988. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4989. cpumask_clear(&mask);
  4990. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4991. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4992. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4993. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4994. pm_qos_add_request(&substream->latency_pm_qos_req,
  4995. PM_QOS_CPU_DMA_LATENCY,
  4996. MSM_LL_QOS_VALUE);
  4997. return 0;
  4998. }
  4999. static struct snd_soc_ops msm_fe_qos_ops = {
  5000. .prepare = msm_fe_qos_prepare,
  5001. };
  5002. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  5003. {
  5004. int ret = 0;
  5005. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5006. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5007. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5008. int index = cpu_dai->id;
  5009. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  5010. struct snd_soc_card *card = rtd->card;
  5011. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5012. dev_dbg(rtd->card->dev,
  5013. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5014. __func__, substream->name, substream->stream,
  5015. cpu_dai->name, cpu_dai->id);
  5016. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5017. ret = -EINVAL;
  5018. dev_err(rtd->card->dev,
  5019. "%s: CPU DAI id (%d) out of range\n",
  5020. __func__, cpu_dai->id);
  5021. goto err;
  5022. }
  5023. /*
  5024. * Mutex protection in case the same MI2S
  5025. * interface using for both TX and RX so
  5026. * that the same clock won't be enable twice.
  5027. */
  5028. mutex_lock(&mi2s_intf_conf[index].lock);
  5029. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  5030. /* Check if msm needs to provide the clock to the interface */
  5031. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  5032. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  5033. fmt = SND_SOC_DAIFMT_CBM_CFM;
  5034. }
  5035. ret = msm_mi2s_set_sclk(substream, true);
  5036. if (ret < 0) {
  5037. dev_err(rtd->card->dev,
  5038. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  5039. __func__, ret);
  5040. goto clean_up;
  5041. }
  5042. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  5043. if (ret < 0) {
  5044. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  5045. __func__, index, ret);
  5046. goto clk_off;
  5047. }
  5048. if (pdata->mi2s_gpio_p[index])
  5049. msm_cdc_pinctrl_select_active_state(
  5050. pdata->mi2s_gpio_p[index]);
  5051. }
  5052. ret = qcs405_send_island_vad_config(dai_link->id);
  5053. if (ret) {
  5054. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5055. __func__, ret);
  5056. return ret;
  5057. }
  5058. clk_off:
  5059. if (ret < 0)
  5060. msm_mi2s_set_sclk(substream, false);
  5061. clean_up:
  5062. if (ret < 0)
  5063. mi2s_intf_conf[index].ref_cnt--;
  5064. mutex_unlock(&mi2s_intf_conf[index].lock);
  5065. err:
  5066. return ret;
  5067. }
  5068. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  5069. {
  5070. int ret;
  5071. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5072. int index = rtd->cpu_dai->id;
  5073. struct snd_soc_card *card = rtd->card;
  5074. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5075. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5076. substream->name, substream->stream);
  5077. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5078. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  5079. return;
  5080. }
  5081. mutex_lock(&mi2s_intf_conf[index].lock);
  5082. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  5083. if (pdata->mi2s_gpio_p[index])
  5084. msm_cdc_pinctrl_select_sleep_state(
  5085. pdata->mi2s_gpio_p[index]);
  5086. ret = msm_mi2s_set_sclk(substream, false);
  5087. if (ret < 0)
  5088. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  5089. __func__, index, ret);
  5090. }
  5091. mutex_unlock(&mi2s_intf_conf[index].lock);
  5092. }
  5093. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  5094. {
  5095. int ret = 0;
  5096. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5097. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5098. int port_id = cpu_dai->id;
  5099. struct afe_clk_set clk_cfg;
  5100. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  5101. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  5102. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  5103. clk_cfg.enable = enable;
  5104. /* Set core clock (based on sample rate for RX, fixed for TX) */
  5105. switch (port_id) {
  5106. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5107. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  5108. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  5109. clk_cfg.clk_freq_in_hz =
  5110. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5111. break;
  5112. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5113. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  5114. clk_cfg.clk_freq_in_hz =
  5115. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5116. break;
  5117. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  5118. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  5119. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5120. break;
  5121. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  5122. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  5123. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5124. break;
  5125. }
  5126. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5127. if (ret < 0) {
  5128. dev_err(rtd->card->dev,
  5129. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5130. __func__, port_id, ret);
  5131. goto err;
  5132. }
  5133. /* Set NPL clock for RX in addition */
  5134. switch (port_id) {
  5135. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5136. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  5137. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5138. if (ret < 0) {
  5139. dev_err(rtd->card->dev,
  5140. "%s: afe NPL failed port 0x%x, err:%d\n",
  5141. __func__, port_id, ret);
  5142. goto err;
  5143. }
  5144. break;
  5145. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5146. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  5147. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5148. if (ret < 0) {
  5149. dev_err(rtd->card->dev,
  5150. "%s: afe NPL failed for port 0x%x, err:%d\n",
  5151. __func__, port_id, ret);
  5152. goto err;
  5153. }
  5154. break;
  5155. }
  5156. if (enable) {
  5157. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5158. clk_cfg.clk_freq_in_hz);
  5159. }
  5160. err:
  5161. return ret;
  5162. }
  5163. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  5164. {
  5165. int ret = 0;
  5166. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5167. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5168. int port_id = cpu_dai->id;
  5169. dev_dbg(rtd->card->dev,
  5170. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5171. __func__, substream->name, substream->stream,
  5172. cpu_dai->name, cpu_dai->id);
  5173. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5174. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5175. ret = -EINVAL;
  5176. dev_err(rtd->card->dev,
  5177. "%s: CPU DAI id (%d) out of range\n",
  5178. __func__, cpu_dai->id);
  5179. goto err;
  5180. }
  5181. ret = msm_spdif_set_clk(substream, true);
  5182. if (ret < 0) {
  5183. dev_err(rtd->card->dev,
  5184. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5185. __func__, port_id, ret);
  5186. }
  5187. err:
  5188. return ret;
  5189. }
  5190. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5191. {
  5192. int ret;
  5193. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5194. int port_id = rtd->cpu_dai->id;
  5195. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5196. substream->name, substream->stream);
  5197. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5198. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5199. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5200. return;
  5201. }
  5202. ret = msm_spdif_set_clk(substream, false);
  5203. if (ret < 0)
  5204. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5205. __func__, port_id, ret);
  5206. }
  5207. static struct snd_soc_ops msm_mi2s_be_ops = {
  5208. .startup = msm_mi2s_snd_startup,
  5209. .shutdown = msm_mi2s_snd_shutdown,
  5210. };
  5211. static struct snd_soc_ops msm_auxpcm_be_ops = {
  5212. .startup = msm_snd_auxpcm_startup,
  5213. };
  5214. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5215. .startup = msm_snd_cdc_dma_startup,
  5216. .hw_params = msm_snd_cdc_dma_hw_params,
  5217. };
  5218. static struct snd_soc_ops msm_be_ops = {
  5219. .hw_params = msm_snd_hw_params,
  5220. };
  5221. static struct snd_soc_ops msm_wcn_ops = {
  5222. .hw_params = msm_wcn_hw_params,
  5223. };
  5224. static struct snd_soc_ops msm_spdif_be_ops = {
  5225. .startup = msm_spdif_snd_startup,
  5226. .shutdown = msm_spdif_snd_shutdown,
  5227. };
  5228. /* Digital audio interface glue - connects codec <---> CPU */
  5229. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5230. /* FrontEnd DAI Links */
  5231. {
  5232. .name = MSM_DAILINK_NAME(Media1),
  5233. .stream_name = "MultiMedia1",
  5234. .cpu_dai_name = "MultiMedia1",
  5235. .platform_name = "msm-pcm-dsp.0",
  5236. .dynamic = 1,
  5237. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5238. .dpcm_playback = 1,
  5239. .dpcm_capture = 1,
  5240. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5241. SND_SOC_DPCM_TRIGGER_POST},
  5242. .codec_dai_name = "snd-soc-dummy-dai",
  5243. .codec_name = "snd-soc-dummy",
  5244. .ignore_suspend = 1,
  5245. /* this dainlink has playback support */
  5246. .ignore_pmdown_time = 1,
  5247. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5248. },
  5249. {
  5250. .name = MSM_DAILINK_NAME(Media2),
  5251. .stream_name = "MultiMedia2",
  5252. .cpu_dai_name = "MultiMedia2",
  5253. .platform_name = "msm-pcm-dsp.0",
  5254. .dynamic = 1,
  5255. .dpcm_playback = 1,
  5256. .dpcm_capture = 1,
  5257. .codec_dai_name = "snd-soc-dummy-dai",
  5258. .codec_name = "snd-soc-dummy",
  5259. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5260. SND_SOC_DPCM_TRIGGER_POST},
  5261. .ignore_suspend = 1,
  5262. /* this dainlink has playback support */
  5263. .ignore_pmdown_time = 1,
  5264. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5265. },
  5266. {
  5267. .name = "VoiceMMode1",
  5268. .stream_name = "VoiceMMode1",
  5269. .cpu_dai_name = "VoiceMMode1",
  5270. .platform_name = "msm-pcm-voice",
  5271. .dynamic = 1,
  5272. .dpcm_playback = 1,
  5273. .dpcm_capture = 1,
  5274. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5275. SND_SOC_DPCM_TRIGGER_POST},
  5276. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5277. .ignore_suspend = 1,
  5278. .ignore_pmdown_time = 1,
  5279. .codec_dai_name = "snd-soc-dummy-dai",
  5280. .codec_name = "snd-soc-dummy",
  5281. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5282. },
  5283. {
  5284. .name = "MSM VoIP",
  5285. .stream_name = "VoIP",
  5286. .cpu_dai_name = "VoIP",
  5287. .platform_name = "msm-voip-dsp",
  5288. .dynamic = 1,
  5289. .dpcm_playback = 1,
  5290. .dpcm_capture = 1,
  5291. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5292. SND_SOC_DPCM_TRIGGER_POST},
  5293. .codec_dai_name = "snd-soc-dummy-dai",
  5294. .codec_name = "snd-soc-dummy",
  5295. .ignore_suspend = 1,
  5296. /* this dainlink has playback support */
  5297. .ignore_pmdown_time = 1,
  5298. .id = MSM_FRONTEND_DAI_VOIP,
  5299. },
  5300. {
  5301. .name = MSM_DAILINK_NAME(ULL),
  5302. .stream_name = "MultiMedia3",
  5303. .cpu_dai_name = "MultiMedia3",
  5304. .platform_name = "msm-pcm-dsp.2",
  5305. .dynamic = 1,
  5306. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5307. .dpcm_playback = 1,
  5308. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5309. SND_SOC_DPCM_TRIGGER_POST},
  5310. .codec_dai_name = "snd-soc-dummy-dai",
  5311. .codec_name = "snd-soc-dummy",
  5312. .ignore_suspend = 1,
  5313. /* this dainlink has playback support */
  5314. .ignore_pmdown_time = 1,
  5315. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5316. },
  5317. /* Hostless PCM purpose */
  5318. {
  5319. .name = "SLIMBUS_0 Hostless",
  5320. .stream_name = "SLIMBUS_0 Hostless",
  5321. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5322. .platform_name = "msm-pcm-hostless",
  5323. .dynamic = 1,
  5324. .dpcm_playback = 1,
  5325. .dpcm_capture = 1,
  5326. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5327. SND_SOC_DPCM_TRIGGER_POST},
  5328. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5329. .ignore_suspend = 1,
  5330. /* this dailink has playback support */
  5331. .ignore_pmdown_time = 1,
  5332. .codec_dai_name = "snd-soc-dummy-dai",
  5333. .codec_name = "snd-soc-dummy",
  5334. },
  5335. {
  5336. .name = "MSM AFE-PCM RX",
  5337. .stream_name = "AFE-PROXY RX",
  5338. .cpu_dai_name = "msm-dai-q6-dev.241",
  5339. .codec_name = "msm-stub-codec.1",
  5340. .codec_dai_name = "msm-stub-rx",
  5341. .platform_name = "msm-pcm-afe",
  5342. .dpcm_playback = 1,
  5343. .ignore_suspend = 1,
  5344. /* this dainlink has playback support */
  5345. .ignore_pmdown_time = 1,
  5346. },
  5347. {
  5348. .name = "MSM AFE-PCM TX",
  5349. .stream_name = "AFE-PROXY TX",
  5350. .cpu_dai_name = "msm-dai-q6-dev.240",
  5351. .codec_name = "msm-stub-codec.1",
  5352. .codec_dai_name = "msm-stub-tx",
  5353. .platform_name = "msm-pcm-afe",
  5354. .dpcm_capture = 1,
  5355. .ignore_suspend = 1,
  5356. },
  5357. {
  5358. .name = MSM_DAILINK_NAME(Compress1),
  5359. .stream_name = "Compress1",
  5360. .cpu_dai_name = "MultiMedia4",
  5361. .platform_name = "msm-compress-dsp",
  5362. .dynamic = 1,
  5363. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5364. .dpcm_playback = 1,
  5365. .dpcm_capture = 1,
  5366. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5367. SND_SOC_DPCM_TRIGGER_POST},
  5368. .codec_dai_name = "snd-soc-dummy-dai",
  5369. .codec_name = "snd-soc-dummy",
  5370. .ignore_suspend = 1,
  5371. .ignore_pmdown_time = 1,
  5372. /* this dainlink has playback support */
  5373. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5374. },
  5375. {
  5376. .name = "AUXPCM Hostless",
  5377. .stream_name = "AUXPCM Hostless",
  5378. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5379. .platform_name = "msm-pcm-hostless",
  5380. .dynamic = 1,
  5381. .dpcm_playback = 1,
  5382. .dpcm_capture = 1,
  5383. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5384. SND_SOC_DPCM_TRIGGER_POST},
  5385. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5386. .ignore_suspend = 1,
  5387. /* this dainlink has playback support */
  5388. .ignore_pmdown_time = 1,
  5389. .codec_dai_name = "snd-soc-dummy-dai",
  5390. .codec_name = "snd-soc-dummy",
  5391. },
  5392. {
  5393. .name = "SLIMBUS_1 Hostless",
  5394. .stream_name = "SLIMBUS_1 Hostless",
  5395. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5396. .platform_name = "msm-pcm-hostless",
  5397. .dynamic = 1,
  5398. .dpcm_playback = 1,
  5399. .dpcm_capture = 1,
  5400. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5401. SND_SOC_DPCM_TRIGGER_POST},
  5402. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5403. .ignore_suspend = 1,
  5404. /* this dailink has playback support */
  5405. .ignore_pmdown_time = 1,
  5406. .codec_dai_name = "snd-soc-dummy-dai",
  5407. .codec_name = "snd-soc-dummy",
  5408. },
  5409. {
  5410. .name = "SLIMBUS_3 Hostless",
  5411. .stream_name = "SLIMBUS_3 Hostless",
  5412. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5413. .platform_name = "msm-pcm-hostless",
  5414. .dynamic = 1,
  5415. .dpcm_playback = 1,
  5416. .dpcm_capture = 1,
  5417. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5418. SND_SOC_DPCM_TRIGGER_POST},
  5419. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5420. .ignore_suspend = 1,
  5421. /* this dailink has playback support */
  5422. .ignore_pmdown_time = 1,
  5423. .codec_dai_name = "snd-soc-dummy-dai",
  5424. .codec_name = "snd-soc-dummy",
  5425. },
  5426. {
  5427. .name = "SLIMBUS_4 Hostless",
  5428. .stream_name = "SLIMBUS_4 Hostless",
  5429. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5430. .platform_name = "msm-pcm-hostless",
  5431. .dynamic = 1,
  5432. .dpcm_playback = 1,
  5433. .dpcm_capture = 1,
  5434. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5435. SND_SOC_DPCM_TRIGGER_POST},
  5436. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5437. .ignore_suspend = 1,
  5438. /* this dailink has playback support */
  5439. .ignore_pmdown_time = 1,
  5440. .codec_dai_name = "snd-soc-dummy-dai",
  5441. .codec_name = "snd-soc-dummy",
  5442. },
  5443. {
  5444. .name = MSM_DAILINK_NAME(LowLatency),
  5445. .stream_name = "MultiMedia5",
  5446. .cpu_dai_name = "MultiMedia5",
  5447. .platform_name = "msm-pcm-dsp.1",
  5448. .dynamic = 1,
  5449. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5450. .dpcm_playback = 1,
  5451. .dpcm_capture = 1,
  5452. .codec_dai_name = "snd-soc-dummy-dai",
  5453. .codec_name = "snd-soc-dummy",
  5454. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5455. SND_SOC_DPCM_TRIGGER_POST},
  5456. .ignore_suspend = 1,
  5457. /* this dainlink has playback support */
  5458. .ignore_pmdown_time = 1,
  5459. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5460. .ops = &msm_fe_qos_ops,
  5461. },
  5462. {
  5463. .name = "Listen 1 Audio Service",
  5464. .stream_name = "Listen 1 Audio Service",
  5465. .cpu_dai_name = "LSM1",
  5466. .platform_name = "msm-lsm-client",
  5467. .dynamic = 1,
  5468. .dpcm_capture = 1,
  5469. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5470. SND_SOC_DPCM_TRIGGER_POST },
  5471. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5472. .ignore_suspend = 1,
  5473. .codec_dai_name = "snd-soc-dummy-dai",
  5474. .codec_name = "snd-soc-dummy",
  5475. .id = MSM_FRONTEND_DAI_LSM1,
  5476. },
  5477. /* Multiple Tunnel instances */
  5478. {
  5479. .name = MSM_DAILINK_NAME(Compress2),
  5480. .stream_name = "Compress2",
  5481. .cpu_dai_name = "MultiMedia7",
  5482. .platform_name = "msm-compress-dsp",
  5483. .dynamic = 1,
  5484. .dpcm_playback = 1,
  5485. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5486. SND_SOC_DPCM_TRIGGER_POST},
  5487. .codec_dai_name = "snd-soc-dummy-dai",
  5488. .codec_name = "snd-soc-dummy",
  5489. .ignore_suspend = 1,
  5490. .ignore_pmdown_time = 1,
  5491. /* this dainlink has playback support */
  5492. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5493. },
  5494. {
  5495. .name = MSM_DAILINK_NAME(MultiMedia10),
  5496. .stream_name = "MultiMedia10",
  5497. .cpu_dai_name = "MultiMedia10",
  5498. .platform_name = "msm-pcm-dsp.1",
  5499. .dynamic = 1,
  5500. .dpcm_playback = 1,
  5501. .dpcm_capture = 1,
  5502. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5503. SND_SOC_DPCM_TRIGGER_POST},
  5504. .codec_dai_name = "snd-soc-dummy-dai",
  5505. .codec_name = "snd-soc-dummy",
  5506. .ignore_suspend = 1,
  5507. .ignore_pmdown_time = 1,
  5508. /* this dainlink has playback support */
  5509. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5510. },
  5511. {
  5512. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5513. .stream_name = "MM_NOIRQ",
  5514. .cpu_dai_name = "MultiMedia8",
  5515. .platform_name = "msm-pcm-dsp-noirq",
  5516. .dynamic = 1,
  5517. .dpcm_playback = 1,
  5518. .dpcm_capture = 1,
  5519. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5520. SND_SOC_DPCM_TRIGGER_POST},
  5521. .codec_dai_name = "snd-soc-dummy-dai",
  5522. .codec_name = "snd-soc-dummy",
  5523. .ignore_suspend = 1,
  5524. .ignore_pmdown_time = 1,
  5525. /* this dainlink has playback support */
  5526. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5527. .ops = &msm_fe_qos_ops,
  5528. },
  5529. /* HDMI Hostless */
  5530. {
  5531. .name = "HDMI_RX_HOSTLESS",
  5532. .stream_name = "HDMI_RX_HOSTLESS",
  5533. .cpu_dai_name = "HDMI_HOSTLESS",
  5534. .platform_name = "msm-pcm-hostless",
  5535. .dynamic = 1,
  5536. .dpcm_playback = 1,
  5537. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5538. SND_SOC_DPCM_TRIGGER_POST},
  5539. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5540. .ignore_suspend = 1,
  5541. .ignore_pmdown_time = 1,
  5542. .codec_dai_name = "snd-soc-dummy-dai",
  5543. .codec_name = "snd-soc-dummy",
  5544. },
  5545. {
  5546. .name = "VoiceMMode2",
  5547. .stream_name = "VoiceMMode2",
  5548. .cpu_dai_name = "VoiceMMode2",
  5549. .platform_name = "msm-pcm-voice",
  5550. .dynamic = 1,
  5551. .dpcm_playback = 1,
  5552. .dpcm_capture = 1,
  5553. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5554. SND_SOC_DPCM_TRIGGER_POST},
  5555. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5556. .ignore_suspend = 1,
  5557. .ignore_pmdown_time = 1,
  5558. .codec_dai_name = "snd-soc-dummy-dai",
  5559. .codec_name = "snd-soc-dummy",
  5560. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5561. },
  5562. /* LSM FE */
  5563. {
  5564. .name = "Listen 2 Audio Service",
  5565. .stream_name = "Listen 2 Audio Service",
  5566. .cpu_dai_name = "LSM2",
  5567. .platform_name = "msm-lsm-client",
  5568. .dynamic = 1,
  5569. .dpcm_capture = 1,
  5570. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5571. SND_SOC_DPCM_TRIGGER_POST },
  5572. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5573. .ignore_suspend = 1,
  5574. .codec_dai_name = "snd-soc-dummy-dai",
  5575. .codec_name = "snd-soc-dummy",
  5576. .id = MSM_FRONTEND_DAI_LSM2,
  5577. },
  5578. {
  5579. .name = "Listen 3 Audio Service",
  5580. .stream_name = "Listen 3 Audio Service",
  5581. .cpu_dai_name = "LSM3",
  5582. .platform_name = "msm-lsm-client",
  5583. .dynamic = 1,
  5584. .dpcm_capture = 1,
  5585. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5586. SND_SOC_DPCM_TRIGGER_POST },
  5587. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5588. .ignore_suspend = 1,
  5589. .codec_dai_name = "snd-soc-dummy-dai",
  5590. .codec_name = "snd-soc-dummy",
  5591. .id = MSM_FRONTEND_DAI_LSM3,
  5592. },
  5593. {
  5594. .name = "Listen 4 Audio Service",
  5595. .stream_name = "Listen 4 Audio Service",
  5596. .cpu_dai_name = "LSM4",
  5597. .platform_name = "msm-lsm-client",
  5598. .dynamic = 1,
  5599. .dpcm_capture = 1,
  5600. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5601. SND_SOC_DPCM_TRIGGER_POST },
  5602. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5603. .ignore_suspend = 1,
  5604. .codec_dai_name = "snd-soc-dummy-dai",
  5605. .codec_name = "snd-soc-dummy",
  5606. .id = MSM_FRONTEND_DAI_LSM4,
  5607. },
  5608. {
  5609. .name = "Listen 5 Audio Service",
  5610. .stream_name = "Listen 5 Audio Service",
  5611. .cpu_dai_name = "LSM5",
  5612. .platform_name = "msm-lsm-client",
  5613. .dynamic = 1,
  5614. .dpcm_capture = 1,
  5615. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5616. SND_SOC_DPCM_TRIGGER_POST },
  5617. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5618. .ignore_suspend = 1,
  5619. .codec_dai_name = "snd-soc-dummy-dai",
  5620. .codec_name = "snd-soc-dummy",
  5621. .id = MSM_FRONTEND_DAI_LSM5,
  5622. },
  5623. {
  5624. .name = "Listen 6 Audio Service",
  5625. .stream_name = "Listen 6 Audio Service",
  5626. .cpu_dai_name = "LSM6",
  5627. .platform_name = "msm-lsm-client",
  5628. .dynamic = 1,
  5629. .dpcm_capture = 1,
  5630. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5631. SND_SOC_DPCM_TRIGGER_POST },
  5632. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5633. .ignore_suspend = 1,
  5634. .codec_dai_name = "snd-soc-dummy-dai",
  5635. .codec_name = "snd-soc-dummy",
  5636. .id = MSM_FRONTEND_DAI_LSM6,
  5637. },
  5638. {
  5639. .name = "Listen 7 Audio Service",
  5640. .stream_name = "Listen 7 Audio Service",
  5641. .cpu_dai_name = "LSM7",
  5642. .platform_name = "msm-lsm-client",
  5643. .dynamic = 1,
  5644. .dpcm_capture = 1,
  5645. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5646. SND_SOC_DPCM_TRIGGER_POST },
  5647. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5648. .ignore_suspend = 1,
  5649. .codec_dai_name = "snd-soc-dummy-dai",
  5650. .codec_name = "snd-soc-dummy",
  5651. .id = MSM_FRONTEND_DAI_LSM7,
  5652. },
  5653. {
  5654. .name = "Listen 8 Audio Service",
  5655. .stream_name = "Listen 8 Audio Service",
  5656. .cpu_dai_name = "LSM8",
  5657. .platform_name = "msm-lsm-client",
  5658. .dynamic = 1,
  5659. .dpcm_capture = 1,
  5660. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5661. SND_SOC_DPCM_TRIGGER_POST },
  5662. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5663. .ignore_suspend = 1,
  5664. .codec_dai_name = "snd-soc-dummy-dai",
  5665. .codec_name = "snd-soc-dummy",
  5666. .id = MSM_FRONTEND_DAI_LSM8,
  5667. },
  5668. {
  5669. .name = MSM_DAILINK_NAME(Media9),
  5670. .stream_name = "MultiMedia9",
  5671. .cpu_dai_name = "MultiMedia9",
  5672. .platform_name = "msm-pcm-dsp.0",
  5673. .dynamic = 1,
  5674. .dpcm_playback = 1,
  5675. .dpcm_capture = 1,
  5676. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5677. SND_SOC_DPCM_TRIGGER_POST},
  5678. .codec_dai_name = "snd-soc-dummy-dai",
  5679. .codec_name = "snd-soc-dummy",
  5680. .ignore_suspend = 1,
  5681. /* this dainlink has playback support */
  5682. .ignore_pmdown_time = 1,
  5683. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5684. },
  5685. {
  5686. .name = MSM_DAILINK_NAME(Compress4),
  5687. .stream_name = "Compress4",
  5688. .cpu_dai_name = "MultiMedia11",
  5689. .platform_name = "msm-compress-dsp",
  5690. .dynamic = 1,
  5691. .dpcm_playback = 1,
  5692. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5693. SND_SOC_DPCM_TRIGGER_POST},
  5694. .codec_dai_name = "snd-soc-dummy-dai",
  5695. .codec_name = "snd-soc-dummy",
  5696. .ignore_suspend = 1,
  5697. .ignore_pmdown_time = 1,
  5698. /* this dainlink has playback support */
  5699. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5700. },
  5701. {
  5702. .name = MSM_DAILINK_NAME(Compress5),
  5703. .stream_name = "Compress5",
  5704. .cpu_dai_name = "MultiMedia12",
  5705. .platform_name = "msm-compress-dsp",
  5706. .dynamic = 1,
  5707. .dpcm_playback = 1,
  5708. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5709. SND_SOC_DPCM_TRIGGER_POST},
  5710. .codec_dai_name = "snd-soc-dummy-dai",
  5711. .codec_name = "snd-soc-dummy",
  5712. .ignore_suspend = 1,
  5713. .ignore_pmdown_time = 1,
  5714. /* this dainlink has playback support */
  5715. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5716. },
  5717. {
  5718. .name = MSM_DAILINK_NAME(Compress6),
  5719. .stream_name = "Compress6",
  5720. .cpu_dai_name = "MultiMedia13",
  5721. .platform_name = "msm-compress-dsp",
  5722. .dynamic = 1,
  5723. .dpcm_playback = 1,
  5724. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5725. SND_SOC_DPCM_TRIGGER_POST},
  5726. .codec_dai_name = "snd-soc-dummy-dai",
  5727. .codec_name = "snd-soc-dummy",
  5728. .ignore_suspend = 1,
  5729. .ignore_pmdown_time = 1,
  5730. /* this dainlink has playback support */
  5731. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5732. },
  5733. {
  5734. .name = MSM_DAILINK_NAME(Compress7),
  5735. .stream_name = "Compress7",
  5736. .cpu_dai_name = "MultiMedia14",
  5737. .platform_name = "msm-compress-dsp",
  5738. .dynamic = 1,
  5739. .dpcm_playback = 1,
  5740. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5741. SND_SOC_DPCM_TRIGGER_POST},
  5742. .codec_dai_name = "snd-soc-dummy-dai",
  5743. .codec_name = "snd-soc-dummy",
  5744. .ignore_suspend = 1,
  5745. .ignore_pmdown_time = 1,
  5746. /* this dainlink has playback support */
  5747. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5748. },
  5749. {
  5750. .name = MSM_DAILINK_NAME(Compress8),
  5751. .stream_name = "Compress8",
  5752. .cpu_dai_name = "MultiMedia15",
  5753. .platform_name = "msm-compress-dsp",
  5754. .dynamic = 1,
  5755. .dpcm_playback = 1,
  5756. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5757. SND_SOC_DPCM_TRIGGER_POST},
  5758. .codec_dai_name = "snd-soc-dummy-dai",
  5759. .codec_name = "snd-soc-dummy",
  5760. .ignore_suspend = 1,
  5761. .ignore_pmdown_time = 1,
  5762. /* this dainlink has playback support */
  5763. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5764. },
  5765. {
  5766. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5767. .stream_name = "MM_NOIRQ_2",
  5768. .cpu_dai_name = "MultiMedia16",
  5769. .platform_name = "msm-pcm-dsp-noirq",
  5770. .dynamic = 1,
  5771. .dpcm_playback = 1,
  5772. .dpcm_capture = 1,
  5773. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5774. SND_SOC_DPCM_TRIGGER_POST},
  5775. .codec_dai_name = "snd-soc-dummy-dai",
  5776. .codec_name = "snd-soc-dummy",
  5777. .ignore_suspend = 1,
  5778. .ignore_pmdown_time = 1,
  5779. /* this dainlink has playback support */
  5780. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5781. },
  5782. {
  5783. .name = "SLIMBUS_8 Hostless",
  5784. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5785. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5786. .platform_name = "msm-pcm-hostless",
  5787. .dynamic = 1,
  5788. .dpcm_capture = 1,
  5789. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5790. SND_SOC_DPCM_TRIGGER_POST},
  5791. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5792. .ignore_suspend = 1,
  5793. .codec_dai_name = "snd-soc-dummy-dai",
  5794. .codec_name = "snd-soc-dummy",
  5795. },
  5796. /* Hostless PCM purpose */
  5797. {
  5798. .name = "CDC_DMA Hostless",
  5799. .stream_name = "CDC_DMA Hostless",
  5800. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5801. .platform_name = "msm-pcm-hostless",
  5802. .dynamic = 1,
  5803. .dpcm_playback = 1,
  5804. .dpcm_capture = 1,
  5805. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5806. SND_SOC_DPCM_TRIGGER_POST},
  5807. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5808. .ignore_suspend = 1,
  5809. /* this dailink has playback support */
  5810. .ignore_pmdown_time = 1,
  5811. .codec_dai_name = "snd-soc-dummy-dai",
  5812. .codec_name = "snd-soc-dummy",
  5813. },
  5814. };
  5815. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5816. {
  5817. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5818. .stream_name = "WSA CDC DMA0 Capture",
  5819. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5820. .platform_name = "msm-pcm-hostless",
  5821. .codec_name = "bolero_codec",
  5822. .codec_dai_name = "wsa_macro_vifeedback",
  5823. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5824. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5825. .ignore_suspend = 1,
  5826. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5827. .ops = &msm_cdc_dma_be_ops,
  5828. },
  5829. };
  5830. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5831. {
  5832. .name = MSM_DAILINK_NAME(ASM Loopback),
  5833. .stream_name = "MultiMedia6",
  5834. .cpu_dai_name = "MultiMedia6",
  5835. .platform_name = "msm-pcm-loopback",
  5836. .dynamic = 1,
  5837. .dpcm_playback = 1,
  5838. .dpcm_capture = 1,
  5839. .codec_dai_name = "snd-soc-dummy-dai",
  5840. .codec_name = "snd-soc-dummy",
  5841. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5842. SND_SOC_DPCM_TRIGGER_POST},
  5843. .ignore_suspend = 1,
  5844. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5845. .ignore_pmdown_time = 1,
  5846. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5847. },
  5848. {
  5849. .name = "USB Audio Hostless",
  5850. .stream_name = "USB Audio Hostless",
  5851. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5852. .platform_name = "msm-pcm-hostless",
  5853. .dynamic = 1,
  5854. .dpcm_playback = 1,
  5855. .dpcm_capture = 1,
  5856. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5857. SND_SOC_DPCM_TRIGGER_POST},
  5858. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5859. .ignore_suspend = 1,
  5860. .ignore_pmdown_time = 1,
  5861. .codec_dai_name = "snd-soc-dummy-dai",
  5862. .codec_name = "snd-soc-dummy",
  5863. },
  5864. {
  5865. .name = "SLIMBUS_7 Hostless",
  5866. .stream_name = "SLIMBUS_7 Hostless",
  5867. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5868. .platform_name = "msm-pcm-hostless",
  5869. .dynamic = 1,
  5870. .dpcm_capture = 1,
  5871. .dpcm_playback = 1,
  5872. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5873. SND_SOC_DPCM_TRIGGER_POST},
  5874. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5875. .ignore_suspend = 1,
  5876. .ignore_pmdown_time = 1,
  5877. .codec_dai_name = "snd-soc-dummy-dai",
  5878. .codec_name = "snd-soc-dummy",
  5879. },
  5880. {
  5881. .name = MSM_DAILINK_NAME(Compr Capture2),
  5882. .stream_name = "Compr Capture2",
  5883. .cpu_dai_name = "MultiMedia18",
  5884. .platform_name = "msm-compress-dsp",
  5885. .dynamic = 1,
  5886. .dpcm_capture = 1,
  5887. .codec_dai_name = "snd-soc-dummy-dai",
  5888. .codec_name = "snd-soc-dummy",
  5889. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5890. SND_SOC_DPCM_TRIGGER_POST},
  5891. .ignore_pmdown_time = 1,
  5892. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5893. },
  5894. {
  5895. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  5896. .stream_name = "Transcode Loopback Playback",
  5897. .cpu_dai_name = "MultiMedia26",
  5898. .platform_name = "msm-transcode-loopback",
  5899. .dynamic = 1,
  5900. .dpcm_playback = 1,
  5901. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5902. SND_SOC_DPCM_TRIGGER_POST},
  5903. .codec_dai_name = "snd-soc-dummy-dai",
  5904. .codec_name = "snd-soc-dummy",
  5905. .ignore_suspend = 1,
  5906. .ignore_pmdown_time = 1,
  5907. /* this dailink has playback support */
  5908. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  5909. },
  5910. {
  5911. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  5912. .stream_name = "Transcode Loopback Capture",
  5913. .cpu_dai_name = "MultiMedia27",
  5914. .platform_name = "msm-transcode-loopback",
  5915. .dynamic = 1,
  5916. .dpcm_capture = 1,
  5917. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5918. SND_SOC_DPCM_TRIGGER_POST},
  5919. .codec_dai_name = "snd-soc-dummy-dai",
  5920. .codec_name = "snd-soc-dummy",
  5921. .ignore_suspend = 1,
  5922. .ignore_pmdown_time = 1,
  5923. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  5924. },
  5925. {
  5926. .name = MSM_DAILINK_NAME(Compr Capture3),
  5927. .stream_name = "Compr Capture3",
  5928. .cpu_dai_name = "MultiMedia19",
  5929. .platform_name = "msm-compress-dsp",
  5930. .dynamic = 1,
  5931. .dpcm_capture = 1,
  5932. .codec_dai_name = "snd-soc-dummy-dai",
  5933. .codec_name = "snd-soc-dummy",
  5934. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5935. SND_SOC_DPCM_TRIGGER_POST},
  5936. .ignore_pmdown_time = 1,
  5937. .id = MSM_FRONTEND_DAI_MULTIMEDIA19,
  5938. },
  5939. {
  5940. .name = MSM_DAILINK_NAME(Compr Capture4),
  5941. .stream_name = "Compr Capture4",
  5942. .cpu_dai_name = "MultiMedia28",
  5943. .platform_name = "msm-compress-dsp",
  5944. .dynamic = 1,
  5945. .dpcm_capture = 1,
  5946. .codec_dai_name = "snd-soc-dummy-dai",
  5947. .codec_name = "snd-soc-dummy",
  5948. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5949. SND_SOC_DPCM_TRIGGER_POST},
  5950. .ignore_pmdown_time = 1,
  5951. .id = MSM_FRONTEND_DAI_MULTIMEDIA28,
  5952. },
  5953. {
  5954. .name = MSM_DAILINK_NAME(Compr Capture5),
  5955. .stream_name = "Compr Capture5",
  5956. .cpu_dai_name = "MultiMedia29",
  5957. .platform_name = "msm-compress-dsp",
  5958. .dynamic = 1,
  5959. .dpcm_capture = 1,
  5960. .codec_dai_name = "snd-soc-dummy-dai",
  5961. .codec_name = "snd-soc-dummy",
  5962. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5963. SND_SOC_DPCM_TRIGGER_POST},
  5964. .ignore_pmdown_time = 1,
  5965. .id = MSM_FRONTEND_DAI_MULTIMEDIA29,
  5966. },
  5967. };
  5968. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5969. /* Backend AFE DAI Links */
  5970. {
  5971. .name = LPASS_BE_AFE_PCM_RX,
  5972. .stream_name = "AFE Playback",
  5973. .cpu_dai_name = "msm-dai-q6-dev.224",
  5974. .platform_name = "msm-pcm-routing",
  5975. .codec_name = "msm-stub-codec.1",
  5976. .codec_dai_name = "msm-stub-rx",
  5977. .no_pcm = 1,
  5978. .dpcm_playback = 1,
  5979. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5980. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5981. /* this dainlink has playback support */
  5982. .ignore_pmdown_time = 1,
  5983. .ignore_suspend = 1,
  5984. },
  5985. {
  5986. .name = LPASS_BE_AFE_PCM_TX,
  5987. .stream_name = "AFE Capture",
  5988. .cpu_dai_name = "msm-dai-q6-dev.225",
  5989. .platform_name = "msm-pcm-routing",
  5990. .codec_name = "msm-stub-codec.1",
  5991. .codec_dai_name = "msm-stub-tx",
  5992. .no_pcm = 1,
  5993. .dpcm_capture = 1,
  5994. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5995. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5996. .ignore_suspend = 1,
  5997. },
  5998. /* Incall Record Uplink BACK END DAI Link */
  5999. {
  6000. .name = LPASS_BE_INCALL_RECORD_TX,
  6001. .stream_name = "Voice Uplink Capture",
  6002. .cpu_dai_name = "msm-dai-q6-dev.32772",
  6003. .platform_name = "msm-pcm-routing",
  6004. .codec_name = "msm-stub-codec.1",
  6005. .codec_dai_name = "msm-stub-tx",
  6006. .no_pcm = 1,
  6007. .dpcm_capture = 1,
  6008. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  6009. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6010. .ignore_suspend = 1,
  6011. },
  6012. /* Incall Record Downlink BACK END DAI Link */
  6013. {
  6014. .name = LPASS_BE_INCALL_RECORD_RX,
  6015. .stream_name = "Voice Downlink Capture",
  6016. .cpu_dai_name = "msm-dai-q6-dev.32771",
  6017. .platform_name = "msm-pcm-routing",
  6018. .codec_name = "msm-stub-codec.1",
  6019. .codec_dai_name = "msm-stub-tx",
  6020. .no_pcm = 1,
  6021. .dpcm_capture = 1,
  6022. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  6023. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6024. .ignore_suspend = 1,
  6025. },
  6026. /* Incall Music BACK END DAI Link */
  6027. {
  6028. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  6029. .stream_name = "Voice Farend Playback",
  6030. .cpu_dai_name = "msm-dai-q6-dev.32773",
  6031. .platform_name = "msm-pcm-routing",
  6032. .codec_name = "msm-stub-codec.1",
  6033. .codec_dai_name = "msm-stub-rx",
  6034. .no_pcm = 1,
  6035. .dpcm_playback = 1,
  6036. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  6037. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6038. .ignore_suspend = 1,
  6039. .ignore_pmdown_time = 1,
  6040. },
  6041. /* Incall Music 2 BACK END DAI Link */
  6042. {
  6043. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  6044. .stream_name = "Voice2 Farend Playback",
  6045. .cpu_dai_name = "msm-dai-q6-dev.32770",
  6046. .platform_name = "msm-pcm-routing",
  6047. .codec_name = "msm-stub-codec.1",
  6048. .codec_dai_name = "msm-stub-rx",
  6049. .no_pcm = 1,
  6050. .dpcm_playback = 1,
  6051. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  6052. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6053. .ignore_suspend = 1,
  6054. .ignore_pmdown_time = 1,
  6055. },
  6056. {
  6057. .name = LPASS_BE_USB_AUDIO_RX,
  6058. .stream_name = "USB Audio Playback",
  6059. .cpu_dai_name = "msm-dai-q6-dev.28672",
  6060. .platform_name = "msm-pcm-routing",
  6061. .codec_name = "msm-stub-codec.1",
  6062. .codec_dai_name = "msm-stub-rx",
  6063. .no_pcm = 1,
  6064. .dpcm_playback = 1,
  6065. .id = MSM_BACKEND_DAI_USB_RX,
  6066. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6067. .ignore_pmdown_time = 1,
  6068. .ignore_suspend = 1,
  6069. },
  6070. {
  6071. .name = LPASS_BE_USB_AUDIO_TX,
  6072. .stream_name = "USB Audio Capture",
  6073. .cpu_dai_name = "msm-dai-q6-dev.28673",
  6074. .platform_name = "msm-pcm-routing",
  6075. .codec_name = "msm-stub-codec.1",
  6076. .codec_dai_name = "msm-stub-tx",
  6077. .no_pcm = 1,
  6078. .dpcm_capture = 1,
  6079. .id = MSM_BACKEND_DAI_USB_TX,
  6080. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6081. .ignore_suspend = 1,
  6082. },
  6083. {
  6084. .name = LPASS_BE_PRI_TDM_RX_0,
  6085. .stream_name = "Primary TDM0 Playback",
  6086. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  6087. .platform_name = "msm-pcm-routing",
  6088. .codec_name = "msm-stub-codec.1",
  6089. .codec_dai_name = "msm-stub-rx",
  6090. .no_pcm = 1,
  6091. .dpcm_playback = 1,
  6092. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  6093. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6094. .ops = &qcs405_tdm_be_ops,
  6095. .ignore_suspend = 1,
  6096. .ignore_pmdown_time = 1,
  6097. },
  6098. {
  6099. .name = LPASS_BE_PRI_TDM_TX_0,
  6100. .stream_name = "Primary TDM0 Capture",
  6101. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  6102. .platform_name = "msm-pcm-routing",
  6103. .codec_name = "msm-stub-codec.1",
  6104. .codec_dai_name = "msm-stub-tx",
  6105. .no_pcm = 1,
  6106. .dpcm_capture = 1,
  6107. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  6108. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6109. .ops = &qcs405_tdm_be_ops,
  6110. .ignore_suspend = 1,
  6111. },
  6112. {
  6113. .name = LPASS_BE_SEC_TDM_RX_0,
  6114. .stream_name = "Secondary TDM0 Playback",
  6115. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  6116. .platform_name = "msm-pcm-routing",
  6117. .codec_name = "msm-stub-codec.1",
  6118. .codec_dai_name = "msm-stub-rx",
  6119. .no_pcm = 1,
  6120. .dpcm_playback = 1,
  6121. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  6122. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6123. .ops = &qcs405_tdm_be_ops,
  6124. .ignore_suspend = 1,
  6125. .ignore_pmdown_time = 1,
  6126. },
  6127. {
  6128. .name = LPASS_BE_SEC_TDM_TX_0,
  6129. .stream_name = "Secondary TDM0 Capture",
  6130. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  6131. .platform_name = "msm-pcm-routing",
  6132. .codec_name = "msm-stub-codec.1",
  6133. .codec_dai_name = "msm-stub-tx",
  6134. .no_pcm = 1,
  6135. .dpcm_capture = 1,
  6136. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  6137. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6138. .ops = &qcs405_tdm_be_ops,
  6139. .ignore_suspend = 1,
  6140. },
  6141. {
  6142. .name = LPASS_BE_TERT_TDM_RX_0,
  6143. .stream_name = "Tertiary TDM0 Playback",
  6144. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  6145. .platform_name = "msm-pcm-routing",
  6146. .codec_name = "msm-stub-codec.1",
  6147. .codec_dai_name = "msm-stub-rx",
  6148. .no_pcm = 1,
  6149. .dpcm_playback = 1,
  6150. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  6151. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6152. .ops = &qcs405_tdm_be_ops,
  6153. .ignore_suspend = 1,
  6154. .ignore_pmdown_time = 1,
  6155. },
  6156. {
  6157. .name = LPASS_BE_TERT_TDM_TX_0,
  6158. .stream_name = "Tertiary TDM0 Capture",
  6159. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  6160. .platform_name = "msm-pcm-routing",
  6161. .codec_name = "msm-stub-codec.1",
  6162. .codec_dai_name = "msm-stub-tx",
  6163. .no_pcm = 1,
  6164. .dpcm_capture = 1,
  6165. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  6166. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6167. .ops = &qcs405_tdm_be_ops,
  6168. .ignore_suspend = 1,
  6169. },
  6170. {
  6171. .name = LPASS_BE_QUAT_TDM_RX_0,
  6172. .stream_name = "Quaternary TDM0 Playback",
  6173. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  6174. .platform_name = "msm-pcm-routing",
  6175. .codec_name = "msm-stub-codec.1",
  6176. .codec_dai_name = "msm-stub-rx",
  6177. .no_pcm = 1,
  6178. .dpcm_playback = 1,
  6179. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  6180. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6181. .ops = &qcs405_tdm_be_ops,
  6182. .ignore_suspend = 1,
  6183. .ignore_pmdown_time = 1,
  6184. },
  6185. {
  6186. .name = LPASS_BE_QUAT_TDM_TX_0,
  6187. .stream_name = "Quaternary TDM0 Capture",
  6188. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  6189. .platform_name = "msm-pcm-routing",
  6190. .codec_name = "msm-stub-codec.1",
  6191. .codec_dai_name = "msm-stub-tx",
  6192. .no_pcm = 1,
  6193. .dpcm_capture = 1,
  6194. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  6195. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6196. .ops = &qcs405_tdm_be_ops,
  6197. .ignore_suspend = 1,
  6198. },
  6199. {
  6200. .name = LPASS_BE_QUIN_TDM_RX_0,
  6201. .stream_name = "Quinary TDM0 Playback",
  6202. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  6203. .platform_name = "msm-pcm-routing",
  6204. .codec_name = "msm-stub-codec.1",
  6205. .codec_dai_name = "msm-stub-rx",
  6206. .no_pcm = 1,
  6207. .dpcm_playback = 1,
  6208. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  6209. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6210. .ops = &qcs405_tdm_be_ops,
  6211. .ignore_suspend = 1,
  6212. .ignore_pmdown_time = 1,
  6213. },
  6214. {
  6215. .name = LPASS_BE_QUIN_TDM_TX_0,
  6216. .stream_name = "Quinary TDM0 Capture",
  6217. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  6218. .platform_name = "msm-pcm-routing",
  6219. .codec_name = "msm-stub-codec.1",
  6220. .codec_dai_name = "msm-stub-tx",
  6221. .no_pcm = 1,
  6222. .dpcm_capture = 1,
  6223. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  6224. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6225. .ops = &qcs405_tdm_be_ops,
  6226. .ignore_suspend = 1,
  6227. },
  6228. };
  6229. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6230. {
  6231. .name = LPASS_BE_SLIMBUS_0_RX,
  6232. .stream_name = "Slimbus Playback",
  6233. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6234. .platform_name = "msm-pcm-routing",
  6235. .codec_name = "tasha_codec",
  6236. .codec_dai_name = "tasha_mix_rx1",
  6237. .no_pcm = 1,
  6238. .dpcm_playback = 1,
  6239. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6240. .init = &msm_audrx_init,
  6241. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6242. /* this dainlink has playback support */
  6243. .ignore_pmdown_time = 1,
  6244. .ignore_suspend = 1,
  6245. .ops = &msm_be_ops,
  6246. },
  6247. {
  6248. .name = LPASS_BE_SLIMBUS_0_TX,
  6249. .stream_name = "Slimbus Capture",
  6250. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6251. .platform_name = "msm-pcm-routing",
  6252. .codec_name = "tasha_codec",
  6253. .codec_dai_name = "tasha_tx1",
  6254. .no_pcm = 1,
  6255. .dpcm_capture = 1,
  6256. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6257. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6258. .ignore_suspend = 1,
  6259. .ops = &msm_be_ops,
  6260. },
  6261. {
  6262. .name = LPASS_BE_SLIMBUS_1_RX,
  6263. .stream_name = "Slimbus1 Playback",
  6264. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6265. .platform_name = "msm-pcm-routing",
  6266. .codec_name = "tasha_codec",
  6267. .codec_dai_name = "tasha_mix_rx1",
  6268. .no_pcm = 1,
  6269. .dpcm_playback = 1,
  6270. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6271. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6272. .ops = &msm_be_ops,
  6273. /* dai link has playback support */
  6274. .ignore_pmdown_time = 1,
  6275. .ignore_suspend = 1,
  6276. },
  6277. {
  6278. .name = LPASS_BE_SLIMBUS_1_TX,
  6279. .stream_name = "Slimbus1 Capture",
  6280. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6281. .platform_name = "msm-pcm-routing",
  6282. .codec_name = "tasha_codec",
  6283. .codec_dai_name = "tasha_tx3",
  6284. .no_pcm = 1,
  6285. .dpcm_capture = 1,
  6286. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6287. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6288. .ops = &msm_be_ops,
  6289. .ignore_suspend = 1,
  6290. },
  6291. {
  6292. .name = LPASS_BE_SLIMBUS_2_RX,
  6293. .stream_name = "Slimbus2 Playback",
  6294. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6295. .platform_name = "msm-pcm-routing",
  6296. .codec_name = "tasha_codec",
  6297. .codec_dai_name = "tasha_rx2",
  6298. .no_pcm = 1,
  6299. .dpcm_playback = 1,
  6300. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6301. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6302. .ops = &msm_be_ops,
  6303. .ignore_pmdown_time = 1,
  6304. .ignore_suspend = 1,
  6305. },
  6306. {
  6307. .name = LPASS_BE_SLIMBUS_3_RX,
  6308. .stream_name = "Slimbus3 Playback",
  6309. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6310. .platform_name = "msm-pcm-routing",
  6311. .codec_name = "tasha_codec",
  6312. .codec_dai_name = "tasha_mix_rx1",
  6313. .no_pcm = 1,
  6314. .dpcm_playback = 1,
  6315. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6316. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6317. .ops = &msm_be_ops,
  6318. /* dai link has playback support */
  6319. .ignore_pmdown_time = 1,
  6320. .ignore_suspend = 1,
  6321. },
  6322. {
  6323. .name = LPASS_BE_SLIMBUS_3_TX,
  6324. .stream_name = "Slimbus3 Capture",
  6325. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6326. .platform_name = "msm-pcm-routing",
  6327. .codec_name = "tasha_codec",
  6328. .codec_dai_name = "tasha_tx1",
  6329. .no_pcm = 1,
  6330. .dpcm_capture = 1,
  6331. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6332. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6333. .ops = &msm_be_ops,
  6334. .ignore_suspend = 1,
  6335. },
  6336. {
  6337. .name = LPASS_BE_SLIMBUS_4_RX,
  6338. .stream_name = "Slimbus4 Playback",
  6339. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6340. .platform_name = "msm-pcm-routing",
  6341. .codec_name = "tasha_codec",
  6342. .codec_dai_name = "tasha_mix_rx1",
  6343. .no_pcm = 1,
  6344. .dpcm_playback = 1,
  6345. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6346. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6347. .ops = &msm_be_ops,
  6348. /* dai link has playback support */
  6349. .ignore_pmdown_time = 1,
  6350. .ignore_suspend = 1,
  6351. },
  6352. {
  6353. .name = LPASS_BE_SLIMBUS_5_RX,
  6354. .stream_name = "Slimbus5 Playback",
  6355. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6356. .platform_name = "msm-pcm-routing",
  6357. .codec_name = "tasha_codec",
  6358. .codec_dai_name = "tasha_rx3",
  6359. .no_pcm = 1,
  6360. .dpcm_playback = 1,
  6361. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6362. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6363. .ops = &msm_be_ops,
  6364. /* dai link has playback support */
  6365. .ignore_pmdown_time = 1,
  6366. .ignore_suspend = 1,
  6367. },
  6368. {
  6369. .name = LPASS_BE_SLIMBUS_6_RX,
  6370. .stream_name = "Slimbus6 Playback",
  6371. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6372. .platform_name = "msm-pcm-routing",
  6373. .codec_name = "tasha_codec",
  6374. .codec_dai_name = "tasha_rx4",
  6375. .no_pcm = 1,
  6376. .dpcm_playback = 1,
  6377. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6378. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6379. .ops = &msm_be_ops,
  6380. /* dai link has playback support */
  6381. .ignore_pmdown_time = 1,
  6382. .ignore_suspend = 1,
  6383. },
  6384. /* Slimbus VI Recording */
  6385. {
  6386. .name = LPASS_BE_SLIMBUS_TX_VI,
  6387. .stream_name = "Slimbus4 Capture",
  6388. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6389. .platform_name = "msm-pcm-routing",
  6390. .codec_name = "tasha_codec",
  6391. .codec_dai_name = "tasha_vifeedback",
  6392. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6393. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6394. .ops = &msm_be_ops,
  6395. .ignore_suspend = 1,
  6396. .no_pcm = 1,
  6397. .dpcm_capture = 1,
  6398. .ignore_pmdown_time = 1,
  6399. },
  6400. };
  6401. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6402. {
  6403. .name = LPASS_BE_SLIMBUS_7_RX,
  6404. .stream_name = "Slimbus7 Playback",
  6405. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6406. .platform_name = "msm-pcm-routing",
  6407. .codec_name = "btfmslim_slave",
  6408. /* BT codec driver determines capabilities based on
  6409. * dai name, bt codecdai name should always contains
  6410. * supported usecase information
  6411. */
  6412. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6413. .no_pcm = 1,
  6414. .dpcm_playback = 1,
  6415. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6416. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6417. .ops = &msm_wcn_ops,
  6418. /* dai link has playback support */
  6419. .ignore_pmdown_time = 1,
  6420. .ignore_suspend = 1,
  6421. },
  6422. {
  6423. .name = LPASS_BE_SLIMBUS_7_TX,
  6424. .stream_name = "Slimbus7 Capture",
  6425. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6426. .platform_name = "msm-pcm-routing",
  6427. .codec_name = "btfmslim_slave",
  6428. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6429. .no_pcm = 1,
  6430. .dpcm_capture = 1,
  6431. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6432. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6433. .ops = &msm_wcn_ops,
  6434. .ignore_suspend = 1,
  6435. },
  6436. {
  6437. .name = LPASS_BE_SLIMBUS_8_TX,
  6438. .stream_name = "Slimbus8 Capture",
  6439. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6440. .platform_name = "msm-pcm-routing",
  6441. .codec_name = "btfmslim_slave",
  6442. .codec_dai_name = "btfm_fm_slim_tx",
  6443. .no_pcm = 1,
  6444. .dpcm_capture = 1,
  6445. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6446. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6447. .init = &msm_wcn_init,
  6448. .ops = &msm_wcn_ops,
  6449. .ignore_suspend = 1,
  6450. },
  6451. {
  6452. .name = LPASS_BE_SLIMBUS_9_TX,
  6453. .stream_name = "Slimbus9 Capture",
  6454. .cpu_dai_name = "msm-dai-q6-dev.16403",
  6455. .platform_name = "msm-pcm-routing",
  6456. .codec_name = "btfmslim_slave",
  6457. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  6458. .no_pcm = 1,
  6459. .dpcm_capture = 1,
  6460. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  6461. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6462. .ops = &msm_wcn_ops,
  6463. .ignore_suspend = 1,
  6464. },
  6465. };
  6466. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6467. {
  6468. .name = LPASS_BE_PRI_MI2S_RX,
  6469. .stream_name = "Primary MI2S Playback",
  6470. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6471. .platform_name = "msm-pcm-routing",
  6472. .codec_name = "msm-stub-codec.1",
  6473. .codec_dai_name = "msm-stub-rx",
  6474. .no_pcm = 1,
  6475. .dpcm_playback = 1,
  6476. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6477. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6478. .ops = &msm_mi2s_be_ops,
  6479. .ignore_suspend = 1,
  6480. .ignore_pmdown_time = 1,
  6481. },
  6482. {
  6483. .name = LPASS_BE_PRI_MI2S_TX,
  6484. .stream_name = "Primary MI2S Capture",
  6485. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6486. .platform_name = "msm-pcm-routing",
  6487. .codec_name = "msm-stub-codec.1",
  6488. .codec_dai_name = "msm-stub-tx",
  6489. .no_pcm = 1,
  6490. .dpcm_capture = 1,
  6491. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6492. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6493. .ops = &msm_mi2s_be_ops,
  6494. .ignore_suspend = 1,
  6495. },
  6496. {
  6497. .name = LPASS_BE_SEC_MI2S_RX,
  6498. .stream_name = "Secondary MI2S Playback",
  6499. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6500. .platform_name = "msm-pcm-routing",
  6501. .codec_name = "msm-stub-codec.1",
  6502. .codec_dai_name = "msm-stub-rx",
  6503. .no_pcm = 1,
  6504. .dpcm_playback = 1,
  6505. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6506. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6507. .ops = &msm_mi2s_be_ops,
  6508. .ignore_suspend = 1,
  6509. .ignore_pmdown_time = 1,
  6510. },
  6511. {
  6512. .name = LPASS_BE_SEC_MI2S_TX,
  6513. .stream_name = "Secondary MI2S Capture",
  6514. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6515. .platform_name = "msm-pcm-routing",
  6516. .codec_name = "msm-stub-codec.1",
  6517. .codec_dai_name = "msm-stub-tx",
  6518. .no_pcm = 1,
  6519. .dpcm_capture = 1,
  6520. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6521. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6522. .ops = &msm_mi2s_be_ops,
  6523. .ignore_suspend = 1,
  6524. },
  6525. {
  6526. .name = LPASS_BE_TERT_MI2S_RX,
  6527. .stream_name = "Tertiary MI2S Playback",
  6528. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6529. .platform_name = "msm-pcm-routing",
  6530. .codec_name = "msm-stub-codec.1",
  6531. .codec_dai_name = "msm-stub-rx",
  6532. .no_pcm = 1,
  6533. .dpcm_playback = 1,
  6534. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6535. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6536. .ops = &msm_mi2s_be_ops,
  6537. .ignore_suspend = 1,
  6538. .ignore_pmdown_time = 1,
  6539. },
  6540. {
  6541. .name = LPASS_BE_TERT_MI2S_TX,
  6542. .stream_name = "Tertiary MI2S Capture",
  6543. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6544. .platform_name = "msm-pcm-routing",
  6545. .codec_name = "msm-stub-codec.1",
  6546. .codec_dai_name = "msm-stub-tx",
  6547. .no_pcm = 1,
  6548. .dpcm_capture = 1,
  6549. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6550. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6551. .ops = &msm_mi2s_be_ops,
  6552. .ignore_suspend = 1,
  6553. },
  6554. {
  6555. .name = LPASS_BE_QUAT_MI2S_RX,
  6556. .stream_name = "Quaternary MI2S Playback",
  6557. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6558. .platform_name = "msm-pcm-routing",
  6559. .codec_name = "msm-stub-codec.1",
  6560. .codec_dai_name = "msm-stub-rx",
  6561. .no_pcm = 1,
  6562. .dpcm_playback = 1,
  6563. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6564. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6565. .ops = &msm_mi2s_be_ops,
  6566. .ignore_suspend = 1,
  6567. .ignore_pmdown_time = 1,
  6568. },
  6569. {
  6570. .name = LPASS_BE_QUAT_MI2S_TX,
  6571. .stream_name = "Quaternary MI2S Capture",
  6572. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6573. .platform_name = "msm-pcm-routing",
  6574. .codec_name = "msm-stub-codec.1",
  6575. .codec_dai_name = "msm-stub-tx",
  6576. .no_pcm = 1,
  6577. .dpcm_capture = 1,
  6578. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6579. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6580. .ops = &msm_mi2s_be_ops,
  6581. .ignore_suspend = 1,
  6582. },
  6583. {
  6584. .name = LPASS_BE_QUIN_MI2S_RX,
  6585. .stream_name = "Quinary MI2S Playback",
  6586. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6587. .platform_name = "msm-pcm-routing",
  6588. .codec_name = "msm-stub-codec.1",
  6589. .codec_dai_name = "msm-stub-rx",
  6590. .no_pcm = 1,
  6591. .dpcm_playback = 1,
  6592. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6593. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6594. .ops = &msm_mi2s_be_ops,
  6595. .ignore_suspend = 1,
  6596. .ignore_pmdown_time = 1,
  6597. },
  6598. {
  6599. .name = LPASS_BE_QUIN_MI2S_TX,
  6600. .stream_name = "Quinary MI2S Capture",
  6601. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6602. .platform_name = "msm-pcm-routing",
  6603. .codec_name = "msm-stub-codec.1",
  6604. .codec_dai_name = "msm-stub-tx",
  6605. .no_pcm = 1,
  6606. .dpcm_capture = 1,
  6607. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6608. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6609. .ops = &msm_mi2s_be_ops,
  6610. .ignore_suspend = 1,
  6611. },
  6612. };
  6613. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6614. /* Primary AUX PCM Backend DAI Links */
  6615. {
  6616. .name = LPASS_BE_AUXPCM_RX,
  6617. .stream_name = "AUX PCM Playback",
  6618. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6619. .platform_name = "msm-pcm-routing",
  6620. .codec_name = "msm-stub-codec.1",
  6621. .codec_dai_name = "msm-stub-rx",
  6622. .no_pcm = 1,
  6623. .dpcm_playback = 1,
  6624. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6625. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6626. .ops = &msm_auxpcm_be_ops,
  6627. .ignore_pmdown_time = 1,
  6628. .ignore_suspend = 1,
  6629. },
  6630. {
  6631. .name = LPASS_BE_AUXPCM_TX,
  6632. .stream_name = "AUX PCM Capture",
  6633. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6634. .platform_name = "msm-pcm-routing",
  6635. .codec_name = "msm-stub-codec.1",
  6636. .codec_dai_name = "msm-stub-tx",
  6637. .no_pcm = 1,
  6638. .dpcm_capture = 1,
  6639. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6640. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6641. .ops = &msm_auxpcm_be_ops,
  6642. .ignore_suspend = 1,
  6643. },
  6644. /* Secondary AUX PCM Backend DAI Links */
  6645. {
  6646. .name = LPASS_BE_SEC_AUXPCM_RX,
  6647. .stream_name = "Sec AUX PCM Playback",
  6648. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6649. .platform_name = "msm-pcm-routing",
  6650. .codec_name = "msm-stub-codec.1",
  6651. .codec_dai_name = "msm-stub-rx",
  6652. .no_pcm = 1,
  6653. .dpcm_playback = 1,
  6654. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6655. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6656. .ops = &msm_auxpcm_be_ops,
  6657. .ignore_pmdown_time = 1,
  6658. .ignore_suspend = 1,
  6659. },
  6660. {
  6661. .name = LPASS_BE_SEC_AUXPCM_TX,
  6662. .stream_name = "Sec AUX PCM Capture",
  6663. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6664. .platform_name = "msm-pcm-routing",
  6665. .codec_name = "msm-stub-codec.1",
  6666. .codec_dai_name = "msm-stub-tx",
  6667. .no_pcm = 1,
  6668. .dpcm_capture = 1,
  6669. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6670. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6671. .ops = &msm_auxpcm_be_ops,
  6672. .ignore_suspend = 1,
  6673. },
  6674. /* Tertiary AUX PCM Backend DAI Links */
  6675. {
  6676. .name = LPASS_BE_TERT_AUXPCM_RX,
  6677. .stream_name = "Tert AUX PCM Playback",
  6678. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6679. .platform_name = "msm-pcm-routing",
  6680. .codec_name = "msm-stub-codec.1",
  6681. .codec_dai_name = "msm-stub-rx",
  6682. .no_pcm = 1,
  6683. .dpcm_playback = 1,
  6684. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6685. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6686. .ops = &msm_auxpcm_be_ops,
  6687. .ignore_suspend = 1,
  6688. },
  6689. {
  6690. .name = LPASS_BE_TERT_AUXPCM_TX,
  6691. .stream_name = "Tert AUX PCM Capture",
  6692. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6693. .platform_name = "msm-pcm-routing",
  6694. .codec_name = "msm-stub-codec.1",
  6695. .codec_dai_name = "msm-stub-tx",
  6696. .no_pcm = 1,
  6697. .dpcm_capture = 1,
  6698. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6699. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6700. .ops = &msm_auxpcm_be_ops,
  6701. .ignore_suspend = 1,
  6702. },
  6703. /* Quaternary AUX PCM Backend DAI Links */
  6704. {
  6705. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6706. .stream_name = "Quat AUX PCM Playback",
  6707. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6708. .platform_name = "msm-pcm-routing",
  6709. .codec_name = "msm-stub-codec.1",
  6710. .codec_dai_name = "msm-stub-rx",
  6711. .no_pcm = 1,
  6712. .dpcm_playback = 1,
  6713. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6714. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6715. .ops = &msm_auxpcm_be_ops,
  6716. .ignore_pmdown_time = 1,
  6717. .ignore_suspend = 1,
  6718. },
  6719. {
  6720. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6721. .stream_name = "Quat AUX PCM Capture",
  6722. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6723. .platform_name = "msm-pcm-routing",
  6724. .codec_name = "msm-stub-codec.1",
  6725. .codec_dai_name = "msm-stub-tx",
  6726. .no_pcm = 1,
  6727. .dpcm_capture = 1,
  6728. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6729. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6730. .ops = &msm_auxpcm_be_ops,
  6731. .ignore_suspend = 1,
  6732. },
  6733. /* Quinary AUX PCM Backend DAI Links */
  6734. {
  6735. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6736. .stream_name = "Quin AUX PCM Playback",
  6737. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6738. .platform_name = "msm-pcm-routing",
  6739. .codec_name = "msm-stub-codec.1",
  6740. .codec_dai_name = "msm-stub-rx",
  6741. .no_pcm = 1,
  6742. .dpcm_playback = 1,
  6743. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6744. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6745. .ops = &msm_auxpcm_be_ops,
  6746. .ignore_pmdown_time = 1,
  6747. .ignore_suspend = 1,
  6748. },
  6749. {
  6750. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6751. .stream_name = "Quin AUX PCM Capture",
  6752. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6753. .platform_name = "msm-pcm-routing",
  6754. .codec_name = "msm-stub-codec.1",
  6755. .codec_dai_name = "msm-stub-tx",
  6756. .no_pcm = 1,
  6757. .dpcm_capture = 1,
  6758. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6759. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6760. .ops = &msm_auxpcm_be_ops,
  6761. .ignore_suspend = 1,
  6762. },
  6763. };
  6764. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6765. /* WSA CDC DMA Backend DAI Links */
  6766. {
  6767. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6768. .stream_name = "WSA CDC DMA0 Playback",
  6769. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6770. .platform_name = "msm-pcm-routing",
  6771. .codec_name = "bolero_codec",
  6772. .codec_dai_name = "wsa_macro_rx1",
  6773. .no_pcm = 1,
  6774. .dpcm_playback = 1,
  6775. .init = &msm_wsa_cdc_dma_init,
  6776. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6777. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6778. .ignore_pmdown_time = 1,
  6779. .ignore_suspend = 1,
  6780. .ops = &msm_cdc_dma_be_ops,
  6781. },
  6782. {
  6783. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6784. .stream_name = "WSA CDC DMA1 Playback",
  6785. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6786. .platform_name = "msm-pcm-routing",
  6787. .codec_name = "bolero_codec",
  6788. .codec_dai_name = "wsa_macro_rx_mix",
  6789. .no_pcm = 1,
  6790. .dpcm_playback = 1,
  6791. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6792. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6793. .ignore_pmdown_time = 1,
  6794. .ignore_suspend = 1,
  6795. .ops = &msm_cdc_dma_be_ops,
  6796. },
  6797. {
  6798. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6799. .stream_name = "WSA CDC DMA1 Capture",
  6800. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6801. .platform_name = "msm-pcm-routing",
  6802. .codec_name = "bolero_codec",
  6803. .codec_dai_name = "wsa_macro_echo",
  6804. .no_pcm = 1,
  6805. .dpcm_capture = 1,
  6806. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6807. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6808. .ignore_suspend = 1,
  6809. .ops = &msm_cdc_dma_be_ops,
  6810. },
  6811. };
  6812. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6813. {
  6814. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6815. .stream_name = "VA CDC DMA0 Capture",
  6816. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6817. .platform_name = "msm-pcm-routing",
  6818. .codec_name = "bolero_codec",
  6819. .codec_dai_name = "va_macro_tx1",
  6820. .no_pcm = 1,
  6821. .dpcm_capture = 1,
  6822. .init = &msm_va_cdc_dma_init,
  6823. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6824. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6825. .ignore_suspend = 1,
  6826. .ops = &msm_cdc_dma_be_ops,
  6827. },
  6828. {
  6829. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6830. .stream_name = "VA CDC DMA1 Capture",
  6831. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6832. .platform_name = "msm-pcm-routing",
  6833. .codec_name = "bolero_codec",
  6834. .codec_dai_name = "va_macro_tx2",
  6835. .no_pcm = 1,
  6836. .dpcm_capture = 1,
  6837. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6838. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6839. .ignore_suspend = 1,
  6840. .ops = &msm_cdc_dma_be_ops,
  6841. },
  6842. };
  6843. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6844. {
  6845. .name = LPASS_BE_PRI_SPDIF_RX,
  6846. .stream_name = "Primary SPDIF Playback",
  6847. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6848. .platform_name = "msm-pcm-routing",
  6849. .codec_name = "msm-stub-codec.1",
  6850. .codec_dai_name = "msm-stub-rx",
  6851. .no_pcm = 1,
  6852. .dpcm_playback = 1,
  6853. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6854. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6855. .ops = &msm_spdif_be_ops,
  6856. .ignore_suspend = 1,
  6857. .ignore_pmdown_time = 1,
  6858. },
  6859. {
  6860. .name = LPASS_BE_PRI_SPDIF_TX,
  6861. .stream_name = "Primary SPDIF Capture",
  6862. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6863. .platform_name = "msm-pcm-routing",
  6864. .codec_name = "msm-stub-codec.1",
  6865. .codec_dai_name = "msm-stub-tx",
  6866. .no_pcm = 1,
  6867. .dpcm_capture = 1,
  6868. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6869. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6870. .ops = &msm_spdif_be_ops,
  6871. .ignore_suspend = 1,
  6872. },
  6873. {
  6874. .name = LPASS_BE_SEC_SPDIF_RX,
  6875. .stream_name = "Secondary SPDIF Playback",
  6876. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6877. .platform_name = "msm-pcm-routing",
  6878. .codec_name = "msm-stub-codec.1",
  6879. .codec_dai_name = "msm-stub-rx",
  6880. .no_pcm = 1,
  6881. .dpcm_playback = 1,
  6882. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6883. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6884. .ops = &msm_spdif_be_ops,
  6885. .ignore_suspend = 1,
  6886. .ignore_pmdown_time = 1,
  6887. },
  6888. {
  6889. .name = LPASS_BE_SEC_SPDIF_TX,
  6890. .stream_name = "Secondary SPDIF Capture",
  6891. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6892. .platform_name = "msm-pcm-routing",
  6893. .codec_name = "msm-stub-codec.1",
  6894. .codec_dai_name = "msm-stub-tx",
  6895. .no_pcm = 1,
  6896. .dpcm_capture = 1,
  6897. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6898. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6899. .ops = &msm_spdif_be_ops,
  6900. .ignore_suspend = 1,
  6901. },
  6902. };
  6903. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6904. {
  6905. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6906. .stream_name = "AFE Loopback Capture",
  6907. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6908. .platform_name = "msm-pcm-routing",
  6909. .codec_name = "msm-stub-codec.1",
  6910. .codec_dai_name = "msm-stub-tx",
  6911. .no_pcm = 1,
  6912. .dpcm_capture = 1,
  6913. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6914. .ignore_pmdown_time = 1,
  6915. .ignore_suspend = 1,
  6916. },
  6917. };
  6918. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6919. ARRAY_SIZE(msm_common_dai_links) +
  6920. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6921. ARRAY_SIZE(msm_common_be_dai_links) +
  6922. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6923. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6924. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6925. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6926. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6927. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6928. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6929. ARRAY_SIZE(msm_spdif_be_dai_links) +
  6930. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link)];
  6931. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6932. {
  6933. int ret = 0;
  6934. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6935. &service_nb);
  6936. if (ret < 0)
  6937. pr_err("%s: Audio notifier register failed ret = %d\n",
  6938. __func__, ret);
  6939. return ret;
  6940. }
  6941. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6942. struct snd_ctl_elem_value *ucontrol)
  6943. {
  6944. int ret = 0;
  6945. int port_id;
  6946. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6947. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6948. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6949. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6950. (vad_enable < 0) || (vad_enable > 1) ||
  6951. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6952. pr_err("%s: Invalid arguments\n", __func__);
  6953. ret = -EINVAL;
  6954. goto done;
  6955. }
  6956. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6957. vad_enable, preroll_config, vad_intf);
  6958. ret = msm_island_vad_get_portid_from_beid(vad_intf, &port_id);
  6959. if (ret) {
  6960. pr_err("%s: Invalid vad interface\n", __func__);
  6961. goto done;
  6962. }
  6963. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6964. done:
  6965. return ret;
  6966. }
  6967. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6968. {
  6969. int ret = 0;
  6970. uint32_t tasha_codec = 0;
  6971. ret = afe_cal_init_hwdep(card);
  6972. if (ret) {
  6973. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6974. ret = 0;
  6975. }
  6976. /* tasha late probe when it is present */
  6977. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6978. &tasha_codec);
  6979. if (ret) {
  6980. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6981. ret = 0;
  6982. } else {
  6983. if (tasha_codec) {
  6984. ret = msm_snd_card_tasha_late_probe(card);
  6985. if (ret)
  6986. dev_err(card->dev, "%s: tasha late probe err\n",
  6987. __func__);
  6988. }
  6989. }
  6990. return ret;
  6991. }
  6992. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6993. .name = "qcs405-snd-card",
  6994. .controls = msm_snd_controls,
  6995. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6996. .late_probe = msm_snd_card_codec_late_probe,
  6997. };
  6998. static int msm_populate_dai_link_component_of_node(
  6999. struct snd_soc_card *card)
  7000. {
  7001. int i, index, ret = 0;
  7002. struct device *cdev = card->dev;
  7003. struct snd_soc_dai_link *dai_link = card->dai_link;
  7004. struct device_node *np;
  7005. if (!cdev) {
  7006. pr_err("%s: Sound card device memory NULL\n", __func__);
  7007. return -ENODEV;
  7008. }
  7009. for (i = 0; i < card->num_links; i++) {
  7010. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  7011. continue;
  7012. /* populate platform_of_node for snd card dai links */
  7013. if (dai_link[i].platform_name &&
  7014. !dai_link[i].platform_of_node) {
  7015. index = of_property_match_string(cdev->of_node,
  7016. "asoc-platform-names",
  7017. dai_link[i].platform_name);
  7018. if (index < 0) {
  7019. pr_err("%s: No match found for platform name: %s\n",
  7020. __func__, dai_link[i].platform_name);
  7021. ret = index;
  7022. goto err;
  7023. }
  7024. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  7025. index);
  7026. if (!np) {
  7027. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  7028. __func__, dai_link[i].platform_name,
  7029. index);
  7030. ret = -ENODEV;
  7031. goto err;
  7032. }
  7033. dai_link[i].platform_of_node = np;
  7034. dai_link[i].platform_name = NULL;
  7035. }
  7036. /* populate cpu_of_node for snd card dai links */
  7037. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  7038. index = of_property_match_string(cdev->of_node,
  7039. "asoc-cpu-names",
  7040. dai_link[i].cpu_dai_name);
  7041. if (index >= 0) {
  7042. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  7043. index);
  7044. if (!np) {
  7045. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  7046. __func__,
  7047. dai_link[i].cpu_dai_name);
  7048. ret = -ENODEV;
  7049. goto err;
  7050. }
  7051. dai_link[i].cpu_of_node = np;
  7052. dai_link[i].cpu_dai_name = NULL;
  7053. }
  7054. }
  7055. /* populate codec_of_node for snd card dai links */
  7056. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  7057. index = of_property_match_string(cdev->of_node,
  7058. "asoc-codec-names",
  7059. dai_link[i].codec_name);
  7060. if (index < 0)
  7061. continue;
  7062. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  7063. index);
  7064. if (!np) {
  7065. pr_err("%s: retrieving phandle for codec %s failed\n",
  7066. __func__, dai_link[i].codec_name);
  7067. ret = -ENODEV;
  7068. goto err;
  7069. }
  7070. dai_link[i].codec_of_node = np;
  7071. dai_link[i].codec_name = NULL;
  7072. }
  7073. }
  7074. err:
  7075. return ret;
  7076. }
  7077. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  7078. /* FrontEnd DAI Links */
  7079. {
  7080. .name = "MSMSTUB Media1",
  7081. .stream_name = "MultiMedia1",
  7082. .cpu_dai_name = "MultiMedia1",
  7083. .platform_name = "msm-pcm-dsp.0",
  7084. .dynamic = 1,
  7085. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  7086. .dpcm_playback = 1,
  7087. .dpcm_capture = 1,
  7088. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  7089. SND_SOC_DPCM_TRIGGER_POST},
  7090. .codec_dai_name = "snd-soc-dummy-dai",
  7091. .codec_name = "snd-soc-dummy",
  7092. .ignore_suspend = 1,
  7093. /* this dainlink has playback support */
  7094. .ignore_pmdown_time = 1,
  7095. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  7096. },
  7097. };
  7098. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  7099. /* Backend DAI Links */
  7100. {
  7101. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  7102. .stream_name = "VA CDC DMA0 Capture",
  7103. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  7104. .platform_name = "msm-pcm-routing",
  7105. .codec_name = "bolero_codec",
  7106. .codec_dai_name = "va_macro_tx1",
  7107. .no_pcm = 1,
  7108. .dpcm_capture = 1,
  7109. .init = &msm_va_cdc_dma_init,
  7110. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  7111. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7112. .ignore_suspend = 1,
  7113. .ops = &msm_cdc_dma_be_ops,
  7114. },
  7115. {
  7116. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  7117. .stream_name = "VA CDC DMA1 Capture",
  7118. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  7119. .platform_name = "msm-pcm-routing",
  7120. .codec_name = "bolero_codec",
  7121. .codec_dai_name = "va_macro_tx2",
  7122. .no_pcm = 1,
  7123. .dpcm_capture = 1,
  7124. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7125. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7126. .ignore_suspend = 1,
  7127. .ops = &msm_cdc_dma_be_ops,
  7128. },
  7129. };
  7130. static struct snd_soc_dai_link msm_stub_dai_links[
  7131. ARRAY_SIZE(msm_stub_fe_dai_links) +
  7132. ARRAY_SIZE(msm_stub_be_dai_links)];
  7133. struct snd_soc_card snd_soc_card_stub_msm = {
  7134. .name = "qcs405-stub-snd-card",
  7135. };
  7136. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  7137. { .compatible = "qcom,qcs405-asoc-snd",
  7138. .data = "codec"},
  7139. { .compatible = "qcom,qcs405-asoc-snd-stub",
  7140. .data = "stub_codec"},
  7141. {},
  7142. };
  7143. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  7144. {
  7145. struct snd_soc_card *card = NULL;
  7146. struct snd_soc_dai_link *dailink;
  7147. int total_links = 0;
  7148. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  7149. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  7150. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  7151. uint32_t afe_loopback_intf = 0;
  7152. const struct of_device_id *match;
  7153. char __iomem *spdif_cfg, *spdif_pin_ctl;
  7154. int rc = 0;
  7155. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  7156. if (!match) {
  7157. dev_err(dev, "%s: No DT match found for sound card\n",
  7158. __func__);
  7159. return NULL;
  7160. }
  7161. if (!strcmp(match->data, "codec")) {
  7162. card = &snd_soc_card_qcs405_msm;
  7163. memcpy(msm_qcs405_dai_links + total_links,
  7164. msm_common_dai_links,
  7165. sizeof(msm_common_dai_links));
  7166. total_links += ARRAY_SIZE(msm_common_dai_links);
  7167. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  7168. &wsa_bolero_codec);
  7169. if (rc) {
  7170. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  7171. __func__);
  7172. } else {
  7173. if (wsa_bolero_codec) {
  7174. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  7175. __func__);
  7176. memcpy(msm_qcs405_dai_links + total_links,
  7177. msm_bolero_fe_dai_links,
  7178. sizeof(msm_bolero_fe_dai_links));
  7179. total_links +=
  7180. ARRAY_SIZE(msm_bolero_fe_dai_links);
  7181. }
  7182. }
  7183. memcpy(msm_qcs405_dai_links + total_links,
  7184. msm_common_misc_fe_dai_links,
  7185. sizeof(msm_common_misc_fe_dai_links));
  7186. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  7187. memcpy(msm_qcs405_dai_links + total_links,
  7188. msm_common_be_dai_links,
  7189. sizeof(msm_common_be_dai_links));
  7190. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  7191. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  7192. &tasha_codec);
  7193. if (rc) {
  7194. dev_dbg(dev, "%s: No DT match tasha codec\n",
  7195. __func__);
  7196. } else {
  7197. if (tasha_codec) {
  7198. memcpy(msm_qcs405_dai_links + total_links,
  7199. msm_tasha_be_dai_links,
  7200. sizeof(msm_tasha_be_dai_links));
  7201. total_links +=
  7202. ARRAY_SIZE(msm_tasha_be_dai_links);
  7203. }
  7204. }
  7205. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  7206. &va_bolero_codec);
  7207. if (rc) {
  7208. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  7209. __func__);
  7210. } else {
  7211. if (va_bolero_codec) {
  7212. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  7213. __func__);
  7214. memcpy(msm_qcs405_dai_links + total_links,
  7215. msm_va_cdc_dma_be_dai_links,
  7216. sizeof(msm_va_cdc_dma_be_dai_links));
  7217. total_links +=
  7218. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  7219. }
  7220. }
  7221. if (wsa_bolero_codec) {
  7222. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  7223. __func__);
  7224. memcpy(msm_qcs405_dai_links + total_links,
  7225. msm_wsa_cdc_dma_be_dai_links,
  7226. sizeof(msm_wsa_cdc_dma_be_dai_links));
  7227. total_links +=
  7228. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  7229. }
  7230. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  7231. &mi2s_audio_intf);
  7232. if (rc) {
  7233. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  7234. __func__);
  7235. } else {
  7236. if (mi2s_audio_intf) {
  7237. memcpy(msm_qcs405_dai_links + total_links,
  7238. msm_mi2s_be_dai_links,
  7239. sizeof(msm_mi2s_be_dai_links));
  7240. total_links +=
  7241. ARRAY_SIZE(msm_mi2s_be_dai_links);
  7242. }
  7243. }
  7244. rc = of_property_read_u32(dev->of_node,
  7245. "qcom,auxpcm-audio-intf",
  7246. &auxpcm_audio_intf);
  7247. if (rc) {
  7248. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  7249. __func__);
  7250. } else {
  7251. if (auxpcm_audio_intf) {
  7252. memcpy(msm_qcs405_dai_links + total_links,
  7253. msm_auxpcm_be_dai_links,
  7254. sizeof(msm_auxpcm_be_dai_links));
  7255. total_links +=
  7256. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  7257. }
  7258. }
  7259. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  7260. &spdif_audio_intf);
  7261. if (rc) {
  7262. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  7263. __func__);
  7264. } else {
  7265. if (spdif_audio_intf) {
  7266. memcpy(msm_qcs405_dai_links + total_links,
  7267. msm_spdif_be_dai_links,
  7268. sizeof(msm_spdif_be_dai_links));
  7269. total_links +=
  7270. ARRAY_SIZE(msm_spdif_be_dai_links);
  7271. /* enable spdif coax pins */
  7272. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7273. spdif_pin_ctl =
  7274. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7275. iowrite32(0xc0, spdif_cfg);
  7276. iowrite32(0x2220, spdif_pin_ctl);
  7277. }
  7278. }
  7279. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7280. &wcn_audio_intf);
  7281. if (rc) {
  7282. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7283. __func__);
  7284. } else {
  7285. if (wcn_audio_intf) {
  7286. memcpy(msm_qcs405_dai_links + total_links,
  7287. msm_wcn_be_dai_links,
  7288. sizeof(msm_wcn_be_dai_links));
  7289. total_links +=
  7290. ARRAY_SIZE(msm_wcn_be_dai_links);
  7291. }
  7292. }
  7293. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  7294. &afe_loopback_intf);
  7295. if (rc) {
  7296. dev_dbg(dev, "%s: No DT match AFE loopback audio interface\n",
  7297. __func__);
  7298. } else {
  7299. if (afe_loopback_intf) {
  7300. memcpy(msm_qcs405_dai_links + total_links,
  7301. msm_afe_rxtx_lb_be_dai_link,
  7302. sizeof(msm_afe_rxtx_lb_be_dai_link));
  7303. total_links +=
  7304. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  7305. }
  7306. }
  7307. dailink = msm_qcs405_dai_links;
  7308. } else if (!strcmp(match->data, "stub_codec")) {
  7309. card = &snd_soc_card_stub_msm;
  7310. memcpy(msm_stub_dai_links + total_links,
  7311. msm_stub_fe_dai_links,
  7312. sizeof(msm_stub_fe_dai_links));
  7313. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7314. memcpy(msm_stub_dai_links + total_links,
  7315. msm_stub_be_dai_links,
  7316. sizeof(msm_stub_be_dai_links));
  7317. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7318. dailink = msm_stub_dai_links;
  7319. }
  7320. if (card) {
  7321. card->dai_link = dailink;
  7322. card->num_links = total_links;
  7323. }
  7324. return card;
  7325. }
  7326. static int msm_wsa881x_init(struct snd_soc_component *component)
  7327. {
  7328. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7329. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7330. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7331. SPKR_L_BOOST, SPKR_L_VI};
  7332. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7333. SPKR_R_BOOST, SPKR_R_VI};
  7334. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7335. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7336. struct msm_asoc_mach_data *pdata;
  7337. struct snd_soc_dapm_context *dapm;
  7338. int ret = 0;
  7339. if (!component) {
  7340. pr_err("%s component is NULL\n", __func__);
  7341. return -EINVAL;
  7342. }
  7343. dapm = snd_soc_component_get_dapm(component);
  7344. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7345. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  7346. __func__, component->name);
  7347. wsa881x_set_channel_map(component, &spkleft_ports[0],
  7348. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7349. &ch_rate[0], &spkleft_port_types[0]);
  7350. if (dapm->component) {
  7351. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7352. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7353. }
  7354. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7355. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  7356. __func__, component->name);
  7357. wsa881x_set_channel_map(component, &spkright_ports[0],
  7358. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7359. &ch_rate[0], &spkright_port_types[0]);
  7360. if (dapm->component) {
  7361. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7362. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7363. }
  7364. } else {
  7365. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  7366. component->name);
  7367. ret = -EINVAL;
  7368. goto err;
  7369. }
  7370. pdata = snd_soc_card_get_drvdata(component->card);
  7371. if (pdata && pdata->codec_root)
  7372. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7373. component);
  7374. err:
  7375. return ret;
  7376. }
  7377. static int msm_init_wsa_dev(struct platform_device *pdev,
  7378. struct snd_soc_card *card)
  7379. {
  7380. struct device_node *wsa_of_node;
  7381. u32 wsa_max_devs;
  7382. u32 wsa_dev_cnt;
  7383. int i;
  7384. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7385. const char *wsa_auxdev_name_prefix[1];
  7386. char *dev_name_str = NULL;
  7387. int found = 0;
  7388. int ret = 0;
  7389. /* Get maximum WSA device count for this platform */
  7390. ret = of_property_read_u32(pdev->dev.of_node,
  7391. "qcom,wsa-max-devs", &wsa_max_devs);
  7392. if (ret) {
  7393. dev_info(&pdev->dev,
  7394. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7395. __func__, pdev->dev.of_node->full_name, ret);
  7396. card->num_aux_devs = 0;
  7397. return 0;
  7398. }
  7399. if (wsa_max_devs == 0) {
  7400. dev_warn(&pdev->dev,
  7401. "%s: Max WSA devices is 0 for this target?\n",
  7402. __func__);
  7403. card->num_aux_devs = 0;
  7404. return 0;
  7405. }
  7406. /* Get count of WSA device phandles for this platform */
  7407. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7408. "qcom,wsa-devs", NULL);
  7409. if (wsa_dev_cnt == -ENOENT) {
  7410. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7411. __func__);
  7412. goto err;
  7413. } else if (wsa_dev_cnt <= 0) {
  7414. dev_err(&pdev->dev,
  7415. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7416. __func__, wsa_dev_cnt);
  7417. ret = -EINVAL;
  7418. goto err;
  7419. }
  7420. /*
  7421. * Expect total phandles count to be NOT less than maximum possible
  7422. * WSA count. However, if it is less, then assign same value to
  7423. * max count as well.
  7424. */
  7425. if (wsa_dev_cnt < wsa_max_devs) {
  7426. dev_dbg(&pdev->dev,
  7427. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7428. __func__, wsa_max_devs, wsa_dev_cnt);
  7429. wsa_max_devs = wsa_dev_cnt;
  7430. }
  7431. /* Make sure prefix string passed for each WSA device */
  7432. ret = of_property_count_strings(pdev->dev.of_node,
  7433. "qcom,wsa-aux-dev-prefix");
  7434. if (ret != wsa_dev_cnt) {
  7435. dev_err(&pdev->dev,
  7436. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7437. __func__, wsa_dev_cnt, ret);
  7438. ret = -EINVAL;
  7439. goto err;
  7440. }
  7441. /*
  7442. * Alloc mem to store phandle and index info of WSA device, if already
  7443. * registered with ALSA core
  7444. */
  7445. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7446. sizeof(struct msm_wsa881x_dev_info),
  7447. GFP_KERNEL);
  7448. if (!wsa881x_dev_info) {
  7449. ret = -ENOMEM;
  7450. goto err;
  7451. }
  7452. /*
  7453. * search and check whether all WSA devices are already
  7454. * registered with ALSA core or not. If found a node, store
  7455. * the node and the index in a local array of struct for later
  7456. * use.
  7457. */
  7458. for (i = 0; i < wsa_dev_cnt; i++) {
  7459. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7460. "qcom,wsa-devs", i);
  7461. if (unlikely(!wsa_of_node)) {
  7462. /* we should not be here */
  7463. dev_err(&pdev->dev,
  7464. "%s: wsa dev node is not present\n",
  7465. __func__);
  7466. ret = -EINVAL;
  7467. goto err_free_dev_info;
  7468. }
  7469. if (soc_find_component(wsa_of_node, NULL)) {
  7470. /* WSA device registered with ALSA core */
  7471. wsa881x_dev_info[found].of_node = wsa_of_node;
  7472. wsa881x_dev_info[found].index = i;
  7473. found++;
  7474. if (found == wsa_max_devs)
  7475. break;
  7476. }
  7477. }
  7478. if (found < wsa_max_devs) {
  7479. dev_err(&pdev->dev,
  7480. "%s: failed to find %d components. Found only %d\n",
  7481. __func__, wsa_max_devs, found);
  7482. return -EPROBE_DEFER;
  7483. }
  7484. dev_info(&pdev->dev,
  7485. "%s: found %d wsa881x devices registered with ALSA core\n",
  7486. __func__, found);
  7487. card->num_aux_devs = wsa_max_devs;
  7488. card->num_configs = wsa_max_devs;
  7489. /* Alloc array of AUX devs struct */
  7490. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7491. sizeof(struct snd_soc_aux_dev),
  7492. GFP_KERNEL);
  7493. if (!msm_aux_dev) {
  7494. ret = -ENOMEM;
  7495. goto err_free_dev_info;
  7496. }
  7497. /* Alloc array of codec conf struct */
  7498. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7499. sizeof(struct snd_soc_codec_conf),
  7500. GFP_KERNEL);
  7501. if (!msm_codec_conf) {
  7502. ret = -ENOMEM;
  7503. goto err_free_aux_dev;
  7504. }
  7505. for (i = 0; i < card->num_aux_devs; i++) {
  7506. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7507. GFP_KERNEL);
  7508. if (!dev_name_str) {
  7509. ret = -ENOMEM;
  7510. goto err_free_cdc_conf;
  7511. }
  7512. ret = of_property_read_string_index(pdev->dev.of_node,
  7513. "qcom,wsa-aux-dev-prefix",
  7514. wsa881x_dev_info[i].index,
  7515. wsa_auxdev_name_prefix);
  7516. if (ret) {
  7517. dev_err(&pdev->dev,
  7518. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7519. __func__, ret);
  7520. ret = -EINVAL;
  7521. goto err_free_dev_name_str;
  7522. }
  7523. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7524. msm_aux_dev[i].name = dev_name_str;
  7525. msm_aux_dev[i].codec_name = NULL;
  7526. msm_aux_dev[i].codec_of_node =
  7527. wsa881x_dev_info[i].of_node;
  7528. msm_aux_dev[i].init = msm_wsa881x_init;
  7529. msm_codec_conf[i].dev_name = NULL;
  7530. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7531. msm_codec_conf[i].of_node =
  7532. wsa881x_dev_info[i].of_node;
  7533. }
  7534. card->codec_conf = msm_codec_conf;
  7535. card->aux_dev = msm_aux_dev;
  7536. return 0;
  7537. err_free_dev_name_str:
  7538. devm_kfree(&pdev->dev, dev_name_str);
  7539. err_free_cdc_conf:
  7540. devm_kfree(&pdev->dev, msm_codec_conf);
  7541. err_free_aux_dev:
  7542. devm_kfree(&pdev->dev, msm_aux_dev);
  7543. err_free_dev_info:
  7544. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7545. err:
  7546. return ret;
  7547. }
  7548. static int msm_csra66x0_init(struct snd_soc_component *component)
  7549. {
  7550. if (!component) {
  7551. pr_err("%s component is NULL\n", __func__);
  7552. return -EINVAL;
  7553. }
  7554. return 0;
  7555. }
  7556. static int msm_init_csra_dev(struct platform_device *pdev,
  7557. struct snd_soc_card *card)
  7558. {
  7559. struct device_node *csra_of_node;
  7560. u32 csra_max_devs;
  7561. u32 csra_dev_cnt;
  7562. char *dev_name_str = NULL;
  7563. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7564. const char *csra_auxdev_name_prefix[1];
  7565. int i;
  7566. int found = 0;
  7567. int ret = 0;
  7568. /* Get maximum CSRA device count for this platform */
  7569. ret = of_property_read_u32(pdev->dev.of_node,
  7570. "qcom,csra-max-devs", &csra_max_devs);
  7571. if (ret) {
  7572. dev_info(&pdev->dev,
  7573. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7574. __func__, pdev->dev.of_node->full_name, ret);
  7575. card->num_aux_devs = 0;
  7576. return 0;
  7577. }
  7578. if (csra_max_devs == 0) {
  7579. dev_warn(&pdev->dev,
  7580. "%s: Max CSRA devices is 0 for this target?\n",
  7581. __func__);
  7582. return 0;
  7583. }
  7584. /* Get count of CSRA device phandles for this platform */
  7585. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7586. "qcom,csra-devs", NULL);
  7587. if (csra_dev_cnt == -ENOENT) {
  7588. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7589. __func__);
  7590. goto err;
  7591. } else if (csra_dev_cnt <= 0) {
  7592. dev_err(&pdev->dev,
  7593. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7594. __func__, csra_dev_cnt);
  7595. ret = -EINVAL;
  7596. goto err;
  7597. }
  7598. /*
  7599. * Expect total phandles count to be NOT less than maximum possible
  7600. * CSRA count. However, if it is less, then assign same value to
  7601. * max count as well.
  7602. */
  7603. if (csra_dev_cnt < csra_max_devs) {
  7604. dev_dbg(&pdev->dev,
  7605. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7606. __func__, csra_max_devs, csra_dev_cnt);
  7607. csra_max_devs = csra_dev_cnt;
  7608. }
  7609. /* Make sure prefix string passed for each CSRA device */
  7610. ret = of_property_count_strings(pdev->dev.of_node,
  7611. "qcom,csra-aux-dev-prefix");
  7612. if (ret != csra_dev_cnt) {
  7613. dev_err(&pdev->dev,
  7614. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7615. __func__, csra_dev_cnt, ret);
  7616. ret = -EINVAL;
  7617. goto err;
  7618. }
  7619. /*
  7620. * Alloc mem to store phandle and index info of CSRA device, if already
  7621. * registered with ALSA core
  7622. */
  7623. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7624. sizeof(struct msm_csra66x0_dev_info),
  7625. GFP_KERNEL);
  7626. if (!csra66x0_dev_info) {
  7627. ret = -ENOMEM;
  7628. goto err;
  7629. }
  7630. /*
  7631. * search and check whether all CSRA devices are already
  7632. * registered with ALSA core or not. If found a node, store
  7633. * the node and the index in a local array of struct for later
  7634. * use.
  7635. */
  7636. for (i = 0; i < csra_dev_cnt; i++) {
  7637. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7638. "qcom,csra-devs", i);
  7639. if (unlikely(!csra_of_node)) {
  7640. /* we should not be here */
  7641. dev_err(&pdev->dev,
  7642. "%s: csra dev node is not present\n",
  7643. __func__);
  7644. ret = -EINVAL;
  7645. goto err_free_dev_info;
  7646. }
  7647. if (soc_find_component(csra_of_node, NULL)) {
  7648. /* CSRA device registered with ALSA core */
  7649. csra66x0_dev_info[found].of_node = csra_of_node;
  7650. csra66x0_dev_info[found].index = i;
  7651. found++;
  7652. if (found == csra_max_devs)
  7653. break;
  7654. }
  7655. }
  7656. if (found < csra_max_devs) {
  7657. dev_dbg(&pdev->dev,
  7658. "%s: failed to find %d components. Found only %d\n",
  7659. __func__, csra_max_devs, found);
  7660. return -EPROBE_DEFER;
  7661. }
  7662. dev_info(&pdev->dev,
  7663. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7664. __func__, found);
  7665. card->num_aux_devs = csra_max_devs;
  7666. card->num_configs = csra_max_devs;
  7667. /* Alloc array of AUX devs struct */
  7668. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7669. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7670. if (!msm_aux_dev) {
  7671. ret = -ENOMEM;
  7672. goto err_free_dev_info;
  7673. }
  7674. /* Alloc array of codec conf struct */
  7675. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7676. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7677. if (!msm_codec_conf) {
  7678. ret = -ENOMEM;
  7679. goto err_free_aux_dev;
  7680. }
  7681. for (i = 0; i < card->num_aux_devs; i++) {
  7682. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7683. GFP_KERNEL);
  7684. if (!dev_name_str) {
  7685. ret = -ENOMEM;
  7686. goto err_free_cdc_conf;
  7687. }
  7688. ret = of_property_read_string_index(pdev->dev.of_node,
  7689. "qcom,csra-aux-dev-prefix",
  7690. csra66x0_dev_info[i].index,
  7691. csra_auxdev_name_prefix);
  7692. if (ret) {
  7693. dev_err(&pdev->dev,
  7694. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7695. __func__, ret);
  7696. ret = -EINVAL;
  7697. goto err_free_dev_name_str;
  7698. }
  7699. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7700. msm_aux_dev[i].name = dev_name_str;
  7701. msm_aux_dev[i].codec_name = NULL;
  7702. msm_aux_dev[i].codec_of_node =
  7703. csra66x0_dev_info[i].of_node;
  7704. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7705. msm_codec_conf[i].dev_name = NULL;
  7706. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7707. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7708. }
  7709. card->codec_conf = msm_codec_conf;
  7710. card->aux_dev = msm_aux_dev;
  7711. return 0;
  7712. err_free_dev_name_str:
  7713. devm_kfree(&pdev->dev, dev_name_str);
  7714. err_free_cdc_conf:
  7715. devm_kfree(&pdev->dev, msm_codec_conf);
  7716. err_free_aux_dev:
  7717. devm_kfree(&pdev->dev, msm_aux_dev);
  7718. err_free_dev_info:
  7719. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7720. err:
  7721. return ret;
  7722. }
  7723. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7724. {
  7725. int count;
  7726. u32 mi2s_master_slave[MI2S_MAX];
  7727. int ret;
  7728. for (count = 0; count < MI2S_MAX; count++) {
  7729. mutex_init(&mi2s_intf_conf[count].lock);
  7730. mi2s_intf_conf[count].ref_cnt = 0;
  7731. }
  7732. ret = of_property_read_u32_array(pdev->dev.of_node,
  7733. "qcom,msm-mi2s-master",
  7734. mi2s_master_slave, MI2S_MAX);
  7735. if (ret) {
  7736. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7737. __func__);
  7738. } else {
  7739. for (count = 0; count < MI2S_MAX; count++) {
  7740. mi2s_intf_conf[count].msm_is_mi2s_master =
  7741. mi2s_master_slave[count];
  7742. }
  7743. }
  7744. }
  7745. static void msm_i2s_auxpcm_deinit(void)
  7746. {
  7747. int count;
  7748. for (count = 0; count < MI2S_MAX; count++) {
  7749. mutex_destroy(&mi2s_intf_conf[count].lock);
  7750. mi2s_intf_conf[count].ref_cnt = 0;
  7751. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7752. }
  7753. }
  7754. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7755. uint32_t busnum, uint32_t addr)
  7756. {
  7757. struct i2c_adapter *adap;
  7758. u8 rbuf;
  7759. struct i2c_msg msg;
  7760. int status = 0;
  7761. adap = i2c_get_adapter(busnum);
  7762. if (!adap) {
  7763. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7764. __func__, busnum);
  7765. return -EBUSY;
  7766. }
  7767. /* to test presence, read one byte from device */
  7768. msg.addr = addr;
  7769. msg.flags = I2C_M_RD;
  7770. msg.len = 1;
  7771. msg.buf = &rbuf;
  7772. status = i2c_transfer(adap, &msg, 1);
  7773. i2c_put_adapter(adap);
  7774. if (status != 1) {
  7775. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7776. __func__, addr);
  7777. return -ENODEV;
  7778. }
  7779. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7780. __func__, addr);
  7781. return 0;
  7782. }
  7783. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7784. struct snd_soc_card *card)
  7785. {
  7786. int i;
  7787. uint32_t ep92_busnum = 0;
  7788. uint32_t ep92_reg = 0;
  7789. const char *ep92_name = NULL;
  7790. struct snd_soc_dai_link *dai;
  7791. int rc = 0;
  7792. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7793. &ep92_busnum);
  7794. if (rc) {
  7795. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7796. return 0;
  7797. }
  7798. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7799. &ep92_reg);
  7800. if (rc) {
  7801. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7802. return 0;
  7803. }
  7804. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7805. &ep92_name);
  7806. if (rc) {
  7807. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7808. return 0;
  7809. }
  7810. /* check I2C bus for connected ep92 chip */
  7811. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7812. /* check a second time after a short delay */
  7813. msleep(20);
  7814. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7815. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7816. __func__);
  7817. /* continue with snd_card registration without ep92 */
  7818. return 0;
  7819. }
  7820. }
  7821. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7822. /* update codec info in MI2S dai link */
  7823. dai = &msm_mi2s_be_dai_links[0];
  7824. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7825. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7826. dev_dbg(&pdev->dev,
  7827. "%s: Set Sec MI2S dai to ep92 codec\n",
  7828. __func__);
  7829. dai->codec_name = ep92_name;
  7830. dai->codec_dai_name = "ep92-hdmi";
  7831. break;
  7832. }
  7833. dai++;
  7834. }
  7835. /* update codec info in SPDIF dai link */
  7836. dai = &msm_spdif_be_dai_links[0];
  7837. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7838. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7839. dev_dbg(&pdev->dev,
  7840. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7841. __func__);
  7842. dai->codec_name = ep92_name;
  7843. dai->codec_dai_name = "ep92-arc";
  7844. break;
  7845. }
  7846. dai++;
  7847. }
  7848. return 0;
  7849. }
  7850. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7851. {
  7852. struct snd_soc_card *card;
  7853. struct msm_asoc_mach_data *pdata;
  7854. int ret;
  7855. u32 val;
  7856. const char *micb_supply_str = "tdm-vdd-micb-supply";
  7857. const char *micb_supply_str1 = "tdm-vdd-micb";
  7858. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  7859. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  7860. if (!pdev->dev.of_node) {
  7861. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7862. return -EINVAL;
  7863. }
  7864. pdata = devm_kzalloc(&pdev->dev,
  7865. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7866. if (!pdata)
  7867. return -ENOMEM;
  7868. /* test for ep92 HDMI bridge and update dai links accordingly */
  7869. ret = msm_detect_ep92_dev(pdev, card);
  7870. if (ret)
  7871. goto err;
  7872. card = populate_snd_card_dailinks(&pdev->dev);
  7873. if (!card) {
  7874. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7875. ret = -EINVAL;
  7876. goto err;
  7877. }
  7878. card->dev = &pdev->dev;
  7879. platform_set_drvdata(pdev, card);
  7880. snd_soc_card_set_drvdata(card, pdata);
  7881. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7882. if (ret) {
  7883. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7884. ret);
  7885. goto err;
  7886. }
  7887. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7888. if (ret) {
  7889. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7890. ret);
  7891. goto err;
  7892. }
  7893. ret = msm_populate_dai_link_component_of_node(card);
  7894. if (ret) {
  7895. ret = -EPROBE_DEFER;
  7896. goto err;
  7897. }
  7898. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7899. if (ret) {
  7900. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7901. val = 0;
  7902. }
  7903. if (val) {
  7904. pdata->codec_is_csra = true;
  7905. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  7906. ret = msm_init_csra_dev(pdev, card);
  7907. if (ret)
  7908. goto err;
  7909. } else {
  7910. pdata->codec_is_csra = false;
  7911. ret = msm_init_wsa_dev(pdev, card);
  7912. if (ret)
  7913. goto err;
  7914. }
  7915. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7916. "qcom,cdc-dmic01-gpios", 0);
  7917. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7918. "qcom,cdc-dmic23-gpios", 0);
  7919. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7920. "qcom,cdc-dmic45-gpios", 0);
  7921. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7922. "qcom,cdc-dmic67-gpios", 0);
  7923. pdata->lineout_booster_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7924. "qcom,lineout-booster-gpio", 0);
  7925. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7926. "qcom,pri-mi2s-gpios", 0);
  7927. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7928. "qcom,sec-mi2s-gpios", 0);
  7929. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7930. "qcom,tert-mi2s-gpios", 0);
  7931. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7932. "qcom,quat-mi2s-gpios", 0);
  7933. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7934. "qcom,quin-mi2s-gpios", 0);
  7935. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  7936. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  7937. micb_supply_str1);
  7938. if (IS_ERR(pdata->tdm_micb_supply)) {
  7939. ret = PTR_ERR(pdata->tdm_micb_supply);
  7940. dev_err(&pdev->dev,
  7941. "%s:Failed to get micbias supply for TDM Mic %d\n",
  7942. __func__, ret);
  7943. }
  7944. ret = of_property_read_u32(pdev->dev.of_node,
  7945. micb_voltage_str,
  7946. &pdata->tdm_micb_voltage);
  7947. if (ret) {
  7948. dev_err(&pdev->dev,
  7949. "%s:Looking up %s property in node %s failed\n",
  7950. __func__, micb_voltage_str,
  7951. pdev->dev.of_node->full_name);
  7952. }
  7953. ret = of_property_read_u32(pdev->dev.of_node,
  7954. micb_current_str,
  7955. &pdata->tdm_micb_current);
  7956. if (ret) {
  7957. dev_err(&pdev->dev,
  7958. "%s:Looking up %s property in node %s failed\n",
  7959. __func__, micb_current_str,
  7960. pdev->dev.of_node->full_name);
  7961. }
  7962. }
  7963. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7964. if (ret == -EPROBE_DEFER) {
  7965. if (codec_reg_done)
  7966. ret = -EINVAL;
  7967. goto err;
  7968. } else if (ret) {
  7969. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7970. ret);
  7971. goto err;
  7972. }
  7973. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7974. spdev = pdev;
  7975. ret = msm_mdf_mem_init();
  7976. if (ret)
  7977. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7978. ret);
  7979. msm_i2s_auxpcm_init(pdev);
  7980. is_initial_boot = true;
  7981. return 0;
  7982. err:
  7983. return ret;
  7984. }
  7985. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7986. {
  7987. audio_notifier_deregister("qcs405");
  7988. msm_i2s_auxpcm_deinit();
  7989. msm_mdf_mem_deinit();
  7990. return 0;
  7991. }
  7992. static struct platform_driver qcs405_asoc_machine_driver = {
  7993. .driver = {
  7994. .name = DRV_NAME,
  7995. .owner = THIS_MODULE,
  7996. .pm = &snd_soc_pm_ops,
  7997. .of_match_table = qcs405_asoc_machine_of_match,
  7998. },
  7999. .probe = msm_asoc_machine_probe,
  8000. .remove = msm_asoc_machine_remove,
  8001. };
  8002. module_platform_driver(qcs405_asoc_machine_driver);
  8003. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  8004. MODULE_LICENSE("GPL v2");
  8005. MODULE_ALIAS("platform:" DRV_NAME);
  8006. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);