cam_soc_util.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/of.h>
  6. #include <linux/clk.h>
  7. #include <linux/slab.h>
  8. #include <linux/gpio.h>
  9. #include <linux/of_gpio.h>
  10. #include "cam_soc_util.h"
  11. #include "cam_debug_util.h"
  12. #include "cam_cx_ipeak.h"
  13. #include "cam_mem_mgr.h"
  14. static char supported_clk_info[256];
  15. static char debugfs_dir_name[64];
  16. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  17. int64_t clk_rate, int clk_idx, int32_t *clk_lvl)
  18. {
  19. int i;
  20. long clk_rate_round;
  21. if (!soc_info || (clk_idx < 0) || (clk_idx >= CAM_SOC_MAX_CLK)) {
  22. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d", clk_idx);
  23. *clk_lvl = -1;
  24. return -EINVAL;
  25. }
  26. clk_rate_round = clk_round_rate(soc_info->clk[clk_idx], clk_rate);
  27. if (clk_rate_round < 0) {
  28. CAM_ERR(CAM_UTIL, "round failed rc = %ld",
  29. clk_rate_round);
  30. *clk_lvl = -1;
  31. return -EINVAL;
  32. }
  33. for (i = 0; i < CAM_MAX_VOTE; i++) {
  34. if ((soc_info->clk_level_valid[i]) &&
  35. (soc_info->clk_rate[i][clk_idx] >=
  36. clk_rate_round)) {
  37. CAM_DBG(CAM_UTIL,
  38. "soc = %d round rate = %ld actual = %lld",
  39. soc_info->clk_rate[i][clk_idx],
  40. clk_rate_round, clk_rate);
  41. *clk_lvl = i;
  42. return 0;
  43. }
  44. }
  45. CAM_WARN(CAM_UTIL, "Invalid clock rate %ld", clk_rate_round);
  46. *clk_lvl = -1;
  47. return -EINVAL;
  48. }
  49. /**
  50. * cam_soc_util_get_string_from_level()
  51. *
  52. * @brief: Returns the string for a given clk level
  53. *
  54. * @level: Clock level
  55. *
  56. * @return: String corresponding to the clk level
  57. */
  58. static const char *cam_soc_util_get_string_from_level(
  59. enum cam_vote_level level)
  60. {
  61. switch (level) {
  62. case CAM_SUSPEND_VOTE:
  63. return "";
  64. case CAM_MINSVS_VOTE:
  65. return "MINSVS[1]";
  66. case CAM_LOWSVS_VOTE:
  67. return "LOWSVS[2]";
  68. case CAM_SVS_VOTE:
  69. return "SVS[3]";
  70. case CAM_SVSL1_VOTE:
  71. return "SVSL1[4]";
  72. case CAM_NOMINAL_VOTE:
  73. return "NOM[5]";
  74. case CAM_NOMINALL1_VOTE:
  75. return "NOML1[6]";
  76. case CAM_TURBO_VOTE:
  77. return "TURBO[7]";
  78. default:
  79. return "";
  80. }
  81. }
  82. /**
  83. * cam_soc_util_get_supported_clk_levels()
  84. *
  85. * @brief: Returns the string of all the supported clk levels for
  86. * the given device
  87. *
  88. * @soc_info: Device soc information
  89. *
  90. * @return: String containing all supported clk levels
  91. */
  92. static const char *cam_soc_util_get_supported_clk_levels(
  93. struct cam_hw_soc_info *soc_info)
  94. {
  95. int i = 0;
  96. memset(supported_clk_info, 0, sizeof(supported_clk_info));
  97. strlcat(supported_clk_info, "Supported levels: ",
  98. sizeof(supported_clk_info));
  99. for (i = 0; i < CAM_MAX_VOTE; i++) {
  100. if (soc_info->clk_level_valid[i] == true) {
  101. strlcat(supported_clk_info,
  102. cam_soc_util_get_string_from_level(i),
  103. sizeof(supported_clk_info));
  104. strlcat(supported_clk_info, " ",
  105. sizeof(supported_clk_info));
  106. }
  107. }
  108. strlcat(supported_clk_info, "\n", sizeof(supported_clk_info));
  109. return supported_clk_info;
  110. }
  111. static int cam_soc_util_clk_lvl_options_open(struct inode *inode,
  112. struct file *file)
  113. {
  114. file->private_data = inode->i_private;
  115. return 0;
  116. }
  117. static ssize_t cam_soc_util_clk_lvl_options_read(struct file *file,
  118. char __user *clk_info, size_t size_t, loff_t *loff_t)
  119. {
  120. struct cam_hw_soc_info *soc_info =
  121. (struct cam_hw_soc_info *)file->private_data;
  122. const char *display_string =
  123. cam_soc_util_get_supported_clk_levels(soc_info);
  124. return simple_read_from_buffer(clk_info, size_t, loff_t, display_string,
  125. strlen(display_string));
  126. }
  127. static const struct file_operations cam_soc_util_clk_lvl_options = {
  128. .open = cam_soc_util_clk_lvl_options_open,
  129. .read = cam_soc_util_clk_lvl_options_read,
  130. };
  131. static int cam_soc_util_set_clk_lvl(void *data, u64 val)
  132. {
  133. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  134. if (val <= CAM_SUSPEND_VOTE || val >= CAM_MAX_VOTE)
  135. return 0;
  136. if (soc_info->clk_level_valid[val] == true)
  137. soc_info->clk_level_override = val;
  138. else
  139. soc_info->clk_level_override = 0;
  140. return 0;
  141. }
  142. static int cam_soc_util_get_clk_lvl(void *data, u64 *val)
  143. {
  144. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  145. *val = soc_info->clk_level_override;
  146. return 0;
  147. }
  148. DEFINE_SIMPLE_ATTRIBUTE(cam_soc_util_clk_lvl_control,
  149. cam_soc_util_get_clk_lvl, cam_soc_util_set_clk_lvl, "%08llu");
  150. /**
  151. * cam_soc_util_create_clk_lvl_debugfs()
  152. *
  153. * @brief: Creates debugfs files to view/control device clk rates
  154. *
  155. * @soc_info: Device soc information
  156. *
  157. * @return: Success or failure
  158. */
  159. static int cam_soc_util_create_clk_lvl_debugfs(
  160. struct cam_hw_soc_info *soc_info)
  161. {
  162. if (!soc_info) {
  163. CAM_ERR(CAM_UTIL, "soc info is NULL");
  164. return -EINVAL;
  165. }
  166. if (soc_info->dentry) {
  167. CAM_DBG(CAM_UTIL, "Debubfs entry for %s already exist",
  168. soc_info->dev_name);
  169. return 0;
  170. }
  171. memset(debugfs_dir_name, 0, sizeof(debugfs_dir_name));
  172. strlcat(debugfs_dir_name, "clk_dir_", sizeof(debugfs_dir_name));
  173. strlcat(debugfs_dir_name, soc_info->dev_name, sizeof(debugfs_dir_name));
  174. soc_info->dentry = debugfs_create_dir(debugfs_dir_name, NULL);
  175. if (IS_ERR_OR_NULL(soc_info->dentry)) {
  176. CAM_ERR(CAM_UTIL, "failed to create debug directory");
  177. return -ENOMEM;
  178. }
  179. if (!debugfs_create_file("clk_lvl_options", 0444,
  180. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_options)) {
  181. CAM_ERR(CAM_UTIL, "failed to create clk_lvl_options");
  182. goto err;
  183. }
  184. if (!debugfs_create_file("clk_lvl_control", 0644,
  185. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_control)) {
  186. CAM_ERR(CAM_UTIL, "failed to create clk_lvl_control");
  187. goto err;
  188. }
  189. CAM_DBG(CAM_UTIL, "clk lvl debugfs for %s successfully created",
  190. soc_info->dev_name);
  191. return 0;
  192. err:
  193. CAM_ERR(CAM_UTIL, "Error in creating Debugfs Entry: %s",
  194. soc_info->dev_name);
  195. debugfs_remove_recursive(soc_info->dentry);
  196. soc_info->dentry = NULL;
  197. return -ENOMEM;
  198. }
  199. /**
  200. * cam_soc_util_remove_clk_lvl_debugfs()
  201. *
  202. * @brief: Removes the debugfs files used to view/control
  203. * device clk rates
  204. *
  205. * @soc_info: Device soc information
  206. *
  207. */
  208. static void cam_soc_util_remove_clk_lvl_debugfs(
  209. struct cam_hw_soc_info *soc_info)
  210. {
  211. debugfs_remove_recursive(soc_info->dentry);
  212. soc_info->dentry = NULL;
  213. }
  214. int cam_soc_util_get_level_from_string(const char *string,
  215. enum cam_vote_level *level)
  216. {
  217. if (!level)
  218. return -EINVAL;
  219. if (!strcmp(string, "suspend")) {
  220. *level = CAM_SUSPEND_VOTE;
  221. } else if (!strcmp(string, "minsvs")) {
  222. *level = CAM_MINSVS_VOTE;
  223. } else if (!strcmp(string, "lowsvs")) {
  224. *level = CAM_LOWSVS_VOTE;
  225. } else if (!strcmp(string, "svs")) {
  226. *level = CAM_SVS_VOTE;
  227. } else if (!strcmp(string, "svs_l1")) {
  228. *level = CAM_SVSL1_VOTE;
  229. } else if (!strcmp(string, "nominal")) {
  230. *level = CAM_NOMINAL_VOTE;
  231. } else if (!strcmp(string, "nominal_l1")) {
  232. *level = CAM_NOMINALL1_VOTE;
  233. } else if (!strcmp(string, "turbo")) {
  234. *level = CAM_TURBO_VOTE;
  235. } else {
  236. CAM_ERR(CAM_UTIL, "Invalid string %s", string);
  237. return -EINVAL;
  238. }
  239. return 0;
  240. }
  241. /**
  242. * cam_soc_util_get_clk_level_to_apply()
  243. *
  244. * @brief: Get the clock level to apply. If the requested level
  245. * is not valid, bump the level to next available valid
  246. * level. If no higher level found, return failure.
  247. *
  248. * @soc_info: Device soc struct to be populated
  249. * @req_level: Requested level
  250. * @apply_level Level to apply
  251. *
  252. * @return: success or failure
  253. */
  254. static int cam_soc_util_get_clk_level_to_apply(
  255. struct cam_hw_soc_info *soc_info, enum cam_vote_level req_level,
  256. enum cam_vote_level *apply_level)
  257. {
  258. if (req_level >= CAM_MAX_VOTE) {
  259. CAM_ERR(CAM_UTIL, "Invalid clock level parameter %d",
  260. req_level);
  261. return -EINVAL;
  262. }
  263. if (soc_info->clk_level_valid[req_level] == true) {
  264. *apply_level = req_level;
  265. } else {
  266. int i;
  267. for (i = (req_level + 1); i < CAM_MAX_VOTE; i++)
  268. if (soc_info->clk_level_valid[i] == true) {
  269. *apply_level = i;
  270. break;
  271. }
  272. if (i == CAM_MAX_VOTE) {
  273. CAM_ERR(CAM_UTIL,
  274. "No valid clock level found to apply, req=%d",
  275. req_level);
  276. return -EINVAL;
  277. }
  278. }
  279. CAM_DBG(CAM_UTIL, "Req level %d, Applying %d",
  280. req_level, *apply_level);
  281. return 0;
  282. }
  283. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info)
  284. {
  285. if (!soc_info) {
  286. CAM_ERR(CAM_UTIL, "Invalid arguments");
  287. return -EINVAL;
  288. }
  289. if (!soc_info->irq_line) {
  290. CAM_ERR(CAM_UTIL, "No IRQ line available");
  291. return -ENODEV;
  292. }
  293. enable_irq(soc_info->irq_line->start);
  294. return 0;
  295. }
  296. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info)
  297. {
  298. if (!soc_info) {
  299. CAM_ERR(CAM_UTIL, "Invalid arguments");
  300. return -EINVAL;
  301. }
  302. if (!soc_info->irq_line) {
  303. CAM_ERR(CAM_UTIL, "No IRQ line available");
  304. return -ENODEV;
  305. }
  306. disable_irq(soc_info->irq_line->start);
  307. return 0;
  308. }
  309. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  310. uint32_t clk_index, unsigned long clk_rate)
  311. {
  312. if (!soc_info || (clk_index >= soc_info->num_clk) || (clk_rate == 0)) {
  313. CAM_ERR(CAM_UTIL, "Invalid input params %pK, %d %lu",
  314. soc_info, clk_index, clk_rate);
  315. return clk_rate;
  316. }
  317. return clk_round_rate(soc_info->clk[clk_index], clk_rate);
  318. }
  319. /**
  320. * cam_soc_util_set_clk_rate()
  321. *
  322. * @brief: Sets the given rate for the clk requested for
  323. *
  324. * @clk: Clock structure information for which rate is to be set
  325. * @clk_name: Name of the clock for which rate is being set
  326. * @clk_rate Clock rate to be set
  327. *
  328. * @return: Success or failure
  329. */
  330. static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name,
  331. int64_t clk_rate)
  332. {
  333. int rc = 0;
  334. long clk_rate_round;
  335. if (!clk || !clk_name)
  336. return -EINVAL;
  337. CAM_DBG(CAM_UTIL, "set %s, rate %lld", clk_name, clk_rate);
  338. if (clk_rate > 0) {
  339. clk_rate_round = clk_round_rate(clk, clk_rate);
  340. CAM_DBG(CAM_UTIL, "new_rate %ld", clk_rate_round);
  341. if (clk_rate_round < 0) {
  342. CAM_ERR(CAM_UTIL, "round failed for clock %s rc = %ld",
  343. clk_name, clk_rate_round);
  344. return clk_rate_round;
  345. }
  346. rc = clk_set_rate(clk, clk_rate_round);
  347. if (rc) {
  348. CAM_ERR(CAM_UTIL, "set_rate failed on %s", clk_name);
  349. return rc;
  350. }
  351. } else if (clk_rate == INIT_RATE) {
  352. clk_rate_round = clk_get_rate(clk);
  353. CAM_DBG(CAM_UTIL, "init new_rate %ld", clk_rate_round);
  354. if (clk_rate_round == 0) {
  355. clk_rate_round = clk_round_rate(clk, 0);
  356. if (clk_rate_round <= 0) {
  357. CAM_ERR(CAM_UTIL, "round rate failed on %s",
  358. clk_name);
  359. return clk_rate_round;
  360. }
  361. }
  362. rc = clk_set_rate(clk, clk_rate_round);
  363. if (rc) {
  364. CAM_ERR(CAM_UTIL, "set_rate failed on %s", clk_name);
  365. return rc;
  366. }
  367. }
  368. return rc;
  369. }
  370. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
  371. int64_t clk_rate)
  372. {
  373. int rc = 0;
  374. int i = 0;
  375. int32_t src_clk_idx;
  376. int32_t scl_clk_idx;
  377. struct clk *clk = NULL;
  378. int32_t apply_level;
  379. uint32_t clk_level_override = 0;
  380. if (!soc_info || (soc_info->src_clk_idx < 0) ||
  381. (soc_info->src_clk_idx >= CAM_SOC_MAX_CLK)) {
  382. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d",
  383. soc_info ? soc_info->src_clk_idx : -1);
  384. return -EINVAL;
  385. }
  386. src_clk_idx = soc_info->src_clk_idx;
  387. clk_level_override = soc_info->clk_level_override;
  388. if (clk_level_override && clk_rate)
  389. clk_rate =
  390. soc_info->clk_rate[clk_level_override][src_clk_idx];
  391. clk = soc_info->clk[src_clk_idx];
  392. rc = cam_soc_util_get_clk_level(soc_info, clk_rate, src_clk_idx,
  393. &apply_level);
  394. if (rc || (apply_level < 0) || (apply_level >= CAM_MAX_VOTE)) {
  395. CAM_ERR(CAM_UTIL,
  396. "set %s, rate %lld dev_name = %s apply level = %d",
  397. soc_info->clk_name[src_clk_idx], clk_rate,
  398. soc_info->dev_name, apply_level);
  399. return -EINVAL;
  400. }
  401. CAM_DBG(CAM_UTIL, "set %s, rate %lld dev_name = %s apply level = %d",
  402. soc_info->clk_name[src_clk_idx], clk_rate,
  403. soc_info->dev_name, apply_level);
  404. if ((soc_info->cam_cx_ipeak_enable) && (clk_rate >= 0)) {
  405. cam_cx_ipeak_update_vote_cx_ipeak(soc_info,
  406. apply_level);
  407. }
  408. rc = cam_soc_util_set_clk_rate(clk,
  409. soc_info->clk_name[src_clk_idx], clk_rate);
  410. if (rc) {
  411. CAM_ERR(CAM_UTIL,
  412. "SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
  413. soc_info->clk_name[src_clk_idx], clk_rate,
  414. soc_info->dev_name, rc);
  415. return rc;
  416. }
  417. /* set clk rate for scalable clk if available */
  418. for (i = 0; i < soc_info->scl_clk_count; i++) {
  419. scl_clk_idx = soc_info->scl_clk_idx[i];
  420. if (scl_clk_idx < 0) {
  421. CAM_DBG(CAM_UTIL, "Scl clk index invalid");
  422. continue;
  423. }
  424. clk = soc_info->clk[scl_clk_idx];
  425. rc = cam_soc_util_set_clk_rate(clk,
  426. soc_info->clk_name[scl_clk_idx],
  427. soc_info->clk_rate[apply_level][scl_clk_idx]);
  428. if (rc) {
  429. CAM_WARN(CAM_UTIL,
  430. "SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
  431. soc_info->clk_name[scl_clk_idx],
  432. soc_info->clk_rate[apply_level][scl_clk_idx],
  433. soc_info->dev_name, rc);
  434. }
  435. }
  436. return 0;
  437. }
  438. int cam_soc_util_clk_put(struct clk **clk)
  439. {
  440. if (!(*clk)) {
  441. CAM_ERR(CAM_UTIL, "Invalid params clk");
  442. return -EINVAL;
  443. }
  444. clk_put(*clk);
  445. *clk = NULL;
  446. return 0;
  447. }
  448. static struct clk *cam_soc_util_option_clk_get(struct device_node *np,
  449. int index)
  450. {
  451. struct of_phandle_args clkspec;
  452. struct clk *clk;
  453. int rc;
  454. if (index < 0)
  455. return ERR_PTR(-EINVAL);
  456. rc = of_parse_phandle_with_args(np, "clocks-option", "#clock-cells",
  457. index, &clkspec);
  458. if (rc)
  459. return ERR_PTR(rc);
  460. clk = of_clk_get_from_provider(&clkspec);
  461. of_node_put(clkspec.np);
  462. return clk;
  463. }
  464. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  465. const char *clk_name, struct clk **clk, int32_t *clk_index,
  466. int32_t *clk_rate)
  467. {
  468. int index = 0;
  469. int rc = 0;
  470. struct device_node *of_node = NULL;
  471. if (!soc_info || !clk_name || !clk) {
  472. CAM_ERR(CAM_UTIL,
  473. "Invalid params soc_info %pK clk_name %s clk %pK",
  474. soc_info, clk_name, clk);
  475. return -EINVAL;
  476. }
  477. of_node = soc_info->dev->of_node;
  478. index = of_property_match_string(of_node, "clock-names-option",
  479. clk_name);
  480. if (index < 0) {
  481. CAM_DBG(CAM_UTIL, "No clk data for %s", clk_name);
  482. *clk_index = -1;
  483. *clk = ERR_PTR(-EINVAL);
  484. return -EINVAL;
  485. }
  486. *clk = cam_soc_util_option_clk_get(of_node, index);
  487. if (IS_ERR(*clk)) {
  488. CAM_ERR(CAM_UTIL, "No clk named %s found. Dev %s", clk_name,
  489. soc_info->dev_name);
  490. *clk_index = -1;
  491. return -EFAULT;
  492. }
  493. *clk_index = index;
  494. rc = of_property_read_u32_index(of_node, "clock-rates-option",
  495. index, clk_rate);
  496. if (rc) {
  497. CAM_ERR(CAM_UTIL,
  498. "Error reading clock-rates clk_name %s index %d",
  499. clk_name, index);
  500. cam_soc_util_clk_put(clk);
  501. *clk_rate = 0;
  502. return rc;
  503. }
  504. /*
  505. * Option clocks are assumed to be available to single Device here.
  506. * Hence use INIT_RATE instead of NO_SET_RATE.
  507. */
  508. *clk_rate = (*clk_rate == 0) ? (int32_t)INIT_RATE : *clk_rate;
  509. CAM_DBG(CAM_UTIL, "clk_name %s index %d clk_rate %d",
  510. clk_name, *clk_index, *clk_rate);
  511. return 0;
  512. }
  513. int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
  514. int32_t clk_rate)
  515. {
  516. int rc = 0;
  517. if (!clk || !clk_name)
  518. return -EINVAL;
  519. rc = cam_soc_util_set_clk_rate(clk, clk_name, clk_rate);
  520. if (rc)
  521. return rc;
  522. rc = clk_prepare_enable(clk);
  523. if (rc) {
  524. CAM_ERR(CAM_UTIL, "enable failed for %s: rc(%d)", clk_name, rc);
  525. return rc;
  526. }
  527. return rc;
  528. }
  529. int cam_soc_util_clk_disable(struct clk *clk, const char *clk_name)
  530. {
  531. if (!clk || !clk_name)
  532. return -EINVAL;
  533. CAM_DBG(CAM_UTIL, "disable %s", clk_name);
  534. clk_disable_unprepare(clk);
  535. return 0;
  536. }
  537. /**
  538. * cam_soc_util_clk_enable_default()
  539. *
  540. * @brief: This function enables the default clocks present
  541. * in soc_info
  542. *
  543. * @soc_info: Device soc struct to be populated
  544. * @clk_level: Clk level to apply while enabling
  545. *
  546. * @return: success or failure
  547. */
  548. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
  549. enum cam_vote_level clk_level)
  550. {
  551. int i, rc = 0;
  552. enum cam_vote_level apply_level;
  553. if ((soc_info->num_clk == 0) ||
  554. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  555. CAM_ERR(CAM_UTIL, "Invalid number of clock %d",
  556. soc_info->num_clk);
  557. return -EINVAL;
  558. }
  559. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level,
  560. &apply_level);
  561. if (rc)
  562. return rc;
  563. if (soc_info->cam_cx_ipeak_enable)
  564. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level);
  565. for (i = 0; i < soc_info->num_clk; i++) {
  566. rc = cam_soc_util_clk_enable(soc_info->clk[i],
  567. soc_info->clk_name[i],
  568. soc_info->clk_rate[apply_level][i]);
  569. if (rc)
  570. goto clk_disable;
  571. if (soc_info->cam_cx_ipeak_enable) {
  572. CAM_DBG(CAM_UTIL,
  573. "dev name = %s clk name = %s idx = %d\n"
  574. "apply_level = %d clc idx = %d",
  575. soc_info->dev_name, soc_info->clk_name[i], i,
  576. apply_level, i);
  577. }
  578. }
  579. return rc;
  580. clk_disable:
  581. if (soc_info->cam_cx_ipeak_enable)
  582. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  583. for (i--; i >= 0; i--) {
  584. cam_soc_util_clk_disable(soc_info->clk[i],
  585. soc_info->clk_name[i]);
  586. }
  587. return rc;
  588. }
  589. /**
  590. * cam_soc_util_clk_disable_default()
  591. *
  592. * @brief: This function disables the default clocks present
  593. * in soc_info
  594. *
  595. * @soc_info: device soc struct to be populated
  596. *
  597. * @return: success or failure
  598. */
  599. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info)
  600. {
  601. int i;
  602. if (soc_info->num_clk == 0)
  603. return;
  604. if (soc_info->cam_cx_ipeak_enable)
  605. cam_cx_ipeak_unvote_cx_ipeak(soc_info);
  606. for (i = soc_info->num_clk - 1; i >= 0; i--)
  607. cam_soc_util_clk_disable(soc_info->clk[i],
  608. soc_info->clk_name[i]);
  609. }
  610. /**
  611. * cam_soc_util_get_dt_clk_info()
  612. *
  613. * @brief: Parse the DT and populate the Clock properties
  614. *
  615. * @soc_info: device soc struct to be populated
  616. * @src_clk_str name of src clock that has rate control
  617. *
  618. * @return: success or failure
  619. */
  620. static int cam_soc_util_get_dt_clk_info(struct cam_hw_soc_info *soc_info)
  621. {
  622. struct device_node *of_node = NULL;
  623. int count;
  624. int num_clk_rates, num_clk_levels;
  625. int i, j, rc;
  626. int32_t num_clk_level_strings;
  627. const char *src_clk_str = NULL;
  628. const char *scl_clk_str = NULL;
  629. const char *clk_control_debugfs = NULL;
  630. const char *clk_cntl_lvl_string = NULL;
  631. enum cam_vote_level level;
  632. if (!soc_info || !soc_info->dev)
  633. return -EINVAL;
  634. of_node = soc_info->dev->of_node;
  635. if (!of_property_read_bool(of_node, "use-shared-clk")) {
  636. CAM_DBG(CAM_UTIL, "No shared clk parameter defined");
  637. soc_info->use_shared_clk = false;
  638. } else {
  639. soc_info->use_shared_clk = true;
  640. }
  641. count = of_property_count_strings(of_node, "clock-names");
  642. CAM_DBG(CAM_UTIL, "E: dev_name = %s count = %d",
  643. soc_info->dev_name, count);
  644. if (count > CAM_SOC_MAX_CLK) {
  645. CAM_ERR(CAM_UTIL, "invalid count of clocks, count=%d", count);
  646. rc = -EINVAL;
  647. return rc;
  648. }
  649. if (count <= 0) {
  650. CAM_DBG(CAM_UTIL, "No clock-names found");
  651. count = 0;
  652. soc_info->num_clk = count;
  653. return 0;
  654. }
  655. soc_info->num_clk = count;
  656. for (i = 0; i < count; i++) {
  657. rc = of_property_read_string_index(of_node, "clock-names",
  658. i, &(soc_info->clk_name[i]));
  659. CAM_DBG(CAM_UTIL, "clock-names[%d] = %s",
  660. i, soc_info->clk_name[i]);
  661. if (rc) {
  662. CAM_ERR(CAM_UTIL,
  663. "i= %d count= %d reading clock-names failed",
  664. i, count);
  665. return rc;
  666. }
  667. }
  668. num_clk_rates = of_property_count_u32_elems(of_node, "clock-rates");
  669. if (num_clk_rates <= 0) {
  670. CAM_ERR(CAM_UTIL, "reading clock-rates count failed");
  671. return -EINVAL;
  672. }
  673. if ((num_clk_rates % soc_info->num_clk) != 0) {
  674. CAM_ERR(CAM_UTIL,
  675. "mismatch clk/rates, No of clocks=%d, No of rates=%d",
  676. soc_info->num_clk, num_clk_rates);
  677. return -EINVAL;
  678. }
  679. num_clk_levels = (num_clk_rates / soc_info->num_clk);
  680. num_clk_level_strings = of_property_count_strings(of_node,
  681. "clock-cntl-level");
  682. if (num_clk_level_strings != num_clk_levels) {
  683. CAM_ERR(CAM_UTIL,
  684. "Mismatch No of levels=%d, No of level string=%d",
  685. num_clk_levels, num_clk_level_strings);
  686. return -EINVAL;
  687. }
  688. for (i = 0; i < num_clk_levels; i++) {
  689. rc = of_property_read_string_index(of_node,
  690. "clock-cntl-level", i, &clk_cntl_lvl_string);
  691. if (rc) {
  692. CAM_ERR(CAM_UTIL,
  693. "Error reading clock-cntl-level, rc=%d", rc);
  694. return rc;
  695. }
  696. rc = cam_soc_util_get_level_from_string(clk_cntl_lvl_string,
  697. &level);
  698. if (rc)
  699. return rc;
  700. CAM_DBG(CAM_UTIL,
  701. "[%d] : %s %d", i, clk_cntl_lvl_string, level);
  702. soc_info->clk_level_valid[level] = true;
  703. for (j = 0; j < soc_info->num_clk; j++) {
  704. rc = of_property_read_u32_index(of_node, "clock-rates",
  705. ((i * soc_info->num_clk) + j),
  706. &soc_info->clk_rate[level][j]);
  707. if (rc) {
  708. CAM_ERR(CAM_UTIL,
  709. "Error reading clock-rates, rc=%d",
  710. rc);
  711. return rc;
  712. }
  713. soc_info->clk_rate[level][j] =
  714. (soc_info->clk_rate[level][j] == 0) ?
  715. (int32_t)NO_SET_RATE :
  716. soc_info->clk_rate[level][j];
  717. CAM_DBG(CAM_UTIL, "soc_info->clk_rate[%d][%d] = %d",
  718. level, j,
  719. soc_info->clk_rate[level][j]);
  720. }
  721. }
  722. soc_info->src_clk_idx = -1;
  723. rc = of_property_read_string_index(of_node, "src-clock-name", 0,
  724. &src_clk_str);
  725. if (rc || !src_clk_str) {
  726. CAM_DBG(CAM_UTIL, "No src_clk_str found");
  727. rc = 0;
  728. goto end;
  729. }
  730. for (i = 0; i < soc_info->num_clk; i++) {
  731. if (strcmp(soc_info->clk_name[i], src_clk_str) == 0) {
  732. soc_info->src_clk_idx = i;
  733. CAM_DBG(CAM_UTIL, "src clock = %s, index = %d",
  734. src_clk_str, i);
  735. break;
  736. }
  737. }
  738. /* scalable clk info parsing */
  739. soc_info->scl_clk_count = 0;
  740. soc_info->scl_clk_count = of_property_count_strings(of_node,
  741. "scl-clk-names");
  742. if ((soc_info->scl_clk_count <= 0) ||
  743. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  744. if (soc_info->scl_clk_count == -EINVAL) {
  745. CAM_DBG(CAM_UTIL, "scl_clk_name prop not avialable");
  746. } else if ((soc_info->scl_clk_count == -ENODATA) ||
  747. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  748. CAM_ERR(CAM_UTIL, "Invalid scl_clk_count: %d",
  749. soc_info->scl_clk_count);
  750. return -EINVAL;
  751. }
  752. CAM_DBG(CAM_UTIL, "Invalid scl_clk count: %d",
  753. soc_info->scl_clk_count);
  754. soc_info->scl_clk_count = -1;
  755. } else {
  756. CAM_DBG(CAM_UTIL, "No of scalable clocks: %d",
  757. soc_info->scl_clk_count);
  758. for (i = 0; i < soc_info->scl_clk_count; i++) {
  759. rc = of_property_read_string_index(of_node,
  760. "scl-clk-names", i,
  761. (const char **)&scl_clk_str);
  762. if (rc || !scl_clk_str) {
  763. CAM_WARN(CAM_UTIL, "scl_clk_str is NULL");
  764. soc_info->scl_clk_idx[i] = -1;
  765. continue;
  766. }
  767. for (j = 0; j < soc_info->num_clk; j++) {
  768. if (strnstr(scl_clk_str, soc_info->clk_name[j],
  769. strlen(scl_clk_str))) {
  770. soc_info->scl_clk_idx[i] = j;
  771. CAM_DBG(CAM_UTIL,
  772. "scl clock = %s, index = %d",
  773. scl_clk_str, j);
  774. break;
  775. }
  776. }
  777. }
  778. }
  779. rc = of_property_read_string_index(of_node,
  780. "clock-control-debugfs", 0, &clk_control_debugfs);
  781. if (rc || !clk_control_debugfs) {
  782. CAM_DBG(CAM_UTIL, "No clock_control_debugfs property found");
  783. rc = 0;
  784. goto end;
  785. }
  786. if (strcmp("true", clk_control_debugfs) == 0)
  787. soc_info->clk_control_enable = true;
  788. CAM_DBG(CAM_UTIL, "X: dev_name = %s count = %d",
  789. soc_info->dev_name, count);
  790. end:
  791. return rc;
  792. }
  793. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  794. enum cam_vote_level clk_level)
  795. {
  796. int i, rc = 0;
  797. enum cam_vote_level apply_level;
  798. if ((soc_info->num_clk == 0) ||
  799. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  800. CAM_ERR(CAM_UTIL, "Invalid number of clock %d",
  801. soc_info->num_clk);
  802. return -EINVAL;
  803. }
  804. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level,
  805. &apply_level);
  806. if (rc)
  807. return rc;
  808. if (soc_info->cam_cx_ipeak_enable)
  809. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level);
  810. for (i = 0; i < soc_info->num_clk; i++) {
  811. rc = cam_soc_util_set_clk_rate(soc_info->clk[i],
  812. soc_info->clk_name[i],
  813. soc_info->clk_rate[apply_level][i]);
  814. if (rc < 0) {
  815. CAM_DBG(CAM_UTIL,
  816. "dev name = %s clk_name = %s idx = %d\n"
  817. "apply_level = %d",
  818. soc_info->dev_name, soc_info->clk_name[i],
  819. i, apply_level);
  820. if (soc_info->cam_cx_ipeak_enable)
  821. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  822. break;
  823. }
  824. }
  825. return rc;
  826. };
  827. static int cam_soc_util_get_dt_gpio_req_tbl(struct device_node *of_node,
  828. struct cam_soc_gpio_data *gconf, uint16_t *gpio_array,
  829. uint16_t gpio_array_size)
  830. {
  831. int32_t rc = 0, i = 0;
  832. uint32_t count = 0;
  833. uint32_t *val_array = NULL;
  834. if (!of_get_property(of_node, "gpio-req-tbl-num", &count))
  835. return 0;
  836. count /= sizeof(uint32_t);
  837. if (!count) {
  838. CAM_ERR(CAM_UTIL, "gpio-req-tbl-num 0");
  839. return 0;
  840. }
  841. val_array = kcalloc(count, sizeof(uint32_t), GFP_KERNEL);
  842. if (!val_array)
  843. return -ENOMEM;
  844. gconf->cam_gpio_req_tbl = kcalloc(count, sizeof(struct gpio),
  845. GFP_KERNEL);
  846. if (!gconf->cam_gpio_req_tbl) {
  847. rc = -ENOMEM;
  848. goto free_val_array;
  849. }
  850. gconf->cam_gpio_req_tbl_size = count;
  851. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-num",
  852. val_array, count);
  853. if (rc) {
  854. CAM_ERR(CAM_UTIL, "failed in reading gpio-req-tbl-num, rc = %d",
  855. rc);
  856. goto free_gpio_req_tbl;
  857. }
  858. for (i = 0; i < count; i++) {
  859. if (val_array[i] >= gpio_array_size) {
  860. CAM_ERR(CAM_UTIL, "gpio req tbl index %d invalid",
  861. val_array[i]);
  862. goto free_gpio_req_tbl;
  863. }
  864. gconf->cam_gpio_req_tbl[i].gpio = gpio_array[val_array[i]];
  865. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].gpio = %d", i,
  866. gconf->cam_gpio_req_tbl[i].gpio);
  867. }
  868. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-flags",
  869. val_array, count);
  870. if (rc) {
  871. CAM_ERR(CAM_UTIL, "Failed in gpio-req-tbl-flags, rc %d", rc);
  872. goto free_gpio_req_tbl;
  873. }
  874. for (i = 0; i < count; i++) {
  875. gconf->cam_gpio_req_tbl[i].flags = val_array[i];
  876. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].flags = %ld", i,
  877. gconf->cam_gpio_req_tbl[i].flags);
  878. }
  879. for (i = 0; i < count; i++) {
  880. rc = of_property_read_string_index(of_node,
  881. "gpio-req-tbl-label", i,
  882. &gconf->cam_gpio_req_tbl[i].label);
  883. if (rc) {
  884. CAM_ERR(CAM_UTIL, "Failed rc %d", rc);
  885. goto free_gpio_req_tbl;
  886. }
  887. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].label = %s", i,
  888. gconf->cam_gpio_req_tbl[i].label);
  889. }
  890. kfree(val_array);
  891. return rc;
  892. free_gpio_req_tbl:
  893. kfree(gconf->cam_gpio_req_tbl);
  894. free_val_array:
  895. kfree(val_array);
  896. gconf->cam_gpio_req_tbl_size = 0;
  897. return rc;
  898. }
  899. static int cam_soc_util_get_gpio_info(struct cam_hw_soc_info *soc_info)
  900. {
  901. int32_t rc = 0, i = 0;
  902. uint16_t *gpio_array = NULL;
  903. int16_t gpio_array_size = 0;
  904. struct cam_soc_gpio_data *gconf = NULL;
  905. struct device_node *of_node = NULL;
  906. if (!soc_info || !soc_info->dev)
  907. return -EINVAL;
  908. of_node = soc_info->dev->of_node;
  909. /* Validate input parameters */
  910. if (!of_node) {
  911. CAM_ERR(CAM_UTIL, "Invalid param of_node");
  912. return -EINVAL;
  913. }
  914. gpio_array_size = of_gpio_count(of_node);
  915. if (gpio_array_size <= 0)
  916. return 0;
  917. CAM_DBG(CAM_UTIL, "gpio count %d", gpio_array_size);
  918. gpio_array = kcalloc(gpio_array_size, sizeof(uint16_t), GFP_KERNEL);
  919. if (!gpio_array)
  920. goto free_gpio_conf;
  921. for (i = 0; i < gpio_array_size; i++) {
  922. gpio_array[i] = of_get_gpio(of_node, i);
  923. CAM_DBG(CAM_UTIL, "gpio_array[%d] = %d", i, gpio_array[i]);
  924. }
  925. gconf = kzalloc(sizeof(*gconf), GFP_KERNEL);
  926. if (!gconf)
  927. return -ENOMEM;
  928. rc = cam_soc_util_get_dt_gpio_req_tbl(of_node, gconf, gpio_array,
  929. gpio_array_size);
  930. if (rc) {
  931. CAM_ERR(CAM_UTIL, "failed in msm_camera_get_dt_gpio_req_tbl");
  932. goto free_gpio_array;
  933. }
  934. gconf->cam_gpio_common_tbl = kcalloc(gpio_array_size,
  935. sizeof(struct gpio), GFP_KERNEL);
  936. if (!gconf->cam_gpio_common_tbl) {
  937. rc = -ENOMEM;
  938. goto free_gpio_array;
  939. }
  940. for (i = 0; i < gpio_array_size; i++)
  941. gconf->cam_gpio_common_tbl[i].gpio = gpio_array[i];
  942. gconf->cam_gpio_common_tbl_size = gpio_array_size;
  943. soc_info->gpio_data = gconf;
  944. kfree(gpio_array);
  945. return rc;
  946. free_gpio_array:
  947. kfree(gpio_array);
  948. free_gpio_conf:
  949. kfree(gconf);
  950. soc_info->gpio_data = NULL;
  951. return rc;
  952. }
  953. static int cam_soc_util_request_gpio_table(
  954. struct cam_hw_soc_info *soc_info, bool gpio_en)
  955. {
  956. int rc = 0, i = 0;
  957. uint8_t size = 0;
  958. struct cam_soc_gpio_data *gpio_conf =
  959. soc_info->gpio_data;
  960. struct gpio *gpio_tbl = NULL;
  961. if (!gpio_conf) {
  962. CAM_DBG(CAM_UTIL, "No GPIO entry");
  963. return 0;
  964. }
  965. if (gpio_conf->cam_gpio_common_tbl_size <= 0) {
  966. CAM_ERR(CAM_UTIL, "GPIO table size is invalid");
  967. return -EINVAL;
  968. }
  969. size = gpio_conf->cam_gpio_req_tbl_size;
  970. gpio_tbl = gpio_conf->cam_gpio_req_tbl;
  971. if (!gpio_tbl || !size) {
  972. CAM_ERR(CAM_UTIL, "Invalid gpio_tbl %pK / size %d",
  973. gpio_tbl, size);
  974. return -EINVAL;
  975. }
  976. for (i = 0; i < size; i++) {
  977. CAM_DBG(CAM_UTIL, "i=%d, gpio=%d dir=%ld", i,
  978. gpio_tbl[i].gpio, gpio_tbl[i].flags);
  979. }
  980. if (gpio_en) {
  981. for (i = 0; i < size; i++) {
  982. rc = gpio_request_one(gpio_tbl[i].gpio,
  983. gpio_tbl[i].flags, gpio_tbl[i].label);
  984. if (rc) {
  985. /*
  986. * After GPIO request fails, contine to
  987. * apply new gpios, outout a error message
  988. * for driver bringup debug
  989. */
  990. CAM_ERR(CAM_UTIL, "gpio %d:%s request fails",
  991. gpio_tbl[i].gpio, gpio_tbl[i].label);
  992. }
  993. }
  994. } else {
  995. gpio_free_array(gpio_tbl, size);
  996. }
  997. return rc;
  998. }
  999. static int cam_soc_util_get_dt_regulator_info
  1000. (struct cam_hw_soc_info *soc_info)
  1001. {
  1002. int rc = 0, count = 0, i = 0;
  1003. struct device_node *of_node = NULL;
  1004. if (!soc_info || !soc_info->dev) {
  1005. CAM_ERR(CAM_UTIL, "Invalid parameters");
  1006. return -EINVAL;
  1007. }
  1008. of_node = soc_info->dev->of_node;
  1009. soc_info->num_rgltr = 0;
  1010. count = of_property_count_strings(of_node, "regulator-names");
  1011. if (count != -EINVAL) {
  1012. if (count <= 0) {
  1013. CAM_ERR(CAM_UTIL, "no regulators found");
  1014. count = 0;
  1015. return -EINVAL;
  1016. }
  1017. soc_info->num_rgltr = count;
  1018. } else {
  1019. CAM_DBG(CAM_UTIL, "No regulators node found");
  1020. return 0;
  1021. }
  1022. for (i = 0; i < soc_info->num_rgltr; i++) {
  1023. rc = of_property_read_string_index(of_node,
  1024. "regulator-names", i, &soc_info->rgltr_name[i]);
  1025. CAM_DBG(CAM_UTIL, "rgltr_name[%d] = %s",
  1026. i, soc_info->rgltr_name[i]);
  1027. if (rc) {
  1028. CAM_ERR(CAM_UTIL, "no regulator resource at cnt=%d", i);
  1029. return -ENODEV;
  1030. }
  1031. }
  1032. if (!of_property_read_bool(of_node, "rgltr-cntrl-support")) {
  1033. CAM_DBG(CAM_UTIL, "No regulator control parameter defined");
  1034. soc_info->rgltr_ctrl_support = false;
  1035. return 0;
  1036. }
  1037. soc_info->rgltr_ctrl_support = true;
  1038. rc = of_property_read_u32_array(of_node, "rgltr-min-voltage",
  1039. soc_info->rgltr_min_volt, soc_info->num_rgltr);
  1040. if (rc) {
  1041. CAM_ERR(CAM_UTIL, "No minimum volatage value found, rc=%d", rc);
  1042. return -EINVAL;
  1043. }
  1044. rc = of_property_read_u32_array(of_node, "rgltr-max-voltage",
  1045. soc_info->rgltr_max_volt, soc_info->num_rgltr);
  1046. if (rc) {
  1047. CAM_ERR(CAM_UTIL, "No maximum volatage value found, rc=%d", rc);
  1048. return -EINVAL;
  1049. }
  1050. rc = of_property_read_u32_array(of_node, "rgltr-load-current",
  1051. soc_info->rgltr_op_mode, soc_info->num_rgltr);
  1052. if (rc) {
  1053. CAM_ERR(CAM_UTIL, "No Load curent found rc=%d", rc);
  1054. return -EINVAL;
  1055. }
  1056. return rc;
  1057. }
  1058. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info)
  1059. {
  1060. struct device_node *of_node = NULL;
  1061. int count = 0, i = 0, rc = 0;
  1062. if (!soc_info || !soc_info->dev)
  1063. return -EINVAL;
  1064. of_node = soc_info->dev->of_node;
  1065. rc = of_property_read_u32(of_node, "cell-index", &soc_info->index);
  1066. if (rc) {
  1067. CAM_ERR(CAM_UTIL, "device %s failed to read cell-index",
  1068. soc_info->dev_name);
  1069. return rc;
  1070. }
  1071. count = of_property_count_strings(of_node, "reg-names");
  1072. if (count <= 0) {
  1073. CAM_DBG(CAM_UTIL, "no reg-names found for: %s",
  1074. soc_info->dev_name);
  1075. count = 0;
  1076. }
  1077. soc_info->num_mem_block = count;
  1078. for (i = 0; i < soc_info->num_mem_block; i++) {
  1079. rc = of_property_read_string_index(of_node, "reg-names", i,
  1080. &soc_info->mem_block_name[i]);
  1081. if (rc) {
  1082. CAM_ERR(CAM_UTIL, "failed to read reg-names at %d", i);
  1083. return rc;
  1084. }
  1085. soc_info->mem_block[i] =
  1086. platform_get_resource_byname(soc_info->pdev,
  1087. IORESOURCE_MEM, soc_info->mem_block_name[i]);
  1088. if (!soc_info->mem_block[i]) {
  1089. CAM_ERR(CAM_UTIL, "no mem resource by name %s",
  1090. soc_info->mem_block_name[i]);
  1091. rc = -ENODEV;
  1092. return rc;
  1093. }
  1094. }
  1095. rc = of_property_read_string(of_node, "label", &soc_info->label_name);
  1096. if (rc)
  1097. CAM_DBG(CAM_UTIL, "Label is not available in the node: %d", rc);
  1098. if (soc_info->num_mem_block > 0) {
  1099. rc = of_property_read_u32_array(of_node, "reg-cam-base",
  1100. soc_info->mem_block_cam_base, soc_info->num_mem_block);
  1101. if (rc) {
  1102. CAM_ERR(CAM_UTIL, "Error reading register offsets");
  1103. return rc;
  1104. }
  1105. }
  1106. rc = of_property_read_string_index(of_node, "interrupt-names", 0,
  1107. &soc_info->irq_name);
  1108. if (rc) {
  1109. CAM_DBG(CAM_UTIL, "No interrupt line preset for: %s",
  1110. soc_info->dev_name);
  1111. rc = 0;
  1112. } else {
  1113. soc_info->irq_line =
  1114. platform_get_resource_byname(soc_info->pdev,
  1115. IORESOURCE_IRQ, soc_info->irq_name);
  1116. if (!soc_info->irq_line) {
  1117. CAM_ERR(CAM_UTIL, "no irq resource");
  1118. rc = -ENODEV;
  1119. return rc;
  1120. }
  1121. }
  1122. rc = of_property_read_string_index(of_node, "compatible", 0,
  1123. (const char **)&soc_info->compatible);
  1124. if (rc) {
  1125. CAM_DBG(CAM_UTIL, "No compatible string present for: %s",
  1126. soc_info->dev_name);
  1127. rc = 0;
  1128. }
  1129. rc = cam_soc_util_get_dt_regulator_info(soc_info);
  1130. if (rc)
  1131. return rc;
  1132. rc = cam_soc_util_get_dt_clk_info(soc_info);
  1133. if (rc)
  1134. return rc;
  1135. rc = cam_soc_util_get_gpio_info(soc_info);
  1136. if (rc)
  1137. return rc;
  1138. if (of_find_property(of_node, "qcom,cam-cx-ipeak", NULL))
  1139. rc = cam_cx_ipeak_register_cx_ipeak(soc_info);
  1140. return rc;
  1141. }
  1142. /**
  1143. * cam_soc_util_get_regulator()
  1144. *
  1145. * @brief: Get regulator resource named vdd
  1146. *
  1147. * @dev: Device associated with regulator
  1148. * @reg: Return pointer to be filled with regulator on success
  1149. * @rgltr_name: Name of regulator to get
  1150. *
  1151. * @return: 0 for Success, negative value for failure
  1152. */
  1153. static int cam_soc_util_get_regulator(struct device *dev,
  1154. struct regulator **reg, const char *rgltr_name)
  1155. {
  1156. int rc = 0;
  1157. *reg = regulator_get(dev, rgltr_name);
  1158. if (IS_ERR_OR_NULL(*reg)) {
  1159. rc = PTR_ERR(*reg);
  1160. rc = rc ? rc : -EINVAL;
  1161. CAM_ERR(CAM_UTIL, "Regulator %s get failed %d", rgltr_name, rc);
  1162. *reg = NULL;
  1163. }
  1164. return rc;
  1165. }
  1166. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  1167. const char *rgltr_name, uint32_t rgltr_min_volt,
  1168. uint32_t rgltr_max_volt, uint32_t rgltr_op_mode,
  1169. uint32_t rgltr_delay_ms)
  1170. {
  1171. int32_t rc = 0;
  1172. if (!rgltr) {
  1173. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  1174. return -EINVAL;
  1175. }
  1176. rc = regulator_disable(rgltr);
  1177. if (rc) {
  1178. CAM_ERR(CAM_UTIL, "%s regulator disable failed", rgltr_name);
  1179. return rc;
  1180. }
  1181. if (rgltr_delay_ms > 20)
  1182. msleep(rgltr_delay_ms);
  1183. else if (rgltr_delay_ms)
  1184. usleep_range(rgltr_delay_ms * 1000,
  1185. (rgltr_delay_ms * 1000) + 1000);
  1186. if (regulator_count_voltages(rgltr) > 0) {
  1187. regulator_set_load(rgltr, 0);
  1188. regulator_set_voltage(rgltr, 0, rgltr_max_volt);
  1189. }
  1190. return rc;
  1191. }
  1192. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  1193. const char *rgltr_name,
  1194. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  1195. uint32_t rgltr_op_mode, uint32_t rgltr_delay)
  1196. {
  1197. int32_t rc = 0;
  1198. if (!rgltr) {
  1199. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  1200. return -EINVAL;
  1201. }
  1202. if (regulator_count_voltages(rgltr) > 0) {
  1203. CAM_DBG(CAM_UTIL, "voltage min=%d, max=%d",
  1204. rgltr_min_volt, rgltr_max_volt);
  1205. rc = regulator_set_voltage(
  1206. rgltr, rgltr_min_volt, rgltr_max_volt);
  1207. if (rc) {
  1208. CAM_ERR(CAM_UTIL, "%s set voltage failed", rgltr_name);
  1209. return rc;
  1210. }
  1211. rc = regulator_set_load(rgltr, rgltr_op_mode);
  1212. if (rc) {
  1213. CAM_ERR(CAM_UTIL, "%s set optimum mode failed",
  1214. rgltr_name);
  1215. return rc;
  1216. }
  1217. }
  1218. rc = regulator_enable(rgltr);
  1219. if (rc) {
  1220. CAM_ERR(CAM_UTIL, "%s regulator_enable failed", rgltr_name);
  1221. return rc;
  1222. }
  1223. if (rgltr_delay > 20)
  1224. msleep(rgltr_delay);
  1225. else if (rgltr_delay)
  1226. usleep_range(rgltr_delay * 1000,
  1227. (rgltr_delay * 1000) + 1000);
  1228. return rc;
  1229. }
  1230. static int cam_soc_util_request_pinctrl(
  1231. struct cam_hw_soc_info *soc_info)
  1232. {
  1233. struct cam_soc_pinctrl_info *device_pctrl = &soc_info->pinctrl_info;
  1234. struct device *dev = soc_info->dev;
  1235. device_pctrl->pinctrl = devm_pinctrl_get(dev);
  1236. if (IS_ERR_OR_NULL(device_pctrl->pinctrl)) {
  1237. CAM_DBG(CAM_UTIL, "Pinctrl not available");
  1238. device_pctrl->pinctrl = NULL;
  1239. return 0;
  1240. }
  1241. device_pctrl->gpio_state_active =
  1242. pinctrl_lookup_state(device_pctrl->pinctrl,
  1243. CAM_SOC_PINCTRL_STATE_DEFAULT);
  1244. if (IS_ERR_OR_NULL(device_pctrl->gpio_state_active)) {
  1245. CAM_ERR(CAM_UTIL,
  1246. "Failed to get the active state pinctrl handle");
  1247. device_pctrl->gpio_state_active = NULL;
  1248. return -EINVAL;
  1249. }
  1250. device_pctrl->gpio_state_suspend
  1251. = pinctrl_lookup_state(device_pctrl->pinctrl,
  1252. CAM_SOC_PINCTRL_STATE_SLEEP);
  1253. if (IS_ERR_OR_NULL(device_pctrl->gpio_state_suspend)) {
  1254. CAM_ERR(CAM_UTIL,
  1255. "Failed to get the suspend state pinctrl handle");
  1256. device_pctrl->gpio_state_suspend = NULL;
  1257. return -EINVAL;
  1258. }
  1259. return 0;
  1260. }
  1261. static void cam_soc_util_regulator_disable_default(
  1262. struct cam_hw_soc_info *soc_info)
  1263. {
  1264. int j = 0;
  1265. uint32_t num_rgltr = soc_info->num_rgltr;
  1266. for (j = num_rgltr-1; j >= 0; j--) {
  1267. if (soc_info->rgltr_ctrl_support == true) {
  1268. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  1269. soc_info->rgltr_name[j],
  1270. soc_info->rgltr_min_volt[j],
  1271. soc_info->rgltr_max_volt[j],
  1272. soc_info->rgltr_op_mode[j],
  1273. soc_info->rgltr_delay[j]);
  1274. } else {
  1275. if (soc_info->rgltr[j])
  1276. regulator_disable(soc_info->rgltr[j]);
  1277. }
  1278. }
  1279. }
  1280. static int cam_soc_util_regulator_enable_default(
  1281. struct cam_hw_soc_info *soc_info)
  1282. {
  1283. int j = 0, rc = 0;
  1284. uint32_t num_rgltr = soc_info->num_rgltr;
  1285. for (j = 0; j < num_rgltr; j++) {
  1286. if (soc_info->rgltr_ctrl_support == true) {
  1287. rc = cam_soc_util_regulator_enable(soc_info->rgltr[j],
  1288. soc_info->rgltr_name[j],
  1289. soc_info->rgltr_min_volt[j],
  1290. soc_info->rgltr_max_volt[j],
  1291. soc_info->rgltr_op_mode[j],
  1292. soc_info->rgltr_delay[j]);
  1293. } else {
  1294. if (soc_info->rgltr[j])
  1295. rc = regulator_enable(soc_info->rgltr[j]);
  1296. }
  1297. if (rc) {
  1298. CAM_ERR(CAM_UTIL, "%s enable failed",
  1299. soc_info->rgltr_name[j]);
  1300. goto disable_rgltr;
  1301. }
  1302. }
  1303. return rc;
  1304. disable_rgltr:
  1305. for (j--; j >= 0; j--) {
  1306. if (soc_info->rgltr_ctrl_support == true) {
  1307. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  1308. soc_info->rgltr_name[j],
  1309. soc_info->rgltr_min_volt[j],
  1310. soc_info->rgltr_max_volt[j],
  1311. soc_info->rgltr_op_mode[j],
  1312. soc_info->rgltr_delay[j]);
  1313. } else {
  1314. if (soc_info->rgltr[j])
  1315. regulator_disable(soc_info->rgltr[j]);
  1316. }
  1317. }
  1318. return rc;
  1319. }
  1320. int cam_soc_util_request_platform_resource(
  1321. struct cam_hw_soc_info *soc_info,
  1322. irq_handler_t handler, void *irq_data)
  1323. {
  1324. int i = 0, rc = 0;
  1325. if (!soc_info || !soc_info->dev) {
  1326. CAM_ERR(CAM_UTIL, "Invalid parameters");
  1327. return -EINVAL;
  1328. }
  1329. for (i = 0; i < soc_info->num_mem_block; i++) {
  1330. if (soc_info->reserve_mem) {
  1331. if (!request_mem_region(soc_info->mem_block[i]->start,
  1332. resource_size(soc_info->mem_block[i]),
  1333. soc_info->mem_block_name[i])){
  1334. CAM_ERR(CAM_UTIL,
  1335. "Error Mem region request Failed:%s",
  1336. soc_info->mem_block_name[i]);
  1337. rc = -ENOMEM;
  1338. goto unmap_base;
  1339. }
  1340. }
  1341. soc_info->reg_map[i].mem_base = ioremap(
  1342. soc_info->mem_block[i]->start,
  1343. resource_size(soc_info->mem_block[i]));
  1344. if (!soc_info->reg_map[i].mem_base) {
  1345. CAM_ERR(CAM_UTIL, "i= %d base NULL", i);
  1346. rc = -ENOMEM;
  1347. goto unmap_base;
  1348. }
  1349. soc_info->reg_map[i].mem_cam_base =
  1350. soc_info->mem_block_cam_base[i];
  1351. soc_info->reg_map[i].size =
  1352. resource_size(soc_info->mem_block[i]);
  1353. soc_info->num_reg_map++;
  1354. }
  1355. for (i = 0; i < soc_info->num_rgltr; i++) {
  1356. if (soc_info->rgltr_name[i] == NULL) {
  1357. CAM_ERR(CAM_UTIL, "can't find regulator name");
  1358. goto put_regulator;
  1359. }
  1360. rc = cam_soc_util_get_regulator(soc_info->dev,
  1361. &soc_info->rgltr[i],
  1362. soc_info->rgltr_name[i]);
  1363. if (rc)
  1364. goto put_regulator;
  1365. }
  1366. if (soc_info->irq_line) {
  1367. rc = devm_request_irq(soc_info->dev, soc_info->irq_line->start,
  1368. handler, IRQF_TRIGGER_RISING,
  1369. soc_info->irq_name, irq_data);
  1370. if (rc) {
  1371. CAM_ERR(CAM_UTIL, "irq request fail");
  1372. rc = -EBUSY;
  1373. goto put_regulator;
  1374. }
  1375. disable_irq(soc_info->irq_line->start);
  1376. soc_info->irq_data = irq_data;
  1377. }
  1378. /* Get Clock */
  1379. for (i = 0; i < soc_info->num_clk; i++) {
  1380. soc_info->clk[i] = clk_get(soc_info->dev,
  1381. soc_info->clk_name[i]);
  1382. if (!soc_info->clk[i]) {
  1383. CAM_ERR(CAM_UTIL, "get failed for %s",
  1384. soc_info->clk_name[i]);
  1385. rc = -ENOENT;
  1386. goto put_clk;
  1387. }
  1388. }
  1389. rc = cam_soc_util_request_pinctrl(soc_info);
  1390. if (rc)
  1391. CAM_DBG(CAM_UTIL, "Failed in request pinctrl, rc=%d", rc);
  1392. rc = cam_soc_util_request_gpio_table(soc_info, true);
  1393. if (rc) {
  1394. CAM_ERR(CAM_UTIL, "Failed in request gpio table, rc=%d", rc);
  1395. goto put_clk;
  1396. }
  1397. if (soc_info->clk_control_enable)
  1398. cam_soc_util_create_clk_lvl_debugfs(soc_info);
  1399. return rc;
  1400. put_clk:
  1401. if (i == -1)
  1402. i = soc_info->num_clk;
  1403. for (i = i - 1; i >= 0; i--) {
  1404. if (soc_info->clk[i]) {
  1405. clk_put(soc_info->clk[i]);
  1406. soc_info->clk[i] = NULL;
  1407. }
  1408. }
  1409. if (soc_info->irq_line) {
  1410. disable_irq(soc_info->irq_line->start);
  1411. devm_free_irq(soc_info->dev,
  1412. soc_info->irq_line->start, irq_data);
  1413. }
  1414. put_regulator:
  1415. if (i == -1)
  1416. i = soc_info->num_rgltr;
  1417. for (i = i - 1; i >= 0; i--) {
  1418. if (soc_info->rgltr[i]) {
  1419. regulator_disable(soc_info->rgltr[i]);
  1420. regulator_put(soc_info->rgltr[i]);
  1421. soc_info->rgltr[i] = NULL;
  1422. }
  1423. }
  1424. unmap_base:
  1425. if (i == -1)
  1426. i = soc_info->num_reg_map;
  1427. for (i = i - 1; i >= 0; i--) {
  1428. if (soc_info->reserve_mem)
  1429. release_mem_region(soc_info->mem_block[i]->start,
  1430. resource_size(soc_info->mem_block[i]));
  1431. iounmap(soc_info->reg_map[i].mem_base);
  1432. soc_info->reg_map[i].mem_base = NULL;
  1433. soc_info->reg_map[i].size = 0;
  1434. }
  1435. return rc;
  1436. }
  1437. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info)
  1438. {
  1439. int i;
  1440. if (!soc_info || !soc_info->dev) {
  1441. CAM_ERR(CAM_UTIL, "Invalid parameter");
  1442. return -EINVAL;
  1443. }
  1444. for (i = soc_info->num_clk - 1; i >= 0; i--) {
  1445. clk_put(soc_info->clk[i]);
  1446. soc_info->clk[i] = NULL;
  1447. }
  1448. for (i = soc_info->num_rgltr - 1; i >= 0; i--) {
  1449. if (soc_info->rgltr[i]) {
  1450. regulator_put(soc_info->rgltr[i]);
  1451. soc_info->rgltr[i] = NULL;
  1452. }
  1453. }
  1454. for (i = soc_info->num_reg_map - 1; i >= 0; i--) {
  1455. iounmap(soc_info->reg_map[i].mem_base);
  1456. soc_info->reg_map[i].mem_base = NULL;
  1457. soc_info->reg_map[i].size = 0;
  1458. }
  1459. if (soc_info->irq_line) {
  1460. disable_irq(soc_info->irq_line->start);
  1461. devm_free_irq(soc_info->dev,
  1462. soc_info->irq_line->start, soc_info->irq_data);
  1463. }
  1464. if (soc_info->pinctrl_info.pinctrl)
  1465. devm_pinctrl_put(soc_info->pinctrl_info.pinctrl);
  1466. /* release for gpio */
  1467. cam_soc_util_request_gpio_table(soc_info, false);
  1468. if (soc_info->clk_control_enable)
  1469. cam_soc_util_remove_clk_lvl_debugfs(soc_info);
  1470. return 0;
  1471. }
  1472. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  1473. bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq)
  1474. {
  1475. int rc = 0;
  1476. if (!soc_info)
  1477. return -EINVAL;
  1478. rc = cam_soc_util_regulator_enable_default(soc_info);
  1479. if (rc) {
  1480. CAM_ERR(CAM_UTIL, "Regulators enable failed");
  1481. return rc;
  1482. }
  1483. if (enable_clocks) {
  1484. rc = cam_soc_util_clk_enable_default(soc_info, clk_level);
  1485. if (rc)
  1486. goto disable_regulator;
  1487. }
  1488. if (enable_irq) {
  1489. rc = cam_soc_util_irq_enable(soc_info);
  1490. if (rc)
  1491. goto disable_clk;
  1492. }
  1493. if (soc_info->pinctrl_info.pinctrl &&
  1494. soc_info->pinctrl_info.gpio_state_active) {
  1495. rc = pinctrl_select_state(soc_info->pinctrl_info.pinctrl,
  1496. soc_info->pinctrl_info.gpio_state_active);
  1497. if (rc)
  1498. goto disable_irq;
  1499. }
  1500. return rc;
  1501. disable_irq:
  1502. if (enable_irq)
  1503. cam_soc_util_irq_disable(soc_info);
  1504. disable_clk:
  1505. if (enable_clocks)
  1506. cam_soc_util_clk_disable_default(soc_info);
  1507. disable_regulator:
  1508. cam_soc_util_regulator_disable_default(soc_info);
  1509. return rc;
  1510. }
  1511. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  1512. bool disable_clocks, bool disable_irq)
  1513. {
  1514. int rc = 0;
  1515. if (!soc_info)
  1516. return -EINVAL;
  1517. if (disable_irq)
  1518. rc |= cam_soc_util_irq_disable(soc_info);
  1519. if (disable_clocks)
  1520. cam_soc_util_clk_disable_default(soc_info);
  1521. cam_soc_util_regulator_disable_default(soc_info);
  1522. if (soc_info->pinctrl_info.pinctrl &&
  1523. soc_info->pinctrl_info.gpio_state_suspend)
  1524. rc = pinctrl_select_state(soc_info->pinctrl_info.pinctrl,
  1525. soc_info->pinctrl_info.gpio_state_suspend);
  1526. return rc;
  1527. }
  1528. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  1529. uint32_t base_index, uint32_t offset, int size)
  1530. {
  1531. void __iomem *base_addr = NULL;
  1532. CAM_DBG(CAM_UTIL, "base_idx %u size=%d", base_index, size);
  1533. if (!soc_info || base_index >= soc_info->num_reg_map ||
  1534. size <= 0 || (offset + size) >=
  1535. CAM_SOC_GET_REG_MAP_SIZE(soc_info, base_index))
  1536. return -EINVAL;
  1537. base_addr = CAM_SOC_GET_REG_MAP_START(soc_info, base_index);
  1538. /*
  1539. * All error checking already done above,
  1540. * hence ignoring the return value below.
  1541. */
  1542. cam_io_dump(base_addr, offset, size);
  1543. return 0;
  1544. }
  1545. static int cam_soc_util_dump_cont_reg_range(
  1546. struct cam_hw_soc_info *soc_info,
  1547. struct cam_reg_range_read_desc *reg_read, uint32_t base_idx,
  1548. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  1549. {
  1550. int i = 0, rc = 0;
  1551. uint32_t write_idx = 0;
  1552. if (!soc_info || !dump_out_buf || !reg_read || !cmd_buf_end) {
  1553. CAM_ERR(CAM_UTIL,
  1554. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK cmd_buf_end: %pK",
  1555. soc_info, dump_out_buf, reg_read, cmd_buf_end);
  1556. rc = -EINVAL;
  1557. goto end;
  1558. }
  1559. if ((reg_read->num_values) && ((reg_read->num_values > U32_MAX / 2) ||
  1560. (sizeof(uint32_t) > ((U32_MAX -
  1561. sizeof(struct cam_reg_dump_out_buffer) -
  1562. dump_out_buf->bytes_written) /
  1563. (reg_read->num_values * 2))))) {
  1564. CAM_ERR(CAM_UTIL,
  1565. "Integer Overflow bytes_written: [%u] num_values: [%u]",
  1566. dump_out_buf->bytes_written, reg_read->num_values);
  1567. rc = -EOVERFLOW;
  1568. goto end;
  1569. }
  1570. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  1571. (uintptr_t)(sizeof(struct cam_reg_dump_out_buffer)
  1572. - sizeof(uint32_t) + dump_out_buf->bytes_written +
  1573. (reg_read->num_values * 2 * sizeof(uint32_t)))) {
  1574. CAM_ERR(CAM_UTIL,
  1575. "Insufficient space in out buffer num_values: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  1576. reg_read->num_values, cmd_buf_end,
  1577. (uintptr_t)dump_out_buf);
  1578. rc = -EINVAL;
  1579. goto end;
  1580. }
  1581. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  1582. for (i = 0; i < reg_read->num_values; i++) {
  1583. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  1584. (uint32_t)soc_info->reg_map[base_idx].size) {
  1585. CAM_ERR(CAM_UTIL,
  1586. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  1587. (reg_read->offset + (i * sizeof(uint32_t))),
  1588. (uint32_t)soc_info->reg_map[base_idx].size);
  1589. rc = -EINVAL;
  1590. goto end;
  1591. }
  1592. dump_out_buf->dump_data[write_idx++] = reg_read->offset +
  1593. (i * sizeof(uint32_t));
  1594. dump_out_buf->dump_data[write_idx++] =
  1595. cam_soc_util_r(soc_info, base_idx,
  1596. (reg_read->offset + (i * sizeof(uint32_t))));
  1597. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  1598. }
  1599. end:
  1600. return rc;
  1601. }
  1602. static int cam_soc_util_dump_dmi_reg_range(
  1603. struct cam_hw_soc_info *soc_info,
  1604. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  1605. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  1606. {
  1607. int i = 0, rc = 0;
  1608. uint32_t write_idx = 0;
  1609. if (!soc_info || !dump_out_buf || !dmi_read || !cmd_buf_end) {
  1610. CAM_ERR(CAM_UTIL,
  1611. "Invalid input args soc_info: %pK, dump_out_buffer: %pK",
  1612. soc_info, dump_out_buf);
  1613. rc = -EINVAL;
  1614. goto end;
  1615. }
  1616. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  1617. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  1618. CAM_ERR(CAM_UTIL,
  1619. "Invalid number of requested writes, pre: %d post: %d",
  1620. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  1621. rc = -EINVAL;
  1622. goto end;
  1623. }
  1624. if ((dmi_read->num_pre_writes + dmi_read->dmi_data_read.num_values)
  1625. && ((dmi_read->num_pre_writes > U32_MAX / 2) ||
  1626. (dmi_read->dmi_data_read.num_values > U32_MAX / 2) ||
  1627. ((dmi_read->num_pre_writes * 2) > U32_MAX -
  1628. (dmi_read->dmi_data_read.num_values * 2)) ||
  1629. (sizeof(uint32_t) > ((U32_MAX -
  1630. sizeof(struct cam_reg_dump_out_buffer) -
  1631. dump_out_buf->bytes_written) / ((dmi_read->num_pre_writes +
  1632. dmi_read->dmi_data_read.num_values) * 2))))) {
  1633. CAM_ERR(CAM_UTIL,
  1634. "Integer Overflow bytes_written: [%u] num_pre_writes: [%u] num_values: [%u]",
  1635. dump_out_buf->bytes_written, dmi_read->num_pre_writes,
  1636. dmi_read->dmi_data_read.num_values);
  1637. rc = -EOVERFLOW;
  1638. goto end;
  1639. }
  1640. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  1641. (uintptr_t)(
  1642. sizeof(struct cam_reg_dump_out_buffer) - sizeof(uint32_t) +
  1643. (dump_out_buf->bytes_written +
  1644. (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  1645. (dmi_read->dmi_data_read.num_values * 2 *
  1646. sizeof(uint32_t))))) {
  1647. CAM_ERR(CAM_UTIL,
  1648. "Insufficient space in out buffer num_read_val: [%d] num_write_val: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  1649. dmi_read->dmi_data_read.num_values,
  1650. dmi_read->num_pre_writes, cmd_buf_end,
  1651. (uintptr_t)dump_out_buf);
  1652. rc = -EINVAL;
  1653. goto end;
  1654. }
  1655. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  1656. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  1657. if (dmi_read->pre_read_config[i].offset >
  1658. (uint32_t)soc_info->reg_map[base_idx].size) {
  1659. CAM_ERR(CAM_UTIL,
  1660. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  1661. dmi_read->pre_read_config[i].offset,
  1662. (uint32_t)soc_info->reg_map[base_idx].size);
  1663. rc = -EINVAL;
  1664. goto end;
  1665. }
  1666. cam_soc_util_w_mb(soc_info, base_idx,
  1667. dmi_read->pre_read_config[i].offset,
  1668. dmi_read->pre_read_config[i].value);
  1669. dump_out_buf->dump_data[write_idx++] =
  1670. dmi_read->pre_read_config[i].offset;
  1671. dump_out_buf->dump_data[write_idx++] =
  1672. dmi_read->pre_read_config[i].value;
  1673. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  1674. }
  1675. if (dmi_read->dmi_data_read.offset >
  1676. (uint32_t)soc_info->reg_map[base_idx].size) {
  1677. CAM_ERR(CAM_UTIL,
  1678. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  1679. dmi_read->dmi_data_read.offset,
  1680. (uint32_t)soc_info->reg_map[base_idx].size);
  1681. rc = -EINVAL;
  1682. goto end;
  1683. }
  1684. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  1685. dump_out_buf->dump_data[write_idx++] =
  1686. dmi_read->dmi_data_read.offset;
  1687. dump_out_buf->dump_data[write_idx++] =
  1688. cam_soc_util_r_mb(soc_info, base_idx,
  1689. dmi_read->dmi_data_read.offset);
  1690. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  1691. }
  1692. for (i = 0; i < dmi_read->num_post_writes; i++) {
  1693. if (dmi_read->post_read_config[i].offset >
  1694. (uint32_t)soc_info->reg_map[base_idx].size) {
  1695. CAM_ERR(CAM_UTIL,
  1696. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  1697. dmi_read->post_read_config[i].offset,
  1698. (uint32_t)soc_info->reg_map[base_idx].size);
  1699. rc = -EINVAL;
  1700. goto end;
  1701. }
  1702. cam_soc_util_w_mb(soc_info, base_idx,
  1703. dmi_read->post_read_config[i].offset,
  1704. dmi_read->post_read_config[i].value);
  1705. }
  1706. end:
  1707. return rc;
  1708. }
  1709. static int cam_soc_util_dump_dmi_reg_range_user_buf(
  1710. struct cam_hw_soc_info *soc_info,
  1711. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  1712. struct cam_hw_soc_dump_args *dump_args)
  1713. {
  1714. int i;
  1715. int rc;
  1716. size_t buf_len = 0;
  1717. uint8_t *dst;
  1718. size_t remain_len;
  1719. uint32_t min_len;
  1720. uint32_t *waddr, *start;
  1721. uintptr_t cpu_addr;
  1722. struct cam_hw_soc_dump_header *hdr;
  1723. if (!soc_info || !dump_args || !dmi_read) {
  1724. CAM_ERR(CAM_UTIL,
  1725. "Invalid input args soc_info: %pK, dump_args: %pK",
  1726. soc_info, dump_args);
  1727. rc = -EINVAL;
  1728. goto end;
  1729. }
  1730. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  1731. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  1732. CAM_ERR(CAM_UTIL,
  1733. "Invalid number of requested writes, pre: %d post: %d",
  1734. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  1735. rc = -EINVAL;
  1736. goto end;
  1737. }
  1738. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  1739. if (rc) {
  1740. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  1741. dump_args->buf_handle, rc);
  1742. goto end;
  1743. }
  1744. if (buf_len <= dump_args->offset) {
  1745. CAM_WARN(CAM_UTIL, "Dump offset overshoot offset %zu len %zu",
  1746. dump_args->offset, buf_len);
  1747. rc = -ENOSPC;
  1748. goto end;
  1749. }
  1750. remain_len = buf_len - dump_args->offset;
  1751. min_len = (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  1752. (dmi_read->dmi_data_read.num_values * 2 * sizeof(uint32_t)) +
  1753. sizeof(uint32_t);
  1754. if (remain_len < min_len) {
  1755. CAM_WARN(CAM_UTIL,
  1756. "Dump Buffer exhaust read %d write %d remain %zu min %u",
  1757. dmi_read->dmi_data_read.num_values,
  1758. dmi_read->num_pre_writes, remain_len,
  1759. min_len);
  1760. rc = -ENOSPC;
  1761. goto end;
  1762. }
  1763. dst = (uint8_t *)cpu_addr + dump_args->offset;
  1764. hdr = (struct cam_hw_soc_dump_header *)dst;
  1765. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  1766. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN,
  1767. "DMI_DUMP:");
  1768. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  1769. start = waddr;
  1770. hdr->word_size = sizeof(uint32_t);
  1771. *waddr = soc_info->index;
  1772. waddr++;
  1773. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  1774. if (dmi_read->pre_read_config[i].offset >
  1775. (uint32_t)soc_info->reg_map[base_idx].size) {
  1776. CAM_ERR(CAM_UTIL,
  1777. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  1778. dmi_read->pre_read_config[i].offset,
  1779. (uint32_t)soc_info->reg_map[base_idx].size);
  1780. rc = -EINVAL;
  1781. goto end;
  1782. }
  1783. cam_soc_util_w_mb(soc_info, base_idx,
  1784. dmi_read->pre_read_config[i].offset,
  1785. dmi_read->pre_read_config[i].value);
  1786. *waddr++ = dmi_read->pre_read_config[i].offset;
  1787. *waddr++ = dmi_read->pre_read_config[i].value;
  1788. }
  1789. if (dmi_read->dmi_data_read.offset >
  1790. (uint32_t)soc_info->reg_map[base_idx].size) {
  1791. CAM_ERR(CAM_UTIL,
  1792. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  1793. dmi_read->dmi_data_read.offset,
  1794. (uint32_t)soc_info->reg_map[base_idx].size);
  1795. rc = -EINVAL;
  1796. goto end;
  1797. }
  1798. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  1799. *waddr++ = dmi_read->dmi_data_read.offset;
  1800. *waddr++ = cam_soc_util_r_mb(soc_info, base_idx,
  1801. dmi_read->dmi_data_read.offset);
  1802. }
  1803. for (i = 0; i < dmi_read->num_post_writes; i++) {
  1804. if (dmi_read->post_read_config[i].offset >
  1805. (uint32_t)soc_info->reg_map[base_idx].size) {
  1806. CAM_ERR(CAM_UTIL,
  1807. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  1808. dmi_read->post_read_config[i].offset,
  1809. (uint32_t)soc_info->reg_map[base_idx].size);
  1810. rc = -EINVAL;
  1811. goto end;
  1812. }
  1813. cam_soc_util_w_mb(soc_info, base_idx,
  1814. dmi_read->post_read_config[i].offset,
  1815. dmi_read->post_read_config[i].value);
  1816. }
  1817. hdr->size = (waddr - start) * hdr->word_size;
  1818. dump_args->offset += hdr->size +
  1819. sizeof(struct cam_hw_soc_dump_header);
  1820. end:
  1821. return rc;
  1822. }
  1823. static int cam_soc_util_dump_cont_reg_range_user_buf(
  1824. struct cam_hw_soc_info *soc_info,
  1825. struct cam_reg_range_read_desc *reg_read,
  1826. uint32_t base_idx,
  1827. struct cam_hw_soc_dump_args *dump_args)
  1828. {
  1829. int i;
  1830. int rc = 0;
  1831. size_t buf_len;
  1832. uint8_t *dst;
  1833. size_t remain_len;
  1834. uint32_t min_len;
  1835. uint32_t *waddr, *start;
  1836. uintptr_t cpu_addr;
  1837. struct cam_hw_soc_dump_header *hdr;
  1838. if (!soc_info || !dump_args || !reg_read) {
  1839. CAM_ERR(CAM_UTIL,
  1840. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK",
  1841. soc_info, dump_args, reg_read);
  1842. rc = -EINVAL;
  1843. goto end;
  1844. }
  1845. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  1846. if (rc) {
  1847. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  1848. dump_args->buf_handle, rc);
  1849. goto end;
  1850. }
  1851. if (buf_len <= dump_args->offset) {
  1852. CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu",
  1853. dump_args->offset, buf_len);
  1854. rc = -ENOSPC;
  1855. goto end;
  1856. }
  1857. remain_len = buf_len - dump_args->offset;
  1858. min_len = (reg_read->num_values * 2 * sizeof(uint32_t)) +
  1859. sizeof(struct cam_hw_soc_dump_header) + sizeof(uint32_t);
  1860. if (remain_len < min_len) {
  1861. CAM_WARN(CAM_UTIL,
  1862. "Dump Buffer exhaust read_values %d remain %zu min %u",
  1863. reg_read->num_values,
  1864. remain_len,
  1865. min_len);
  1866. rc = -ENOSPC;
  1867. goto end;
  1868. }
  1869. dst = (uint8_t *)cpu_addr + dump_args->offset;
  1870. hdr = (struct cam_hw_soc_dump_header *)dst;
  1871. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  1872. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, "%s_REG:",
  1873. soc_info->dev_name);
  1874. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  1875. start = waddr;
  1876. hdr->word_size = sizeof(uint32_t);
  1877. *waddr = soc_info->index;
  1878. waddr++;
  1879. for (i = 0; i < reg_read->num_values; i++) {
  1880. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  1881. (uint32_t)soc_info->reg_map[base_idx].size) {
  1882. CAM_ERR(CAM_UTIL,
  1883. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  1884. (reg_read->offset + (i * sizeof(uint32_t))),
  1885. (uint32_t)soc_info->reg_map[base_idx].size);
  1886. rc = -EINVAL;
  1887. goto end;
  1888. }
  1889. waddr[0] = reg_read->offset + (i * sizeof(uint32_t));
  1890. waddr[1] = cam_soc_util_r(soc_info, base_idx,
  1891. (reg_read->offset + (i * sizeof(uint32_t))));
  1892. waddr += 2;
  1893. }
  1894. hdr->size = (waddr - start) * hdr->word_size;
  1895. dump_args->offset += hdr->size +
  1896. sizeof(struct cam_hw_soc_dump_header);
  1897. end:
  1898. return rc;
  1899. }
  1900. static int cam_soc_util_user_reg_dump(
  1901. struct cam_reg_dump_desc *reg_dump_desc,
  1902. struct cam_hw_soc_dump_args *dump_args,
  1903. struct cam_hw_soc_info *soc_info,
  1904. uint32_t reg_base_idx)
  1905. {
  1906. int rc = 0;
  1907. int i;
  1908. struct cam_reg_read_info *reg_read_info = NULL;
  1909. if (!dump_args || !reg_dump_desc || !soc_info) {
  1910. CAM_ERR(CAM_UTIL,
  1911. "Invalid input parameters %pK %pK %pK",
  1912. dump_args, reg_dump_desc, soc_info);
  1913. return -EINVAL;
  1914. }
  1915. for (i = 0; i < reg_dump_desc->num_read_range; i++) {
  1916. reg_read_info = &reg_dump_desc->read_range[i];
  1917. if (reg_read_info->type ==
  1918. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  1919. rc = cam_soc_util_dump_cont_reg_range_user_buf(
  1920. soc_info,
  1921. &reg_read_info->reg_read,
  1922. reg_base_idx,
  1923. dump_args);
  1924. } else if (reg_read_info->type ==
  1925. CAM_REG_DUMP_READ_TYPE_DMI) {
  1926. rc = cam_soc_util_dump_dmi_reg_range_user_buf(
  1927. soc_info,
  1928. &reg_read_info->dmi_read,
  1929. reg_base_idx,
  1930. dump_args);
  1931. } else {
  1932. CAM_ERR(CAM_UTIL,
  1933. "Invalid Reg dump read type: %d",
  1934. reg_read_info->type);
  1935. rc = -EINVAL;
  1936. goto end;
  1937. }
  1938. if (rc) {
  1939. CAM_ERR(CAM_UTIL,
  1940. "Reg range read failed rc: %d reg_base_idx: %d",
  1941. rc, reg_base_idx);
  1942. goto end;
  1943. }
  1944. }
  1945. end:
  1946. return rc;
  1947. }
  1948. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  1949. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  1950. cam_soc_util_regspace_data_cb reg_data_cb,
  1951. struct cam_hw_soc_dump_args *soc_dump_args,
  1952. bool user_triggered_dump)
  1953. {
  1954. int rc = 0, i, j;
  1955. uintptr_t cpu_addr = 0;
  1956. uintptr_t cmd_buf_start = 0;
  1957. uintptr_t cmd_in_data_end = 0;
  1958. uintptr_t cmd_buf_end = 0;
  1959. uint32_t reg_base_type = 0;
  1960. size_t buf_size = 0, remain_len = 0;
  1961. struct cam_reg_dump_input_info *reg_input_info = NULL;
  1962. struct cam_reg_dump_desc *reg_dump_desc = NULL;
  1963. struct cam_reg_dump_out_buffer *dump_out_buf = NULL;
  1964. struct cam_reg_read_info *reg_read_info = NULL;
  1965. struct cam_hw_soc_info *soc_info;
  1966. uint32_t reg_base_idx = 0;
  1967. if (!ctx || !cmd_desc || !reg_data_cb) {
  1968. CAM_ERR(CAM_UTIL, "Invalid args to reg dump [%pK] [%pK]",
  1969. cmd_desc, reg_data_cb);
  1970. return -EINVAL;
  1971. }
  1972. if (!cmd_desc->length || !cmd_desc->size) {
  1973. CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d",
  1974. cmd_desc->length, cmd_desc->size);
  1975. return -EINVAL;
  1976. }
  1977. rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, &cpu_addr, &buf_size);
  1978. if (rc || !cpu_addr || (buf_size == 0)) {
  1979. CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK",
  1980. rc, (void *)cpu_addr);
  1981. goto end;
  1982. }
  1983. CAM_DBG(CAM_UTIL, "Get cpu buf success req_id: %llu buf_size: %zu",
  1984. req_id, buf_size);
  1985. if ((buf_size < sizeof(uint32_t)) ||
  1986. ((size_t)cmd_desc->offset > (buf_size - sizeof(uint32_t)))) {
  1987. CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu",
  1988. (size_t)cmd_desc->offset);
  1989. rc = -EINVAL;
  1990. goto end;
  1991. }
  1992. remain_len = buf_size - (size_t)cmd_desc->offset;
  1993. if ((remain_len < (size_t)cmd_desc->size) || (cmd_desc->size <
  1994. cmd_desc->length)) {
  1995. CAM_ERR(CAM_UTIL,
  1996. "Invalid params for cmd buf len: %zu size: %zu remain_len: %zu",
  1997. (size_t)cmd_desc->length, (size_t)cmd_desc->length,
  1998. remain_len);
  1999. rc = -EINVAL;
  2000. goto end;
  2001. }
  2002. cmd_buf_start = cpu_addr + (uintptr_t)cmd_desc->offset;
  2003. cmd_in_data_end = cmd_buf_start + (uintptr_t)cmd_desc->length;
  2004. cmd_buf_end = cmd_buf_start + (uintptr_t)cmd_desc->size;
  2005. if ((cmd_buf_end <= cmd_buf_start) ||
  2006. (cmd_in_data_end <= cmd_buf_start)) {
  2007. CAM_ERR(CAM_UTIL,
  2008. "Invalid length or size for cmd buf: [%zu] [%zu]",
  2009. (size_t)cmd_desc->length, (size_t)cmd_desc->size);
  2010. rc = -EINVAL;
  2011. goto end;
  2012. }
  2013. CAM_DBG(CAM_UTIL,
  2014. "Buffer params start [%pK] input_end [%pK] buf_end [%pK]",
  2015. cmd_buf_start, cmd_in_data_end, cmd_buf_end);
  2016. reg_input_info = (struct cam_reg_dump_input_info *) cmd_buf_start;
  2017. if ((reg_input_info->num_dump_sets > 1) && (sizeof(uint32_t) >
  2018. ((U32_MAX - sizeof(struct cam_reg_dump_input_info)) /
  2019. (reg_input_info->num_dump_sets - 1)))) {
  2020. CAM_ERR(CAM_UTIL,
  2021. "Integer Overflow req_id: [%llu] num_dump_sets: [%u]",
  2022. req_id, reg_input_info->num_dump_sets);
  2023. rc = -EOVERFLOW;
  2024. goto end;
  2025. }
  2026. if ((!reg_input_info->num_dump_sets) ||
  2027. ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  2028. (sizeof(struct cam_reg_dump_input_info) +
  2029. ((reg_input_info->num_dump_sets - 1) * sizeof(uint32_t))))) {
  2030. CAM_ERR(CAM_UTIL,
  2031. "Invalid number of dump sets, req_id: [%llu] num_dump_sets: [%u]",
  2032. req_id, reg_input_info->num_dump_sets);
  2033. rc = -EINVAL;
  2034. goto end;
  2035. }
  2036. CAM_DBG(CAM_UTIL,
  2037. "reg_input_info req_id: %llu ctx %pK num_dump_sets: %d",
  2038. req_id, ctx, reg_input_info->num_dump_sets);
  2039. for (i = 0; i < reg_input_info->num_dump_sets; i++) {
  2040. if ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  2041. reg_input_info->dump_set_offsets[i]) {
  2042. CAM_ERR(CAM_UTIL,
  2043. "Invalid dump set offset: [%pK], cmd_buf_start: [%pK] cmd_in_data_end: [%pK]",
  2044. (uintptr_t)reg_input_info->dump_set_offsets[i],
  2045. cmd_buf_start, cmd_in_data_end);
  2046. rc = -EINVAL;
  2047. goto end;
  2048. }
  2049. reg_dump_desc = (struct cam_reg_dump_desc *)
  2050. (cmd_buf_start +
  2051. (uintptr_t)reg_input_info->dump_set_offsets[i]);
  2052. if ((reg_dump_desc->num_read_range > 1) &&
  2053. (sizeof(struct cam_reg_read_info) > ((U32_MAX -
  2054. sizeof(struct cam_reg_dump_desc)) /
  2055. (reg_dump_desc->num_read_range - 1)))) {
  2056. CAM_ERR(CAM_UTIL,
  2057. "Integer Overflow req_id: [%llu] num_read_range: [%u]",
  2058. req_id, reg_dump_desc->num_read_range);
  2059. rc = -EOVERFLOW;
  2060. goto end;
  2061. }
  2062. if ((!reg_dump_desc->num_read_range) ||
  2063. ((cmd_in_data_end - (uintptr_t)reg_dump_desc) <=
  2064. (uintptr_t)(sizeof(struct cam_reg_dump_desc) +
  2065. ((reg_dump_desc->num_read_range - 1) *
  2066. sizeof(struct cam_reg_read_info))))) {
  2067. CAM_ERR(CAM_UTIL,
  2068. "Invalid number of read ranges, req_id: [%llu] num_read_range: [%d]",
  2069. req_id, reg_dump_desc->num_read_range);
  2070. rc = -EINVAL;
  2071. goto end;
  2072. }
  2073. if ((cmd_buf_end - cmd_buf_start) <= (uintptr_t)
  2074. (reg_dump_desc->dump_buffer_offset +
  2075. sizeof(struct cam_reg_dump_out_buffer))) {
  2076. CAM_ERR(CAM_UTIL,
  2077. "Invalid out buffer offset: [%pK], cmd_buf_start: [%pK] cmd_buf_end: [%pK]",
  2078. (uintptr_t)reg_dump_desc->dump_buffer_offset,
  2079. cmd_buf_start, cmd_buf_end);
  2080. rc = -EINVAL;
  2081. goto end;
  2082. }
  2083. reg_base_type = reg_dump_desc->reg_base_type;
  2084. if (reg_base_type == 0 || reg_base_type >
  2085. CAM_REG_DUMP_BASE_TYPE_CAMNOC) {
  2086. CAM_ERR(CAM_UTIL,
  2087. "Invalid Reg dump base type: %d",
  2088. reg_base_type);
  2089. rc = -EINVAL;
  2090. goto end;
  2091. }
  2092. rc = reg_data_cb(reg_base_type, ctx, &soc_info, &reg_base_idx);
  2093. if (rc || !soc_info) {
  2094. CAM_ERR(CAM_UTIL,
  2095. "Reg space data callback failed rc: %d soc_info: [%pK]",
  2096. rc, soc_info);
  2097. rc = -EINVAL;
  2098. goto end;
  2099. }
  2100. if (reg_base_idx > soc_info->num_reg_map) {
  2101. CAM_ERR(CAM_UTIL,
  2102. "Invalid reg base idx: %d num reg map: %d",
  2103. reg_base_idx, soc_info->num_reg_map);
  2104. rc = -EINVAL;
  2105. goto end;
  2106. }
  2107. CAM_DBG(CAM_UTIL,
  2108. "Reg data callback success req_id: %llu base_type: %d base_idx: %d num_read_range: %d",
  2109. req_id, reg_base_type, reg_base_idx,
  2110. reg_dump_desc->num_read_range);
  2111. /* If the dump request is triggered by user space
  2112. * buffer will be different from the buffer which is received
  2113. * in init packet. In this case, dump the data to the
  2114. * user provided buffer and exit.
  2115. */
  2116. if (user_triggered_dump) {
  2117. rc = cam_soc_util_user_reg_dump(reg_dump_desc,
  2118. soc_dump_args, soc_info, reg_base_idx);
  2119. CAM_INFO(CAM_UTIL,
  2120. "%s reg_base_idx %d dumped offset %u",
  2121. soc_info->dev_name, reg_base_idx,
  2122. soc_dump_args->offset);
  2123. goto end;
  2124. }
  2125. /* Below code is executed when data is dumped to the
  2126. * out buffer received in init packet
  2127. */
  2128. dump_out_buf = (struct cam_reg_dump_out_buffer *)
  2129. (cmd_buf_start +
  2130. (uintptr_t)reg_dump_desc->dump_buffer_offset);
  2131. dump_out_buf->req_id = req_id;
  2132. dump_out_buf->bytes_written = 0;
  2133. for (j = 0; j < reg_dump_desc->num_read_range; j++) {
  2134. CAM_DBG(CAM_UTIL,
  2135. "Number of bytes written to cmd buffer: %u req_id: %llu",
  2136. dump_out_buf->bytes_written, req_id);
  2137. reg_read_info = &reg_dump_desc->read_range[j];
  2138. if (reg_read_info->type ==
  2139. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  2140. rc = cam_soc_util_dump_cont_reg_range(soc_info,
  2141. &reg_read_info->reg_read, reg_base_idx,
  2142. dump_out_buf, cmd_buf_end);
  2143. } else if (reg_read_info->type ==
  2144. CAM_REG_DUMP_READ_TYPE_DMI) {
  2145. rc = cam_soc_util_dump_dmi_reg_range(soc_info,
  2146. &reg_read_info->dmi_read, reg_base_idx,
  2147. dump_out_buf, cmd_buf_end);
  2148. } else {
  2149. CAM_ERR(CAM_UTIL,
  2150. "Invalid Reg dump read type: %d",
  2151. reg_read_info->type);
  2152. rc = -EINVAL;
  2153. goto end;
  2154. }
  2155. if (rc) {
  2156. CAM_ERR(CAM_UTIL,
  2157. "Reg range read failed rc: %d reg_base_idx: %d dump_out_buf: %pK",
  2158. rc, reg_base_idx, dump_out_buf);
  2159. goto end;
  2160. }
  2161. }
  2162. }
  2163. end:
  2164. return rc;
  2165. }