95c95b2d67
Update digital_cdc_rsc_mgr_hw_vote_enable/disable API with device info for easy debug. Also, add swrm clock enable checks during SSR. When SSR happens, swrm->hw_core_clk_en and swrm->aud_core_clk_en will be reset without resetting audio_vote and core_vote clk. This would cause clk mismatch in audio driver and adsp and device fails suspending when there's no audio usecase. Make this change to reset audio_vote and core_vote clk when receiving SWR_DEVICE_SSR_DOWN. Change-Id: I9875aac9f6faf8b6481457a70f31b005073369e0 Signed-off-by: Meng Wang <quic_mengw@quicinc.com>
47 rader
1.1 KiB
C
47 rader
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
|
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#ifndef DIGITAL_CDC_RSC_MGR_H
|
|
#define DIGITAL_CDC_RSC_MGR_H
|
|
|
|
#include <linux/clk.h>
|
|
|
|
#ifdef CONFIG_DIGITAL_CDC_RSC_MGR
|
|
|
|
int digital_cdc_rsc_mgr_hw_vote_enable(struct clk *vote_handle, struct device *dev);
|
|
void digital_cdc_rsc_mgr_hw_vote_disable(struct clk *vote_handle, struct device *dev);
|
|
void digital_cdc_rsc_mgr_hw_vote_reset(struct clk *vote_handle);
|
|
|
|
void digital_cdc_rsc_mgr_init(void);
|
|
void digital_cdc_rsc_mgr_exit(void);
|
|
|
|
#else
|
|
|
|
static inline int digital_cdc_rsc_mgr_hw_vote_enable(struct clk *vote_handle, struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void digital_cdc_rsc_mgr_hw_vote_disable(struct clk *vote_handle, struct device *dev)
|
|
{
|
|
}
|
|
|
|
static inline void digital_cdc_rsc_mgr_hw_vote_reset(struct clk *vote_handle)
|
|
{
|
|
}
|
|
|
|
static inline void digital_cdc_rsc_mgr_init(void)
|
|
{
|
|
}
|
|
|
|
static inline void digital_cdc_rsc_mgr_exit(void)
|
|
{
|
|
}
|
|
|
|
#endif /* CONFIG_DIGITAL_CDC_RSC_MGR */
|
|
|
|
#endif /* DIGITAL_CDC_RSC_MGR_H */
|