android_kernel_samsung_sm8650-modules/hw/wcn6450/v1/wcss_seq_hwiobase.h

/*
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
 * above copyright notice and this permission notice appear in all
 * copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 * PERFORMANCE OF THIS SOFTWARE.
 */



#ifndef __WCSS_SEQ_BASE_H__
#define __WCSS_SEQ_BASE_H__

#ifdef SCALE_INCLUDES
	#include "HALhwio.h"
#else
	#include "msmhwio.h"
#endif

#ifndef SOC_WCSS_BASE_ADDR
    #if defined(WCSS_BASE)
        #if ( WCSS_BASE != 0x0 )
            #error WCSS_BASE incorrectly redefined!
        #endif
    #endif

    #define SOC_WCSS_BASE_ADDR 0x0
#else
    #if ( SOC_WCSS_BASE_ADDR != 0x0 )
        #error SOC_WCSS_BASE_ADDR incorrectly redefined!
    #endif
#endif

#define SEQ_WCSS_UMAC_NOC_OFFSET                                     0x00140000
#define SEQ_WCSS_PHYA_OFFSET                                         0x00300000
#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                 0x00300000
#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET                       0x00338000
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                 0x00338400
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                 0x00338800
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                 0x00338c00
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                 0x00339000
#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                 0x00339400
#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET                0x00339800
#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_REG_MAP_OFFSET                  0x0033f400
#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET           0x0033f600
#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET                        0x00388000
#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET                       0x00390000
#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET                       0x003a0000
#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET                       0x003b0000
#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET                 0x00400000
#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET                      0x00480000
#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET                       0x004b0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET                     0x005c0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET             0x005c0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET  0x005cf000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET     0x005cf400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET     0x005c0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x005c5000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET         0x005d1000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x005d1000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x005d1038
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET     0x005d10cc
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x005c7000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x005cb000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET             0x005d4000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET         0x005d4000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET  0x005d41fc
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET      0x005d4204
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET      0x005d4300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET    0x005d43c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x005d4424
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET     0x005d4880
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET      0x005d4c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET     0x005d5c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6840
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6900
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6940
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6980
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d69c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d7000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d7040
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d7100
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d7140
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d7180
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d71c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET    0x005d7400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x005d7400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x005d7438
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x005d74cc
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET              0x005d8000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET        0x005d8000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET        0x005d8400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET  0x005d8800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x005d8880
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET  0x005d8940
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET  0x005d8980
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET              0x005dc000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET       0x005dc000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET   0x005dc400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET      0x005dc800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET      0x005dcc00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET      0x005dd000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET      0x005dd400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005dd800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET       0x005dd980
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005dd9c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET  0x005ddac0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET  0x005dfc00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET  0x005dfc80
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET  0x005dfcc0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x005dfd40
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET              0x005e0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x005e021c
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e21b8
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x005e821c
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET  0x005e8400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET  0x005e8800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000
#define SEQ_WCSS_UMAC_OFFSET                                         0x00a00000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET                             0x00a20000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET                 0x00a20000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                0x00a22000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET            0x00a24000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET                 0x00a26000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET                 0x00a28000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET                 0x00a2a000
#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET                          0x00a30000
#define SEQ_WCSS_UMAC_TQM_REG_OFFSET                                 0x00a3c000
#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET                           0x00a40000
#define SEQ_WCSS_WMAC0_OFFSET                                        0x00a80000
#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET                            0x00a80000
#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET                          0x00a83000
#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET                          0x00a86000
#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET                           0x00a89000
#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET                          0x00a8c000
#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET                          0x00a8f000
#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET                           0x00a92000
#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET                          0x00a95000
#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET                   0x00a98000
#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET                            0x00a9b000
#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET                          0x00a9e000
#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET                   0x00aa1000
#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET                            0x00aa4000
#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET                         0x00aa7000
#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET                          0x00aaa000
#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET                            0x00ab0000
#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET                            0x00ab3000
#define SEQ_WCSS_APB_TSLV_OFFSET                                     0x00b40000
#define SEQ_WCSS_TOP_CMN_OFFSET                                      0x00b50000
#define SEQ_WCSS_WCMN_CORE_OFFSET                                    0x00b58000
#define SEQ_WCSS_WFSS_PMM_OFFSET                                     0x00b60000
#define SEQ_WCSS_PMM_TOP_OFFSET                                      0x00b70000
#define SEQ_WCSS_MSIP_OFFSET                                         0x00b80000
#define SEQ_WCSS_MSIP_RBIST_TX_CH0_OFFSET                            0x00b80000
#define SEQ_WCSS_MSIP_WL_DAC_CH0_OFFSET                              0x00b80180
#define SEQ_WCSS_MSIP_WL_DAC_CALIB_CH0_OFFSET                        0x00b80190
#define SEQ_WCSS_MSIP_WL_DAC_REGARRAY_CH0_OFFSET                     0x00b80200
#define SEQ_WCSS_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET                     0x00b802c0
#define SEQ_WCSS_MSIP_WL_ADC_CH0_OFFSET                              0x00b80400
#define SEQ_WCSS_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET                     0x00b80434
#define SEQ_WCSS_MSIP_MSIP_SHD_OTP_OFFSET                            0x00b8d000
#define SEQ_WCSS_MSIP_MSIP_TMUX_OFFSET                               0x00b8d040
#define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET                                0x00b8d080
#define SEQ_WCSS_MSIP_MSIP_LDO_CTRL_OFFSET                           0x00b8d0b4
#define SEQ_WCSS_MSIP_MSIP_CLKGEN_OFFSET                             0x00b8d100
#define SEQ_WCSS_MSIP_MSIP_BIAS_OFFSET                               0x00b8e000
#define SEQ_WCSS_MSIP_BBPLL_OFFSET                                   0x00b8f000
#define SEQ_WCSS_MSIP_WL_CLKGEN_OFFSET                               0x00b8f800
#define SEQ_WCSS_MSIP_MSIP_DRM_REG_OFFSET                            0x00b8fc00
#define SEQ_WCSS_DBG_OFFSET                                          0x00b90000
#define SEQ_WCSS_DBG_WCSS_DBG_ROM_TABLE_OFFSET                       0x00b90000
#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET                         0x00b91000
#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET                            0x00b92000
#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET                    0x00b94000
#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET                     0x00b95000
#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                    0x00b96000
#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET                           0x00bb0000
#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET              0x00bb1000
#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET                               0x00bb2000
#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET                0x00bb3000
#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET                             0x00bb4000
#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET               0x00bb5000
#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET                    0x00bb6000
#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET                    0x00bb8000
#define SEQ_WCSS_DBG_TPDM_OFFSET                                     0x00bb9000
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000
#define SEQ_WCSS_DBG_TPDA_OFFSET                                     0x00bba000
#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET                      0x00bbb000
#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET                       0x00bbc000
#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET               0x00bbe000
#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET               0x00bbf000
#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET                        0x00bc0000
#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET                                 0x00bc1000
#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET                  0x00bc4000
#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET                     0x00bc5000
#define SEQ_WCSS_DBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET          0x00bc9000
#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET                            0x00bd0000
#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET                            0x00be0000
#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET                   0x00be0000
#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET     0x00be4000
#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET         0x00be5000
#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET            0x00be6000
#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET                              0x00c31000
#define SEQ_WCSS_RET_AHB_OFFSET                                      0x00c90000
#define SEQ_WCSS_WAHB_TSLV_OFFSET                                    0x00ca0000
#define SEQ_WCSS_CC_OFFSET                                           0x00cb0000
#define SEQ_WCSS_UMAC_ACMT_OFFSET                                    0x00cc0000

#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                  0x00000000
#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET                        0x00038000
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                  0x00038400
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                  0x00038800
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                  0x00038c00
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                  0x00039000
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                  0x00039400
#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET                 0x00039800
#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_REG_MAP_OFFSET                   0x0003f400
#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET            0x0003f600
#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET                         0x00088000
#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET                        0x00090000
#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET                        0x000a0000
#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET                        0x000b0000
#define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET                  0x00100000
#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET                       0x00180000
#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET                        0x001b0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET                      0x002c0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET              0x002c0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET   0x002cf000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET      0x002cf400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET  0x002cfc00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET      0x002c0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x002c5000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET          0x002d1000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x002d1000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET  0x002d1038
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET      0x002d10cc
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x002c7000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x002cb000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET              0x002d4000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET          0x002d4000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET   0x002d41fc
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET       0x002d4204
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET       0x002d4300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET     0x002d43c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x002d4424
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET  0x002d4800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET      0x002d4880
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET       0x002d4c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET      0x002d5c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6840
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6900
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6940
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6980
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d69c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d7000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d7040
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d7100
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d7140
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d7180
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d71c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET     0x002d7400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x002d7400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x002d7438
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x002d74cc
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET               0x002d8000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET         0x002d8000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET         0x002d8400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET   0x002d8800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x002d8880
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x002d88c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET   0x002d8940
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET   0x002d8980
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET               0x002dc000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET        0x002dc000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET    0x002dc400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET       0x002dc800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET       0x002dcc00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET       0x002dd000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET       0x002dd400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002dd800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET        0x002dd980
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002dd9c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET   0x002ddac0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET   0x002dfc00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET   0x002dfc80
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET   0x002dfcc0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x002dfd40
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET               0x002e0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET  0x002e0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x002e021c
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e21b8
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET  0x002e8000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x002e821c
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET   0x002e8400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET   0x002e8800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000

#define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET                              0x00000000
#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET                   0x0000f000
#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET                      0x0000f400
#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET              0x0000f800
#define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET                  0x0000fc00
#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET                      0x00000000
#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET             0x00005000
#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET                          0x00011000
#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET              0x00011000
#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OTP_OFFSET                  0x00011038
#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OFFSET                      0x000110cc
#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET          0x00007000
#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00
#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000
#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000
#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET                              0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET                          0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SW_RST_OFFSET                   0x000141fc
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_RAH_OFFSET                       0x00014204
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET                       0x00014300
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET                     0x000143c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET                 0x00014424
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET                  0x00014800
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET                      0x00014880
#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET                       0x00014c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET                      0x00015c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET                 0x00016800
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET               0x00016840
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET               0x00016900
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET                 0x00016940
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET               0x00016980
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET                 0x000169c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET                 0x00017000
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET               0x00017040
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET               0x00017100
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET                 0x00017140
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET               0x00017180
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET                 0x000171c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET               0x00017c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET                     0x00017400
#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET         0x00017400
#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET             0x00017438
#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OFFSET                 0x000174cc
#define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET                               0x00018000
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET                         0x00018000
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET                         0x00018400
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BS_OFFSET                   0x00018800
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_CLBS_OFFSET                 0x00018880
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET                 0x000188c0
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET                   0x00018940
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET                   0x00018980
#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET                               0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET                        0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DRM_REG_OFFSET                    0x0001c400
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXBB_OFFSET                       0x0001c800
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_OFFSET                       0x0001cc00
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_OFFSET                       0x0001d000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_OFFSET                       0x0001d400
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET          0x0001d800
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET                        0x0001d980
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET         0x0001d9c0
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET                   0x0001dac0
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET                   0x0001fc00
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET                 0x0001fc40
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET                   0x0001fc80
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET                   0x0001fcc0
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_CLBS_OFFSET                 0x0001fd40
#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET                               0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET                  0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_2G_CH0_OFFSET                0x0002021c
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET                0x00021000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET                0x00021300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET                 0x000221b8
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET                 0x00024000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET                  0x00028000
#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_5G_CH0_OFFSET                0x0002821c
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET                   0x00028400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET                   0x00028800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET                0x00029000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET                0x00029300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET                 0x0002a000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET                 0x0002c000

#define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET                                0x0000f000
#define SEQ_RFA_SOC_AO_TLMM_OFFSET                                   0x0000f400
#define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET                           0x0000f800
#define SEQ_RFA_SOC_AON_1P8_REG_OFFSET                               0x0000fc00
#define SEQ_RFA_SOC_HZ_TLMM_OFFSET                                   0x00000000
#define SEQ_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET                          0x00005000
#define SEQ_RFA_SOC_PMU_OFFSET                                       0x00011000
#define SEQ_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET                           0x00011000
#define SEQ_RFA_SOC_PMU_PMU_OTP_OFFSET                               0x00011038
#define SEQ_RFA_SOC_PMU_PMU_OFFSET                                   0x000110cc
#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET                       0x00007000
#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00
#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET   0x00007000
#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET  0x0000b000

#define SEQ_PMU_TOP_PMU_SHD_OTP_OFFSET                               0x00000000
#define SEQ_PMU_TOP_PMU_OTP_OFFSET                                   0x00000038
#define SEQ_PMU_TOP_PMU_OFFSET                                       0x000000cc

#define SEQ_SECURITY_CONTROL_BT_CMN_SECURITY_CONTROL_CORE_OFFSET     0x00002b00
#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_RAW_FUSE_OFFSET           0x00000000
#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_CORR_FUSE_OFFSET          0x00004000

#define SEQ_RFA_CMN_AON_OFFSET                                       0x00000000
#define SEQ_RFA_CMN_RFA_SW_RST_OFFSET                                0x000001fc
#define SEQ_RFA_CMN_WL_RAH_OFFSET                                    0x00000204
#define SEQ_RFA_CMN_RFFE_M_OFFSET                                    0x00000300
#define SEQ_RFA_CMN_AON_COEX_OFFSET                                  0x000003c0
#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET                              0x00000424
#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET                               0x00000800
#define SEQ_RFA_CMN_RFA_OTP_OFFSET                                   0x00000880
#define SEQ_RFA_CMN_CLKGEN_OFFSET                                    0x00000c00
#define SEQ_RFA_CMN_BTFMPLL_OFFSET                                   0x00001c00
#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET                              0x00002800
#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET                            0x00002840
#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET                            0x00002900
#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET                              0x00002940
#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET                            0x00002980
#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET                              0x000029c0
#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET                              0x00003000
#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET                            0x00003040
#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET                            0x00003100
#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET                              0x00003140
#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET                            0x00003180
#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET                              0x000031c0
#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET                            0x00003c00
#define SEQ_RFA_CMN_PMU_TEST_OFFSET                                  0x00003400
#define SEQ_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET                      0x00003400
#define SEQ_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET                          0x00003438
#define SEQ_RFA_CMN_PMU_TEST_PMU_OFFSET                              0x000034cc

#define SEQ_RFA_FM_FM_MC_OFFSET                                      0x00000000
#define SEQ_RFA_FM_FM_RX_OFFSET                                      0x00000400
#define SEQ_RFA_FM_FM_SYNTH_BS_OFFSET                                0x00000800
#define SEQ_RFA_FM_FM_SYNTH_CLBS_OFFSET                              0x00000880
#define SEQ_RFA_FM_FM_SYNTH_BIST_OFFSET                              0x000008c0
#define SEQ_RFA_FM_FM_SYNTH_PC_OFFSET                                0x00000940
#define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET                                0x00000980

#define SEQ_RFA_BT_BT_TOP_OFFSET                                     0x00000000
#define SEQ_RFA_BT_BT_DRM_REG_OFFSET                                 0x00000400
#define SEQ_RFA_BT_BT_TXBB_OFFSET                                    0x00000800
#define SEQ_RFA_BT_BT_TXFE_OFFSET                                    0x00000c00
#define SEQ_RFA_BT_BT_RXBB_OFFSET                                    0x00001000
#define SEQ_RFA_BT_BT_RXFE_OFFSET                                    0x00001400
#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET                       0x00001800
#define SEQ_RFA_BT_BT_DAC_OFFSET                                     0x00001980
#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET                      0x000019c0
#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET                                0x00001ac0
#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET                                0x00003c00
#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET                              0x00003c40
#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET                                0x00003c80
#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET                                0x00003cc0
#define SEQ_RFA_BT_BT_SYNTH_CLBS_OFFSET                              0x00003d40

#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET                               0x00000000
#define SEQ_RFA_WL_RFA_TGL_2G_CH0_OFFSET                             0x0000021c
#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET                             0x00001000
#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET                             0x00001300
#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET                              0x000021b8
#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET                              0x00004000
#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET                               0x00008000
#define SEQ_RFA_WL_RFA_TGL_5G_CH0_OFFSET                             0x0000821c
#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET                                0x00008400
#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET                                0x00008800
#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET                             0x00009000
#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET                             0x00009300
#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET                              0x0000a000
#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET                              0x0000c000

#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET                          0x00020000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET              0x00020000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET             0x00022000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET         0x00024000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET              0x00026000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET              0x00028000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET              0x0002a000
#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET                       0x00030000
#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET                              0x0003c000
#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET                        0x00040000

#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET                           0x00000000
#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                          0x00002000
#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET                      0x00004000
#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET                           0x00006000
#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET                           0x00008000
#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET                           0x0000a000

#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET                          0x00000000
#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET                        0x00003000
#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET                        0x00006000
#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET                         0x00009000
#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET                        0x0000c000
#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET                        0x0000f000
#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET                         0x00012000
#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET                        0x00015000
#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET                 0x00018000
#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET                          0x0001b000
#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET                        0x0001e000
#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET                 0x00021000
#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET                          0x00024000
#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET                       0x00027000
#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET                        0x0002a000
#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET                          0x00030000
#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET                          0x00033000

#define SEQ_MSIP_RBIST_TX_CH0_OFFSET                                 0x00000000
#define SEQ_MSIP_WL_DAC_CH0_OFFSET                                   0x00000180
#define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET                             0x00000190
#define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET                          0x00000200
#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET                          0x000002c0
#define SEQ_MSIP_WL_ADC_CH0_OFFSET                                   0x00000400
#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET                          0x00000434
#define SEQ_MSIP_MSIP_SHD_OTP_OFFSET                                 0x0000d000
#define SEQ_MSIP_MSIP_TMUX_OFFSET                                    0x0000d040
#define SEQ_MSIP_MSIP_OTP_OFFSET                                     0x0000d080
#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET                                0x0000d0b4
#define SEQ_MSIP_MSIP_CLKGEN_OFFSET                                  0x0000d100
#define SEQ_MSIP_MSIP_BIAS_OFFSET                                    0x0000e000
#define SEQ_MSIP_BBPLL_OFFSET                                        0x0000f000
#define SEQ_MSIP_WL_CLKGEN_OFFSET                                    0x0000f800
#define SEQ_MSIP_MSIP_DRM_REG_OFFSET                                 0x0000fc00

#define SEQ_WCSSDBG_WCSS_DBG_ROM_TABLE_OFFSET                        0x00000000
#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET                          0x00001000
#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET                             0x00002000
#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET                     0x00004000
#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET                      0x00005000
#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                     0x00006000
#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET                            0x00020000
#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET               0x00021000
#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET                                0x00022000
#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET                 0x00023000
#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET                              0x00024000
#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET                0x00025000
#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET                     0x00026000
#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET                     0x00028000
#define SEQ_WCSSDBG_TPDM_OFFSET                                      0x00029000
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000
#define SEQ_WCSSDBG_TPDA_OFFSET                                      0x0002a000
#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET                       0x0002b000
#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET                        0x0002c000
#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET                0x0002e000
#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET                0x0002f000
#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET                         0x00030000
#define SEQ_WCSSDBG_TRCCNTRS_OFFSET                                  0x00031000
#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET                   0x00034000
#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET                      0x00035000
#define SEQ_WCSSDBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET           0x00039000
#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET                             0x00040000
#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET                             0x00050000
#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET                    0x00050000
#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET      0x00054000
#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET          0x00055000
#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET             0x00056000
#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET                               0x000a1000

#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000

#define SEQ_PHYA_DBG_PHYA_NOC_OFFSET                                 0x00000000
#define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET                   0x00004000
#define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET                       0x00005000
#define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET                          0x00006000

#endif