reo_entrance_ring.h 18 KB

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  1. /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  2. *
  3. * Permission to use, copy, modify, and/or distribute this software for any
  4. * purpose with or without fee is hereby granted, provided that the above
  5. * copyright notice and this permission notice appear in all copies.
  6. *
  7. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  8. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  9. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14. */
  15. #ifndef _REO_ENTRANCE_RING_H_
  16. #define _REO_ENTRANCE_RING_H_
  17. #if !defined(__ASSEMBLER__)
  18. #endif
  19. #include "rx_mpdu_details.h"
  20. #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
  21. struct reo_entrance_ring {
  22. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  23. struct rx_mpdu_details reo_level_mpdu_frame_info;
  24. uint32_t rx_reo_queue_desc_addr_31_0 : 32;
  25. uint32_t rx_reo_queue_desc_addr_39_32 : 8,
  26. rounded_mpdu_byte_count : 14,
  27. reo_destination_indication : 5,
  28. frameless_bar : 1,
  29. reserved_5a : 4;
  30. uint32_t rxdma_push_reason : 2,
  31. rxdma_error_code : 5,
  32. mpdu_fragment_number : 4,
  33. sw_exception : 1,
  34. sw_exception_mpdu_delink : 1,
  35. sw_exception_destination_ring_valid : 1,
  36. sw_exception_destination_ring : 5,
  37. mpdu_sequence_number : 12,
  38. reserved_6a : 1;
  39. uint32_t phy_ppdu_id : 16,
  40. src_link_id : 3,
  41. reserved_7a : 1,
  42. ring_id : 8,
  43. looping_count : 4;
  44. #else
  45. struct rx_mpdu_details reo_level_mpdu_frame_info;
  46. uint32_t rx_reo_queue_desc_addr_31_0 : 32;
  47. uint32_t reserved_5a : 4,
  48. frameless_bar : 1,
  49. reo_destination_indication : 5,
  50. rounded_mpdu_byte_count : 14,
  51. rx_reo_queue_desc_addr_39_32 : 8;
  52. uint32_t reserved_6a : 1,
  53. mpdu_sequence_number : 12,
  54. sw_exception_destination_ring : 5,
  55. sw_exception_destination_ring_valid : 1,
  56. sw_exception_mpdu_delink : 1,
  57. sw_exception : 1,
  58. mpdu_fragment_number : 4,
  59. rxdma_error_code : 5,
  60. rxdma_push_reason : 2;
  61. uint32_t looping_count : 4,
  62. ring_id : 8,
  63. reserved_7a : 1,
  64. src_link_id : 3,
  65. phy_ppdu_id : 16;
  66. #endif
  67. };
  68. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
  69. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  70. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
  71. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  72. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
  73. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  74. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
  75. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  76. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
  77. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  78. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
  79. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
  80. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
  81. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
  82. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
  83. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
  84. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
  85. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
  86. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
  87. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
  88. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
  89. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
  90. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
  91. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
  92. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
  93. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
  94. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
  95. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
  96. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
  97. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
  98. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
  99. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
  100. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
  101. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
  102. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
  103. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
  104. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
  105. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
  106. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
  107. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
  108. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
  109. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
  110. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
  111. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
  112. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
  113. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
  114. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
  115. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
  116. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
  117. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
  118. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
  119. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
  120. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
  121. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
  122. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
  123. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
  124. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
  125. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
  126. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
  127. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
  128. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
  129. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
  130. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
  131. #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
  132. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
  133. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
  134. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
  135. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
  136. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
  137. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
  138. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
  139. #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
  140. #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
  141. #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8
  142. #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21
  143. #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
  144. #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014
  145. #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22
  146. #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26
  147. #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000
  148. #define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014
  149. #define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27
  150. #define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27
  151. #define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000
  152. #define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014
  153. #define REO_ENTRANCE_RING_RESERVED_5A_LSB 28
  154. #define REO_ENTRANCE_RING_RESERVED_5A_MSB 31
  155. #define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000
  156. #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018
  157. #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0
  158. #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1
  159. #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003
  160. #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018
  161. #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2
  162. #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6
  163. #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c
  164. #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
  165. #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7
  166. #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10
  167. #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
  168. #define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018
  169. #define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11
  170. #define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11
  171. #define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800
  172. #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
  173. #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12
  174. #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12
  175. #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
  176. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
  177. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
  178. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13
  179. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
  180. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
  181. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14
  182. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18
  183. #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
  184. #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018
  185. #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19
  186. #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30
  187. #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000
  188. #define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018
  189. #define REO_ENTRANCE_RING_RESERVED_6A_LSB 31
  190. #define REO_ENTRANCE_RING_RESERVED_6A_MSB 31
  191. #define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000
  192. #define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c
  193. #define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0
  194. #define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15
  195. #define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff
  196. #define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c
  197. #define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16
  198. #define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18
  199. #define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000
  200. #define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c
  201. #define REO_ENTRANCE_RING_RESERVED_7A_LSB 19
  202. #define REO_ENTRANCE_RING_RESERVED_7A_MSB 19
  203. #define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000
  204. #define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c
  205. #define REO_ENTRANCE_RING_RING_ID_LSB 20
  206. #define REO_ENTRANCE_RING_RING_ID_MSB 27
  207. #define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000
  208. #define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c
  209. #define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28
  210. #define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31
  211. #define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000
  212. #endif