mactx_phy_desc.h 27 KB

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  1. /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  2. *
  3. * Permission to use, copy, modify, and/or distribute this software for any
  4. * purpose with or without fee is hereby granted, provided that the above
  5. * copyright notice and this permission notice appear in all copies.
  6. *
  7. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  8. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  9. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14. */
  15. #ifndef _MACTX_PHY_DESC_H_
  16. #define _MACTX_PHY_DESC_H_
  17. #if !defined(__ASSEMBLER__)
  18. #endif
  19. #define NUM_OF_DWORDS_MACTX_PHY_DESC 4
  20. #define NUM_OF_QWORDS_MACTX_PHY_DESC 2
  21. struct mactx_phy_desc {
  22. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  23. uint32_t reserved_0a : 16,
  24. bf_type : 2,
  25. wait_sifs : 2,
  26. dot11b_preamble_type : 1,
  27. pkt_type : 4,
  28. su_or_mu : 2,
  29. mu_type : 1,
  30. bandwidth : 3,
  31. channel_capture : 1;
  32. uint32_t mcs : 4,
  33. global_ofdma_mimo_enable : 1,
  34. reserved_1a : 1,
  35. stbc : 1,
  36. dot11ax_su_extended : 1,
  37. dot11ax_trigger_frame_embedded : 1,
  38. tx_pwr_shared : 8,
  39. tx_pwr_unshared : 8,
  40. measure_power : 1,
  41. tpc_glut_self_cal : 1,
  42. back_to_back_transmission_expected : 1,
  43. heavy_clip_nss : 3,
  44. txbf_per_packet_no_csd_no_walsh : 1;
  45. uint32_t ndp : 2,
  46. ul_flag : 1,
  47. triggered : 1,
  48. ap_pkt_bw : 3,
  49. ru_position_start : 8,
  50. pcu_ppdu_setup_start_reason : 3,
  51. tlv_source : 1,
  52. reserved_2a : 2,
  53. nss : 3,
  54. stream_offset : 3,
  55. reserved_2b : 2,
  56. clpc_enable : 1,
  57. mu_ndp : 1,
  58. response_expected : 1;
  59. uint32_t rx_chain_mask : 8,
  60. rx_chain_mask_valid : 1,
  61. ant_sel_valid : 1,
  62. ant_sel : 1,
  63. cp_setting : 2,
  64. he_ppdu_subtype : 2,
  65. active_channel : 3,
  66. generate_phyrx_tx_start_timing : 1,
  67. ltf_size : 2,
  68. ru_size_updated_v2 : 4,
  69. reserved_3c : 1,
  70. u_sig_puncture_pattern_encoding : 6;
  71. #else
  72. uint32_t channel_capture : 1,
  73. bandwidth : 3,
  74. mu_type : 1,
  75. su_or_mu : 2,
  76. pkt_type : 4,
  77. dot11b_preamble_type : 1,
  78. wait_sifs : 2,
  79. bf_type : 2,
  80. reserved_0a : 16;
  81. uint32_t txbf_per_packet_no_csd_no_walsh : 1,
  82. heavy_clip_nss : 3,
  83. back_to_back_transmission_expected : 1,
  84. tpc_glut_self_cal : 1,
  85. measure_power : 1,
  86. tx_pwr_unshared : 8,
  87. tx_pwr_shared : 8,
  88. dot11ax_trigger_frame_embedded : 1,
  89. dot11ax_su_extended : 1,
  90. stbc : 1,
  91. reserved_1a : 1,
  92. global_ofdma_mimo_enable : 1,
  93. mcs : 4;
  94. uint32_t response_expected : 1,
  95. mu_ndp : 1,
  96. clpc_enable : 1,
  97. reserved_2b : 2,
  98. stream_offset : 3,
  99. nss : 3,
  100. reserved_2a : 2,
  101. tlv_source : 1,
  102. pcu_ppdu_setup_start_reason : 3,
  103. ru_position_start : 8,
  104. ap_pkt_bw : 3,
  105. triggered : 1,
  106. ul_flag : 1,
  107. ndp : 2;
  108. uint32_t u_sig_puncture_pattern_encoding : 6,
  109. reserved_3c : 1,
  110. ru_size_updated_v2 : 4,
  111. ltf_size : 2,
  112. generate_phyrx_tx_start_timing : 1,
  113. active_channel : 3,
  114. he_ppdu_subtype : 2,
  115. cp_setting : 2,
  116. ant_sel : 1,
  117. ant_sel_valid : 1,
  118. rx_chain_mask_valid : 1,
  119. rx_chain_mask : 8;
  120. #endif
  121. };
  122. #define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000
  123. #define MACTX_PHY_DESC_RESERVED_0A_LSB 0
  124. #define MACTX_PHY_DESC_RESERVED_0A_MSB 15
  125. #define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff
  126. #define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000
  127. #define MACTX_PHY_DESC_BF_TYPE_LSB 16
  128. #define MACTX_PHY_DESC_BF_TYPE_MSB 17
  129. #define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000
  130. #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000
  131. #define MACTX_PHY_DESC_WAIT_SIFS_LSB 18
  132. #define MACTX_PHY_DESC_WAIT_SIFS_MSB 19
  133. #define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000
  134. #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000
  135. #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20
  136. #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20
  137. #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000
  138. #define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000
  139. #define MACTX_PHY_DESC_PKT_TYPE_LSB 21
  140. #define MACTX_PHY_DESC_PKT_TYPE_MSB 24
  141. #define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000
  142. #define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000
  143. #define MACTX_PHY_DESC_SU_OR_MU_LSB 25
  144. #define MACTX_PHY_DESC_SU_OR_MU_MSB 26
  145. #define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000
  146. #define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000
  147. #define MACTX_PHY_DESC_MU_TYPE_LSB 27
  148. #define MACTX_PHY_DESC_MU_TYPE_MSB 27
  149. #define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000
  150. #define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000
  151. #define MACTX_PHY_DESC_BANDWIDTH_LSB 28
  152. #define MACTX_PHY_DESC_BANDWIDTH_MSB 30
  153. #define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000
  154. #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000
  155. #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31
  156. #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31
  157. #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000
  158. #define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000
  159. #define MACTX_PHY_DESC_MCS_LSB 32
  160. #define MACTX_PHY_DESC_MCS_MSB 35
  161. #define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000
  162. #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000
  163. #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36
  164. #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36
  165. #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000
  166. #define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000
  167. #define MACTX_PHY_DESC_RESERVED_1A_LSB 37
  168. #define MACTX_PHY_DESC_RESERVED_1A_MSB 37
  169. #define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000
  170. #define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000
  171. #define MACTX_PHY_DESC_STBC_LSB 38
  172. #define MACTX_PHY_DESC_STBC_MSB 38
  173. #define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000
  174. #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
  175. #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39
  176. #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39
  177. #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000
  178. #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000
  179. #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40
  180. #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40
  181. #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000
  182. #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000
  183. #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41
  184. #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48
  185. #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000
  186. #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000
  187. #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49
  188. #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56
  189. #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000
  190. #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000
  191. #define MACTX_PHY_DESC_MEASURE_POWER_LSB 57
  192. #define MACTX_PHY_DESC_MEASURE_POWER_MSB 57
  193. #define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000
  194. #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000
  195. #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58
  196. #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58
  197. #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000
  198. #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000
  199. #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59
  200. #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59
  201. #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000
  202. #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000
  203. #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60
  204. #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62
  205. #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000
  206. #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000
  207. #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63
  208. #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63
  209. #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000
  210. #define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008
  211. #define MACTX_PHY_DESC_NDP_LSB 0
  212. #define MACTX_PHY_DESC_NDP_MSB 1
  213. #define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003
  214. #define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008
  215. #define MACTX_PHY_DESC_UL_FLAG_LSB 2
  216. #define MACTX_PHY_DESC_UL_FLAG_MSB 2
  217. #define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004
  218. #define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008
  219. #define MACTX_PHY_DESC_TRIGGERED_LSB 3
  220. #define MACTX_PHY_DESC_TRIGGERED_MSB 3
  221. #define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008
  222. #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008
  223. #define MACTX_PHY_DESC_AP_PKT_BW_LSB 4
  224. #define MACTX_PHY_DESC_AP_PKT_BW_MSB 6
  225. #define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070
  226. #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008
  227. #define MACTX_PHY_DESC_RU_POSITION_START_LSB 7
  228. #define MACTX_PHY_DESC_RU_POSITION_START_MSB 14
  229. #define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80
  230. #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008
  231. #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15
  232. #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17
  233. #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000
  234. #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008
  235. #define MACTX_PHY_DESC_TLV_SOURCE_LSB 18
  236. #define MACTX_PHY_DESC_TLV_SOURCE_MSB 18
  237. #define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000
  238. #define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008
  239. #define MACTX_PHY_DESC_RESERVED_2A_LSB 19
  240. #define MACTX_PHY_DESC_RESERVED_2A_MSB 20
  241. #define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000
  242. #define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008
  243. #define MACTX_PHY_DESC_NSS_LSB 21
  244. #define MACTX_PHY_DESC_NSS_MSB 23
  245. #define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000
  246. #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008
  247. #define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24
  248. #define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26
  249. #define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000
  250. #define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008
  251. #define MACTX_PHY_DESC_RESERVED_2B_LSB 27
  252. #define MACTX_PHY_DESC_RESERVED_2B_MSB 28
  253. #define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000
  254. #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008
  255. #define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29
  256. #define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29
  257. #define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000
  258. #define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008
  259. #define MACTX_PHY_DESC_MU_NDP_LSB 30
  260. #define MACTX_PHY_DESC_MU_NDP_MSB 30
  261. #define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000
  262. #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008
  263. #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31
  264. #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31
  265. #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000
  266. #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008
  267. #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32
  268. #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39
  269. #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000
  270. #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008
  271. #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40
  272. #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40
  273. #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000
  274. #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008
  275. #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41
  276. #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41
  277. #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000
  278. #define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008
  279. #define MACTX_PHY_DESC_ANT_SEL_LSB 42
  280. #define MACTX_PHY_DESC_ANT_SEL_MSB 42
  281. #define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000
  282. #define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008
  283. #define MACTX_PHY_DESC_CP_SETTING_LSB 43
  284. #define MACTX_PHY_DESC_CP_SETTING_MSB 44
  285. #define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000
  286. #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008
  287. #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45
  288. #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46
  289. #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000
  290. #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008
  291. #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47
  292. #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49
  293. #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000
  294. #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008
  295. #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50
  296. #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50
  297. #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000
  298. #define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008
  299. #define MACTX_PHY_DESC_LTF_SIZE_LSB 51
  300. #define MACTX_PHY_DESC_LTF_SIZE_MSB 52
  301. #define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000
  302. #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008
  303. #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53
  304. #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56
  305. #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000
  306. #define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008
  307. #define MACTX_PHY_DESC_RESERVED_3C_LSB 57
  308. #define MACTX_PHY_DESC_RESERVED_3C_MSB 57
  309. #define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000
  310. #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008
  311. #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
  312. #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
  313. #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
  314. #endif