rx_msdu_end.h 84 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574
  1. /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
  2. *
  3. * Permission to use, copy, modify, and/or distribute this software for any
  4. * purpose with or without fee is hereby granted, provided that the above
  5. * copyright notice and this permission notice appear in all copies.
  6. *
  7. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  8. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  9. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14. */
  15. #ifndef _RX_MSDU_END_H_
  16. #define _RX_MSDU_END_H_
  17. #if !defined(__ASSEMBLER__)
  18. #endif
  19. #define NUM_OF_DWORDS_RX_MSDU_END 32
  20. #define NUM_OF_QWORDS_RX_MSDU_END 16
  21. struct rx_msdu_end {
  22. #ifndef BIG_ENDIAN_HOST
  23. uint32_t rxpcu_mpdu_filter_in_category : 2,
  24. sw_frame_group_id : 7,
  25. reserved_0 : 7,
  26. phy_ppdu_id : 16;
  27. uint32_t ip_hdr_chksum : 16,
  28. reported_mpdu_length : 14,
  29. reserved_1a : 2;
  30. uint32_t reserved_2a : 8,
  31. cce_super_rule : 6,
  32. cce_classify_not_done_truncate : 1,
  33. cce_classify_not_done_cce_dis : 1,
  34. cumulative_l3_checksum : 16;
  35. uint32_t rule_indication_31_0 : 32;
  36. uint32_t ipv6_options_crc : 32;
  37. uint32_t da_offset : 6,
  38. sa_offset : 6,
  39. da_offset_valid : 1,
  40. sa_offset_valid : 1,
  41. reserved_5a : 2,
  42. l3_type : 16;
  43. uint32_t rule_indication_63_32 : 32;
  44. uint32_t tcp_seq_number : 32;
  45. uint32_t tcp_ack_number : 32;
  46. uint32_t tcp_flag : 9,
  47. lro_eligible : 1,
  48. reserved_9a : 6,
  49. window_size : 16;
  50. uint32_t sa_sw_peer_id : 16,
  51. sa_idx_timeout : 1,
  52. da_idx_timeout : 1,
  53. to_ds : 1,
  54. tid : 4,
  55. sa_is_valid : 1,
  56. da_is_valid : 1,
  57. da_is_mcbc : 1,
  58. l3_header_padding : 2,
  59. first_msdu : 1,
  60. last_msdu : 1,
  61. fr_ds : 1,
  62. ip_chksum_fail_copy : 1;
  63. uint32_t sa_idx : 16,
  64. da_idx_or_sw_peer_id : 16;
  65. uint32_t msdu_drop : 1,
  66. reo_destination_indication : 5,
  67. flow_idx : 20,
  68. use_ppe : 1,
  69. mesh_sta : 2,
  70. vlan_ctag_stripped : 1,
  71. vlan_stag_stripped : 1,
  72. fragment_flag : 1;
  73. uint32_t fse_metadata : 32;
  74. uint32_t cce_metadata : 16,
  75. tcp_udp_chksum : 16;
  76. uint32_t aggregation_count : 8,
  77. flow_aggregation_continuation : 1,
  78. fisa_timeout : 1,
  79. tcp_udp_chksum_fail_copy : 1,
  80. msdu_limit_error : 1,
  81. flow_idx_timeout : 1,
  82. flow_idx_invalid : 1,
  83. cce_match : 1,
  84. amsdu_parser_error : 1,
  85. cumulative_ip_length : 16;
  86. uint32_t key_id_octet : 8,
  87. reserved_16a : 24;
  88. uint32_t reserved_17a : 6,
  89. service_code : 9,
  90. priority_valid : 1,
  91. intra_bss : 1,
  92. dest_chip_id : 2,
  93. multicast_echo : 1,
  94. wds_learning_event : 1,
  95. wds_roaming_event : 1,
  96. wds_keep_alive_event : 1,
  97. reserved_17b : 9;
  98. uint32_t msdu_length : 14,
  99. stbc : 1,
  100. ipsec_esp : 1,
  101. l3_offset : 7,
  102. ipsec_ah : 1,
  103. l4_offset : 8;
  104. uint32_t msdu_number : 8,
  105. decap_format : 2,
  106. ipv4_proto : 1,
  107. ipv6_proto : 1,
  108. tcp_proto : 1,
  109. udp_proto : 1,
  110. ip_frag : 1,
  111. tcp_only_ack : 1,
  112. da_is_bcast_mcast : 1,
  113. toeplitz_hash_sel : 2,
  114. ip_fixed_header_valid : 1,
  115. ip_extn_header_valid : 1,
  116. tcp_udp_header_valid : 1,
  117. mesh_control_present : 1,
  118. ldpc : 1,
  119. ip4_protocol_ip6_next_header : 8;
  120. uint32_t vlan_ctag_ci : 16,
  121. vlan_stag_ci : 16;
  122. uint32_t peer_meta_data : 32;
  123. uint32_t user_rssi : 8,
  124. pkt_type : 4,
  125. sgi : 2,
  126. rate_mcs : 4,
  127. receive_bandwidth : 3,
  128. reception_type : 3,
  129. mimo_ss_bitmap : 7,
  130. msdu_done_copy : 1;
  131. uint32_t flow_id_toeplitz : 32;
  132. uint32_t ppdu_start_timestamp_63_32 : 32;
  133. uint32_t sw_phy_meta_data : 32;
  134. uint32_t ppdu_start_timestamp_31_0 : 32;
  135. uint32_t toeplitz_hash_2_or_4 : 32;
  136. uint32_t reserved_28a : 16,
  137. sa_15_0 : 16;
  138. uint32_t sa_47_16 : 32;
  139. uint32_t first_mpdu : 1,
  140. reserved_30a : 1,
  141. mcast_bcast : 1,
  142. ast_index_not_found : 1,
  143. ast_index_timeout : 1,
  144. power_mgmt : 1,
  145. non_qos : 1,
  146. null_data : 1,
  147. mgmt_type : 1,
  148. ctrl_type : 1,
  149. more_data : 1,
  150. eosp : 1,
  151. a_msdu_error : 1,
  152. reserved_30b : 1,
  153. order : 1,
  154. wifi_parser_error : 1,
  155. overflow_err : 1,
  156. msdu_length_err : 1,
  157. tcp_udp_chksum_fail : 1,
  158. ip_chksum_fail : 1,
  159. sa_idx_invalid : 1,
  160. da_idx_invalid : 1,
  161. amsdu_addr_mismatch : 1,
  162. rx_in_tx_decrypt_byp : 1,
  163. encrypt_required : 1,
  164. directed : 1,
  165. buffer_fragment : 1,
  166. mpdu_length_err : 1,
  167. tkip_mic_err : 1,
  168. decrypt_err : 1,
  169. unencrypted_frame_err : 1,
  170. fcs_err : 1;
  171. uint32_t reserved_31a : 10,
  172. decrypt_status_code : 3,
  173. rx_bitmap_not_updated : 1,
  174. reserved_31b : 17,
  175. msdu_done : 1;
  176. #else
  177. uint32_t phy_ppdu_id : 16,
  178. reserved_0 : 7,
  179. sw_frame_group_id : 7,
  180. rxpcu_mpdu_filter_in_category : 2;
  181. uint32_t reserved_1a : 2,
  182. reported_mpdu_length : 14,
  183. ip_hdr_chksum : 16;
  184. uint32_t cumulative_l3_checksum : 16,
  185. cce_classify_not_done_cce_dis : 1,
  186. cce_classify_not_done_truncate : 1,
  187. cce_super_rule : 6,
  188. reserved_2a : 8;
  189. uint32_t rule_indication_31_0 : 32;
  190. uint32_t ipv6_options_crc : 32;
  191. uint32_t l3_type : 16,
  192. reserved_5a : 2,
  193. sa_offset_valid : 1,
  194. da_offset_valid : 1,
  195. sa_offset : 6,
  196. da_offset : 6;
  197. uint32_t rule_indication_63_32 : 32;
  198. uint32_t tcp_seq_number : 32;
  199. uint32_t tcp_ack_number : 32;
  200. uint32_t window_size : 16,
  201. reserved_9a : 6,
  202. lro_eligible : 1,
  203. tcp_flag : 9;
  204. uint32_t ip_chksum_fail_copy : 1,
  205. fr_ds : 1,
  206. last_msdu : 1,
  207. first_msdu : 1,
  208. l3_header_padding : 2,
  209. da_is_mcbc : 1,
  210. da_is_valid : 1,
  211. sa_is_valid : 1,
  212. tid : 4,
  213. to_ds : 1,
  214. da_idx_timeout : 1,
  215. sa_idx_timeout : 1,
  216. sa_sw_peer_id : 16;
  217. uint32_t da_idx_or_sw_peer_id : 16,
  218. sa_idx : 16;
  219. uint32_t fragment_flag : 1,
  220. vlan_stag_stripped : 1,
  221. vlan_ctag_stripped : 1,
  222. mesh_sta : 2,
  223. use_ppe : 1,
  224. flow_idx : 20,
  225. reo_destination_indication : 5,
  226. msdu_drop : 1;
  227. uint32_t fse_metadata : 32;
  228. uint32_t tcp_udp_chksum : 16,
  229. cce_metadata : 16;
  230. uint32_t cumulative_ip_length : 16,
  231. amsdu_parser_error : 1,
  232. cce_match : 1,
  233. flow_idx_invalid : 1,
  234. flow_idx_timeout : 1,
  235. msdu_limit_error : 1,
  236. tcp_udp_chksum_fail_copy : 1,
  237. fisa_timeout : 1,
  238. flow_aggregation_continuation : 1,
  239. aggregation_count : 8;
  240. uint32_t reserved_16a : 24,
  241. key_id_octet : 8;
  242. uint32_t reserved_17b : 9,
  243. wds_keep_alive_event : 1,
  244. wds_roaming_event : 1,
  245. wds_learning_event : 1,
  246. multicast_echo : 1,
  247. dest_chip_id : 2,
  248. intra_bss : 1,
  249. priority_valid : 1,
  250. service_code : 9,
  251. reserved_17a : 6;
  252. uint32_t l4_offset : 8,
  253. ipsec_ah : 1,
  254. l3_offset : 7,
  255. ipsec_esp : 1,
  256. stbc : 1,
  257. msdu_length : 14;
  258. uint32_t ip4_protocol_ip6_next_header : 8,
  259. ldpc : 1,
  260. mesh_control_present : 1,
  261. tcp_udp_header_valid : 1,
  262. ip_extn_header_valid : 1,
  263. ip_fixed_header_valid : 1,
  264. toeplitz_hash_sel : 2,
  265. da_is_bcast_mcast : 1,
  266. tcp_only_ack : 1,
  267. ip_frag : 1,
  268. udp_proto : 1,
  269. tcp_proto : 1,
  270. ipv6_proto : 1,
  271. ipv4_proto : 1,
  272. decap_format : 2,
  273. msdu_number : 8;
  274. uint32_t vlan_stag_ci : 16,
  275. vlan_ctag_ci : 16;
  276. uint32_t peer_meta_data : 32;
  277. uint32_t msdu_done_copy : 1,
  278. mimo_ss_bitmap : 7,
  279. reception_type : 3,
  280. receive_bandwidth : 3,
  281. rate_mcs : 4,
  282. sgi : 2,
  283. pkt_type : 4,
  284. user_rssi : 8;
  285. uint32_t flow_id_toeplitz : 32;
  286. uint32_t ppdu_start_timestamp_63_32 : 32;
  287. uint32_t sw_phy_meta_data : 32;
  288. uint32_t ppdu_start_timestamp_31_0 : 32;
  289. uint32_t toeplitz_hash_2_or_4 : 32;
  290. uint32_t sa_15_0 : 16,
  291. reserved_28a : 16;
  292. uint32_t sa_47_16 : 32;
  293. uint32_t fcs_err : 1,
  294. unencrypted_frame_err : 1,
  295. decrypt_err : 1,
  296. tkip_mic_err : 1,
  297. mpdu_length_err : 1,
  298. buffer_fragment : 1,
  299. directed : 1,
  300. encrypt_required : 1,
  301. rx_in_tx_decrypt_byp : 1,
  302. amsdu_addr_mismatch : 1,
  303. da_idx_invalid : 1,
  304. sa_idx_invalid : 1,
  305. ip_chksum_fail : 1,
  306. tcp_udp_chksum_fail : 1,
  307. msdu_length_err : 1,
  308. overflow_err : 1,
  309. wifi_parser_error : 1,
  310. order : 1,
  311. reserved_30b : 1,
  312. a_msdu_error : 1,
  313. eosp : 1,
  314. more_data : 1,
  315. ctrl_type : 1,
  316. mgmt_type : 1,
  317. null_data : 1,
  318. non_qos : 1,
  319. power_mgmt : 1,
  320. ast_index_timeout : 1,
  321. ast_index_not_found : 1,
  322. mcast_bcast : 1,
  323. reserved_30a : 1,
  324. first_mpdu : 1;
  325. uint32_t msdu_done : 1,
  326. reserved_31b : 17,
  327. rx_bitmap_not_updated : 1,
  328. decrypt_status_code : 3,
  329. reserved_31a : 10;
  330. #endif
  331. };
  332. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
  333. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
  334. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
  335. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
  336. #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
  337. #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2
  338. #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8
  339. #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
  340. #define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000
  341. #define RX_MSDU_END_RESERVED_0_LSB 9
  342. #define RX_MSDU_END_RESERVED_0_MSB 15
  343. #define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00
  344. #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000
  345. #define RX_MSDU_END_PHY_PPDU_ID_LSB 16
  346. #define RX_MSDU_END_PHY_PPDU_ID_MSB 31
  347. #define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000
  348. #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000
  349. #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32
  350. #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47
  351. #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000
  352. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000
  353. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48
  354. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61
  355. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000
  356. #define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000
  357. #define RX_MSDU_END_RESERVED_1A_LSB 62
  358. #define RX_MSDU_END_RESERVED_1A_MSB 63
  359. #define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000
  360. #define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008
  361. #define RX_MSDU_END_RESERVED_2A_LSB 0
  362. #define RX_MSDU_END_RESERVED_2A_MSB 7
  363. #define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff
  364. #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008
  365. #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8
  366. #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13
  367. #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00
  368. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008
  369. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14
  370. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14
  371. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000
  372. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008
  373. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15
  374. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15
  375. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000
  376. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008
  377. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16
  378. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31
  379. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000
  380. #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008
  381. #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32
  382. #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63
  383. #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000
  384. #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010
  385. #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0
  386. #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31
  387. #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff
  388. #define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010
  389. #define RX_MSDU_END_DA_OFFSET_LSB 32
  390. #define RX_MSDU_END_DA_OFFSET_MSB 37
  391. #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000
  392. #define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010
  393. #define RX_MSDU_END_SA_OFFSET_LSB 38
  394. #define RX_MSDU_END_SA_OFFSET_MSB 43
  395. #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000
  396. #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010
  397. #define RX_MSDU_END_DA_OFFSET_VALID_LSB 44
  398. #define RX_MSDU_END_DA_OFFSET_VALID_MSB 44
  399. #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000
  400. #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010
  401. #define RX_MSDU_END_SA_OFFSET_VALID_LSB 45
  402. #define RX_MSDU_END_SA_OFFSET_VALID_MSB 45
  403. #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000
  404. #define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010
  405. #define RX_MSDU_END_RESERVED_5A_LSB 46
  406. #define RX_MSDU_END_RESERVED_5A_MSB 47
  407. #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000
  408. #define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010
  409. #define RX_MSDU_END_L3_TYPE_LSB 48
  410. #define RX_MSDU_END_L3_TYPE_MSB 63
  411. #define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000
  412. #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018
  413. #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0
  414. #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31
  415. #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff
  416. #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018
  417. #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32
  418. #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63
  419. #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000
  420. #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020
  421. #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0
  422. #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31
  423. #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff
  424. #define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020
  425. #define RX_MSDU_END_TCP_FLAG_LSB 32
  426. #define RX_MSDU_END_TCP_FLAG_MSB 40
  427. #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000
  428. #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020
  429. #define RX_MSDU_END_LRO_ELIGIBLE_LSB 41
  430. #define RX_MSDU_END_LRO_ELIGIBLE_MSB 41
  431. #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000
  432. #define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020
  433. #define RX_MSDU_END_RESERVED_9A_LSB 42
  434. #define RX_MSDU_END_RESERVED_9A_MSB 47
  435. #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000
  436. #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020
  437. #define RX_MSDU_END_WINDOW_SIZE_LSB 48
  438. #define RX_MSDU_END_WINDOW_SIZE_MSB 63
  439. #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000
  440. #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028
  441. #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0
  442. #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15
  443. #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff
  444. #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028
  445. #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16
  446. #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16
  447. #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000
  448. #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028
  449. #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17
  450. #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17
  451. #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000
  452. #define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028
  453. #define RX_MSDU_END_TO_DS_LSB 18
  454. #define RX_MSDU_END_TO_DS_MSB 18
  455. #define RX_MSDU_END_TO_DS_MASK 0x0000000000040000
  456. #define RX_MSDU_END_TID_OFFSET 0x0000000000000028
  457. #define RX_MSDU_END_TID_LSB 19
  458. #define RX_MSDU_END_TID_MSB 22
  459. #define RX_MSDU_END_TID_MASK 0x0000000000780000
  460. #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028
  461. #define RX_MSDU_END_SA_IS_VALID_LSB 23
  462. #define RX_MSDU_END_SA_IS_VALID_MSB 23
  463. #define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000
  464. #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028
  465. #define RX_MSDU_END_DA_IS_VALID_LSB 24
  466. #define RX_MSDU_END_DA_IS_VALID_MSB 24
  467. #define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000
  468. #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028
  469. #define RX_MSDU_END_DA_IS_MCBC_LSB 25
  470. #define RX_MSDU_END_DA_IS_MCBC_MSB 25
  471. #define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000
  472. #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028
  473. #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26
  474. #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27
  475. #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000
  476. #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028
  477. #define RX_MSDU_END_FIRST_MSDU_LSB 28
  478. #define RX_MSDU_END_FIRST_MSDU_MSB 28
  479. #define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000
  480. #define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028
  481. #define RX_MSDU_END_LAST_MSDU_LSB 29
  482. #define RX_MSDU_END_LAST_MSDU_MSB 29
  483. #define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000
  484. #define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028
  485. #define RX_MSDU_END_FR_DS_LSB 30
  486. #define RX_MSDU_END_FR_DS_MSB 30
  487. #define RX_MSDU_END_FR_DS_MASK 0x0000000040000000
  488. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028
  489. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31
  490. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31
  491. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000
  492. #define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028
  493. #define RX_MSDU_END_SA_IDX_LSB 32
  494. #define RX_MSDU_END_SA_IDX_MSB 47
  495. #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000
  496. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028
  497. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48
  498. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63
  499. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000
  500. #define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030
  501. #define RX_MSDU_END_MSDU_DROP_LSB 0
  502. #define RX_MSDU_END_MSDU_DROP_MSB 0
  503. #define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001
  504. #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030
  505. #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1
  506. #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5
  507. #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e
  508. #define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030
  509. #define RX_MSDU_END_FLOW_IDX_LSB 6
  510. #define RX_MSDU_END_FLOW_IDX_MSB 25
  511. #define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0
  512. #define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030
  513. #define RX_MSDU_END_USE_PPE_LSB 26
  514. #define RX_MSDU_END_USE_PPE_MSB 26
  515. #define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000
  516. #define RX_MSDU_END_MESH_STA_OFFSET 0x0000000000000030
  517. #define RX_MSDU_END_MESH_STA_LSB 27
  518. #define RX_MSDU_END_MESH_STA_MSB 28
  519. #define RX_MSDU_END_MESH_STA_MASK 0x0000000018000000
  520. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030
  521. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29
  522. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29
  523. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000
  524. #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030
  525. #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30
  526. #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30
  527. #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000
  528. #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030
  529. #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31
  530. #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31
  531. #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000
  532. #define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030
  533. #define RX_MSDU_END_FSE_METADATA_LSB 32
  534. #define RX_MSDU_END_FSE_METADATA_MSB 63
  535. #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000
  536. #define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038
  537. #define RX_MSDU_END_CCE_METADATA_LSB 0
  538. #define RX_MSDU_END_CCE_METADATA_MSB 15
  539. #define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff
  540. #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038
  541. #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16
  542. #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31
  543. #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000
  544. #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038
  545. #define RX_MSDU_END_AGGREGATION_COUNT_LSB 32
  546. #define RX_MSDU_END_AGGREGATION_COUNT_MSB 39
  547. #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000
  548. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038
  549. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40
  550. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40
  551. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000
  552. #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038
  553. #define RX_MSDU_END_FISA_TIMEOUT_LSB 41
  554. #define RX_MSDU_END_FISA_TIMEOUT_MSB 41
  555. #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000
  556. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038
  557. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42
  558. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42
  559. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000
  560. #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038
  561. #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43
  562. #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43
  563. #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000
  564. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038
  565. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44
  566. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44
  567. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000
  568. #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038
  569. #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45
  570. #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45
  571. #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000
  572. #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038
  573. #define RX_MSDU_END_CCE_MATCH_LSB 46
  574. #define RX_MSDU_END_CCE_MATCH_MSB 46
  575. #define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000
  576. #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038
  577. #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47
  578. #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47
  579. #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000
  580. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038
  581. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48
  582. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63
  583. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000
  584. #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040
  585. #define RX_MSDU_END_KEY_ID_OCTET_LSB 0
  586. #define RX_MSDU_END_KEY_ID_OCTET_MSB 7
  587. #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff
  588. #define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040
  589. #define RX_MSDU_END_RESERVED_16A_LSB 8
  590. #define RX_MSDU_END_RESERVED_16A_MSB 31
  591. #define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00
  592. #define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040
  593. #define RX_MSDU_END_RESERVED_17A_LSB 32
  594. #define RX_MSDU_END_RESERVED_17A_MSB 37
  595. #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000
  596. #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040
  597. #define RX_MSDU_END_SERVICE_CODE_LSB 38
  598. #define RX_MSDU_END_SERVICE_CODE_MSB 46
  599. #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000
  600. #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040
  601. #define RX_MSDU_END_PRIORITY_VALID_LSB 47
  602. #define RX_MSDU_END_PRIORITY_VALID_MSB 47
  603. #define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000
  604. #define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040
  605. #define RX_MSDU_END_INTRA_BSS_LSB 48
  606. #define RX_MSDU_END_INTRA_BSS_MSB 48
  607. #define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000
  608. #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040
  609. #define RX_MSDU_END_DEST_CHIP_ID_LSB 49
  610. #define RX_MSDU_END_DEST_CHIP_ID_MSB 50
  611. #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000
  612. #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040
  613. #define RX_MSDU_END_MULTICAST_ECHO_LSB 51
  614. #define RX_MSDU_END_MULTICAST_ECHO_MSB 51
  615. #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000
  616. #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040
  617. #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52
  618. #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52
  619. #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000
  620. #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040
  621. #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53
  622. #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53
  623. #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000
  624. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040
  625. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54
  626. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54
  627. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000
  628. #define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040
  629. #define RX_MSDU_END_RESERVED_17B_LSB 55
  630. #define RX_MSDU_END_RESERVED_17B_MSB 63
  631. #define RX_MSDU_END_RESERVED_17B_MASK 0xff80000000000000
  632. #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048
  633. #define RX_MSDU_END_MSDU_LENGTH_LSB 0
  634. #define RX_MSDU_END_MSDU_LENGTH_MSB 13
  635. #define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff
  636. #define RX_MSDU_END_STBC_OFFSET 0x0000000000000048
  637. #define RX_MSDU_END_STBC_LSB 14
  638. #define RX_MSDU_END_STBC_MSB 14
  639. #define RX_MSDU_END_STBC_MASK 0x0000000000004000
  640. #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048
  641. #define RX_MSDU_END_IPSEC_ESP_LSB 15
  642. #define RX_MSDU_END_IPSEC_ESP_MSB 15
  643. #define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000
  644. #define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048
  645. #define RX_MSDU_END_L3_OFFSET_LSB 16
  646. #define RX_MSDU_END_L3_OFFSET_MSB 22
  647. #define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000
  648. #define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048
  649. #define RX_MSDU_END_IPSEC_AH_LSB 23
  650. #define RX_MSDU_END_IPSEC_AH_MSB 23
  651. #define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000
  652. #define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048
  653. #define RX_MSDU_END_L4_OFFSET_LSB 24
  654. #define RX_MSDU_END_L4_OFFSET_MSB 31
  655. #define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000
  656. #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048
  657. #define RX_MSDU_END_MSDU_NUMBER_LSB 32
  658. #define RX_MSDU_END_MSDU_NUMBER_MSB 39
  659. #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000
  660. #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048
  661. #define RX_MSDU_END_DECAP_FORMAT_LSB 40
  662. #define RX_MSDU_END_DECAP_FORMAT_MSB 41
  663. #define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000
  664. #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048
  665. #define RX_MSDU_END_IPV4_PROTO_LSB 42
  666. #define RX_MSDU_END_IPV4_PROTO_MSB 42
  667. #define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000
  668. #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048
  669. #define RX_MSDU_END_IPV6_PROTO_LSB 43
  670. #define RX_MSDU_END_IPV6_PROTO_MSB 43
  671. #define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000
  672. #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048
  673. #define RX_MSDU_END_TCP_PROTO_LSB 44
  674. #define RX_MSDU_END_TCP_PROTO_MSB 44
  675. #define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000
  676. #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048
  677. #define RX_MSDU_END_UDP_PROTO_LSB 45
  678. #define RX_MSDU_END_UDP_PROTO_MSB 45
  679. #define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000
  680. #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048
  681. #define RX_MSDU_END_IP_FRAG_LSB 46
  682. #define RX_MSDU_END_IP_FRAG_MSB 46
  683. #define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000
  684. #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048
  685. #define RX_MSDU_END_TCP_ONLY_ACK_LSB 47
  686. #define RX_MSDU_END_TCP_ONLY_ACK_MSB 47
  687. #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000
  688. #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048
  689. #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48
  690. #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48
  691. #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000
  692. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048
  693. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49
  694. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50
  695. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000
  696. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048
  697. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51
  698. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51
  699. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000
  700. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048
  701. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52
  702. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52
  703. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000
  704. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048
  705. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53
  706. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53
  707. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000
  708. #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048
  709. #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54
  710. #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54
  711. #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000
  712. #define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048
  713. #define RX_MSDU_END_LDPC_LSB 55
  714. #define RX_MSDU_END_LDPC_MSB 55
  715. #define RX_MSDU_END_LDPC_MASK 0x0080000000000000
  716. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048
  717. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56
  718. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63
  719. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000
  720. #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050
  721. #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0
  722. #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15
  723. #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff
  724. #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050
  725. #define RX_MSDU_END_VLAN_STAG_CI_LSB 16
  726. #define RX_MSDU_END_VLAN_STAG_CI_MSB 31
  727. #define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000
  728. #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050
  729. #define RX_MSDU_END_PEER_META_DATA_LSB 32
  730. #define RX_MSDU_END_PEER_META_DATA_MSB 63
  731. #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000
  732. #define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058
  733. #define RX_MSDU_END_USER_RSSI_LSB 0
  734. #define RX_MSDU_END_USER_RSSI_MSB 7
  735. #define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff
  736. #define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058
  737. #define RX_MSDU_END_PKT_TYPE_LSB 8
  738. #define RX_MSDU_END_PKT_TYPE_MSB 11
  739. #define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00
  740. #define RX_MSDU_END_SGI_OFFSET 0x0000000000000058
  741. #define RX_MSDU_END_SGI_LSB 12
  742. #define RX_MSDU_END_SGI_MSB 13
  743. #define RX_MSDU_END_SGI_MASK 0x0000000000003000
  744. #define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058
  745. #define RX_MSDU_END_RATE_MCS_LSB 14
  746. #define RX_MSDU_END_RATE_MCS_MSB 17
  747. #define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000
  748. #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058
  749. #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18
  750. #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20
  751. #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000
  752. #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058
  753. #define RX_MSDU_END_RECEPTION_TYPE_LSB 21
  754. #define RX_MSDU_END_RECEPTION_TYPE_MSB 23
  755. #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000
  756. #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058
  757. #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24
  758. #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30
  759. #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000
  760. #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058
  761. #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31
  762. #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31
  763. #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000
  764. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058
  765. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32
  766. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63
  767. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000
  768. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060
  769. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0
  770. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31
  771. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff
  772. #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060
  773. #define RX_MSDU_END_SW_PHY_META_DATA_LSB 32
  774. #define RX_MSDU_END_SW_PHY_META_DATA_MSB 63
  775. #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000
  776. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068
  777. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0
  778. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31
  779. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff
  780. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068
  781. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32
  782. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63
  783. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000
  784. #define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070
  785. #define RX_MSDU_END_RESERVED_28A_LSB 0
  786. #define RX_MSDU_END_RESERVED_28A_MSB 15
  787. #define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff
  788. #define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070
  789. #define RX_MSDU_END_SA_15_0_LSB 16
  790. #define RX_MSDU_END_SA_15_0_MSB 31
  791. #define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000
  792. #define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070
  793. #define RX_MSDU_END_SA_47_16_LSB 32
  794. #define RX_MSDU_END_SA_47_16_MSB 63
  795. #define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000
  796. #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078
  797. #define RX_MSDU_END_FIRST_MPDU_LSB 0
  798. #define RX_MSDU_END_FIRST_MPDU_MSB 0
  799. #define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001
  800. #define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078
  801. #define RX_MSDU_END_RESERVED_30A_LSB 1
  802. #define RX_MSDU_END_RESERVED_30A_MSB 1
  803. #define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002
  804. #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078
  805. #define RX_MSDU_END_MCAST_BCAST_LSB 2
  806. #define RX_MSDU_END_MCAST_BCAST_MSB 2
  807. #define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004
  808. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078
  809. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3
  810. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3
  811. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008
  812. #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078
  813. #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4
  814. #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4
  815. #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010
  816. #define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078
  817. #define RX_MSDU_END_POWER_MGMT_LSB 5
  818. #define RX_MSDU_END_POWER_MGMT_MSB 5
  819. #define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020
  820. #define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078
  821. #define RX_MSDU_END_NON_QOS_LSB 6
  822. #define RX_MSDU_END_NON_QOS_MSB 6
  823. #define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040
  824. #define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078
  825. #define RX_MSDU_END_NULL_DATA_LSB 7
  826. #define RX_MSDU_END_NULL_DATA_MSB 7
  827. #define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080
  828. #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078
  829. #define RX_MSDU_END_MGMT_TYPE_LSB 8
  830. #define RX_MSDU_END_MGMT_TYPE_MSB 8
  831. #define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100
  832. #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078
  833. #define RX_MSDU_END_CTRL_TYPE_LSB 9
  834. #define RX_MSDU_END_CTRL_TYPE_MSB 9
  835. #define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200
  836. #define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078
  837. #define RX_MSDU_END_MORE_DATA_LSB 10
  838. #define RX_MSDU_END_MORE_DATA_MSB 10
  839. #define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400
  840. #define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078
  841. #define RX_MSDU_END_EOSP_LSB 11
  842. #define RX_MSDU_END_EOSP_MSB 11
  843. #define RX_MSDU_END_EOSP_MASK 0x0000000000000800
  844. #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078
  845. #define RX_MSDU_END_A_MSDU_ERROR_LSB 12
  846. #define RX_MSDU_END_A_MSDU_ERROR_MSB 12
  847. #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000
  848. #define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078
  849. #define RX_MSDU_END_RESERVED_30B_LSB 13
  850. #define RX_MSDU_END_RESERVED_30B_MSB 13
  851. #define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000
  852. #define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078
  853. #define RX_MSDU_END_ORDER_LSB 14
  854. #define RX_MSDU_END_ORDER_MSB 14
  855. #define RX_MSDU_END_ORDER_MASK 0x0000000000004000
  856. #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078
  857. #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15
  858. #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15
  859. #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000
  860. #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078
  861. #define RX_MSDU_END_OVERFLOW_ERR_LSB 16
  862. #define RX_MSDU_END_OVERFLOW_ERR_MSB 16
  863. #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000
  864. #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078
  865. #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17
  866. #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17
  867. #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000
  868. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078
  869. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18
  870. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18
  871. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000
  872. #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078
  873. #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19
  874. #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19
  875. #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000
  876. #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078
  877. #define RX_MSDU_END_SA_IDX_INVALID_LSB 20
  878. #define RX_MSDU_END_SA_IDX_INVALID_MSB 20
  879. #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000
  880. #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078
  881. #define RX_MSDU_END_DA_IDX_INVALID_LSB 21
  882. #define RX_MSDU_END_DA_IDX_INVALID_MSB 21
  883. #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000
  884. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078
  885. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22
  886. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22
  887. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000
  888. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078
  889. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23
  890. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23
  891. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000
  892. #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078
  893. #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24
  894. #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24
  895. #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000
  896. #define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078
  897. #define RX_MSDU_END_DIRECTED_LSB 25
  898. #define RX_MSDU_END_DIRECTED_MSB 25
  899. #define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000
  900. #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078
  901. #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26
  902. #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26
  903. #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000
  904. #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078
  905. #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27
  906. #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27
  907. #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000
  908. #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078
  909. #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28
  910. #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28
  911. #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000
  912. #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078
  913. #define RX_MSDU_END_DECRYPT_ERR_LSB 29
  914. #define RX_MSDU_END_DECRYPT_ERR_MSB 29
  915. #define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000
  916. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078
  917. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30
  918. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30
  919. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000
  920. #define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078
  921. #define RX_MSDU_END_FCS_ERR_LSB 31
  922. #define RX_MSDU_END_FCS_ERR_MSB 31
  923. #define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000
  924. #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078
  925. #define RX_MSDU_END_RESERVED_31A_LSB 32
  926. #define RX_MSDU_END_RESERVED_31A_MSB 41
  927. #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000
  928. #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078
  929. #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42
  930. #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44
  931. #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000
  932. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078
  933. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45
  934. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45
  935. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000
  936. #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078
  937. #define RX_MSDU_END_RESERVED_31B_LSB 46
  938. #define RX_MSDU_END_RESERVED_31B_MSB 62
  939. #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000
  940. #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078
  941. #define RX_MSDU_END_MSDU_DONE_LSB 63
  942. #define RX_MSDU_END_MSDU_DONE_MSB 63
  943. #define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000
  944. #endif