dsi_display.c 218 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define MAX_TE_RECHECKS 5
  28. #define DSI_CLOCK_BITRATE_RADIX 10
  29. #define MAX_TE_SOURCE_ID 2
  30. #define SEC_PANEL_NAME_MAX_LEN 256
  31. #define DSI_MODE_MATCH_ACTIVE_TIMINGS (1 << 0)
  32. #define DSI_MODE_MATCH_PORCH_TIMINGS (1 << 1)
  33. #define DSI_MODE_MATCH_FULL_TIMINGS (DSI_MODE_MATCH_ACTIVE_TIMINGS | DSI_MODE_MATCH_PORCH_TIMINGS)
  34. u8 dbgfs_tx_cmd_buf[SZ_4K];
  35. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  36. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  37. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  38. {.boot_param = dsi_display_primary},
  39. {.boot_param = dsi_display_secondary},
  40. };
  41. static void dsi_display_panel_id_notification(struct dsi_display *display);
  42. static const struct of_device_id dsi_display_dt_match[] = {
  43. {.compatible = "qcom,dsi-display"},
  44. {}
  45. };
  46. bool is_skip_op_required(struct dsi_display *display)
  47. {
  48. if (!display)
  49. return false;
  50. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  51. }
  52. static bool is_sim_panel(struct dsi_display *display)
  53. {
  54. if (!display || !display->panel)
  55. return false;
  56. return display->panel->te_using_watchdog_timer;
  57. }
  58. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  59. u32 mask, bool enable)
  60. {
  61. int i;
  62. struct dsi_display_ctrl *ctrl;
  63. if (!display)
  64. return;
  65. display_for_each_ctrl(i, display) {
  66. ctrl = &display->ctrl[i];
  67. if (!ctrl)
  68. continue;
  69. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  70. }
  71. }
  72. static int dsi_display_config_clk_gating(struct dsi_display *display,
  73. bool enable)
  74. {
  75. int rc = 0, i = 0;
  76. struct dsi_display_ctrl *mctrl, *ctrl;
  77. enum dsi_clk_gate_type clk_selection;
  78. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  79. if (!display) {
  80. DSI_ERR("Invalid params\n");
  81. return -EINVAL;
  82. }
  83. if (display->panel->host_config.force_hs_clk_lane) {
  84. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  85. return 0;
  86. }
  87. mctrl = &display->ctrl[display->clk_master_idx];
  88. if (!mctrl) {
  89. DSI_ERR("Invalid controller\n");
  90. return -EINVAL;
  91. }
  92. clk_selection = display->clk_gating_config;
  93. if (!enable) {
  94. /* for disable path, make sure to disable all clk gating */
  95. clk_selection = DSI_CLK_ALL;
  96. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  97. /* Default selection, no overrides */
  98. clk_selection = default_clk_select;
  99. } else if (clk_selection == DSI_CLK_NONE) {
  100. clk_selection = 0;
  101. }
  102. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  103. enable ? "Enabling" : "Disabling",
  104. clk_selection & BYTE_CLK ? "yes" : "no",
  105. clk_selection & PIXEL_CLK ? "yes" : "no",
  106. clk_selection & DSI_PHY ? "yes" : "no");
  107. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  108. if (rc) {
  109. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  110. display->name, enable ? "enable" : "disable",
  111. clk_selection, rc);
  112. return rc;
  113. }
  114. display_for_each_ctrl(i, display) {
  115. ctrl = &display->ctrl[i];
  116. if (!ctrl->ctrl || (ctrl == mctrl))
  117. continue;
  118. /**
  119. * In Split DSI usecase we should not enable clock gating on
  120. * DSI PHY1 to ensure no display atrifacts are seen.
  121. */
  122. clk_selection &= ~DSI_PHY;
  123. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  124. clk_selection);
  125. if (rc) {
  126. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  127. display->name, enable ? "enable" : "disable",
  128. clk_selection, rc);
  129. return rc;
  130. }
  131. }
  132. return 0;
  133. }
  134. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  135. bool enable)
  136. {
  137. int i;
  138. struct dsi_display_ctrl *ctrl;
  139. if (!display)
  140. return;
  141. display_for_each_ctrl(i, display) {
  142. ctrl = &display->ctrl[i];
  143. if (!ctrl)
  144. continue;
  145. ctrl->ctrl->esd_check_underway = enable;
  146. }
  147. }
  148. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  149. {
  150. int i;
  151. struct dsi_display_ctrl *ctrl;
  152. if (!display)
  153. return;
  154. display_for_each_ctrl(i, display) {
  155. ctrl = &display->ctrl[i];
  156. if (!ctrl)
  157. continue;
  158. dsi_ctrl_irq_update(ctrl->ctrl, en);
  159. }
  160. }
  161. void dsi_rect_intersect(const struct dsi_rect *r1,
  162. const struct dsi_rect *r2,
  163. struct dsi_rect *result)
  164. {
  165. int l, t, r, b;
  166. if (!r1 || !r2 || !result)
  167. return;
  168. l = max(r1->x, r2->x);
  169. t = max(r1->y, r2->y);
  170. r = min((r1->x + r1->w), (r2->x + r2->w));
  171. b = min((r1->y + r1->h), (r2->y + r2->h));
  172. if (r <= l || b <= t) {
  173. memset(result, 0, sizeof(*result));
  174. } else {
  175. result->x = l;
  176. result->y = t;
  177. result->w = r - l;
  178. result->h = b - t;
  179. }
  180. }
  181. int dsi_display_set_backlight(struct drm_connector *connector,
  182. void *display, u32 bl_lvl)
  183. {
  184. struct dsi_display *dsi_display = display;
  185. struct dsi_panel *panel;
  186. u32 bl_scale, bl_scale_sv;
  187. u64 bl_temp;
  188. int rc = 0;
  189. if (dsi_display == NULL || dsi_display->panel == NULL)
  190. return -EINVAL;
  191. panel = dsi_display->panel;
  192. mutex_lock(&panel->panel_lock);
  193. if (!dsi_panel_initialized(panel)) {
  194. rc = -EINVAL;
  195. goto error;
  196. }
  197. panel->bl_config.bl_level = bl_lvl;
  198. /* scale backlight */
  199. bl_scale = panel->bl_config.bl_scale;
  200. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  201. bl_scale_sv = panel->bl_config.bl_scale_sv;
  202. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  203. if (bl_temp > panel->bl_config.bl_max_level)
  204. bl_temp = panel->bl_config.bl_max_level;
  205. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  206. bl_scale, bl_scale_sv, (u32)bl_temp);
  207. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  208. DSI_CORE_CLK, DSI_CLK_ON);
  209. if (rc) {
  210. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  211. dsi_display->name, rc);
  212. goto error;
  213. }
  214. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  215. if (rc)
  216. DSI_ERR("unable to set backlight\n");
  217. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  218. DSI_CORE_CLK, DSI_CLK_OFF);
  219. if (rc) {
  220. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  221. dsi_display->name, rc);
  222. goto error;
  223. }
  224. error:
  225. mutex_unlock(&panel->panel_lock);
  226. return rc;
  227. }
  228. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  229. {
  230. int rc = 0;
  231. int i;
  232. struct dsi_display_ctrl *m_ctrl, *ctrl;
  233. bool skip_op = is_skip_op_required(display);
  234. m_ctrl = &display->ctrl[display->cmd_master_idx];
  235. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  236. if (display->cmd_engine_refcount > 0) {
  237. display->cmd_engine_refcount++;
  238. goto done;
  239. }
  240. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  241. DSI_CTRL_ENGINE_ON, skip_op);
  242. if (rc) {
  243. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  244. display->name, skip_op, rc);
  245. goto done;
  246. }
  247. display_for_each_ctrl(i, display) {
  248. ctrl = &display->ctrl[i];
  249. if (!ctrl->ctrl || (ctrl == m_ctrl))
  250. continue;
  251. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  252. DSI_CTRL_ENGINE_ON, skip_op);
  253. if (rc) {
  254. DSI_ERR(
  255. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  256. display->name, skip_op, rc);
  257. goto error_disable_master;
  258. }
  259. }
  260. display->cmd_engine_refcount++;
  261. goto done;
  262. error_disable_master:
  263. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  264. DSI_CTRL_ENGINE_OFF, skip_op);
  265. done:
  266. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  267. return rc;
  268. }
  269. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  270. {
  271. int rc = 0;
  272. int i;
  273. struct dsi_display_ctrl *m_ctrl, *ctrl;
  274. bool skip_op = is_skip_op_required(display);
  275. m_ctrl = &display->ctrl[display->cmd_master_idx];
  276. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  277. if (display->cmd_engine_refcount == 0) {
  278. DSI_ERR("[%s] Invalid refcount\n", display->name);
  279. goto done;
  280. } else if (display->cmd_engine_refcount > 1) {
  281. display->cmd_engine_refcount--;
  282. goto done;
  283. }
  284. display_for_each_ctrl(i, display) {
  285. ctrl = &display->ctrl[i];
  286. if (!ctrl->ctrl || (ctrl == m_ctrl))
  287. continue;
  288. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  289. DSI_CTRL_ENGINE_OFF, skip_op);
  290. if (rc)
  291. DSI_ERR(
  292. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  293. display->name, skip_op, rc);
  294. }
  295. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  296. DSI_CTRL_ENGINE_OFF, skip_op);
  297. if (rc) {
  298. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  299. display->name, skip_op, rc);
  300. goto error;
  301. }
  302. error:
  303. display->cmd_engine_refcount = 0;
  304. done:
  305. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  306. return rc;
  307. }
  308. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  309. {
  310. struct dsi_display *display;
  311. struct dsi_display_ctrl *display_ctrl;
  312. int rc, cnt;
  313. if (!cb_data) {
  314. DSI_ERR("aspace cb called with invalid cb_data\n");
  315. return;
  316. }
  317. display = (struct dsi_display *)cb_data;
  318. /*
  319. * acquire panel_lock to make sure no commands are in-progress
  320. * while detaching the non-secure context banks
  321. */
  322. dsi_panel_acquire_panel_lock(display->panel);
  323. if (is_detach) {
  324. /* invalidate the stored iova */
  325. display->cmd_buffer_iova = 0;
  326. /* return the virtual address mapping */
  327. msm_gem_put_vaddr(display->tx_cmd_buf);
  328. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  329. } else {
  330. rc = msm_gem_get_iova(display->tx_cmd_buf,
  331. display->aspace, &(display->cmd_buffer_iova));
  332. if (rc) {
  333. DSI_ERR("failed to get the iova rc %d\n", rc);
  334. goto end;
  335. }
  336. display->vaddr =
  337. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  338. if (IS_ERR_OR_NULL(display->vaddr)) {
  339. DSI_ERR("failed to get va rc %d\n", rc);
  340. goto end;
  341. }
  342. }
  343. display_for_each_ctrl(cnt, display) {
  344. display_ctrl = &display->ctrl[cnt];
  345. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  346. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  347. display_ctrl->ctrl->vaddr = display->vaddr;
  348. display_ctrl->ctrl->secure_mode = is_detach;
  349. }
  350. end:
  351. /* release panel_lock */
  352. dsi_panel_release_panel_lock(display->panel);
  353. }
  354. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  355. {
  356. struct dsi_display *display = (struct dsi_display *)data;
  357. /*
  358. * This irq handler is used for sole purpose of identifying
  359. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  360. * in case of display not being initialized yet
  361. */
  362. if (!display)
  363. return IRQ_HANDLED;
  364. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  365. complete_all(&display->esd_te_gate);
  366. return IRQ_HANDLED;
  367. }
  368. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  369. bool enable)
  370. {
  371. if (!display) {
  372. DSI_ERR("Invalid params\n");
  373. return;
  374. }
  375. /* Handle unbalanced irq enable/disable calls */
  376. if (enable && !display->is_te_irq_enabled) {
  377. enable_irq(gpio_to_irq(display->disp_te_gpio));
  378. display->is_te_irq_enabled = true;
  379. } else if (!enable && display->is_te_irq_enabled) {
  380. disable_irq(gpio_to_irq(display->disp_te_gpio));
  381. display->is_te_irq_enabled = false;
  382. }
  383. }
  384. static void dsi_display_register_te_irq(struct dsi_display *display)
  385. {
  386. int rc = 0;
  387. struct platform_device *pdev;
  388. struct device *dev;
  389. unsigned int te_irq;
  390. pdev = display->pdev;
  391. if (!pdev) {
  392. DSI_ERR("invalid platform device\n");
  393. return;
  394. }
  395. dev = &pdev->dev;
  396. if (!dev) {
  397. DSI_ERR("invalid device\n");
  398. return;
  399. }
  400. if (display->trusted_vm_env) {
  401. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  402. return;
  403. }
  404. if (!gpio_is_valid(display->disp_te_gpio)) {
  405. rc = -EINVAL;
  406. goto error;
  407. }
  408. init_completion(&display->esd_te_gate);
  409. te_irq = gpio_to_irq(display->disp_te_gpio);
  410. /* Avoid deferred spurious irqs with disable_irq() */
  411. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  412. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  413. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  414. "TE_GPIO", display);
  415. if (rc) {
  416. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  417. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  418. goto error;
  419. }
  420. disable_irq(te_irq);
  421. display->is_te_irq_enabled = false;
  422. return;
  423. error:
  424. /* disable the TE based ESD check */
  425. DSI_WARN("Unable to register for TE IRQ\n");
  426. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  427. display->panel->esd_config.esd_enabled = false;
  428. }
  429. /* Allocate memory for cmd dma tx buffer */
  430. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  431. {
  432. int rc = 0, cnt = 0;
  433. struct dsi_display_ctrl *display_ctrl;
  434. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  435. SZ_4K,
  436. MSM_BO_UNCACHED);
  437. if ((display->tx_cmd_buf) == NULL) {
  438. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  439. rc = -ENOMEM;
  440. goto error;
  441. }
  442. display->cmd_buffer_size = SZ_4K;
  443. display->aspace = msm_gem_smmu_address_space_get(
  444. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  445. if (PTR_ERR(display->aspace) == -ENODEV) {
  446. display->aspace = NULL;
  447. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  448. } else if (IS_ERR_OR_NULL(display->aspace)) {
  449. rc = PTR_ERR(display->aspace);
  450. display->aspace = NULL;
  451. DSI_ERR("failed to get aspace %d\n", rc);
  452. goto free_gem;
  453. } else if (display->aspace) {
  454. /* register to aspace */
  455. rc = msm_gem_address_space_register_cb(display->aspace,
  456. dsi_display_aspace_cb_locked, (void *)display);
  457. if (rc) {
  458. DSI_ERR("failed to register callback %d\n", rc);
  459. goto free_gem;
  460. }
  461. }
  462. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  463. &(display->cmd_buffer_iova));
  464. if (rc) {
  465. DSI_ERR("failed to get the iova rc %d\n", rc);
  466. goto free_aspace_cb;
  467. }
  468. display->vaddr =
  469. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  470. if (IS_ERR_OR_NULL(display->vaddr)) {
  471. DSI_ERR("failed to get va rc %d\n", rc);
  472. rc = -EINVAL;
  473. goto put_iova;
  474. }
  475. display_for_each_ctrl(cnt, display) {
  476. display_ctrl = &display->ctrl[cnt];
  477. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  478. display_ctrl->ctrl->cmd_buffer_iova =
  479. display->cmd_buffer_iova;
  480. display_ctrl->ctrl->vaddr = display->vaddr;
  481. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  482. }
  483. return rc;
  484. put_iova:
  485. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  486. free_aspace_cb:
  487. msm_gem_address_space_unregister_cb(display->aspace,
  488. dsi_display_aspace_cb_locked, display);
  489. free_gem:
  490. mutex_lock(&display->drm_dev->struct_mutex);
  491. msm_gem_free_object(display->tx_cmd_buf);
  492. mutex_unlock(&display->drm_dev->struct_mutex);
  493. error:
  494. return rc;
  495. }
  496. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  497. {
  498. int i, j = 0;
  499. int len = 0, *lenp;
  500. int group = 0, count = 0;
  501. struct drm_panel_esd_config *config;
  502. if (!panel)
  503. return false;
  504. config = &(panel->esd_config);
  505. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  506. count = config->status_cmd.count;
  507. for (i = 0; i < count; i++)
  508. len += lenp[i];
  509. for (i = 0; i < len; i++)
  510. j += len;
  511. for (j = 0; j < config->groups; ++j) {
  512. for (i = 0; i < len; ++i) {
  513. if (config->return_buf[i] !=
  514. config->status_value[group + i]) {
  515. DRM_ERROR("mismatch: 0x%x\n",
  516. config->return_buf[i]);
  517. break;
  518. }
  519. }
  520. if (i == len)
  521. return true;
  522. group += len;
  523. }
  524. return false;
  525. }
  526. static void dsi_display_parse_demura_data(struct dsi_display *display)
  527. {
  528. int rc = 0;
  529. display->panel_id = ~0x0;
  530. if (display->fw) {
  531. DSI_DEBUG("FW definition unsupported for Demura panel data\n");
  532. return;
  533. }
  534. rc = of_property_read_u64(display->pdev->dev.of_node,
  535. "qcom,demura-panel-id", &display->panel_id);
  536. if (rc) {
  537. DSI_DEBUG("No panel ID is present for this display\n");
  538. } else if (!display->panel_id) {
  539. DSI_DEBUG("Dummy panel ID node present for this display\n");
  540. display->panel_id = ~0x0;
  541. } else {
  542. DSI_DEBUG("panel id found: %lx\n", display->panel_id);
  543. }
  544. }
  545. static void dsi_display_parse_te_data(struct dsi_display *display)
  546. {
  547. struct platform_device *pdev;
  548. struct device *dev;
  549. int rc = 0;
  550. u32 val = 0;
  551. pdev = display->pdev;
  552. if (!pdev) {
  553. DSI_ERR("Invalid platform device\n");
  554. return;
  555. }
  556. dev = &pdev->dev;
  557. if (!dev) {
  558. DSI_ERR("Invalid platform device\n");
  559. return;
  560. }
  561. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  562. "qcom,platform-te-gpio", 0);
  563. if (display->fw)
  564. rc = dsi_parser_read_u32(display->parser_node,
  565. "qcom,panel-te-source", &val);
  566. else
  567. rc = of_property_read_u32(dev->of_node,
  568. "qcom,panel-te-source", &val);
  569. if (rc || (val > MAX_TE_SOURCE_ID)) {
  570. DSI_ERR("invalid vsync source selection\n");
  571. val = 0;
  572. }
  573. display->te_source = val;
  574. }
  575. static void dsi_display_set_cmd_tx_ctrl_flags(struct dsi_display *display,
  576. struct dsi_cmd_desc *cmd)
  577. {
  578. struct dsi_display_ctrl *ctrl, *m_ctrl;
  579. struct mipi_dsi_msg *msg = &cmd->msg;
  580. u32 flags = 0;
  581. int i = 0;
  582. m_ctrl = &display->ctrl[display->clk_master_idx];
  583. display_for_each_ctrl(i, display) {
  584. ctrl = &display->ctrl[i];
  585. if (!ctrl->ctrl)
  586. continue;
  587. /*
  588. * Set cmd transfer mode flags.
  589. * 1) Default selection is CMD fetch from memory.
  590. * 2) In secure session override and use FIFO rather than
  591. * memory.
  592. * 3) If cmd_len is greater than FIFO size non embedded mode of
  593. * tx is used.
  594. */
  595. flags = DSI_CTRL_CMD_FETCH_MEMORY;
  596. if (ctrl->ctrl->secure_mode) {
  597. flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
  598. flags |= DSI_CTRL_CMD_FIFO_STORE;
  599. } else if (msg->tx_len > DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES) {
  600. flags |= DSI_CTRL_CMD_NON_EMBEDDED_MODE;
  601. }
  602. /* Set flags needed for broadcast. Read commands are always unicast */
  603. if (!(msg->flags & MIPI_DSI_MSG_UNICAST_COMMAND) && (display->ctrl_count > 1))
  604. flags |= DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER;
  605. /*
  606. * Set flags for command scheduling.
  607. * 1) In video mode command DMA scheduling is default.
  608. * 2) In command mode command DMA scheduling depends on message
  609. * flag and TE needs to be running.
  610. */
  611. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  612. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  613. } else {
  614. if (msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED)
  615. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  616. if (!display->enabled)
  617. flags &= ~DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  618. }
  619. /* Set flags for last command */
  620. if (!(msg->flags & MIPI_DSI_MSG_BATCH_COMMAND))
  621. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  622. /*
  623. * Set flags for asynchronous wait.
  624. * Asynchronous wait is supported in the following scenarios
  625. * 1) queue_cmd_waits is set by connector and
  626. * - commands are not sent using DSI FIFO memory
  627. * - commands are not sent in non-embedded mode
  628. * - not a video mode panel
  629. * - no explicit msg post_wait_ms is specified
  630. * - not a read command
  631. * 2) if async override msg flag is present
  632. */
  633. if (display->queue_cmd_waits)
  634. if (!(flags & DSI_CTRL_CMD_FIFO_STORE) &&
  635. !(flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) &&
  636. !(display->panel->panel_mode == DSI_OP_VIDEO_MODE) &&
  637. (cmd->post_wait_ms == 0) &&
  638. !(cmd->ctrl_flags & DSI_CTRL_CMD_READ))
  639. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  640. if (msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  641. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  642. }
  643. cmd->ctrl_flags |= flags;
  644. }
  645. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  646. struct dsi_display *display)
  647. {
  648. int i, rc = 0, count = 0, start = 0, *lenp;
  649. struct drm_panel_esd_config *config;
  650. struct dsi_cmd_desc *cmds;
  651. struct dsi_panel *panel;
  652. u32 flags = 0;
  653. if (!display->panel || !ctrl || !ctrl->ctrl)
  654. return -EINVAL;
  655. panel = display->panel;
  656. /*
  657. * When DSI controller is not in initialized state, we do not want to
  658. * report a false ESD failure and hence we defer until next read
  659. * happen.
  660. */
  661. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  662. return 1;
  663. config = &(panel->esd_config);
  664. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  665. count = config->status_cmd.count;
  666. cmds = config->status_cmd.cmds;
  667. flags = DSI_CTRL_CMD_READ;
  668. for (i = 0; i < count; ++i) {
  669. memset(config->status_buf, 0x0, SZ_4K);
  670. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  671. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  672. cmds[i].msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  673. cmds[i].msg.rx_buf = config->status_buf;
  674. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  675. cmds[i].ctrl_flags = flags;
  676. dsi_display_set_cmd_tx_ctrl_flags(display,&cmds[i]);
  677. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i]);
  678. if (rc <= 0) {
  679. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  680. return rc;
  681. }
  682. memcpy(config->return_buf + start,
  683. config->status_buf, lenp[i]);
  684. start += lenp[i];
  685. }
  686. return rc;
  687. }
  688. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  689. struct dsi_display *display)
  690. {
  691. int rc = 0;
  692. rc = dsi_display_read_status(ctrl, display);
  693. if (rc <= 0) {
  694. goto exit;
  695. } else {
  696. /*
  697. * panel status read successfully.
  698. * check for validity of the data read back.
  699. */
  700. rc = dsi_display_validate_reg_read(display->panel);
  701. if (!rc) {
  702. rc = -EINVAL;
  703. goto exit;
  704. }
  705. }
  706. exit:
  707. return rc;
  708. }
  709. static int dsi_display_status_reg_read(struct dsi_display *display)
  710. {
  711. int rc = 0, i;
  712. struct dsi_display_ctrl *m_ctrl, *ctrl;
  713. DSI_DEBUG(" ++\n");
  714. m_ctrl = &display->ctrl[display->cmd_master_idx];
  715. if (display->tx_cmd_buf == NULL) {
  716. rc = dsi_host_alloc_cmd_tx_buffer(display);
  717. if (rc) {
  718. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  719. goto done;
  720. }
  721. }
  722. rc = dsi_display_cmd_engine_enable(display);
  723. if (rc) {
  724. DSI_ERR("cmd engine enable failed\n");
  725. return -EPERM;
  726. }
  727. rc = dsi_display_validate_status(m_ctrl, display);
  728. if (rc <= 0) {
  729. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  730. display->name, rc);
  731. goto exit;
  732. }
  733. if (!display->panel->sync_broadcast_en)
  734. goto exit;
  735. display_for_each_ctrl(i, display) {
  736. ctrl = &display->ctrl[i];
  737. if (ctrl == m_ctrl)
  738. continue;
  739. rc = dsi_display_validate_status(ctrl, display);
  740. if (rc <= 0) {
  741. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  742. display->name, rc);
  743. goto exit;
  744. }
  745. }
  746. exit:
  747. dsi_display_cmd_engine_disable(display);
  748. done:
  749. return rc;
  750. }
  751. static int dsi_display_status_bta_request(struct dsi_display *display)
  752. {
  753. int rc = 0;
  754. DSI_DEBUG(" ++\n");
  755. /* TODO: trigger SW BTA and wait for acknowledgment */
  756. return rc;
  757. }
  758. static void dsi_display_release_te_irq(struct dsi_display *display)
  759. {
  760. int te_irq = 0;
  761. te_irq = gpio_to_irq(display->disp_te_gpio);
  762. if (te_irq)
  763. free_irq(te_irq, display);
  764. }
  765. static int dsi_display_status_check_te(struct dsi_display *display,
  766. int rechecks)
  767. {
  768. int rc = 1, i = 0;
  769. int const esd_te_timeout = msecs_to_jiffies(3*20);
  770. if (!rechecks)
  771. return rc;
  772. /* register te irq handler */
  773. dsi_display_register_te_irq(display);
  774. dsi_display_change_te_irq_status(display, true);
  775. for (i = 0; i < rechecks; i++) {
  776. reinit_completion(&display->esd_te_gate);
  777. if (!wait_for_completion_timeout(&display->esd_te_gate,
  778. esd_te_timeout)) {
  779. DSI_ERR("TE check failed\n");
  780. dsi_display_change_te_irq_status(display, false);
  781. return -EINVAL;
  782. }
  783. }
  784. dsi_display_change_te_irq_status(display, false);
  785. dsi_display_release_te_irq(display);
  786. return rc;
  787. }
  788. int dsi_display_check_status(struct drm_connector *connector, void *display,
  789. bool te_check_override)
  790. {
  791. struct dsi_display *dsi_display = display;
  792. struct dsi_panel *panel;
  793. u32 status_mode;
  794. int rc = 0x1, ret;
  795. u32 mask;
  796. int te_rechecks = 1;
  797. if (!dsi_display || !dsi_display->panel)
  798. return -EINVAL;
  799. panel = dsi_display->panel;
  800. dsi_panel_acquire_panel_lock(panel);
  801. if (!panel->panel_initialized) {
  802. DSI_DEBUG("Panel not initialized\n");
  803. goto release_panel_lock;
  804. }
  805. /* Prevent another ESD check,when ESD recovery is underway */
  806. if (atomic_read(&panel->esd_recovery_pending))
  807. goto release_panel_lock;
  808. status_mode = panel->esd_config.status_mode;
  809. if ((status_mode == ESD_MODE_SW_SIM_SUCCESS) || is_sim_panel(display))
  810. goto release_panel_lock;
  811. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  812. rc = -EINVAL;
  813. goto release_panel_lock;
  814. }
  815. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
  816. if (te_check_override)
  817. te_rechecks = MAX_TE_RECHECKS;
  818. if ((dsi_display->trusted_vm_env) ||
  819. (panel->panel_mode == DSI_OP_VIDEO_MODE))
  820. te_rechecks = 0;
  821. ret = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  822. DSI_ALL_CLKS, DSI_CLK_ON);
  823. if (ret)
  824. goto release_panel_lock;
  825. /* Mask error interrupts before attempting ESD read */
  826. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  827. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  828. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
  829. if (status_mode == ESD_MODE_REG_READ) {
  830. rc = dsi_display_status_reg_read(dsi_display);
  831. } else if (status_mode == ESD_MODE_SW_BTA) {
  832. rc = dsi_display_status_bta_request(dsi_display);
  833. } else if (status_mode == ESD_MODE_PANEL_TE) {
  834. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  835. te_check_override = false;
  836. } else {
  837. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  838. panel->esd_config.esd_enabled = false;
  839. }
  840. if (rc <= 0 && te_check_override)
  841. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  842. /* Unmask error interrupts if check passed*/
  843. if (rc > 0) {
  844. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  845. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
  846. false);
  847. if (te_check_override && panel->esd_config.esd_enabled == false)
  848. rc = dsi_display_status_check_te(dsi_display,
  849. te_rechecks);
  850. }
  851. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  852. DSI_ALL_CLKS, DSI_CLK_OFF);
  853. /* Handle Panel failures during display disable sequence */
  854. if (rc <=0)
  855. atomic_set(&panel->esd_recovery_pending, 1);
  856. release_panel_lock:
  857. dsi_panel_release_panel_lock(panel);
  858. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
  859. return rc;
  860. }
  861. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  862. bool *state)
  863. {
  864. struct dsi_display_ctrl *ctrl;
  865. int i, rc = -EINVAL;
  866. display_for_each_ctrl(i, dsi_display) {
  867. ctrl = &dsi_display->ctrl[i];
  868. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  869. if (rc)
  870. break;
  871. }
  872. return rc;
  873. }
  874. static int dsi_display_cmd_rx(struct dsi_display *display,
  875. struct dsi_cmd_desc *cmd)
  876. {
  877. struct dsi_display_ctrl *m_ctrl = NULL;
  878. u32 mask = 0, flags = 0;
  879. int rc = 0;
  880. if (!display || !display->panel)
  881. return -EINVAL;
  882. m_ctrl = &display->ctrl[display->cmd_master_idx];
  883. if (!m_ctrl || !m_ctrl->ctrl)
  884. return -EINVAL;
  885. /* acquire panel_lock to make sure no commands are in progress */
  886. dsi_panel_acquire_panel_lock(display->panel);
  887. if (!display->panel->panel_initialized) {
  888. DSI_DEBUG("panel not initialized\n");
  889. goto release_panel_lock;
  890. }
  891. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  892. DSI_ALL_CLKS, DSI_CLK_ON);
  893. if (rc)
  894. goto release_panel_lock;
  895. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  896. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  897. rc = dsi_display_cmd_engine_enable(display);
  898. if (rc) {
  899. DSI_ERR("cmd engine enable failed rc = %d\n", rc);
  900. goto error;
  901. }
  902. flags = DSI_CTRL_CMD_READ;
  903. cmd->ctrl_flags = flags;
  904. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  905. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  906. if (rc <= 0)
  907. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  908. dsi_display_cmd_engine_disable(display);
  909. error:
  910. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  911. dsi_display_clk_ctrl(display->dsi_clk_handle,
  912. DSI_ALL_CLKS, DSI_CLK_OFF);
  913. release_panel_lock:
  914. dsi_panel_release_panel_lock(display->panel);
  915. return rc;
  916. }
  917. int dsi_display_cmd_transfer(struct drm_connector *connector,
  918. void *display, const char *cmd_buf,
  919. u32 cmd_buf_len)
  920. {
  921. struct dsi_display *dsi_display = display;
  922. int rc = 0, cnt = 0, i = 0;
  923. bool state = false, transfer = false;
  924. struct dsi_panel_cmd_set *set;
  925. if (!dsi_display || !cmd_buf) {
  926. DSI_ERR("[DSI] invalid params\n");
  927. return -EINVAL;
  928. }
  929. DSI_DEBUG("[DSI] Display command transfer\n");
  930. if (!(cmd_buf[3] & MIPI_DSI_MSG_BATCH_COMMAND))
  931. transfer = true;
  932. mutex_lock(&dsi_display->display_lock);
  933. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  934. /**
  935. * Handle scenario where a command transfer is initiated through
  936. * sysfs interface when device is in suepnd state.
  937. */
  938. if (!rc && !state) {
  939. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  940. );
  941. rc = -EPERM;
  942. goto end;
  943. }
  944. if (rc || !state) {
  945. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  946. state, rc);
  947. rc = -EPERM;
  948. goto end;
  949. }
  950. /*
  951. * Reset the dbgfs buffer if the commands sent exceed the available
  952. * buffer size. For video mode, limiting the buffer size to 2K to
  953. * ensure no performance issues.
  954. */
  955. if (dsi_display->panel->panel_mode == DSI_OP_CMD_MODE) {
  956. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_4K) {
  957. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  958. dsi_display->tx_cmd_buf_ndx = 0;
  959. }
  960. } else {
  961. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_2K) {
  962. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  963. dsi_display->tx_cmd_buf_ndx = 0;
  964. }
  965. }
  966. memcpy(&dbgfs_tx_cmd_buf[dsi_display->tx_cmd_buf_ndx], cmd_buf,
  967. cmd_buf_len);
  968. dsi_display->tx_cmd_buf_ndx += cmd_buf_len;
  969. if (transfer) {
  970. struct dsi_cmd_desc *cmds;
  971. set = &dsi_display->cmd_set;
  972. set->count = 0;
  973. dsi_panel_get_cmd_pkt_count(dbgfs_tx_cmd_buf,
  974. dsi_display->tx_cmd_buf_ndx, &cnt);
  975. dsi_panel_alloc_cmd_packets(set, cnt);
  976. dsi_panel_create_cmd_packets(dbgfs_tx_cmd_buf,
  977. dsi_display->tx_cmd_buf_ndx, cnt, set->cmds);
  978. cmds = set->cmds;
  979. dsi_display->tx_cmd_buf_ndx = 0;
  980. for (i = 0; i < cnt; i++) {
  981. rc = dsi_host_transfer_sub(&dsi_display->host, cmds);
  982. if (rc < 0) {
  983. DSI_ERR("failed to send command, rc=%d\n", rc);
  984. break;
  985. }
  986. if (cmds->post_wait_ms)
  987. usleep_range(cmds->post_wait_ms*1000,
  988. ((cmds->post_wait_ms*1000)+10));
  989. cmds++;
  990. }
  991. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  992. dsi_panel_destroy_cmd_packets(set);
  993. dsi_panel_dealloc_cmd_packets(set);
  994. }
  995. end:
  996. mutex_unlock(&dsi_display->display_lock);
  997. return rc;
  998. }
  999. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  1000. bool enable)
  1001. {
  1002. int i;
  1003. struct dsi_display_ctrl *ctrl;
  1004. if (!display || !display->panel->host_config.force_hs_clk_lane)
  1005. return;
  1006. display_for_each_ctrl(i, display) {
  1007. ctrl = &display->ctrl[i];
  1008. /*
  1009. * For phy ver 4.0 chipsets, configure DSI controller and
  1010. * DSI PHY to force clk lane to HS mode always whereas
  1011. * for other phy ver chipsets, configure DSI controller only.
  1012. */
  1013. if (ctrl->phy->hw.ops.set_continuous_clk) {
  1014. dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
  1015. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  1016. dsi_phy_set_continuous_clk(ctrl->phy, enable);
  1017. } else {
  1018. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  1019. }
  1020. }
  1021. }
  1022. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  1023. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len)
  1024. {
  1025. struct dsi_display *dsi_display = display;
  1026. struct dsi_cmd_desc cmd = {};
  1027. bool state = false;
  1028. int rc = -1;
  1029. if (!dsi_display || !cmd_buf || !recv_buf) {
  1030. DSI_ERR("[DSI] invalid params\n");
  1031. return -EINVAL;
  1032. }
  1033. rc = dsi_panel_create_cmd_packets(cmd_buf, cmd_buf_len, 1, &cmd);
  1034. if (rc) {
  1035. DSI_ERR("[DSI] command packet create failed, rc = %d\n", rc);
  1036. return rc;
  1037. }
  1038. cmd.msg.rx_buf = recv_buf;
  1039. cmd.msg.rx_len = recv_buf_len;
  1040. cmd.msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  1041. mutex_lock(&dsi_display->display_lock);
  1042. if (is_sim_panel(display)) {
  1043. DSI_DEBUG("Simulation panel doesn't support read commands\n");
  1044. goto end;
  1045. }
  1046. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  1047. if (rc || !state) {
  1048. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  1049. state, rc);
  1050. rc = -EPERM;
  1051. goto end;
  1052. }
  1053. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  1054. if (rc <= 0)
  1055. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  1056. end:
  1057. mutex_unlock(&dsi_display->display_lock);
  1058. return rc;
  1059. }
  1060. int dsi_display_soft_reset(void *display)
  1061. {
  1062. struct dsi_display *dsi_display;
  1063. struct dsi_display_ctrl *ctrl;
  1064. int rc = 0;
  1065. int i;
  1066. if (!display)
  1067. return -EINVAL;
  1068. dsi_display = display;
  1069. display_for_each_ctrl(i, dsi_display) {
  1070. ctrl = &dsi_display->ctrl[i];
  1071. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  1072. if (rc) {
  1073. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  1074. dsi_display->name, i, rc);
  1075. break;
  1076. }
  1077. }
  1078. return rc;
  1079. }
  1080. enum dsi_pixel_format dsi_display_get_dst_format(
  1081. struct drm_connector *connector,
  1082. void *display)
  1083. {
  1084. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  1085. struct dsi_display *dsi_display = (struct dsi_display *)display;
  1086. if (!dsi_display || !dsi_display->panel) {
  1087. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  1088. dsi_display,
  1089. ((dsi_display) ? dsi_display->panel : NULL));
  1090. return format;
  1091. }
  1092. format = dsi_display->panel->host_config.dst_format;
  1093. return format;
  1094. }
  1095. static void _dsi_display_setup_misr(struct dsi_display *display)
  1096. {
  1097. int i;
  1098. display_for_each_ctrl(i, display) {
  1099. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  1100. display->misr_enable,
  1101. display->misr_frame_count);
  1102. }
  1103. }
  1104. int dsi_display_set_power(struct drm_connector *connector,
  1105. int power_mode, void *disp)
  1106. {
  1107. struct dsi_display *display = disp;
  1108. int rc = 0;
  1109. if (!display || !display->panel) {
  1110. DSI_ERR("invalid display/panel\n");
  1111. return -EINVAL;
  1112. }
  1113. switch (power_mode) {
  1114. case SDE_MODE_DPMS_LP1:
  1115. rc = dsi_panel_set_lp1(display->panel);
  1116. break;
  1117. case SDE_MODE_DPMS_LP2:
  1118. rc = dsi_panel_set_lp2(display->panel);
  1119. break;
  1120. case SDE_MODE_DPMS_ON:
  1121. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  1122. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  1123. rc = dsi_panel_set_nolp(display->panel);
  1124. break;
  1125. case SDE_MODE_DPMS_OFF:
  1126. default:
  1127. return rc;
  1128. }
  1129. SDE_EVT32(display->panel->power_mode, power_mode, rc);
  1130. DSI_DEBUG("Power mode transition from %d to %d %s",
  1131. display->panel->power_mode, power_mode,
  1132. rc ? "failed" : "successful");
  1133. if (!rc)
  1134. display->panel->power_mode = power_mode;
  1135. return rc;
  1136. }
  1137. #ifdef CONFIG_DEBUG_FS
  1138. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  1139. {
  1140. u32 status_mode = 0;
  1141. if (!display->panel) {
  1142. DSI_ERR("Invalid panel data\n");
  1143. return false;
  1144. }
  1145. status_mode = display->panel->esd_config.status_mode;
  1146. if (status_mode == ESD_MODE_PANEL_TE &&
  1147. gpio_is_valid(display->disp_te_gpio))
  1148. return true;
  1149. return false;
  1150. }
  1151. static ssize_t debugfs_dump_info_read(struct file *file,
  1152. char __user *user_buf,
  1153. size_t user_len,
  1154. loff_t *ppos)
  1155. {
  1156. struct dsi_display *display = file->private_data;
  1157. struct dsi_mode_info *m;
  1158. char *buf;
  1159. u32 len = 0;
  1160. int i;
  1161. if (!display)
  1162. return -ENODEV;
  1163. if (*ppos)
  1164. return 0;
  1165. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1166. if (!buf)
  1167. return -ENOMEM;
  1168. m = &display->config.video_timing;
  1169. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1170. len += snprintf(buf + len, (SZ_4K - len),
  1171. "\tResolution = %d(%d|%d|%d|%d)x%d(%d|%d|%d|%d)@%dfps %llu Hz\n",
  1172. m->h_active, m->h_back_porch, m->h_front_porch, m->h_sync_width,
  1173. m->h_sync_polarity, m->v_active, m->v_back_porch, m->v_front_porch,
  1174. m->v_sync_width, m->v_sync_polarity, m->refresh_rate, m->clk_rate_hz);
  1175. display_for_each_ctrl(i, display) {
  1176. len += snprintf(buf + len, (SZ_4K - len),
  1177. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1178. i, display->ctrl[i].ctrl->name,
  1179. display->ctrl[i].phy->name);
  1180. }
  1181. len += snprintf(buf + len, (SZ_4K - len),
  1182. "\tPanel = %s\n", display->panel->name);
  1183. len += snprintf(buf + len, (SZ_4K - len),
  1184. "\tClock master = %s\n",
  1185. display->ctrl[display->clk_master_idx].ctrl->name);
  1186. if (len > user_len)
  1187. len = user_len;
  1188. if (copy_to_user(user_buf, buf, len)) {
  1189. kfree(buf);
  1190. return -EFAULT;
  1191. }
  1192. *ppos += len;
  1193. kfree(buf);
  1194. return len;
  1195. }
  1196. static ssize_t debugfs_misr_setup(struct file *file,
  1197. const char __user *user_buf,
  1198. size_t user_len,
  1199. loff_t *ppos)
  1200. {
  1201. struct dsi_display *display = file->private_data;
  1202. char *buf;
  1203. int rc = 0;
  1204. size_t len;
  1205. u32 enable, frame_count;
  1206. if (!display)
  1207. return -ENODEV;
  1208. if (*ppos)
  1209. return 0;
  1210. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1211. if (!buf)
  1212. return -ENOMEM;
  1213. /* leave room for termination char */
  1214. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1215. if (copy_from_user(buf, user_buf, len)) {
  1216. rc = -EINVAL;
  1217. goto error;
  1218. }
  1219. buf[len] = '\0'; /* terminate the string */
  1220. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1221. rc = -EINVAL;
  1222. goto error;
  1223. }
  1224. display->misr_enable = enable;
  1225. display->misr_frame_count = frame_count;
  1226. mutex_lock(&display->display_lock);
  1227. if (!display->hw_ownership) {
  1228. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1229. display->name);
  1230. rc = -EOPNOTSUPP;
  1231. goto unlock;
  1232. }
  1233. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1234. DSI_CORE_CLK, DSI_CLK_ON);
  1235. if (rc) {
  1236. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1237. display->name, rc);
  1238. goto unlock;
  1239. }
  1240. _dsi_display_setup_misr(display);
  1241. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1242. DSI_CORE_CLK, DSI_CLK_OFF);
  1243. if (rc) {
  1244. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1245. display->name, rc);
  1246. goto unlock;
  1247. }
  1248. rc = user_len;
  1249. unlock:
  1250. mutex_unlock(&display->display_lock);
  1251. error:
  1252. kfree(buf);
  1253. return rc;
  1254. }
  1255. static ssize_t debugfs_misr_read(struct file *file,
  1256. char __user *user_buf,
  1257. size_t user_len,
  1258. loff_t *ppos)
  1259. {
  1260. struct dsi_display *display = file->private_data;
  1261. char *buf;
  1262. u32 len = 0;
  1263. int rc = 0;
  1264. struct dsi_ctrl *dsi_ctrl;
  1265. int i;
  1266. u32 misr;
  1267. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1268. if (!display)
  1269. return -ENODEV;
  1270. if (*ppos)
  1271. return 0;
  1272. buf = kzalloc(max_len, GFP_KERNEL);
  1273. if (ZERO_OR_NULL_PTR(buf))
  1274. return -ENOMEM;
  1275. mutex_lock(&display->display_lock);
  1276. if (!display->hw_ownership) {
  1277. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1278. display->name);
  1279. rc = -EOPNOTSUPP;
  1280. goto error;
  1281. }
  1282. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1283. DSI_CORE_CLK, DSI_CLK_ON);
  1284. if (rc) {
  1285. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1286. display->name, rc);
  1287. goto error;
  1288. }
  1289. display_for_each_ctrl(i, display) {
  1290. dsi_ctrl = display->ctrl[i].ctrl;
  1291. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1292. len += snprintf((buf + len), max_len - len,
  1293. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1294. if (len >= max_len)
  1295. break;
  1296. }
  1297. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1298. DSI_CORE_CLK, DSI_CLK_OFF);
  1299. if (rc) {
  1300. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1301. display->name, rc);
  1302. goto error;
  1303. }
  1304. if (copy_to_user(user_buf, buf, max_len)) {
  1305. rc = -EFAULT;
  1306. goto error;
  1307. }
  1308. *ppos += len;
  1309. error:
  1310. mutex_unlock(&display->display_lock);
  1311. kfree(buf);
  1312. return len;
  1313. }
  1314. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1315. const char __user *user_buf,
  1316. size_t user_len,
  1317. loff_t *ppos)
  1318. {
  1319. struct dsi_display *display = file->private_data;
  1320. char *buf;
  1321. int rc = 0;
  1322. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1323. u32 esd_trigger;
  1324. size_t len;
  1325. if (!display)
  1326. return -ENODEV;
  1327. if (*ppos)
  1328. return 0;
  1329. if (user_len > sizeof(u32))
  1330. return -EINVAL;
  1331. if (!user_len || !user_buf)
  1332. return -EINVAL;
  1333. if (!display->panel ||
  1334. atomic_read(&display->panel->esd_recovery_pending))
  1335. return user_len;
  1336. if (!esd_config->esd_enabled) {
  1337. DSI_ERR("ESD feature is not enabled\n");
  1338. return -EINVAL;
  1339. }
  1340. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1341. if (!buf)
  1342. return -ENOMEM;
  1343. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1344. if (copy_from_user(buf, user_buf, len)) {
  1345. rc = -EINVAL;
  1346. goto error;
  1347. }
  1348. buf[len] = '\0'; /* terminate the string */
  1349. if (kstrtouint(buf, 10, &esd_trigger)) {
  1350. rc = -EINVAL;
  1351. goto error;
  1352. }
  1353. if (esd_trigger != 1) {
  1354. rc = -EINVAL;
  1355. goto error;
  1356. }
  1357. display->esd_trigger = esd_trigger;
  1358. mutex_lock(&display->display_lock);
  1359. if (!display->hw_ownership) {
  1360. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1361. display->name);
  1362. rc = -EOPNOTSUPP;
  1363. goto unlock;
  1364. }
  1365. if (display->esd_trigger) {
  1366. DSI_INFO("ESD attack triggered by user\n");
  1367. rc = dsi_panel_trigger_esd_attack(display->panel,
  1368. display->trusted_vm_env);
  1369. if (rc) {
  1370. DSI_ERR("Failed to trigger ESD attack\n");
  1371. goto error;
  1372. }
  1373. }
  1374. rc = len;
  1375. unlock:
  1376. mutex_unlock(&display->display_lock);
  1377. error:
  1378. kfree(buf);
  1379. return rc;
  1380. }
  1381. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1382. const char __user *user_buf,
  1383. size_t user_len,
  1384. loff_t *ppos)
  1385. {
  1386. struct dsi_display *display = file->private_data;
  1387. struct drm_panel_esd_config *esd_config;
  1388. char *buf;
  1389. int rc = 0;
  1390. size_t len;
  1391. if (!display)
  1392. return -ENODEV;
  1393. if (*ppos)
  1394. return 0;
  1395. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1396. if (ZERO_OR_NULL_PTR(buf))
  1397. return -ENOMEM;
  1398. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1399. if (copy_from_user(buf, user_buf, len)) {
  1400. rc = -EINVAL;
  1401. goto error;
  1402. }
  1403. buf[len] = '\0'; /* terminate the string */
  1404. if (!display->panel) {
  1405. rc = -EINVAL;
  1406. goto error;
  1407. }
  1408. esd_config = &display->panel->esd_config;
  1409. if (!esd_config) {
  1410. DSI_ERR("Invalid panel esd config\n");
  1411. rc = -EINVAL;
  1412. goto error;
  1413. }
  1414. if (!esd_config->esd_enabled) {
  1415. rc = -EINVAL;
  1416. goto error;
  1417. }
  1418. if (!strcmp(buf, "te_signal_check\n")) {
  1419. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1420. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1421. rc = -EINVAL;
  1422. goto error;
  1423. }
  1424. DSI_INFO("ESD check is switched to TE mode by user\n");
  1425. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1426. dsi_display_change_te_irq_status(display, true);
  1427. }
  1428. if (!strcmp(buf, "reg_read\n")) {
  1429. DSI_INFO("ESD check is switched to reg read by user\n");
  1430. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1431. if (rc) {
  1432. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1433. rc);
  1434. rc = user_len;
  1435. goto error;
  1436. }
  1437. esd_config->status_mode = ESD_MODE_REG_READ;
  1438. if (dsi_display_is_te_based_esd(display))
  1439. dsi_display_change_te_irq_status(display, false);
  1440. }
  1441. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1442. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1443. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1444. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1445. rc = len;
  1446. error:
  1447. kfree(buf);
  1448. return rc;
  1449. }
  1450. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1451. char __user *user_buf,
  1452. size_t user_len,
  1453. loff_t *ppos)
  1454. {
  1455. struct dsi_display *display = file->private_data;
  1456. struct drm_panel_esd_config *esd_config;
  1457. char *buf;
  1458. int rc = 0;
  1459. size_t len = 0;
  1460. if (!display)
  1461. return -ENODEV;
  1462. if (*ppos)
  1463. return 0;
  1464. if (!display->panel) {
  1465. DSI_ERR("invalid panel data\n");
  1466. return -EINVAL;
  1467. }
  1468. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1469. if (ZERO_OR_NULL_PTR(buf))
  1470. return -ENOMEM;
  1471. esd_config = &display->panel->esd_config;
  1472. if (!esd_config) {
  1473. DSI_ERR("Invalid panel esd config\n");
  1474. rc = -EINVAL;
  1475. goto error;
  1476. }
  1477. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1478. if (!esd_config->esd_enabled) {
  1479. rc = snprintf(buf, len, "ESD feature not enabled");
  1480. goto output_mode;
  1481. }
  1482. switch (esd_config->status_mode) {
  1483. case ESD_MODE_REG_READ:
  1484. rc = snprintf(buf, len, "reg_read");
  1485. break;
  1486. case ESD_MODE_PANEL_TE:
  1487. rc = snprintf(buf, len, "te_signal_check");
  1488. break;
  1489. case ESD_MODE_SW_SIM_FAILURE:
  1490. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1491. break;
  1492. case ESD_MODE_SW_SIM_SUCCESS:
  1493. rc = snprintf(buf, len, "esd_sw_sim_success");
  1494. break;
  1495. default:
  1496. rc = snprintf(buf, len, "invalid");
  1497. break;
  1498. }
  1499. output_mode:
  1500. if (!rc) {
  1501. rc = -EINVAL;
  1502. goto error;
  1503. }
  1504. if (copy_to_user(user_buf, buf, len)) {
  1505. rc = -EFAULT;
  1506. goto error;
  1507. }
  1508. *ppos += len;
  1509. error:
  1510. kfree(buf);
  1511. return len;
  1512. }
  1513. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1514. const char __user *user_buf,
  1515. size_t user_len,
  1516. loff_t *ppos)
  1517. {
  1518. struct dsi_display *display = file->private_data;
  1519. struct dsi_display_ctrl *display_ctrl;
  1520. char *buf;
  1521. int rc = 0;
  1522. u32 line = 0, window = 0;
  1523. size_t len;
  1524. int i;
  1525. if (!display)
  1526. return -ENODEV;
  1527. if (*ppos)
  1528. return 0;
  1529. buf = kzalloc(256, GFP_KERNEL);
  1530. if (ZERO_OR_NULL_PTR(buf))
  1531. return -ENOMEM;
  1532. len = min_t(size_t, user_len, 255);
  1533. if (copy_from_user(buf, user_buf, len)) {
  1534. rc = -EINVAL;
  1535. goto error;
  1536. }
  1537. buf[len] = '\0'; /* terminate the string */
  1538. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1539. return -EFAULT;
  1540. display_for_each_ctrl(i, display) {
  1541. struct dsi_ctrl *ctrl;
  1542. display_ctrl = &display->ctrl[i];
  1543. if (!display_ctrl->ctrl)
  1544. continue;
  1545. ctrl = display_ctrl->ctrl;
  1546. ctrl->host_config.common_config.dma_sched_line = line;
  1547. ctrl->host_config.common_config.dma_sched_window = window;
  1548. }
  1549. rc = len;
  1550. error:
  1551. kfree(buf);
  1552. return rc;
  1553. }
  1554. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1555. char __user *user_buf,
  1556. size_t user_len,
  1557. loff_t *ppos)
  1558. {
  1559. struct dsi_display *display = file->private_data;
  1560. struct dsi_display_ctrl *m_ctrl;
  1561. struct dsi_ctrl *ctrl;
  1562. char *buf;
  1563. u32 len = 0;
  1564. int rc = 0;
  1565. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1566. if (!display)
  1567. return -ENODEV;
  1568. if (*ppos)
  1569. return 0;
  1570. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1571. ctrl = m_ctrl->ctrl;
  1572. buf = kzalloc(max_len, GFP_KERNEL);
  1573. if (ZERO_OR_NULL_PTR(buf))
  1574. return -ENOMEM;
  1575. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1576. ctrl->host_config.common_config.dma_sched_line);
  1577. len += scnprintf((buf + len), max_len - len,
  1578. "Schedule command window width: %d\n",
  1579. ctrl->host_config.common_config.dma_sched_window);
  1580. if (len > max_len)
  1581. len = max_len;
  1582. if (copy_to_user(user_buf, buf, len)) {
  1583. rc = -EFAULT;
  1584. goto error;
  1585. }
  1586. *ppos += len;
  1587. error:
  1588. kfree(buf);
  1589. return len;
  1590. }
  1591. static const struct file_operations dump_info_fops = {
  1592. .open = simple_open,
  1593. .read = debugfs_dump_info_read,
  1594. };
  1595. static const struct file_operations misr_data_fops = {
  1596. .open = simple_open,
  1597. .read = debugfs_misr_read,
  1598. .write = debugfs_misr_setup,
  1599. };
  1600. static const struct file_operations esd_trigger_fops = {
  1601. .open = simple_open,
  1602. .write = debugfs_esd_trigger_check,
  1603. };
  1604. static const struct file_operations esd_check_mode_fops = {
  1605. .open = simple_open,
  1606. .write = debugfs_alter_esd_check_mode,
  1607. .read = debugfs_read_esd_check_mode,
  1608. };
  1609. static const struct file_operations dsi_command_scheduling_fops = {
  1610. .open = simple_open,
  1611. .write = debugfs_update_cmd_scheduling_params,
  1612. .read = debugfs_read_cmd_scheduling_params,
  1613. };
  1614. static int dsi_display_debugfs_init(struct dsi_display *display)
  1615. {
  1616. int rc = 0;
  1617. struct dentry *dir, *dump_file, *misr_data;
  1618. char name[MAX_NAME_SIZE];
  1619. char panel_name[SEC_PANEL_NAME_MAX_LEN];
  1620. char secondary_panel_str[] = "_secondary";
  1621. int i;
  1622. strlcpy(panel_name, display->name, SEC_PANEL_NAME_MAX_LEN);
  1623. if (strcmp(display->display_type, "secondary") == 0)
  1624. strlcat(panel_name, secondary_panel_str, SEC_PANEL_NAME_MAX_LEN);
  1625. dir = debugfs_create_dir(panel_name, NULL);
  1626. if (IS_ERR_OR_NULL(dir)) {
  1627. rc = PTR_ERR(dir);
  1628. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1629. display->name, rc);
  1630. goto error;
  1631. }
  1632. dump_file = debugfs_create_file("dump_info",
  1633. 0400,
  1634. dir,
  1635. display,
  1636. &dump_info_fops);
  1637. if (IS_ERR_OR_NULL(dump_file)) {
  1638. rc = PTR_ERR(dump_file);
  1639. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1640. display->name, rc);
  1641. goto error_remove_dir;
  1642. }
  1643. dump_file = debugfs_create_file("esd_trigger",
  1644. 0644,
  1645. dir,
  1646. display,
  1647. &esd_trigger_fops);
  1648. if (IS_ERR_OR_NULL(dump_file)) {
  1649. rc = PTR_ERR(dump_file);
  1650. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1651. display->name, rc);
  1652. goto error_remove_dir;
  1653. }
  1654. dump_file = debugfs_create_file("esd_check_mode",
  1655. 0644,
  1656. dir,
  1657. display,
  1658. &esd_check_mode_fops);
  1659. if (IS_ERR_OR_NULL(dump_file)) {
  1660. rc = PTR_ERR(dump_file);
  1661. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1662. display->name, rc);
  1663. goto error_remove_dir;
  1664. }
  1665. dump_file = debugfs_create_file("cmd_sched_params",
  1666. 0644,
  1667. dir,
  1668. display,
  1669. &dsi_command_scheduling_fops);
  1670. if (IS_ERR_OR_NULL(dump_file)) {
  1671. rc = PTR_ERR(dump_file);
  1672. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1673. display->name, rc);
  1674. goto error_remove_dir;
  1675. }
  1676. misr_data = debugfs_create_file("misr_data",
  1677. 0600,
  1678. dir,
  1679. display,
  1680. &misr_data_fops);
  1681. if (IS_ERR_OR_NULL(misr_data)) {
  1682. rc = PTR_ERR(misr_data);
  1683. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1684. display->name, rc);
  1685. goto error_remove_dir;
  1686. }
  1687. display_for_each_ctrl(i, display) {
  1688. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1689. if (!phy || !phy->name)
  1690. continue;
  1691. snprintf(name, ARRAY_SIZE(name),
  1692. "%s_allow_phy_power_off", phy->name);
  1693. dump_file = debugfs_create_bool(name, 0600, dir,
  1694. &phy->allow_phy_power_off);
  1695. if (IS_ERR_OR_NULL(dump_file)) {
  1696. rc = PTR_ERR(dump_file);
  1697. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1698. display->name, name, rc);
  1699. goto error_remove_dir;
  1700. }
  1701. snprintf(name, ARRAY_SIZE(name),
  1702. "%s_regulator_min_datarate_bps", phy->name);
  1703. debugfs_create_u32(name, 0600, dir, &phy->regulator_min_datarate_bps);
  1704. }
  1705. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1706. &display->panel->ulps_feature_enabled)) {
  1707. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1708. display->name);
  1709. goto error_remove_dir;
  1710. }
  1711. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1712. &display->panel->ulps_suspend_enabled)) {
  1713. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1714. display->name);
  1715. goto error_remove_dir;
  1716. }
  1717. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1718. &display->ulps_enabled)) {
  1719. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1720. display->name);
  1721. goto error_remove_dir;
  1722. }
  1723. debugfs_create_u32("clk_gating_config", 0600, dir, &display->clk_gating_config);
  1724. display->root = dir;
  1725. dsi_parser_dbg_init(display->parser, dir);
  1726. return rc;
  1727. error_remove_dir:
  1728. debugfs_remove(dir);
  1729. error:
  1730. return rc;
  1731. }
  1732. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1733. {
  1734. debugfs_remove_recursive(display->root);
  1735. return 0;
  1736. }
  1737. #else
  1738. static int dsi_display_debugfs_init(struct dsi_display *display)
  1739. {
  1740. return 0;
  1741. }
  1742. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1743. {
  1744. return 0;
  1745. }
  1746. #endif /* CONFIG_DEBUG_FS */
  1747. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1748. struct dsi_display_mode *mode)
  1749. {
  1750. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1751. bool is_split_link = host->split_link.enabled;
  1752. u32 sublinks_count = host->split_link.num_sublinks;
  1753. if (is_split_link && sublinks_count > 1) {
  1754. mode->timing.h_active /= sublinks_count;
  1755. mode->timing.h_front_porch /= sublinks_count;
  1756. mode->timing.h_sync_width /= sublinks_count;
  1757. mode->timing.h_back_porch /= sublinks_count;
  1758. mode->timing.h_skew /= sublinks_count;
  1759. mode->pixel_clk_khz /= sublinks_count;
  1760. } else {
  1761. if (mode->priv_info->dsc_enabled)
  1762. mode->priv_info->dsc.config.pic_width =
  1763. mode->timing.h_active;
  1764. mode->timing.h_active /= display->ctrl_count;
  1765. mode->timing.h_front_porch /= display->ctrl_count;
  1766. mode->timing.h_sync_width /= display->ctrl_count;
  1767. mode->timing.h_back_porch /= display->ctrl_count;
  1768. mode->timing.h_skew /= display->ctrl_count;
  1769. mode->pixel_clk_khz /= display->ctrl_count;
  1770. }
  1771. }
  1772. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1773. bool enable)
  1774. {
  1775. /* TODO: make checks based on cont. splash */
  1776. DSI_DEBUG("checking ulps req validity\n");
  1777. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1778. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1779. return false;
  1780. }
  1781. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1782. !display->panel->ulps_suspend_enabled) {
  1783. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1784. return false;
  1785. }
  1786. if (!dsi_panel_initialized(display->panel) &&
  1787. !display->panel->ulps_suspend_enabled) {
  1788. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1789. return false;
  1790. }
  1791. if (enable && display->ulps_enabled) {
  1792. DSI_DEBUG("ULPS already enabled\n");
  1793. return false;
  1794. } else if (!enable && !display->ulps_enabled) {
  1795. DSI_DEBUG("ULPS already disabled\n");
  1796. return false;
  1797. }
  1798. /*
  1799. * No need to enter ULPS when transitioning from splash screen to
  1800. * boot animation or trusted vm environments since it is expected
  1801. * that the clocks would be turned right back on.
  1802. */
  1803. if (enable && is_skip_op_required(display))
  1804. return false;
  1805. return true;
  1806. }
  1807. /**
  1808. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1809. * @dsi_display: DSI display handle.
  1810. * @enable: enable/disable ULPS.
  1811. *
  1812. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1813. *
  1814. * Return: error code.
  1815. */
  1816. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1817. {
  1818. int rc = 0;
  1819. int i = 0;
  1820. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1821. if (!display) {
  1822. DSI_ERR("Invalid params\n");
  1823. return -EINVAL;
  1824. }
  1825. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1826. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1827. __func__, enable);
  1828. return 0;
  1829. }
  1830. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1831. /*
  1832. * ULPS entry-exit can be either through the DSI controller or
  1833. * the DSI PHY depending on hardware variation. For some chipsets,
  1834. * both controller version and phy version ulps entry-exit ops can
  1835. * be present. To handle such cases, send ulps request through PHY,
  1836. * if ulps request is handled in PHY, then no need to send request
  1837. * through controller.
  1838. */
  1839. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1840. display->clamp_enabled);
  1841. if (rc == DSI_PHY_ULPS_ERROR) {
  1842. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1843. return -EINVAL;
  1844. }
  1845. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1846. display_for_each_ctrl(i, display) {
  1847. ctrl = &display->ctrl[i];
  1848. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1849. continue;
  1850. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1851. enable, display->clamp_enabled);
  1852. if (rc == DSI_PHY_ULPS_ERROR) {
  1853. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1854. enable);
  1855. return -EINVAL;
  1856. }
  1857. }
  1858. }
  1859. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1860. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1861. if (rc) {
  1862. DSI_ERR("Ulps controller state change(%d) failed\n",
  1863. enable);
  1864. return rc;
  1865. }
  1866. display_for_each_ctrl(i, display) {
  1867. ctrl = &display->ctrl[i];
  1868. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1869. continue;
  1870. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1871. if (rc) {
  1872. DSI_ERR("Ulps controller state change(%d) failed\n",
  1873. enable);
  1874. return rc;
  1875. }
  1876. }
  1877. }
  1878. display->ulps_enabled = enable;
  1879. return 0;
  1880. }
  1881. /**
  1882. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1883. * @dsi_display: DSI display handle.
  1884. * @enable: enable/disable clamping.
  1885. *
  1886. * Return: error code.
  1887. */
  1888. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1889. {
  1890. int rc = 0;
  1891. int i = 0;
  1892. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1893. bool ulps_enabled = false;
  1894. if (!display) {
  1895. DSI_ERR("Invalid params\n");
  1896. return -EINVAL;
  1897. }
  1898. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1899. ulps_enabled = display->ulps_enabled;
  1900. /*
  1901. * Clamp control can be either through the DSI controller or
  1902. * the DSI PHY depending on hardware variation
  1903. */
  1904. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1905. if (rc) {
  1906. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1907. return rc;
  1908. }
  1909. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1910. if (rc) {
  1911. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1912. return rc;
  1913. }
  1914. display_for_each_ctrl(i, display) {
  1915. ctrl = &display->ctrl[i];
  1916. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1917. continue;
  1918. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1919. if (rc) {
  1920. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1921. return rc;
  1922. }
  1923. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1924. if (rc) {
  1925. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1926. enable);
  1927. return rc;
  1928. }
  1929. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1930. enable ? "enabled" : "disabled", i);
  1931. }
  1932. display->clamp_enabled = enable;
  1933. return 0;
  1934. }
  1935. /**
  1936. * dsi_display_setup_ctrl() - setup DSI controller.
  1937. * @dsi_display: DSI display handle.
  1938. *
  1939. * Return: error code.
  1940. */
  1941. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1942. {
  1943. int rc = 0;
  1944. int i = 0;
  1945. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1946. if (!display) {
  1947. DSI_ERR("Invalid params\n");
  1948. return -EINVAL;
  1949. }
  1950. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1951. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1952. if (rc) {
  1953. DSI_ERR("DSI controller setup failed\n");
  1954. return rc;
  1955. }
  1956. display_for_each_ctrl(i, display) {
  1957. ctrl = &display->ctrl[i];
  1958. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1959. continue;
  1960. rc = dsi_ctrl_setup(ctrl->ctrl);
  1961. if (rc) {
  1962. DSI_ERR("DSI controller setup failed\n");
  1963. return rc;
  1964. }
  1965. }
  1966. return 0;
  1967. }
  1968. static int dsi_display_phy_enable(struct dsi_display *display);
  1969. /**
  1970. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1971. * @dsi_display: DSI display handle.
  1972. * @mmss_clamp: True if clamp is enabled.
  1973. *
  1974. * Return: error code.
  1975. */
  1976. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1977. bool mmss_clamp)
  1978. {
  1979. int rc = 0;
  1980. int i = 0;
  1981. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1982. if (!display) {
  1983. DSI_ERR("Invalid params\n");
  1984. return -EINVAL;
  1985. }
  1986. if (mmss_clamp && !display->phy_idle_power_off) {
  1987. dsi_display_phy_enable(display);
  1988. return 0;
  1989. }
  1990. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1991. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1992. if (rc) {
  1993. DSI_ERR("DSI controller setup failed\n");
  1994. return rc;
  1995. }
  1996. display_for_each_ctrl(i, display) {
  1997. ctrl = &display->ctrl[i];
  1998. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1999. continue;
  2000. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  2001. if (rc) {
  2002. DSI_ERR("DSI controller setup failed\n");
  2003. return rc;
  2004. }
  2005. }
  2006. display->phy_idle_power_off = false;
  2007. return 0;
  2008. }
  2009. /**
  2010. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  2011. * @dsi_display: DSI display handle.
  2012. *
  2013. * Return: error code.
  2014. */
  2015. static int dsi_display_phy_idle_off(struct dsi_display *display)
  2016. {
  2017. int rc = 0;
  2018. int i = 0;
  2019. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2020. if (!display) {
  2021. DSI_ERR("Invalid params\n");
  2022. return -EINVAL;
  2023. }
  2024. display_for_each_ctrl(i, display) {
  2025. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  2026. if (!phy)
  2027. continue;
  2028. if (!phy->allow_phy_power_off) {
  2029. DSI_DEBUG("phy doesn't support this feature\n");
  2030. return 0;
  2031. }
  2032. }
  2033. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2034. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  2035. if (rc) {
  2036. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2037. display->name, rc);
  2038. return rc;
  2039. }
  2040. display_for_each_ctrl(i, display) {
  2041. ctrl = &display->ctrl[i];
  2042. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2043. continue;
  2044. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  2045. if (rc) {
  2046. DSI_ERR("DSI controller setup failed\n");
  2047. return rc;
  2048. }
  2049. }
  2050. display->phy_idle_power_off = true;
  2051. return 0;
  2052. }
  2053. void dsi_display_enable_event(struct drm_connector *connector,
  2054. struct dsi_display *display,
  2055. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  2056. bool enable)
  2057. {
  2058. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  2059. int i;
  2060. if (!display) {
  2061. DSI_ERR("invalid display\n");
  2062. return;
  2063. }
  2064. if (event_info)
  2065. event_info->event_idx = event_idx;
  2066. switch (event_idx) {
  2067. case SDE_CONN_EVENT_VID_DONE:
  2068. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  2069. break;
  2070. case SDE_CONN_EVENT_CMD_DONE:
  2071. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  2072. break;
  2073. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  2074. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  2075. if (event_info) {
  2076. display_for_each_ctrl(i, display)
  2077. display->ctrl[i].ctrl->recovery_cb =
  2078. *event_info;
  2079. }
  2080. break;
  2081. case SDE_CONN_EVENT_PANEL_ID:
  2082. if (event_info)
  2083. display_for_each_ctrl(i, display)
  2084. display->ctrl[i].ctrl->panel_id_cb
  2085. = *event_info;
  2086. dsi_display_panel_id_notification(display);
  2087. break;
  2088. default:
  2089. /* nothing to do */
  2090. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  2091. return;
  2092. }
  2093. if (enable) {
  2094. display_for_each_ctrl(i, display)
  2095. dsi_ctrl_enable_status_interrupt(
  2096. display->ctrl[i].ctrl, irq_status_idx,
  2097. event_info);
  2098. } else {
  2099. display_for_each_ctrl(i, display)
  2100. dsi_ctrl_disable_status_interrupt(
  2101. display->ctrl[i].ctrl, irq_status_idx);
  2102. }
  2103. }
  2104. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  2105. {
  2106. int rc = 0;
  2107. int i;
  2108. struct dsi_display_ctrl *ctrl;
  2109. /* Sequence does not matter for split dsi usecases */
  2110. display_for_each_ctrl(i, display) {
  2111. ctrl = &display->ctrl[i];
  2112. if (!ctrl->ctrl)
  2113. continue;
  2114. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2115. DSI_CTRL_POWER_VREG_ON);
  2116. if (rc) {
  2117. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2118. ctrl->ctrl->name, rc);
  2119. goto error;
  2120. }
  2121. }
  2122. return rc;
  2123. error:
  2124. for (i = i - 1; i >= 0; i--) {
  2125. ctrl = &display->ctrl[i];
  2126. if (!ctrl->ctrl)
  2127. continue;
  2128. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  2129. DSI_CTRL_POWER_VREG_OFF);
  2130. }
  2131. return rc;
  2132. }
  2133. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  2134. {
  2135. int rc = 0;
  2136. int i;
  2137. struct dsi_display_ctrl *ctrl;
  2138. /* Sequence does not matter for split dsi usecases */
  2139. display_for_each_ctrl(i, display) {
  2140. ctrl = &display->ctrl[i];
  2141. if (!ctrl->ctrl)
  2142. continue;
  2143. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2144. DSI_CTRL_POWER_VREG_OFF);
  2145. if (rc) {
  2146. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2147. ctrl->ctrl->name, rc);
  2148. goto error;
  2149. }
  2150. }
  2151. error:
  2152. return rc;
  2153. }
  2154. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  2155. unsigned int display_type)
  2156. {
  2157. char *boot_str = NULL;
  2158. char *str = NULL;
  2159. char *sw_te = NULL;
  2160. unsigned long cmdline_topology = NO_OVERRIDE;
  2161. unsigned long cmdline_timing = NO_OVERRIDE;
  2162. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2163. DSI_ERR("display_type=%d not supported\n", display_type);
  2164. goto end;
  2165. }
  2166. if (display_type == DSI_PRIMARY)
  2167. boot_str = dsi_display_primary;
  2168. else
  2169. boot_str = dsi_display_secondary;
  2170. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2171. if (sw_te)
  2172. display->sw_te_using_wd = true;
  2173. str = strnstr(boot_str, ":config", strlen(boot_str));
  2174. if (str) {
  2175. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2176. DSI_ERR("invalid config index override: %s\n",
  2177. boot_str);
  2178. goto end;
  2179. }
  2180. }
  2181. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2182. if (str) {
  2183. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2184. DSI_ERR("invalid timing index override: %s\n",
  2185. boot_str);
  2186. cmdline_topology = NO_OVERRIDE;
  2187. goto end;
  2188. }
  2189. }
  2190. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2191. end:
  2192. display->cmdline_topology = cmdline_topology;
  2193. display->cmdline_timing = cmdline_timing;
  2194. }
  2195. /**
  2196. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2197. *
  2198. * Return: returns error status
  2199. */
  2200. static int dsi_display_parse_boot_display_selection(void)
  2201. {
  2202. char *pos = NULL;
  2203. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2204. int i, j;
  2205. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2206. strlcpy(disp_buf, boot_displays[i].boot_param,
  2207. MAX_CMDLINE_PARAM_LEN);
  2208. pos = strnstr(disp_buf, ":", strlen(disp_buf));
  2209. /* Use ':' as a delimiter to retrieve the display name */
  2210. if (!pos) {
  2211. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2212. continue;
  2213. }
  2214. for (j = 0; (disp_buf + j) < pos; j++)
  2215. boot_displays[i].name[j] = *(disp_buf + j);
  2216. boot_displays[i].name[j] = '\0';
  2217. boot_displays[i].boot_disp_en = true;
  2218. }
  2219. return 0;
  2220. }
  2221. static int dsi_display_phy_power_on(struct dsi_display *display)
  2222. {
  2223. int rc = 0;
  2224. int i;
  2225. struct dsi_display_ctrl *ctrl;
  2226. /* Sequence does not matter for split dsi usecases */
  2227. display_for_each_ctrl(i, display) {
  2228. ctrl = &display->ctrl[i];
  2229. if (!ctrl->ctrl)
  2230. continue;
  2231. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2232. if (rc) {
  2233. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2234. ctrl->phy->name, rc);
  2235. goto error;
  2236. }
  2237. }
  2238. return rc;
  2239. error:
  2240. for (i = i - 1; i >= 0; i--) {
  2241. ctrl = &display->ctrl[i];
  2242. if (!ctrl->phy)
  2243. continue;
  2244. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2245. }
  2246. return rc;
  2247. }
  2248. static int dsi_display_phy_power_off(struct dsi_display *display)
  2249. {
  2250. int rc = 0;
  2251. int i;
  2252. struct dsi_display_ctrl *ctrl;
  2253. /* Sequence does not matter for split dsi usecases */
  2254. display_for_each_ctrl(i, display) {
  2255. ctrl = &display->ctrl[i];
  2256. if (!ctrl->phy)
  2257. continue;
  2258. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2259. if (rc) {
  2260. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2261. ctrl->ctrl->name, rc);
  2262. goto error;
  2263. }
  2264. }
  2265. error:
  2266. return rc;
  2267. }
  2268. static int dsi_display_set_clk_src(struct dsi_display *display, bool set_xo)
  2269. {
  2270. int rc = 0;
  2271. int i;
  2272. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2273. struct dsi_ctrl_clk_info *info;
  2274. if (display->trusted_vm_env)
  2275. return 0;
  2276. /*
  2277. * In case of split DSI usecases, the clock for master controller should
  2278. * be enabled before the other controller. Master controller in the
  2279. * clock context refers to the controller that sources the clock. While turning off the
  2280. * clocks, the source is set to xo.
  2281. */
  2282. m_ctrl = &display->ctrl[display->clk_master_idx];
  2283. info = &m_ctrl->ctrl->clk_info;
  2284. if (!set_xo)
  2285. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.pll_clks);
  2286. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2287. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &info->xo_clk);
  2288. if (rc) {
  2289. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n", display->name, rc);
  2290. return rc;
  2291. }
  2292. /* Set source for the rest of the controllers */
  2293. display_for_each_ctrl(i, display) {
  2294. ctrl = &display->ctrl[i];
  2295. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2296. continue;
  2297. info = &ctrl->ctrl->clk_info;
  2298. if (!set_xo)
  2299. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &display->clock_info.pll_clks);
  2300. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2301. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &info->xo_clk);
  2302. if (rc) {
  2303. DSI_ERR("[%s] failed to set source clocks, rc=%d\n", display->name, rc);
  2304. return rc;
  2305. }
  2306. }
  2307. return 0;
  2308. }
  2309. int dsi_display_phy_pll_toggle(void *priv, bool prepare)
  2310. {
  2311. int rc = 0;
  2312. struct dsi_display *display = priv;
  2313. struct dsi_display_ctrl *m_ctrl;
  2314. if (!display) {
  2315. DSI_ERR("invalid arguments\n");
  2316. return -EINVAL;
  2317. }
  2318. if (is_skip_op_required(display))
  2319. return 0;
  2320. rc = dsi_display_set_clk_src(display, !prepare);
  2321. m_ctrl = &display->ctrl[display->clk_master_idx];
  2322. if (!m_ctrl->phy) {
  2323. DSI_ERR("[%s] PHY not found\n", display->name);
  2324. return -EINVAL;
  2325. }
  2326. rc = dsi_phy_pll_toggle(m_ctrl->phy, prepare);
  2327. return rc;
  2328. }
  2329. int dsi_display_phy_configure(void *priv, bool commit)
  2330. {
  2331. int rc = 0;
  2332. struct dsi_display *display = priv;
  2333. struct dsi_display_ctrl *m_ctrl;
  2334. struct dsi_pll_resource *pll_res;
  2335. struct dsi_ctrl *ctrl;
  2336. if (!display) {
  2337. DSI_ERR("invalid arguments\n");
  2338. return -EINVAL;
  2339. }
  2340. if (is_skip_op_required(display))
  2341. return 0;
  2342. m_ctrl = &display->ctrl[display->clk_master_idx];
  2343. if ((!m_ctrl->phy) || (!m_ctrl->ctrl)) {
  2344. DSI_ERR("[%s] PHY not found\n", display->name);
  2345. return -EINVAL;
  2346. }
  2347. pll_res = m_ctrl->phy->pll;
  2348. if (!pll_res) {
  2349. DSI_ERR("[%s] PLL res not found\n", display->name);
  2350. return -EINVAL;
  2351. }
  2352. ctrl = m_ctrl->ctrl;
  2353. pll_res->byteclk_rate = ctrl->clk_freq.byte_clk_rate;
  2354. pll_res->pclk_rate = ctrl->clk_freq.pix_clk_rate;
  2355. rc = dsi_phy_configure(m_ctrl->phy, commit);
  2356. return rc;
  2357. }
  2358. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2359. bool enable)
  2360. {
  2361. int rc = 0;
  2362. int i;
  2363. struct dsi_display_ctrl *ctrl;
  2364. display_for_each_ctrl(i, display) {
  2365. ctrl = &display->ctrl[i];
  2366. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2367. if (rc) {
  2368. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2369. display->name, enable ? "mask" : "unmask", rc);
  2370. return rc;
  2371. }
  2372. }
  2373. return 0;
  2374. }
  2375. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2376. {
  2377. struct dsi_display_ctrl *ctrl;
  2378. int i;
  2379. if (!display)
  2380. return;
  2381. display_for_each_ctrl(i, display) {
  2382. ctrl = &display->ctrl[i];
  2383. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2384. }
  2385. /*
  2386. * After retime buffer synchronization we need to turn of clk_en_sel
  2387. * bit on each phy. Avoid this for Cphy.
  2388. */
  2389. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2390. return;
  2391. display_for_each_ctrl(i, display) {
  2392. ctrl = &display->ctrl[i];
  2393. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2394. }
  2395. }
  2396. static int dsi_display_ctrl_update(struct dsi_display *display)
  2397. {
  2398. int rc = 0;
  2399. int i;
  2400. struct dsi_display_ctrl *ctrl;
  2401. display_for_each_ctrl(i, display) {
  2402. ctrl = &display->ctrl[i];
  2403. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2404. if (rc) {
  2405. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2406. display->name, i, rc);
  2407. goto error_host_deinit;
  2408. }
  2409. }
  2410. return 0;
  2411. error_host_deinit:
  2412. for (i = i - 1; i >= 0; i--) {
  2413. ctrl = &display->ctrl[i];
  2414. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2415. }
  2416. return rc;
  2417. }
  2418. static int dsi_display_ctrl_init(struct dsi_display *display)
  2419. {
  2420. int rc = 0;
  2421. int i;
  2422. struct dsi_display_ctrl *ctrl;
  2423. bool skip_op = is_skip_op_required(display);
  2424. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2425. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2426. * we will programe DSI controller as part of core clock enable.
  2427. * After that we should not re-configure DSI controller again here for
  2428. * usecases where we are resuming from ulps suspend as it might put
  2429. * the HW in bad state.
  2430. */
  2431. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2432. display_for_each_ctrl(i, display) {
  2433. ctrl = &display->ctrl[i];
  2434. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2435. if (rc) {
  2436. DSI_ERR(
  2437. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2438. display->name, i, skip_op, rc);
  2439. goto error_host_deinit;
  2440. }
  2441. }
  2442. } else {
  2443. display_for_each_ctrl(i, display) {
  2444. ctrl = &display->ctrl[i];
  2445. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2446. DSI_CTRL_OP_HOST_INIT,
  2447. true);
  2448. if (rc)
  2449. DSI_DEBUG("host init update failed rc=%d\n",
  2450. rc);
  2451. }
  2452. }
  2453. return rc;
  2454. error_host_deinit:
  2455. for (i = i - 1; i >= 0; i--) {
  2456. ctrl = &display->ctrl[i];
  2457. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2458. }
  2459. return rc;
  2460. }
  2461. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2462. {
  2463. int rc = 0;
  2464. int i;
  2465. struct dsi_display_ctrl *ctrl;
  2466. display_for_each_ctrl(i, display) {
  2467. ctrl = &display->ctrl[i];
  2468. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2469. if (rc) {
  2470. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2471. display->name, i, rc);
  2472. }
  2473. }
  2474. return rc;
  2475. }
  2476. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2477. {
  2478. int rc = 0;
  2479. int i;
  2480. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2481. bool skip_op = is_skip_op_required(display);
  2482. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2483. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2484. DSI_CTRL_ENGINE_ON, skip_op);
  2485. if (rc) {
  2486. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2487. display->name, skip_op, rc);
  2488. goto error;
  2489. }
  2490. display_for_each_ctrl(i, display) {
  2491. ctrl = &display->ctrl[i];
  2492. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2493. continue;
  2494. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2495. DSI_CTRL_ENGINE_ON, skip_op);
  2496. if (rc) {
  2497. DSI_ERR(
  2498. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2499. display->name, skip_op, rc);
  2500. goto error_disable_master;
  2501. }
  2502. }
  2503. return rc;
  2504. error_disable_master:
  2505. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2506. DSI_CTRL_ENGINE_OFF, skip_op);
  2507. error:
  2508. return rc;
  2509. }
  2510. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2511. {
  2512. int rc = 0;
  2513. int i;
  2514. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2515. bool skip_op = is_skip_op_required(display);
  2516. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2517. /*
  2518. * For platforms where ULPS is controlled by DSI controller block,
  2519. * do not disable dsi controller block if lanes are to be
  2520. * kept in ULPS during suspend. So just update the SW state
  2521. * and return early.
  2522. */
  2523. if (display->panel->ulps_suspend_enabled &&
  2524. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2525. display_for_each_ctrl(i, display) {
  2526. ctrl = &display->ctrl[i];
  2527. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2528. DSI_CTRL_OP_HOST_ENGINE,
  2529. false);
  2530. if (rc)
  2531. DSI_DEBUG("host state update failed %d\n", rc);
  2532. }
  2533. return rc;
  2534. }
  2535. display_for_each_ctrl(i, display) {
  2536. ctrl = &display->ctrl[i];
  2537. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2538. continue;
  2539. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2540. DSI_CTRL_ENGINE_OFF, skip_op);
  2541. if (rc)
  2542. DSI_ERR(
  2543. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2544. display->name, skip_op, rc);
  2545. }
  2546. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2547. DSI_CTRL_ENGINE_OFF, skip_op);
  2548. if (rc) {
  2549. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2550. display->name, skip_op, rc);
  2551. goto error;
  2552. }
  2553. error:
  2554. return rc;
  2555. }
  2556. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2557. {
  2558. int rc = 0;
  2559. int i;
  2560. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2561. bool skip_op = is_skip_op_required(display);
  2562. m_ctrl = &display->ctrl[display->video_master_idx];
  2563. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2564. DSI_CTRL_ENGINE_ON, skip_op);
  2565. if (rc) {
  2566. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2567. display->name, skip_op, rc);
  2568. goto error;
  2569. }
  2570. display_for_each_ctrl(i, display) {
  2571. ctrl = &display->ctrl[i];
  2572. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2573. continue;
  2574. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2575. DSI_CTRL_ENGINE_ON, skip_op);
  2576. if (rc) {
  2577. DSI_ERR(
  2578. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2579. display->name, skip_op, rc);
  2580. goto error_disable_master;
  2581. }
  2582. }
  2583. return rc;
  2584. error_disable_master:
  2585. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2586. DSI_CTRL_ENGINE_OFF, skip_op);
  2587. error:
  2588. return rc;
  2589. }
  2590. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2591. {
  2592. int rc = 0;
  2593. int i;
  2594. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2595. bool skip_op = is_skip_op_required(display);
  2596. m_ctrl = &display->ctrl[display->video_master_idx];
  2597. display_for_each_ctrl(i, display) {
  2598. ctrl = &display->ctrl[i];
  2599. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2600. continue;
  2601. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2602. DSI_CTRL_ENGINE_OFF, skip_op);
  2603. if (rc)
  2604. DSI_ERR(
  2605. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2606. display->name, skip_op, rc);
  2607. }
  2608. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2609. DSI_CTRL_ENGINE_OFF, skip_op);
  2610. if (rc)
  2611. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2612. display->name, skip_op, rc);
  2613. return rc;
  2614. }
  2615. static int dsi_display_phy_enable(struct dsi_display *display)
  2616. {
  2617. int rc = 0;
  2618. int i;
  2619. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2620. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2621. bool skip_op = is_skip_op_required(display);
  2622. m_ctrl = &display->ctrl[display->clk_master_idx];
  2623. if (display->ctrl_count > 1)
  2624. m_src = DSI_PLL_SOURCE_NATIVE;
  2625. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2626. m_src, true, skip_op);
  2627. if (rc) {
  2628. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2629. display->name, skip_op, rc);
  2630. goto error;
  2631. }
  2632. display_for_each_ctrl(i, display) {
  2633. ctrl = &display->ctrl[i];
  2634. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2635. continue;
  2636. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2637. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2638. if (rc) {
  2639. DSI_ERR(
  2640. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2641. display->name, skip_op, rc);
  2642. goto error_disable_master;
  2643. }
  2644. }
  2645. return rc;
  2646. error_disable_master:
  2647. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2648. error:
  2649. return rc;
  2650. }
  2651. static int dsi_display_phy_disable(struct dsi_display *display)
  2652. {
  2653. int rc = 0;
  2654. int i;
  2655. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2656. bool skip_op = is_skip_op_required(display);
  2657. m_ctrl = &display->ctrl[display->clk_master_idx];
  2658. display_for_each_ctrl(i, display) {
  2659. ctrl = &display->ctrl[i];
  2660. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2661. continue;
  2662. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2663. if (rc)
  2664. DSI_ERR(
  2665. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2666. display->name, skip_op, rc);
  2667. }
  2668. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2669. if (rc)
  2670. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2671. display->name, skip_op, rc);
  2672. return rc;
  2673. }
  2674. static int dsi_display_wake_up(struct dsi_display *display)
  2675. {
  2676. return 0;
  2677. }
  2678. static void dsi_display_mask_overflow(struct dsi_display *display, u32 flags,
  2679. bool enable)
  2680. {
  2681. struct dsi_display_ctrl *ctrl;
  2682. int i;
  2683. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2684. return;
  2685. display_for_each_ctrl(i, display) {
  2686. ctrl = &display->ctrl[i];
  2687. if (!ctrl)
  2688. continue;
  2689. dsi_ctrl_mask_overflow(ctrl->ctrl, enable);
  2690. }
  2691. }
  2692. static int dsi_display_broadcast_cmd(struct dsi_display *display, struct dsi_cmd_desc *cmd)
  2693. {
  2694. int rc = 0;
  2695. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2696. int i;
  2697. /*
  2698. * 1. Setup commands in FIFO
  2699. * 2. Trigger commands
  2700. */
  2701. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2702. dsi_display_mask_overflow(display, cmd->ctrl_flags, true);
  2703. cmd->ctrl_flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2704. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  2705. if (rc) {
  2706. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2707. display->name, rc);
  2708. goto error;
  2709. }
  2710. cmd->ctrl_flags &= ~DSI_CTRL_CMD_BROADCAST_MASTER;
  2711. display_for_each_ctrl(i, display) {
  2712. ctrl = &display->ctrl[i];
  2713. if (ctrl == m_ctrl)
  2714. continue;
  2715. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, cmd);
  2716. if (rc) {
  2717. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2718. display->name, rc);
  2719. goto error;
  2720. }
  2721. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, cmd->ctrl_flags);
  2722. if (rc) {
  2723. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2724. display->name, rc);
  2725. goto error;
  2726. }
  2727. }
  2728. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, cmd->ctrl_flags | DSI_CTRL_CMD_BROADCAST_MASTER);
  2729. if (rc) {
  2730. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2731. display->name, rc);
  2732. goto error;
  2733. }
  2734. error:
  2735. dsi_display_mask_overflow(display, cmd->ctrl_flags, false);
  2736. return rc;
  2737. }
  2738. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2739. {
  2740. int rc = 0;
  2741. int i;
  2742. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2743. /*
  2744. * For continuous splash and trusted vm environment,
  2745. * ctrl states are updated separately and hence we do
  2746. * an early return
  2747. */
  2748. if (is_skip_op_required(display)) {
  2749. DSI_DEBUG(
  2750. "cont splash/trusted vm use case, phy sw reset not required\n");
  2751. return 0;
  2752. }
  2753. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2754. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2755. if (rc) {
  2756. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2757. goto error;
  2758. }
  2759. display_for_each_ctrl(i, display) {
  2760. ctrl = &display->ctrl[i];
  2761. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2762. continue;
  2763. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2764. if (rc) {
  2765. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2766. display->name, rc);
  2767. goto error;
  2768. }
  2769. }
  2770. error:
  2771. return rc;
  2772. }
  2773. static int dsi_host_attach(struct mipi_dsi_host *host,
  2774. struct mipi_dsi_device *dsi)
  2775. {
  2776. return 0;
  2777. }
  2778. static int dsi_host_detach(struct mipi_dsi_host *host,
  2779. struct mipi_dsi_device *dsi)
  2780. {
  2781. return 0;
  2782. }
  2783. int dsi_host_transfer_sub(struct mipi_dsi_host *host, struct dsi_cmd_desc *cmd)
  2784. {
  2785. struct dsi_display *display;
  2786. int rc = 0, ret = 0;
  2787. if (!host || !cmd) {
  2788. DSI_ERR("Invalid params\n");
  2789. return 0;
  2790. }
  2791. display = to_dsi_display(host);
  2792. /* Avoid sending DCS commands when ESD recovery is pending */
  2793. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2794. DSI_DEBUG("ESD recovery pending\n");
  2795. return 0;
  2796. }
  2797. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2798. DSI_ALL_CLKS, DSI_CLK_ON);
  2799. if (rc) {
  2800. DSI_ERR("[%s] failed to enable all DSI clocks, rc=%d\n",
  2801. display->name, rc);
  2802. goto error;
  2803. }
  2804. rc = dsi_display_wake_up(display);
  2805. if (rc) {
  2806. DSI_ERR("[%s] failed to wake up display, rc=%d\n",
  2807. display->name, rc);
  2808. goto error_disable_clks;
  2809. }
  2810. rc = dsi_display_cmd_engine_enable(display);
  2811. if (rc) {
  2812. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2813. display->name, rc);
  2814. goto error_disable_clks;
  2815. }
  2816. if (display->tx_cmd_buf == NULL) {
  2817. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2818. if (rc) {
  2819. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2820. goto error_disable_cmd_engine;
  2821. }
  2822. }
  2823. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  2824. if (cmd->ctrl_flags & DSI_CTRL_CMD_BROADCAST) {
  2825. rc = dsi_display_broadcast_cmd(display, cmd);
  2826. if (rc) {
  2827. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n", display->name, rc);
  2828. goto error_disable_cmd_engine;
  2829. }
  2830. } else {
  2831. int idx = cmd->ctrl;
  2832. rc = dsi_ctrl_cmd_transfer(display->ctrl[idx].ctrl, cmd);
  2833. if (rc) {
  2834. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2835. display->name, rc);
  2836. goto error_disable_cmd_engine;
  2837. }
  2838. }
  2839. error_disable_cmd_engine:
  2840. ret = dsi_display_cmd_engine_disable(display);
  2841. if (ret) {
  2842. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  2843. display->name, ret);
  2844. }
  2845. error_disable_clks:
  2846. ret = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2847. DSI_ALL_CLKS, DSI_CLK_OFF);
  2848. if (ret) {
  2849. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  2850. display->name, ret);
  2851. }
  2852. error:
  2853. return rc;
  2854. }
  2855. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg)
  2856. {
  2857. int rc = 0;
  2858. struct dsi_cmd_desc cmd;
  2859. if (!msg) {
  2860. DSI_ERR("Invalid params\n");
  2861. return 0;
  2862. }
  2863. memcpy(&cmd.msg, msg, sizeof(*msg));
  2864. cmd.ctrl = 0;
  2865. cmd.post_wait_ms = 0;
  2866. cmd.ctrl_flags = 0;
  2867. rc = dsi_host_transfer_sub(host, &cmd);
  2868. return rc;
  2869. }
  2870. static struct mipi_dsi_host_ops dsi_host_ops = {
  2871. .attach = dsi_host_attach,
  2872. .detach = dsi_host_detach,
  2873. .transfer = dsi_host_transfer,
  2874. };
  2875. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2876. {
  2877. int rc = 0;
  2878. struct mipi_dsi_host *host = &display->host;
  2879. host->dev = &display->pdev->dev;
  2880. host->ops = &dsi_host_ops;
  2881. rc = mipi_dsi_host_register(host);
  2882. if (rc) {
  2883. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2884. display->name, rc);
  2885. goto error;
  2886. }
  2887. error:
  2888. return rc;
  2889. }
  2890. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2891. {
  2892. int rc = 0;
  2893. struct mipi_dsi_host *host = &display->host;
  2894. mipi_dsi_host_unregister(host);
  2895. host->dev = NULL;
  2896. host->ops = NULL;
  2897. return rc;
  2898. }
  2899. static bool dsi_display_check_prefix(const char *clk_prefix,
  2900. const char *clk_name)
  2901. {
  2902. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2903. }
  2904. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2905. char *dsi_clk_name)
  2906. {
  2907. if (display->fw)
  2908. return dsi_parser_count_strings(display->parser_node,
  2909. dsi_clk_name);
  2910. else
  2911. return of_property_count_strings(display->panel_node,
  2912. dsi_clk_name);
  2913. }
  2914. static void dsi_display_get_clock_name(struct dsi_display *display,
  2915. char *dsi_clk_name, int index,
  2916. const char **clk_name)
  2917. {
  2918. if (display->fw)
  2919. dsi_parser_read_string_index(display->parser_node,
  2920. dsi_clk_name, index, clk_name);
  2921. else
  2922. of_property_read_string_index(display->panel_node,
  2923. dsi_clk_name, index, clk_name);
  2924. }
  2925. static int dsi_display_clocks_init(struct dsi_display *display)
  2926. {
  2927. int i, rc = 0, num_clk = 0;
  2928. const char *clk_name;
  2929. const char *pll_byte = "pll_byte", *pll_dsi = "pll_dsi";
  2930. struct clk *dsi_clk;
  2931. struct dsi_clk_link_set *pll = &display->clock_info.pll_clks;
  2932. char *dsi_clock_name;
  2933. if (!strcmp(display->display_type, "primary"))
  2934. dsi_clock_name = "qcom,dsi-select-clocks";
  2935. else
  2936. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2937. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2938. for (i = 0; i < num_clk; i++) {
  2939. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2940. &clk_name);
  2941. DSI_DEBUG("clock name:%s\n", clk_name);
  2942. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2943. if (IS_ERR_OR_NULL(dsi_clk)) {
  2944. rc = PTR_ERR(dsi_clk);
  2945. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2946. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2947. pll->byte_clk = NULL;
  2948. goto error;
  2949. }
  2950. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2951. pll->pixel_clk = NULL;
  2952. goto error;
  2953. }
  2954. }
  2955. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2956. pll->byte_clk = dsi_clk;
  2957. continue;
  2958. }
  2959. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2960. pll->pixel_clk = dsi_clk;
  2961. continue;
  2962. }
  2963. }
  2964. return 0;
  2965. error:
  2966. return rc;
  2967. }
  2968. static int dsi_display_clk_ctrl_cb(void *priv,
  2969. struct dsi_clk_ctrl_info clk_state_info)
  2970. {
  2971. int rc = 0;
  2972. struct dsi_display *display = NULL;
  2973. void *clk_handle = NULL;
  2974. if (!priv) {
  2975. DSI_ERR("Invalid params\n");
  2976. return -EINVAL;
  2977. }
  2978. display = priv;
  2979. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2980. clk_handle = display->mdp_clk_handle;
  2981. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2982. clk_handle = display->dsi_clk_handle;
  2983. } else {
  2984. DSI_ERR("invalid clk handle, return error\n");
  2985. return -EINVAL;
  2986. }
  2987. /*
  2988. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2989. * to turn off DSI clocks.
  2990. */
  2991. rc = dsi_display_clk_ctrl(clk_handle,
  2992. clk_state_info.clk_type, clk_state_info.clk_state);
  2993. if (rc) {
  2994. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2995. display->name, clk_state_info.clk_state,
  2996. clk_state_info.clk_type, rc);
  2997. return rc;
  2998. }
  2999. return 0;
  3000. }
  3001. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  3002. {
  3003. int i;
  3004. struct dsi_display_ctrl *ctrl;
  3005. if (!display)
  3006. return;
  3007. display_for_each_ctrl(i, display) {
  3008. ctrl = &display->ctrl[i];
  3009. if (!ctrl)
  3010. continue;
  3011. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  3012. }
  3013. }
  3014. int dsi_pre_clkoff_cb(void *priv,
  3015. enum dsi_clk_type clk,
  3016. enum dsi_lclk_type l_type,
  3017. enum dsi_clk_state new_state)
  3018. {
  3019. int rc = 0, i;
  3020. struct dsi_display *display = priv;
  3021. struct dsi_display_ctrl *ctrl;
  3022. /*
  3023. * If Idle Power Collapse occurs immediately after a CMD
  3024. * transfer with an asynchronous wait for DMA done, ensure
  3025. * that the work queued is scheduled and completed before turning
  3026. * off the clocks and disabling interrupts to validate the command
  3027. * transfer.
  3028. */
  3029. display_for_each_ctrl(i, display) {
  3030. ctrl = &display->ctrl[i];
  3031. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  3032. continue;
  3033. flush_workqueue(display->dma_cmd_workq);
  3034. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  3035. ctrl->ctrl->dma_wait_queued = false;
  3036. }
  3037. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3038. (l_type & DSI_LINK_LP_CLK)) {
  3039. /*
  3040. * If continuous clock is enabled then disable it
  3041. * before entering into ULPS Mode.
  3042. */
  3043. if (display->panel->host_config.force_hs_clk_lane)
  3044. _dsi_display_continuous_clk_ctrl(display, false);
  3045. /*
  3046. * If ULPS feature is enabled, enter ULPS first.
  3047. * However, when blanking the panel, we should enter ULPS
  3048. * only if ULPS during suspend feature is enabled.
  3049. */
  3050. if (!dsi_panel_initialized(display->panel)) {
  3051. if (display->panel->ulps_suspend_enabled)
  3052. rc = dsi_display_set_ulps(display, true);
  3053. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  3054. rc = dsi_display_set_ulps(display, true);
  3055. }
  3056. if (rc)
  3057. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  3058. __func__, rc);
  3059. }
  3060. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3061. (l_type & DSI_LINK_HS_CLK)) {
  3062. /*
  3063. * PHY clock gating should be disabled before the PLL and the
  3064. * branch clocks are turned off. Otherwise, it is possible that
  3065. * the clock RCGs may not be turned off correctly resulting
  3066. * in clock warnings.
  3067. */
  3068. rc = dsi_display_config_clk_gating(display, false);
  3069. if (rc)
  3070. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  3071. display->name, rc);
  3072. }
  3073. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  3074. /*
  3075. * Enable DSI clamps only if entering idle power collapse or
  3076. * when ULPS during suspend is enabled..
  3077. */
  3078. if (dsi_panel_initialized(display->panel) ||
  3079. display->panel->ulps_suspend_enabled) {
  3080. dsi_display_phy_idle_off(display);
  3081. rc = dsi_display_set_clamp(display, true);
  3082. if (rc)
  3083. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  3084. __func__, rc);
  3085. rc = dsi_display_phy_reset_config(display, false);
  3086. if (rc)
  3087. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3088. __func__, rc);
  3089. } else {
  3090. /* Make sure that controller is not in ULPS state when
  3091. * the DSI link is not active.
  3092. */
  3093. rc = dsi_display_set_ulps(display, false);
  3094. if (rc)
  3095. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  3096. __func__, rc);
  3097. }
  3098. /* dsi will not be able to serve irqs from here on */
  3099. dsi_display_ctrl_irq_update(display, false);
  3100. /* cache the MISR values */
  3101. display_for_each_ctrl(i, display) {
  3102. ctrl = &display->ctrl[i];
  3103. if (!ctrl->ctrl)
  3104. continue;
  3105. dsi_ctrl_cache_misr(ctrl->ctrl);
  3106. }
  3107. }
  3108. return rc;
  3109. }
  3110. int dsi_post_clkon_cb(void *priv,
  3111. enum dsi_clk_type clk,
  3112. enum dsi_lclk_type l_type,
  3113. enum dsi_clk_state curr_state)
  3114. {
  3115. int rc = 0;
  3116. struct dsi_display *display = priv;
  3117. bool mmss_clamp = false;
  3118. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3119. mmss_clamp = display->clamp_enabled;
  3120. /*
  3121. * controller setup is needed if coming out of idle
  3122. * power collapse with clamps enabled.
  3123. */
  3124. if (mmss_clamp)
  3125. dsi_display_ctrl_setup(display);
  3126. /*
  3127. * Phy setup is needed if coming out of idle
  3128. * power collapse with clamps enabled.
  3129. */
  3130. if (display->phy_idle_power_off || mmss_clamp)
  3131. dsi_display_phy_idle_on(display, mmss_clamp);
  3132. if (display->ulps_enabled && mmss_clamp) {
  3133. /*
  3134. * ULPS Entry Request. This is needed if the lanes were
  3135. * in ULPS prior to power collapse, since after
  3136. * power collapse and reset, the DSI controller resets
  3137. * back to idle state and not ULPS. This ulps entry
  3138. * request will transition the state of the DSI
  3139. * controller to ULPS which will match the state of the
  3140. * DSI phy. This needs to be done prior to disabling
  3141. * the DSI clamps.
  3142. *
  3143. * Also, reset the ulps flag so that ulps_config
  3144. * function would reconfigure the controller state to
  3145. * ULPS.
  3146. */
  3147. display->ulps_enabled = false;
  3148. rc = dsi_display_set_ulps(display, true);
  3149. if (rc) {
  3150. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3151. __func__, rc);
  3152. goto error;
  3153. }
  3154. }
  3155. rc = dsi_display_phy_reset_config(display, true);
  3156. if (rc) {
  3157. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3158. __func__, rc);
  3159. goto error;
  3160. }
  3161. rc = dsi_display_set_clamp(display, false);
  3162. if (rc) {
  3163. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3164. __func__, rc);
  3165. goto error;
  3166. }
  3167. }
  3168. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3169. /*
  3170. * Toggle the resync FIFO everytime clock changes, except
  3171. * when cont-splash screen transition is going on.
  3172. * Toggling resync FIFO during cont splash transition
  3173. * can lead to blinks on the display.
  3174. */
  3175. if (!display->is_cont_splash_enabled)
  3176. dsi_display_toggle_resync_fifo(display);
  3177. if (display->ulps_enabled) {
  3178. rc = dsi_display_set_ulps(display, false);
  3179. if (rc) {
  3180. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3181. __func__, rc);
  3182. goto error;
  3183. }
  3184. }
  3185. if (display->panel->host_config.force_hs_clk_lane)
  3186. _dsi_display_continuous_clk_ctrl(display, true);
  3187. rc = dsi_display_config_clk_gating(display, true);
  3188. if (rc) {
  3189. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3190. display->name, rc);
  3191. goto error;
  3192. }
  3193. }
  3194. /* enable dsi to serve irqs */
  3195. if (clk & DSI_CORE_CLK)
  3196. dsi_display_ctrl_irq_update(display, true);
  3197. error:
  3198. return rc;
  3199. }
  3200. int dsi_post_clkoff_cb(void *priv,
  3201. enum dsi_clk_type clk_type,
  3202. enum dsi_lclk_type l_type,
  3203. enum dsi_clk_state curr_state)
  3204. {
  3205. int rc = 0;
  3206. struct dsi_display *display = priv;
  3207. if (!display) {
  3208. DSI_ERR("%s: Invalid arg\n", __func__);
  3209. return -EINVAL;
  3210. }
  3211. if ((clk_type & DSI_CORE_CLK) &&
  3212. (curr_state == DSI_CLK_OFF)) {
  3213. rc = dsi_display_phy_power_off(display);
  3214. if (rc)
  3215. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3216. display->name, rc);
  3217. rc = dsi_display_ctrl_power_off(display);
  3218. if (rc)
  3219. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3220. display->name, rc);
  3221. }
  3222. return rc;
  3223. }
  3224. int dsi_pre_clkon_cb(void *priv,
  3225. enum dsi_clk_type clk_type,
  3226. enum dsi_lclk_type l_type,
  3227. enum dsi_clk_state new_state)
  3228. {
  3229. int rc = 0;
  3230. struct dsi_display *display = priv;
  3231. if (!display) {
  3232. DSI_ERR("%s: invalid input\n", __func__);
  3233. return -EINVAL;
  3234. }
  3235. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3236. /*
  3237. * Enable DSI core power
  3238. * 1.> PANEL_PM are controlled as part of
  3239. * panel_power_ctrl. Needed not be handled here.
  3240. * 2.> CTRL_PM need to be enabled/disabled
  3241. * only during unblank/blank. Their state should
  3242. * not be changed during static screen.
  3243. */
  3244. DSI_DEBUG("updating power states for ctrl and phy\n");
  3245. rc = dsi_display_ctrl_power_on(display);
  3246. if (rc) {
  3247. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3248. display->name, rc);
  3249. return rc;
  3250. }
  3251. rc = dsi_display_phy_power_on(display);
  3252. if (rc) {
  3253. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3254. display->name, rc);
  3255. return rc;
  3256. }
  3257. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3258. }
  3259. return rc;
  3260. }
  3261. static void __set_lane_map_v2(u8 *lane_map_v2,
  3262. enum dsi_phy_data_lanes lane0,
  3263. enum dsi_phy_data_lanes lane1,
  3264. enum dsi_phy_data_lanes lane2,
  3265. enum dsi_phy_data_lanes lane3)
  3266. {
  3267. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3268. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3269. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3270. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3271. }
  3272. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3273. {
  3274. int rc = 0, i = 0;
  3275. const char *data;
  3276. u8 temp[DSI_LANE_MAX - 1];
  3277. if (!display) {
  3278. DSI_ERR("invalid params\n");
  3279. return -EINVAL;
  3280. }
  3281. /* lane-map-v2 supersedes lane-map-v1 setting */
  3282. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3283. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3284. if (!rc) {
  3285. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3286. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3287. return 0;
  3288. } else if (rc != EINVAL) {
  3289. DSI_DEBUG("Incorrect mapping, configure default\n");
  3290. goto set_default;
  3291. }
  3292. /* lane-map older version, for DSI controller version < 2.0 */
  3293. data = of_get_property(display->pdev->dev.of_node,
  3294. "qcom,lane-map", NULL);
  3295. if (!data)
  3296. goto set_default;
  3297. if (!strcmp(data, "lane_map_3012")) {
  3298. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3299. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3300. DSI_PHYSICAL_LANE_1,
  3301. DSI_PHYSICAL_LANE_2,
  3302. DSI_PHYSICAL_LANE_3,
  3303. DSI_PHYSICAL_LANE_0);
  3304. } else if (!strcmp(data, "lane_map_2301")) {
  3305. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3306. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3307. DSI_PHYSICAL_LANE_2,
  3308. DSI_PHYSICAL_LANE_3,
  3309. DSI_PHYSICAL_LANE_0,
  3310. DSI_PHYSICAL_LANE_1);
  3311. } else if (!strcmp(data, "lane_map_1230")) {
  3312. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3313. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3314. DSI_PHYSICAL_LANE_3,
  3315. DSI_PHYSICAL_LANE_0,
  3316. DSI_PHYSICAL_LANE_1,
  3317. DSI_PHYSICAL_LANE_2);
  3318. } else if (!strcmp(data, "lane_map_0321")) {
  3319. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3320. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3321. DSI_PHYSICAL_LANE_0,
  3322. DSI_PHYSICAL_LANE_3,
  3323. DSI_PHYSICAL_LANE_2,
  3324. DSI_PHYSICAL_LANE_1);
  3325. } else if (!strcmp(data, "lane_map_1032")) {
  3326. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3327. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3328. DSI_PHYSICAL_LANE_1,
  3329. DSI_PHYSICAL_LANE_0,
  3330. DSI_PHYSICAL_LANE_3,
  3331. DSI_PHYSICAL_LANE_2);
  3332. } else if (!strcmp(data, "lane_map_2103")) {
  3333. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3334. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3335. DSI_PHYSICAL_LANE_2,
  3336. DSI_PHYSICAL_LANE_1,
  3337. DSI_PHYSICAL_LANE_0,
  3338. DSI_PHYSICAL_LANE_3);
  3339. } else if (!strcmp(data, "lane_map_3210")) {
  3340. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3341. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3342. DSI_PHYSICAL_LANE_3,
  3343. DSI_PHYSICAL_LANE_2,
  3344. DSI_PHYSICAL_LANE_1,
  3345. DSI_PHYSICAL_LANE_0);
  3346. } else {
  3347. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3348. __func__, data);
  3349. goto set_default;
  3350. }
  3351. return 0;
  3352. set_default:
  3353. /* default lane mapping */
  3354. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3355. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3356. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3357. return 0;
  3358. }
  3359. static int dsi_display_get_phandle_index(
  3360. struct dsi_display *display,
  3361. const char *propname, int count, int index)
  3362. {
  3363. struct device_node *disp_node = display->panel_node;
  3364. u32 *val = NULL;
  3365. int rc = 0;
  3366. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3367. if (ZERO_OR_NULL_PTR(val)) {
  3368. rc = -ENOMEM;
  3369. goto end;
  3370. }
  3371. if (index >= count)
  3372. goto end;
  3373. if (display->fw)
  3374. rc = dsi_parser_read_u32_array(display->parser_node,
  3375. propname, val, count);
  3376. else
  3377. rc = of_property_read_u32_array(disp_node, propname,
  3378. val, count);
  3379. if (rc)
  3380. goto end;
  3381. rc = val[index];
  3382. DSI_DEBUG("%s index=%d\n", propname, rc);
  3383. end:
  3384. kfree(val);
  3385. return rc;
  3386. }
  3387. static bool dsi_display_validate_res(struct dsi_display *display)
  3388. {
  3389. struct device_node *of_node = display->pdev->dev.of_node;
  3390. struct of_phandle_iterator it;
  3391. bool ctrl_avail = false;
  3392. bool phy_avail = false;
  3393. /*
  3394. * At least if one of the controller or PHY is present or has been probed, the
  3395. * dsi_display_dev_probe can pass this check. Exact ctrl and PHY match will be
  3396. * done after the DT is parsed.
  3397. */
  3398. of_phandle_iterator_init(&it, of_node, "qcom,dsi-ctrl", NULL, 0);
  3399. while (of_phandle_iterator_next(&it) == 0)
  3400. ctrl_avail |= dsi_ctrl_check_resource(it.node);
  3401. of_phandle_iterator_init(&it, of_node, "qcom,dsi-phy", NULL, 0);
  3402. while (of_phandle_iterator_next(&it) == 0)
  3403. phy_avail |= dsi_phy_check_resource(it.node);
  3404. return (ctrl_avail & phy_avail);
  3405. }
  3406. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3407. const char *propname)
  3408. {
  3409. if (display->fw)
  3410. return dsi_parser_count_u32_elems(display->parser_node,
  3411. propname);
  3412. else
  3413. return of_property_count_u32_elems(display->panel_node,
  3414. propname);
  3415. }
  3416. static int dsi_display_parse_dt(struct dsi_display *display)
  3417. {
  3418. int i, rc = 0;
  3419. u32 phy_count = 0;
  3420. struct device_node *of_node = display->pdev->dev.of_node;
  3421. char *dsi_ctrl_name, *dsi_phy_name;
  3422. if (!strcmp(display->display_type, "primary")) {
  3423. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3424. dsi_phy_name = "qcom,dsi-phy-num";
  3425. } else {
  3426. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3427. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3428. }
  3429. display->ctrl_count = dsi_display_get_phandle_count(display,
  3430. dsi_ctrl_name);
  3431. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3432. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3433. display->ctrl_count, phy_count);
  3434. if (!phy_count || !display->ctrl_count) {
  3435. DSI_ERR("no ctrl/phys found\n");
  3436. rc = -ENODEV;
  3437. goto error;
  3438. }
  3439. if (phy_count != display->ctrl_count) {
  3440. DSI_ERR("different ctrl and phy counts\n");
  3441. rc = -ENODEV;
  3442. goto error;
  3443. }
  3444. display_for_each_ctrl(i, display) {
  3445. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3446. int index;
  3447. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3448. display->ctrl_count, i);
  3449. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3450. "qcom,dsi-ctrl", index);
  3451. of_node_put(ctrl->ctrl_of_node);
  3452. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3453. display->ctrl_count, i);
  3454. ctrl->phy_of_node = of_parse_phandle(of_node,
  3455. "qcom,dsi-phy", index);
  3456. of_node_put(ctrl->phy_of_node);
  3457. }
  3458. /* Parse TE data */
  3459. dsi_display_parse_te_data(display);
  3460. /* Parse all external bridges from port 0 */
  3461. display_for_each_ctrl(i, display) {
  3462. display->ext_bridge[i].node_of =
  3463. of_graph_get_remote_node(of_node, 0, i);
  3464. if (display->ext_bridge[i].node_of)
  3465. display->ext_bridge_cnt++;
  3466. else
  3467. break;
  3468. }
  3469. /* Parse Demura data */
  3470. dsi_display_parse_demura_data(display);
  3471. DSI_DEBUG("success\n");
  3472. error:
  3473. return rc;
  3474. }
  3475. static bool dsi_display_validate_panel_resources(struct dsi_display *display)
  3476. {
  3477. if (!is_sim_panel(display)) {
  3478. if (!gpio_is_valid(display->panel->reset_config.reset_gpio)) {
  3479. DSI_ERR("invalid reset gpio for the panel\n");
  3480. return false;
  3481. }
  3482. } else {
  3483. display->panel->power_info.count = 0;
  3484. DSI_DEBUG("no dir set and no request for gpios in sim panel\n");
  3485. }
  3486. return true;
  3487. }
  3488. static int dsi_display_res_init(struct dsi_display *display)
  3489. {
  3490. int rc = 0;
  3491. int i;
  3492. struct dsi_display_ctrl *ctrl;
  3493. display_for_each_ctrl(i, display) {
  3494. ctrl = &display->ctrl[i];
  3495. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3496. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3497. rc = PTR_ERR(ctrl->ctrl);
  3498. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3499. ctrl->ctrl = NULL;
  3500. goto error_ctrl_put;
  3501. }
  3502. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3503. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3504. rc = PTR_ERR(ctrl->phy);
  3505. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3506. dsi_ctrl_put(ctrl->ctrl);
  3507. ctrl->phy = NULL;
  3508. goto error_ctrl_put;
  3509. }
  3510. }
  3511. display->panel = dsi_panel_get(&display->pdev->dev,
  3512. display->panel_node,
  3513. display->parser_node,
  3514. display->display_type,
  3515. display->cmdline_topology,
  3516. display->trusted_vm_env);
  3517. if (IS_ERR_OR_NULL(display->panel)) {
  3518. rc = PTR_ERR(display->panel);
  3519. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3520. display->panel = NULL;
  3521. goto error_ctrl_put;
  3522. }
  3523. display->panel->te_using_watchdog_timer |= display->sw_te_using_wd;
  3524. if (!dsi_display_validate_panel_resources(display))
  3525. goto error_ctrl_put;
  3526. display_for_each_ctrl(i, display) {
  3527. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3528. struct dsi_host_common_cfg *host = &display->panel->host_config;
  3529. phy->cfg.force_clk_lane_hs =
  3530. display->panel->host_config.force_hs_clk_lane;
  3531. phy->cfg.phy_type =
  3532. display->panel->host_config.phy_type;
  3533. /*
  3534. * Parse the dynamic clock trim codes for PLL, for video mode panels that have
  3535. * dynamic clock property set.
  3536. */
  3537. if ((display->panel->dyn_clk_caps.dyn_clk_support) &&
  3538. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  3539. dsi_phy_pll_parse_dfps_data(phy);
  3540. phy->cfg.split_link.enabled = host->split_link.enabled;
  3541. phy->cfg.split_link.num_sublinks = host->split_link.num_sublinks;
  3542. phy->cfg.split_link.lanes_per_sublink = host->split_link.lanes_per_sublink;
  3543. }
  3544. rc = dsi_display_parse_lane_map(display);
  3545. if (rc) {
  3546. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3547. goto error_ctrl_put;
  3548. }
  3549. rc = dsi_display_clocks_init(display);
  3550. if (rc) {
  3551. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3552. goto error_ctrl_put;
  3553. }
  3554. /**
  3555. * In trusted vm, the connectors will not be enabled
  3556. * until the HW resources are assigned and accepted.
  3557. */
  3558. if (display->trusted_vm_env) {
  3559. display->is_active = false;
  3560. display->hw_ownership = false;
  3561. } else {
  3562. display->is_active = true;
  3563. display->hw_ownership = true;
  3564. }
  3565. return 0;
  3566. error_ctrl_put:
  3567. for (i = i - 1; i >= 0; i--) {
  3568. ctrl = &display->ctrl[i];
  3569. dsi_ctrl_put(ctrl->ctrl);
  3570. dsi_phy_put(ctrl->phy);
  3571. }
  3572. return rc;
  3573. }
  3574. static int dsi_display_res_deinit(struct dsi_display *display)
  3575. {
  3576. int rc = 0;
  3577. int i;
  3578. struct dsi_display_ctrl *ctrl;
  3579. display_for_each_ctrl(i, display) {
  3580. ctrl = &display->ctrl[i];
  3581. dsi_phy_put(ctrl->phy);
  3582. dsi_ctrl_put(ctrl->ctrl);
  3583. }
  3584. if (display->panel)
  3585. dsi_panel_put(display->panel);
  3586. return rc;
  3587. }
  3588. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3589. struct dsi_display_mode *mode,
  3590. u32 flags)
  3591. {
  3592. int rc = 0;
  3593. int i;
  3594. struct dsi_display_ctrl *ctrl;
  3595. /*
  3596. * To set a mode:
  3597. * 1. Controllers should be turned off.
  3598. * 2. Link clocks should be off.
  3599. * 3. Phy should be disabled.
  3600. */
  3601. display_for_each_ctrl(i, display) {
  3602. ctrl = &display->ctrl[i];
  3603. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3604. (ctrl->phy_enabled)) {
  3605. rc = -EINVAL;
  3606. goto error;
  3607. }
  3608. }
  3609. error:
  3610. return rc;
  3611. }
  3612. static bool dsi_display_is_seamless_dfps_possible(
  3613. const struct dsi_display *display,
  3614. const struct dsi_display_mode *tgt,
  3615. const enum dsi_dfps_type dfps_type)
  3616. {
  3617. struct dsi_display_mode *cur;
  3618. if (!display || !tgt || !display->panel) {
  3619. DSI_ERR("Invalid params\n");
  3620. return false;
  3621. }
  3622. cur = display->panel->cur_mode;
  3623. if (cur->timing.h_active != tgt->timing.h_active) {
  3624. DSI_DEBUG("timing.h_active differs %d %d\n",
  3625. cur->timing.h_active, tgt->timing.h_active);
  3626. return false;
  3627. }
  3628. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3629. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3630. cur->timing.h_back_porch,
  3631. tgt->timing.h_back_porch);
  3632. return false;
  3633. }
  3634. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3635. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3636. cur->timing.h_sync_width,
  3637. tgt->timing.h_sync_width);
  3638. return false;
  3639. }
  3640. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3641. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3642. cur->timing.h_front_porch,
  3643. tgt->timing.h_front_porch);
  3644. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3645. return false;
  3646. }
  3647. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3648. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3649. cur->timing.h_skew,
  3650. tgt->timing.h_skew);
  3651. return false;
  3652. }
  3653. /* skip polarity comparison */
  3654. if (cur->timing.v_active != tgt->timing.v_active) {
  3655. DSI_DEBUG("timing.v_active differs %d %d\n",
  3656. cur->timing.v_active,
  3657. tgt->timing.v_active);
  3658. return false;
  3659. }
  3660. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3661. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3662. cur->timing.v_back_porch,
  3663. tgt->timing.v_back_porch);
  3664. return false;
  3665. }
  3666. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3667. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3668. cur->timing.v_sync_width,
  3669. tgt->timing.v_sync_width);
  3670. return false;
  3671. }
  3672. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3673. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3674. cur->timing.v_front_porch,
  3675. tgt->timing.v_front_porch);
  3676. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3677. return false;
  3678. }
  3679. /* skip polarity comparison */
  3680. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3681. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3682. cur->timing.refresh_rate,
  3683. tgt->timing.refresh_rate);
  3684. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3685. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3686. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3687. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3688. DSI_DEBUG("flags differs %d %d\n",
  3689. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3690. return true;
  3691. }
  3692. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3693. {
  3694. struct dsi_host_common_cfg *config;
  3695. struct dsi_display_ctrl *m_ctrl;
  3696. int phy_ver;
  3697. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3698. config = &display->panel->host_config;
  3699. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3700. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3701. config->byte_intf_clk_div = 1;
  3702. else
  3703. config->byte_intf_clk_div = 2;
  3704. }
  3705. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3706. u32 bit_clk_rate)
  3707. {
  3708. int rc = 0;
  3709. int i;
  3710. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3711. if (!display->panel) {
  3712. DSI_ERR("Invalid params\n");
  3713. return -EINVAL;
  3714. }
  3715. if (bit_clk_rate == 0) {
  3716. DSI_ERR("Invalid bit clock rate\n");
  3717. return -EINVAL;
  3718. }
  3719. display->config.bit_clk_rate_hz = bit_clk_rate;
  3720. display_for_each_ctrl(i, display) {
  3721. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3722. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3723. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3724. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3725. byte_intf_clk_rate;
  3726. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3727. struct dsi_host_common_cfg *host_cfg;
  3728. mutex_lock(&ctrl->ctrl_lock);
  3729. host_cfg = &display->panel->host_config;
  3730. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3731. num_of_lanes++;
  3732. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3733. num_of_lanes++;
  3734. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3735. num_of_lanes++;
  3736. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3737. num_of_lanes++;
  3738. if (num_of_lanes == 0) {
  3739. DSI_ERR("Invalid lane count\n");
  3740. rc = -EINVAL;
  3741. goto error;
  3742. }
  3743. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3744. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3745. bit_rate_per_lane = bit_rate;
  3746. do_div(bit_rate_per_lane, num_of_lanes);
  3747. pclk_rate = bit_rate;
  3748. do_div(pclk_rate, bpp);
  3749. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3750. bit_rate_per_lane = bit_rate;
  3751. do_div(bit_rate_per_lane, num_of_lanes);
  3752. byte_clk_rate = bit_rate_per_lane;
  3753. do_div(byte_clk_rate, 8);
  3754. byte_intf_clk_rate = byte_clk_rate;
  3755. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3756. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3757. } else {
  3758. bit_rate_per_lane = bit_clk_rate;
  3759. pclk_rate *= bits_per_symbol;
  3760. do_div(pclk_rate, num_of_symbols);
  3761. byte_clk_rate = bit_clk_rate;
  3762. do_div(byte_clk_rate, num_of_symbols);
  3763. /* For CPHY, byte_intf_clk is same as byte_clk */
  3764. byte_intf_clk_rate = byte_clk_rate;
  3765. }
  3766. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3767. bit_rate, bit_rate_per_lane);
  3768. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3769. byte_clk_rate, byte_intf_clk_rate);
  3770. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3771. SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
  3772. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3773. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3774. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3775. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3776. ctrl->clk_freq, ctrl->cell_index);
  3777. if (rc) {
  3778. DSI_ERR("Failed to update link frequencies\n");
  3779. goto error;
  3780. }
  3781. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3782. error:
  3783. mutex_unlock(&ctrl->ctrl_lock);
  3784. /* TODO: recover ctrl->clk_freq in case of failure */
  3785. if (rc)
  3786. return rc;
  3787. }
  3788. return 0;
  3789. }
  3790. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3791. struct dsi_dyn_clk_delay *delay,
  3792. struct dsi_display_mode *mode)
  3793. {
  3794. u32 esc_clk_rate_hz;
  3795. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3796. u32 hsync_period = 0;
  3797. struct dsi_display_ctrl *m_ctrl;
  3798. struct dsi_ctrl *dsi_ctrl;
  3799. struct dsi_phy_cfg *cfg;
  3800. int phy_ver;
  3801. m_ctrl = &display->ctrl[display->clk_master_idx];
  3802. dsi_ctrl = m_ctrl->ctrl;
  3803. cfg = &(m_ctrl->phy->cfg);
  3804. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3805. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3806. esc_clk_rate_hz);
  3807. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3808. esc_clk_rate_hz);
  3809. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3810. esc_clk_rate_hz);
  3811. hsync_period = dsi_h_total_dce(&mode->timing);
  3812. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3813. if (!display->panel->video_config.eof_bllp_lp11_en)
  3814. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3815. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3816. (display->config.common_config.t_clk_post + 1)) /
  3817. byte_to_esc_ratio) +
  3818. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3819. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3820. ((cfg->timing.lane_v3[3] * 4) +
  3821. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3822. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3823. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3824. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3825. hr_bit_to_esc_ratio);
  3826. delay->pipe_delay2 = 0;
  3827. if (display->panel->host_config.force_hs_clk_lane)
  3828. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3829. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3830. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3831. hr_bit_to_esc_ratio);
  3832. /*
  3833. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3834. * 25us pll delay recommended for phy ver 4.0
  3835. */
  3836. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3837. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3838. delay->pll_delay = 100;
  3839. else
  3840. delay->pll_delay = 25;
  3841. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3842. }
  3843. /*
  3844. * dsi_display_is_type_cphy - check if panel type is cphy
  3845. * @display: Pointer to private display structure
  3846. * Returns: True if panel type is cphy
  3847. */
  3848. static inline bool dsi_display_is_type_cphy(struct dsi_display *display)
  3849. {
  3850. return (display->panel->host_config.phy_type ==
  3851. DSI_PHY_TYPE_CPHY) ? true : false;
  3852. }
  3853. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3854. struct link_clk_freq *bkp_freq)
  3855. {
  3856. int rc = 0, i;
  3857. u8 ctrl_version;
  3858. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3859. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3860. struct dsi_clk_link_set *enable_clk;
  3861. m_ctrl = &display->ctrl[display->clk_master_idx];
  3862. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3863. ctrl_version = m_ctrl->ctrl->version;
  3864. enable_clk = &display->clock_info.pll_clks;
  3865. dsi_clk_prepare_enable(enable_clk);
  3866. dsi_display_phy_configure(display, false);
  3867. display_for_each_ctrl(i, display) {
  3868. ctrl = &display->ctrl[i];
  3869. if (!ctrl->ctrl)
  3870. continue;
  3871. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3872. ctrl->ctrl->clk_freq.byte_clk_rate,
  3873. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3874. if (rc) {
  3875. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3876. goto recover_byte_clk;
  3877. }
  3878. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3879. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3880. if (rc) {
  3881. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3882. goto recover_pix_clk;
  3883. }
  3884. }
  3885. display_for_each_ctrl(i, display) {
  3886. ctrl = &display->ctrl[i];
  3887. if (ctrl == m_ctrl)
  3888. continue;
  3889. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3890. }
  3891. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3892. /*
  3893. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3894. * and with constant fps, as dynamic refresh will applied with
  3895. * next mdp intf ctrl flush.
  3896. */
  3897. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3898. (dyn_clk_caps->maintain_const_fps))
  3899. return 0;
  3900. /* wait for dynamic refresh done */
  3901. display_for_each_ctrl(i, display) {
  3902. ctrl = &display->ctrl[i];
  3903. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3904. if (rc) {
  3905. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3906. goto recover_pix_clk;
  3907. } else {
  3908. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3909. i ? "slave" : "master");
  3910. }
  3911. }
  3912. display_for_each_ctrl(i, display) {
  3913. ctrl = &display->ctrl[i];
  3914. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3915. }
  3916. if (rc)
  3917. DSI_ERR("could not switch back to src clks %d\n", rc);
  3918. dsi_clk_disable_unprepare(enable_clk);
  3919. return rc;
  3920. recover_pix_clk:
  3921. display_for_each_ctrl(i, display) {
  3922. ctrl = &display->ctrl[i];
  3923. if (!ctrl->ctrl)
  3924. continue;
  3925. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3926. bkp_freq->pix_clk_rate, i);
  3927. }
  3928. recover_byte_clk:
  3929. display_for_each_ctrl(i, display) {
  3930. ctrl = &display->ctrl[i];
  3931. if (!ctrl->ctrl)
  3932. continue;
  3933. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3934. bkp_freq->byte_clk_rate,
  3935. bkp_freq->byte_intf_clk_rate, i);
  3936. }
  3937. return rc;
  3938. }
  3939. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3940. struct dsi_display_mode *mode)
  3941. {
  3942. int rc = 0, mask, i;
  3943. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3944. struct dsi_dyn_clk_delay delay;
  3945. struct link_clk_freq bkp_freq;
  3946. dsi_panel_acquire_panel_lock(display->panel);
  3947. m_ctrl = &display->ctrl[display->clk_master_idx];
  3948. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3949. /* mask PLL unlock, FIFO overflow and underflow errors */
  3950. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3951. BIT(DSI_FIFO_OVERFLOW);
  3952. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3953. /* update the phy timings based on new mode */
  3954. display_for_each_ctrl(i, display) {
  3955. ctrl = &display->ctrl[i];
  3956. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3957. }
  3958. /* back up existing rates to handle failure case */
  3959. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3960. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3961. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3962. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3963. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3964. if (rc) {
  3965. DSI_ERR("failed set link frequencies %d\n", rc);
  3966. goto exit;
  3967. }
  3968. /* calculate pipe delays */
  3969. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3970. /* configure dynamic refresh ctrl registers */
  3971. display_for_each_ctrl(i, display) {
  3972. ctrl = &display->ctrl[i];
  3973. if (!ctrl->phy)
  3974. continue;
  3975. if (ctrl == m_ctrl)
  3976. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3977. else
  3978. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3979. false);
  3980. }
  3981. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3982. exit:
  3983. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3984. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3985. DSI_CLK_OFF);
  3986. /* store newly calculated phy timings in mode private info */
  3987. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3988. mode->priv_info->phy_timing_val,
  3989. mode->priv_info->phy_timing_len);
  3990. dsi_panel_release_panel_lock(display->panel);
  3991. return rc;
  3992. }
  3993. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3994. int clk_rate)
  3995. {
  3996. int rc = 0;
  3997. if (clk_rate <= 0) {
  3998. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3999. return -EINVAL;
  4000. }
  4001. if (clk_rate == display->cached_clk_rate) {
  4002. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  4003. return rc;
  4004. }
  4005. display->cached_clk_rate = clk_rate;
  4006. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  4007. if (!rc) {
  4008. DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
  4009. __func__, clk_rate);
  4010. atomic_set(&display->clkrate_change_pending, 1);
  4011. } else {
  4012. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  4013. __func__, clk_rate, rc);
  4014. /* Caching clock failed, so don't go on doing so. */
  4015. atomic_set(&display->clkrate_change_pending, 0);
  4016. display->cached_clk_rate = 0;
  4017. }
  4018. return rc;
  4019. }
  4020. static int dsi_display_dfps_update(struct dsi_display *display,
  4021. struct dsi_display_mode *dsi_mode)
  4022. {
  4023. struct dsi_mode_info *timing;
  4024. struct dsi_display_ctrl *m_ctrl, *ctrl;
  4025. struct dsi_display_mode *panel_mode;
  4026. struct dsi_dfps_capabilities dfps_caps;
  4027. int rc = 0;
  4028. int i = 0;
  4029. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4030. if (!display || !dsi_mode || !display->panel) {
  4031. DSI_ERR("Invalid params\n");
  4032. return -EINVAL;
  4033. }
  4034. timing = &dsi_mode->timing;
  4035. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4036. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4037. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  4038. DSI_ERR("dfps or constant fps not supported\n");
  4039. return -ENOTSUPP;
  4040. }
  4041. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  4042. DSI_ERR("dfps clock method not supported\n");
  4043. return -ENOTSUPP;
  4044. }
  4045. /* For split DSI, update the clock master first */
  4046. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  4047. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  4048. m_ctrl = &display->ctrl[display->clk_master_idx];
  4049. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  4050. if (rc) {
  4051. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  4052. display->name, i, rc);
  4053. goto error;
  4054. }
  4055. /* Update the rest of the controllers */
  4056. display_for_each_ctrl(i, display) {
  4057. ctrl = &display->ctrl[i];
  4058. if (!ctrl->ctrl || (ctrl == m_ctrl))
  4059. continue;
  4060. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  4061. if (rc) {
  4062. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  4063. display->name, i, rc);
  4064. goto error;
  4065. }
  4066. }
  4067. panel_mode = display->panel->cur_mode;
  4068. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  4069. /*
  4070. * dsi_mode_flags flags are used to communicate with other drm driver
  4071. * components, and are transient. They aren't inherently part of the
  4072. * display panel's mode and shouldn't be saved into the cached currently
  4073. * active mode.
  4074. */
  4075. panel_mode->dsi_mode_flags = 0;
  4076. error:
  4077. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  4078. return rc;
  4079. }
  4080. static int dsi_display_dfps_calc_front_porch(
  4081. u32 old_fps,
  4082. u32 new_fps,
  4083. u32 a_total,
  4084. u32 b_total,
  4085. u32 b_fp,
  4086. u32 *b_fp_out)
  4087. {
  4088. s32 b_fp_new;
  4089. int add_porches, diff;
  4090. if (!b_fp_out) {
  4091. DSI_ERR("Invalid params\n");
  4092. return -EINVAL;
  4093. }
  4094. if (!a_total || !new_fps) {
  4095. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  4096. return -EINVAL;
  4097. }
  4098. /*
  4099. * Keep clock, other porches constant, use new fps, calc front porch
  4100. * new_vtotal = old_vtotal * (old_fps / new_fps )
  4101. * new_vfp - old_vfp = new_vtotal - old_vtotal
  4102. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  4103. */
  4104. diff = abs(old_fps - new_fps);
  4105. add_porches = mult_frac(b_total, diff, new_fps);
  4106. if (old_fps > new_fps)
  4107. b_fp_new = b_fp + add_porches;
  4108. else
  4109. b_fp_new = b_fp - add_porches;
  4110. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  4111. new_fps, a_total, b_total, b_fp, b_fp_new);
  4112. if (b_fp_new < 0) {
  4113. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  4114. return -EINVAL;
  4115. }
  4116. /**
  4117. * TODO: To differentiate from clock method when communicating to the
  4118. * other components, perhaps we should set clk here to original value
  4119. */
  4120. *b_fp_out = b_fp_new;
  4121. return 0;
  4122. }
  4123. /**
  4124. * dsi_display_get_dfps_timing() - Get the new dfps values.
  4125. * @display: DSI display handle.
  4126. * @adj_mode: Mode value structure to be changed.
  4127. * It contains old timing values and latest fps value.
  4128. * New timing values are updated based on new fps.
  4129. * @curr_refresh_rate: Current fps rate.
  4130. * If zero , current fps rate is taken from
  4131. * display->panel->cur_mode.
  4132. * Return: error code.
  4133. */
  4134. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  4135. struct dsi_display_mode *adj_mode,
  4136. u32 curr_refresh_rate)
  4137. {
  4138. struct dsi_dfps_capabilities dfps_caps;
  4139. struct dsi_display_mode per_ctrl_mode;
  4140. struct dsi_mode_info *timing;
  4141. struct dsi_ctrl *m_ctrl;
  4142. int rc = 0;
  4143. if (!display || !adj_mode) {
  4144. DSI_ERR("Invalid params\n");
  4145. return -EINVAL;
  4146. }
  4147. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  4148. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4149. if (!dfps_caps.dfps_support) {
  4150. DSI_ERR("dfps not supported by panel\n");
  4151. return -EINVAL;
  4152. }
  4153. per_ctrl_mode = *adj_mode;
  4154. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  4155. if (!curr_refresh_rate) {
  4156. if (!dsi_display_is_seamless_dfps_possible(display,
  4157. &per_ctrl_mode, dfps_caps.type)) {
  4158. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4159. return -EINVAL;
  4160. }
  4161. if (display->panel->cur_mode) {
  4162. curr_refresh_rate =
  4163. display->panel->cur_mode->timing.refresh_rate;
  4164. } else {
  4165. DSI_ERR("cur_mode is not initialized\n");
  4166. return -EINVAL;
  4167. }
  4168. }
  4169. /* TODO: Remove this direct reference to the dsi_ctrl */
  4170. timing = &per_ctrl_mode.timing;
  4171. switch (dfps_caps.type) {
  4172. case DSI_DFPS_IMMEDIATE_VFP:
  4173. rc = dsi_display_dfps_calc_front_porch(
  4174. curr_refresh_rate,
  4175. timing->refresh_rate,
  4176. dsi_h_total_dce(timing),
  4177. DSI_V_TOTAL(timing),
  4178. timing->v_front_porch,
  4179. &adj_mode->timing.v_front_porch);
  4180. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
  4181. curr_refresh_rate, timing->refresh_rate,
  4182. timing->v_front_porch, adj_mode->timing.v_front_porch);
  4183. break;
  4184. case DSI_DFPS_IMMEDIATE_HFP:
  4185. rc = dsi_display_dfps_calc_front_porch(
  4186. curr_refresh_rate,
  4187. timing->refresh_rate,
  4188. DSI_V_TOTAL(timing),
  4189. dsi_h_total_dce(timing),
  4190. timing->h_front_porch,
  4191. &adj_mode->timing.h_front_porch);
  4192. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
  4193. curr_refresh_rate, timing->refresh_rate,
  4194. timing->h_front_porch, adj_mode->timing.h_front_porch);
  4195. if (!rc)
  4196. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4197. break;
  4198. default:
  4199. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4200. rc = -ENOTSUPP;
  4201. }
  4202. return rc;
  4203. }
  4204. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4205. struct dsi_display_mode *adj_mode)
  4206. {
  4207. int rc = 0;
  4208. if (!display || !adj_mode) {
  4209. DSI_ERR("Invalid params\n");
  4210. return false;
  4211. }
  4212. /* Currently the only seamless transition is dynamic fps */
  4213. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4214. if (rc) {
  4215. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4216. } else {
  4217. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4218. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4219. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4220. }
  4221. return rc;
  4222. }
  4223. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4224. struct dsi_display_mode *to_mode)
  4225. {
  4226. u32 cur_fps, to_fps;
  4227. u32 cur_h_active, to_h_active;
  4228. u32 cur_v_active, to_v_active;
  4229. cur_fps = cur_mode->timing.refresh_rate;
  4230. to_fps = to_mode->timing.refresh_rate;
  4231. cur_h_active = cur_mode->timing.h_active;
  4232. cur_v_active = cur_mode->timing.v_active;
  4233. to_h_active = to_mode->timing.h_active;
  4234. to_v_active = to_mode->timing.v_active;
  4235. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4236. (cur_fps != to_fps)) {
  4237. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4238. DSI_DEBUG("DMS Modeset with FPS change\n");
  4239. } else {
  4240. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4241. }
  4242. }
  4243. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4244. struct dsi_display_mode *mode,
  4245. u32 flags)
  4246. {
  4247. int rc = 0, clk_rate = 0;
  4248. int i;
  4249. struct dsi_display_ctrl *ctrl;
  4250. struct dsi_display_ctrl *mctrl;
  4251. struct dsi_display_mode_priv_info *priv_info;
  4252. bool commit_phy_timing = false;
  4253. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4254. priv_info = mode->priv_info;
  4255. if (!priv_info) {
  4256. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4257. display->name);
  4258. return -EINVAL;
  4259. }
  4260. SDE_EVT32(mode->dsi_mode_flags, display->panel->panel_mode);
  4261. if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  4262. display->panel->panel_mode = DSI_OP_VIDEO_MODE;
  4263. else if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  4264. display->panel->panel_mode = DSI_OP_CMD_MODE;
  4265. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4266. mode,
  4267. &display->config);
  4268. if (rc) {
  4269. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4270. display->name, rc);
  4271. goto error;
  4272. }
  4273. memcpy(&display->config.lane_map, &display->lane_map,
  4274. sizeof(display->lane_map));
  4275. mctrl = &display->ctrl[display->clk_master_idx];
  4276. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4277. if (mode->dsi_mode_flags &
  4278. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4279. display_for_each_ctrl(i, display) {
  4280. ctrl = &display->ctrl[i];
  4281. if (!ctrl->ctrl || (ctrl != mctrl))
  4282. continue;
  4283. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4284. true);
  4285. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4286. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4287. (dyn_clk_caps->maintain_const_fps)) {
  4288. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4289. true);
  4290. }
  4291. }
  4292. rc = dsi_display_dfps_update(display, mode);
  4293. if (rc) {
  4294. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4295. display->name, rc);
  4296. goto error;
  4297. }
  4298. display_for_each_ctrl(i, display) {
  4299. ctrl = &display->ctrl[i];
  4300. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4301. &display->config, mode, mode->dsi_mode_flags,
  4302. display->dsi_clk_handle);
  4303. if (rc) {
  4304. DSI_ERR("failed to update ctrl config\n");
  4305. goto error;
  4306. }
  4307. }
  4308. if (priv_info->phy_timing_len) {
  4309. display_for_each_ctrl(i, display) {
  4310. ctrl = &display->ctrl[i];
  4311. rc = dsi_phy_set_timing_params(ctrl->phy,
  4312. priv_info->phy_timing_val,
  4313. priv_info->phy_timing_len,
  4314. commit_phy_timing);
  4315. if (rc)
  4316. DSI_ERR("Fail to add timing params\n");
  4317. }
  4318. }
  4319. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4320. return rc;
  4321. }
  4322. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4323. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4324. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4325. if (rc)
  4326. DSI_ERR("dynamic clk change failed %d\n", rc);
  4327. /*
  4328. * skip rest of the opearations since
  4329. * dsi_display_dynamic_clk_switch_vid() already takes
  4330. * care of them.
  4331. */
  4332. return rc;
  4333. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4334. clk_rate = mode->timing.clk_rate_hz;
  4335. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4336. clk_rate);
  4337. if (rc) {
  4338. DSI_ERR("Failed to configure dynamic clk\n");
  4339. return rc;
  4340. }
  4341. }
  4342. }
  4343. display_for_each_ctrl(i, display) {
  4344. ctrl = &display->ctrl[i];
  4345. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4346. mode, mode->dsi_mode_flags,
  4347. display->dsi_clk_handle);
  4348. if (rc) {
  4349. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4350. display->name, rc);
  4351. goto error;
  4352. }
  4353. }
  4354. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4355. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4356. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4357. u64 to_bitclk = mode->timing.clk_rate_hz;
  4358. commit_phy_timing = true;
  4359. /* No need to set clkrate pending flag if clocks are same */
  4360. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4361. atomic_set(&display->clkrate_change_pending, 1);
  4362. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4363. }
  4364. if (priv_info->phy_timing_len) {
  4365. display_for_each_ctrl(i, display) {
  4366. ctrl = &display->ctrl[i];
  4367. rc = dsi_phy_set_timing_params(ctrl->phy,
  4368. priv_info->phy_timing_val,
  4369. priv_info->phy_timing_len,
  4370. commit_phy_timing);
  4371. if (rc)
  4372. DSI_ERR("failed to add DSI PHY timing params\n");
  4373. }
  4374. }
  4375. error:
  4376. return rc;
  4377. }
  4378. /**
  4379. * _dsi_display_dev_init - initializes the display device
  4380. * Initialization will acquire references to the resources required for the
  4381. * display hardware to function.
  4382. * @display: Handle to the display
  4383. * Returns: Zero on success
  4384. */
  4385. static int _dsi_display_dev_init(struct dsi_display *display)
  4386. {
  4387. int rc = 0;
  4388. if (!display) {
  4389. DSI_ERR("invalid display\n");
  4390. return -EINVAL;
  4391. }
  4392. if (!display->panel_node && !display->fw)
  4393. return 0;
  4394. mutex_lock(&display->display_lock);
  4395. display->parser = dsi_parser_get(&display->pdev->dev);
  4396. if (display->fw && display->parser)
  4397. display->parser_node = dsi_parser_get_head_node(
  4398. display->parser, display->fw->data,
  4399. display->fw->size);
  4400. rc = dsi_display_parse_dt(display);
  4401. if (rc) {
  4402. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4403. goto error;
  4404. }
  4405. rc = dsi_display_res_init(display);
  4406. if (rc) {
  4407. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4408. display->name, rc);
  4409. goto error;
  4410. }
  4411. error:
  4412. mutex_unlock(&display->display_lock);
  4413. return rc;
  4414. }
  4415. /**
  4416. * _dsi_display_dev_deinit - deinitializes the display device
  4417. * All the resources acquired during device init will be released.
  4418. * @display: Handle to the display
  4419. * Returns: Zero on success
  4420. */
  4421. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4422. {
  4423. int rc = 0;
  4424. if (!display) {
  4425. DSI_ERR("invalid display\n");
  4426. return -EINVAL;
  4427. }
  4428. mutex_lock(&display->display_lock);
  4429. rc = dsi_display_res_deinit(display);
  4430. if (rc)
  4431. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4432. display->name, rc);
  4433. mutex_unlock(&display->display_lock);
  4434. return rc;
  4435. }
  4436. /**
  4437. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4438. * @dsi_display: Pointer to dsi display
  4439. * Returns: Zero on success
  4440. */
  4441. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4442. {
  4443. struct dsi_display *display = dsi_display;
  4444. int rc = 0;
  4445. /* Remove the panel vote that was added during dsi display probe */
  4446. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4447. if (rc)
  4448. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4449. display->panel->name, rc);
  4450. return rc;
  4451. }
  4452. /**
  4453. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4454. * @dsi_display: Pointer to dsi display
  4455. * Returns: Zero on success
  4456. */
  4457. int dsi_display_cont_splash_config(void *dsi_display)
  4458. {
  4459. struct dsi_display *display = dsi_display;
  4460. int rc = 0;
  4461. /* Vote for gdsc required to read register address space */
  4462. if (!display) {
  4463. DSI_ERR("invalid input display param\n");
  4464. return -EINVAL;
  4465. }
  4466. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4467. if (rc < 0) {
  4468. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4469. rc);
  4470. return rc;
  4471. }
  4472. mutex_lock(&display->display_lock);
  4473. display->is_cont_splash_enabled = true;
  4474. /* Update splash status for clock manager */
  4475. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4476. display->is_cont_splash_enabled);
  4477. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
  4478. /* Set up ctrl isr before enabling core clk */
  4479. dsi_display_ctrl_isr_configure(display, true);
  4480. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4481. * regulator are inplicit from pre clk on callback
  4482. */
  4483. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4484. DSI_ALL_CLKS, DSI_CLK_ON);
  4485. if (rc) {
  4486. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4487. display->name, rc);
  4488. goto clk_manager_update;
  4489. }
  4490. mutex_unlock(&display->display_lock);
  4491. /* Set the current brightness level */
  4492. dsi_panel_bl_handoff(display->panel);
  4493. return rc;
  4494. clk_manager_update:
  4495. dsi_display_ctrl_isr_configure(display, false);
  4496. /* Update splash status for clock manager */
  4497. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4498. false);
  4499. pm_runtime_put_sync(display->drm_dev->dev);
  4500. display->is_cont_splash_enabled = false;
  4501. mutex_unlock(&display->display_lock);
  4502. return rc;
  4503. }
  4504. /**
  4505. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4506. * @display: Pointer to dsi display
  4507. * Returns: Zero on success
  4508. */
  4509. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4510. {
  4511. int rc = 0;
  4512. if (!display->is_cont_splash_enabled)
  4513. return 0;
  4514. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4515. DSI_ALL_CLKS, DSI_CLK_OFF);
  4516. if (rc)
  4517. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4518. display->name, rc);
  4519. pm_runtime_put_sync(display->drm_dev->dev);
  4520. display->is_cont_splash_enabled = false;
  4521. /* Update splash status for clock manager */
  4522. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4523. display->is_cont_splash_enabled);
  4524. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
  4525. return rc;
  4526. }
  4527. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4528. {
  4529. int rc = 0;
  4530. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4531. if (!rc) {
  4532. DSI_DEBUG("dsi bit clk has been configured to %d\n",
  4533. display->cached_clk_rate);
  4534. atomic_set(&display->clkrate_change_pending, 0);
  4535. } else {
  4536. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4537. display->cached_clk_rate, rc);
  4538. }
  4539. return rc;
  4540. }
  4541. static int dsi_display_validate_split_link(struct dsi_display *display)
  4542. {
  4543. int i, rc = 0;
  4544. struct dsi_display_ctrl *ctrl;
  4545. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4546. if (!host->split_link.enabled)
  4547. return 0;
  4548. display_for_each_ctrl(i, display) {
  4549. ctrl = &display->ctrl[i];
  4550. if (!ctrl->ctrl->split_link_supported) {
  4551. DSI_ERR("[%s] split link is not supported by hw\n",
  4552. display->name);
  4553. rc = -ENOTSUPP;
  4554. goto error;
  4555. }
  4556. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4557. host->split_link.panel_mode = display->panel->panel_mode;
  4558. }
  4559. DSI_DEBUG("Split link is enabled\n");
  4560. return 0;
  4561. error:
  4562. host->split_link.enabled = false;
  4563. return rc;
  4564. }
  4565. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4566. {
  4567. int rc = 0;
  4568. struct dsi_display *display;
  4569. if (!data)
  4570. return -EINVAL;
  4571. rc = dsi_ctrl_get_io_resources(io_res);
  4572. if (rc)
  4573. goto end;
  4574. rc = dsi_phy_get_io_resources(io_res);
  4575. if (rc)
  4576. goto end;
  4577. display = (struct dsi_display *)data;
  4578. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4579. end:
  4580. return rc;
  4581. }
  4582. static int dsi_display_pre_release(void *data)
  4583. {
  4584. struct dsi_display *display;
  4585. if (!data)
  4586. return -EINVAL;
  4587. display = (struct dsi_display *)data;
  4588. mutex_lock(&display->display_lock);
  4589. display->hw_ownership = false;
  4590. mutex_unlock(&display->display_lock);
  4591. dsi_display_ctrl_irq_update(display, false);
  4592. return 0;
  4593. }
  4594. static int dsi_display_pre_acquire(void *data)
  4595. {
  4596. struct dsi_display *display;
  4597. if (!data)
  4598. return -EINVAL;
  4599. display = (struct dsi_display *)data;
  4600. mutex_lock(&display->display_lock);
  4601. display->hw_ownership = true;
  4602. mutex_unlock(&display->display_lock);
  4603. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4604. return 0;
  4605. }
  4606. /**
  4607. * dsi_display_bind - bind dsi device with controlling device
  4608. * @dev: Pointer to base of platform device
  4609. * @master: Pointer to container of drm device
  4610. * @data: Pointer to private data
  4611. * Returns: Zero on success
  4612. */
  4613. static int dsi_display_bind(struct device *dev,
  4614. struct device *master,
  4615. void *data)
  4616. {
  4617. struct dsi_display_ctrl *display_ctrl;
  4618. struct drm_device *drm;
  4619. struct dsi_display *display;
  4620. struct dsi_clk_info info;
  4621. struct clk_ctrl_cb clk_cb;
  4622. void *handle = NULL;
  4623. struct platform_device *pdev = to_platform_device(dev);
  4624. char *client1 = "dsi_clk_client";
  4625. char *client2 = "mdp_event_client";
  4626. struct msm_vm_ops vm_event_ops = {
  4627. .vm_get_io_resources = dsi_display_get_io_resources,
  4628. .vm_pre_hw_release = dsi_display_pre_release,
  4629. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4630. };
  4631. int i, rc = 0;
  4632. if (!dev || !pdev || !master) {
  4633. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4634. dev, pdev, master);
  4635. return -EINVAL;
  4636. }
  4637. drm = dev_get_drvdata(master);
  4638. display = platform_get_drvdata(pdev);
  4639. if (!drm || !display) {
  4640. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4641. drm, display);
  4642. return -EINVAL;
  4643. }
  4644. if (!display->panel_node && !display->fw)
  4645. return 0;
  4646. if (!display->fw)
  4647. display->name = display->panel_node->name;
  4648. /* defer bind if ext bridge driver is not loaded */
  4649. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4650. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4651. if (!of_drm_find_bridge(
  4652. display->ext_bridge[i].node_of)) {
  4653. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4654. display->ext_bridge[i].node_of->full_name);
  4655. return -EPROBE_DEFER;
  4656. }
  4657. }
  4658. }
  4659. mutex_lock(&display->display_lock);
  4660. rc = dsi_display_validate_split_link(display);
  4661. if (rc) {
  4662. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4663. display->name, rc);
  4664. goto error;
  4665. }
  4666. rc = dsi_display_debugfs_init(display);
  4667. if (rc) {
  4668. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4669. goto error;
  4670. }
  4671. atomic_set(&display->clkrate_change_pending, 0);
  4672. display->cached_clk_rate = 0;
  4673. memset(&info, 0x0, sizeof(info));
  4674. display_for_each_ctrl(i, display) {
  4675. display_ctrl = &display->ctrl[i];
  4676. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4677. if (rc) {
  4678. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4679. display->name, i, rc);
  4680. goto error_ctrl_deinit;
  4681. }
  4682. display_ctrl->ctrl->horiz_index = i;
  4683. rc = dsi_phy_drv_init(display_ctrl->phy);
  4684. if (rc) {
  4685. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4686. display->name, i, rc);
  4687. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4688. goto error_ctrl_deinit;
  4689. }
  4690. display_ctrl->ctrl->dma_cmd_workq = display->dma_cmd_workq;
  4691. memcpy(&info.c_clks[i],
  4692. (&display_ctrl->ctrl->clk_info.core_clks),
  4693. sizeof(struct dsi_core_clk_info));
  4694. memcpy(&info.l_hs_clks[i],
  4695. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4696. sizeof(struct dsi_link_hs_clk_info));
  4697. memcpy(&info.l_lp_clks[i],
  4698. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4699. sizeof(struct dsi_link_lp_clk_info));
  4700. info.c_clks[i].drm = drm;
  4701. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4702. }
  4703. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4704. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4705. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4706. info.post_clkon_cb = dsi_post_clkon_cb;
  4707. info.phy_config_cb = dsi_display_phy_configure;
  4708. info.phy_pll_toggle_cb = dsi_display_phy_pll_toggle;
  4709. info.priv_data = display;
  4710. info.master_ndx = display->clk_master_idx;
  4711. info.dsi_ctrl_count = display->ctrl_count;
  4712. snprintf(info.name, MAX_STRING_LEN,
  4713. "DSI_MNGR-%s", display->name);
  4714. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4715. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4716. rc = PTR_ERR(display->clk_mngr);
  4717. display->clk_mngr = NULL;
  4718. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4719. goto error_ctrl_deinit;
  4720. }
  4721. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4722. if (IS_ERR_OR_NULL(handle)) {
  4723. rc = PTR_ERR(handle);
  4724. DSI_ERR("failed to register %s client, rc = %d\n",
  4725. client1, rc);
  4726. goto error_clk_deinit;
  4727. } else {
  4728. display->dsi_clk_handle = handle;
  4729. }
  4730. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4731. if (IS_ERR_OR_NULL(handle)) {
  4732. rc = PTR_ERR(handle);
  4733. DSI_ERR("failed to register %s client, rc = %d\n",
  4734. client2, rc);
  4735. goto error_clk_client_deinit;
  4736. } else {
  4737. display->mdp_clk_handle = handle;
  4738. }
  4739. clk_cb.priv = display;
  4740. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4741. display_for_each_ctrl(i, display) {
  4742. display_ctrl = &display->ctrl[i];
  4743. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4744. if (rc) {
  4745. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4746. display->name, i, rc);
  4747. goto error_ctrl_deinit;
  4748. }
  4749. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4750. if (rc) {
  4751. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4752. display->name, i, rc);
  4753. goto error_ctrl_deinit;
  4754. }
  4755. }
  4756. dsi_display_update_byte_intf_div(display);
  4757. rc = dsi_display_mipi_host_init(display);
  4758. if (rc) {
  4759. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4760. display->name, rc);
  4761. goto error_ctrl_deinit;
  4762. }
  4763. rc = dsi_panel_drv_init(display->panel, &display->host);
  4764. if (rc) {
  4765. if (rc != -EPROBE_DEFER)
  4766. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4767. display->name, rc);
  4768. goto error_host_deinit;
  4769. }
  4770. DSI_INFO("Successfully bind display panel '%s %s'\n", display->name,
  4771. display->panel->te_using_watchdog_timer ? "as sim panel" : "");
  4772. display->drm_dev = drm;
  4773. display_for_each_ctrl(i, display) {
  4774. display_ctrl = &display->ctrl[i];
  4775. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4776. continue;
  4777. display_ctrl->ctrl->drm_dev = drm;
  4778. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4779. &display_ctrl->ctrl->clk_freq);
  4780. if (rc) {
  4781. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4782. display->name, rc);
  4783. goto error;
  4784. }
  4785. }
  4786. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4787. goto error;
  4788. error_host_deinit:
  4789. (void)dsi_display_mipi_host_deinit(display);
  4790. error_clk_client_deinit:
  4791. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4792. error_clk_deinit:
  4793. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4794. error_ctrl_deinit:
  4795. for (i = i - 1; i >= 0; i--) {
  4796. display_ctrl = &display->ctrl[i];
  4797. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4798. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4799. dsi_ctrl_put(display_ctrl->ctrl);
  4800. dsi_phy_put(display_ctrl->phy);
  4801. }
  4802. (void)dsi_display_debugfs_deinit(display);
  4803. error:
  4804. mutex_unlock(&display->display_lock);
  4805. return rc;
  4806. }
  4807. /**
  4808. * dsi_display_unbind - unbind dsi from controlling device
  4809. * @dev: Pointer to base of platform device
  4810. * @master: Pointer to container of drm device
  4811. * @data: Pointer to private data
  4812. */
  4813. static void dsi_display_unbind(struct device *dev,
  4814. struct device *master, void *data)
  4815. {
  4816. struct dsi_display_ctrl *display_ctrl;
  4817. struct dsi_display *display;
  4818. struct platform_device *pdev = to_platform_device(dev);
  4819. int i, rc = 0;
  4820. if (!dev || !pdev || !master) {
  4821. DSI_ERR("invalid param(s)\n");
  4822. return;
  4823. }
  4824. display = platform_get_drvdata(pdev);
  4825. if (!display || !display->panel_node) {
  4826. DSI_ERR("invalid display\n");
  4827. return;
  4828. }
  4829. mutex_lock(&display->display_lock);
  4830. rc = dsi_display_mipi_host_deinit(display);
  4831. if (rc)
  4832. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4833. display->name,
  4834. rc);
  4835. display_for_each_ctrl(i, display) {
  4836. display_ctrl = &display->ctrl[i];
  4837. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4838. if (rc)
  4839. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4840. display->name, i, rc);
  4841. display->ctrl->ctrl->dma_cmd_workq = NULL;
  4842. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4843. if (rc)
  4844. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4845. display->name, i, rc);
  4846. }
  4847. atomic_set(&display->clkrate_change_pending, 0);
  4848. (void)dsi_display_debugfs_deinit(display);
  4849. mutex_unlock(&display->display_lock);
  4850. }
  4851. static const struct component_ops dsi_display_comp_ops = {
  4852. .bind = dsi_display_bind,
  4853. .unbind = dsi_display_unbind,
  4854. };
  4855. static struct platform_driver dsi_display_driver = {
  4856. .probe = dsi_display_dev_probe,
  4857. .remove = dsi_display_dev_remove,
  4858. .driver = {
  4859. .name = "msm-dsi-display",
  4860. .of_match_table = dsi_display_dt_match,
  4861. .suppress_bind_attrs = true,
  4862. },
  4863. };
  4864. static int dsi_display_init(struct dsi_display *display)
  4865. {
  4866. int rc = 0;
  4867. struct platform_device *pdev = display->pdev;
  4868. mutex_init(&display->display_lock);
  4869. rc = _dsi_display_dev_init(display);
  4870. if (rc) {
  4871. DSI_ERR("device init failed, rc=%d\n", rc);
  4872. goto end;
  4873. }
  4874. /*
  4875. * Vote on panel regulator is added to make sure panel regulators
  4876. * are ON for cont-splash enabled usecase.
  4877. * This panel regulator vote will be removed only in:
  4878. * 1) device suspend when cont-splash is enabled.
  4879. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4880. * For GKI, adding this vote will make sure that sync_state
  4881. * kernel driver doesn't disable the panel regulators after
  4882. * dsi probe is complete.
  4883. */
  4884. if (display->panel) {
  4885. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4886. true);
  4887. if (rc) {
  4888. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4889. display->panel->name, rc);
  4890. return rc;
  4891. }
  4892. }
  4893. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4894. if (rc)
  4895. DSI_ERR("component add failed, rc=%d\n", rc);
  4896. DSI_DEBUG("component add success: %s\n", display->name);
  4897. end:
  4898. return rc;
  4899. }
  4900. static void dsi_display_firmware_display(const struct firmware *fw,
  4901. void *context)
  4902. {
  4903. struct dsi_display *display = context;
  4904. if (fw) {
  4905. DSI_INFO("reading data from firmware, size=%zd\n",
  4906. fw->size);
  4907. display->fw = fw;
  4908. if (!strcmp(display->display_type, "primary"))
  4909. display->name = "dsi_firmware_display";
  4910. else if (!strcmp(display->display_type, "secondary"))
  4911. display->name = "dsi_firmware_display_secondary";
  4912. } else {
  4913. DSI_INFO("no firmware available, fallback to device node\n");
  4914. }
  4915. if (dsi_display_init(display))
  4916. return;
  4917. DSI_DEBUG("success\n");
  4918. }
  4919. int dsi_display_dev_probe(struct platform_device *pdev)
  4920. {
  4921. struct dsi_display *display = NULL;
  4922. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4923. int rc = 0, index = DSI_PRIMARY;
  4924. bool firm_req = false;
  4925. struct dsi_display_boot_param *boot_disp;
  4926. if (!pdev || !pdev->dev.of_node) {
  4927. DSI_ERR("pdev not found\n");
  4928. rc = -ENODEV;
  4929. goto end;
  4930. }
  4931. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4932. if (!display) {
  4933. rc = -ENOMEM;
  4934. goto end;
  4935. }
  4936. display->dma_cmd_workq = create_singlethread_workqueue(
  4937. "dsi_dma_cmd_workq");
  4938. if (!display->dma_cmd_workq) {
  4939. DSI_ERR("failed to create work queue\n");
  4940. rc = -EINVAL;
  4941. goto end;
  4942. }
  4943. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  4944. if (!mdp_node) {
  4945. DSI_ERR("mdp_node not found\n");
  4946. rc = -ENODEV;
  4947. goto end;
  4948. }
  4949. display->trusted_vm_env = of_property_read_bool(mdp_node,
  4950. "qcom,sde-trusted-vm-env");
  4951. if (display->trusted_vm_env)
  4952. DSI_INFO("Display enabled with trusted vm path\n");
  4953. /* initialize panel id to UINT64_MAX */
  4954. display->panel_id = ~0x0;
  4955. display->display_type = of_get_property(pdev->dev.of_node,
  4956. "label", NULL);
  4957. if (!display->display_type)
  4958. display->display_type = "primary";
  4959. if (!strcmp(display->display_type, "secondary"))
  4960. index = DSI_SECONDARY;
  4961. boot_disp = &boot_displays[index];
  4962. node = pdev->dev.of_node;
  4963. if (boot_disp->boot_disp_en) {
  4964. /* The panel name should be same as UEFI name index */
  4965. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4966. if (!panel_node)
  4967. DSI_WARN("%s panel_node %s not found\n", display->display_type,
  4968. boot_disp->name);
  4969. } else {
  4970. panel_node = of_parse_phandle(node,
  4971. "qcom,dsi-default-panel", 0);
  4972. if (!panel_node)
  4973. DSI_WARN("%s default panel not found\n", display->display_type);
  4974. }
  4975. boot_disp->node = pdev->dev.of_node;
  4976. boot_disp->disp = display;
  4977. display->panel_node = panel_node;
  4978. display->pdev = pdev;
  4979. display->boot_disp = boot_disp;
  4980. dsi_display_parse_cmdline_topology(display, index);
  4981. platform_set_drvdata(pdev, display);
  4982. if (!dsi_display_validate_res(display)) {
  4983. rc = -EPROBE_DEFER;
  4984. DSI_ERR("resources required for display probe not present: rc=%d\n", rc);
  4985. goto end;
  4986. }
  4987. /* initialize display in firmware callback */
  4988. if (!(boot_displays[DSI_PRIMARY].boot_disp_en ||
  4989. boot_displays[DSI_SECONDARY].boot_disp_en) &&
  4990. IS_ENABLED(CONFIG_DSI_PARSER)) {
  4991. if (!strcmp(display->display_type, "primary"))
  4992. firm_req = !request_firmware_nowait(
  4993. THIS_MODULE, 1, "dsi_prop",
  4994. &pdev->dev, GFP_KERNEL, display,
  4995. dsi_display_firmware_display);
  4996. else if (!strcmp(display->display_type, "secondary"))
  4997. firm_req = !request_firmware_nowait(
  4998. THIS_MODULE, 1, "dsi_prop_sec",
  4999. &pdev->dev, GFP_KERNEL, display,
  5000. dsi_display_firmware_display);
  5001. }
  5002. if (!firm_req) {
  5003. rc = dsi_display_init(display);
  5004. if (rc)
  5005. goto end;
  5006. }
  5007. return 0;
  5008. end:
  5009. if (display)
  5010. devm_kfree(&pdev->dev, display);
  5011. return rc;
  5012. }
  5013. int dsi_display_dev_remove(struct platform_device *pdev)
  5014. {
  5015. int rc = 0, i = 0;
  5016. struct dsi_display *display;
  5017. struct dsi_display_ctrl *ctrl;
  5018. if (!pdev) {
  5019. DSI_ERR("Invalid device\n");
  5020. return -EINVAL;
  5021. }
  5022. display = platform_get_drvdata(pdev);
  5023. /* decrement ref count */
  5024. of_node_put(display->panel_node);
  5025. if (display->dma_cmd_workq) {
  5026. flush_workqueue(display->dma_cmd_workq);
  5027. destroy_workqueue(display->dma_cmd_workq);
  5028. display->dma_cmd_workq = NULL;
  5029. display_for_each_ctrl(i, display) {
  5030. ctrl = &display->ctrl[i];
  5031. if (!ctrl->ctrl)
  5032. continue;
  5033. ctrl->ctrl->dma_cmd_workq = NULL;
  5034. }
  5035. }
  5036. (void)_dsi_display_dev_deinit(display);
  5037. platform_set_drvdata(pdev, NULL);
  5038. devm_kfree(&pdev->dev, display);
  5039. return rc;
  5040. }
  5041. int dsi_display_get_num_of_displays(void)
  5042. {
  5043. int i, count = 0;
  5044. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  5045. struct dsi_display *display = boot_displays[i].disp;
  5046. if ((display && display->panel_node) ||
  5047. (display && display->fw))
  5048. count++;
  5049. }
  5050. return count;
  5051. }
  5052. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  5053. {
  5054. int index = 0, count = 0;
  5055. if (!display_array || !max_display_count) {
  5056. DSI_ERR("invalid params\n");
  5057. return 0;
  5058. }
  5059. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  5060. struct dsi_display *display = boot_displays[index].disp;
  5061. if ((display && display->panel_node) ||
  5062. (display && display->fw))
  5063. display_array[count++] = display;
  5064. }
  5065. return count;
  5066. }
  5067. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  5068. {
  5069. if (!display)
  5070. return;
  5071. mutex_lock(&display->display_lock);
  5072. display->is_active = is_active;
  5073. mutex_unlock(&display->display_lock);
  5074. }
  5075. int dsi_display_drm_bridge_init(struct dsi_display *display,
  5076. struct drm_encoder *enc)
  5077. {
  5078. int rc = 0;
  5079. struct dsi_bridge *bridge;
  5080. struct msm_drm_private *priv = NULL;
  5081. if (!display || !display->drm_dev || !enc) {
  5082. DSI_ERR("invalid param(s)\n");
  5083. return -EINVAL;
  5084. }
  5085. mutex_lock(&display->display_lock);
  5086. priv = display->drm_dev->dev_private;
  5087. if (!priv) {
  5088. DSI_ERR("Private data is not present\n");
  5089. rc = -EINVAL;
  5090. goto error;
  5091. }
  5092. if (display->bridge) {
  5093. DSI_ERR("display is already initialize\n");
  5094. goto error;
  5095. }
  5096. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  5097. if (IS_ERR_OR_NULL(bridge)) {
  5098. rc = PTR_ERR(bridge);
  5099. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  5100. goto error;
  5101. }
  5102. display->bridge = bridge;
  5103. priv->bridges[priv->num_bridges++] = &bridge->base;
  5104. if (display->tx_cmd_buf == NULL) {
  5105. rc = dsi_host_alloc_cmd_tx_buffer(display);
  5106. if (rc)
  5107. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  5108. }
  5109. error:
  5110. mutex_unlock(&display->display_lock);
  5111. return rc;
  5112. }
  5113. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  5114. {
  5115. int rc = 0;
  5116. if (!display) {
  5117. DSI_ERR("Invalid params\n");
  5118. return -EINVAL;
  5119. }
  5120. mutex_lock(&display->display_lock);
  5121. dsi_drm_bridge_cleanup(display->bridge);
  5122. display->bridge = NULL;
  5123. mutex_unlock(&display->display_lock);
  5124. return rc;
  5125. }
  5126. /* Hook functions to call external connector, pointer validation is
  5127. * done in dsi_display_drm_ext_bridge_init.
  5128. */
  5129. static enum drm_connector_status dsi_display_drm_ext_detect(
  5130. struct drm_connector *connector,
  5131. bool force,
  5132. void *disp)
  5133. {
  5134. struct dsi_display *display = disp;
  5135. return display->ext_conn->funcs->detect(display->ext_conn, force);
  5136. }
  5137. static int dsi_display_drm_ext_get_modes(
  5138. struct drm_connector *connector, void *disp,
  5139. const struct msm_resource_caps_info *avail_res)
  5140. {
  5141. struct dsi_display *display = disp;
  5142. struct drm_display_mode *pmode, *pt;
  5143. int count;
  5144. /* if there are modes defined in panel, ignore external modes */
  5145. if (display->panel->num_timing_nodes)
  5146. return dsi_connector_get_modes(connector, disp, avail_res);
  5147. count = display->ext_conn->helper_private->get_modes(
  5148. display->ext_conn);
  5149. list_for_each_entry_safe(pmode, pt,
  5150. &display->ext_conn->probed_modes, head) {
  5151. list_move_tail(&pmode->head, &connector->probed_modes);
  5152. }
  5153. connector->display_info = display->ext_conn->display_info;
  5154. return count;
  5155. }
  5156. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  5157. struct drm_connector *connector,
  5158. struct drm_display_mode *mode,
  5159. void *disp, const struct msm_resource_caps_info *avail_res)
  5160. {
  5161. struct dsi_display *display = disp;
  5162. enum drm_mode_status status;
  5163. /* always do internal mode_valid check */
  5164. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  5165. if (status != MODE_OK)
  5166. return status;
  5167. return display->ext_conn->helper_private->mode_valid(
  5168. display->ext_conn, mode);
  5169. }
  5170. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  5171. void *disp,
  5172. struct drm_atomic_state *state)
  5173. {
  5174. struct dsi_display *display = disp;
  5175. struct drm_connector_state *c_state;
  5176. c_state = drm_atomic_get_new_connector_state(state, connector);
  5177. return display->ext_conn->helper_private->atomic_check(
  5178. display->ext_conn, state);
  5179. }
  5180. static int dsi_display_ext_get_info(struct drm_connector *connector,
  5181. struct msm_display_info *info, void *disp)
  5182. {
  5183. struct dsi_display *display;
  5184. int i;
  5185. if (!info || !disp) {
  5186. DSI_ERR("invalid params\n");
  5187. return -EINVAL;
  5188. }
  5189. display = disp;
  5190. if (!display->panel) {
  5191. DSI_ERR("invalid display panel\n");
  5192. return -EINVAL;
  5193. }
  5194. mutex_lock(&display->display_lock);
  5195. memset(info, 0, sizeof(struct msm_display_info));
  5196. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5197. info->num_of_h_tiles = display->ctrl_count;
  5198. for (i = 0; i < info->num_of_h_tiles; i++)
  5199. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5200. info->is_connected = connector->status != connector_status_disconnected;
  5201. if (!strcmp(display->display_type, "primary"))
  5202. info->display_type = SDE_CONNECTOR_PRIMARY;
  5203. else if (!strcmp(display->display_type, "secondary"))
  5204. info->display_type = SDE_CONNECTOR_SECONDARY;
  5205. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5206. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5207. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5208. mutex_unlock(&display->display_lock);
  5209. return 0;
  5210. }
  5211. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5212. const struct drm_display_mode *drm_mode,
  5213. struct msm_mode_info *mode_info,
  5214. void *display, const struct msm_resource_caps_info *avail_res)
  5215. {
  5216. struct msm_display_topology *topology;
  5217. if (!drm_mode || !mode_info ||
  5218. !avail_res || !avail_res->max_mixer_width)
  5219. return -EINVAL;
  5220. memset(mode_info, 0, sizeof(*mode_info));
  5221. mode_info->frame_rate = drm_mode_vrefresh(drm_mode);
  5222. mode_info->vtotal = drm_mode->vtotal;
  5223. topology = &mode_info->topology;
  5224. topology->num_lm = (avail_res->max_mixer_width
  5225. <= drm_mode->hdisplay) ? 2 : 1;
  5226. topology->num_enc = 0;
  5227. topology->num_intf = topology->num_lm;
  5228. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5229. return 0;
  5230. }
  5231. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5232. struct drm_bridge *bridge)
  5233. {
  5234. struct msm_drm_private *priv;
  5235. struct sde_kms *sde_kms;
  5236. struct drm_connector *conn;
  5237. struct drm_connector_list_iter conn_iter;
  5238. struct sde_connector *sde_conn;
  5239. struct dsi_display *display;
  5240. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5241. int i;
  5242. if (!bridge || !bridge->encoder) {
  5243. SDE_ERROR("invalid argument\n");
  5244. return NULL;
  5245. }
  5246. priv = bridge->dev->dev_private;
  5247. sde_kms = to_sde_kms(priv->kms);
  5248. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5249. drm_for_each_connector_iter(conn, &conn_iter) {
  5250. sde_conn = to_sde_connector(conn);
  5251. if (sde_conn->encoder == bridge->encoder) {
  5252. display = sde_conn->display;
  5253. display_for_each_ctrl(i, display) {
  5254. if (display->ext_bridge[i].bridge == bridge) {
  5255. dsi_bridge = &display->ext_bridge[i];
  5256. break;
  5257. }
  5258. }
  5259. }
  5260. }
  5261. drm_connector_list_iter_end(&conn_iter);
  5262. return dsi_bridge;
  5263. }
  5264. static void dsi_display_drm_ext_adjust_timing(
  5265. const struct dsi_display *display,
  5266. struct drm_display_mode *mode)
  5267. {
  5268. mode->hdisplay /= display->ctrl_count;
  5269. mode->hsync_start /= display->ctrl_count;
  5270. mode->hsync_end /= display->ctrl_count;
  5271. mode->htotal /= display->ctrl_count;
  5272. mode->hskew /= display->ctrl_count;
  5273. mode->clock /= display->ctrl_count;
  5274. }
  5275. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5276. struct drm_bridge *bridge,
  5277. const struct drm_display_info *info,
  5278. const struct drm_display_mode *mode)
  5279. {
  5280. struct dsi_display_ext_bridge *ext_bridge;
  5281. struct drm_display_mode tmp;
  5282. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5283. if (!ext_bridge)
  5284. return MODE_ERROR;
  5285. tmp = *mode;
  5286. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5287. return ext_bridge->orig_funcs->mode_valid(bridge, info, &tmp);
  5288. }
  5289. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5290. struct drm_bridge *bridge,
  5291. const struct drm_display_mode *mode,
  5292. struct drm_display_mode *adjusted_mode)
  5293. {
  5294. struct dsi_display_ext_bridge *ext_bridge;
  5295. struct drm_display_mode tmp;
  5296. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5297. if (!ext_bridge)
  5298. return false;
  5299. tmp = *mode;
  5300. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5301. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5302. }
  5303. static void dsi_display_drm_ext_bridge_mode_set(
  5304. struct drm_bridge *bridge,
  5305. const struct drm_display_mode *mode,
  5306. const struct drm_display_mode *adjusted_mode)
  5307. {
  5308. struct dsi_display_ext_bridge *ext_bridge;
  5309. struct drm_display_mode tmp;
  5310. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5311. if (!ext_bridge)
  5312. return;
  5313. tmp = *mode;
  5314. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5315. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5316. }
  5317. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5318. struct mipi_dsi_device *dsi)
  5319. {
  5320. struct dsi_display *display = to_dsi_display(host);
  5321. struct dsi_panel *panel;
  5322. if (!host || !dsi || !display->panel) {
  5323. DSI_ERR("Invalid param\n");
  5324. return -EINVAL;
  5325. }
  5326. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5327. dsi->name, dsi->channel, dsi->lanes,
  5328. dsi->format, dsi->mode_flags);
  5329. panel = display->panel;
  5330. panel->host_config.data_lanes = 0;
  5331. if (dsi->lanes > 0)
  5332. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5333. if (dsi->lanes > 1)
  5334. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5335. if (dsi->lanes > 2)
  5336. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5337. if (dsi->lanes > 3)
  5338. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5339. switch (dsi->format) {
  5340. case MIPI_DSI_FMT_RGB888:
  5341. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5342. break;
  5343. case MIPI_DSI_FMT_RGB666:
  5344. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5345. break;
  5346. case MIPI_DSI_FMT_RGB666_PACKED:
  5347. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5348. break;
  5349. case MIPI_DSI_FMT_RGB565:
  5350. default:
  5351. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5352. break;
  5353. }
  5354. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5355. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5356. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5357. panel->video_config.traffic_mode =
  5358. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5359. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5360. panel->video_config.traffic_mode =
  5361. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5362. else
  5363. panel->video_config.traffic_mode =
  5364. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5365. panel->video_config.hsa_lp11_en =
  5366. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5367. panel->video_config.hbp_lp11_en =
  5368. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5369. panel->video_config.hfp_lp11_en =
  5370. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5371. panel->video_config.pulse_mode_hsa_he =
  5372. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5373. } else {
  5374. panel->panel_mode = DSI_OP_CMD_MODE;
  5375. DSI_ERR("command mode not supported by ext bridge\n");
  5376. return -ENOTSUPP;
  5377. }
  5378. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5379. return 0;
  5380. }
  5381. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5382. .attach = dsi_host_ext_attach,
  5383. .detach = dsi_host_detach,
  5384. .transfer = dsi_host_transfer,
  5385. };
  5386. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5387. {
  5388. if (!display || !display->panel) {
  5389. pr_err("invalid param(s)\n");
  5390. return NULL;
  5391. }
  5392. return &display->panel->drm_panel;
  5393. }
  5394. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5395. struct drm_encoder *encoder, struct drm_connector *connector)
  5396. {
  5397. struct drm_device *drm;
  5398. struct drm_bridge *bridge;
  5399. struct drm_bridge *ext_bridge;
  5400. struct drm_connector *ext_conn;
  5401. struct sde_connector *sde_conn;
  5402. struct drm_bridge *prev_bridge;
  5403. int rc = 0, i;
  5404. if (!display || !encoder || !connector)
  5405. return -EINVAL;
  5406. drm = encoder->dev;
  5407. bridge = drm_bridge_chain_get_first_bridge(encoder);
  5408. sde_conn = to_sde_connector(connector);
  5409. prev_bridge = bridge;
  5410. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5411. return 0;
  5412. if (!bridge)
  5413. return -EINVAL;
  5414. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5415. struct dsi_display_ext_bridge *ext_bridge_info =
  5416. &display->ext_bridge[i];
  5417. struct drm_encoder *c_encoder;
  5418. /* return if ext bridge is already initialized */
  5419. if (ext_bridge_info->bridge)
  5420. return 0;
  5421. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5422. if (IS_ERR_OR_NULL(ext_bridge)) {
  5423. rc = PTR_ERR(ext_bridge);
  5424. DSI_ERR("failed to find ext bridge\n");
  5425. goto error;
  5426. }
  5427. /* override functions for mode adjustment */
  5428. if (display->ext_bridge_cnt > 1) {
  5429. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5430. if (ext_bridge->funcs->mode_fixup)
  5431. ext_bridge_info->bridge_funcs.mode_fixup =
  5432. dsi_display_drm_ext_bridge_mode_fixup;
  5433. if (ext_bridge->funcs->mode_valid)
  5434. ext_bridge_info->bridge_funcs.mode_valid =
  5435. dsi_display_drm_ext_bridge_mode_valid;
  5436. if (ext_bridge->funcs->mode_set)
  5437. ext_bridge_info->bridge_funcs.mode_set =
  5438. dsi_display_drm_ext_bridge_mode_set;
  5439. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5440. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5441. }
  5442. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge, 0);
  5443. if (rc) {
  5444. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5445. display->name, rc);
  5446. goto error;
  5447. }
  5448. ext_bridge_info->display = display;
  5449. ext_bridge_info->bridge = ext_bridge;
  5450. prev_bridge = ext_bridge;
  5451. /* ext bridge will init its own connector during attach,
  5452. * we need to extract it out of the connector list
  5453. */
  5454. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5455. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5456. struct drm_connector, head);
  5457. if (!ext_conn) {
  5458. DSI_ERR("failed to get external connector\n");
  5459. rc = PTR_ERR(ext_conn);
  5460. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5461. goto error;
  5462. }
  5463. drm_connector_for_each_possible_encoder(ext_conn, c_encoder)
  5464. break;
  5465. if (!c_encoder) {
  5466. DSI_ERR("failed to get encoder\n");
  5467. rc = PTR_ERR(c_encoder);
  5468. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5469. goto error;
  5470. }
  5471. if (ext_conn && ext_conn != connector &&
  5472. c_encoder->base.id == bridge->encoder->base.id) {
  5473. list_del_init(&ext_conn->head);
  5474. display->ext_conn = ext_conn;
  5475. }
  5476. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5477. /* if there is no valid external connector created, or in split
  5478. * mode, default setting is used from panel defined in DT file.
  5479. */
  5480. if (!display->ext_conn ||
  5481. !display->ext_conn->funcs ||
  5482. !display->ext_conn->helper_private ||
  5483. display->ext_bridge_cnt > 1) {
  5484. display->ext_conn = NULL;
  5485. continue;
  5486. }
  5487. /* otherwise, hook up the functions to use external connector */
  5488. if (display->ext_conn->funcs->detect)
  5489. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5490. if (display->ext_conn->helper_private->get_modes)
  5491. sde_conn->ops.get_modes =
  5492. dsi_display_drm_ext_get_modes;
  5493. if (display->ext_conn->helper_private->mode_valid)
  5494. sde_conn->ops.mode_valid =
  5495. dsi_display_drm_ext_mode_valid;
  5496. if (display->ext_conn->helper_private->atomic_check)
  5497. sde_conn->ops.atomic_check =
  5498. dsi_display_drm_ext_atomic_check;
  5499. sde_conn->ops.get_info =
  5500. dsi_display_ext_get_info;
  5501. sde_conn->ops.get_mode_info =
  5502. dsi_display_ext_get_mode_info;
  5503. /* add support to attach/detach */
  5504. display->host.ops = &dsi_host_ext_ops;
  5505. }
  5506. return 0;
  5507. error:
  5508. return rc;
  5509. }
  5510. int dsi_display_get_info(struct drm_connector *connector,
  5511. struct msm_display_info *info, void *disp)
  5512. {
  5513. struct dsi_display *display;
  5514. struct dsi_panel_phy_props phy_props;
  5515. struct dsi_host_common_cfg *host;
  5516. int i, rc;
  5517. if (!info || !disp) {
  5518. DSI_ERR("invalid params\n");
  5519. return -EINVAL;
  5520. }
  5521. display = disp;
  5522. if (!display->panel) {
  5523. DSI_ERR("invalid display panel\n");
  5524. return -EINVAL;
  5525. }
  5526. mutex_lock(&display->display_lock);
  5527. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5528. if (rc) {
  5529. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5530. display->name, rc);
  5531. goto error;
  5532. }
  5533. memset(info, 0, sizeof(struct msm_display_info));
  5534. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5535. info->num_of_h_tiles = display->ctrl_count;
  5536. for (i = 0; i < info->num_of_h_tiles; i++)
  5537. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5538. info->is_connected = display->is_active;
  5539. if (!strcmp(display->display_type, "primary"))
  5540. info->display_type = SDE_CONNECTOR_PRIMARY;
  5541. else if (!strcmp(display->display_type, "secondary"))
  5542. info->display_type = SDE_CONNECTOR_SECONDARY;
  5543. info->width_mm = phy_props.panel_width_mm;
  5544. info->height_mm = phy_props.panel_height_mm;
  5545. info->max_width = 1920;
  5546. info->max_height = 1080;
  5547. info->qsync_min_fps = display->panel->qsync_caps.qsync_min_fps;
  5548. info->has_qsync_min_fps_list = (display->panel->qsync_caps.qsync_min_fps_list_len > 0);
  5549. info->has_avr_step_req = (display->panel->avr_caps.avr_step_fps_list_len > 0);
  5550. info->poms_align_vsync = display->panel->poms_align_vsync;
  5551. switch (display->panel->panel_mode) {
  5552. case DSI_OP_VIDEO_MODE:
  5553. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5554. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5555. if (display->panel->panel_mode_switch_enabled)
  5556. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5557. break;
  5558. case DSI_OP_CMD_MODE:
  5559. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5560. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5561. if (display->panel->panel_mode_switch_enabled)
  5562. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5563. info->is_te_using_watchdog_timer = is_sim_panel(display);
  5564. break;
  5565. default:
  5566. DSI_ERR("unknwown dsi panel mode %d\n",
  5567. display->panel->panel_mode);
  5568. break;
  5569. }
  5570. if (display->panel->esd_config.esd_enabled && !is_sim_panel(display))
  5571. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5572. info->te_source = display->te_source;
  5573. host = &display->panel->host_config;
  5574. if (host->split_link.enabled)
  5575. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5576. info->dsc_count = display->panel->dsc_count;
  5577. info->lm_count = display->panel->lm_count;
  5578. error:
  5579. mutex_unlock(&display->display_lock);
  5580. return rc;
  5581. }
  5582. int dsi_display_get_mode_count(struct dsi_display *display,
  5583. u32 *count)
  5584. {
  5585. if (!display || !display->panel) {
  5586. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5587. display ? display->panel != NULL : 0);
  5588. return -EINVAL;
  5589. }
  5590. mutex_lock(&display->display_lock);
  5591. *count = display->panel->num_display_modes;
  5592. mutex_unlock(&display->display_lock);
  5593. return 0;
  5594. }
  5595. void dsi_display_adjust_mode_timing(struct dsi_display *display,
  5596. struct dsi_display_mode *dsi_mode,
  5597. int lanes, int bpp)
  5598. {
  5599. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5600. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5601. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  5602. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5603. /* Constant FPS is not supported on command mode */
  5604. if (!(dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE))
  5605. return;
  5606. if (!dyn_clk_caps->maintain_const_fps)
  5607. return;
  5608. /*
  5609. * When there is a dynamic clock switch, there is small change
  5610. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5611. * is adjusted. It has been assumed that the refined porch values
  5612. * are supported by the panel. This logic can be enhanced further
  5613. * in future by taking min/max porches supported by the panel.
  5614. */
  5615. switch (dyn_clk_caps->type) {
  5616. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5617. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5618. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5619. do_div(old_htotal, display->ctrl_count);
  5620. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5621. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5622. if (dsi_display_is_type_cphy(display)) {
  5623. new_htotal = new_htotal * bits_per_symbol;
  5624. div = div * num_of_symbols;
  5625. }
  5626. do_div(new_htotal, div);
  5627. if (old_htotal > new_htotal)
  5628. dsi_mode->timing.h_front_porch -=
  5629. ((old_htotal - new_htotal) * display->ctrl_count);
  5630. else
  5631. dsi_mode->timing.h_front_porch +=
  5632. ((new_htotal - old_htotal) * display->ctrl_count);
  5633. break;
  5634. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5635. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5636. do_div(htotal, display->ctrl_count);
  5637. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5638. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5639. if (dsi_display_is_type_cphy(display)) {
  5640. new_vtotal = new_vtotal * bits_per_symbol;
  5641. div = div * num_of_symbols;
  5642. }
  5643. do_div(new_vtotal, div);
  5644. dsi_mode->timing.v_front_porch = new_vtotal -
  5645. dsi_mode->timing.v_back_porch -
  5646. dsi_mode->timing.v_sync_width -
  5647. dsi_mode->timing.v_active;
  5648. break;
  5649. default:
  5650. break;
  5651. }
  5652. }
  5653. static void _dsi_display_populate_bit_clks(struct dsi_display *display, int start, int end)
  5654. {
  5655. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5656. struct dsi_display_mode *src;
  5657. struct dsi_host_common_cfg *cfg;
  5658. int i, bpp, lanes = 0;
  5659. if (!display)
  5660. return;
  5661. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5662. if (!dyn_clk_caps->dyn_clk_support)
  5663. return;
  5664. cfg = &(display->panel->host_config);
  5665. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5666. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5667. lanes++;
  5668. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5669. lanes++;
  5670. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5671. lanes++;
  5672. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5673. lanes++;
  5674. for (i = start; i < end; i++) {
  5675. src = &display->modes[i];
  5676. if (!src)
  5677. return;
  5678. if (!src->priv_info->bit_clk_list.count)
  5679. continue;
  5680. src->timing.clk_rate_hz = src->priv_info->bit_clk_list.rates[0];
  5681. dsi_display_adjust_mode_timing(display, src, lanes, bpp);
  5682. src->pixel_clk_khz = div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5683. src->pixel_clk_khz /= 1000;
  5684. src->pixel_clk_khz *= display->ctrl_count;
  5685. }
  5686. }
  5687. int dsi_display_restore_bit_clk(struct dsi_display *display, struct dsi_display_mode *mode)
  5688. {
  5689. int i;
  5690. u32 clk_rate_hz = 0;
  5691. if (!display || !mode || !mode->priv_info) {
  5692. DSI_ERR("invalid arguments\n");
  5693. return -EINVAL;
  5694. }
  5695. clk_rate_hz = display->cached_clk_rate;
  5696. if (mode->priv_info->bit_clk_list.count) {
  5697. /* use first entry as the default bit clk rate */
  5698. clk_rate_hz = mode->priv_info->bit_clk_list.rates[0];
  5699. for (i = 0; i < mode->priv_info->bit_clk_list.count; i++) {
  5700. if (display->dyn_bit_clk == mode->priv_info->bit_clk_list.rates[i])
  5701. clk_rate_hz = display->dyn_bit_clk;
  5702. }
  5703. }
  5704. mode->timing.clk_rate_hz = clk_rate_hz;
  5705. mode->priv_info->clk_rate_hz = clk_rate_hz;
  5706. SDE_EVT32(clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5707. DSI_DEBUG("clk_rate_hz:%u, cached_clk_rate:%u, dyn_bit_clk:%u\n",
  5708. clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5709. return 0;
  5710. }
  5711. void dsi_display_put_mode(struct dsi_display *display,
  5712. struct dsi_display_mode *mode)
  5713. {
  5714. dsi_panel_put_mode(mode);
  5715. }
  5716. int dsi_display_get_modes(struct dsi_display *display,
  5717. struct dsi_display_mode **out_modes)
  5718. {
  5719. struct dsi_dfps_capabilities dfps_caps;
  5720. struct dsi_display_ctrl *ctrl;
  5721. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5722. bool is_split_link, support_cmd_mode, support_video_mode;
  5723. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5724. u32 sublinks_count, mode_idx, array_idx = 0;
  5725. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5726. int i, start, end, rc = -EINVAL;
  5727. if (!display || !out_modes) {
  5728. DSI_ERR("Invalid params\n");
  5729. return -EINVAL;
  5730. }
  5731. *out_modes = NULL;
  5732. ctrl = &display->ctrl[0];
  5733. mutex_lock(&display->display_lock);
  5734. if (display->modes)
  5735. goto exit;
  5736. display_mode_count = display->panel->num_display_modes;
  5737. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5738. GFP_KERNEL);
  5739. if (!display->modes) {
  5740. rc = -ENOMEM;
  5741. goto error;
  5742. }
  5743. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5744. if (rc) {
  5745. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5746. display->name);
  5747. goto error;
  5748. }
  5749. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5750. timing_mode_count = display->panel->num_timing_nodes;
  5751. /* Validate command line timing */
  5752. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5753. (display->cmdline_timing >= timing_mode_count))
  5754. display->cmdline_timing = NO_OVERRIDE;
  5755. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5756. struct dsi_display_mode display_mode;
  5757. int topology_override = NO_OVERRIDE;
  5758. bool is_preferred = false;
  5759. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5760. memset(&display_mode, 0, sizeof(display_mode));
  5761. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5762. &display_mode,
  5763. topology_override);
  5764. if (rc) {
  5765. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5766. display->name, mode_idx);
  5767. goto error;
  5768. }
  5769. if (display->cmdline_timing == display_mode.mode_idx) {
  5770. topology_override = display->cmdline_topology;
  5771. is_preferred = true;
  5772. }
  5773. support_cmd_mode = display_mode.panel_mode_caps & DSI_OP_CMD_MODE;
  5774. support_video_mode = display_mode.panel_mode_caps & DSI_OP_VIDEO_MODE;
  5775. /* Setup widebus support */
  5776. display_mode.priv_info->widebus_support =
  5777. ctrl->ctrl->hw.widebus_support;
  5778. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5779. !support_video_mode) ? 1 : dfps_caps.dfps_list_len);
  5780. /* Calculate dsi frame transfer time */
  5781. if (support_cmd_mode) {
  5782. dsi_panel_calc_dsi_transfer_time(
  5783. &display->panel->host_config,
  5784. &display_mode, frame_threshold_us);
  5785. display_mode.priv_info->dsi_transfer_time_us =
  5786. display_mode.timing.dsi_transfer_time_us;
  5787. display_mode.priv_info->min_dsi_clk_hz =
  5788. display_mode.timing.min_dsi_clk_hz;
  5789. display_mode.priv_info->mdp_transfer_time_us =
  5790. display_mode.timing.mdp_transfer_time_us;
  5791. }
  5792. is_split_link = host->split_link.enabled;
  5793. sublinks_count = host->split_link.num_sublinks;
  5794. if (is_split_link && sublinks_count > 1) {
  5795. display_mode.timing.h_active *= sublinks_count;
  5796. display_mode.timing.h_front_porch *= sublinks_count;
  5797. display_mode.timing.h_sync_width *= sublinks_count;
  5798. display_mode.timing.h_back_porch *= sublinks_count;
  5799. display_mode.timing.h_skew *= sublinks_count;
  5800. display_mode.pixel_clk_khz *= sublinks_count;
  5801. } else {
  5802. display_mode.timing.h_active *= display->ctrl_count;
  5803. display_mode.timing.h_front_porch *=
  5804. display->ctrl_count;
  5805. display_mode.timing.h_sync_width *=
  5806. display->ctrl_count;
  5807. display_mode.timing.h_back_porch *=
  5808. display->ctrl_count;
  5809. display_mode.timing.h_skew *= display->ctrl_count;
  5810. display_mode.pixel_clk_khz *= display->ctrl_count;
  5811. }
  5812. start = array_idx;
  5813. for (i = 0; i < num_dfps_rates; i++) {
  5814. struct dsi_display_mode *sub_mode =
  5815. &display->modes[array_idx];
  5816. u32 curr_refresh_rate;
  5817. if (!sub_mode) {
  5818. DSI_ERR("invalid mode data\n");
  5819. rc = -EFAULT;
  5820. goto error;
  5821. }
  5822. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5823. array_idx++;
  5824. if (!dfps_caps.dfps_support || !support_video_mode)
  5825. continue;
  5826. sub_mode->mode_idx += (array_idx - 1);
  5827. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5828. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5829. dsi_display_get_dfps_timing(display, sub_mode,
  5830. curr_refresh_rate);
  5831. sub_mode->panel_mode_caps = DSI_OP_VIDEO_MODE;
  5832. }
  5833. end = array_idx;
  5834. _dsi_display_populate_bit_clks(display, start, end);
  5835. if (is_preferred) {
  5836. /* Set first timing sub mode as preferred mode */
  5837. display->modes[start].is_preferred = true;
  5838. }
  5839. }
  5840. exit:
  5841. *out_modes = display->modes;
  5842. rc = 0;
  5843. error:
  5844. if (rc)
  5845. kfree(display->modes);
  5846. mutex_unlock(&display->display_lock);
  5847. return rc;
  5848. }
  5849. int dsi_display_get_panel_vfp(void *dsi_display,
  5850. int h_active, int v_active)
  5851. {
  5852. int i, rc = 0;
  5853. u32 count, refresh_rate = 0;
  5854. struct dsi_dfps_capabilities dfps_caps;
  5855. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5856. struct dsi_host_common_cfg *host;
  5857. if (!display || !display->panel)
  5858. return -EINVAL;
  5859. mutex_lock(&display->display_lock);
  5860. count = display->panel->num_display_modes;
  5861. if (display->panel->cur_mode)
  5862. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5863. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5864. if (dfps_caps.dfps_support)
  5865. refresh_rate = dfps_caps.max_refresh_rate;
  5866. if (!refresh_rate) {
  5867. mutex_unlock(&display->display_lock);
  5868. DSI_ERR("Null Refresh Rate\n");
  5869. return -EINVAL;
  5870. }
  5871. host = &display->panel->host_config;
  5872. if (host->split_link.enabled)
  5873. h_active *= host->split_link.num_sublinks;
  5874. else
  5875. h_active *= display->ctrl_count;
  5876. for (i = 0; i < count; i++) {
  5877. struct dsi_display_mode *m = &display->modes[i];
  5878. if (m && v_active == m->timing.v_active &&
  5879. h_active == m->timing.h_active &&
  5880. refresh_rate == m->timing.refresh_rate) {
  5881. rc = m->timing.v_front_porch;
  5882. break;
  5883. }
  5884. }
  5885. mutex_unlock(&display->display_lock);
  5886. return rc;
  5887. }
  5888. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5889. {
  5890. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5891. u32 count, i;
  5892. int rc = 0;
  5893. *num_lm = 0;
  5894. mutex_lock(&display->display_lock);
  5895. count = display->panel->num_display_modes;
  5896. mutex_unlock(&display->display_lock);
  5897. if (!display->modes) {
  5898. struct dsi_display_mode *m;
  5899. rc = dsi_display_get_modes(display, &m);
  5900. if (rc)
  5901. return rc;
  5902. }
  5903. mutex_lock(&display->display_lock);
  5904. for (i = 0; i < count; i++) {
  5905. struct dsi_display_mode *m = &display->modes[i];
  5906. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5907. }
  5908. mutex_unlock(&display->display_lock);
  5909. return rc;
  5910. }
  5911. int dsi_display_get_qsync_min_fps(void *display_dsi, u32 mode_fps)
  5912. {
  5913. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5914. struct dsi_panel *panel;
  5915. u32 i;
  5916. if (display == NULL || display->panel == NULL)
  5917. return -EINVAL;
  5918. panel = display->panel;
  5919. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5920. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5921. return panel->qsync_caps.qsync_min_fps_list[i];
  5922. }
  5923. SDE_EVT32(mode_fps);
  5924. DSI_DEBUG("Invalid mode_fps %d\n", mode_fps);
  5925. return -EINVAL;
  5926. }
  5927. int dsi_display_get_avr_step_req_fps(void *display_dsi, u32 mode_fps)
  5928. {
  5929. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5930. struct dsi_panel *panel;
  5931. u32 i, step = 0;
  5932. if (!display || !display->panel)
  5933. return -EINVAL;
  5934. panel = display->panel;
  5935. /* support a single fixed rate, or rate corresponding to dfps list entry */
  5936. if (panel->avr_caps.avr_step_fps_list_len == 1) {
  5937. step = panel->avr_caps.avr_step_fps_list[0];
  5938. } else if (panel->avr_caps.avr_step_fps_list_len > 1) {
  5939. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5940. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5941. step = panel->avr_caps.avr_step_fps_list[i];
  5942. }
  5943. }
  5944. DSI_DEBUG("mode_fps %u, avr_step fps %u\n", mode_fps, step);
  5945. return step;
  5946. }
  5947. static bool dsi_display_match_timings(const struct dsi_display_mode *mode1,
  5948. struct dsi_display_mode *mode2, unsigned int match_flags)
  5949. {
  5950. bool is_matching = false;
  5951. if (match_flags & DSI_MODE_MATCH_ACTIVE_TIMINGS) {
  5952. is_matching = mode1->timing.h_active == mode2->timing.h_active &&
  5953. mode1->timing.v_active == mode2->timing.v_active &&
  5954. mode1->timing.refresh_rate == mode2->timing.refresh_rate;
  5955. if (!is_matching)
  5956. goto end;
  5957. }
  5958. if (match_flags & DSI_MODE_MATCH_PORCH_TIMINGS)
  5959. is_matching = mode1->timing.h_back_porch == mode2->timing.h_back_porch &&
  5960. mode1->timing.h_front_porch == mode2->timing.h_front_porch &&
  5961. mode1->timing.h_sync_width == mode2->timing.h_sync_width &&
  5962. mode1->timing.h_skew == mode2->timing.h_skew &&
  5963. mode1->timing.v_back_porch == mode2->timing.v_back_porch &&
  5964. mode1->timing.v_front_porch == mode2->timing.v_front_porch &&
  5965. mode1->timing.v_sync_width == mode2->timing.v_sync_width;
  5966. end:
  5967. return is_matching;
  5968. }
  5969. static bool dsi_display_mode_match(const struct dsi_display_mode *mode1,
  5970. struct dsi_display_mode *mode2, unsigned int match_flags)
  5971. {
  5972. if (!mode1 && !mode2)
  5973. return true;
  5974. if (!mode1 || !mode2)
  5975. return false;
  5976. if ((match_flags & DSI_MODE_MATCH_FULL_TIMINGS) &&
  5977. !dsi_display_match_timings(mode1, mode2, match_flags))
  5978. return false;
  5979. return true;
  5980. }
  5981. int dsi_display_find_mode(struct dsi_display *display,
  5982. const struct dsi_display_mode *cmp,
  5983. struct dsi_display_mode **out_mode)
  5984. {
  5985. u32 count, i;
  5986. int rc;
  5987. struct dsi_display_mode *m;
  5988. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5989. unsigned int match_flags = DSI_MODE_MATCH_FULL_TIMINGS;
  5990. if (!display || !out_mode)
  5991. return -EINVAL;
  5992. *out_mode = NULL;
  5993. mutex_lock(&display->display_lock);
  5994. count = display->panel->num_display_modes;
  5995. mutex_unlock(&display->display_lock);
  5996. if (!display->modes) {
  5997. rc = dsi_display_get_modes(display, &m);
  5998. if (rc)
  5999. return rc;
  6000. }
  6001. mutex_lock(&display->display_lock);
  6002. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  6003. for (i = 0; i < count; i++) {
  6004. m = &display->modes[i];
  6005. /**
  6006. * When dynamic bit clock is enabled with contants FPS,
  6007. * the adjusted mode porches value may not match the panel
  6008. * default mode porches and panel mode lookup will fail.
  6009. * In that case we omit porches in mode matching function.
  6010. */
  6011. if (dyn_clk_caps->maintain_const_fps)
  6012. match_flags = DSI_MODE_MATCH_ACTIVE_TIMINGS;
  6013. if (dsi_display_mode_match(cmp, m, match_flags)) {
  6014. *out_mode = m;
  6015. rc = 0;
  6016. break;
  6017. }
  6018. }
  6019. mutex_unlock(&display->display_lock);
  6020. if (!*out_mode) {
  6021. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  6022. display->name, cmp->timing.v_active,
  6023. cmp->timing.h_active, cmp->timing.refresh_rate,
  6024. cmp->pixel_clk_khz);
  6025. rc = -ENOENT;
  6026. }
  6027. return rc;
  6028. }
  6029. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  6030. struct dsi_display_mode *adj)
  6031. {
  6032. /*
  6033. * If there is a change in the hfp or vfp of the current and adjoining
  6034. * mode,then either it is a dfps mode switch or dynamic clk change with
  6035. * constant fps.
  6036. */
  6037. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  6038. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  6039. return true;
  6040. else
  6041. return false;
  6042. }
  6043. /**
  6044. * dsi_display_validate_mode_change() - Validate mode change case.
  6045. * @display: DSI display handle.
  6046. * @cur_mode: Current mode.
  6047. * @adj_mode: Mode to be set.
  6048. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  6049. * is change in hfp or vfp but vactive and hactive are same.
  6050. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  6051. * is change in clk but vactive and hactive are same.
  6052. * Return: error code.
  6053. */
  6054. int dsi_display_validate_mode_change(struct dsi_display *display,
  6055. struct dsi_display_mode *cur_mode,
  6056. struct dsi_display_mode *adj_mode)
  6057. {
  6058. int rc = 0;
  6059. struct dsi_dfps_capabilities dfps_caps;
  6060. struct dsi_dyn_clk_caps *dyn_clk_caps;
  6061. struct sde_connector *sde_conn;
  6062. if (!display || !adj_mode || !display->drm_conn) {
  6063. DSI_ERR("Invalid params\n");
  6064. return -EINVAL;
  6065. }
  6066. if (!display->panel || !display->panel->cur_mode) {
  6067. DSI_DEBUG("Current panel mode not set\n");
  6068. return rc;
  6069. }
  6070. if ((cur_mode->timing.v_active != adj_mode->timing.v_active) ||
  6071. (cur_mode->timing.h_active != adj_mode->timing.h_active)) {
  6072. DSI_DEBUG("Avoid VRR and POMS when resolution is changed\n");
  6073. return rc;
  6074. }
  6075. sde_conn = to_sde_connector(display->drm_conn);
  6076. mutex_lock(&display->display_lock);
  6077. if (sde_conn->expected_panel_mode == MSM_DISPLAY_VIDEO_MODE &&
  6078. display->config.panel_mode == DSI_OP_CMD_MODE) {
  6079. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  6080. DSI_DEBUG("Panel operating mode change to video detected\n");
  6081. } else if (sde_conn->expected_panel_mode == MSM_DISPLAY_CMD_MODE &&
  6082. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6083. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  6084. DSI_DEBUG("Panel operating mode change to command detected\n");
  6085. } else {
  6086. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  6087. /* dfps and dynamic clock with const fps use case */
  6088. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  6089. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  6090. if (dfps_caps.dfps_support ||
  6091. dyn_clk_caps->maintain_const_fps) {
  6092. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  6093. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  6094. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1,
  6095. cur_mode->timing.refresh_rate,
  6096. adj_mode->timing.refresh_rate,
  6097. cur_mode->timing.h_front_porch,
  6098. adj_mode->timing.h_front_porch,
  6099. cur_mode->timing.v_front_porch,
  6100. adj_mode->timing.v_front_porch);
  6101. }
  6102. }
  6103. /* dynamic clk change use case */
  6104. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  6105. if (dyn_clk_caps->dyn_clk_support) {
  6106. DSI_DEBUG("dynamic clk change detected\n");
  6107. if ((adj_mode->dsi_mode_flags &
  6108. DSI_MODE_FLAG_VRR) &&
  6109. (!dyn_clk_caps->maintain_const_fps)) {
  6110. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  6111. rc = -ENOTSUPP;
  6112. goto error;
  6113. }
  6114. /**
  6115. * Set VRR flag whenever there is a dynamic clock
  6116. * change on video mode panel as dynamic refresh is
  6117. * always required when fps compensation is enabled.
  6118. */
  6119. if ((display->config.panel_mode == DSI_OP_VIDEO_MODE) &&
  6120. dyn_clk_caps->maintain_const_fps)
  6121. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  6122. adj_mode->dsi_mode_flags |=
  6123. DSI_MODE_FLAG_DYN_CLK;
  6124. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  6125. cur_mode->pixel_clk_khz,
  6126. adj_mode->pixel_clk_khz);
  6127. }
  6128. }
  6129. }
  6130. error:
  6131. mutex_unlock(&display->display_lock);
  6132. return rc;
  6133. }
  6134. int dsi_display_validate_mode(struct dsi_display *display,
  6135. struct dsi_display_mode *mode,
  6136. u32 flags)
  6137. {
  6138. int rc = 0;
  6139. int i;
  6140. struct dsi_display_ctrl *ctrl;
  6141. struct dsi_display_mode adj_mode;
  6142. if (!display || !mode) {
  6143. DSI_ERR("Invalid params\n");
  6144. return -EINVAL;
  6145. }
  6146. mutex_lock(&display->display_lock);
  6147. adj_mode = *mode;
  6148. adjust_timing_by_ctrl_count(display, &adj_mode);
  6149. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  6150. if (rc) {
  6151. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  6152. display->name, rc);
  6153. goto error;
  6154. }
  6155. display_for_each_ctrl(i, display) {
  6156. ctrl = &display->ctrl[i];
  6157. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  6158. if (rc) {
  6159. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  6160. display->name, rc);
  6161. goto error;
  6162. }
  6163. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  6164. if (rc) {
  6165. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  6166. display->name, rc);
  6167. goto error;
  6168. }
  6169. }
  6170. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  6171. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  6172. rc = dsi_display_validate_mode_seamless(display, mode);
  6173. if (rc) {
  6174. DSI_ERR("[%s] seamless not possible rc=%d\n",
  6175. display->name, rc);
  6176. goto error;
  6177. }
  6178. }
  6179. error:
  6180. mutex_unlock(&display->display_lock);
  6181. return rc;
  6182. }
  6183. int dsi_display_set_mode(struct dsi_display *display,
  6184. struct dsi_display_mode *mode,
  6185. u32 flags)
  6186. {
  6187. int rc = 0;
  6188. struct dsi_display_mode adj_mode;
  6189. struct dsi_mode_info timing;
  6190. if (!display || !mode || !display->panel) {
  6191. DSI_ERR("Invalid params\n");
  6192. return -EINVAL;
  6193. }
  6194. mutex_lock(&display->display_lock);
  6195. adj_mode = *mode;
  6196. timing = adj_mode.timing;
  6197. adjust_timing_by_ctrl_count(display, &adj_mode);
  6198. if (!display->panel->cur_mode) {
  6199. display->panel->cur_mode =
  6200. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  6201. if (!display->panel->cur_mode) {
  6202. rc = -ENOMEM;
  6203. goto error;
  6204. }
  6205. }
  6206. rc = dsi_display_restore_bit_clk(display, &adj_mode);
  6207. if (rc) {
  6208. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  6209. goto error;
  6210. }
  6211. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  6212. if (rc) {
  6213. DSI_ERR("[%s] mode cannot be set\n", display->name);
  6214. goto error;
  6215. }
  6216. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  6217. if (rc) {
  6218. DSI_ERR("[%s] failed to set mode\n", display->name);
  6219. goto error;
  6220. }
  6221. DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d, clk_rate=%llu\n",
  6222. adj_mode.priv_info->mdp_transfer_time_us,
  6223. timing.h_active, timing.v_active, timing.refresh_rate,
  6224. adj_mode.priv_info->clk_rate_hz);
  6225. SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
  6226. timing.h_active, timing.v_active, timing.refresh_rate,
  6227. adj_mode.priv_info->clk_rate_hz);
  6228. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  6229. error:
  6230. mutex_unlock(&display->display_lock);
  6231. return rc;
  6232. }
  6233. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  6234. {
  6235. int rc = 0;
  6236. int i;
  6237. struct dsi_display_ctrl *ctrl;
  6238. if (!display) {
  6239. DSI_ERR("Invalid params\n");
  6240. return -EINVAL;
  6241. }
  6242. display_for_each_ctrl(i, display) {
  6243. ctrl = &display->ctrl[i];
  6244. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  6245. if (rc) {
  6246. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  6247. display->name, i);
  6248. goto error;
  6249. }
  6250. }
  6251. display->is_tpg_enabled = enable;
  6252. error:
  6253. return rc;
  6254. }
  6255. static int dsi_display_pre_switch(struct dsi_display *display)
  6256. {
  6257. int rc = 0;
  6258. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6259. DSI_CORE_CLK, DSI_CLK_ON);
  6260. if (rc) {
  6261. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6262. display->name, rc);
  6263. goto error;
  6264. }
  6265. rc = dsi_display_ctrl_update(display);
  6266. if (rc) {
  6267. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  6268. display->name, rc);
  6269. goto error_ctrl_clk_off;
  6270. }
  6271. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6272. DSI_LINK_CLK, DSI_CLK_ON);
  6273. if (rc) {
  6274. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6275. display->name, rc);
  6276. goto error_ctrl_deinit;
  6277. }
  6278. goto error;
  6279. error_ctrl_deinit:
  6280. (void)dsi_display_ctrl_deinit(display);
  6281. error_ctrl_clk_off:
  6282. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6283. DSI_CORE_CLK, DSI_CLK_OFF);
  6284. error:
  6285. return rc;
  6286. }
  6287. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  6288. {
  6289. int i;
  6290. struct dsi_display_ctrl *ctrl;
  6291. display_for_each_ctrl(i, display) {
  6292. ctrl = &display->ctrl[i];
  6293. if (!ctrl->ctrl)
  6294. continue;
  6295. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  6296. return false;
  6297. }
  6298. return true;
  6299. }
  6300. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  6301. {
  6302. struct dsi_display *display = NULL;
  6303. display = container_of(work, struct dsi_display, fifo_underflow_work);
  6304. if (!display || !display->panel ||
  6305. atomic_read(&display->panel->esd_recovery_pending)) {
  6306. DSI_DEBUG("Invalid recovery use case\n");
  6307. return;
  6308. }
  6309. mutex_lock(&display->display_lock);
  6310. if (!_dsi_display_validate_host_state(display)) {
  6311. mutex_unlock(&display->display_lock);
  6312. return;
  6313. }
  6314. DSI_INFO("handle DSI FIFO underflow error\n");
  6315. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6316. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6317. DSI_ALL_CLKS, DSI_CLK_ON);
  6318. dsi_display_soft_reset(display);
  6319. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6320. DSI_ALL_CLKS, DSI_CLK_OFF);
  6321. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6322. mutex_unlock(&display->display_lock);
  6323. }
  6324. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6325. {
  6326. struct dsi_display *display = NULL;
  6327. struct dsi_display_ctrl *ctrl;
  6328. int i, rc;
  6329. int mask = BIT(20); /* clock lane */
  6330. int (*cb_func)(void *event_usr_ptr,
  6331. uint32_t event_idx, uint32_t instance_idx,
  6332. uint32_t data0, uint32_t data1,
  6333. uint32_t data2, uint32_t data3);
  6334. void *data;
  6335. u32 version = 0;
  6336. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6337. if (!display || !display->panel ||
  6338. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6339. atomic_read(&display->panel->esd_recovery_pending)) {
  6340. DSI_DEBUG("Invalid recovery use case\n");
  6341. return;
  6342. }
  6343. mutex_lock(&display->display_lock);
  6344. if (!_dsi_display_validate_host_state(display)) {
  6345. mutex_unlock(&display->display_lock);
  6346. return;
  6347. }
  6348. DSI_INFO("handle DSI FIFO overflow error\n");
  6349. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6350. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6351. DSI_ALL_CLKS, DSI_CLK_ON);
  6352. /*
  6353. * below recovery sequence is not applicable to
  6354. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6355. */
  6356. ctrl = &display->ctrl[display->clk_master_idx];
  6357. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6358. if (!version || (version < 0x20020001))
  6359. goto end;
  6360. /* reset ctrl and lanes */
  6361. display_for_each_ctrl(i, display) {
  6362. ctrl = &display->ctrl[i];
  6363. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6364. rc = dsi_phy_lane_reset(ctrl->phy);
  6365. }
  6366. /* wait for display line count to be in active area */
  6367. ctrl = &display->ctrl[display->clk_master_idx];
  6368. if (ctrl->ctrl->recovery_cb.event_cb) {
  6369. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6370. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6371. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6372. display->clk_master_idx, 0, 0, 0, 0);
  6373. if (rc < 0) {
  6374. DSI_DEBUG("sde callback failed\n");
  6375. goto end;
  6376. }
  6377. }
  6378. /* Enable Video mode for DSI controller */
  6379. display_for_each_ctrl(i, display) {
  6380. ctrl = &display->ctrl[i];
  6381. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6382. }
  6383. /*
  6384. * Add sufficient delay to make sure
  6385. * pixel transmission has started
  6386. */
  6387. udelay(200);
  6388. end:
  6389. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6390. DSI_ALL_CLKS, DSI_CLK_OFF);
  6391. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6392. mutex_unlock(&display->display_lock);
  6393. }
  6394. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6395. {
  6396. struct dsi_display *display = NULL;
  6397. struct dsi_display_ctrl *ctrl;
  6398. int i, rc;
  6399. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6400. int (*cb_func)(void *event_usr_ptr,
  6401. uint32_t event_idx, uint32_t instance_idx,
  6402. uint32_t data0, uint32_t data1,
  6403. uint32_t data2, uint32_t data3);
  6404. void *data;
  6405. u32 version = 0;
  6406. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6407. if (!display || !display->panel ||
  6408. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6409. atomic_read(&display->panel->esd_recovery_pending)) {
  6410. DSI_DEBUG("Invalid recovery use case\n");
  6411. return;
  6412. }
  6413. mutex_lock(&display->display_lock);
  6414. if (!_dsi_display_validate_host_state(display)) {
  6415. mutex_unlock(&display->display_lock);
  6416. return;
  6417. }
  6418. DSI_INFO("handle DSI LP RX Timeout error\n");
  6419. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6420. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6421. DSI_ALL_CLKS, DSI_CLK_ON);
  6422. /*
  6423. * below recovery sequence is not applicable to
  6424. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6425. */
  6426. ctrl = &display->ctrl[display->clk_master_idx];
  6427. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6428. if (!version || (version < 0x20020001))
  6429. goto end;
  6430. /* reset ctrl and lanes */
  6431. display_for_each_ctrl(i, display) {
  6432. ctrl = &display->ctrl[i];
  6433. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6434. rc = dsi_phy_lane_reset(ctrl->phy);
  6435. }
  6436. ctrl = &display->ctrl[display->clk_master_idx];
  6437. if (ctrl->ctrl->recovery_cb.event_cb) {
  6438. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6439. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6440. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6441. display->clk_master_idx, 0, 0, 0, 0);
  6442. if (rc < 0) {
  6443. DSI_DEBUG("Target is in suspend/shutdown\n");
  6444. goto end;
  6445. }
  6446. }
  6447. /* Enable Video mode for DSI controller */
  6448. display_for_each_ctrl(i, display) {
  6449. ctrl = &display->ctrl[i];
  6450. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6451. }
  6452. /*
  6453. * Add sufficient delay to make sure
  6454. * pixel transmission as started
  6455. */
  6456. udelay(200);
  6457. end:
  6458. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6459. DSI_ALL_CLKS, DSI_CLK_OFF);
  6460. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6461. mutex_unlock(&display->display_lock);
  6462. }
  6463. static int dsi_display_cb_error_handler(void *data,
  6464. uint32_t event_idx, uint32_t instance_idx,
  6465. uint32_t data0, uint32_t data1,
  6466. uint32_t data2, uint32_t data3)
  6467. {
  6468. struct dsi_display *display = data;
  6469. if (!display || !(display->err_workq))
  6470. return -EINVAL;
  6471. switch (event_idx) {
  6472. case DSI_FIFO_UNDERFLOW:
  6473. queue_work(display->err_workq, &display->fifo_underflow_work);
  6474. break;
  6475. case DSI_FIFO_OVERFLOW:
  6476. queue_work(display->err_workq, &display->fifo_overflow_work);
  6477. break;
  6478. case DSI_LP_Rx_TIMEOUT:
  6479. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6480. break;
  6481. default:
  6482. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6483. break;
  6484. }
  6485. return 0;
  6486. }
  6487. static void dsi_display_register_error_handler(struct dsi_display *display)
  6488. {
  6489. int i = 0;
  6490. struct dsi_display_ctrl *ctrl;
  6491. struct dsi_event_cb_info event_info;
  6492. if (!display)
  6493. return;
  6494. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6495. if (!display->err_workq) {
  6496. DSI_ERR("failed to create dsi workq!\n");
  6497. return;
  6498. }
  6499. INIT_WORK(&display->fifo_underflow_work,
  6500. dsi_display_handle_fifo_underflow);
  6501. INIT_WORK(&display->fifo_overflow_work,
  6502. dsi_display_handle_fifo_overflow);
  6503. INIT_WORK(&display->lp_rx_timeout_work,
  6504. dsi_display_handle_lp_rx_timeout);
  6505. memset(&event_info, 0, sizeof(event_info));
  6506. event_info.event_cb = dsi_display_cb_error_handler;
  6507. event_info.event_usr_ptr = display;
  6508. display_for_each_ctrl(i, display) {
  6509. ctrl = &display->ctrl[i];
  6510. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6511. }
  6512. }
  6513. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6514. {
  6515. int i = 0;
  6516. struct dsi_display_ctrl *ctrl;
  6517. if (!display)
  6518. return;
  6519. display_for_each_ctrl(i, display) {
  6520. ctrl = &display->ctrl[i];
  6521. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6522. 0, sizeof(struct dsi_event_cb_info));
  6523. }
  6524. if (display->err_workq) {
  6525. destroy_workqueue(display->err_workq);
  6526. display->err_workq = NULL;
  6527. }
  6528. }
  6529. int dsi_display_prepare(struct dsi_display *display)
  6530. {
  6531. int rc = 0;
  6532. struct dsi_display_mode *mode;
  6533. if (!display) {
  6534. DSI_ERR("Invalid params\n");
  6535. return -EINVAL;
  6536. }
  6537. if (!display->panel->cur_mode) {
  6538. DSI_ERR("no valid mode set for the display\n");
  6539. return -EINVAL;
  6540. }
  6541. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6542. mutex_lock(&display->display_lock);
  6543. display->hw_ownership = true;
  6544. mode = display->panel->cur_mode;
  6545. dsi_display_set_ctrl_esd_check_flag(display, false);
  6546. /* Set up ctrl isr before enabling core clk */
  6547. if (!display->trusted_vm_env)
  6548. dsi_display_ctrl_isr_configure(display, true);
  6549. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6550. if (display->is_cont_splash_enabled &&
  6551. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6552. DSI_ERR("DMS not supported on first frame\n");
  6553. rc = -EINVAL;
  6554. goto error;
  6555. }
  6556. if (!is_skip_op_required(display)) {
  6557. /* update dsi ctrl for new mode */
  6558. rc = dsi_display_pre_switch(display);
  6559. if (rc)
  6560. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6561. display->name, rc);
  6562. goto error;
  6563. }
  6564. }
  6565. if (!display->poms_pending &&
  6566. (!is_skip_op_required(display))) {
  6567. /*
  6568. * For continuous splash/trusted vm, we skip panel
  6569. * pre prepare since the regulator vote is already
  6570. * taken care in splash resource init
  6571. */
  6572. rc = dsi_panel_pre_prepare(display->panel);
  6573. if (rc) {
  6574. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6575. display->name, rc);
  6576. goto error;
  6577. }
  6578. }
  6579. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6580. DSI_CORE_CLK, DSI_CLK_ON);
  6581. if (rc) {
  6582. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6583. display->name, rc);
  6584. goto error_panel_post_unprep;
  6585. }
  6586. /*
  6587. * If ULPS during suspend feature is enabled, then DSI PHY was
  6588. * left on during suspend. In this case, we do not need to reset/init
  6589. * PHY. This would have already been done when the CORE clocks are
  6590. * turned on. However, if cont splash is disabled, the first time DSI
  6591. * is powered on, phy init needs to be done unconditionally.
  6592. */
  6593. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6594. rc = dsi_display_phy_sw_reset(display);
  6595. if (rc) {
  6596. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6597. display->name, rc);
  6598. goto error_ctrl_clk_off;
  6599. }
  6600. rc = dsi_display_phy_enable(display);
  6601. if (rc) {
  6602. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6603. display->name, rc);
  6604. goto error_ctrl_clk_off;
  6605. }
  6606. }
  6607. rc = dsi_display_ctrl_init(display);
  6608. if (rc) {
  6609. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6610. display->name, rc);
  6611. goto error_phy_disable;
  6612. }
  6613. /* Set up DSI ERROR event callback */
  6614. dsi_display_register_error_handler(display);
  6615. rc = dsi_display_ctrl_host_enable(display);
  6616. if (rc) {
  6617. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6618. display->name, rc);
  6619. goto error_ctrl_deinit;
  6620. }
  6621. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6622. DSI_LINK_CLK, DSI_CLK_ON);
  6623. if (rc) {
  6624. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6625. display->name, rc);
  6626. goto error_host_engine_off;
  6627. }
  6628. if (!is_skip_op_required(display)) {
  6629. /*
  6630. * For continuous splash/trusted vm, skip panel prepare and
  6631. * ctl reset since the pnael and ctrl is already in active
  6632. * state and panel on commands are not needed
  6633. */
  6634. rc = dsi_display_soft_reset(display);
  6635. if (rc) {
  6636. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6637. display->name, rc);
  6638. goto error_ctrl_link_off;
  6639. }
  6640. if (!display->poms_pending) {
  6641. rc = dsi_panel_prepare(display->panel);
  6642. if (rc) {
  6643. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6644. display->name, rc);
  6645. goto error_ctrl_link_off;
  6646. }
  6647. }
  6648. }
  6649. goto error;
  6650. error_ctrl_link_off:
  6651. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6652. DSI_LINK_CLK, DSI_CLK_OFF);
  6653. error_host_engine_off:
  6654. (void)dsi_display_ctrl_host_disable(display);
  6655. error_ctrl_deinit:
  6656. (void)dsi_display_ctrl_deinit(display);
  6657. error_phy_disable:
  6658. (void)dsi_display_phy_disable(display);
  6659. error_ctrl_clk_off:
  6660. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6661. DSI_CORE_CLK, DSI_CLK_OFF);
  6662. error_panel_post_unprep:
  6663. (void)dsi_panel_post_unprepare(display->panel);
  6664. error:
  6665. mutex_unlock(&display->display_lock);
  6666. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6667. return rc;
  6668. }
  6669. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6670. const struct dsi_display_ctrl *ctrl,
  6671. const struct msm_roi_list *req_rois,
  6672. struct dsi_rect *out_roi)
  6673. {
  6674. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6675. struct dsi_display_mode *cur_mode;
  6676. struct msm_roi_caps *roi_caps;
  6677. struct dsi_rect req_roi = { 0 };
  6678. int rc = 0;
  6679. cur_mode = display->panel->cur_mode;
  6680. if (!cur_mode)
  6681. return 0;
  6682. roi_caps = &cur_mode->priv_info->roi_caps;
  6683. if (req_rois->num_rects > roi_caps->num_roi) {
  6684. DSI_ERR("request for %d rois greater than max %d\n",
  6685. req_rois->num_rects,
  6686. roi_caps->num_roi);
  6687. rc = -EINVAL;
  6688. goto exit;
  6689. }
  6690. /**
  6691. * if no rois, user wants to reset back to full resolution
  6692. * note: h_active is already divided by ctrl_count
  6693. */
  6694. if (!req_rois->num_rects) {
  6695. *out_roi = *bounds;
  6696. goto exit;
  6697. }
  6698. /* intersect with the bounds */
  6699. req_roi.x = req_rois->roi[0].x1;
  6700. req_roi.y = req_rois->roi[0].y1;
  6701. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6702. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6703. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6704. exit:
  6705. /* adjust the ctrl origin to be top left within the ctrl */
  6706. out_roi->x = out_roi->x - bounds->x;
  6707. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6708. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6709. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6710. bounds->x, bounds->y, bounds->w, bounds->h,
  6711. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6712. return rc;
  6713. }
  6714. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6715. {
  6716. int i;
  6717. int rc = 0;
  6718. if (!display->panel->qsync_caps.qsync_min_fps) {
  6719. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6720. return 0;
  6721. }
  6722. mutex_lock(&display->display_lock);
  6723. display_for_each_ctrl(i, display) {
  6724. if (enable) {
  6725. /* send the commands to enable qsync */
  6726. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6727. if (rc) {
  6728. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6729. goto exit;
  6730. }
  6731. } else {
  6732. /* send the commands to enable qsync */
  6733. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6734. if (rc) {
  6735. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6736. goto exit;
  6737. }
  6738. }
  6739. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6740. }
  6741. exit:
  6742. SDE_EVT32(enable, display->panel->qsync_caps.qsync_min_fps, rc);
  6743. mutex_unlock(&display->display_lock);
  6744. return rc;
  6745. }
  6746. static int dsi_display_set_roi(struct dsi_display *display,
  6747. struct msm_roi_list *rois)
  6748. {
  6749. struct dsi_display_mode *cur_mode;
  6750. struct msm_roi_caps *roi_caps;
  6751. int rc = 0;
  6752. int i;
  6753. if (!display || !rois || !display->panel)
  6754. return -EINVAL;
  6755. cur_mode = display->panel->cur_mode;
  6756. if (!cur_mode)
  6757. return 0;
  6758. roi_caps = &cur_mode->priv_info->roi_caps;
  6759. if (!roi_caps->enabled)
  6760. return 0;
  6761. display_for_each_ctrl(i, display) {
  6762. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6763. struct dsi_rect ctrl_roi;
  6764. bool changed = false;
  6765. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6766. if (rc) {
  6767. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6768. return rc;
  6769. }
  6770. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6771. if (rc) {
  6772. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6773. return rc;
  6774. }
  6775. if (!changed)
  6776. continue;
  6777. /* send the new roi to the panel via dcs commands */
  6778. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6779. if (rc) {
  6780. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6781. return rc;
  6782. }
  6783. /* re-program the ctrl with the timing based on the new roi */
  6784. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6785. if (rc) {
  6786. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6787. return rc;
  6788. }
  6789. }
  6790. return rc;
  6791. }
  6792. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6793. struct dsi_display *display,
  6794. struct msm_display_kickoff_params *params)
  6795. {
  6796. int rc = 0, ret = 0;
  6797. int i;
  6798. /* check and setup MISR */
  6799. if (display->misr_enable)
  6800. _dsi_display_setup_misr(display);
  6801. /* dynamic DSI clock setting */
  6802. if (atomic_read(&display->clkrate_change_pending)) {
  6803. mutex_lock(&display->display_lock);
  6804. /*
  6805. * acquire panel_lock to make sure no commands are in progress
  6806. */
  6807. dsi_panel_acquire_panel_lock(display->panel);
  6808. /*
  6809. * Wait for DSI command engine not to be busy sending data
  6810. * from display engine.
  6811. * If waiting fails, return "rc" instead of below "ret" so as
  6812. * not to impact DRM commit. The clock updating would be
  6813. * deferred to the next DRM commit.
  6814. */
  6815. display_for_each_ctrl(i, display) {
  6816. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6817. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6818. if (ret)
  6819. goto wait_failure;
  6820. }
  6821. /*
  6822. * Don't check the return value so as not to impact DRM commit
  6823. * when error occurs.
  6824. */
  6825. (void)dsi_display_force_update_dsi_clk(display);
  6826. wait_failure:
  6827. /* release panel_lock */
  6828. dsi_panel_release_panel_lock(display->panel);
  6829. mutex_unlock(&display->display_lock);
  6830. }
  6831. if (!ret)
  6832. rc = dsi_display_set_roi(display, params->rois);
  6833. return rc;
  6834. }
  6835. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6836. {
  6837. int rc = 0;
  6838. if (!display || !display->panel) {
  6839. DSI_ERR("Invalid params\n");
  6840. return -EINVAL;
  6841. }
  6842. if (!display->panel->cur_mode) {
  6843. DSI_ERR("no valid mode set for the display\n");
  6844. return -EINVAL;
  6845. }
  6846. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6847. rc = dsi_display_vid_engine_enable(display);
  6848. if (rc) {
  6849. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6850. display->name, rc);
  6851. goto error_out;
  6852. }
  6853. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6854. rc = dsi_display_cmd_engine_enable(display);
  6855. if (rc) {
  6856. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6857. display->name, rc);
  6858. goto error_out;
  6859. }
  6860. } else {
  6861. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6862. rc = -EINVAL;
  6863. }
  6864. error_out:
  6865. return rc;
  6866. }
  6867. int dsi_display_pre_commit(void *display,
  6868. struct msm_display_conn_params *params)
  6869. {
  6870. bool enable = false;
  6871. int rc = 0;
  6872. if (!display || !params) {
  6873. pr_err("Invalid params\n");
  6874. return -EINVAL;
  6875. }
  6876. if (params->qsync_update) {
  6877. enable = (params->qsync_mode > 0) ? true : false;
  6878. rc = dsi_display_qsync(display, enable);
  6879. if (rc)
  6880. pr_err("%s failed to send qsync commands\n",
  6881. __func__);
  6882. SDE_EVT32(params->qsync_mode, rc);
  6883. }
  6884. return rc;
  6885. }
  6886. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6887. {
  6888. if (display->panel_id != ~0x0 &&
  6889. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6890. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6891. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6892. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6893. 0, ((display->panel_id & 0xffffffff00000000) >> 32),
  6894. (display->panel_id & 0xffffffff), 0, 0);
  6895. }
  6896. }
  6897. int dsi_display_enable(struct dsi_display *display)
  6898. {
  6899. int rc = 0;
  6900. struct dsi_display_mode *mode;
  6901. if (!display || !display->panel) {
  6902. DSI_ERR("Invalid params\n");
  6903. return -EINVAL;
  6904. }
  6905. if (!display->panel->cur_mode) {
  6906. DSI_ERR("no valid mode set for the display\n");
  6907. return -EINVAL;
  6908. }
  6909. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6910. /*
  6911. * Engine states and panel states are populated during splash
  6912. * resource/trusted vm and hence we return early
  6913. */
  6914. if (is_skip_op_required(display)) {
  6915. dsi_display_config_ctrl_for_cont_splash(display);
  6916. rc = dsi_display_splash_res_cleanup(display);
  6917. if (rc) {
  6918. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6919. rc);
  6920. return -EINVAL;
  6921. }
  6922. display->panel->panel_initialized = true;
  6923. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6924. dsi_display_panel_id_notification(display);
  6925. return 0;
  6926. }
  6927. mutex_lock(&display->display_lock);
  6928. mode = display->panel->cur_mode;
  6929. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6930. rc = dsi_panel_post_switch(display->panel);
  6931. if (rc) {
  6932. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6933. display->name, rc);
  6934. goto error;
  6935. }
  6936. } else if (!display->poms_pending) {
  6937. rc = dsi_panel_enable(display->panel);
  6938. if (rc) {
  6939. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6940. display->name, rc);
  6941. goto error;
  6942. }
  6943. }
  6944. dsi_display_panel_id_notification(display);
  6945. /* Block sending pps command if modeset is due to fps difference */
  6946. if ((mode->priv_info->dsc_enabled ||
  6947. mode->priv_info->vdc_enabled) &&
  6948. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6949. rc = dsi_panel_update_pps(display->panel);
  6950. if (rc) {
  6951. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6952. display->name, rc);
  6953. goto error;
  6954. }
  6955. }
  6956. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6957. rc = dsi_panel_switch(display->panel);
  6958. if (rc)
  6959. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6960. display->name, rc);
  6961. goto error;
  6962. }
  6963. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6964. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6965. rc = dsi_display_vid_engine_enable(display);
  6966. if (rc) {
  6967. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6968. display->name, rc);
  6969. goto error_disable_panel;
  6970. }
  6971. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6972. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6973. rc = dsi_display_cmd_engine_enable(display);
  6974. if (rc) {
  6975. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6976. display->name, rc);
  6977. goto error_disable_panel;
  6978. }
  6979. } else {
  6980. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6981. rc = -EINVAL;
  6982. goto error_disable_panel;
  6983. }
  6984. goto error;
  6985. error_disable_panel:
  6986. (void)dsi_panel_disable(display->panel);
  6987. error:
  6988. mutex_unlock(&display->display_lock);
  6989. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6990. return rc;
  6991. }
  6992. int dsi_display_post_enable(struct dsi_display *display)
  6993. {
  6994. int rc = 0;
  6995. if (!display) {
  6996. DSI_ERR("Invalid params\n");
  6997. return -EINVAL;
  6998. }
  6999. mutex_lock(&display->display_lock);
  7000. if (display->panel->cur_mode->dsi_mode_flags &
  7001. DSI_MODE_FLAG_POMS_TO_CMD) {
  7002. dsi_panel_switch_cmd_mode_in(display->panel);
  7003. } else if (display->panel->cur_mode->dsi_mode_flags &
  7004. DSI_MODE_FLAG_POMS_TO_VID)
  7005. dsi_panel_switch_video_mode_in(display->panel);
  7006. else {
  7007. rc = dsi_panel_post_enable(display->panel);
  7008. if (rc)
  7009. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  7010. display->name, rc);
  7011. }
  7012. /* remove the clk vote for CMD mode panels */
  7013. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7014. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7015. DSI_ALL_CLKS, DSI_CLK_OFF);
  7016. mutex_unlock(&display->display_lock);
  7017. return rc;
  7018. }
  7019. int dsi_display_pre_disable(struct dsi_display *display)
  7020. {
  7021. int rc = 0;
  7022. if (!display) {
  7023. DSI_ERR("Invalid params\n");
  7024. return -EINVAL;
  7025. }
  7026. mutex_lock(&display->display_lock);
  7027. /* enable the clk vote for CMD mode panels */
  7028. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7029. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7030. DSI_ALL_CLKS, DSI_CLK_ON);
  7031. if (display->poms_pending) {
  7032. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  7033. dsi_panel_switch_cmd_mode_out(display->panel);
  7034. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7035. /*
  7036. * Add unbalanced vote for clock & cmd engine to enable
  7037. * async trigger of pre video to cmd mode switch.
  7038. */
  7039. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7040. DSI_ALL_CLKS, DSI_CLK_ON);
  7041. if (rc) {
  7042. DSI_ERR("[%s]failed to enable all clocks,rc=%d",
  7043. display->name, rc);
  7044. goto exit;
  7045. }
  7046. rc = dsi_display_cmd_engine_enable(display);
  7047. if (rc) {
  7048. DSI_ERR("[%s]failed to enable cmd engine,rc=%d",
  7049. display->name, rc);
  7050. goto error_disable_clks;
  7051. }
  7052. dsi_panel_switch_video_mode_out(display->panel);
  7053. }
  7054. } else {
  7055. rc = dsi_panel_pre_disable(display->panel);
  7056. if (rc)
  7057. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  7058. display->name, rc);
  7059. }
  7060. goto exit;
  7061. error_disable_clks:
  7062. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7063. DSI_ALL_CLKS, DSI_CLK_OFF);
  7064. if (rc)
  7065. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  7066. display->name, rc);
  7067. exit:
  7068. mutex_unlock(&display->display_lock);
  7069. return rc;
  7070. }
  7071. static void dsi_display_handle_poms_te(struct work_struct *work)
  7072. {
  7073. struct dsi_display *display = NULL;
  7074. struct delayed_work *dw = to_delayed_work(work);
  7075. struct mipi_dsi_device *dsi = NULL;
  7076. struct dsi_panel *panel = NULL;
  7077. int rc = 0;
  7078. display = container_of(dw, struct dsi_display, poms_te_work);
  7079. if (!display || !display->panel) {
  7080. DSI_ERR("Invalid params\n");
  7081. return;
  7082. }
  7083. panel = display->panel;
  7084. mutex_lock(&panel->panel_lock);
  7085. if (!dsi_panel_initialized(panel)) {
  7086. rc = -EINVAL;
  7087. goto error;
  7088. }
  7089. dsi = &panel->mipi_device;
  7090. rc = mipi_dsi_dcs_set_tear_off(dsi);
  7091. error:
  7092. mutex_unlock(&panel->panel_lock);
  7093. if (rc < 0)
  7094. DSI_ERR("failed to set tear off\n");
  7095. }
  7096. int dsi_display_disable(struct dsi_display *display)
  7097. {
  7098. int rc = 0;
  7099. if (!display) {
  7100. DSI_ERR("Invalid params\n");
  7101. return -EINVAL;
  7102. }
  7103. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7104. mutex_lock(&display->display_lock);
  7105. /* cancel delayed work */
  7106. if (display->poms_pending &&
  7107. display->panel->poms_align_vsync)
  7108. cancel_delayed_work_sync(&display->poms_te_work);
  7109. rc = dsi_display_wake_up(display);
  7110. if (rc)
  7111. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7112. display->name, rc);
  7113. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7114. rc = dsi_display_vid_engine_disable(display);
  7115. if (rc)
  7116. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  7117. display->name, rc);
  7118. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  7119. /**
  7120. * On POMS request , disable panel TE through
  7121. * delayed work queue.
  7122. */
  7123. if (display->poms_pending &&
  7124. display->panel->poms_align_vsync) {
  7125. INIT_DELAYED_WORK(&display->poms_te_work,
  7126. dsi_display_handle_poms_te);
  7127. queue_delayed_work(system_wq,
  7128. &display->poms_te_work,
  7129. msecs_to_jiffies(100));
  7130. }
  7131. rc = dsi_display_cmd_engine_disable(display);
  7132. if (rc)
  7133. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  7134. display->name, rc);
  7135. } else {
  7136. DSI_ERR("[%s] Invalid configuration\n", display->name);
  7137. rc = -EINVAL;
  7138. }
  7139. if (!display->poms_pending && !is_skip_op_required(display)) {
  7140. rc = dsi_panel_disable(display->panel);
  7141. if (rc)
  7142. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  7143. display->name, rc);
  7144. }
  7145. if (is_skip_op_required(display)) {
  7146. /* applicable only for trusted vm */
  7147. display->panel->panel_initialized = false;
  7148. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  7149. }
  7150. mutex_unlock(&display->display_lock);
  7151. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7152. return rc;
  7153. }
  7154. int dsi_display_update_pps(char *pps_cmd, void *disp)
  7155. {
  7156. struct dsi_display *display;
  7157. if (pps_cmd == NULL || disp == NULL) {
  7158. DSI_ERR("Invalid parameter\n");
  7159. return -EINVAL;
  7160. }
  7161. display = disp;
  7162. mutex_lock(&display->display_lock);
  7163. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  7164. mutex_unlock(&display->display_lock);
  7165. return 0;
  7166. }
  7167. int dsi_display_update_dyn_bit_clk(struct dsi_display *display,
  7168. struct dsi_display_mode *mode)
  7169. {
  7170. struct dsi_dyn_clk_caps *dyn_clk_caps;
  7171. struct dsi_host_common_cfg *host_cfg;
  7172. int bpp, lanes = 0;
  7173. if (!display || !mode) {
  7174. DSI_ERR("invalid arguments\n");
  7175. return -EINVAL;
  7176. }
  7177. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  7178. if (!dyn_clk_caps->dyn_clk_support) {
  7179. DSI_DEBUG("dynamic bit clock support not enabled\n");
  7180. return 0;
  7181. } else if (!display->dyn_bit_clk_pending) {
  7182. DSI_DEBUG("dynamic bit clock rate not updated\n");
  7183. return 0;
  7184. } else if (!display->dyn_bit_clk) {
  7185. DSI_DEBUG("dynamic bit clock rate cleared\n");
  7186. return 0;
  7187. } else if (display->dyn_bit_clk < mode->priv_info->min_dsi_clk_hz) {
  7188. DSI_ERR("dynamic bit clock rate %llu smaller than minimum value:%llu\n",
  7189. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz);
  7190. return -EINVAL;
  7191. }
  7192. /* update mode clk rate with user value */
  7193. mode->timing.clk_rate_hz = display->dyn_bit_clk;
  7194. mode->priv_info->clk_rate_hz = display->dyn_bit_clk;
  7195. host_cfg = &(display->panel->host_config);
  7196. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  7197. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  7198. lanes++;
  7199. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  7200. lanes++;
  7201. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  7202. lanes++;
  7203. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  7204. lanes++;
  7205. dsi_display_adjust_mode_timing(display, mode, lanes, bpp);
  7206. /* adjust pixel clock based on dynamic bit clock */
  7207. mode->pixel_clk_khz = div_u64(mode->timing.clk_rate_hz * lanes, bpp);
  7208. do_div(mode->pixel_clk_khz, 1000);
  7209. mode->pixel_clk_khz *= display->ctrl_count;
  7210. SDE_EVT32(display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, mode->pixel_clk_khz);
  7211. DSI_DEBUG("dynamic bit clk:%u, min dsi clk:%llu, lanes:%d, bpp:%d, pck:%d Khz\n",
  7212. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, lanes, bpp,
  7213. mode->pixel_clk_khz);
  7214. display->dyn_bit_clk_pending = false;
  7215. return 0;
  7216. }
  7217. int dsi_display_dump_clks_state(struct dsi_display *display)
  7218. {
  7219. int rc = 0;
  7220. if (!display) {
  7221. DSI_ERR("invalid display argument\n");
  7222. return -EINVAL;
  7223. }
  7224. if (!display->clk_mngr) {
  7225. DSI_ERR("invalid clk manager\n");
  7226. return -EINVAL;
  7227. }
  7228. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  7229. DSI_ERR("invalid clk handles\n");
  7230. return -EINVAL;
  7231. }
  7232. mutex_lock(&display->display_lock);
  7233. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  7234. if (rc) {
  7235. DSI_ERR("failed to dump dsi clock state\n");
  7236. goto end;
  7237. }
  7238. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  7239. if (rc) {
  7240. DSI_ERR("failed to dump mdp clock state\n");
  7241. goto end;
  7242. }
  7243. end:
  7244. mutex_unlock(&display->display_lock);
  7245. return rc;
  7246. }
  7247. int dsi_display_unprepare(struct dsi_display *display)
  7248. {
  7249. int rc = 0, i;
  7250. struct dsi_display_ctrl *ctrl;
  7251. if (!display) {
  7252. DSI_ERR("Invalid params\n");
  7253. return -EINVAL;
  7254. }
  7255. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7256. mutex_lock(&display->display_lock);
  7257. rc = dsi_display_wake_up(display);
  7258. if (rc)
  7259. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7260. display->name, rc);
  7261. if (!display->poms_pending && !is_skip_op_required(display)) {
  7262. rc = dsi_panel_unprepare(display->panel);
  7263. if (rc)
  7264. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  7265. display->name, rc);
  7266. }
  7267. /* Remove additional vote added for pre_mode_switch_to_cmd */
  7268. if (display->poms_pending &&
  7269. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7270. display_for_each_ctrl(i, display) {
  7271. ctrl = &display->ctrl[i];
  7272. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  7273. continue;
  7274. flush_workqueue(display->dma_cmd_workq);
  7275. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  7276. ctrl->ctrl->dma_wait_queued = false;
  7277. }
  7278. dsi_display_cmd_engine_disable(display);
  7279. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7280. DSI_ALL_CLKS, DSI_CLK_OFF);
  7281. }
  7282. rc = dsi_display_ctrl_host_disable(display);
  7283. if (rc)
  7284. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  7285. display->name, rc);
  7286. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7287. DSI_LINK_CLK, DSI_CLK_OFF);
  7288. if (rc)
  7289. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  7290. display->name, rc);
  7291. rc = dsi_display_ctrl_deinit(display);
  7292. if (rc)
  7293. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  7294. display->name, rc);
  7295. if (!display->panel->ulps_suspend_enabled) {
  7296. rc = dsi_display_phy_disable(display);
  7297. if (rc)
  7298. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  7299. display->name, rc);
  7300. }
  7301. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7302. DSI_CORE_CLK, DSI_CLK_OFF);
  7303. if (rc)
  7304. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  7305. display->name, rc);
  7306. /* destrory dsi isr set up */
  7307. dsi_display_ctrl_isr_configure(display, false);
  7308. if (!display->poms_pending && !is_skip_op_required(display)) {
  7309. rc = dsi_panel_post_unprepare(display->panel);
  7310. if (rc)
  7311. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  7312. display->name, rc);
  7313. }
  7314. display->hw_ownership = false;
  7315. mutex_unlock(&display->display_lock);
  7316. /* Free up DSI ERROR event callback */
  7317. dsi_display_unregister_error_handler(display);
  7318. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7319. return rc;
  7320. }
  7321. void __init dsi_display_register(void)
  7322. {
  7323. dsi_phy_drv_register();
  7324. dsi_ctrl_drv_register();
  7325. dsi_display_parse_boot_display_selection();
  7326. platform_driver_register(&dsi_display_driver);
  7327. }
  7328. void __exit dsi_display_unregister(void)
  7329. {
  7330. platform_driver_unregister(&dsi_display_driver);
  7331. dsi_ctrl_drv_unregister();
  7332. dsi_phy_drv_unregister();
  7333. }
  7334. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  7335. 0600);
  7336. MODULE_PARM_DESC(dsi_display0,
  7337. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  7338. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  7339. 0600);
  7340. MODULE_PARM_DESC(dsi_display1,
  7341. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");