dsi_display.c 211 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define MAX_TE_RECHECKS 5
  28. #define DSI_CLOCK_BITRATE_RADIX 10
  29. #define MAX_TE_SOURCE_ID 2
  30. #define SEC_PANEL_NAME_MAX_LEN 256
  31. u8 dbgfs_tx_cmd_buf[SZ_4K];
  32. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  33. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  34. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  35. {.boot_param = dsi_display_primary},
  36. {.boot_param = dsi_display_secondary},
  37. };
  38. static const struct of_device_id dsi_display_dt_match[] = {
  39. {.compatible = "qcom,dsi-display"},
  40. {}
  41. };
  42. bool is_skip_op_required(struct dsi_display *display)
  43. {
  44. if (!display)
  45. return false;
  46. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  47. }
  48. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  49. u32 mask, bool enable)
  50. {
  51. int i;
  52. struct dsi_display_ctrl *ctrl;
  53. if (!display)
  54. return;
  55. display_for_each_ctrl(i, display) {
  56. ctrl = &display->ctrl[i];
  57. if (!ctrl)
  58. continue;
  59. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  60. }
  61. }
  62. static int dsi_display_config_clk_gating(struct dsi_display *display,
  63. bool enable)
  64. {
  65. int rc = 0, i = 0;
  66. struct dsi_display_ctrl *mctrl, *ctrl;
  67. enum dsi_clk_gate_type clk_selection;
  68. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  69. if (!display) {
  70. DSI_ERR("Invalid params\n");
  71. return -EINVAL;
  72. }
  73. if (display->panel->host_config.force_hs_clk_lane) {
  74. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  75. return 0;
  76. }
  77. mctrl = &display->ctrl[display->clk_master_idx];
  78. if (!mctrl) {
  79. DSI_ERR("Invalid controller\n");
  80. return -EINVAL;
  81. }
  82. clk_selection = display->clk_gating_config;
  83. if (!enable) {
  84. /* for disable path, make sure to disable all clk gating */
  85. clk_selection = DSI_CLK_ALL;
  86. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  87. /* Default selection, no overrides */
  88. clk_selection = default_clk_select;
  89. } else if (clk_selection == DSI_CLK_NONE) {
  90. clk_selection = 0;
  91. }
  92. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  93. enable ? "Enabling" : "Disabling",
  94. clk_selection & BYTE_CLK ? "yes" : "no",
  95. clk_selection & PIXEL_CLK ? "yes" : "no",
  96. clk_selection & DSI_PHY ? "yes" : "no");
  97. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  98. if (rc) {
  99. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  100. display->name, enable ? "enable" : "disable",
  101. clk_selection, rc);
  102. return rc;
  103. }
  104. display_for_each_ctrl(i, display) {
  105. ctrl = &display->ctrl[i];
  106. if (!ctrl->ctrl || (ctrl == mctrl))
  107. continue;
  108. /**
  109. * In Split DSI usecase we should not enable clock gating on
  110. * DSI PHY1 to ensure no display atrifacts are seen.
  111. */
  112. clk_selection &= ~DSI_PHY;
  113. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  114. clk_selection);
  115. if (rc) {
  116. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  117. display->name, enable ? "enable" : "disable",
  118. clk_selection, rc);
  119. return rc;
  120. }
  121. }
  122. return 0;
  123. }
  124. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  125. bool enable)
  126. {
  127. int i;
  128. struct dsi_display_ctrl *ctrl;
  129. if (!display)
  130. return;
  131. display_for_each_ctrl(i, display) {
  132. ctrl = &display->ctrl[i];
  133. if (!ctrl)
  134. continue;
  135. ctrl->ctrl->esd_check_underway = enable;
  136. }
  137. }
  138. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  139. {
  140. int i;
  141. struct dsi_display_ctrl *ctrl;
  142. if (!display)
  143. return;
  144. display_for_each_ctrl(i, display) {
  145. ctrl = &display->ctrl[i];
  146. if (!ctrl)
  147. continue;
  148. dsi_ctrl_irq_update(ctrl->ctrl, en);
  149. }
  150. }
  151. void dsi_rect_intersect(const struct dsi_rect *r1,
  152. const struct dsi_rect *r2,
  153. struct dsi_rect *result)
  154. {
  155. int l, t, r, b;
  156. if (!r1 || !r2 || !result)
  157. return;
  158. l = max(r1->x, r2->x);
  159. t = max(r1->y, r2->y);
  160. r = min((r1->x + r1->w), (r2->x + r2->w));
  161. b = min((r1->y + r1->h), (r2->y + r2->h));
  162. if (r <= l || b <= t) {
  163. memset(result, 0, sizeof(*result));
  164. } else {
  165. result->x = l;
  166. result->y = t;
  167. result->w = r - l;
  168. result->h = b - t;
  169. }
  170. }
  171. int dsi_display_set_backlight(struct drm_connector *connector,
  172. void *display, u32 bl_lvl)
  173. {
  174. struct dsi_display *dsi_display = display;
  175. struct dsi_panel *panel;
  176. u32 bl_scale, bl_scale_sv;
  177. u64 bl_temp;
  178. int rc = 0;
  179. if (dsi_display == NULL || dsi_display->panel == NULL)
  180. return -EINVAL;
  181. panel = dsi_display->panel;
  182. mutex_lock(&panel->panel_lock);
  183. if (!dsi_panel_initialized(panel)) {
  184. rc = -EINVAL;
  185. goto error;
  186. }
  187. panel->bl_config.bl_level = bl_lvl;
  188. /* scale backlight */
  189. bl_scale = panel->bl_config.bl_scale;
  190. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  191. bl_scale_sv = panel->bl_config.bl_scale_sv;
  192. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  193. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  194. bl_scale, bl_scale_sv, (u32)bl_temp);
  195. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  196. DSI_CORE_CLK, DSI_CLK_ON);
  197. if (rc) {
  198. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  199. dsi_display->name, rc);
  200. goto error;
  201. }
  202. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  203. if (rc)
  204. DSI_ERR("unable to set backlight\n");
  205. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  206. DSI_CORE_CLK, DSI_CLK_OFF);
  207. if (rc) {
  208. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  209. dsi_display->name, rc);
  210. goto error;
  211. }
  212. error:
  213. mutex_unlock(&panel->panel_lock);
  214. return rc;
  215. }
  216. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  217. {
  218. int rc = 0;
  219. int i;
  220. struct dsi_display_ctrl *m_ctrl, *ctrl;
  221. bool skip_op = is_skip_op_required(display);
  222. m_ctrl = &display->ctrl[display->cmd_master_idx];
  223. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  224. if (display->cmd_engine_refcount > 0) {
  225. display->cmd_engine_refcount++;
  226. goto done;
  227. }
  228. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  229. DSI_CTRL_ENGINE_ON, skip_op);
  230. if (rc) {
  231. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  232. display->name, skip_op, rc);
  233. goto done;
  234. }
  235. display_for_each_ctrl(i, display) {
  236. ctrl = &display->ctrl[i];
  237. if (!ctrl->ctrl || (ctrl == m_ctrl))
  238. continue;
  239. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  240. DSI_CTRL_ENGINE_ON, skip_op);
  241. if (rc) {
  242. DSI_ERR(
  243. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  244. display->name, skip_op, rc);
  245. goto error_disable_master;
  246. }
  247. }
  248. display->cmd_engine_refcount++;
  249. goto done;
  250. error_disable_master:
  251. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  252. DSI_CTRL_ENGINE_OFF, skip_op);
  253. done:
  254. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  255. return rc;
  256. }
  257. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  258. {
  259. int rc = 0;
  260. int i;
  261. struct dsi_display_ctrl *m_ctrl, *ctrl;
  262. bool skip_op = is_skip_op_required(display);
  263. m_ctrl = &display->ctrl[display->cmd_master_idx];
  264. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  265. if (display->cmd_engine_refcount == 0) {
  266. DSI_ERR("[%s] Invalid refcount\n", display->name);
  267. goto done;
  268. } else if (display->cmd_engine_refcount > 1) {
  269. display->cmd_engine_refcount--;
  270. goto done;
  271. }
  272. display_for_each_ctrl(i, display) {
  273. ctrl = &display->ctrl[i];
  274. if (!ctrl->ctrl || (ctrl == m_ctrl))
  275. continue;
  276. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  277. DSI_CTRL_ENGINE_OFF, skip_op);
  278. if (rc)
  279. DSI_ERR(
  280. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  281. display->name, skip_op, rc);
  282. }
  283. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  284. DSI_CTRL_ENGINE_OFF, skip_op);
  285. if (rc) {
  286. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  287. display->name, skip_op, rc);
  288. goto error;
  289. }
  290. error:
  291. display->cmd_engine_refcount = 0;
  292. done:
  293. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  294. return rc;
  295. }
  296. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  297. {
  298. struct dsi_display *display;
  299. struct dsi_display_ctrl *display_ctrl;
  300. int rc, cnt;
  301. if (!cb_data) {
  302. DSI_ERR("aspace cb called with invalid cb_data\n");
  303. return;
  304. }
  305. display = (struct dsi_display *)cb_data;
  306. /*
  307. * acquire panel_lock to make sure no commands are in-progress
  308. * while detaching the non-secure context banks
  309. */
  310. dsi_panel_acquire_panel_lock(display->panel);
  311. if (is_detach) {
  312. /* invalidate the stored iova */
  313. display->cmd_buffer_iova = 0;
  314. /* return the virtual address mapping */
  315. msm_gem_put_vaddr(display->tx_cmd_buf);
  316. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  317. } else {
  318. rc = msm_gem_get_iova(display->tx_cmd_buf,
  319. display->aspace, &(display->cmd_buffer_iova));
  320. if (rc) {
  321. DSI_ERR("failed to get the iova rc %d\n", rc);
  322. goto end;
  323. }
  324. display->vaddr =
  325. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  326. if (IS_ERR_OR_NULL(display->vaddr)) {
  327. DSI_ERR("failed to get va rc %d\n", rc);
  328. goto end;
  329. }
  330. }
  331. display_for_each_ctrl(cnt, display) {
  332. display_ctrl = &display->ctrl[cnt];
  333. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  334. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  335. display_ctrl->ctrl->vaddr = display->vaddr;
  336. display_ctrl->ctrl->secure_mode = is_detach;
  337. }
  338. end:
  339. /* release panel_lock */
  340. dsi_panel_release_panel_lock(display->panel);
  341. }
  342. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  343. {
  344. struct dsi_display *display = (struct dsi_display *)data;
  345. /*
  346. * This irq handler is used for sole purpose of identifying
  347. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  348. * in case of display not being initialized yet
  349. */
  350. if (!display)
  351. return IRQ_HANDLED;
  352. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  353. complete_all(&display->esd_te_gate);
  354. return IRQ_HANDLED;
  355. }
  356. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  357. bool enable)
  358. {
  359. if (!display) {
  360. DSI_ERR("Invalid params\n");
  361. return;
  362. }
  363. /* Handle unbalanced irq enable/disable calls */
  364. if (enable && !display->is_te_irq_enabled) {
  365. enable_irq(gpio_to_irq(display->disp_te_gpio));
  366. display->is_te_irq_enabled = true;
  367. } else if (!enable && display->is_te_irq_enabled) {
  368. disable_irq(gpio_to_irq(display->disp_te_gpio));
  369. display->is_te_irq_enabled = false;
  370. }
  371. }
  372. static void dsi_display_register_te_irq(struct dsi_display *display)
  373. {
  374. int rc = 0;
  375. struct platform_device *pdev;
  376. struct device *dev;
  377. unsigned int te_irq;
  378. pdev = display->pdev;
  379. if (!pdev) {
  380. DSI_ERR("invalid platform device\n");
  381. return;
  382. }
  383. dev = &pdev->dev;
  384. if (!dev) {
  385. DSI_ERR("invalid device\n");
  386. return;
  387. }
  388. if (display->trusted_vm_env) {
  389. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  390. return;
  391. }
  392. if (!gpio_is_valid(display->disp_te_gpio)) {
  393. rc = -EINVAL;
  394. goto error;
  395. }
  396. init_completion(&display->esd_te_gate);
  397. te_irq = gpio_to_irq(display->disp_te_gpio);
  398. /* Avoid deferred spurious irqs with disable_irq() */
  399. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  400. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  401. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  402. "TE_GPIO", display);
  403. if (rc) {
  404. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  405. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  406. goto error;
  407. }
  408. disable_irq(te_irq);
  409. display->is_te_irq_enabled = false;
  410. return;
  411. error:
  412. /* disable the TE based ESD check */
  413. DSI_WARN("Unable to register for TE IRQ\n");
  414. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  415. display->panel->esd_config.esd_enabled = false;
  416. }
  417. /* Allocate memory for cmd dma tx buffer */
  418. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  419. {
  420. int rc = 0, cnt = 0;
  421. struct dsi_display_ctrl *display_ctrl;
  422. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  423. SZ_4K,
  424. MSM_BO_UNCACHED);
  425. if ((display->tx_cmd_buf) == NULL) {
  426. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  427. rc = -ENOMEM;
  428. goto error;
  429. }
  430. display->cmd_buffer_size = SZ_4K;
  431. display->aspace = msm_gem_smmu_address_space_get(
  432. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  433. if (PTR_ERR(display->aspace) == -ENODEV) {
  434. display->aspace = NULL;
  435. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  436. } else if (IS_ERR_OR_NULL(display->aspace)) {
  437. rc = PTR_ERR(display->aspace);
  438. display->aspace = NULL;
  439. DSI_ERR("failed to get aspace %d\n", rc);
  440. goto free_gem;
  441. } else if (display->aspace) {
  442. /* register to aspace */
  443. rc = msm_gem_address_space_register_cb(display->aspace,
  444. dsi_display_aspace_cb_locked, (void *)display);
  445. if (rc) {
  446. DSI_ERR("failed to register callback %d\n", rc);
  447. goto free_gem;
  448. }
  449. }
  450. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  451. &(display->cmd_buffer_iova));
  452. if (rc) {
  453. DSI_ERR("failed to get the iova rc %d\n", rc);
  454. goto free_aspace_cb;
  455. }
  456. display->vaddr =
  457. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  458. if (IS_ERR_OR_NULL(display->vaddr)) {
  459. DSI_ERR("failed to get va rc %d\n", rc);
  460. rc = -EINVAL;
  461. goto put_iova;
  462. }
  463. display_for_each_ctrl(cnt, display) {
  464. display_ctrl = &display->ctrl[cnt];
  465. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  466. display_ctrl->ctrl->cmd_buffer_iova =
  467. display->cmd_buffer_iova;
  468. display_ctrl->ctrl->vaddr = display->vaddr;
  469. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  470. }
  471. return rc;
  472. put_iova:
  473. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  474. free_aspace_cb:
  475. msm_gem_address_space_unregister_cb(display->aspace,
  476. dsi_display_aspace_cb_locked, display);
  477. free_gem:
  478. mutex_lock(&display->drm_dev->struct_mutex);
  479. msm_gem_free_object(display->tx_cmd_buf);
  480. mutex_unlock(&display->drm_dev->struct_mutex);
  481. error:
  482. return rc;
  483. }
  484. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  485. {
  486. int i, j = 0;
  487. int len = 0, *lenp;
  488. int group = 0, count = 0;
  489. struct drm_panel_esd_config *config;
  490. if (!panel)
  491. return false;
  492. config = &(panel->esd_config);
  493. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  494. count = config->status_cmd.count;
  495. for (i = 0; i < count; i++)
  496. len += lenp[i];
  497. for (i = 0; i < len; i++)
  498. j += len;
  499. for (j = 0; j < config->groups; ++j) {
  500. for (i = 0; i < len; ++i) {
  501. if (config->return_buf[i] !=
  502. config->status_value[group + i]) {
  503. DRM_ERROR("mismatch: 0x%x\n",
  504. config->return_buf[i]);
  505. break;
  506. }
  507. }
  508. if (i == len)
  509. return true;
  510. group += len;
  511. }
  512. return false;
  513. }
  514. static void dsi_display_parse_te_data(struct dsi_display *display)
  515. {
  516. struct platform_device *pdev;
  517. struct device *dev;
  518. int rc = 0;
  519. u32 val = 0;
  520. pdev = display->pdev;
  521. if (!pdev) {
  522. DSI_ERR("Invalid platform device\n");
  523. return;
  524. }
  525. dev = &pdev->dev;
  526. if (!dev) {
  527. DSI_ERR("Invalid platform device\n");
  528. return;
  529. }
  530. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  531. "qcom,platform-te-gpio", 0);
  532. if (display->fw)
  533. rc = dsi_parser_read_u32(display->parser_node,
  534. "qcom,panel-te-source", &val);
  535. else
  536. rc = of_property_read_u32(dev->of_node,
  537. "qcom,panel-te-source", &val);
  538. if (rc || (val > MAX_TE_SOURCE_ID)) {
  539. DSI_ERR("invalid vsync source selection\n");
  540. val = 0;
  541. }
  542. display->te_source = val;
  543. }
  544. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  545. struct dsi_panel *panel)
  546. {
  547. int i, rc = 0, count = 0, start = 0, *lenp;
  548. struct drm_panel_esd_config *config;
  549. struct dsi_cmd_desc *cmds;
  550. u32 flags = 0;
  551. if (!panel || !ctrl || !ctrl->ctrl)
  552. return -EINVAL;
  553. /*
  554. * When DSI controller is not in initialized state, we do not want to
  555. * report a false ESD failure and hence we defer until next read
  556. * happen.
  557. */
  558. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  559. return 1;
  560. config = &(panel->esd_config);
  561. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  562. count = config->status_cmd.count;
  563. cmds = config->status_cmd.cmds;
  564. flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ);
  565. if (ctrl->ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE)
  566. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  567. for (i = 0; i < count; ++i) {
  568. memset(config->status_buf, 0x0, SZ_4K);
  569. if (cmds[i].last_command) {
  570. cmds[i].msg.flags |= MIPI_DSI_MSG_LASTCOMMAND;
  571. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  572. }
  573. if ((cmds[i].msg.flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  574. (panel->panel_initialized))
  575. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  576. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  577. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  578. cmds[i].msg.rx_buf = config->status_buf;
  579. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  580. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i].msg, &flags);
  581. if (rc <= 0) {
  582. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  583. return rc;
  584. }
  585. memcpy(config->return_buf + start,
  586. config->status_buf, lenp[i]);
  587. start += lenp[i];
  588. }
  589. return rc;
  590. }
  591. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  592. struct dsi_panel *panel)
  593. {
  594. int rc = 0;
  595. rc = dsi_display_read_status(ctrl, panel);
  596. if (rc <= 0) {
  597. goto exit;
  598. } else {
  599. /*
  600. * panel status read successfully.
  601. * check for validity of the data read back.
  602. */
  603. rc = dsi_display_validate_reg_read(panel);
  604. if (!rc) {
  605. rc = -EINVAL;
  606. goto exit;
  607. }
  608. }
  609. exit:
  610. return rc;
  611. }
  612. static int dsi_display_status_reg_read(struct dsi_display *display)
  613. {
  614. int rc = 0, i;
  615. struct dsi_display_ctrl *m_ctrl, *ctrl;
  616. DSI_DEBUG(" ++\n");
  617. m_ctrl = &display->ctrl[display->cmd_master_idx];
  618. if (display->tx_cmd_buf == NULL) {
  619. rc = dsi_host_alloc_cmd_tx_buffer(display);
  620. if (rc) {
  621. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  622. goto done;
  623. }
  624. }
  625. rc = dsi_display_cmd_engine_enable(display);
  626. if (rc) {
  627. DSI_ERR("cmd engine enable failed\n");
  628. return -EPERM;
  629. }
  630. rc = dsi_display_validate_status(m_ctrl, display->panel);
  631. if (rc <= 0) {
  632. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  633. display->name, rc);
  634. goto exit;
  635. }
  636. if (!display->panel->sync_broadcast_en)
  637. goto exit;
  638. display_for_each_ctrl(i, display) {
  639. ctrl = &display->ctrl[i];
  640. if (ctrl == m_ctrl)
  641. continue;
  642. rc = dsi_display_validate_status(ctrl, display->panel);
  643. if (rc <= 0) {
  644. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  645. display->name, rc);
  646. goto exit;
  647. }
  648. }
  649. exit:
  650. dsi_display_cmd_engine_disable(display);
  651. done:
  652. return rc;
  653. }
  654. static int dsi_display_status_bta_request(struct dsi_display *display)
  655. {
  656. int rc = 0;
  657. DSI_DEBUG(" ++\n");
  658. /* TODO: trigger SW BTA and wait for acknowledgment */
  659. return rc;
  660. }
  661. static int dsi_display_status_check_te(struct dsi_display *display,
  662. int rechecks)
  663. {
  664. int rc = 1, i = 0;
  665. int const esd_te_timeout = msecs_to_jiffies(3*20);
  666. if (!rechecks)
  667. return rc;
  668. dsi_display_change_te_irq_status(display, true);
  669. for (i = 0; i < rechecks; i++) {
  670. reinit_completion(&display->esd_te_gate);
  671. if (!wait_for_completion_timeout(&display->esd_te_gate,
  672. esd_te_timeout)) {
  673. DSI_ERR("TE check failed\n");
  674. dsi_display_change_te_irq_status(display, false);
  675. return -EINVAL;
  676. }
  677. }
  678. dsi_display_change_te_irq_status(display, false);
  679. return rc;
  680. }
  681. int dsi_display_check_status(struct drm_connector *connector, void *display,
  682. bool te_check_override)
  683. {
  684. struct dsi_display *dsi_display = display;
  685. struct dsi_panel *panel;
  686. u32 status_mode;
  687. int rc = 0x1, ret;
  688. u32 mask;
  689. int te_rechecks = 1;
  690. if (!dsi_display || !dsi_display->panel)
  691. return -EINVAL;
  692. panel = dsi_display->panel;
  693. dsi_panel_acquire_panel_lock(panel);
  694. if (!panel->panel_initialized) {
  695. DSI_DEBUG("Panel not initialized\n");
  696. goto release_panel_lock;
  697. }
  698. /* Prevent another ESD check,when ESD recovery is underway */
  699. if (atomic_read(&panel->esd_recovery_pending))
  700. goto release_panel_lock;
  701. status_mode = panel->esd_config.status_mode;
  702. if ((status_mode == ESD_MODE_SW_SIM_SUCCESS) ||
  703. (dsi_display->sw_te_using_wd))
  704. goto release_panel_lock;
  705. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  706. rc = -EINVAL;
  707. goto release_panel_lock;
  708. }
  709. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
  710. if (te_check_override)
  711. te_rechecks = MAX_TE_RECHECKS;
  712. if ((dsi_display->trusted_vm_env) ||
  713. (panel->panel_mode == DSI_OP_VIDEO_MODE))
  714. te_rechecks = 0;
  715. ret = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  716. DSI_ALL_CLKS, DSI_CLK_ON);
  717. if (ret)
  718. goto release_panel_lock;
  719. /* Mask error interrupts before attempting ESD read */
  720. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  721. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  722. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
  723. if (status_mode == ESD_MODE_REG_READ) {
  724. rc = dsi_display_status_reg_read(dsi_display);
  725. } else if (status_mode == ESD_MODE_SW_BTA) {
  726. rc = dsi_display_status_bta_request(dsi_display);
  727. } else if (status_mode == ESD_MODE_PANEL_TE) {
  728. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  729. te_check_override = false;
  730. } else {
  731. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  732. panel->esd_config.esd_enabled = false;
  733. }
  734. if (rc <= 0 && te_check_override)
  735. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  736. /* Unmask error interrupts if check passed*/
  737. if (rc > 0) {
  738. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  739. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
  740. false);
  741. if (te_check_override && panel->esd_config.esd_enabled == false)
  742. rc = dsi_display_status_check_te(dsi_display,
  743. te_rechecks);
  744. }
  745. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  746. DSI_ALL_CLKS, DSI_CLK_OFF);
  747. /* Handle Panel failures during display disable sequence */
  748. if (rc <=0)
  749. atomic_set(&panel->esd_recovery_pending, 1);
  750. release_panel_lock:
  751. dsi_panel_release_panel_lock(panel);
  752. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
  753. return rc;
  754. }
  755. static int dsi_display_cmd_prepare(const char *cmd_buf, u32 cmd_buf_len,
  756. struct dsi_cmd_desc *cmd, u8 *payload, u32 payload_len)
  757. {
  758. int i;
  759. memset(cmd, 0x00, sizeof(*cmd));
  760. cmd->msg.type = cmd_buf[0];
  761. cmd->last_command = (cmd_buf[1] == 1);
  762. cmd->msg.channel = cmd_buf[2];
  763. cmd->msg.flags = cmd_buf[3];
  764. cmd->msg.ctrl = 0;
  765. cmd->post_wait_ms = cmd->msg.wait_ms = cmd_buf[4];
  766. cmd->msg.tx_len = ((cmd_buf[5] << 8) | (cmd_buf[6]));
  767. if (cmd->msg.tx_len > payload_len) {
  768. DSI_ERR("Incorrect payload length tx_len %zu, payload_len %d\n",
  769. cmd->msg.tx_len, payload_len);
  770. return -EINVAL;
  771. }
  772. if (cmd->last_command)
  773. cmd->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND;
  774. for (i = 0; i < cmd->msg.tx_len; i++)
  775. payload[i] = cmd_buf[7 + i];
  776. cmd->msg.tx_buf = payload;
  777. return 0;
  778. }
  779. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  780. bool *state)
  781. {
  782. struct dsi_display_ctrl *ctrl;
  783. int i, rc = -EINVAL;
  784. display_for_each_ctrl(i, dsi_display) {
  785. ctrl = &dsi_display->ctrl[i];
  786. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  787. if (rc)
  788. break;
  789. }
  790. return rc;
  791. }
  792. static int dsi_display_cmd_rx(struct dsi_display *display,
  793. struct dsi_cmd_desc *cmd)
  794. {
  795. struct dsi_display_ctrl *m_ctrl = NULL;
  796. u32 mask = 0, flags = 0;
  797. int rc = 0;
  798. if (!display || !display->panel)
  799. return -EINVAL;
  800. m_ctrl = &display->ctrl[display->cmd_master_idx];
  801. if (!m_ctrl || !m_ctrl->ctrl)
  802. return -EINVAL;
  803. /* acquire panel_lock to make sure no commands are in progress */
  804. dsi_panel_acquire_panel_lock(display->panel);
  805. if (!display->panel->panel_initialized) {
  806. DSI_DEBUG("panel not initialized\n");
  807. goto release_panel_lock;
  808. }
  809. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  810. DSI_ALL_CLKS, DSI_CLK_ON);
  811. if (rc)
  812. goto release_panel_lock;
  813. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  814. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  815. rc = dsi_display_cmd_engine_enable(display);
  816. if (rc) {
  817. DSI_ERR("cmd engine enable failed rc = %d\n", rc);
  818. goto error;
  819. }
  820. flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ);
  821. if ((m_ctrl->ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) ||
  822. ((cmd->msg.flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  823. (display->enabled)))
  824. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  825. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmd->msg, &flags);
  826. if (rc <= 0)
  827. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  828. dsi_display_cmd_engine_disable(display);
  829. error:
  830. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  831. dsi_display_clk_ctrl(display->dsi_clk_handle,
  832. DSI_ALL_CLKS, DSI_CLK_OFF);
  833. release_panel_lock:
  834. dsi_panel_release_panel_lock(display->panel);
  835. return rc;
  836. }
  837. int dsi_display_cmd_transfer(struct drm_connector *connector,
  838. void *display, const char *cmd_buf,
  839. u32 cmd_buf_len)
  840. {
  841. struct dsi_display *dsi_display = display;
  842. int rc = 0, cnt = 0, i = 0;
  843. bool state = false, transfer = false;
  844. struct dsi_panel_cmd_set *set;
  845. if (!dsi_display || !cmd_buf) {
  846. DSI_ERR("[DSI] invalid params\n");
  847. return -EINVAL;
  848. }
  849. DSI_DEBUG("[DSI] Display command transfer\n");
  850. if ((cmd_buf[1]) || (cmd_buf[3] & MIPI_DSI_MSG_LASTCOMMAND))
  851. transfer = true;
  852. mutex_lock(&dsi_display->display_lock);
  853. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  854. /**
  855. * Handle scenario where a command transfer is initiated through
  856. * sysfs interface when device is in suepnd state.
  857. */
  858. if (!rc && !state) {
  859. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  860. );
  861. rc = -EPERM;
  862. goto end;
  863. }
  864. if (rc || !state) {
  865. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  866. state, rc);
  867. rc = -EPERM;
  868. goto end;
  869. }
  870. /*
  871. * Reset the dbgfs buffer if the commands sent exceed the available
  872. * buffer size. For video mode, limiting the buffer size to 2K to
  873. * ensure no performance issues.
  874. */
  875. if (dsi_display->panel->panel_mode == DSI_OP_CMD_MODE) {
  876. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_4K) {
  877. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  878. dsi_display->tx_cmd_buf_ndx = 0;
  879. }
  880. } else {
  881. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_2K) {
  882. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  883. dsi_display->tx_cmd_buf_ndx = 0;
  884. }
  885. }
  886. memcpy(&dbgfs_tx_cmd_buf[dsi_display->tx_cmd_buf_ndx], cmd_buf,
  887. cmd_buf_len);
  888. dsi_display->tx_cmd_buf_ndx += cmd_buf_len;
  889. if (transfer) {
  890. struct dsi_cmd_desc *cmds;
  891. set = &dsi_display->cmd_set;
  892. set->count = 0;
  893. dsi_panel_get_cmd_pkt_count(dbgfs_tx_cmd_buf,
  894. dsi_display->tx_cmd_buf_ndx, &cnt);
  895. dsi_panel_alloc_cmd_packets(set, cnt);
  896. dsi_panel_create_cmd_packets(dbgfs_tx_cmd_buf,
  897. dsi_display->tx_cmd_buf_ndx, cnt, set->cmds);
  898. cmds = set->cmds;
  899. dsi_display->tx_cmd_buf_ndx = 0;
  900. for (i = 0; i < cnt; i++) {
  901. if (cmds->last_command)
  902. cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND;
  903. rc = dsi_display->host.ops->transfer(&dsi_display->host,
  904. &cmds->msg);
  905. if (rc < 0) {
  906. DSI_ERR("failed to send command, rc=%d\n", rc);
  907. break;
  908. }
  909. if (cmds->post_wait_ms)
  910. usleep_range(cmds->post_wait_ms*1000,
  911. ((cmds->post_wait_ms*1000)+10));
  912. cmds++;
  913. }
  914. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  915. dsi_panel_destroy_cmd_packets(set);
  916. dsi_panel_dealloc_cmd_packets(set);
  917. }
  918. end:
  919. mutex_unlock(&dsi_display->display_lock);
  920. return rc;
  921. }
  922. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  923. bool enable)
  924. {
  925. int i;
  926. struct dsi_display_ctrl *ctrl;
  927. if (!display || !display->panel->host_config.force_hs_clk_lane)
  928. return;
  929. display_for_each_ctrl(i, display) {
  930. ctrl = &display->ctrl[i];
  931. /*
  932. * For phy ver 4.0 chipsets, configure DSI controller and
  933. * DSI PHY to force clk lane to HS mode always whereas
  934. * for other phy ver chipsets, configure DSI controller only.
  935. */
  936. if (ctrl->phy->hw.ops.set_continuous_clk) {
  937. dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
  938. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  939. dsi_phy_set_continuous_clk(ctrl->phy, enable);
  940. } else {
  941. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  942. }
  943. }
  944. }
  945. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  946. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len)
  947. {
  948. struct dsi_display *dsi_display = display;
  949. struct dsi_cmd_desc cmd = {};
  950. u8 cmd_payload[MAX_CMD_PAYLOAD_SIZE] = {0};
  951. bool state = false;
  952. int rc = -1;
  953. if (!dsi_display || !cmd_buf || !recv_buf) {
  954. DSI_ERR("[DSI] invalid params\n");
  955. return -EINVAL;
  956. }
  957. rc = dsi_display_cmd_prepare(cmd_buf, cmd_buf_len,
  958. &cmd, cmd_payload, MAX_CMD_PAYLOAD_SIZE);
  959. if (rc) {
  960. DSI_ERR("[DSI] command prepare failed, rc = %d\n", rc);
  961. return rc;
  962. }
  963. cmd.msg.rx_buf = recv_buf;
  964. cmd.msg.rx_len = recv_buf_len;
  965. mutex_lock(&dsi_display->display_lock);
  966. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  967. if (rc || !state) {
  968. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  969. state, rc);
  970. rc = -EPERM;
  971. goto end;
  972. }
  973. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  974. if (rc <= 0)
  975. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  976. end:
  977. mutex_unlock(&dsi_display->display_lock);
  978. return rc;
  979. }
  980. int dsi_display_soft_reset(void *display)
  981. {
  982. struct dsi_display *dsi_display;
  983. struct dsi_display_ctrl *ctrl;
  984. int rc = 0;
  985. int i;
  986. if (!display)
  987. return -EINVAL;
  988. dsi_display = display;
  989. display_for_each_ctrl(i, dsi_display) {
  990. ctrl = &dsi_display->ctrl[i];
  991. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  992. if (rc) {
  993. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  994. dsi_display->name, i, rc);
  995. break;
  996. }
  997. }
  998. return rc;
  999. }
  1000. enum dsi_pixel_format dsi_display_get_dst_format(
  1001. struct drm_connector *connector,
  1002. void *display)
  1003. {
  1004. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  1005. struct dsi_display *dsi_display = (struct dsi_display *)display;
  1006. if (!dsi_display || !dsi_display->panel) {
  1007. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  1008. dsi_display,
  1009. ((dsi_display) ? dsi_display->panel : NULL));
  1010. return format;
  1011. }
  1012. format = dsi_display->panel->host_config.dst_format;
  1013. return format;
  1014. }
  1015. static void _dsi_display_setup_misr(struct dsi_display *display)
  1016. {
  1017. int i;
  1018. display_for_each_ctrl(i, display) {
  1019. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  1020. display->misr_enable,
  1021. display->misr_frame_count);
  1022. }
  1023. }
  1024. int dsi_display_set_power(struct drm_connector *connector,
  1025. int power_mode, void *disp)
  1026. {
  1027. struct dsi_display *display = disp;
  1028. int rc = 0;
  1029. if (!display || !display->panel) {
  1030. DSI_ERR("invalid display/panel\n");
  1031. return -EINVAL;
  1032. }
  1033. switch (power_mode) {
  1034. case SDE_MODE_DPMS_LP1:
  1035. rc = dsi_panel_set_lp1(display->panel);
  1036. break;
  1037. case SDE_MODE_DPMS_LP2:
  1038. rc = dsi_panel_set_lp2(display->panel);
  1039. break;
  1040. case SDE_MODE_DPMS_ON:
  1041. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  1042. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  1043. rc = dsi_panel_set_nolp(display->panel);
  1044. break;
  1045. case SDE_MODE_DPMS_OFF:
  1046. default:
  1047. return rc;
  1048. }
  1049. SDE_EVT32(display->panel->power_mode, power_mode, rc);
  1050. DSI_DEBUG("Power mode transition from %d to %d %s",
  1051. display->panel->power_mode, power_mode,
  1052. rc ? "failed" : "successful");
  1053. if (!rc)
  1054. display->panel->power_mode = power_mode;
  1055. return rc;
  1056. }
  1057. #ifdef CONFIG_DEBUG_FS
  1058. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  1059. {
  1060. u32 status_mode = 0;
  1061. if (!display->panel) {
  1062. DSI_ERR("Invalid panel data\n");
  1063. return false;
  1064. }
  1065. status_mode = display->panel->esd_config.status_mode;
  1066. if (status_mode == ESD_MODE_PANEL_TE &&
  1067. gpio_is_valid(display->disp_te_gpio))
  1068. return true;
  1069. return false;
  1070. }
  1071. static ssize_t debugfs_dump_info_read(struct file *file,
  1072. char __user *user_buf,
  1073. size_t user_len,
  1074. loff_t *ppos)
  1075. {
  1076. struct dsi_display *display = file->private_data;
  1077. char *buf;
  1078. u32 len = 0;
  1079. int i;
  1080. if (!display)
  1081. return -ENODEV;
  1082. if (*ppos)
  1083. return 0;
  1084. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1085. if (!buf)
  1086. return -ENOMEM;
  1087. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1088. len += snprintf(buf + len, (SZ_4K - len),
  1089. "\tResolution = %dx%d\n",
  1090. display->config.video_timing.h_active,
  1091. display->config.video_timing.v_active);
  1092. display_for_each_ctrl(i, display) {
  1093. len += snprintf(buf + len, (SZ_4K - len),
  1094. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1095. i, display->ctrl[i].ctrl->name,
  1096. display->ctrl[i].phy->name);
  1097. }
  1098. len += snprintf(buf + len, (SZ_4K - len),
  1099. "\tPanel = %s\n", display->panel->name);
  1100. len += snprintf(buf + len, (SZ_4K - len),
  1101. "\tClock master = %s\n",
  1102. display->ctrl[display->clk_master_idx].ctrl->name);
  1103. if (len > user_len)
  1104. len = user_len;
  1105. if (copy_to_user(user_buf, buf, len)) {
  1106. kfree(buf);
  1107. return -EFAULT;
  1108. }
  1109. *ppos += len;
  1110. kfree(buf);
  1111. return len;
  1112. }
  1113. static ssize_t debugfs_misr_setup(struct file *file,
  1114. const char __user *user_buf,
  1115. size_t user_len,
  1116. loff_t *ppos)
  1117. {
  1118. struct dsi_display *display = file->private_data;
  1119. char *buf;
  1120. int rc = 0;
  1121. size_t len;
  1122. u32 enable, frame_count;
  1123. if (!display)
  1124. return -ENODEV;
  1125. if (*ppos)
  1126. return 0;
  1127. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1128. if (!buf)
  1129. return -ENOMEM;
  1130. /* leave room for termination char */
  1131. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1132. if (copy_from_user(buf, user_buf, len)) {
  1133. rc = -EINVAL;
  1134. goto error;
  1135. }
  1136. buf[len] = '\0'; /* terminate the string */
  1137. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1138. rc = -EINVAL;
  1139. goto error;
  1140. }
  1141. display->misr_enable = enable;
  1142. display->misr_frame_count = frame_count;
  1143. mutex_lock(&display->display_lock);
  1144. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1145. DSI_CORE_CLK, DSI_CLK_ON);
  1146. if (rc) {
  1147. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1148. display->name, rc);
  1149. goto unlock;
  1150. }
  1151. _dsi_display_setup_misr(display);
  1152. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1153. DSI_CORE_CLK, DSI_CLK_OFF);
  1154. if (rc) {
  1155. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1156. display->name, rc);
  1157. goto unlock;
  1158. }
  1159. rc = user_len;
  1160. unlock:
  1161. mutex_unlock(&display->display_lock);
  1162. error:
  1163. kfree(buf);
  1164. return rc;
  1165. }
  1166. static ssize_t debugfs_misr_read(struct file *file,
  1167. char __user *user_buf,
  1168. size_t user_len,
  1169. loff_t *ppos)
  1170. {
  1171. struct dsi_display *display = file->private_data;
  1172. char *buf;
  1173. u32 len = 0;
  1174. int rc = 0;
  1175. struct dsi_ctrl *dsi_ctrl;
  1176. int i;
  1177. u32 misr;
  1178. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1179. if (!display)
  1180. return -ENODEV;
  1181. if (*ppos)
  1182. return 0;
  1183. buf = kzalloc(max_len, GFP_KERNEL);
  1184. if (ZERO_OR_NULL_PTR(buf))
  1185. return -ENOMEM;
  1186. mutex_lock(&display->display_lock);
  1187. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1188. DSI_CORE_CLK, DSI_CLK_ON);
  1189. if (rc) {
  1190. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1191. display->name, rc);
  1192. goto error;
  1193. }
  1194. display_for_each_ctrl(i, display) {
  1195. dsi_ctrl = display->ctrl[i].ctrl;
  1196. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1197. len += snprintf((buf + len), max_len - len,
  1198. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1199. if (len >= max_len)
  1200. break;
  1201. }
  1202. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1203. DSI_CORE_CLK, DSI_CLK_OFF);
  1204. if (rc) {
  1205. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1206. display->name, rc);
  1207. goto error;
  1208. }
  1209. if (copy_to_user(user_buf, buf, max_len)) {
  1210. rc = -EFAULT;
  1211. goto error;
  1212. }
  1213. *ppos += len;
  1214. error:
  1215. mutex_unlock(&display->display_lock);
  1216. kfree(buf);
  1217. return len;
  1218. }
  1219. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1220. const char __user *user_buf,
  1221. size_t user_len,
  1222. loff_t *ppos)
  1223. {
  1224. struct dsi_display *display = file->private_data;
  1225. char *buf;
  1226. int rc = 0;
  1227. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1228. u32 esd_trigger;
  1229. size_t len;
  1230. if (!display)
  1231. return -ENODEV;
  1232. if (*ppos)
  1233. return 0;
  1234. if (user_len > sizeof(u32))
  1235. return -EINVAL;
  1236. if (!user_len || !user_buf)
  1237. return -EINVAL;
  1238. if (!display->panel ||
  1239. atomic_read(&display->panel->esd_recovery_pending))
  1240. return user_len;
  1241. if (!esd_config->esd_enabled) {
  1242. DSI_ERR("ESD feature is not enabled\n");
  1243. return -EINVAL;
  1244. }
  1245. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1246. if (!buf)
  1247. return -ENOMEM;
  1248. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1249. if (copy_from_user(buf, user_buf, len)) {
  1250. rc = -EINVAL;
  1251. goto error;
  1252. }
  1253. buf[len] = '\0'; /* terminate the string */
  1254. if (kstrtouint(buf, 10, &esd_trigger)) {
  1255. rc = -EINVAL;
  1256. goto error;
  1257. }
  1258. if (esd_trigger != 1) {
  1259. rc = -EINVAL;
  1260. goto error;
  1261. }
  1262. display->esd_trigger = esd_trigger;
  1263. if (display->esd_trigger) {
  1264. DSI_INFO("ESD attack triggered by user\n");
  1265. rc = dsi_panel_trigger_esd_attack(display->panel,
  1266. display->trusted_vm_env);
  1267. if (rc) {
  1268. DSI_ERR("Failed to trigger ESD attack\n");
  1269. goto error;
  1270. }
  1271. }
  1272. rc = len;
  1273. error:
  1274. kfree(buf);
  1275. return rc;
  1276. }
  1277. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1278. const char __user *user_buf,
  1279. size_t user_len,
  1280. loff_t *ppos)
  1281. {
  1282. struct dsi_display *display = file->private_data;
  1283. struct drm_panel_esd_config *esd_config;
  1284. char *buf;
  1285. int rc = 0;
  1286. size_t len;
  1287. if (!display)
  1288. return -ENODEV;
  1289. if (*ppos)
  1290. return 0;
  1291. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1292. if (ZERO_OR_NULL_PTR(buf))
  1293. return -ENOMEM;
  1294. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1295. if (copy_from_user(buf, user_buf, len)) {
  1296. rc = -EINVAL;
  1297. goto error;
  1298. }
  1299. buf[len] = '\0'; /* terminate the string */
  1300. if (!display->panel) {
  1301. rc = -EINVAL;
  1302. goto error;
  1303. }
  1304. esd_config = &display->panel->esd_config;
  1305. if (!esd_config) {
  1306. DSI_ERR("Invalid panel esd config\n");
  1307. rc = -EINVAL;
  1308. goto error;
  1309. }
  1310. if (!esd_config->esd_enabled) {
  1311. rc = -EINVAL;
  1312. goto error;
  1313. }
  1314. if (!strcmp(buf, "te_signal_check\n")) {
  1315. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1316. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1317. rc = -EINVAL;
  1318. goto error;
  1319. }
  1320. DSI_INFO("ESD check is switched to TE mode by user\n");
  1321. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1322. dsi_display_change_te_irq_status(display, true);
  1323. }
  1324. if (!strcmp(buf, "reg_read\n")) {
  1325. DSI_INFO("ESD check is switched to reg read by user\n");
  1326. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1327. if (rc) {
  1328. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1329. rc);
  1330. rc = user_len;
  1331. goto error;
  1332. }
  1333. esd_config->status_mode = ESD_MODE_REG_READ;
  1334. if (dsi_display_is_te_based_esd(display))
  1335. dsi_display_change_te_irq_status(display, false);
  1336. }
  1337. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1338. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1339. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1340. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1341. rc = len;
  1342. error:
  1343. kfree(buf);
  1344. return rc;
  1345. }
  1346. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1347. char __user *user_buf,
  1348. size_t user_len,
  1349. loff_t *ppos)
  1350. {
  1351. struct dsi_display *display = file->private_data;
  1352. struct drm_panel_esd_config *esd_config;
  1353. char *buf;
  1354. int rc = 0;
  1355. size_t len = 0;
  1356. if (!display)
  1357. return -ENODEV;
  1358. if (*ppos)
  1359. return 0;
  1360. if (!display->panel) {
  1361. DSI_ERR("invalid panel data\n");
  1362. return -EINVAL;
  1363. }
  1364. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1365. if (ZERO_OR_NULL_PTR(buf))
  1366. return -ENOMEM;
  1367. esd_config = &display->panel->esd_config;
  1368. if (!esd_config) {
  1369. DSI_ERR("Invalid panel esd config\n");
  1370. rc = -EINVAL;
  1371. goto error;
  1372. }
  1373. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1374. if (!esd_config->esd_enabled) {
  1375. rc = snprintf(buf, len, "ESD feature not enabled");
  1376. goto output_mode;
  1377. }
  1378. switch (esd_config->status_mode) {
  1379. case ESD_MODE_REG_READ:
  1380. rc = snprintf(buf, len, "reg_read");
  1381. break;
  1382. case ESD_MODE_PANEL_TE:
  1383. rc = snprintf(buf, len, "te_signal_check");
  1384. break;
  1385. case ESD_MODE_SW_SIM_FAILURE:
  1386. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1387. break;
  1388. case ESD_MODE_SW_SIM_SUCCESS:
  1389. rc = snprintf(buf, len, "esd_sw_sim_success");
  1390. break;
  1391. default:
  1392. rc = snprintf(buf, len, "invalid");
  1393. break;
  1394. }
  1395. output_mode:
  1396. if (!rc) {
  1397. rc = -EINVAL;
  1398. goto error;
  1399. }
  1400. if (copy_to_user(user_buf, buf, len)) {
  1401. rc = -EFAULT;
  1402. goto error;
  1403. }
  1404. *ppos += len;
  1405. error:
  1406. kfree(buf);
  1407. return len;
  1408. }
  1409. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1410. const char __user *user_buf,
  1411. size_t user_len,
  1412. loff_t *ppos)
  1413. {
  1414. struct dsi_display *display = file->private_data;
  1415. struct dsi_display_ctrl *display_ctrl;
  1416. char *buf;
  1417. int rc = 0;
  1418. u32 line = 0, window = 0;
  1419. size_t len;
  1420. int i;
  1421. if (!display)
  1422. return -ENODEV;
  1423. if (*ppos)
  1424. return 0;
  1425. buf = kzalloc(256, GFP_KERNEL);
  1426. if (ZERO_OR_NULL_PTR(buf))
  1427. return -ENOMEM;
  1428. len = min_t(size_t, user_len, 255);
  1429. if (copy_from_user(buf, user_buf, len)) {
  1430. rc = -EINVAL;
  1431. goto error;
  1432. }
  1433. buf[len] = '\0'; /* terminate the string */
  1434. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1435. return -EFAULT;
  1436. display_for_each_ctrl(i, display) {
  1437. struct dsi_ctrl *ctrl;
  1438. display_ctrl = &display->ctrl[i];
  1439. if (!display_ctrl->ctrl)
  1440. continue;
  1441. ctrl = display_ctrl->ctrl;
  1442. ctrl->host_config.common_config.dma_sched_line = line;
  1443. ctrl->host_config.common_config.dma_sched_window = window;
  1444. }
  1445. rc = len;
  1446. error:
  1447. kfree(buf);
  1448. return rc;
  1449. }
  1450. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1451. char __user *user_buf,
  1452. size_t user_len,
  1453. loff_t *ppos)
  1454. {
  1455. struct dsi_display *display = file->private_data;
  1456. struct dsi_display_ctrl *m_ctrl;
  1457. struct dsi_ctrl *ctrl;
  1458. char *buf;
  1459. u32 len = 0;
  1460. int rc = 0;
  1461. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1462. if (!display)
  1463. return -ENODEV;
  1464. if (*ppos)
  1465. return 0;
  1466. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1467. ctrl = m_ctrl->ctrl;
  1468. buf = kzalloc(max_len, GFP_KERNEL);
  1469. if (ZERO_OR_NULL_PTR(buf))
  1470. return -ENOMEM;
  1471. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1472. ctrl->host_config.common_config.dma_sched_line);
  1473. len += scnprintf((buf + len), max_len - len,
  1474. "Schedule command window width: %d\n",
  1475. ctrl->host_config.common_config.dma_sched_window);
  1476. if (len > max_len)
  1477. len = max_len;
  1478. if (copy_to_user(user_buf, buf, len)) {
  1479. rc = -EFAULT;
  1480. goto error;
  1481. }
  1482. *ppos += len;
  1483. error:
  1484. kfree(buf);
  1485. return len;
  1486. }
  1487. static const struct file_operations dump_info_fops = {
  1488. .open = simple_open,
  1489. .read = debugfs_dump_info_read,
  1490. };
  1491. static const struct file_operations misr_data_fops = {
  1492. .open = simple_open,
  1493. .read = debugfs_misr_read,
  1494. .write = debugfs_misr_setup,
  1495. };
  1496. static const struct file_operations esd_trigger_fops = {
  1497. .open = simple_open,
  1498. .write = debugfs_esd_trigger_check,
  1499. };
  1500. static const struct file_operations esd_check_mode_fops = {
  1501. .open = simple_open,
  1502. .write = debugfs_alter_esd_check_mode,
  1503. .read = debugfs_read_esd_check_mode,
  1504. };
  1505. static const struct file_operations dsi_command_scheduling_fops = {
  1506. .open = simple_open,
  1507. .write = debugfs_update_cmd_scheduling_params,
  1508. .read = debugfs_read_cmd_scheduling_params,
  1509. };
  1510. static int dsi_display_debugfs_init(struct dsi_display *display)
  1511. {
  1512. int rc = 0;
  1513. struct dentry *dir, *dump_file, *misr_data;
  1514. char name[MAX_NAME_SIZE];
  1515. char panel_name[SEC_PANEL_NAME_MAX_LEN];
  1516. char secondary_panel_str[] = "_secondary";
  1517. int i;
  1518. strlcpy(panel_name, display->name, SEC_PANEL_NAME_MAX_LEN);
  1519. if (strcmp(display->display_type, "secondary") == 0)
  1520. strlcat(panel_name, secondary_panel_str, SEC_PANEL_NAME_MAX_LEN);
  1521. dir = debugfs_create_dir(panel_name, NULL);
  1522. if (IS_ERR_OR_NULL(dir)) {
  1523. rc = PTR_ERR(dir);
  1524. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1525. display->name, rc);
  1526. goto error;
  1527. }
  1528. dump_file = debugfs_create_file("dump_info",
  1529. 0400,
  1530. dir,
  1531. display,
  1532. &dump_info_fops);
  1533. if (IS_ERR_OR_NULL(dump_file)) {
  1534. rc = PTR_ERR(dump_file);
  1535. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1536. display->name, rc);
  1537. goto error_remove_dir;
  1538. }
  1539. dump_file = debugfs_create_file("esd_trigger",
  1540. 0644,
  1541. dir,
  1542. display,
  1543. &esd_trigger_fops);
  1544. if (IS_ERR_OR_NULL(dump_file)) {
  1545. rc = PTR_ERR(dump_file);
  1546. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1547. display->name, rc);
  1548. goto error_remove_dir;
  1549. }
  1550. dump_file = debugfs_create_file("esd_check_mode",
  1551. 0644,
  1552. dir,
  1553. display,
  1554. &esd_check_mode_fops);
  1555. if (IS_ERR_OR_NULL(dump_file)) {
  1556. rc = PTR_ERR(dump_file);
  1557. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1558. display->name, rc);
  1559. goto error_remove_dir;
  1560. }
  1561. dump_file = debugfs_create_file("cmd_sched_params",
  1562. 0644,
  1563. dir,
  1564. display,
  1565. &dsi_command_scheduling_fops);
  1566. if (IS_ERR_OR_NULL(dump_file)) {
  1567. rc = PTR_ERR(dump_file);
  1568. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1569. display->name, rc);
  1570. goto error_remove_dir;
  1571. }
  1572. misr_data = debugfs_create_file("misr_data",
  1573. 0600,
  1574. dir,
  1575. display,
  1576. &misr_data_fops);
  1577. if (IS_ERR_OR_NULL(misr_data)) {
  1578. rc = PTR_ERR(misr_data);
  1579. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1580. display->name, rc);
  1581. goto error_remove_dir;
  1582. }
  1583. display_for_each_ctrl(i, display) {
  1584. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1585. if (!phy || !phy->name)
  1586. continue;
  1587. snprintf(name, ARRAY_SIZE(name),
  1588. "%s_allow_phy_power_off", phy->name);
  1589. dump_file = debugfs_create_bool(name, 0600, dir,
  1590. &phy->allow_phy_power_off);
  1591. if (IS_ERR_OR_NULL(dump_file)) {
  1592. rc = PTR_ERR(dump_file);
  1593. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1594. display->name, name, rc);
  1595. goto error_remove_dir;
  1596. }
  1597. snprintf(name, ARRAY_SIZE(name),
  1598. "%s_regulator_min_datarate_bps", phy->name);
  1599. debugfs_create_u32(name, 0600, dir, &phy->regulator_min_datarate_bps);
  1600. }
  1601. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1602. &display->panel->ulps_feature_enabled)) {
  1603. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1604. display->name);
  1605. goto error_remove_dir;
  1606. }
  1607. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1608. &display->panel->ulps_suspend_enabled)) {
  1609. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1610. display->name);
  1611. goto error_remove_dir;
  1612. }
  1613. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1614. &display->ulps_enabled)) {
  1615. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1616. display->name);
  1617. goto error_remove_dir;
  1618. }
  1619. debugfs_create_u32("clk_gating_config", 0600, dir, &display->clk_gating_config);
  1620. display->root = dir;
  1621. dsi_parser_dbg_init(display->parser, dir);
  1622. return rc;
  1623. error_remove_dir:
  1624. debugfs_remove(dir);
  1625. error:
  1626. return rc;
  1627. }
  1628. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1629. {
  1630. debugfs_remove_recursive(display->root);
  1631. return 0;
  1632. }
  1633. #else
  1634. static int dsi_display_debugfs_init(struct dsi_display *display)
  1635. {
  1636. return 0;
  1637. }
  1638. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1639. {
  1640. return 0;
  1641. }
  1642. #endif /* CONFIG_DEBUG_FS */
  1643. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1644. struct dsi_display_mode *mode)
  1645. {
  1646. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1647. bool is_split_link = host->split_link.split_link_enabled;
  1648. u32 sublinks_count = host->split_link.num_sublinks;
  1649. if (is_split_link && sublinks_count > 1) {
  1650. mode->timing.h_active /= sublinks_count;
  1651. mode->timing.h_front_porch /= sublinks_count;
  1652. mode->timing.h_sync_width /= sublinks_count;
  1653. mode->timing.h_back_porch /= sublinks_count;
  1654. mode->timing.h_skew /= sublinks_count;
  1655. mode->pixel_clk_khz /= sublinks_count;
  1656. } else {
  1657. if (mode->priv_info->dsc_enabled)
  1658. mode->priv_info->dsc.config.pic_width =
  1659. mode->timing.h_active;
  1660. mode->timing.h_active /= display->ctrl_count;
  1661. mode->timing.h_front_porch /= display->ctrl_count;
  1662. mode->timing.h_sync_width /= display->ctrl_count;
  1663. mode->timing.h_back_porch /= display->ctrl_count;
  1664. mode->timing.h_skew /= display->ctrl_count;
  1665. mode->pixel_clk_khz /= display->ctrl_count;
  1666. }
  1667. }
  1668. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1669. bool enable)
  1670. {
  1671. /* TODO: make checks based on cont. splash */
  1672. DSI_DEBUG("checking ulps req validity\n");
  1673. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1674. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1675. return false;
  1676. }
  1677. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1678. !display->panel->ulps_suspend_enabled) {
  1679. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1680. return false;
  1681. }
  1682. if (!dsi_panel_initialized(display->panel) &&
  1683. !display->panel->ulps_suspend_enabled) {
  1684. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1685. return false;
  1686. }
  1687. if (enable && display->ulps_enabled) {
  1688. DSI_DEBUG("ULPS already enabled\n");
  1689. return false;
  1690. } else if (!enable && !display->ulps_enabled) {
  1691. DSI_DEBUG("ULPS already disabled\n");
  1692. return false;
  1693. }
  1694. /*
  1695. * No need to enter ULPS when transitioning from splash screen to
  1696. * boot animation or trusted vm environments since it is expected
  1697. * that the clocks would be turned right back on.
  1698. */
  1699. if (enable && is_skip_op_required(display))
  1700. return false;
  1701. return true;
  1702. }
  1703. /**
  1704. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1705. * @dsi_display: DSI display handle.
  1706. * @enable: enable/disable ULPS.
  1707. *
  1708. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1709. *
  1710. * Return: error code.
  1711. */
  1712. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1713. {
  1714. int rc = 0;
  1715. int i = 0;
  1716. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1717. if (!display) {
  1718. DSI_ERR("Invalid params\n");
  1719. return -EINVAL;
  1720. }
  1721. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1722. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1723. __func__, enable);
  1724. return 0;
  1725. }
  1726. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1727. /*
  1728. * ULPS entry-exit can be either through the DSI controller or
  1729. * the DSI PHY depending on hardware variation. For some chipsets,
  1730. * both controller version and phy version ulps entry-exit ops can
  1731. * be present. To handle such cases, send ulps request through PHY,
  1732. * if ulps request is handled in PHY, then no need to send request
  1733. * through controller.
  1734. */
  1735. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1736. display->clamp_enabled);
  1737. if (rc == DSI_PHY_ULPS_ERROR) {
  1738. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1739. return -EINVAL;
  1740. }
  1741. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1742. display_for_each_ctrl(i, display) {
  1743. ctrl = &display->ctrl[i];
  1744. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1745. continue;
  1746. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1747. enable, display->clamp_enabled);
  1748. if (rc == DSI_PHY_ULPS_ERROR) {
  1749. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1750. enable);
  1751. return -EINVAL;
  1752. }
  1753. }
  1754. }
  1755. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1756. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1757. if (rc) {
  1758. DSI_ERR("Ulps controller state change(%d) failed\n",
  1759. enable);
  1760. return rc;
  1761. }
  1762. display_for_each_ctrl(i, display) {
  1763. ctrl = &display->ctrl[i];
  1764. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1765. continue;
  1766. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1767. if (rc) {
  1768. DSI_ERR("Ulps controller state change(%d) failed\n",
  1769. enable);
  1770. return rc;
  1771. }
  1772. }
  1773. }
  1774. display->ulps_enabled = enable;
  1775. return 0;
  1776. }
  1777. /**
  1778. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1779. * @dsi_display: DSI display handle.
  1780. * @enable: enable/disable clamping.
  1781. *
  1782. * Return: error code.
  1783. */
  1784. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1785. {
  1786. int rc = 0;
  1787. int i = 0;
  1788. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1789. bool ulps_enabled = false;
  1790. if (!display) {
  1791. DSI_ERR("Invalid params\n");
  1792. return -EINVAL;
  1793. }
  1794. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1795. ulps_enabled = display->ulps_enabled;
  1796. /*
  1797. * Clamp control can be either through the DSI controller or
  1798. * the DSI PHY depending on hardware variation
  1799. */
  1800. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1801. if (rc) {
  1802. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1803. return rc;
  1804. }
  1805. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1806. if (rc) {
  1807. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1808. return rc;
  1809. }
  1810. display_for_each_ctrl(i, display) {
  1811. ctrl = &display->ctrl[i];
  1812. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1813. continue;
  1814. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1815. if (rc) {
  1816. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1817. return rc;
  1818. }
  1819. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1820. if (rc) {
  1821. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1822. enable);
  1823. return rc;
  1824. }
  1825. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1826. enable ? "enabled" : "disabled", i);
  1827. }
  1828. display->clamp_enabled = enable;
  1829. return 0;
  1830. }
  1831. /**
  1832. * dsi_display_setup_ctrl() - setup DSI controller.
  1833. * @dsi_display: DSI display handle.
  1834. *
  1835. * Return: error code.
  1836. */
  1837. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1838. {
  1839. int rc = 0;
  1840. int i = 0;
  1841. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1842. if (!display) {
  1843. DSI_ERR("Invalid params\n");
  1844. return -EINVAL;
  1845. }
  1846. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1847. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1848. if (rc) {
  1849. DSI_ERR("DSI controller setup failed\n");
  1850. return rc;
  1851. }
  1852. display_for_each_ctrl(i, display) {
  1853. ctrl = &display->ctrl[i];
  1854. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1855. continue;
  1856. rc = dsi_ctrl_setup(ctrl->ctrl);
  1857. if (rc) {
  1858. DSI_ERR("DSI controller setup failed\n");
  1859. return rc;
  1860. }
  1861. }
  1862. return 0;
  1863. }
  1864. static int dsi_display_phy_enable(struct dsi_display *display);
  1865. /**
  1866. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1867. * @dsi_display: DSI display handle.
  1868. * @mmss_clamp: True if clamp is enabled.
  1869. *
  1870. * Return: error code.
  1871. */
  1872. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1873. bool mmss_clamp)
  1874. {
  1875. int rc = 0;
  1876. int i = 0;
  1877. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1878. if (!display) {
  1879. DSI_ERR("Invalid params\n");
  1880. return -EINVAL;
  1881. }
  1882. if (mmss_clamp && !display->phy_idle_power_off) {
  1883. dsi_display_phy_enable(display);
  1884. return 0;
  1885. }
  1886. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1887. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1888. if (rc) {
  1889. DSI_ERR("DSI controller setup failed\n");
  1890. return rc;
  1891. }
  1892. display_for_each_ctrl(i, display) {
  1893. ctrl = &display->ctrl[i];
  1894. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1895. continue;
  1896. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1897. if (rc) {
  1898. DSI_ERR("DSI controller setup failed\n");
  1899. return rc;
  1900. }
  1901. }
  1902. display->phy_idle_power_off = false;
  1903. return 0;
  1904. }
  1905. /**
  1906. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  1907. * @dsi_display: DSI display handle.
  1908. *
  1909. * Return: error code.
  1910. */
  1911. static int dsi_display_phy_idle_off(struct dsi_display *display)
  1912. {
  1913. int rc = 0;
  1914. int i = 0;
  1915. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1916. if (!display) {
  1917. DSI_ERR("Invalid params\n");
  1918. return -EINVAL;
  1919. }
  1920. display_for_each_ctrl(i, display) {
  1921. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1922. if (!phy)
  1923. continue;
  1924. if (!phy->allow_phy_power_off) {
  1925. DSI_DEBUG("phy doesn't support this feature\n");
  1926. return 0;
  1927. }
  1928. }
  1929. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1930. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  1931. if (rc) {
  1932. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  1933. display->name, rc);
  1934. return rc;
  1935. }
  1936. display_for_each_ctrl(i, display) {
  1937. ctrl = &display->ctrl[i];
  1938. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1939. continue;
  1940. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  1941. if (rc) {
  1942. DSI_ERR("DSI controller setup failed\n");
  1943. return rc;
  1944. }
  1945. }
  1946. display->phy_idle_power_off = true;
  1947. return 0;
  1948. }
  1949. void dsi_display_enable_event(struct drm_connector *connector,
  1950. struct dsi_display *display,
  1951. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  1952. bool enable)
  1953. {
  1954. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  1955. int i;
  1956. if (!display) {
  1957. DSI_ERR("invalid display\n");
  1958. return;
  1959. }
  1960. if (event_info)
  1961. event_info->event_idx = event_idx;
  1962. switch (event_idx) {
  1963. case SDE_CONN_EVENT_VID_DONE:
  1964. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  1965. break;
  1966. case SDE_CONN_EVENT_CMD_DONE:
  1967. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  1968. break;
  1969. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  1970. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  1971. if (event_info) {
  1972. display_for_each_ctrl(i, display)
  1973. display->ctrl[i].ctrl->recovery_cb =
  1974. *event_info;
  1975. }
  1976. break;
  1977. case SDE_CONN_EVENT_PANEL_ID:
  1978. if (event_info)
  1979. display_for_each_ctrl(i, display)
  1980. display->ctrl[i].ctrl->panel_id_cb
  1981. = *event_info;
  1982. break;
  1983. default:
  1984. /* nothing to do */
  1985. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  1986. return;
  1987. }
  1988. if (enable) {
  1989. display_for_each_ctrl(i, display)
  1990. dsi_ctrl_enable_status_interrupt(
  1991. display->ctrl[i].ctrl, irq_status_idx,
  1992. event_info);
  1993. } else {
  1994. display_for_each_ctrl(i, display)
  1995. dsi_ctrl_disable_status_interrupt(
  1996. display->ctrl[i].ctrl, irq_status_idx);
  1997. }
  1998. }
  1999. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  2000. {
  2001. int rc = 0;
  2002. int i;
  2003. struct dsi_display_ctrl *ctrl;
  2004. /* Sequence does not matter for split dsi usecases */
  2005. display_for_each_ctrl(i, display) {
  2006. ctrl = &display->ctrl[i];
  2007. if (!ctrl->ctrl)
  2008. continue;
  2009. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2010. DSI_CTRL_POWER_VREG_ON);
  2011. if (rc) {
  2012. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2013. ctrl->ctrl->name, rc);
  2014. goto error;
  2015. }
  2016. }
  2017. return rc;
  2018. error:
  2019. for (i = i - 1; i >= 0; i--) {
  2020. ctrl = &display->ctrl[i];
  2021. if (!ctrl->ctrl)
  2022. continue;
  2023. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  2024. DSI_CTRL_POWER_VREG_OFF);
  2025. }
  2026. return rc;
  2027. }
  2028. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  2029. {
  2030. int rc = 0;
  2031. int i;
  2032. struct dsi_display_ctrl *ctrl;
  2033. /* Sequence does not matter for split dsi usecases */
  2034. display_for_each_ctrl(i, display) {
  2035. ctrl = &display->ctrl[i];
  2036. if (!ctrl->ctrl)
  2037. continue;
  2038. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2039. DSI_CTRL_POWER_VREG_OFF);
  2040. if (rc) {
  2041. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2042. ctrl->ctrl->name, rc);
  2043. goto error;
  2044. }
  2045. }
  2046. error:
  2047. return rc;
  2048. }
  2049. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  2050. unsigned int display_type)
  2051. {
  2052. char *boot_str = NULL;
  2053. char *str = NULL;
  2054. char *sw_te = NULL;
  2055. unsigned long cmdline_topology = NO_OVERRIDE;
  2056. unsigned long cmdline_timing = NO_OVERRIDE;
  2057. unsigned long panel_id = NO_OVERRIDE;
  2058. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2059. DSI_ERR("display_type=%d not supported\n", display_type);
  2060. goto end;
  2061. }
  2062. if (display_type == DSI_PRIMARY)
  2063. boot_str = dsi_display_primary;
  2064. else
  2065. boot_str = dsi_display_secondary;
  2066. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2067. if (sw_te)
  2068. display->sw_te_using_wd = true;
  2069. str = strnstr(boot_str, ":panelid", strlen(boot_str));
  2070. if (str) {
  2071. if (kstrtol(str + strlen(":panelid"), INT_BASE_10,
  2072. (unsigned long *)&panel_id)) {
  2073. DSI_INFO("panel id not found: %s\n", boot_str);
  2074. } else {
  2075. DSI_INFO("panel id found: %lx\n", panel_id);
  2076. display->panel_id = panel_id;
  2077. }
  2078. }
  2079. str = strnstr(boot_str, ":config", strlen(boot_str));
  2080. if (str) {
  2081. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2082. DSI_ERR("invalid config index override: %s\n",
  2083. boot_str);
  2084. goto end;
  2085. }
  2086. }
  2087. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2088. if (str) {
  2089. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2090. DSI_ERR("invalid timing index override: %s\n",
  2091. boot_str);
  2092. cmdline_topology = NO_OVERRIDE;
  2093. goto end;
  2094. }
  2095. }
  2096. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2097. end:
  2098. display->cmdline_topology = cmdline_topology;
  2099. display->cmdline_timing = cmdline_timing;
  2100. }
  2101. /**
  2102. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2103. *
  2104. * Return: returns error status
  2105. */
  2106. static int dsi_display_parse_boot_display_selection(void)
  2107. {
  2108. char *pos = NULL;
  2109. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2110. int i, j;
  2111. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2112. strlcpy(disp_buf, boot_displays[i].boot_param,
  2113. MAX_CMDLINE_PARAM_LEN);
  2114. pos = strnstr(disp_buf, ":", MAX_CMDLINE_PARAM_LEN);
  2115. /* Use ':' as a delimiter to retrieve the display name */
  2116. if (!pos) {
  2117. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2118. continue;
  2119. }
  2120. for (j = 0; (disp_buf + j) < pos; j++)
  2121. boot_displays[i].name[j] = *(disp_buf + j);
  2122. boot_displays[i].name[j] = '\0';
  2123. boot_displays[i].boot_disp_en = true;
  2124. }
  2125. return 0;
  2126. }
  2127. static int dsi_display_phy_power_on(struct dsi_display *display)
  2128. {
  2129. int rc = 0;
  2130. int i;
  2131. struct dsi_display_ctrl *ctrl;
  2132. /* Sequence does not matter for split dsi usecases */
  2133. display_for_each_ctrl(i, display) {
  2134. ctrl = &display->ctrl[i];
  2135. if (!ctrl->ctrl)
  2136. continue;
  2137. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2138. if (rc) {
  2139. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2140. ctrl->phy->name, rc);
  2141. goto error;
  2142. }
  2143. }
  2144. return rc;
  2145. error:
  2146. for (i = i - 1; i >= 0; i--) {
  2147. ctrl = &display->ctrl[i];
  2148. if (!ctrl->phy)
  2149. continue;
  2150. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2151. }
  2152. return rc;
  2153. }
  2154. static int dsi_display_phy_power_off(struct dsi_display *display)
  2155. {
  2156. int rc = 0;
  2157. int i;
  2158. struct dsi_display_ctrl *ctrl;
  2159. /* Sequence does not matter for split dsi usecases */
  2160. display_for_each_ctrl(i, display) {
  2161. ctrl = &display->ctrl[i];
  2162. if (!ctrl->phy)
  2163. continue;
  2164. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2165. if (rc) {
  2166. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2167. ctrl->ctrl->name, rc);
  2168. goto error;
  2169. }
  2170. }
  2171. error:
  2172. return rc;
  2173. }
  2174. static int dsi_display_set_clk_src(struct dsi_display *display)
  2175. {
  2176. int rc = 0;
  2177. int i;
  2178. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2179. /*
  2180. * For CPHY mode, the parent of mux_clks need to be set
  2181. * to Cphy_clks to have correct dividers for byte and
  2182. * pixel clocks.
  2183. */
  2184. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) {
  2185. rc = dsi_clk_update_parent(&display->clock_info.cphy_clks,
  2186. &display->clock_info.mux_clks);
  2187. if (rc) {
  2188. DSI_ERR("failed update mux parent to shadow\n");
  2189. return rc;
  2190. }
  2191. }
  2192. /*
  2193. * In case of split DSI usecases, the clock for master controller should
  2194. * be enabled before the other controller. Master controller in the
  2195. * clock context refers to the controller that sources the clock.
  2196. */
  2197. m_ctrl = &display->ctrl[display->clk_master_idx];
  2198. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
  2199. &display->clock_info.mux_clks);
  2200. if (rc) {
  2201. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n",
  2202. display->name, rc);
  2203. return rc;
  2204. }
  2205. /* Turn on rest of the controllers */
  2206. display_for_each_ctrl(i, display) {
  2207. ctrl = &display->ctrl[i];
  2208. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2209. continue;
  2210. rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
  2211. &display->clock_info.mux_clks);
  2212. if (rc) {
  2213. DSI_ERR("[%s] failed to set source clocks, rc=%d\n",
  2214. display->name, rc);
  2215. return rc;
  2216. }
  2217. }
  2218. return 0;
  2219. }
  2220. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2221. bool enable)
  2222. {
  2223. int rc = 0;
  2224. int i;
  2225. struct dsi_display_ctrl *ctrl;
  2226. display_for_each_ctrl(i, display) {
  2227. ctrl = &display->ctrl[i];
  2228. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2229. if (rc) {
  2230. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2231. display->name, enable ? "mask" : "unmask", rc);
  2232. return rc;
  2233. }
  2234. }
  2235. return 0;
  2236. }
  2237. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2238. {
  2239. struct dsi_display_ctrl *ctrl;
  2240. int i;
  2241. if (!display)
  2242. return;
  2243. display_for_each_ctrl(i, display) {
  2244. ctrl = &display->ctrl[i];
  2245. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2246. }
  2247. /*
  2248. * After retime buffer synchronization we need to turn of clk_en_sel
  2249. * bit on each phy. Avoid this for Cphy.
  2250. */
  2251. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2252. return;
  2253. display_for_each_ctrl(i, display) {
  2254. ctrl = &display->ctrl[i];
  2255. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2256. }
  2257. }
  2258. static int dsi_display_ctrl_update(struct dsi_display *display)
  2259. {
  2260. int rc = 0;
  2261. int i;
  2262. struct dsi_display_ctrl *ctrl;
  2263. display_for_each_ctrl(i, display) {
  2264. ctrl = &display->ctrl[i];
  2265. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2266. if (rc) {
  2267. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2268. display->name, i, rc);
  2269. goto error_host_deinit;
  2270. }
  2271. }
  2272. return 0;
  2273. error_host_deinit:
  2274. for (i = i - 1; i >= 0; i--) {
  2275. ctrl = &display->ctrl[i];
  2276. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2277. }
  2278. return rc;
  2279. }
  2280. static int dsi_display_ctrl_init(struct dsi_display *display)
  2281. {
  2282. int rc = 0;
  2283. int i;
  2284. struct dsi_display_ctrl *ctrl;
  2285. bool skip_op = is_skip_op_required(display);
  2286. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2287. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2288. * we will programe DSI controller as part of core clock enable.
  2289. * After that we should not re-configure DSI controller again here for
  2290. * usecases where we are resuming from ulps suspend as it might put
  2291. * the HW in bad state.
  2292. */
  2293. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2294. display_for_each_ctrl(i, display) {
  2295. ctrl = &display->ctrl[i];
  2296. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2297. if (rc) {
  2298. DSI_ERR(
  2299. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2300. display->name, i, skip_op, rc);
  2301. goto error_host_deinit;
  2302. }
  2303. }
  2304. } else {
  2305. display_for_each_ctrl(i, display) {
  2306. ctrl = &display->ctrl[i];
  2307. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2308. DSI_CTRL_OP_HOST_INIT,
  2309. true);
  2310. if (rc)
  2311. DSI_DEBUG("host init update failed rc=%d\n",
  2312. rc);
  2313. }
  2314. }
  2315. return rc;
  2316. error_host_deinit:
  2317. for (i = i - 1; i >= 0; i--) {
  2318. ctrl = &display->ctrl[i];
  2319. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2320. }
  2321. return rc;
  2322. }
  2323. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2324. {
  2325. int rc = 0;
  2326. int i;
  2327. struct dsi_display_ctrl *ctrl;
  2328. display_for_each_ctrl(i, display) {
  2329. ctrl = &display->ctrl[i];
  2330. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2331. if (rc) {
  2332. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2333. display->name, i, rc);
  2334. }
  2335. }
  2336. return rc;
  2337. }
  2338. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2339. {
  2340. int rc = 0;
  2341. int i;
  2342. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2343. bool skip_op = is_skip_op_required(display);
  2344. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2345. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2346. DSI_CTRL_ENGINE_ON, skip_op);
  2347. if (rc) {
  2348. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2349. display->name, skip_op, rc);
  2350. goto error;
  2351. }
  2352. display_for_each_ctrl(i, display) {
  2353. ctrl = &display->ctrl[i];
  2354. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2355. continue;
  2356. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2357. DSI_CTRL_ENGINE_ON, skip_op);
  2358. if (rc) {
  2359. DSI_ERR(
  2360. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2361. display->name, skip_op, rc);
  2362. goto error_disable_master;
  2363. }
  2364. }
  2365. return rc;
  2366. error_disable_master:
  2367. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2368. DSI_CTRL_ENGINE_OFF, skip_op);
  2369. error:
  2370. return rc;
  2371. }
  2372. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2373. {
  2374. int rc = 0;
  2375. int i;
  2376. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2377. bool skip_op = is_skip_op_required(display);
  2378. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2379. /*
  2380. * For platforms where ULPS is controlled by DSI controller block,
  2381. * do not disable dsi controller block if lanes are to be
  2382. * kept in ULPS during suspend. So just update the SW state
  2383. * and return early.
  2384. */
  2385. if (display->panel->ulps_suspend_enabled &&
  2386. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2387. display_for_each_ctrl(i, display) {
  2388. ctrl = &display->ctrl[i];
  2389. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2390. DSI_CTRL_OP_HOST_ENGINE,
  2391. false);
  2392. if (rc)
  2393. DSI_DEBUG("host state update failed %d\n", rc);
  2394. }
  2395. return rc;
  2396. }
  2397. display_for_each_ctrl(i, display) {
  2398. ctrl = &display->ctrl[i];
  2399. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2400. continue;
  2401. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2402. DSI_CTRL_ENGINE_OFF, skip_op);
  2403. if (rc)
  2404. DSI_ERR(
  2405. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2406. display->name, skip_op, rc);
  2407. }
  2408. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2409. DSI_CTRL_ENGINE_OFF, skip_op);
  2410. if (rc) {
  2411. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2412. display->name, skip_op, rc);
  2413. goto error;
  2414. }
  2415. error:
  2416. return rc;
  2417. }
  2418. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2419. {
  2420. int rc = 0;
  2421. int i;
  2422. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2423. bool skip_op = is_skip_op_required(display);
  2424. m_ctrl = &display->ctrl[display->video_master_idx];
  2425. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2426. DSI_CTRL_ENGINE_ON, skip_op);
  2427. if (rc) {
  2428. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2429. display->name, skip_op, rc);
  2430. goto error;
  2431. }
  2432. display_for_each_ctrl(i, display) {
  2433. ctrl = &display->ctrl[i];
  2434. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2435. continue;
  2436. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2437. DSI_CTRL_ENGINE_ON, skip_op);
  2438. if (rc) {
  2439. DSI_ERR(
  2440. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2441. display->name, skip_op, rc);
  2442. goto error_disable_master;
  2443. }
  2444. }
  2445. return rc;
  2446. error_disable_master:
  2447. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2448. DSI_CTRL_ENGINE_OFF, skip_op);
  2449. error:
  2450. return rc;
  2451. }
  2452. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2453. {
  2454. int rc = 0;
  2455. int i;
  2456. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2457. bool skip_op = is_skip_op_required(display);
  2458. m_ctrl = &display->ctrl[display->video_master_idx];
  2459. display_for_each_ctrl(i, display) {
  2460. ctrl = &display->ctrl[i];
  2461. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2462. continue;
  2463. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2464. DSI_CTRL_ENGINE_OFF, skip_op);
  2465. if (rc)
  2466. DSI_ERR(
  2467. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2468. display->name, skip_op, rc);
  2469. }
  2470. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2471. DSI_CTRL_ENGINE_OFF, skip_op);
  2472. if (rc)
  2473. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2474. display->name, skip_op, rc);
  2475. return rc;
  2476. }
  2477. static int dsi_display_phy_enable(struct dsi_display *display)
  2478. {
  2479. int rc = 0;
  2480. int i;
  2481. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2482. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2483. bool skip_op = is_skip_op_required(display);
  2484. m_ctrl = &display->ctrl[display->clk_master_idx];
  2485. if (display->ctrl_count > 1)
  2486. m_src = DSI_PLL_SOURCE_NATIVE;
  2487. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2488. m_src, true, skip_op);
  2489. if (rc) {
  2490. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2491. display->name, skip_op, rc);
  2492. goto error;
  2493. }
  2494. display_for_each_ctrl(i, display) {
  2495. ctrl = &display->ctrl[i];
  2496. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2497. continue;
  2498. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2499. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2500. if (rc) {
  2501. DSI_ERR(
  2502. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2503. display->name, skip_op, rc);
  2504. goto error_disable_master;
  2505. }
  2506. }
  2507. return rc;
  2508. error_disable_master:
  2509. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2510. error:
  2511. return rc;
  2512. }
  2513. static int dsi_display_phy_disable(struct dsi_display *display)
  2514. {
  2515. int rc = 0;
  2516. int i;
  2517. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2518. bool skip_op = is_skip_op_required(display);
  2519. m_ctrl = &display->ctrl[display->clk_master_idx];
  2520. display_for_each_ctrl(i, display) {
  2521. ctrl = &display->ctrl[i];
  2522. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2523. continue;
  2524. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2525. if (rc)
  2526. DSI_ERR(
  2527. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2528. display->name, skip_op, rc);
  2529. }
  2530. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2531. if (rc)
  2532. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2533. display->name, skip_op, rc);
  2534. return rc;
  2535. }
  2536. static int dsi_display_wake_up(struct dsi_display *display)
  2537. {
  2538. return 0;
  2539. }
  2540. static void dsi_display_mask_overflow(struct dsi_display *display, u32 flags,
  2541. bool enable)
  2542. {
  2543. struct dsi_display_ctrl *ctrl;
  2544. int i;
  2545. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2546. return;
  2547. display_for_each_ctrl(i, display) {
  2548. ctrl = &display->ctrl[i];
  2549. if (!ctrl)
  2550. continue;
  2551. dsi_ctrl_mask_overflow(ctrl->ctrl, enable);
  2552. }
  2553. }
  2554. static int dsi_display_broadcast_cmd(struct dsi_display *display,
  2555. const struct mipi_dsi_msg *msg)
  2556. {
  2557. int rc = 0;
  2558. u32 flags, m_flags;
  2559. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2560. int i;
  2561. m_flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_BROADCAST_MASTER |
  2562. DSI_CTRL_CMD_DEFER_TRIGGER | DSI_CTRL_CMD_FETCH_MEMORY);
  2563. flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER |
  2564. DSI_CTRL_CMD_FETCH_MEMORY);
  2565. if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) {
  2566. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  2567. m_flags |= DSI_CTRL_CMD_LAST_COMMAND;
  2568. }
  2569. /*
  2570. * During broadcast command dma scheduling is always recommended.
  2571. * As long as the display is enabled and TE is running the
  2572. * DSI_CTRL_CMD_CUSTOM_DMA_SCHED flag should be set.
  2573. */
  2574. if (display->enabled) {
  2575. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2576. m_flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2577. }
  2578. if (display->queue_cmd_waits ||
  2579. msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE) {
  2580. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2581. m_flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2582. }
  2583. /*
  2584. * 1. Setup commands in FIFO
  2585. * 2. Trigger commands
  2586. */
  2587. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2588. dsi_display_mask_overflow(display, m_flags, true);
  2589. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, msg, &m_flags);
  2590. if (rc) {
  2591. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2592. display->name, rc);
  2593. goto error;
  2594. }
  2595. display_for_each_ctrl(i, display) {
  2596. ctrl = &display->ctrl[i];
  2597. if (ctrl == m_ctrl)
  2598. continue;
  2599. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, msg, &flags);
  2600. if (rc) {
  2601. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2602. display->name, rc);
  2603. goto error;
  2604. }
  2605. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, flags);
  2606. if (rc) {
  2607. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2608. display->name, rc);
  2609. goto error;
  2610. }
  2611. }
  2612. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, m_flags);
  2613. if (rc) {
  2614. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2615. display->name, rc);
  2616. goto error;
  2617. }
  2618. error:
  2619. dsi_display_mask_overflow(display, m_flags, false);
  2620. return rc;
  2621. }
  2622. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2623. {
  2624. int rc = 0;
  2625. int i;
  2626. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2627. /*
  2628. * For continuous splash and trusted vm environment,
  2629. * ctrl states are updated separately and hence we do
  2630. * an early return
  2631. */
  2632. if (is_skip_op_required(display)) {
  2633. DSI_DEBUG(
  2634. "cont splash/trusted vm use case, phy sw reset not required\n");
  2635. return 0;
  2636. }
  2637. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2638. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2639. if (rc) {
  2640. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2641. goto error;
  2642. }
  2643. display_for_each_ctrl(i, display) {
  2644. ctrl = &display->ctrl[i];
  2645. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2646. continue;
  2647. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2648. if (rc) {
  2649. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2650. display->name, rc);
  2651. goto error;
  2652. }
  2653. }
  2654. error:
  2655. return rc;
  2656. }
  2657. static int dsi_host_attach(struct mipi_dsi_host *host,
  2658. struct mipi_dsi_device *dsi)
  2659. {
  2660. return 0;
  2661. }
  2662. static int dsi_host_detach(struct mipi_dsi_host *host,
  2663. struct mipi_dsi_device *dsi)
  2664. {
  2665. return 0;
  2666. }
  2667. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
  2668. const struct mipi_dsi_msg *msg)
  2669. {
  2670. struct dsi_display *display;
  2671. int rc = 0, ret = 0;
  2672. if (!host || !msg) {
  2673. DSI_ERR("Invalid params\n");
  2674. return 0;
  2675. }
  2676. display = to_dsi_display(host);
  2677. /* Avoid sending DCS commands when ESD recovery is pending */
  2678. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2679. DSI_DEBUG("ESD recovery pending\n");
  2680. return 0;
  2681. }
  2682. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2683. DSI_ALL_CLKS, DSI_CLK_ON);
  2684. if (rc) {
  2685. DSI_ERR("[%s] failed to enable all DSI clocks, rc=%d\n",
  2686. display->name, rc);
  2687. goto error;
  2688. }
  2689. rc = dsi_display_wake_up(display);
  2690. if (rc) {
  2691. DSI_ERR("[%s] failed to wake up display, rc=%d\n",
  2692. display->name, rc);
  2693. goto error_disable_clks;
  2694. }
  2695. rc = dsi_display_cmd_engine_enable(display);
  2696. if (rc) {
  2697. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2698. display->name, rc);
  2699. goto error_disable_clks;
  2700. }
  2701. if (display->tx_cmd_buf == NULL) {
  2702. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2703. if (rc) {
  2704. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2705. goto error_disable_cmd_engine;
  2706. }
  2707. }
  2708. if (display->ctrl_count > 1 && !(msg->flags & MIPI_DSI_MSG_UNICAST)) {
  2709. rc = dsi_display_broadcast_cmd(display, msg);
  2710. if (rc) {
  2711. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n",
  2712. display->name, rc);
  2713. goto error_disable_cmd_engine;
  2714. }
  2715. } else {
  2716. int ctrl_idx = (msg->flags & MIPI_DSI_MSG_UNICAST) ?
  2717. msg->ctrl : 0;
  2718. u32 cmd_flags = DSI_CTRL_CMD_FETCH_MEMORY;
  2719. if (display->queue_cmd_waits ||
  2720. msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  2721. cmd_flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2722. if ((msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  2723. (display->enabled))
  2724. cmd_flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2725. rc = dsi_ctrl_cmd_transfer(display->ctrl[ctrl_idx].ctrl, msg,
  2726. &cmd_flags);
  2727. if (rc) {
  2728. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2729. display->name, rc);
  2730. goto error_disable_cmd_engine;
  2731. }
  2732. }
  2733. error_disable_cmd_engine:
  2734. ret = dsi_display_cmd_engine_disable(display);
  2735. if (ret) {
  2736. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  2737. display->name, ret);
  2738. }
  2739. error_disable_clks:
  2740. ret = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2741. DSI_ALL_CLKS, DSI_CLK_OFF);
  2742. if (ret) {
  2743. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  2744. display->name, ret);
  2745. }
  2746. error:
  2747. return rc;
  2748. }
  2749. static struct mipi_dsi_host_ops dsi_host_ops = {
  2750. .attach = dsi_host_attach,
  2751. .detach = dsi_host_detach,
  2752. .transfer = dsi_host_transfer,
  2753. };
  2754. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2755. {
  2756. int rc = 0;
  2757. struct mipi_dsi_host *host = &display->host;
  2758. host->dev = &display->pdev->dev;
  2759. host->ops = &dsi_host_ops;
  2760. rc = mipi_dsi_host_register(host);
  2761. if (rc) {
  2762. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2763. display->name, rc);
  2764. goto error;
  2765. }
  2766. error:
  2767. return rc;
  2768. }
  2769. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2770. {
  2771. int rc = 0;
  2772. struct mipi_dsi_host *host = &display->host;
  2773. mipi_dsi_host_unregister(host);
  2774. host->dev = NULL;
  2775. host->ops = NULL;
  2776. return rc;
  2777. }
  2778. static int dsi_display_clocks_deinit(struct dsi_display *display)
  2779. {
  2780. int rc = 0;
  2781. struct dsi_clk_link_set *src = &display->clock_info.src_clks;
  2782. struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
  2783. struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
  2784. if (src->byte_clk) {
  2785. devm_clk_put(&display->pdev->dev, src->byte_clk);
  2786. src->byte_clk = NULL;
  2787. }
  2788. if (src->pixel_clk) {
  2789. devm_clk_put(&display->pdev->dev, src->pixel_clk);
  2790. src->pixel_clk = NULL;
  2791. }
  2792. if (mux->byte_clk) {
  2793. devm_clk_put(&display->pdev->dev, mux->byte_clk);
  2794. mux->byte_clk = NULL;
  2795. }
  2796. if (mux->pixel_clk) {
  2797. devm_clk_put(&display->pdev->dev, mux->pixel_clk);
  2798. mux->pixel_clk = NULL;
  2799. }
  2800. if (shadow->byte_clk) {
  2801. devm_clk_put(&display->pdev->dev, shadow->byte_clk);
  2802. shadow->byte_clk = NULL;
  2803. }
  2804. if (shadow->pixel_clk) {
  2805. devm_clk_put(&display->pdev->dev, shadow->pixel_clk);
  2806. shadow->pixel_clk = NULL;
  2807. }
  2808. return rc;
  2809. }
  2810. static bool dsi_display_check_prefix(const char *clk_prefix,
  2811. const char *clk_name)
  2812. {
  2813. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2814. }
  2815. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2816. char *dsi_clk_name)
  2817. {
  2818. if (display->fw)
  2819. return dsi_parser_count_strings(display->parser_node,
  2820. dsi_clk_name);
  2821. else
  2822. return of_property_count_strings(display->panel_node,
  2823. dsi_clk_name);
  2824. }
  2825. static void dsi_display_get_clock_name(struct dsi_display *display,
  2826. char *dsi_clk_name, int index,
  2827. const char **clk_name)
  2828. {
  2829. if (display->fw)
  2830. dsi_parser_read_string_index(display->parser_node,
  2831. dsi_clk_name, index, clk_name);
  2832. else
  2833. of_property_read_string_index(display->panel_node,
  2834. dsi_clk_name, index, clk_name);
  2835. }
  2836. static int dsi_display_clocks_init(struct dsi_display *display)
  2837. {
  2838. int i, rc = 0, num_clk = 0;
  2839. const char *clk_name;
  2840. const char *src_byte = "src_byte", *src_pixel = "src_pixel";
  2841. const char *mux_byte = "mux_byte", *mux_pixel = "mux_pixel";
  2842. const char *cphy_byte = "cphy_byte", *cphy_pixel = "cphy_pixel";
  2843. const char *shadow_byte = "shadow_byte", *shadow_pixel = "shadow_pixel";
  2844. const char *shadow_cphybyte = "shadow_cphybyte",
  2845. *shadow_cphypixel = "shadow_cphypixel";
  2846. struct clk *dsi_clk;
  2847. struct dsi_clk_link_set *src = &display->clock_info.src_clks;
  2848. struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
  2849. struct dsi_clk_link_set *cphy = &display->clock_info.cphy_clks;
  2850. struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
  2851. struct dsi_clk_link_set *shadow_cphy =
  2852. &display->clock_info.shadow_cphy_clks;
  2853. struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);
  2854. char *dsi_clock_name;
  2855. if (!strcmp(display->display_type, "primary"))
  2856. dsi_clock_name = "qcom,dsi-select-clocks";
  2857. else
  2858. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2859. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2860. DSI_DEBUG("clk count=%d\n", num_clk);
  2861. for (i = 0; i < num_clk; i++) {
  2862. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2863. &clk_name);
  2864. DSI_DEBUG("clock name:%s\n", clk_name);
  2865. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2866. if (IS_ERR_OR_NULL(dsi_clk)) {
  2867. rc = PTR_ERR(dsi_clk);
  2868. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2869. if (dsi_display_check_prefix(mux_byte, clk_name)) {
  2870. mux->byte_clk = NULL;
  2871. goto error;
  2872. }
  2873. if (dsi_display_check_prefix(mux_pixel, clk_name)) {
  2874. mux->pixel_clk = NULL;
  2875. goto error;
  2876. }
  2877. if (dsi_display_check_prefix(cphy_byte, clk_name)) {
  2878. cphy->byte_clk = NULL;
  2879. goto error;
  2880. }
  2881. if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
  2882. cphy->pixel_clk = NULL;
  2883. goto error;
  2884. }
  2885. if (dyn_clk_caps->dyn_clk_support &&
  2886. (display->panel->panel_mode ==
  2887. DSI_OP_VIDEO_MODE)) {
  2888. if (dsi_display_check_prefix(src_byte,
  2889. clk_name))
  2890. src->byte_clk = NULL;
  2891. if (dsi_display_check_prefix(src_pixel,
  2892. clk_name))
  2893. src->pixel_clk = NULL;
  2894. if (dsi_display_check_prefix(shadow_byte,
  2895. clk_name))
  2896. shadow->byte_clk = NULL;
  2897. if (dsi_display_check_prefix(shadow_pixel,
  2898. clk_name))
  2899. shadow->pixel_clk = NULL;
  2900. if (dsi_display_check_prefix(shadow_cphybyte,
  2901. clk_name))
  2902. shadow_cphy->byte_clk = NULL;
  2903. if (dsi_display_check_prefix(shadow_cphypixel,
  2904. clk_name))
  2905. shadow_cphy->pixel_clk = NULL;
  2906. dyn_clk_caps->dyn_clk_support = false;
  2907. }
  2908. }
  2909. if (dsi_display_check_prefix(src_byte, clk_name)) {
  2910. src->byte_clk = dsi_clk;
  2911. continue;
  2912. }
  2913. if (dsi_display_check_prefix(src_pixel, clk_name)) {
  2914. src->pixel_clk = dsi_clk;
  2915. continue;
  2916. }
  2917. if (dsi_display_check_prefix(cphy_byte, clk_name)) {
  2918. cphy->byte_clk = dsi_clk;
  2919. continue;
  2920. }
  2921. if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
  2922. cphy->pixel_clk = dsi_clk;
  2923. continue;
  2924. }
  2925. if (dsi_display_check_prefix(mux_byte, clk_name)) {
  2926. mux->byte_clk = dsi_clk;
  2927. continue;
  2928. }
  2929. if (dsi_display_check_prefix(mux_pixel, clk_name)) {
  2930. mux->pixel_clk = dsi_clk;
  2931. continue;
  2932. }
  2933. if (dsi_display_check_prefix(shadow_byte, clk_name)) {
  2934. shadow->byte_clk = dsi_clk;
  2935. continue;
  2936. }
  2937. if (dsi_display_check_prefix(shadow_pixel, clk_name)) {
  2938. shadow->pixel_clk = dsi_clk;
  2939. continue;
  2940. }
  2941. if (dsi_display_check_prefix(shadow_cphybyte, clk_name)) {
  2942. shadow_cphy->byte_clk = dsi_clk;
  2943. continue;
  2944. }
  2945. if (dsi_display_check_prefix(shadow_cphypixel, clk_name)) {
  2946. shadow_cphy->pixel_clk = dsi_clk;
  2947. continue;
  2948. }
  2949. }
  2950. return 0;
  2951. error:
  2952. (void)dsi_display_clocks_deinit(display);
  2953. return rc;
  2954. }
  2955. static int dsi_display_clk_ctrl_cb(void *priv,
  2956. struct dsi_clk_ctrl_info clk_state_info)
  2957. {
  2958. int rc = 0;
  2959. struct dsi_display *display = NULL;
  2960. void *clk_handle = NULL;
  2961. if (!priv) {
  2962. DSI_ERR("Invalid params\n");
  2963. return -EINVAL;
  2964. }
  2965. display = priv;
  2966. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2967. clk_handle = display->mdp_clk_handle;
  2968. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2969. clk_handle = display->dsi_clk_handle;
  2970. } else {
  2971. DSI_ERR("invalid clk handle, return error\n");
  2972. return -EINVAL;
  2973. }
  2974. /*
  2975. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2976. * to turn off DSI clocks.
  2977. */
  2978. rc = dsi_display_clk_ctrl(clk_handle,
  2979. clk_state_info.clk_type, clk_state_info.clk_state);
  2980. if (rc) {
  2981. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2982. display->name, clk_state_info.clk_state,
  2983. clk_state_info.clk_type, rc);
  2984. return rc;
  2985. }
  2986. return 0;
  2987. }
  2988. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  2989. {
  2990. int i;
  2991. struct dsi_display_ctrl *ctrl;
  2992. if (!display)
  2993. return;
  2994. display_for_each_ctrl(i, display) {
  2995. ctrl = &display->ctrl[i];
  2996. if (!ctrl)
  2997. continue;
  2998. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  2999. }
  3000. }
  3001. int dsi_pre_clkoff_cb(void *priv,
  3002. enum dsi_clk_type clk,
  3003. enum dsi_lclk_type l_type,
  3004. enum dsi_clk_state new_state)
  3005. {
  3006. int rc = 0, i;
  3007. struct dsi_display *display = priv;
  3008. struct dsi_display_ctrl *ctrl;
  3009. /*
  3010. * If Idle Power Collapse occurs immediately after a CMD
  3011. * transfer with an asynchronous wait for DMA done, ensure
  3012. * that the work queued is scheduled and completed before turning
  3013. * off the clocks and disabling interrupts to validate the command
  3014. * transfer.
  3015. */
  3016. display_for_each_ctrl(i, display) {
  3017. ctrl = &display->ctrl[i];
  3018. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  3019. continue;
  3020. flush_workqueue(display->dma_cmd_workq);
  3021. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  3022. ctrl->ctrl->dma_wait_queued = false;
  3023. }
  3024. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3025. (l_type & DSI_LINK_LP_CLK)) {
  3026. /*
  3027. * If continuous clock is enabled then disable it
  3028. * before entering into ULPS Mode.
  3029. */
  3030. if (display->panel->host_config.force_hs_clk_lane)
  3031. _dsi_display_continuous_clk_ctrl(display, false);
  3032. /*
  3033. * If ULPS feature is enabled, enter ULPS first.
  3034. * However, when blanking the panel, we should enter ULPS
  3035. * only if ULPS during suspend feature is enabled.
  3036. */
  3037. if (!dsi_panel_initialized(display->panel)) {
  3038. if (display->panel->ulps_suspend_enabled)
  3039. rc = dsi_display_set_ulps(display, true);
  3040. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  3041. rc = dsi_display_set_ulps(display, true);
  3042. }
  3043. if (rc)
  3044. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  3045. __func__, rc);
  3046. }
  3047. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3048. (l_type & DSI_LINK_HS_CLK)) {
  3049. /*
  3050. * PHY clock gating should be disabled before the PLL and the
  3051. * branch clocks are turned off. Otherwise, it is possible that
  3052. * the clock RCGs may not be turned off correctly resulting
  3053. * in clock warnings.
  3054. */
  3055. rc = dsi_display_config_clk_gating(display, false);
  3056. if (rc)
  3057. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  3058. display->name, rc);
  3059. }
  3060. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  3061. /*
  3062. * Enable DSI clamps only if entering idle power collapse or
  3063. * when ULPS during suspend is enabled..
  3064. */
  3065. if (dsi_panel_initialized(display->panel) ||
  3066. display->panel->ulps_suspend_enabled) {
  3067. dsi_display_phy_idle_off(display);
  3068. rc = dsi_display_set_clamp(display, true);
  3069. if (rc)
  3070. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  3071. __func__, rc);
  3072. rc = dsi_display_phy_reset_config(display, false);
  3073. if (rc)
  3074. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3075. __func__, rc);
  3076. } else {
  3077. /* Make sure that controller is not in ULPS state when
  3078. * the DSI link is not active.
  3079. */
  3080. rc = dsi_display_set_ulps(display, false);
  3081. if (rc)
  3082. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  3083. __func__, rc);
  3084. }
  3085. /* dsi will not be able to serve irqs from here on */
  3086. dsi_display_ctrl_irq_update(display, false);
  3087. /* cache the MISR values */
  3088. display_for_each_ctrl(i, display) {
  3089. ctrl = &display->ctrl[i];
  3090. if (!ctrl->ctrl)
  3091. continue;
  3092. dsi_ctrl_cache_misr(ctrl->ctrl);
  3093. }
  3094. }
  3095. return rc;
  3096. }
  3097. int dsi_post_clkon_cb(void *priv,
  3098. enum dsi_clk_type clk,
  3099. enum dsi_lclk_type l_type,
  3100. enum dsi_clk_state curr_state)
  3101. {
  3102. int rc = 0;
  3103. struct dsi_display *display = priv;
  3104. bool mmss_clamp = false;
  3105. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3106. mmss_clamp = display->clamp_enabled;
  3107. /*
  3108. * controller setup is needed if coming out of idle
  3109. * power collapse with clamps enabled.
  3110. */
  3111. if (mmss_clamp)
  3112. dsi_display_ctrl_setup(display);
  3113. /*
  3114. * Phy setup is needed if coming out of idle
  3115. * power collapse with clamps enabled.
  3116. */
  3117. if (display->phy_idle_power_off || mmss_clamp)
  3118. dsi_display_phy_idle_on(display, mmss_clamp);
  3119. if (display->ulps_enabled && mmss_clamp) {
  3120. /*
  3121. * ULPS Entry Request. This is needed if the lanes were
  3122. * in ULPS prior to power collapse, since after
  3123. * power collapse and reset, the DSI controller resets
  3124. * back to idle state and not ULPS. This ulps entry
  3125. * request will transition the state of the DSI
  3126. * controller to ULPS which will match the state of the
  3127. * DSI phy. This needs to be done prior to disabling
  3128. * the DSI clamps.
  3129. *
  3130. * Also, reset the ulps flag so that ulps_config
  3131. * function would reconfigure the controller state to
  3132. * ULPS.
  3133. */
  3134. display->ulps_enabled = false;
  3135. rc = dsi_display_set_ulps(display, true);
  3136. if (rc) {
  3137. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3138. __func__, rc);
  3139. goto error;
  3140. }
  3141. }
  3142. rc = dsi_display_phy_reset_config(display, true);
  3143. if (rc) {
  3144. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3145. __func__, rc);
  3146. goto error;
  3147. }
  3148. rc = dsi_display_set_clamp(display, false);
  3149. if (rc) {
  3150. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3151. __func__, rc);
  3152. goto error;
  3153. }
  3154. }
  3155. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3156. /*
  3157. * Toggle the resync FIFO everytime clock changes, except
  3158. * when cont-splash screen transition is going on.
  3159. * Toggling resync FIFO during cont splash transition
  3160. * can lead to blinks on the display.
  3161. */
  3162. if (!display->is_cont_splash_enabled)
  3163. dsi_display_toggle_resync_fifo(display);
  3164. if (display->ulps_enabled) {
  3165. rc = dsi_display_set_ulps(display, false);
  3166. if (rc) {
  3167. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3168. __func__, rc);
  3169. goto error;
  3170. }
  3171. }
  3172. if (display->panel->host_config.force_hs_clk_lane)
  3173. _dsi_display_continuous_clk_ctrl(display, true);
  3174. rc = dsi_display_config_clk_gating(display, true);
  3175. if (rc) {
  3176. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3177. display->name, rc);
  3178. goto error;
  3179. }
  3180. }
  3181. /* enable dsi to serve irqs */
  3182. if (clk & DSI_CORE_CLK)
  3183. dsi_display_ctrl_irq_update(display, true);
  3184. error:
  3185. return rc;
  3186. }
  3187. int dsi_post_clkoff_cb(void *priv,
  3188. enum dsi_clk_type clk_type,
  3189. enum dsi_lclk_type l_type,
  3190. enum dsi_clk_state curr_state)
  3191. {
  3192. int rc = 0;
  3193. struct dsi_display *display = priv;
  3194. if (!display) {
  3195. DSI_ERR("%s: Invalid arg\n", __func__);
  3196. return -EINVAL;
  3197. }
  3198. if ((clk_type & DSI_CORE_CLK) &&
  3199. (curr_state == DSI_CLK_OFF)) {
  3200. rc = dsi_display_phy_power_off(display);
  3201. if (rc)
  3202. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3203. display->name, rc);
  3204. rc = dsi_display_ctrl_power_off(display);
  3205. if (rc)
  3206. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3207. display->name, rc);
  3208. }
  3209. return rc;
  3210. }
  3211. int dsi_pre_clkon_cb(void *priv,
  3212. enum dsi_clk_type clk_type,
  3213. enum dsi_lclk_type l_type,
  3214. enum dsi_clk_state new_state)
  3215. {
  3216. int rc = 0;
  3217. struct dsi_display *display = priv;
  3218. if (!display) {
  3219. DSI_ERR("%s: invalid input\n", __func__);
  3220. return -EINVAL;
  3221. }
  3222. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3223. /*
  3224. * Enable DSI core power
  3225. * 1.> PANEL_PM are controlled as part of
  3226. * panel_power_ctrl. Needed not be handled here.
  3227. * 2.> CTRL_PM need to be enabled/disabled
  3228. * only during unblank/blank. Their state should
  3229. * not be changed during static screen.
  3230. */
  3231. DSI_DEBUG("updating power states for ctrl and phy\n");
  3232. rc = dsi_display_ctrl_power_on(display);
  3233. if (rc) {
  3234. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3235. display->name, rc);
  3236. return rc;
  3237. }
  3238. rc = dsi_display_phy_power_on(display);
  3239. if (rc) {
  3240. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3241. display->name, rc);
  3242. return rc;
  3243. }
  3244. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3245. }
  3246. return rc;
  3247. }
  3248. static void __set_lane_map_v2(u8 *lane_map_v2,
  3249. enum dsi_phy_data_lanes lane0,
  3250. enum dsi_phy_data_lanes lane1,
  3251. enum dsi_phy_data_lanes lane2,
  3252. enum dsi_phy_data_lanes lane3)
  3253. {
  3254. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3255. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3256. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3257. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3258. }
  3259. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3260. {
  3261. int rc = 0, i = 0;
  3262. const char *data;
  3263. u8 temp[DSI_LANE_MAX - 1];
  3264. if (!display) {
  3265. DSI_ERR("invalid params\n");
  3266. return -EINVAL;
  3267. }
  3268. /* lane-map-v2 supersedes lane-map-v1 setting */
  3269. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3270. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3271. if (!rc) {
  3272. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3273. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3274. return 0;
  3275. } else if (rc != EINVAL) {
  3276. DSI_DEBUG("Incorrect mapping, configure default\n");
  3277. goto set_default;
  3278. }
  3279. /* lane-map older version, for DSI controller version < 2.0 */
  3280. data = of_get_property(display->pdev->dev.of_node,
  3281. "qcom,lane-map", NULL);
  3282. if (!data)
  3283. goto set_default;
  3284. if (!strcmp(data, "lane_map_3012")) {
  3285. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3286. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3287. DSI_PHYSICAL_LANE_1,
  3288. DSI_PHYSICAL_LANE_2,
  3289. DSI_PHYSICAL_LANE_3,
  3290. DSI_PHYSICAL_LANE_0);
  3291. } else if (!strcmp(data, "lane_map_2301")) {
  3292. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3293. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3294. DSI_PHYSICAL_LANE_2,
  3295. DSI_PHYSICAL_LANE_3,
  3296. DSI_PHYSICAL_LANE_0,
  3297. DSI_PHYSICAL_LANE_1);
  3298. } else if (!strcmp(data, "lane_map_1230")) {
  3299. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3300. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3301. DSI_PHYSICAL_LANE_3,
  3302. DSI_PHYSICAL_LANE_0,
  3303. DSI_PHYSICAL_LANE_1,
  3304. DSI_PHYSICAL_LANE_2);
  3305. } else if (!strcmp(data, "lane_map_0321")) {
  3306. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3307. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3308. DSI_PHYSICAL_LANE_0,
  3309. DSI_PHYSICAL_LANE_3,
  3310. DSI_PHYSICAL_LANE_2,
  3311. DSI_PHYSICAL_LANE_1);
  3312. } else if (!strcmp(data, "lane_map_1032")) {
  3313. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3314. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3315. DSI_PHYSICAL_LANE_1,
  3316. DSI_PHYSICAL_LANE_0,
  3317. DSI_PHYSICAL_LANE_3,
  3318. DSI_PHYSICAL_LANE_2);
  3319. } else if (!strcmp(data, "lane_map_2103")) {
  3320. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3321. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3322. DSI_PHYSICAL_LANE_2,
  3323. DSI_PHYSICAL_LANE_1,
  3324. DSI_PHYSICAL_LANE_0,
  3325. DSI_PHYSICAL_LANE_3);
  3326. } else if (!strcmp(data, "lane_map_3210")) {
  3327. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3328. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3329. DSI_PHYSICAL_LANE_3,
  3330. DSI_PHYSICAL_LANE_2,
  3331. DSI_PHYSICAL_LANE_1,
  3332. DSI_PHYSICAL_LANE_0);
  3333. } else {
  3334. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3335. __func__, data);
  3336. goto set_default;
  3337. }
  3338. return 0;
  3339. set_default:
  3340. /* default lane mapping */
  3341. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3342. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3343. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3344. return 0;
  3345. }
  3346. static int dsi_display_get_phandle_index(
  3347. struct dsi_display *display,
  3348. const char *propname, int count, int index)
  3349. {
  3350. struct device_node *disp_node = display->panel_node;
  3351. u32 *val = NULL;
  3352. int rc = 0;
  3353. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3354. if (ZERO_OR_NULL_PTR(val)) {
  3355. rc = -ENOMEM;
  3356. goto end;
  3357. }
  3358. if (index >= count)
  3359. goto end;
  3360. if (display->fw)
  3361. rc = dsi_parser_read_u32_array(display->parser_node,
  3362. propname, val, count);
  3363. else
  3364. rc = of_property_read_u32_array(disp_node, propname,
  3365. val, count);
  3366. if (rc)
  3367. goto end;
  3368. rc = val[index];
  3369. DSI_DEBUG("%s index=%d\n", propname, rc);
  3370. end:
  3371. kfree(val);
  3372. return rc;
  3373. }
  3374. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3375. const char *propname)
  3376. {
  3377. if (display->fw)
  3378. return dsi_parser_count_u32_elems(display->parser_node,
  3379. propname);
  3380. else
  3381. return of_property_count_u32_elems(display->panel_node,
  3382. propname);
  3383. }
  3384. static int dsi_display_parse_dt(struct dsi_display *display)
  3385. {
  3386. int i, rc = 0;
  3387. u32 phy_count = 0;
  3388. struct device_node *of_node = display->pdev->dev.of_node;
  3389. char *dsi_ctrl_name, *dsi_phy_name;
  3390. if (!strcmp(display->display_type, "primary")) {
  3391. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3392. dsi_phy_name = "qcom,dsi-phy-num";
  3393. } else {
  3394. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3395. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3396. }
  3397. display->ctrl_count = dsi_display_get_phandle_count(display,
  3398. dsi_ctrl_name);
  3399. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3400. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3401. display->ctrl_count, phy_count);
  3402. if (!phy_count || !display->ctrl_count) {
  3403. DSI_ERR("no ctrl/phys found\n");
  3404. rc = -ENODEV;
  3405. goto error;
  3406. }
  3407. if (phy_count != display->ctrl_count) {
  3408. DSI_ERR("different ctrl and phy counts\n");
  3409. rc = -ENODEV;
  3410. goto error;
  3411. }
  3412. display_for_each_ctrl(i, display) {
  3413. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3414. int index;
  3415. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3416. display->ctrl_count, i);
  3417. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3418. "qcom,dsi-ctrl", index);
  3419. of_node_put(ctrl->ctrl_of_node);
  3420. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3421. display->ctrl_count, i);
  3422. ctrl->phy_of_node = of_parse_phandle(of_node,
  3423. "qcom,dsi-phy", index);
  3424. of_node_put(ctrl->phy_of_node);
  3425. }
  3426. /* Parse TE data */
  3427. dsi_display_parse_te_data(display);
  3428. /* Parse all external bridges from port 0 */
  3429. display_for_each_ctrl(i, display) {
  3430. display->ext_bridge[i].node_of =
  3431. of_graph_get_remote_node(of_node, 0, i);
  3432. if (display->ext_bridge[i].node_of)
  3433. display->ext_bridge_cnt++;
  3434. else
  3435. break;
  3436. }
  3437. DSI_DEBUG("success\n");
  3438. error:
  3439. return rc;
  3440. }
  3441. static int dsi_display_res_init(struct dsi_display *display)
  3442. {
  3443. int rc = 0;
  3444. int i;
  3445. struct dsi_display_ctrl *ctrl;
  3446. display_for_each_ctrl(i, display) {
  3447. ctrl = &display->ctrl[i];
  3448. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3449. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3450. rc = PTR_ERR(ctrl->ctrl);
  3451. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3452. ctrl->ctrl = NULL;
  3453. goto error_ctrl_put;
  3454. }
  3455. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3456. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3457. rc = PTR_ERR(ctrl->phy);
  3458. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3459. dsi_ctrl_put(ctrl->ctrl);
  3460. ctrl->phy = NULL;
  3461. goto error_ctrl_put;
  3462. }
  3463. }
  3464. display->panel = dsi_panel_get(&display->pdev->dev,
  3465. display->panel_node,
  3466. display->parser_node,
  3467. display->display_type,
  3468. display->cmdline_topology,
  3469. display->trusted_vm_env);
  3470. if (IS_ERR_OR_NULL(display->panel)) {
  3471. rc = PTR_ERR(display->panel);
  3472. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3473. display->panel = NULL;
  3474. goto error_ctrl_put;
  3475. }
  3476. display_for_each_ctrl(i, display) {
  3477. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3478. phy->cfg.force_clk_lane_hs =
  3479. display->panel->host_config.force_hs_clk_lane;
  3480. phy->cfg.phy_type =
  3481. display->panel->host_config.phy_type;
  3482. }
  3483. rc = dsi_display_parse_lane_map(display);
  3484. if (rc) {
  3485. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3486. goto error_ctrl_put;
  3487. }
  3488. rc = dsi_display_clocks_init(display);
  3489. if (rc) {
  3490. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3491. goto error_ctrl_put;
  3492. }
  3493. /**
  3494. * In trusted vm, the connectors will not be enabled
  3495. * until the HW resources are assigned and accepted.
  3496. */
  3497. if (display->trusted_vm_env)
  3498. display->is_active = false;
  3499. else
  3500. display->is_active = true;
  3501. return 0;
  3502. error_ctrl_put:
  3503. for (i = i - 1; i >= 0; i--) {
  3504. ctrl = &display->ctrl[i];
  3505. dsi_ctrl_put(ctrl->ctrl);
  3506. dsi_phy_put(ctrl->phy);
  3507. }
  3508. return rc;
  3509. }
  3510. static int dsi_display_res_deinit(struct dsi_display *display)
  3511. {
  3512. int rc = 0;
  3513. int i;
  3514. struct dsi_display_ctrl *ctrl;
  3515. rc = dsi_display_clocks_deinit(display);
  3516. if (rc)
  3517. DSI_ERR("clocks deinit failed, rc=%d\n", rc);
  3518. display_for_each_ctrl(i, display) {
  3519. ctrl = &display->ctrl[i];
  3520. dsi_phy_put(ctrl->phy);
  3521. dsi_ctrl_put(ctrl->ctrl);
  3522. }
  3523. if (display->panel)
  3524. dsi_panel_put(display->panel);
  3525. return rc;
  3526. }
  3527. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3528. struct dsi_display_mode *mode,
  3529. u32 flags)
  3530. {
  3531. int rc = 0;
  3532. int i;
  3533. struct dsi_display_ctrl *ctrl;
  3534. /*
  3535. * To set a mode:
  3536. * 1. Controllers should be turned off.
  3537. * 2. Link clocks should be off.
  3538. * 3. Phy should be disabled.
  3539. */
  3540. display_for_each_ctrl(i, display) {
  3541. ctrl = &display->ctrl[i];
  3542. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3543. (ctrl->phy_enabled)) {
  3544. rc = -EINVAL;
  3545. goto error;
  3546. }
  3547. }
  3548. error:
  3549. return rc;
  3550. }
  3551. static bool dsi_display_is_seamless_dfps_possible(
  3552. const struct dsi_display *display,
  3553. const struct dsi_display_mode *tgt,
  3554. const enum dsi_dfps_type dfps_type)
  3555. {
  3556. struct dsi_display_mode *cur;
  3557. if (!display || !tgt || !display->panel) {
  3558. DSI_ERR("Invalid params\n");
  3559. return false;
  3560. }
  3561. cur = display->panel->cur_mode;
  3562. if (cur->timing.h_active != tgt->timing.h_active) {
  3563. DSI_DEBUG("timing.h_active differs %d %d\n",
  3564. cur->timing.h_active, tgt->timing.h_active);
  3565. return false;
  3566. }
  3567. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3568. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3569. cur->timing.h_back_porch,
  3570. tgt->timing.h_back_porch);
  3571. return false;
  3572. }
  3573. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3574. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3575. cur->timing.h_sync_width,
  3576. tgt->timing.h_sync_width);
  3577. return false;
  3578. }
  3579. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3580. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3581. cur->timing.h_front_porch,
  3582. tgt->timing.h_front_porch);
  3583. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3584. return false;
  3585. }
  3586. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3587. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3588. cur->timing.h_skew,
  3589. tgt->timing.h_skew);
  3590. return false;
  3591. }
  3592. /* skip polarity comparison */
  3593. if (cur->timing.v_active != tgt->timing.v_active) {
  3594. DSI_DEBUG("timing.v_active differs %d %d\n",
  3595. cur->timing.v_active,
  3596. tgt->timing.v_active);
  3597. return false;
  3598. }
  3599. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3600. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3601. cur->timing.v_back_porch,
  3602. tgt->timing.v_back_porch);
  3603. return false;
  3604. }
  3605. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3606. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3607. cur->timing.v_sync_width,
  3608. tgt->timing.v_sync_width);
  3609. return false;
  3610. }
  3611. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3612. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3613. cur->timing.v_front_porch,
  3614. tgt->timing.v_front_porch);
  3615. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3616. return false;
  3617. }
  3618. /* skip polarity comparison */
  3619. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3620. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3621. cur->timing.refresh_rate,
  3622. tgt->timing.refresh_rate);
  3623. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3624. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3625. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3626. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3627. DSI_DEBUG("flags differs %d %d\n",
  3628. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3629. return true;
  3630. }
  3631. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3632. {
  3633. struct dsi_host_common_cfg *config;
  3634. struct dsi_display_ctrl *m_ctrl;
  3635. int phy_ver;
  3636. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3637. config = &display->panel->host_config;
  3638. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3639. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3640. config->byte_intf_clk_div = 1;
  3641. else
  3642. config->byte_intf_clk_div = 2;
  3643. }
  3644. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3645. u32 bit_clk_rate)
  3646. {
  3647. int rc = 0;
  3648. int i;
  3649. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3650. if (!display->panel) {
  3651. DSI_ERR("Invalid params\n");
  3652. return -EINVAL;
  3653. }
  3654. if (bit_clk_rate == 0) {
  3655. DSI_ERR("Invalid bit clock rate\n");
  3656. return -EINVAL;
  3657. }
  3658. display->config.bit_clk_rate_hz = bit_clk_rate;
  3659. display_for_each_ctrl(i, display) {
  3660. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3661. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3662. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3663. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3664. byte_intf_clk_rate;
  3665. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3666. struct dsi_host_common_cfg *host_cfg;
  3667. mutex_lock(&ctrl->ctrl_lock);
  3668. host_cfg = &display->panel->host_config;
  3669. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3670. num_of_lanes++;
  3671. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3672. num_of_lanes++;
  3673. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3674. num_of_lanes++;
  3675. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3676. num_of_lanes++;
  3677. if (num_of_lanes == 0) {
  3678. DSI_ERR("Invalid lane count\n");
  3679. rc = -EINVAL;
  3680. goto error;
  3681. }
  3682. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3683. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3684. bit_rate_per_lane = bit_rate;
  3685. do_div(bit_rate_per_lane, num_of_lanes);
  3686. pclk_rate = bit_rate;
  3687. do_div(pclk_rate, bpp);
  3688. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3689. bit_rate_per_lane = bit_rate;
  3690. do_div(bit_rate_per_lane, num_of_lanes);
  3691. byte_clk_rate = bit_rate_per_lane;
  3692. do_div(byte_clk_rate, 8);
  3693. byte_intf_clk_rate = byte_clk_rate;
  3694. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3695. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3696. } else {
  3697. bit_rate_per_lane = bit_clk_rate;
  3698. pclk_rate *= bits_per_symbol;
  3699. do_div(pclk_rate, num_of_symbols);
  3700. byte_clk_rate = bit_clk_rate;
  3701. do_div(byte_clk_rate, num_of_symbols);
  3702. /* For CPHY, byte_intf_clk is same as byte_clk */
  3703. byte_intf_clk_rate = byte_clk_rate;
  3704. }
  3705. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3706. bit_rate, bit_rate_per_lane);
  3707. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3708. byte_clk_rate, byte_intf_clk_rate);
  3709. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3710. SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
  3711. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3712. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3713. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3714. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3715. ctrl->clk_freq, ctrl->cell_index);
  3716. if (rc) {
  3717. DSI_ERR("Failed to update link frequencies\n");
  3718. goto error;
  3719. }
  3720. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3721. error:
  3722. mutex_unlock(&ctrl->ctrl_lock);
  3723. /* TODO: recover ctrl->clk_freq in case of failure */
  3724. if (rc)
  3725. return rc;
  3726. }
  3727. return 0;
  3728. }
  3729. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3730. struct dsi_dyn_clk_delay *delay,
  3731. struct dsi_display_mode *mode)
  3732. {
  3733. u32 esc_clk_rate_hz;
  3734. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3735. u32 hsync_period = 0;
  3736. struct dsi_display_ctrl *m_ctrl;
  3737. struct dsi_ctrl *dsi_ctrl;
  3738. struct dsi_phy_cfg *cfg;
  3739. int phy_ver;
  3740. m_ctrl = &display->ctrl[display->clk_master_idx];
  3741. dsi_ctrl = m_ctrl->ctrl;
  3742. cfg = &(m_ctrl->phy->cfg);
  3743. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3744. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3745. esc_clk_rate_hz);
  3746. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3747. esc_clk_rate_hz);
  3748. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3749. esc_clk_rate_hz);
  3750. hsync_period = dsi_h_total_dce(&mode->timing);
  3751. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3752. if (!display->panel->video_config.eof_bllp_lp11_en)
  3753. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3754. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3755. (display->config.common_config.t_clk_post + 1)) /
  3756. byte_to_esc_ratio) +
  3757. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3758. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3759. ((cfg->timing.lane_v3[3] * 4) +
  3760. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3761. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3762. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3763. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3764. hr_bit_to_esc_ratio);
  3765. delay->pipe_delay2 = 0;
  3766. if (display->panel->host_config.force_hs_clk_lane)
  3767. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3768. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3769. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3770. hr_bit_to_esc_ratio);
  3771. /*
  3772. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3773. * 25us pll delay recommended for phy ver 4.0
  3774. */
  3775. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3776. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3777. delay->pll_delay = 100;
  3778. else
  3779. delay->pll_delay = 25;
  3780. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3781. }
  3782. /*
  3783. * dsi_display_is_type_cphy - check if panel type is cphy
  3784. * @display: Pointer to private display structure
  3785. * Returns: True if panel type is cphy
  3786. */
  3787. static inline bool dsi_display_is_type_cphy(struct dsi_display *display)
  3788. {
  3789. return (display->panel->host_config.phy_type ==
  3790. DSI_PHY_TYPE_CPHY) ? true : false;
  3791. }
  3792. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3793. struct link_clk_freq *bkp_freq)
  3794. {
  3795. int rc = 0, i;
  3796. u8 ctrl_version;
  3797. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3798. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3799. struct dsi_clk_link_set *parent_clk, *enable_clk;
  3800. m_ctrl = &display->ctrl[display->clk_master_idx];
  3801. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3802. ctrl_version = m_ctrl->ctrl->version;
  3803. if (dsi_display_is_type_cphy(display)) {
  3804. enable_clk = &display->clock_info.cphy_clks;
  3805. parent_clk = &display->clock_info.shadow_cphy_clks;
  3806. } else {
  3807. enable_clk = &display->clock_info.src_clks;
  3808. parent_clk = &display->clock_info.shadow_clks;
  3809. }
  3810. dsi_clk_prepare_enable(enable_clk);
  3811. rc = dsi_clk_update_parent(parent_clk,
  3812. &display->clock_info.mux_clks);
  3813. if (rc) {
  3814. DSI_ERR("failed to update mux parent\n");
  3815. goto exit;
  3816. }
  3817. display_for_each_ctrl(i, display) {
  3818. ctrl = &display->ctrl[i];
  3819. if (!ctrl->ctrl)
  3820. continue;
  3821. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3822. ctrl->ctrl->clk_freq.byte_clk_rate,
  3823. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3824. if (rc) {
  3825. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3826. goto recover_byte_clk;
  3827. }
  3828. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3829. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3830. if (rc) {
  3831. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3832. goto recover_pix_clk;
  3833. }
  3834. }
  3835. display_for_each_ctrl(i, display) {
  3836. ctrl = &display->ctrl[i];
  3837. if (ctrl == m_ctrl)
  3838. continue;
  3839. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3840. }
  3841. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3842. /*
  3843. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3844. * and with constant fps, as dynamic refresh will applied with
  3845. * next mdp intf ctrl flush.
  3846. */
  3847. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3848. (dyn_clk_caps->maintain_const_fps))
  3849. goto defer_dfps_wait;
  3850. /* wait for dynamic refresh done */
  3851. display_for_each_ctrl(i, display) {
  3852. ctrl = &display->ctrl[i];
  3853. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3854. if (rc) {
  3855. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3856. goto recover_pix_clk;
  3857. } else {
  3858. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3859. i ? "slave" : "master");
  3860. }
  3861. }
  3862. display_for_each_ctrl(i, display) {
  3863. ctrl = &display->ctrl[i];
  3864. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3865. }
  3866. defer_dfps_wait:
  3867. rc = dsi_clk_update_parent(enable_clk,
  3868. &display->clock_info.mux_clks);
  3869. if (rc)
  3870. DSI_ERR("could not switch back to src clks %d\n", rc);
  3871. dsi_clk_disable_unprepare(enable_clk);
  3872. return rc;
  3873. recover_pix_clk:
  3874. display_for_each_ctrl(i, display) {
  3875. ctrl = &display->ctrl[i];
  3876. if (!ctrl->ctrl)
  3877. continue;
  3878. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3879. bkp_freq->pix_clk_rate, i);
  3880. }
  3881. recover_byte_clk:
  3882. display_for_each_ctrl(i, display) {
  3883. ctrl = &display->ctrl[i];
  3884. if (!ctrl->ctrl)
  3885. continue;
  3886. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3887. bkp_freq->byte_clk_rate,
  3888. bkp_freq->byte_intf_clk_rate, i);
  3889. }
  3890. exit:
  3891. dsi_clk_disable_unprepare(&display->clock_info.src_clks);
  3892. return rc;
  3893. }
  3894. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3895. struct dsi_display_mode *mode)
  3896. {
  3897. int rc = 0, mask, i;
  3898. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3899. struct dsi_dyn_clk_delay delay;
  3900. struct link_clk_freq bkp_freq;
  3901. dsi_panel_acquire_panel_lock(display->panel);
  3902. m_ctrl = &display->ctrl[display->clk_master_idx];
  3903. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3904. /* mask PLL unlock, FIFO overflow and underflow errors */
  3905. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3906. BIT(DSI_FIFO_OVERFLOW);
  3907. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3908. /* update the phy timings based on new mode */
  3909. display_for_each_ctrl(i, display) {
  3910. ctrl = &display->ctrl[i];
  3911. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3912. }
  3913. /* back up existing rates to handle failure case */
  3914. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3915. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3916. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3917. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3918. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3919. if (rc) {
  3920. DSI_ERR("failed set link frequencies %d\n", rc);
  3921. goto exit;
  3922. }
  3923. /* calculate pipe delays */
  3924. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3925. /* configure dynamic refresh ctrl registers */
  3926. display_for_each_ctrl(i, display) {
  3927. ctrl = &display->ctrl[i];
  3928. if (!ctrl->phy)
  3929. continue;
  3930. if (ctrl == m_ctrl)
  3931. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3932. else
  3933. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3934. false);
  3935. }
  3936. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3937. exit:
  3938. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3939. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3940. DSI_CLK_OFF);
  3941. /* store newly calculated phy timings in mode private info */
  3942. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3943. mode->priv_info->phy_timing_val,
  3944. mode->priv_info->phy_timing_len);
  3945. dsi_panel_release_panel_lock(display->panel);
  3946. return rc;
  3947. }
  3948. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3949. int clk_rate)
  3950. {
  3951. int rc = 0;
  3952. if (clk_rate <= 0) {
  3953. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3954. return -EINVAL;
  3955. }
  3956. if (clk_rate == display->cached_clk_rate) {
  3957. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  3958. return rc;
  3959. }
  3960. display->cached_clk_rate = clk_rate;
  3961. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  3962. if (!rc) {
  3963. DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
  3964. __func__, clk_rate);
  3965. atomic_set(&display->clkrate_change_pending, 1);
  3966. } else {
  3967. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  3968. __func__, clk_rate, rc);
  3969. /* Caching clock failed, so don't go on doing so. */
  3970. atomic_set(&display->clkrate_change_pending, 0);
  3971. display->cached_clk_rate = 0;
  3972. }
  3973. return rc;
  3974. }
  3975. static int dsi_display_dfps_update(struct dsi_display *display,
  3976. struct dsi_display_mode *dsi_mode)
  3977. {
  3978. struct dsi_mode_info *timing;
  3979. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3980. struct dsi_display_mode *panel_mode;
  3981. struct dsi_dfps_capabilities dfps_caps;
  3982. int rc = 0;
  3983. int i = 0;
  3984. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3985. if (!display || !dsi_mode || !display->panel) {
  3986. DSI_ERR("Invalid params\n");
  3987. return -EINVAL;
  3988. }
  3989. timing = &dsi_mode->timing;
  3990. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3991. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3992. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  3993. DSI_ERR("dfps or constant fps not supported\n");
  3994. return -ENOTSUPP;
  3995. }
  3996. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  3997. DSI_ERR("dfps clock method not supported\n");
  3998. return -ENOTSUPP;
  3999. }
  4000. /* For split DSI, update the clock master first */
  4001. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  4002. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  4003. m_ctrl = &display->ctrl[display->clk_master_idx];
  4004. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  4005. if (rc) {
  4006. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  4007. display->name, i, rc);
  4008. goto error;
  4009. }
  4010. /* Update the rest of the controllers */
  4011. display_for_each_ctrl(i, display) {
  4012. ctrl = &display->ctrl[i];
  4013. if (!ctrl->ctrl || (ctrl == m_ctrl))
  4014. continue;
  4015. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  4016. if (rc) {
  4017. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  4018. display->name, i, rc);
  4019. goto error;
  4020. }
  4021. }
  4022. panel_mode = display->panel->cur_mode;
  4023. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  4024. /*
  4025. * dsi_mode_flags flags are used to communicate with other drm driver
  4026. * components, and are transient. They aren't inherently part of the
  4027. * display panel's mode and shouldn't be saved into the cached currently
  4028. * active mode.
  4029. */
  4030. panel_mode->dsi_mode_flags = 0;
  4031. error:
  4032. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  4033. return rc;
  4034. }
  4035. static int dsi_display_dfps_calc_front_porch(
  4036. u32 old_fps,
  4037. u32 new_fps,
  4038. u32 a_total,
  4039. u32 b_total,
  4040. u32 b_fp,
  4041. u32 *b_fp_out)
  4042. {
  4043. s32 b_fp_new;
  4044. int add_porches, diff;
  4045. if (!b_fp_out) {
  4046. DSI_ERR("Invalid params\n");
  4047. return -EINVAL;
  4048. }
  4049. if (!a_total || !new_fps) {
  4050. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  4051. return -EINVAL;
  4052. }
  4053. /*
  4054. * Keep clock, other porches constant, use new fps, calc front porch
  4055. * new_vtotal = old_vtotal * (old_fps / new_fps )
  4056. * new_vfp - old_vfp = new_vtotal - old_vtotal
  4057. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  4058. */
  4059. diff = abs(old_fps - new_fps);
  4060. add_porches = mult_frac(b_total, diff, new_fps);
  4061. if (old_fps > new_fps)
  4062. b_fp_new = b_fp + add_porches;
  4063. else
  4064. b_fp_new = b_fp - add_porches;
  4065. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  4066. new_fps, a_total, b_total, b_fp, b_fp_new);
  4067. if (b_fp_new < 0) {
  4068. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  4069. return -EINVAL;
  4070. }
  4071. /**
  4072. * TODO: To differentiate from clock method when communicating to the
  4073. * other components, perhaps we should set clk here to original value
  4074. */
  4075. *b_fp_out = b_fp_new;
  4076. return 0;
  4077. }
  4078. /**
  4079. * dsi_display_get_dfps_timing() - Get the new dfps values.
  4080. * @display: DSI display handle.
  4081. * @adj_mode: Mode value structure to be changed.
  4082. * It contains old timing values and latest fps value.
  4083. * New timing values are updated based on new fps.
  4084. * @curr_refresh_rate: Current fps rate.
  4085. * If zero , current fps rate is taken from
  4086. * display->panel->cur_mode.
  4087. * Return: error code.
  4088. */
  4089. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  4090. struct dsi_display_mode *adj_mode,
  4091. u32 curr_refresh_rate)
  4092. {
  4093. struct dsi_dfps_capabilities dfps_caps;
  4094. struct dsi_display_mode per_ctrl_mode;
  4095. struct dsi_mode_info *timing;
  4096. struct dsi_ctrl *m_ctrl;
  4097. int rc = 0;
  4098. if (!display || !adj_mode) {
  4099. DSI_ERR("Invalid params\n");
  4100. return -EINVAL;
  4101. }
  4102. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  4103. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4104. if (!dfps_caps.dfps_support) {
  4105. DSI_ERR("dfps not supported by panel\n");
  4106. return -EINVAL;
  4107. }
  4108. per_ctrl_mode = *adj_mode;
  4109. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  4110. if (!curr_refresh_rate) {
  4111. if (!dsi_display_is_seamless_dfps_possible(display,
  4112. &per_ctrl_mode, dfps_caps.type)) {
  4113. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4114. return -EINVAL;
  4115. }
  4116. if (display->panel->cur_mode) {
  4117. curr_refresh_rate =
  4118. display->panel->cur_mode->timing.refresh_rate;
  4119. } else {
  4120. DSI_ERR("cur_mode is not initialized\n");
  4121. return -EINVAL;
  4122. }
  4123. }
  4124. /* TODO: Remove this direct reference to the dsi_ctrl */
  4125. timing = &per_ctrl_mode.timing;
  4126. switch (dfps_caps.type) {
  4127. case DSI_DFPS_IMMEDIATE_VFP:
  4128. rc = dsi_display_dfps_calc_front_porch(
  4129. curr_refresh_rate,
  4130. timing->refresh_rate,
  4131. dsi_h_total_dce(timing),
  4132. DSI_V_TOTAL(timing),
  4133. timing->v_front_porch,
  4134. &adj_mode->timing.v_front_porch);
  4135. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
  4136. curr_refresh_rate, timing->refresh_rate,
  4137. timing->v_front_porch, adj_mode->timing.v_front_porch);
  4138. break;
  4139. case DSI_DFPS_IMMEDIATE_HFP:
  4140. rc = dsi_display_dfps_calc_front_porch(
  4141. curr_refresh_rate,
  4142. timing->refresh_rate,
  4143. DSI_V_TOTAL(timing),
  4144. dsi_h_total_dce(timing),
  4145. timing->h_front_porch,
  4146. &adj_mode->timing.h_front_porch);
  4147. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
  4148. curr_refresh_rate, timing->refresh_rate,
  4149. timing->h_front_porch, adj_mode->timing.h_front_porch);
  4150. if (!rc)
  4151. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4152. break;
  4153. default:
  4154. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4155. rc = -ENOTSUPP;
  4156. }
  4157. return rc;
  4158. }
  4159. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4160. struct dsi_display_mode *adj_mode)
  4161. {
  4162. int rc = 0;
  4163. if (!display || !adj_mode) {
  4164. DSI_ERR("Invalid params\n");
  4165. return false;
  4166. }
  4167. /* Currently the only seamless transition is dynamic fps */
  4168. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4169. if (rc) {
  4170. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4171. } else {
  4172. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4173. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4174. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4175. }
  4176. return rc;
  4177. }
  4178. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4179. struct dsi_display_mode *to_mode)
  4180. {
  4181. u32 cur_fps, to_fps;
  4182. u32 cur_h_active, to_h_active;
  4183. u32 cur_v_active, to_v_active;
  4184. cur_fps = cur_mode->timing.refresh_rate;
  4185. to_fps = to_mode->timing.refresh_rate;
  4186. cur_h_active = cur_mode->timing.h_active;
  4187. cur_v_active = cur_mode->timing.v_active;
  4188. to_h_active = to_mode->timing.h_active;
  4189. to_v_active = to_mode->timing.v_active;
  4190. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4191. (cur_fps != to_fps)) {
  4192. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4193. DSI_DEBUG("DMS Modeset with FPS change\n");
  4194. } else {
  4195. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4196. }
  4197. }
  4198. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4199. struct dsi_display_mode *mode,
  4200. u32 flags)
  4201. {
  4202. int rc = 0, clk_rate = 0;
  4203. int i;
  4204. struct dsi_display_ctrl *ctrl;
  4205. struct dsi_display_ctrl *mctrl;
  4206. struct dsi_display_mode_priv_info *priv_info;
  4207. bool commit_phy_timing = false;
  4208. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4209. priv_info = mode->priv_info;
  4210. if (!priv_info) {
  4211. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4212. display->name);
  4213. return -EINVAL;
  4214. }
  4215. SDE_EVT32(mode->dsi_mode_flags, mode->panel_mode);
  4216. display->panel->panel_mode = mode->panel_mode;
  4217. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4218. mode,
  4219. &display->config);
  4220. if (rc) {
  4221. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4222. display->name, rc);
  4223. goto error;
  4224. }
  4225. memcpy(&display->config.lane_map, &display->lane_map,
  4226. sizeof(display->lane_map));
  4227. mctrl = &display->ctrl[display->clk_master_idx];
  4228. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4229. if (mode->dsi_mode_flags &
  4230. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4231. display_for_each_ctrl(i, display) {
  4232. ctrl = &display->ctrl[i];
  4233. if (!ctrl->ctrl || (ctrl != mctrl))
  4234. continue;
  4235. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4236. true);
  4237. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4238. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4239. (dyn_clk_caps->maintain_const_fps)) {
  4240. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4241. true);
  4242. }
  4243. }
  4244. rc = dsi_display_dfps_update(display, mode);
  4245. if (rc) {
  4246. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4247. display->name, rc);
  4248. goto error;
  4249. }
  4250. display_for_each_ctrl(i, display) {
  4251. ctrl = &display->ctrl[i];
  4252. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4253. &display->config, mode, mode->dsi_mode_flags,
  4254. display->dsi_clk_handle);
  4255. if (rc) {
  4256. DSI_ERR("failed to update ctrl config\n");
  4257. goto error;
  4258. }
  4259. }
  4260. if (priv_info->phy_timing_len) {
  4261. display_for_each_ctrl(i, display) {
  4262. ctrl = &display->ctrl[i];
  4263. rc = dsi_phy_set_timing_params(ctrl->phy,
  4264. priv_info->phy_timing_val,
  4265. priv_info->phy_timing_len,
  4266. commit_phy_timing);
  4267. if (rc)
  4268. DSI_ERR("Fail to add timing params\n");
  4269. }
  4270. }
  4271. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4272. return rc;
  4273. }
  4274. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4275. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4276. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4277. if (rc)
  4278. DSI_ERR("dynamic clk change failed %d\n", rc);
  4279. /*
  4280. * skip rest of the opearations since
  4281. * dsi_display_dynamic_clk_switch_vid() already takes
  4282. * care of them.
  4283. */
  4284. return rc;
  4285. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4286. clk_rate = mode->timing.clk_rate_hz;
  4287. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4288. clk_rate);
  4289. if (rc) {
  4290. DSI_ERR("Failed to configure dynamic clk\n");
  4291. return rc;
  4292. }
  4293. }
  4294. }
  4295. display_for_each_ctrl(i, display) {
  4296. ctrl = &display->ctrl[i];
  4297. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4298. mode, mode->dsi_mode_flags,
  4299. display->dsi_clk_handle);
  4300. if (rc) {
  4301. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4302. display->name, rc);
  4303. goto error;
  4304. }
  4305. }
  4306. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4307. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4308. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4309. u64 to_bitclk = mode->timing.clk_rate_hz;
  4310. commit_phy_timing = true;
  4311. /* No need to set clkrate pending flag if clocks are same */
  4312. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4313. atomic_set(&display->clkrate_change_pending, 1);
  4314. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4315. }
  4316. if (priv_info->phy_timing_len) {
  4317. display_for_each_ctrl(i, display) {
  4318. ctrl = &display->ctrl[i];
  4319. rc = dsi_phy_set_timing_params(ctrl->phy,
  4320. priv_info->phy_timing_val,
  4321. priv_info->phy_timing_len,
  4322. commit_phy_timing);
  4323. if (rc)
  4324. DSI_ERR("failed to add DSI PHY timing params\n");
  4325. }
  4326. }
  4327. error:
  4328. return rc;
  4329. }
  4330. /**
  4331. * _dsi_display_dev_init - initializes the display device
  4332. * Initialization will acquire references to the resources required for the
  4333. * display hardware to function.
  4334. * @display: Handle to the display
  4335. * Returns: Zero on success
  4336. */
  4337. static int _dsi_display_dev_init(struct dsi_display *display)
  4338. {
  4339. int rc = 0;
  4340. if (!display) {
  4341. DSI_ERR("invalid display\n");
  4342. return -EINVAL;
  4343. }
  4344. if (!display->panel_node && !display->fw)
  4345. return 0;
  4346. mutex_lock(&display->display_lock);
  4347. display->parser = dsi_parser_get(&display->pdev->dev);
  4348. if (display->fw && display->parser)
  4349. display->parser_node = dsi_parser_get_head_node(
  4350. display->parser, display->fw->data,
  4351. display->fw->size);
  4352. rc = dsi_display_parse_dt(display);
  4353. if (rc) {
  4354. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4355. goto error;
  4356. }
  4357. rc = dsi_display_res_init(display);
  4358. if (rc) {
  4359. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4360. display->name, rc);
  4361. goto error;
  4362. }
  4363. error:
  4364. mutex_unlock(&display->display_lock);
  4365. return rc;
  4366. }
  4367. /**
  4368. * _dsi_display_dev_deinit - deinitializes the display device
  4369. * All the resources acquired during device init will be released.
  4370. * @display: Handle to the display
  4371. * Returns: Zero on success
  4372. */
  4373. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4374. {
  4375. int rc = 0;
  4376. if (!display) {
  4377. DSI_ERR("invalid display\n");
  4378. return -EINVAL;
  4379. }
  4380. mutex_lock(&display->display_lock);
  4381. rc = dsi_display_res_deinit(display);
  4382. if (rc)
  4383. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4384. display->name, rc);
  4385. mutex_unlock(&display->display_lock);
  4386. return rc;
  4387. }
  4388. /**
  4389. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4390. * @dsi_display: Pointer to dsi display
  4391. * Returns: Zero on success
  4392. */
  4393. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4394. {
  4395. struct dsi_display *display = dsi_display;
  4396. int rc = 0;
  4397. /* Remove the panel vote that was added during dsi display probe */
  4398. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4399. if (rc)
  4400. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4401. display->panel->name, rc);
  4402. return rc;
  4403. }
  4404. /**
  4405. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4406. * @dsi_display: Pointer to dsi display
  4407. * Returns: Zero on success
  4408. */
  4409. int dsi_display_cont_splash_config(void *dsi_display)
  4410. {
  4411. struct dsi_display *display = dsi_display;
  4412. int rc = 0;
  4413. /* Vote for gdsc required to read register address space */
  4414. if (!display) {
  4415. DSI_ERR("invalid input display param\n");
  4416. return -EINVAL;
  4417. }
  4418. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4419. if (rc < 0) {
  4420. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4421. rc);
  4422. return rc;
  4423. }
  4424. mutex_lock(&display->display_lock);
  4425. display->is_cont_splash_enabled = true;
  4426. /* Update splash status for clock manager */
  4427. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4428. display->is_cont_splash_enabled);
  4429. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
  4430. /* Set up ctrl isr before enabling core clk */
  4431. dsi_display_ctrl_isr_configure(display, true);
  4432. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4433. * regulator are inplicit from pre clk on callback
  4434. */
  4435. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4436. DSI_ALL_CLKS, DSI_CLK_ON);
  4437. if (rc) {
  4438. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4439. display->name, rc);
  4440. goto clk_manager_update;
  4441. }
  4442. mutex_unlock(&display->display_lock);
  4443. /* Set the current brightness level */
  4444. dsi_panel_bl_handoff(display->panel);
  4445. return rc;
  4446. clk_manager_update:
  4447. dsi_display_ctrl_isr_configure(display, false);
  4448. /* Update splash status for clock manager */
  4449. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4450. false);
  4451. pm_runtime_put_sync(display->drm_dev->dev);
  4452. display->is_cont_splash_enabled = false;
  4453. mutex_unlock(&display->display_lock);
  4454. return rc;
  4455. }
  4456. /**
  4457. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4458. * @display: Pointer to dsi display
  4459. * Returns: Zero on success
  4460. */
  4461. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4462. {
  4463. int rc = 0;
  4464. if (!display->is_cont_splash_enabled)
  4465. return 0;
  4466. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4467. DSI_ALL_CLKS, DSI_CLK_OFF);
  4468. if (rc)
  4469. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4470. display->name, rc);
  4471. pm_runtime_put_sync(display->drm_dev->dev);
  4472. display->is_cont_splash_enabled = false;
  4473. /* Update splash status for clock manager */
  4474. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4475. display->is_cont_splash_enabled);
  4476. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
  4477. return rc;
  4478. }
  4479. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4480. {
  4481. int rc = 0;
  4482. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4483. if (!rc) {
  4484. DSI_DEBUG("dsi bit clk has been configured to %d\n",
  4485. display->cached_clk_rate);
  4486. atomic_set(&display->clkrate_change_pending, 0);
  4487. } else {
  4488. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4489. display->cached_clk_rate, rc);
  4490. }
  4491. return rc;
  4492. }
  4493. static int dsi_display_validate_split_link(struct dsi_display *display)
  4494. {
  4495. int i, rc = 0;
  4496. struct dsi_display_ctrl *ctrl;
  4497. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4498. if (!host->split_link.split_link_enabled)
  4499. return 0;
  4500. if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4501. DSI_ERR("[%s] split link is not supported in command mode\n",
  4502. display->name);
  4503. rc = -ENOTSUPP;
  4504. goto error;
  4505. }
  4506. display_for_each_ctrl(i, display) {
  4507. ctrl = &display->ctrl[i];
  4508. if (!ctrl->ctrl->split_link_supported) {
  4509. DSI_ERR("[%s] split link is not supported by hw\n",
  4510. display->name);
  4511. rc = -ENOTSUPP;
  4512. goto error;
  4513. }
  4514. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4515. }
  4516. DSI_DEBUG("Split link is enabled\n");
  4517. return 0;
  4518. error:
  4519. host->split_link.split_link_enabled = false;
  4520. return rc;
  4521. }
  4522. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4523. {
  4524. int rc = 0;
  4525. struct dsi_display *display;
  4526. if (!data)
  4527. return -EINVAL;
  4528. rc = dsi_ctrl_get_io_resources(io_res);
  4529. if (rc)
  4530. goto end;
  4531. rc = dsi_phy_get_io_resources(io_res);
  4532. if (rc)
  4533. goto end;
  4534. display = (struct dsi_display *)data;
  4535. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4536. end:
  4537. return rc;
  4538. }
  4539. static int dsi_display_pre_release(void *data)
  4540. {
  4541. if (!data)
  4542. return -EINVAL;
  4543. dsi_display_ctrl_irq_update((struct dsi_display *)data, false);
  4544. return 0;
  4545. }
  4546. static int dsi_display_pre_acquire(void *data)
  4547. {
  4548. if (!data)
  4549. return -EINVAL;
  4550. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4551. return 0;
  4552. }
  4553. /**
  4554. * dsi_display_bind - bind dsi device with controlling device
  4555. * @dev: Pointer to base of platform device
  4556. * @master: Pointer to container of drm device
  4557. * @data: Pointer to private data
  4558. * Returns: Zero on success
  4559. */
  4560. static int dsi_display_bind(struct device *dev,
  4561. struct device *master,
  4562. void *data)
  4563. {
  4564. struct dsi_display_ctrl *display_ctrl;
  4565. struct drm_device *drm;
  4566. struct dsi_display *display;
  4567. struct dsi_clk_info info;
  4568. struct clk_ctrl_cb clk_cb;
  4569. void *handle = NULL;
  4570. struct platform_device *pdev = to_platform_device(dev);
  4571. char *client1 = "dsi_clk_client";
  4572. char *client2 = "mdp_event_client";
  4573. struct msm_vm_ops vm_event_ops = {
  4574. .vm_get_io_resources = dsi_display_get_io_resources,
  4575. .vm_pre_hw_release = dsi_display_pre_release,
  4576. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4577. };
  4578. int i, rc = 0;
  4579. if (!dev || !pdev || !master) {
  4580. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4581. dev, pdev, master);
  4582. return -EINVAL;
  4583. }
  4584. drm = dev_get_drvdata(master);
  4585. display = platform_get_drvdata(pdev);
  4586. if (!drm || !display) {
  4587. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4588. drm, display);
  4589. return -EINVAL;
  4590. }
  4591. if (!display->panel_node && !display->fw)
  4592. return 0;
  4593. if (!display->fw)
  4594. display->name = display->panel_node->name;
  4595. /* defer bind if ext bridge driver is not loaded */
  4596. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4597. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4598. if (!of_drm_find_bridge(
  4599. display->ext_bridge[i].node_of)) {
  4600. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4601. display->ext_bridge[i].node_of->full_name);
  4602. return -EPROBE_DEFER;
  4603. }
  4604. }
  4605. }
  4606. mutex_lock(&display->display_lock);
  4607. rc = dsi_display_validate_split_link(display);
  4608. if (rc) {
  4609. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4610. display->name, rc);
  4611. goto error;
  4612. }
  4613. rc = dsi_display_debugfs_init(display);
  4614. if (rc) {
  4615. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4616. goto error;
  4617. }
  4618. atomic_set(&display->clkrate_change_pending, 0);
  4619. display->cached_clk_rate = 0;
  4620. memset(&info, 0x0, sizeof(info));
  4621. display_for_each_ctrl(i, display) {
  4622. display_ctrl = &display->ctrl[i];
  4623. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4624. if (rc) {
  4625. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4626. display->name, i, rc);
  4627. goto error_ctrl_deinit;
  4628. }
  4629. display_ctrl->ctrl->horiz_index = i;
  4630. rc = dsi_phy_drv_init(display_ctrl->phy);
  4631. if (rc) {
  4632. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4633. display->name, i, rc);
  4634. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4635. goto error_ctrl_deinit;
  4636. }
  4637. display_ctrl->ctrl->dma_cmd_workq = display->dma_cmd_workq;
  4638. memcpy(&info.c_clks[i],
  4639. (&display_ctrl->ctrl->clk_info.core_clks),
  4640. sizeof(struct dsi_core_clk_info));
  4641. memcpy(&info.l_hs_clks[i],
  4642. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4643. sizeof(struct dsi_link_hs_clk_info));
  4644. memcpy(&info.l_lp_clks[i],
  4645. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4646. sizeof(struct dsi_link_lp_clk_info));
  4647. info.c_clks[i].drm = drm;
  4648. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4649. }
  4650. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4651. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4652. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4653. info.post_clkon_cb = dsi_post_clkon_cb;
  4654. info.priv_data = display;
  4655. info.master_ndx = display->clk_master_idx;
  4656. info.dsi_ctrl_count = display->ctrl_count;
  4657. snprintf(info.name, MAX_STRING_LEN,
  4658. "DSI_MNGR-%s", display->name);
  4659. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4660. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4661. rc = PTR_ERR(display->clk_mngr);
  4662. display->clk_mngr = NULL;
  4663. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4664. goto error_ctrl_deinit;
  4665. }
  4666. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4667. if (IS_ERR_OR_NULL(handle)) {
  4668. rc = PTR_ERR(handle);
  4669. DSI_ERR("failed to register %s client, rc = %d\n",
  4670. client1, rc);
  4671. goto error_clk_deinit;
  4672. } else {
  4673. display->dsi_clk_handle = handle;
  4674. }
  4675. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4676. if (IS_ERR_OR_NULL(handle)) {
  4677. rc = PTR_ERR(handle);
  4678. DSI_ERR("failed to register %s client, rc = %d\n",
  4679. client2, rc);
  4680. goto error_clk_client_deinit;
  4681. } else {
  4682. display->mdp_clk_handle = handle;
  4683. }
  4684. clk_cb.priv = display;
  4685. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4686. display_for_each_ctrl(i, display) {
  4687. display_ctrl = &display->ctrl[i];
  4688. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4689. if (rc) {
  4690. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4691. display->name, i, rc);
  4692. goto error_ctrl_deinit;
  4693. }
  4694. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4695. if (rc) {
  4696. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4697. display->name, i, rc);
  4698. goto error_ctrl_deinit;
  4699. }
  4700. }
  4701. dsi_display_update_byte_intf_div(display);
  4702. rc = dsi_display_mipi_host_init(display);
  4703. if (rc) {
  4704. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4705. display->name, rc);
  4706. goto error_ctrl_deinit;
  4707. }
  4708. rc = dsi_panel_drv_init(display->panel, &display->host);
  4709. if (rc) {
  4710. if (rc != -EPROBE_DEFER)
  4711. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4712. display->name, rc);
  4713. goto error_host_deinit;
  4714. }
  4715. DSI_INFO("Successfully bind display panel '%s'\n", display->name);
  4716. display->drm_dev = drm;
  4717. display_for_each_ctrl(i, display) {
  4718. display_ctrl = &display->ctrl[i];
  4719. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4720. continue;
  4721. display_ctrl->ctrl->drm_dev = drm;
  4722. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4723. &display_ctrl->ctrl->clk_freq);
  4724. if (rc) {
  4725. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4726. display->name, rc);
  4727. goto error;
  4728. }
  4729. }
  4730. /* register te irq handler */
  4731. dsi_display_register_te_irq(display);
  4732. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4733. goto error;
  4734. error_host_deinit:
  4735. (void)dsi_display_mipi_host_deinit(display);
  4736. error_clk_client_deinit:
  4737. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4738. error_clk_deinit:
  4739. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4740. error_ctrl_deinit:
  4741. for (i = i - 1; i >= 0; i--) {
  4742. display_ctrl = &display->ctrl[i];
  4743. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4744. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4745. }
  4746. (void)dsi_display_debugfs_deinit(display);
  4747. error:
  4748. mutex_unlock(&display->display_lock);
  4749. return rc;
  4750. }
  4751. /**
  4752. * dsi_display_unbind - unbind dsi from controlling device
  4753. * @dev: Pointer to base of platform device
  4754. * @master: Pointer to container of drm device
  4755. * @data: Pointer to private data
  4756. */
  4757. static void dsi_display_unbind(struct device *dev,
  4758. struct device *master, void *data)
  4759. {
  4760. struct dsi_display_ctrl *display_ctrl;
  4761. struct dsi_display *display;
  4762. struct platform_device *pdev = to_platform_device(dev);
  4763. int i, rc = 0;
  4764. if (!dev || !pdev || !master) {
  4765. DSI_ERR("invalid param(s)\n");
  4766. return;
  4767. }
  4768. display = platform_get_drvdata(pdev);
  4769. if (!display || !display->panel_node) {
  4770. DSI_ERR("invalid display\n");
  4771. return;
  4772. }
  4773. mutex_lock(&display->display_lock);
  4774. rc = dsi_display_mipi_host_deinit(display);
  4775. if (rc)
  4776. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4777. display->name,
  4778. rc);
  4779. display_for_each_ctrl(i, display) {
  4780. display_ctrl = &display->ctrl[i];
  4781. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4782. if (rc)
  4783. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4784. display->name, i, rc);
  4785. display->ctrl->ctrl->dma_cmd_workq = NULL;
  4786. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4787. if (rc)
  4788. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4789. display->name, i, rc);
  4790. }
  4791. atomic_set(&display->clkrate_change_pending, 0);
  4792. (void)dsi_display_debugfs_deinit(display);
  4793. mutex_unlock(&display->display_lock);
  4794. }
  4795. static const struct component_ops dsi_display_comp_ops = {
  4796. .bind = dsi_display_bind,
  4797. .unbind = dsi_display_unbind,
  4798. };
  4799. static struct platform_driver dsi_display_driver = {
  4800. .probe = dsi_display_dev_probe,
  4801. .remove = dsi_display_dev_remove,
  4802. .driver = {
  4803. .name = "msm-dsi-display",
  4804. .of_match_table = dsi_display_dt_match,
  4805. .suppress_bind_attrs = true,
  4806. },
  4807. };
  4808. static int dsi_display_init(struct dsi_display *display)
  4809. {
  4810. int rc = 0;
  4811. struct platform_device *pdev = display->pdev;
  4812. mutex_init(&display->display_lock);
  4813. rc = _dsi_display_dev_init(display);
  4814. if (rc) {
  4815. DSI_ERR("device init failed, rc=%d\n", rc);
  4816. goto end;
  4817. }
  4818. /*
  4819. * Vote on panel regulator is added to make sure panel regulators
  4820. * are ON for cont-splash enabled usecase.
  4821. * This panel regulator vote will be removed only in:
  4822. * 1) device suspend when cont-splash is enabled.
  4823. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4824. * For GKI, adding this vote will make sure that sync_state
  4825. * kernel driver doesn't disable the panel regulators after
  4826. * dsi probe is complete.
  4827. */
  4828. if (display->panel) {
  4829. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4830. true);
  4831. if (rc) {
  4832. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4833. display->panel->name, rc);
  4834. return rc;
  4835. }
  4836. }
  4837. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4838. if (rc)
  4839. DSI_ERR("component add failed, rc=%d\n", rc);
  4840. DSI_DEBUG("component add success: %s\n", display->name);
  4841. end:
  4842. return rc;
  4843. }
  4844. static void dsi_display_firmware_display(const struct firmware *fw,
  4845. void *context)
  4846. {
  4847. struct dsi_display *display = context;
  4848. if (fw) {
  4849. DSI_INFO("reading data from firmware, size=%zd\n",
  4850. fw->size);
  4851. display->fw = fw;
  4852. if (!strcmp(display->display_type, "primary"))
  4853. display->name = "dsi_firmware_display";
  4854. else if (!strcmp(display->display_type, "secondary"))
  4855. display->name = "dsi_firmware_display_secondary";
  4856. } else {
  4857. DSI_INFO("no firmware available, fallback to device node\n");
  4858. }
  4859. if (dsi_display_init(display))
  4860. return;
  4861. DSI_DEBUG("success\n");
  4862. }
  4863. int dsi_display_dev_probe(struct platform_device *pdev)
  4864. {
  4865. struct dsi_display *display = NULL;
  4866. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4867. int rc = 0, index = DSI_PRIMARY;
  4868. bool firm_req = false;
  4869. struct dsi_display_boot_param *boot_disp;
  4870. if (!pdev || !pdev->dev.of_node) {
  4871. DSI_ERR("pdev not found\n");
  4872. rc = -ENODEV;
  4873. goto end;
  4874. }
  4875. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4876. if (!display) {
  4877. rc = -ENOMEM;
  4878. goto end;
  4879. }
  4880. display->dma_cmd_workq = create_singlethread_workqueue(
  4881. "dsi_dma_cmd_workq");
  4882. if (!display->dma_cmd_workq) {
  4883. DSI_ERR("failed to create work queue\n");
  4884. rc = -EINVAL;
  4885. goto end;
  4886. }
  4887. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  4888. if (!mdp_node) {
  4889. DSI_ERR("mdp_node not found\n");
  4890. rc = -ENODEV;
  4891. goto end;
  4892. }
  4893. display->trusted_vm_env = of_property_read_bool(mdp_node,
  4894. "qcom,sde-trusted-vm-env");
  4895. if (display->trusted_vm_env)
  4896. DSI_INFO("Display enabled with trusted vm path\n");
  4897. /* initialize panel id to UINT64_MAX */
  4898. display->panel_id = ~0x0;
  4899. display->display_type = of_get_property(pdev->dev.of_node,
  4900. "label", NULL);
  4901. if (!display->display_type)
  4902. display->display_type = "primary";
  4903. if (!strcmp(display->display_type, "secondary"))
  4904. index = DSI_SECONDARY;
  4905. boot_disp = &boot_displays[index];
  4906. node = pdev->dev.of_node;
  4907. if (boot_disp->boot_disp_en) {
  4908. /* The panel name should be same as UEFI name index */
  4909. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4910. if (!panel_node)
  4911. DSI_WARN("panel_node %s not found\n", boot_disp->name);
  4912. } else {
  4913. panel_node = of_parse_phandle(node,
  4914. "qcom,dsi-default-panel", 0);
  4915. if (!panel_node)
  4916. DSI_WARN("default panel not found\n");
  4917. }
  4918. boot_disp->node = pdev->dev.of_node;
  4919. boot_disp->disp = display;
  4920. display->panel_node = panel_node;
  4921. display->pdev = pdev;
  4922. display->boot_disp = boot_disp;
  4923. dsi_display_parse_cmdline_topology(display, index);
  4924. platform_set_drvdata(pdev, display);
  4925. /* initialize display in firmware callback */
  4926. if (!boot_disp->boot_disp_en &&
  4927. IS_ENABLED(CONFIG_DSI_PARSER) &&
  4928. !display->trusted_vm_env) {
  4929. if (!strcmp(display->display_type, "primary"))
  4930. firm_req = !request_firmware_nowait(
  4931. THIS_MODULE, 1, "dsi_prop",
  4932. &pdev->dev, GFP_KERNEL, display,
  4933. dsi_display_firmware_display);
  4934. else if (!strcmp(display->display_type, "secondary"))
  4935. firm_req = !request_firmware_nowait(
  4936. THIS_MODULE, 1, "dsi_prop_sec",
  4937. &pdev->dev, GFP_KERNEL, display,
  4938. dsi_display_firmware_display);
  4939. }
  4940. if (!firm_req) {
  4941. rc = dsi_display_init(display);
  4942. if (rc)
  4943. goto end;
  4944. }
  4945. return 0;
  4946. end:
  4947. if (display)
  4948. devm_kfree(&pdev->dev, display);
  4949. return rc;
  4950. }
  4951. int dsi_display_dev_remove(struct platform_device *pdev)
  4952. {
  4953. int rc = 0, i = 0;
  4954. struct dsi_display *display;
  4955. struct dsi_display_ctrl *ctrl;
  4956. if (!pdev) {
  4957. DSI_ERR("Invalid device\n");
  4958. return -EINVAL;
  4959. }
  4960. display = platform_get_drvdata(pdev);
  4961. /* decrement ref count */
  4962. of_node_put(display->panel_node);
  4963. if (display->dma_cmd_workq) {
  4964. flush_workqueue(display->dma_cmd_workq);
  4965. destroy_workqueue(display->dma_cmd_workq);
  4966. display->dma_cmd_workq = NULL;
  4967. display_for_each_ctrl(i, display) {
  4968. ctrl = &display->ctrl[i];
  4969. if (!ctrl->ctrl)
  4970. continue;
  4971. ctrl->ctrl->dma_cmd_workq = NULL;
  4972. }
  4973. }
  4974. (void)_dsi_display_dev_deinit(display);
  4975. platform_set_drvdata(pdev, NULL);
  4976. devm_kfree(&pdev->dev, display);
  4977. return rc;
  4978. }
  4979. int dsi_display_get_num_of_displays(void)
  4980. {
  4981. int i, count = 0;
  4982. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  4983. struct dsi_display *display = boot_displays[i].disp;
  4984. if ((display && display->panel_node) ||
  4985. (display && display->fw))
  4986. count++;
  4987. }
  4988. return count;
  4989. }
  4990. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  4991. {
  4992. int index = 0, count = 0;
  4993. if (!display_array || !max_display_count) {
  4994. DSI_ERR("invalid params\n");
  4995. return 0;
  4996. }
  4997. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  4998. struct dsi_display *display = boot_displays[index].disp;
  4999. if ((display && display->panel_node) ||
  5000. (display && display->fw))
  5001. display_array[count++] = display;
  5002. }
  5003. return count;
  5004. }
  5005. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  5006. {
  5007. if (!display)
  5008. return;
  5009. mutex_lock(&display->display_lock);
  5010. display->is_active = is_active;
  5011. mutex_unlock(&display->display_lock);
  5012. }
  5013. int dsi_display_drm_bridge_init(struct dsi_display *display,
  5014. struct drm_encoder *enc)
  5015. {
  5016. int rc = 0;
  5017. struct dsi_bridge *bridge;
  5018. struct msm_drm_private *priv = NULL;
  5019. if (!display || !display->drm_dev || !enc) {
  5020. DSI_ERR("invalid param(s)\n");
  5021. return -EINVAL;
  5022. }
  5023. mutex_lock(&display->display_lock);
  5024. priv = display->drm_dev->dev_private;
  5025. if (!priv) {
  5026. DSI_ERR("Private data is not present\n");
  5027. rc = -EINVAL;
  5028. goto error;
  5029. }
  5030. if (display->bridge) {
  5031. DSI_ERR("display is already initialize\n");
  5032. goto error;
  5033. }
  5034. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  5035. if (IS_ERR_OR_NULL(bridge)) {
  5036. rc = PTR_ERR(bridge);
  5037. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  5038. goto error;
  5039. }
  5040. display->bridge = bridge;
  5041. priv->bridges[priv->num_bridges++] = &bridge->base;
  5042. error:
  5043. mutex_unlock(&display->display_lock);
  5044. return rc;
  5045. }
  5046. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  5047. {
  5048. int rc = 0;
  5049. if (!display) {
  5050. DSI_ERR("Invalid params\n");
  5051. return -EINVAL;
  5052. }
  5053. mutex_lock(&display->display_lock);
  5054. dsi_drm_bridge_cleanup(display->bridge);
  5055. display->bridge = NULL;
  5056. mutex_unlock(&display->display_lock);
  5057. return rc;
  5058. }
  5059. /* Hook functions to call external connector, pointer validation is
  5060. * done in dsi_display_drm_ext_bridge_init.
  5061. */
  5062. static enum drm_connector_status dsi_display_drm_ext_detect(
  5063. struct drm_connector *connector,
  5064. bool force,
  5065. void *disp)
  5066. {
  5067. struct dsi_display *display = disp;
  5068. return display->ext_conn->funcs->detect(display->ext_conn, force);
  5069. }
  5070. static int dsi_display_drm_ext_get_modes(
  5071. struct drm_connector *connector, void *disp,
  5072. const struct msm_resource_caps_info *avail_res)
  5073. {
  5074. struct dsi_display *display = disp;
  5075. struct drm_display_mode *pmode, *pt;
  5076. int count;
  5077. /* if there are modes defined in panel, ignore external modes */
  5078. if (display->panel->num_timing_nodes)
  5079. return dsi_connector_get_modes(connector, disp, avail_res);
  5080. count = display->ext_conn->helper_private->get_modes(
  5081. display->ext_conn);
  5082. list_for_each_entry_safe(pmode, pt,
  5083. &display->ext_conn->probed_modes, head) {
  5084. list_move_tail(&pmode->head, &connector->probed_modes);
  5085. }
  5086. connector->display_info = display->ext_conn->display_info;
  5087. return count;
  5088. }
  5089. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  5090. struct drm_connector *connector,
  5091. struct drm_display_mode *mode,
  5092. void *disp, const struct msm_resource_caps_info *avail_res)
  5093. {
  5094. struct dsi_display *display = disp;
  5095. enum drm_mode_status status;
  5096. /* always do internal mode_valid check */
  5097. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  5098. if (status != MODE_OK)
  5099. return status;
  5100. return display->ext_conn->helper_private->mode_valid(
  5101. display->ext_conn, mode);
  5102. }
  5103. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  5104. void *disp,
  5105. struct drm_atomic_state *state)
  5106. {
  5107. struct dsi_display *display = disp;
  5108. struct drm_connector_state *c_state;
  5109. c_state = drm_atomic_get_new_connector_state(state, connector);
  5110. return display->ext_conn->helper_private->atomic_check(
  5111. display->ext_conn, state);
  5112. }
  5113. static int dsi_display_ext_get_info(struct drm_connector *connector,
  5114. struct msm_display_info *info, void *disp)
  5115. {
  5116. struct dsi_display *display;
  5117. int i;
  5118. if (!info || !disp) {
  5119. DSI_ERR("invalid params\n");
  5120. return -EINVAL;
  5121. }
  5122. display = disp;
  5123. if (!display->panel) {
  5124. DSI_ERR("invalid display panel\n");
  5125. return -EINVAL;
  5126. }
  5127. mutex_lock(&display->display_lock);
  5128. memset(info, 0, sizeof(struct msm_display_info));
  5129. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5130. info->num_of_h_tiles = display->ctrl_count;
  5131. for (i = 0; i < info->num_of_h_tiles; i++)
  5132. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5133. info->is_connected = connector->status != connector_status_disconnected;
  5134. if (!strcmp(display->display_type, "primary"))
  5135. info->display_type = SDE_CONNECTOR_PRIMARY;
  5136. else if (!strcmp(display->display_type, "secondary"))
  5137. info->display_type = SDE_CONNECTOR_SECONDARY;
  5138. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5139. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5140. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5141. mutex_unlock(&display->display_lock);
  5142. return 0;
  5143. }
  5144. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5145. const struct drm_display_mode *drm_mode,
  5146. struct msm_mode_info *mode_info,
  5147. void *display, const struct msm_resource_caps_info *avail_res)
  5148. {
  5149. struct msm_display_topology *topology;
  5150. if (!drm_mode || !mode_info ||
  5151. !avail_res || !avail_res->max_mixer_width)
  5152. return -EINVAL;
  5153. memset(mode_info, 0, sizeof(*mode_info));
  5154. mode_info->frame_rate = drm_mode->vrefresh;
  5155. mode_info->vtotal = drm_mode->vtotal;
  5156. topology = &mode_info->topology;
  5157. topology->num_lm = (avail_res->max_mixer_width
  5158. <= drm_mode->hdisplay) ? 2 : 1;
  5159. topology->num_enc = 0;
  5160. topology->num_intf = topology->num_lm;
  5161. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5162. return 0;
  5163. }
  5164. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5165. struct drm_bridge *bridge)
  5166. {
  5167. struct msm_drm_private *priv;
  5168. struct sde_kms *sde_kms;
  5169. struct drm_connector *conn;
  5170. struct drm_connector_list_iter conn_iter;
  5171. struct sde_connector *sde_conn;
  5172. struct dsi_display *display;
  5173. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5174. int i;
  5175. if (!bridge || !bridge->encoder) {
  5176. SDE_ERROR("invalid argument\n");
  5177. return NULL;
  5178. }
  5179. priv = bridge->dev->dev_private;
  5180. sde_kms = to_sde_kms(priv->kms);
  5181. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5182. drm_for_each_connector_iter(conn, &conn_iter) {
  5183. sde_conn = to_sde_connector(conn);
  5184. if (sde_conn->encoder == bridge->encoder) {
  5185. display = sde_conn->display;
  5186. display_for_each_ctrl(i, display) {
  5187. if (display->ext_bridge[i].bridge == bridge) {
  5188. dsi_bridge = &display->ext_bridge[i];
  5189. break;
  5190. }
  5191. }
  5192. }
  5193. }
  5194. drm_connector_list_iter_end(&conn_iter);
  5195. return dsi_bridge;
  5196. }
  5197. static void dsi_display_drm_ext_adjust_timing(
  5198. const struct dsi_display *display,
  5199. struct drm_display_mode *mode)
  5200. {
  5201. mode->hdisplay /= display->ctrl_count;
  5202. mode->hsync_start /= display->ctrl_count;
  5203. mode->hsync_end /= display->ctrl_count;
  5204. mode->htotal /= display->ctrl_count;
  5205. mode->hskew /= display->ctrl_count;
  5206. mode->clock /= display->ctrl_count;
  5207. }
  5208. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5209. struct drm_bridge *bridge,
  5210. const struct drm_display_info *info,
  5211. const struct drm_display_mode *mode)
  5212. {
  5213. struct dsi_display_ext_bridge *ext_bridge;
  5214. struct drm_display_mode tmp;
  5215. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5216. if (!ext_bridge)
  5217. return MODE_ERROR;
  5218. tmp = *mode;
  5219. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5220. return ext_bridge->orig_funcs->mode_valid(bridge, info, &tmp);
  5221. }
  5222. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5223. struct drm_bridge *bridge,
  5224. const struct drm_display_mode *mode,
  5225. struct drm_display_mode *adjusted_mode)
  5226. {
  5227. struct dsi_display_ext_bridge *ext_bridge;
  5228. struct drm_display_mode tmp;
  5229. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5230. if (!ext_bridge)
  5231. return false;
  5232. tmp = *mode;
  5233. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5234. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5235. }
  5236. static void dsi_display_drm_ext_bridge_mode_set(
  5237. struct drm_bridge *bridge,
  5238. const struct drm_display_mode *mode,
  5239. const struct drm_display_mode *adjusted_mode)
  5240. {
  5241. struct dsi_display_ext_bridge *ext_bridge;
  5242. struct drm_display_mode tmp;
  5243. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5244. if (!ext_bridge)
  5245. return;
  5246. tmp = *mode;
  5247. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5248. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5249. }
  5250. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5251. struct mipi_dsi_device *dsi)
  5252. {
  5253. struct dsi_display *display = to_dsi_display(host);
  5254. struct dsi_panel *panel;
  5255. if (!host || !dsi || !display->panel) {
  5256. DSI_ERR("Invalid param\n");
  5257. return -EINVAL;
  5258. }
  5259. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5260. dsi->name, dsi->channel, dsi->lanes,
  5261. dsi->format, dsi->mode_flags);
  5262. panel = display->panel;
  5263. panel->host_config.data_lanes = 0;
  5264. if (dsi->lanes > 0)
  5265. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5266. if (dsi->lanes > 1)
  5267. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5268. if (dsi->lanes > 2)
  5269. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5270. if (dsi->lanes > 3)
  5271. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5272. switch (dsi->format) {
  5273. case MIPI_DSI_FMT_RGB888:
  5274. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5275. break;
  5276. case MIPI_DSI_FMT_RGB666:
  5277. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5278. break;
  5279. case MIPI_DSI_FMT_RGB666_PACKED:
  5280. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5281. break;
  5282. case MIPI_DSI_FMT_RGB565:
  5283. default:
  5284. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5285. break;
  5286. }
  5287. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5288. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5289. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5290. panel->video_config.traffic_mode =
  5291. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5292. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5293. panel->video_config.traffic_mode =
  5294. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5295. else
  5296. panel->video_config.traffic_mode =
  5297. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5298. panel->video_config.hsa_lp11_en =
  5299. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5300. panel->video_config.hbp_lp11_en =
  5301. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5302. panel->video_config.hfp_lp11_en =
  5303. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5304. panel->video_config.pulse_mode_hsa_he =
  5305. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5306. panel->video_config.bllp_lp11_en =
  5307. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BLLP;
  5308. panel->video_config.eof_bllp_lp11_en =
  5309. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_EOF_BLLP;
  5310. } else {
  5311. panel->panel_mode = DSI_OP_CMD_MODE;
  5312. DSI_ERR("command mode not supported by ext bridge\n");
  5313. return -ENOTSUPP;
  5314. }
  5315. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5316. return 0;
  5317. }
  5318. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5319. .attach = dsi_host_ext_attach,
  5320. .detach = dsi_host_detach,
  5321. .transfer = dsi_host_transfer,
  5322. };
  5323. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5324. {
  5325. if (!display || !display->panel) {
  5326. pr_err("invalid param(s)\n");
  5327. return NULL;
  5328. }
  5329. return &display->panel->drm_panel;
  5330. }
  5331. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5332. struct drm_encoder *encoder, struct drm_connector *connector)
  5333. {
  5334. struct drm_device *drm;
  5335. struct drm_bridge *bridge;
  5336. struct drm_bridge *ext_bridge;
  5337. struct drm_connector *ext_conn;
  5338. struct sde_connector *sde_conn;
  5339. struct drm_bridge *prev_bridge;
  5340. int rc = 0, i;
  5341. if (!display || !encoder || !connector)
  5342. return -EINVAL;
  5343. drm = encoder->dev;
  5344. bridge = drm_bridge_chain_get_first_bridge(encoder);
  5345. sde_conn = to_sde_connector(connector);
  5346. prev_bridge = bridge;
  5347. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5348. return 0;
  5349. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5350. struct dsi_display_ext_bridge *ext_bridge_info =
  5351. &display->ext_bridge[i];
  5352. struct drm_encoder *c_encoder;
  5353. /* return if ext bridge is already initialized */
  5354. if (ext_bridge_info->bridge)
  5355. return 0;
  5356. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5357. if (IS_ERR_OR_NULL(ext_bridge)) {
  5358. rc = PTR_ERR(ext_bridge);
  5359. DSI_ERR("failed to find ext bridge\n");
  5360. goto error;
  5361. }
  5362. /* override functions for mode adjustment */
  5363. if (display->ext_bridge_cnt > 1) {
  5364. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5365. if (ext_bridge->funcs->mode_fixup)
  5366. ext_bridge_info->bridge_funcs.mode_fixup =
  5367. dsi_display_drm_ext_bridge_mode_fixup;
  5368. if (ext_bridge->funcs->mode_valid)
  5369. ext_bridge_info->bridge_funcs.mode_valid =
  5370. dsi_display_drm_ext_bridge_mode_valid;
  5371. if (ext_bridge->funcs->mode_set)
  5372. ext_bridge_info->bridge_funcs.mode_set =
  5373. dsi_display_drm_ext_bridge_mode_set;
  5374. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5375. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5376. }
  5377. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge, 0);
  5378. if (rc) {
  5379. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5380. display->name, rc);
  5381. goto error;
  5382. }
  5383. ext_bridge_info->display = display;
  5384. ext_bridge_info->bridge = ext_bridge;
  5385. prev_bridge = ext_bridge;
  5386. /* ext bridge will init its own connector during attach,
  5387. * we need to extract it out of the connector list
  5388. */
  5389. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5390. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5391. struct drm_connector, head);
  5392. drm_connector_for_each_possible_encoder(ext_conn, c_encoder)
  5393. break;
  5394. if (!c_encoder) {
  5395. DSI_ERR("failed to get encoder\n");
  5396. rc = PTR_ERR(c_encoder);
  5397. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5398. goto error;
  5399. }
  5400. if (ext_conn && ext_conn != connector &&
  5401. c_encoder->base.id == bridge->encoder->base.id) {
  5402. list_del_init(&ext_conn->head);
  5403. display->ext_conn = ext_conn;
  5404. }
  5405. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5406. /* if there is no valid external connector created, or in split
  5407. * mode, default setting is used from panel defined in DT file.
  5408. */
  5409. if (!display->ext_conn ||
  5410. !display->ext_conn->funcs ||
  5411. !display->ext_conn->helper_private ||
  5412. display->ext_bridge_cnt > 1) {
  5413. display->ext_conn = NULL;
  5414. continue;
  5415. }
  5416. /* otherwise, hook up the functions to use external connector */
  5417. if (display->ext_conn->funcs->detect)
  5418. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5419. if (display->ext_conn->helper_private->get_modes)
  5420. sde_conn->ops.get_modes =
  5421. dsi_display_drm_ext_get_modes;
  5422. if (display->ext_conn->helper_private->mode_valid)
  5423. sde_conn->ops.mode_valid =
  5424. dsi_display_drm_ext_mode_valid;
  5425. if (display->ext_conn->helper_private->atomic_check)
  5426. sde_conn->ops.atomic_check =
  5427. dsi_display_drm_ext_atomic_check;
  5428. sde_conn->ops.get_info =
  5429. dsi_display_ext_get_info;
  5430. sde_conn->ops.get_mode_info =
  5431. dsi_display_ext_get_mode_info;
  5432. /* add support to attach/detach */
  5433. display->host.ops = &dsi_host_ext_ops;
  5434. }
  5435. return 0;
  5436. error:
  5437. return rc;
  5438. }
  5439. int dsi_display_get_info(struct drm_connector *connector,
  5440. struct msm_display_info *info, void *disp)
  5441. {
  5442. struct dsi_display *display;
  5443. struct dsi_panel_phy_props phy_props;
  5444. struct dsi_host_common_cfg *host;
  5445. int i, rc;
  5446. if (!info || !disp) {
  5447. DSI_ERR("invalid params\n");
  5448. return -EINVAL;
  5449. }
  5450. display = disp;
  5451. if (!display->panel) {
  5452. DSI_ERR("invalid display panel\n");
  5453. return -EINVAL;
  5454. }
  5455. mutex_lock(&display->display_lock);
  5456. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5457. if (rc) {
  5458. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5459. display->name, rc);
  5460. goto error;
  5461. }
  5462. memset(info, 0, sizeof(struct msm_display_info));
  5463. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5464. info->num_of_h_tiles = display->ctrl_count;
  5465. for (i = 0; i < info->num_of_h_tiles; i++)
  5466. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5467. info->is_connected = display->is_active;
  5468. if (!strcmp(display->display_type, "primary"))
  5469. info->display_type = SDE_CONNECTOR_PRIMARY;
  5470. else if (!strcmp(display->display_type, "secondary"))
  5471. info->display_type = SDE_CONNECTOR_SECONDARY;
  5472. info->width_mm = phy_props.panel_width_mm;
  5473. info->height_mm = phy_props.panel_height_mm;
  5474. info->max_width = 1920;
  5475. info->max_height = 1080;
  5476. info->qsync_min_fps =
  5477. display->panel->qsync_caps.qsync_min_fps;
  5478. info->has_qsync_min_fps_list =
  5479. (display->panel->qsync_caps.qsync_min_fps_list_len > 0) ?
  5480. true : false;
  5481. info->poms_align_vsync = display->panel->poms_align_vsync;
  5482. switch (display->panel->panel_mode) {
  5483. case DSI_OP_VIDEO_MODE:
  5484. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5485. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5486. if (display->panel->panel_mode_switch_enabled)
  5487. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5488. break;
  5489. case DSI_OP_CMD_MODE:
  5490. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5491. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5492. if (display->panel->panel_mode_switch_enabled)
  5493. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5494. info->is_te_using_watchdog_timer =
  5495. display->panel->te_using_watchdog_timer |
  5496. display->sw_te_using_wd;
  5497. break;
  5498. default:
  5499. DSI_ERR("unknwown dsi panel mode %d\n",
  5500. display->panel->panel_mode);
  5501. break;
  5502. }
  5503. if (display->panel->esd_config.esd_enabled &&
  5504. !display->sw_te_using_wd)
  5505. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5506. info->te_source = display->te_source;
  5507. host = &display->panel->host_config;
  5508. if (host->split_link.split_link_enabled)
  5509. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5510. info->dsc_count = display->panel->dsc_count;
  5511. info->lm_count = display->panel->lm_count;
  5512. error:
  5513. mutex_unlock(&display->display_lock);
  5514. return rc;
  5515. }
  5516. int dsi_display_get_mode_count(struct dsi_display *display,
  5517. u32 *count)
  5518. {
  5519. if (!display || !display->panel) {
  5520. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5521. display ? display->panel != NULL : 0);
  5522. return -EINVAL;
  5523. }
  5524. mutex_lock(&display->display_lock);
  5525. *count = display->panel->num_display_modes;
  5526. mutex_unlock(&display->display_lock);
  5527. return 0;
  5528. }
  5529. void dsi_display_adjust_mode_timing(struct dsi_display *display,
  5530. struct dsi_display_mode *dsi_mode,
  5531. int lanes, int bpp)
  5532. {
  5533. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5534. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5535. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  5536. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5537. /* Constant FPS is not supported on command mode */
  5538. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  5539. return;
  5540. if (!dyn_clk_caps->maintain_const_fps)
  5541. return;
  5542. /*
  5543. * When there is a dynamic clock switch, there is small change
  5544. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5545. * is adjusted. It has been assumed that the refined porch values
  5546. * are supported by the panel. This logic can be enhanced further
  5547. * in future by taking min/max porches supported by the panel.
  5548. */
  5549. switch (dyn_clk_caps->type) {
  5550. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5551. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5552. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5553. do_div(old_htotal, display->ctrl_count);
  5554. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5555. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5556. if (dsi_display_is_type_cphy(display)) {
  5557. new_htotal = new_htotal * bits_per_symbol;
  5558. div = div * num_of_symbols;
  5559. }
  5560. do_div(new_htotal, div);
  5561. if (old_htotal > new_htotal)
  5562. dsi_mode->timing.h_front_porch -=
  5563. ((old_htotal - new_htotal) * display->ctrl_count);
  5564. else
  5565. dsi_mode->timing.h_front_porch +=
  5566. ((new_htotal - old_htotal) * display->ctrl_count);
  5567. break;
  5568. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5569. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5570. do_div(htotal, display->ctrl_count);
  5571. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5572. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5573. if (dsi_display_is_type_cphy(display)) {
  5574. new_vtotal = new_vtotal * bits_per_symbol;
  5575. div = div * num_of_symbols;
  5576. }
  5577. do_div(new_vtotal, div);
  5578. dsi_mode->timing.v_front_porch = new_vtotal -
  5579. dsi_mode->timing.v_back_porch -
  5580. dsi_mode->timing.v_sync_width -
  5581. dsi_mode->timing.v_active;
  5582. break;
  5583. default:
  5584. break;
  5585. }
  5586. }
  5587. static void _dsi_display_populate_bit_clks(struct dsi_display *display,
  5588. int start, int end, u32 *mode_idx)
  5589. {
  5590. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5591. struct dsi_display_mode *src, *dst;
  5592. struct dsi_host_common_cfg *cfg;
  5593. struct dsi_display_mode_priv_info *priv_info;
  5594. int i, j, total_modes, bpp, lanes = 0;
  5595. size_t size = 0;
  5596. if (!display || !mode_idx)
  5597. return;
  5598. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5599. if (!dyn_clk_caps->dyn_clk_support)
  5600. return;
  5601. cfg = &(display->panel->host_config);
  5602. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5603. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5604. lanes++;
  5605. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5606. lanes++;
  5607. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5608. lanes++;
  5609. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5610. lanes++;
  5611. total_modes = display->panel->num_display_modes;
  5612. for (i = start; i < end; i++) {
  5613. src = &display->modes[i];
  5614. if (!src)
  5615. return;
  5616. /*
  5617. * TODO: currently setting the first bit rate in
  5618. * the list as preferred rate. But ideally should
  5619. * be based on user or device tree preferrence.
  5620. */
  5621. src->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[0];
  5622. dsi_display_adjust_mode_timing(display, src, lanes, bpp);
  5623. src->pixel_clk_khz =
  5624. div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5625. src->pixel_clk_khz /= 1000;
  5626. src->pixel_clk_khz *= display->ctrl_count;
  5627. }
  5628. for (i = 1; i < dyn_clk_caps->bit_clk_list_len; i++) {
  5629. if (*mode_idx >= total_modes)
  5630. return;
  5631. for (j = start; j < end; j++) {
  5632. src = &display->modes[j];
  5633. dst = &display->modes[*mode_idx];
  5634. if (!src || !dst) {
  5635. DSI_ERR("invalid mode index\n");
  5636. return;
  5637. }
  5638. memcpy(dst, src, sizeof(struct dsi_display_mode));
  5639. size = sizeof(struct dsi_display_mode_priv_info);
  5640. priv_info = kzalloc(size, GFP_KERNEL);
  5641. dst->priv_info = priv_info;
  5642. if (dst->priv_info)
  5643. memcpy(dst->priv_info, src->priv_info, size);
  5644. dst->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[i];
  5645. dsi_display_adjust_mode_timing(display, dst, lanes,
  5646. bpp);
  5647. dst->pixel_clk_khz =
  5648. div_u64(dst->timing.clk_rate_hz * lanes, bpp);
  5649. dst->pixel_clk_khz /= 1000;
  5650. dst->pixel_clk_khz *= display->ctrl_count;
  5651. (*mode_idx)++;
  5652. }
  5653. }
  5654. }
  5655. void dsi_display_put_mode(struct dsi_display *display,
  5656. struct dsi_display_mode *mode)
  5657. {
  5658. dsi_panel_put_mode(mode);
  5659. }
  5660. int dsi_display_get_modes(struct dsi_display *display,
  5661. struct dsi_display_mode **out_modes)
  5662. {
  5663. struct dsi_dfps_capabilities dfps_caps;
  5664. struct dsi_display_ctrl *ctrl;
  5665. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5666. bool is_split_link, is_cmd_mode;
  5667. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5668. u32 sublinks_count, mode_idx, array_idx = 0;
  5669. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5670. int i, start, end, rc = -EINVAL;
  5671. if (!display || !out_modes) {
  5672. DSI_ERR("Invalid params\n");
  5673. return -EINVAL;
  5674. }
  5675. *out_modes = NULL;
  5676. ctrl = &display->ctrl[0];
  5677. mutex_lock(&display->display_lock);
  5678. if (display->modes)
  5679. goto exit;
  5680. display_mode_count = display->panel->num_display_modes;
  5681. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5682. GFP_KERNEL);
  5683. if (!display->modes) {
  5684. rc = -ENOMEM;
  5685. goto error;
  5686. }
  5687. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5688. if (rc) {
  5689. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5690. display->name);
  5691. goto error;
  5692. }
  5693. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5694. timing_mode_count = display->panel->num_timing_nodes;
  5695. /* Validate command line timing */
  5696. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5697. (display->cmdline_timing >= timing_mode_count))
  5698. display->cmdline_timing = NO_OVERRIDE;
  5699. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5700. struct dsi_display_mode display_mode;
  5701. int topology_override = NO_OVERRIDE;
  5702. bool is_preferred = false;
  5703. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5704. if (display->cmdline_timing == mode_idx) {
  5705. topology_override = display->cmdline_topology;
  5706. is_preferred = true;
  5707. }
  5708. memset(&display_mode, 0, sizeof(display_mode));
  5709. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5710. &display_mode,
  5711. topology_override);
  5712. if (rc) {
  5713. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5714. display->name, mode_idx);
  5715. goto error;
  5716. }
  5717. is_cmd_mode = (display_mode.panel_mode == DSI_OP_CMD_MODE);
  5718. /* Setup widebus support */
  5719. display_mode.priv_info->widebus_support =
  5720. ctrl->ctrl->hw.widebus_support;
  5721. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5722. is_cmd_mode) ? 1 : dfps_caps.dfps_list_len);
  5723. /* Calculate dsi frame transfer time */
  5724. if (is_cmd_mode) {
  5725. dsi_panel_calc_dsi_transfer_time(
  5726. &display->panel->host_config,
  5727. &display_mode, frame_threshold_us);
  5728. display_mode.priv_info->dsi_transfer_time_us =
  5729. display_mode.timing.dsi_transfer_time_us;
  5730. display_mode.priv_info->min_dsi_clk_hz =
  5731. display_mode.timing.min_dsi_clk_hz;
  5732. display_mode.priv_info->mdp_transfer_time_us =
  5733. display_mode.timing.mdp_transfer_time_us;
  5734. }
  5735. is_split_link = host->split_link.split_link_enabled;
  5736. sublinks_count = host->split_link.num_sublinks;
  5737. if (is_split_link && sublinks_count > 1) {
  5738. display_mode.timing.h_active *= sublinks_count;
  5739. display_mode.timing.h_front_porch *= sublinks_count;
  5740. display_mode.timing.h_sync_width *= sublinks_count;
  5741. display_mode.timing.h_back_porch *= sublinks_count;
  5742. display_mode.timing.h_skew *= sublinks_count;
  5743. display_mode.pixel_clk_khz *= sublinks_count;
  5744. } else {
  5745. display_mode.timing.h_active *= display->ctrl_count;
  5746. display_mode.timing.h_front_porch *=
  5747. display->ctrl_count;
  5748. display_mode.timing.h_sync_width *=
  5749. display->ctrl_count;
  5750. display_mode.timing.h_back_porch *=
  5751. display->ctrl_count;
  5752. display_mode.timing.h_skew *= display->ctrl_count;
  5753. display_mode.pixel_clk_khz *= display->ctrl_count;
  5754. }
  5755. start = array_idx;
  5756. for (i = 0; i < num_dfps_rates; i++) {
  5757. struct dsi_display_mode *sub_mode =
  5758. &display->modes[array_idx];
  5759. u32 curr_refresh_rate;
  5760. if (!sub_mode) {
  5761. DSI_ERR("invalid mode data\n");
  5762. rc = -EFAULT;
  5763. goto error;
  5764. }
  5765. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5766. array_idx++;
  5767. if (!dfps_caps.dfps_support || is_cmd_mode)
  5768. continue;
  5769. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5770. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5771. dsi_display_get_dfps_timing(display, sub_mode,
  5772. curr_refresh_rate);
  5773. }
  5774. end = array_idx;
  5775. /*
  5776. * if POMS is enabled and boot up mode is video mode,
  5777. * skip bit clk rates update for command mode,
  5778. * else if dynamic clk switch is supported then update all
  5779. * the bit clk rates.
  5780. */
  5781. if (is_cmd_mode &&
  5782. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  5783. continue;
  5784. _dsi_display_populate_bit_clks(display, start, end, &array_idx);
  5785. if (is_preferred) {
  5786. /* Set first timing sub mode as preferred mode */
  5787. display->modes[start].is_preferred = true;
  5788. }
  5789. }
  5790. exit:
  5791. *out_modes = display->modes;
  5792. rc = 0;
  5793. error:
  5794. if (rc)
  5795. kfree(display->modes);
  5796. mutex_unlock(&display->display_lock);
  5797. return rc;
  5798. }
  5799. int dsi_display_get_panel_vfp(void *dsi_display,
  5800. int h_active, int v_active)
  5801. {
  5802. int i, rc = 0;
  5803. u32 count, refresh_rate = 0;
  5804. struct dsi_dfps_capabilities dfps_caps;
  5805. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5806. struct dsi_host_common_cfg *host;
  5807. if (!display || !display->panel)
  5808. return -EINVAL;
  5809. mutex_lock(&display->display_lock);
  5810. count = display->panel->num_display_modes;
  5811. if (display->panel->cur_mode)
  5812. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5813. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5814. if (dfps_caps.dfps_support)
  5815. refresh_rate = dfps_caps.max_refresh_rate;
  5816. if (!refresh_rate) {
  5817. mutex_unlock(&display->display_lock);
  5818. DSI_ERR("Null Refresh Rate\n");
  5819. return -EINVAL;
  5820. }
  5821. host = &display->panel->host_config;
  5822. if (host->split_link.split_link_enabled)
  5823. h_active *= host->split_link.num_sublinks;
  5824. else
  5825. h_active *= display->ctrl_count;
  5826. for (i = 0; i < count; i++) {
  5827. struct dsi_display_mode *m = &display->modes[i];
  5828. if (m && v_active == m->timing.v_active &&
  5829. h_active == m->timing.h_active &&
  5830. refresh_rate == m->timing.refresh_rate) {
  5831. rc = m->timing.v_front_porch;
  5832. break;
  5833. }
  5834. }
  5835. mutex_unlock(&display->display_lock);
  5836. return rc;
  5837. }
  5838. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5839. {
  5840. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5841. u32 count, i;
  5842. int rc = 0;
  5843. *num_lm = 0;
  5844. mutex_lock(&display->display_lock);
  5845. count = display->panel->num_display_modes;
  5846. mutex_unlock(&display->display_lock);
  5847. if (!display->modes) {
  5848. struct dsi_display_mode *m;
  5849. rc = dsi_display_get_modes(display, &m);
  5850. if (rc)
  5851. return rc;
  5852. }
  5853. mutex_lock(&display->display_lock);
  5854. for (i = 0; i < count; i++) {
  5855. struct dsi_display_mode *m = &display->modes[i];
  5856. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5857. }
  5858. mutex_unlock(&display->display_lock);
  5859. return rc;
  5860. }
  5861. int dsi_display_get_qsync_min_fps(void *display_dsi, u32 mode_fps)
  5862. {
  5863. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5864. struct dsi_panel *panel;
  5865. u32 i;
  5866. if (display == NULL || display->panel == NULL)
  5867. return -EINVAL;
  5868. panel = display->panel;
  5869. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5870. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5871. return panel->qsync_caps.qsync_min_fps_list[i];
  5872. }
  5873. SDE_EVT32(mode_fps);
  5874. DSI_DEBUG("Invalid mode_fps %d\n", mode_fps);
  5875. return -EINVAL;
  5876. }
  5877. int dsi_display_find_mode(struct dsi_display *display,
  5878. const struct dsi_display_mode *cmp,
  5879. struct dsi_display_mode **out_mode)
  5880. {
  5881. u32 count, i;
  5882. int rc;
  5883. if (!display || !out_mode)
  5884. return -EINVAL;
  5885. *out_mode = NULL;
  5886. mutex_lock(&display->display_lock);
  5887. count = display->panel->num_display_modes;
  5888. mutex_unlock(&display->display_lock);
  5889. if (!display->modes) {
  5890. struct dsi_display_mode *m;
  5891. rc = dsi_display_get_modes(display, &m);
  5892. if (rc)
  5893. return rc;
  5894. }
  5895. mutex_lock(&display->display_lock);
  5896. for (i = 0; i < count; i++) {
  5897. struct dsi_display_mode *m = &display->modes[i];
  5898. if (cmp->timing.v_active == m->timing.v_active &&
  5899. cmp->timing.h_active == m->timing.h_active &&
  5900. cmp->timing.refresh_rate == m->timing.refresh_rate &&
  5901. cmp->panel_mode == m->panel_mode &&
  5902. cmp->pixel_clk_khz == m->pixel_clk_khz) {
  5903. *out_mode = m;
  5904. rc = 0;
  5905. break;
  5906. }
  5907. }
  5908. mutex_unlock(&display->display_lock);
  5909. if (!*out_mode) {
  5910. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  5911. display->name, cmp->timing.v_active,
  5912. cmp->timing.h_active, cmp->timing.refresh_rate,
  5913. cmp->pixel_clk_khz);
  5914. rc = -ENOENT;
  5915. }
  5916. return rc;
  5917. }
  5918. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  5919. struct dsi_display_mode *adj)
  5920. {
  5921. /*
  5922. * If there is a change in the hfp or vfp of the current and adjoining
  5923. * mode,then either it is a dfps mode switch or dynamic clk change with
  5924. * constant fps.
  5925. */
  5926. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  5927. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  5928. return true;
  5929. else
  5930. return false;
  5931. }
  5932. /**
  5933. * dsi_display_validate_mode_change() - Validate mode change case.
  5934. * @display: DSI display handle.
  5935. * @cur_mode: Current mode.
  5936. * @adj_mode: Mode to be set.
  5937. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  5938. * is change in hfp or vfp but vactive and hactive are same.
  5939. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  5940. * is change in clk but vactive and hactive are same.
  5941. * Return: error code.
  5942. */
  5943. int dsi_display_validate_mode_change(struct dsi_display *display,
  5944. struct dsi_display_mode *cur_mode,
  5945. struct dsi_display_mode *adj_mode)
  5946. {
  5947. int rc = 0;
  5948. struct dsi_dfps_capabilities dfps_caps;
  5949. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5950. if (!display || !adj_mode) {
  5951. DSI_ERR("Invalid params\n");
  5952. return -EINVAL;
  5953. }
  5954. if (!display->panel || !display->panel->cur_mode) {
  5955. DSI_DEBUG("Current panel mode not set\n");
  5956. return rc;
  5957. }
  5958. mutex_lock(&display->display_lock);
  5959. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5960. if ((cur_mode->timing.v_active == adj_mode->timing.v_active) &&
  5961. (cur_mode->timing.h_active == adj_mode->timing.h_active) &&
  5962. (cur_mode->panel_mode == adj_mode->panel_mode)) {
  5963. /* dfps and dynamic clock with const fps use case */
  5964. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  5965. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5966. if (dfps_caps.dfps_support ||
  5967. dyn_clk_caps->maintain_const_fps) {
  5968. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  5969. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  5970. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1,
  5971. cur_mode->timing.refresh_rate,
  5972. adj_mode->timing.refresh_rate,
  5973. cur_mode->timing.h_front_porch,
  5974. adj_mode->timing.h_front_porch,
  5975. cur_mode->timing.v_front_porch,
  5976. adj_mode->timing.v_front_porch);
  5977. }
  5978. }
  5979. /* dynamic clk change use case */
  5980. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  5981. if (dyn_clk_caps->dyn_clk_support) {
  5982. DSI_DEBUG("dynamic clk change detected\n");
  5983. if ((adj_mode->dsi_mode_flags &
  5984. DSI_MODE_FLAG_VRR) &&
  5985. (!dyn_clk_caps->maintain_const_fps)) {
  5986. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  5987. rc = -ENOTSUPP;
  5988. goto error;
  5989. }
  5990. adj_mode->dsi_mode_flags |=
  5991. DSI_MODE_FLAG_DYN_CLK;
  5992. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  5993. cur_mode->pixel_clk_khz,
  5994. adj_mode->pixel_clk_khz);
  5995. }
  5996. }
  5997. }
  5998. error:
  5999. mutex_unlock(&display->display_lock);
  6000. return rc;
  6001. }
  6002. int dsi_display_validate_mode(struct dsi_display *display,
  6003. struct dsi_display_mode *mode,
  6004. u32 flags)
  6005. {
  6006. int rc = 0;
  6007. int i;
  6008. struct dsi_display_ctrl *ctrl;
  6009. struct dsi_display_mode adj_mode;
  6010. if (!display || !mode) {
  6011. DSI_ERR("Invalid params\n");
  6012. return -EINVAL;
  6013. }
  6014. mutex_lock(&display->display_lock);
  6015. adj_mode = *mode;
  6016. adjust_timing_by_ctrl_count(display, &adj_mode);
  6017. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  6018. if (rc) {
  6019. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  6020. display->name, rc);
  6021. goto error;
  6022. }
  6023. display_for_each_ctrl(i, display) {
  6024. ctrl = &display->ctrl[i];
  6025. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  6026. if (rc) {
  6027. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  6028. display->name, rc);
  6029. goto error;
  6030. }
  6031. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  6032. if (rc) {
  6033. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  6034. display->name, rc);
  6035. goto error;
  6036. }
  6037. }
  6038. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  6039. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  6040. rc = dsi_display_validate_mode_seamless(display, mode);
  6041. if (rc) {
  6042. DSI_ERR("[%s] seamless not possible rc=%d\n",
  6043. display->name, rc);
  6044. goto error;
  6045. }
  6046. }
  6047. error:
  6048. mutex_unlock(&display->display_lock);
  6049. return rc;
  6050. }
  6051. int dsi_display_set_mode(struct dsi_display *display,
  6052. struct dsi_display_mode *mode,
  6053. u32 flags)
  6054. {
  6055. int rc = 0;
  6056. struct dsi_display_mode adj_mode;
  6057. struct dsi_mode_info timing;
  6058. if (!display || !mode || !display->panel) {
  6059. DSI_ERR("Invalid params\n");
  6060. return -EINVAL;
  6061. }
  6062. mutex_lock(&display->display_lock);
  6063. adj_mode = *mode;
  6064. timing = adj_mode.timing;
  6065. adjust_timing_by_ctrl_count(display, &adj_mode);
  6066. if (!display->panel->cur_mode) {
  6067. display->panel->cur_mode =
  6068. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  6069. if (!display->panel->cur_mode) {
  6070. rc = -ENOMEM;
  6071. goto error;
  6072. }
  6073. }
  6074. /*For dynamic DSI setting, use specified clock rate */
  6075. if (display->cached_clk_rate > 0)
  6076. adj_mode.priv_info->clk_rate_hz = display->cached_clk_rate;
  6077. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  6078. if (rc) {
  6079. DSI_ERR("[%s] mode cannot be set\n", display->name);
  6080. goto error;
  6081. }
  6082. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  6083. if (rc) {
  6084. DSI_ERR("[%s] failed to set mode\n", display->name);
  6085. goto error;
  6086. }
  6087. DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d\n",
  6088. adj_mode.priv_info->mdp_transfer_time_us,
  6089. timing.h_active, timing.v_active, timing.refresh_rate);
  6090. SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
  6091. timing.h_active, timing.v_active, timing.refresh_rate);
  6092. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  6093. error:
  6094. mutex_unlock(&display->display_lock);
  6095. return rc;
  6096. }
  6097. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  6098. {
  6099. int rc = 0;
  6100. int i;
  6101. struct dsi_display_ctrl *ctrl;
  6102. if (!display) {
  6103. DSI_ERR("Invalid params\n");
  6104. return -EINVAL;
  6105. }
  6106. display_for_each_ctrl(i, display) {
  6107. ctrl = &display->ctrl[i];
  6108. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  6109. if (rc) {
  6110. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  6111. display->name, i);
  6112. goto error;
  6113. }
  6114. }
  6115. display->is_tpg_enabled = enable;
  6116. error:
  6117. return rc;
  6118. }
  6119. static int dsi_display_pre_switch(struct dsi_display *display)
  6120. {
  6121. int rc = 0;
  6122. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6123. DSI_CORE_CLK, DSI_CLK_ON);
  6124. if (rc) {
  6125. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6126. display->name, rc);
  6127. goto error;
  6128. }
  6129. rc = dsi_display_ctrl_update(display);
  6130. if (rc) {
  6131. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  6132. display->name, rc);
  6133. goto error_ctrl_clk_off;
  6134. }
  6135. if (!display->trusted_vm_env) {
  6136. rc = dsi_display_set_clk_src(display);
  6137. if (rc) {
  6138. DSI_ERR(
  6139. "[%s] failed to set DSI link clock source, rc=%d\n",
  6140. display->name, rc);
  6141. goto error_ctrl_deinit;
  6142. }
  6143. }
  6144. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6145. DSI_LINK_CLK, DSI_CLK_ON);
  6146. if (rc) {
  6147. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6148. display->name, rc);
  6149. goto error_ctrl_deinit;
  6150. }
  6151. goto error;
  6152. error_ctrl_deinit:
  6153. (void)dsi_display_ctrl_deinit(display);
  6154. error_ctrl_clk_off:
  6155. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6156. DSI_CORE_CLK, DSI_CLK_OFF);
  6157. error:
  6158. return rc;
  6159. }
  6160. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  6161. {
  6162. int i;
  6163. struct dsi_display_ctrl *ctrl;
  6164. display_for_each_ctrl(i, display) {
  6165. ctrl = &display->ctrl[i];
  6166. if (!ctrl->ctrl)
  6167. continue;
  6168. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  6169. return false;
  6170. }
  6171. return true;
  6172. }
  6173. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  6174. {
  6175. struct dsi_display *display = NULL;
  6176. display = container_of(work, struct dsi_display, fifo_underflow_work);
  6177. if (!display || !display->panel ||
  6178. atomic_read(&display->panel->esd_recovery_pending)) {
  6179. DSI_DEBUG("Invalid recovery use case\n");
  6180. return;
  6181. }
  6182. mutex_lock(&display->display_lock);
  6183. if (!_dsi_display_validate_host_state(display)) {
  6184. mutex_unlock(&display->display_lock);
  6185. return;
  6186. }
  6187. DSI_INFO("handle DSI FIFO underflow error\n");
  6188. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6189. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6190. DSI_ALL_CLKS, DSI_CLK_ON);
  6191. dsi_display_soft_reset(display);
  6192. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6193. DSI_ALL_CLKS, DSI_CLK_OFF);
  6194. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6195. mutex_unlock(&display->display_lock);
  6196. }
  6197. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6198. {
  6199. struct dsi_display *display = NULL;
  6200. struct dsi_display_ctrl *ctrl;
  6201. int i, rc;
  6202. int mask = BIT(20); /* clock lane */
  6203. int (*cb_func)(void *event_usr_ptr,
  6204. uint32_t event_idx, uint32_t instance_idx,
  6205. uint32_t data0, uint32_t data1,
  6206. uint32_t data2, uint32_t data3);
  6207. void *data;
  6208. u32 version = 0;
  6209. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6210. if (!display || !display->panel ||
  6211. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6212. atomic_read(&display->panel->esd_recovery_pending)) {
  6213. DSI_DEBUG("Invalid recovery use case\n");
  6214. return;
  6215. }
  6216. mutex_lock(&display->display_lock);
  6217. if (!_dsi_display_validate_host_state(display)) {
  6218. mutex_unlock(&display->display_lock);
  6219. return;
  6220. }
  6221. DSI_INFO("handle DSI FIFO overflow error\n");
  6222. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6223. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6224. DSI_ALL_CLKS, DSI_CLK_ON);
  6225. /*
  6226. * below recovery sequence is not applicable to
  6227. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6228. */
  6229. ctrl = &display->ctrl[display->clk_master_idx];
  6230. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6231. if (!version || (version < 0x20020001))
  6232. goto end;
  6233. /* reset ctrl and lanes */
  6234. display_for_each_ctrl(i, display) {
  6235. ctrl = &display->ctrl[i];
  6236. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6237. rc = dsi_phy_lane_reset(ctrl->phy);
  6238. }
  6239. /* wait for display line count to be in active area */
  6240. ctrl = &display->ctrl[display->clk_master_idx];
  6241. if (ctrl->ctrl->recovery_cb.event_cb) {
  6242. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6243. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6244. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6245. display->clk_master_idx, 0, 0, 0, 0);
  6246. if (rc < 0) {
  6247. DSI_DEBUG("sde callback failed\n");
  6248. goto end;
  6249. }
  6250. }
  6251. /* Enable Video mode for DSI controller */
  6252. display_for_each_ctrl(i, display) {
  6253. ctrl = &display->ctrl[i];
  6254. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6255. }
  6256. /*
  6257. * Add sufficient delay to make sure
  6258. * pixel transmission has started
  6259. */
  6260. udelay(200);
  6261. end:
  6262. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6263. DSI_ALL_CLKS, DSI_CLK_OFF);
  6264. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6265. mutex_unlock(&display->display_lock);
  6266. }
  6267. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6268. {
  6269. struct dsi_display *display = NULL;
  6270. struct dsi_display_ctrl *ctrl;
  6271. int i, rc;
  6272. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6273. int (*cb_func)(void *event_usr_ptr,
  6274. uint32_t event_idx, uint32_t instance_idx,
  6275. uint32_t data0, uint32_t data1,
  6276. uint32_t data2, uint32_t data3);
  6277. void *data;
  6278. u32 version = 0;
  6279. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6280. if (!display || !display->panel ||
  6281. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6282. atomic_read(&display->panel->esd_recovery_pending)) {
  6283. DSI_DEBUG("Invalid recovery use case\n");
  6284. return;
  6285. }
  6286. mutex_lock(&display->display_lock);
  6287. if (!_dsi_display_validate_host_state(display)) {
  6288. mutex_unlock(&display->display_lock);
  6289. return;
  6290. }
  6291. DSI_INFO("handle DSI LP RX Timeout error\n");
  6292. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6293. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6294. DSI_ALL_CLKS, DSI_CLK_ON);
  6295. /*
  6296. * below recovery sequence is not applicable to
  6297. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6298. */
  6299. ctrl = &display->ctrl[display->clk_master_idx];
  6300. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6301. if (!version || (version < 0x20020001))
  6302. goto end;
  6303. /* reset ctrl and lanes */
  6304. display_for_each_ctrl(i, display) {
  6305. ctrl = &display->ctrl[i];
  6306. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6307. rc = dsi_phy_lane_reset(ctrl->phy);
  6308. }
  6309. ctrl = &display->ctrl[display->clk_master_idx];
  6310. if (ctrl->ctrl->recovery_cb.event_cb) {
  6311. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6312. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6313. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6314. display->clk_master_idx, 0, 0, 0, 0);
  6315. if (rc < 0) {
  6316. DSI_DEBUG("Target is in suspend/shutdown\n");
  6317. goto end;
  6318. }
  6319. }
  6320. /* Enable Video mode for DSI controller */
  6321. display_for_each_ctrl(i, display) {
  6322. ctrl = &display->ctrl[i];
  6323. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6324. }
  6325. /*
  6326. * Add sufficient delay to make sure
  6327. * pixel transmission as started
  6328. */
  6329. udelay(200);
  6330. end:
  6331. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6332. DSI_ALL_CLKS, DSI_CLK_OFF);
  6333. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6334. mutex_unlock(&display->display_lock);
  6335. }
  6336. static int dsi_display_cb_error_handler(void *data,
  6337. uint32_t event_idx, uint32_t instance_idx,
  6338. uint32_t data0, uint32_t data1,
  6339. uint32_t data2, uint32_t data3)
  6340. {
  6341. struct dsi_display *display = data;
  6342. if (!display || !(display->err_workq))
  6343. return -EINVAL;
  6344. switch (event_idx) {
  6345. case DSI_FIFO_UNDERFLOW:
  6346. queue_work(display->err_workq, &display->fifo_underflow_work);
  6347. break;
  6348. case DSI_FIFO_OVERFLOW:
  6349. queue_work(display->err_workq, &display->fifo_overflow_work);
  6350. break;
  6351. case DSI_LP_Rx_TIMEOUT:
  6352. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6353. break;
  6354. default:
  6355. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6356. break;
  6357. }
  6358. return 0;
  6359. }
  6360. static void dsi_display_register_error_handler(struct dsi_display *display)
  6361. {
  6362. int i = 0;
  6363. struct dsi_display_ctrl *ctrl;
  6364. struct dsi_event_cb_info event_info;
  6365. if (!display)
  6366. return;
  6367. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6368. if (!display->err_workq) {
  6369. DSI_ERR("failed to create dsi workq!\n");
  6370. return;
  6371. }
  6372. INIT_WORK(&display->fifo_underflow_work,
  6373. dsi_display_handle_fifo_underflow);
  6374. INIT_WORK(&display->fifo_overflow_work,
  6375. dsi_display_handle_fifo_overflow);
  6376. INIT_WORK(&display->lp_rx_timeout_work,
  6377. dsi_display_handle_lp_rx_timeout);
  6378. memset(&event_info, 0, sizeof(event_info));
  6379. event_info.event_cb = dsi_display_cb_error_handler;
  6380. event_info.event_usr_ptr = display;
  6381. display_for_each_ctrl(i, display) {
  6382. ctrl = &display->ctrl[i];
  6383. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6384. }
  6385. }
  6386. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6387. {
  6388. int i = 0;
  6389. struct dsi_display_ctrl *ctrl;
  6390. if (!display)
  6391. return;
  6392. display_for_each_ctrl(i, display) {
  6393. ctrl = &display->ctrl[i];
  6394. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6395. 0, sizeof(struct dsi_event_cb_info));
  6396. }
  6397. if (display->err_workq) {
  6398. destroy_workqueue(display->err_workq);
  6399. display->err_workq = NULL;
  6400. }
  6401. }
  6402. int dsi_display_prepare(struct dsi_display *display)
  6403. {
  6404. int rc = 0;
  6405. struct dsi_display_mode *mode;
  6406. if (!display) {
  6407. DSI_ERR("Invalid params\n");
  6408. return -EINVAL;
  6409. }
  6410. if (!display->panel->cur_mode) {
  6411. DSI_ERR("no valid mode set for the display\n");
  6412. return -EINVAL;
  6413. }
  6414. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6415. mutex_lock(&display->display_lock);
  6416. mode = display->panel->cur_mode;
  6417. dsi_display_set_ctrl_esd_check_flag(display, false);
  6418. /* Set up ctrl isr before enabling core clk */
  6419. if (!display->trusted_vm_env)
  6420. dsi_display_ctrl_isr_configure(display, true);
  6421. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6422. if (display->is_cont_splash_enabled &&
  6423. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6424. DSI_ERR("DMS not supported on first frame\n");
  6425. rc = -EINVAL;
  6426. goto error;
  6427. }
  6428. if (!is_skip_op_required(display)) {
  6429. /* update dsi ctrl for new mode */
  6430. rc = dsi_display_pre_switch(display);
  6431. if (rc)
  6432. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6433. display->name, rc);
  6434. goto error;
  6435. }
  6436. }
  6437. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) &&
  6438. (!is_skip_op_required(display))) {
  6439. /*
  6440. * For continuous splash/trusted vm, we skip panel
  6441. * pre prepare since the regulator vote is already
  6442. * taken care in splash resource init
  6443. */
  6444. rc = dsi_panel_pre_prepare(display->panel);
  6445. if (rc) {
  6446. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6447. display->name, rc);
  6448. goto error;
  6449. }
  6450. }
  6451. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6452. DSI_CORE_CLK, DSI_CLK_ON);
  6453. if (rc) {
  6454. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6455. display->name, rc);
  6456. goto error_panel_post_unprep;
  6457. }
  6458. /*
  6459. * If ULPS during suspend feature is enabled, then DSI PHY was
  6460. * left on during suspend. In this case, we do not need to reset/init
  6461. * PHY. This would have already been done when the CORE clocks are
  6462. * turned on. However, if cont splash is disabled, the first time DSI
  6463. * is powered on, phy init needs to be done unconditionally.
  6464. */
  6465. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6466. rc = dsi_display_phy_sw_reset(display);
  6467. if (rc) {
  6468. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6469. display->name, rc);
  6470. goto error_ctrl_clk_off;
  6471. }
  6472. rc = dsi_display_phy_enable(display);
  6473. if (rc) {
  6474. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6475. display->name, rc);
  6476. goto error_ctrl_clk_off;
  6477. }
  6478. }
  6479. if (!display->trusted_vm_env) {
  6480. rc = dsi_display_set_clk_src(display);
  6481. if (rc) {
  6482. DSI_ERR(
  6483. "[%s] failed to set DSI link clock source, rc=%d\n",
  6484. display->name, rc);
  6485. goto error_phy_disable;
  6486. }
  6487. }
  6488. rc = dsi_display_ctrl_init(display);
  6489. if (rc) {
  6490. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6491. display->name, rc);
  6492. goto error_phy_disable;
  6493. }
  6494. /* Set up DSI ERROR event callback */
  6495. dsi_display_register_error_handler(display);
  6496. rc = dsi_display_ctrl_host_enable(display);
  6497. if (rc) {
  6498. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6499. display->name, rc);
  6500. goto error_ctrl_deinit;
  6501. }
  6502. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6503. DSI_LINK_CLK, DSI_CLK_ON);
  6504. if (rc) {
  6505. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6506. display->name, rc);
  6507. goto error_host_engine_off;
  6508. }
  6509. if (!is_skip_op_required(display)) {
  6510. /*
  6511. * For continuous splash/trusted vm, skip panel prepare and
  6512. * ctl reset since the pnael and ctrl is already in active
  6513. * state and panel on commands are not needed
  6514. */
  6515. rc = dsi_display_soft_reset(display);
  6516. if (rc) {
  6517. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6518. display->name, rc);
  6519. goto error_ctrl_link_off;
  6520. }
  6521. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)) {
  6522. rc = dsi_panel_prepare(display->panel);
  6523. if (rc) {
  6524. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6525. display->name, rc);
  6526. goto error_ctrl_link_off;
  6527. }
  6528. }
  6529. }
  6530. goto error;
  6531. error_ctrl_link_off:
  6532. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6533. DSI_LINK_CLK, DSI_CLK_OFF);
  6534. error_host_engine_off:
  6535. (void)dsi_display_ctrl_host_disable(display);
  6536. error_ctrl_deinit:
  6537. (void)dsi_display_ctrl_deinit(display);
  6538. error_phy_disable:
  6539. (void)dsi_display_phy_disable(display);
  6540. error_ctrl_clk_off:
  6541. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6542. DSI_CORE_CLK, DSI_CLK_OFF);
  6543. error_panel_post_unprep:
  6544. (void)dsi_panel_post_unprepare(display->panel);
  6545. error:
  6546. mutex_unlock(&display->display_lock);
  6547. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6548. return rc;
  6549. }
  6550. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6551. const struct dsi_display_ctrl *ctrl,
  6552. const struct msm_roi_list *req_rois,
  6553. struct dsi_rect *out_roi)
  6554. {
  6555. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6556. struct dsi_display_mode *cur_mode;
  6557. struct msm_roi_caps *roi_caps;
  6558. struct dsi_rect req_roi = { 0 };
  6559. int rc = 0;
  6560. cur_mode = display->panel->cur_mode;
  6561. if (!cur_mode)
  6562. return 0;
  6563. roi_caps = &cur_mode->priv_info->roi_caps;
  6564. if (req_rois->num_rects > roi_caps->num_roi) {
  6565. DSI_ERR("request for %d rois greater than max %d\n",
  6566. req_rois->num_rects,
  6567. roi_caps->num_roi);
  6568. rc = -EINVAL;
  6569. goto exit;
  6570. }
  6571. /**
  6572. * if no rois, user wants to reset back to full resolution
  6573. * note: h_active is already divided by ctrl_count
  6574. */
  6575. if (!req_rois->num_rects) {
  6576. *out_roi = *bounds;
  6577. goto exit;
  6578. }
  6579. /* intersect with the bounds */
  6580. req_roi.x = req_rois->roi[0].x1;
  6581. req_roi.y = req_rois->roi[0].y1;
  6582. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6583. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6584. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6585. exit:
  6586. /* adjust the ctrl origin to be top left within the ctrl */
  6587. out_roi->x = out_roi->x - bounds->x;
  6588. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6589. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6590. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6591. bounds->x, bounds->y, bounds->w, bounds->h,
  6592. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6593. return rc;
  6594. }
  6595. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6596. {
  6597. int i;
  6598. int rc = 0;
  6599. if (!display->panel->qsync_caps.qsync_min_fps) {
  6600. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6601. return 0;
  6602. }
  6603. mutex_lock(&display->display_lock);
  6604. display_for_each_ctrl(i, display) {
  6605. if (enable) {
  6606. /* send the commands to enable qsync */
  6607. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6608. if (rc) {
  6609. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6610. goto exit;
  6611. }
  6612. } else {
  6613. /* send the commands to enable qsync */
  6614. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6615. if (rc) {
  6616. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6617. goto exit;
  6618. }
  6619. }
  6620. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6621. }
  6622. exit:
  6623. SDE_EVT32(enable, display->panel->qsync_caps.qsync_min_fps, rc);
  6624. mutex_unlock(&display->display_lock);
  6625. return rc;
  6626. }
  6627. static int dsi_display_set_roi(struct dsi_display *display,
  6628. struct msm_roi_list *rois)
  6629. {
  6630. struct dsi_display_mode *cur_mode;
  6631. struct msm_roi_caps *roi_caps;
  6632. int rc = 0;
  6633. int i;
  6634. if (!display || !rois || !display->panel)
  6635. return -EINVAL;
  6636. cur_mode = display->panel->cur_mode;
  6637. if (!cur_mode)
  6638. return 0;
  6639. roi_caps = &cur_mode->priv_info->roi_caps;
  6640. if (!roi_caps->enabled)
  6641. return 0;
  6642. display_for_each_ctrl(i, display) {
  6643. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6644. struct dsi_rect ctrl_roi;
  6645. bool changed = false;
  6646. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6647. if (rc) {
  6648. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6649. return rc;
  6650. }
  6651. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6652. if (rc) {
  6653. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6654. return rc;
  6655. }
  6656. if (!changed)
  6657. continue;
  6658. /* send the new roi to the panel via dcs commands */
  6659. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6660. if (rc) {
  6661. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6662. return rc;
  6663. }
  6664. /* re-program the ctrl with the timing based on the new roi */
  6665. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6666. if (rc) {
  6667. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6668. return rc;
  6669. }
  6670. }
  6671. return rc;
  6672. }
  6673. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6674. struct dsi_display *display,
  6675. struct msm_display_kickoff_params *params)
  6676. {
  6677. int rc = 0, ret = 0;
  6678. int i;
  6679. /* check and setup MISR */
  6680. if (display->misr_enable)
  6681. _dsi_display_setup_misr(display);
  6682. /* dynamic DSI clock setting */
  6683. if (atomic_read(&display->clkrate_change_pending)) {
  6684. mutex_lock(&display->display_lock);
  6685. /*
  6686. * acquire panel_lock to make sure no commands are in progress
  6687. */
  6688. dsi_panel_acquire_panel_lock(display->panel);
  6689. /*
  6690. * Wait for DSI command engine not to be busy sending data
  6691. * from display engine.
  6692. * If waiting fails, return "rc" instead of below "ret" so as
  6693. * not to impact DRM commit. The clock updating would be
  6694. * deferred to the next DRM commit.
  6695. */
  6696. display_for_each_ctrl(i, display) {
  6697. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6698. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6699. if (ret)
  6700. goto wait_failure;
  6701. }
  6702. /*
  6703. * Don't check the return value so as not to impact DRM commit
  6704. * when error occurs.
  6705. */
  6706. (void)dsi_display_force_update_dsi_clk(display);
  6707. wait_failure:
  6708. /* release panel_lock */
  6709. dsi_panel_release_panel_lock(display->panel);
  6710. mutex_unlock(&display->display_lock);
  6711. }
  6712. if (!ret)
  6713. rc = dsi_display_set_roi(display, params->rois);
  6714. return rc;
  6715. }
  6716. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6717. {
  6718. int rc = 0;
  6719. if (!display || !display->panel) {
  6720. DSI_ERR("Invalid params\n");
  6721. return -EINVAL;
  6722. }
  6723. if (!display->panel->cur_mode) {
  6724. DSI_ERR("no valid mode set for the display\n");
  6725. return -EINVAL;
  6726. }
  6727. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6728. rc = dsi_display_vid_engine_enable(display);
  6729. if (rc) {
  6730. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6731. display->name, rc);
  6732. goto error_out;
  6733. }
  6734. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6735. rc = dsi_display_cmd_engine_enable(display);
  6736. if (rc) {
  6737. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6738. display->name, rc);
  6739. goto error_out;
  6740. }
  6741. } else {
  6742. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6743. rc = -EINVAL;
  6744. }
  6745. error_out:
  6746. return rc;
  6747. }
  6748. int dsi_display_pre_commit(void *display,
  6749. struct msm_display_conn_params *params)
  6750. {
  6751. bool enable = false;
  6752. int rc = 0;
  6753. if (!display || !params) {
  6754. pr_err("Invalid params\n");
  6755. return -EINVAL;
  6756. }
  6757. if (params->qsync_update) {
  6758. enable = (params->qsync_mode > 0) ? true : false;
  6759. rc = dsi_display_qsync(display, enable);
  6760. if (rc)
  6761. pr_err("%s failed to send qsync commands\n",
  6762. __func__);
  6763. SDE_EVT32(params->qsync_mode, rc);
  6764. }
  6765. return rc;
  6766. }
  6767. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6768. {
  6769. if (display->panel_id != ~0x0 &&
  6770. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6771. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6772. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6773. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6774. 0, ((display->panel_id & 0xffffffff00000000) >> 31),
  6775. (display->panel_id & 0xffffffff), 0, 0);
  6776. }
  6777. }
  6778. int dsi_display_enable(struct dsi_display *display)
  6779. {
  6780. int rc = 0;
  6781. struct dsi_display_mode *mode;
  6782. if (!display || !display->panel) {
  6783. DSI_ERR("Invalid params\n");
  6784. return -EINVAL;
  6785. }
  6786. if (!display->panel->cur_mode) {
  6787. DSI_ERR("no valid mode set for the display\n");
  6788. return -EINVAL;
  6789. }
  6790. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6791. /*
  6792. * Engine states and panel states are populated during splash
  6793. * resource/trusted vm and hence we return early
  6794. */
  6795. if (is_skip_op_required(display)) {
  6796. dsi_display_config_ctrl_for_cont_splash(display);
  6797. rc = dsi_display_splash_res_cleanup(display);
  6798. if (rc) {
  6799. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6800. rc);
  6801. return -EINVAL;
  6802. }
  6803. display->panel->panel_initialized = true;
  6804. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6805. dsi_display_panel_id_notification(display);
  6806. return 0;
  6807. }
  6808. mutex_lock(&display->display_lock);
  6809. mode = display->panel->cur_mode;
  6810. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6811. rc = dsi_panel_post_switch(display->panel);
  6812. if (rc) {
  6813. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6814. display->name, rc);
  6815. goto error;
  6816. }
  6817. } else if (!(display->panel->cur_mode->dsi_mode_flags &
  6818. DSI_MODE_FLAG_POMS)){
  6819. rc = dsi_panel_enable(display->panel);
  6820. if (rc) {
  6821. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6822. display->name, rc);
  6823. goto error;
  6824. }
  6825. }
  6826. dsi_display_panel_id_notification(display);
  6827. /* Block sending pps command if modeset is due to fps difference */
  6828. if ((mode->priv_info->dsc_enabled ||
  6829. mode->priv_info->vdc_enabled) &&
  6830. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6831. rc = dsi_panel_update_pps(display->panel);
  6832. if (rc) {
  6833. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6834. display->name, rc);
  6835. goto error;
  6836. }
  6837. }
  6838. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6839. rc = dsi_panel_switch(display->panel);
  6840. if (rc)
  6841. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6842. display->name, rc);
  6843. goto error;
  6844. }
  6845. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6846. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6847. rc = dsi_display_vid_engine_enable(display);
  6848. if (rc) {
  6849. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6850. display->name, rc);
  6851. goto error_disable_panel;
  6852. }
  6853. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6854. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6855. rc = dsi_display_cmd_engine_enable(display);
  6856. if (rc) {
  6857. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6858. display->name, rc);
  6859. goto error_disable_panel;
  6860. }
  6861. } else {
  6862. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6863. rc = -EINVAL;
  6864. goto error_disable_panel;
  6865. }
  6866. goto error;
  6867. error_disable_panel:
  6868. (void)dsi_panel_disable(display->panel);
  6869. error:
  6870. mutex_unlock(&display->display_lock);
  6871. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6872. return rc;
  6873. }
  6874. int dsi_display_post_enable(struct dsi_display *display)
  6875. {
  6876. int rc = 0;
  6877. if (!display) {
  6878. DSI_ERR("Invalid params\n");
  6879. return -EINVAL;
  6880. }
  6881. mutex_lock(&display->display_lock);
  6882. if (display->panel->cur_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) {
  6883. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6884. dsi_panel_mode_switch_to_cmd(display->panel);
  6885. if (display->config.panel_mode == DSI_OP_VIDEO_MODE)
  6886. dsi_panel_mode_switch_to_vid(display->panel);
  6887. } else {
  6888. rc = dsi_panel_post_enable(display->panel);
  6889. if (rc)
  6890. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  6891. display->name, rc);
  6892. }
  6893. /* remove the clk vote for CMD mode panels */
  6894. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6895. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6896. DSI_ALL_CLKS, DSI_CLK_OFF);
  6897. mutex_unlock(&display->display_lock);
  6898. return rc;
  6899. }
  6900. int dsi_display_pre_disable(struct dsi_display *display)
  6901. {
  6902. int rc = 0;
  6903. if (!display) {
  6904. DSI_ERR("Invalid params\n");
  6905. return -EINVAL;
  6906. }
  6907. mutex_lock(&display->display_lock);
  6908. /* enable the clk vote for CMD mode panels */
  6909. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6910. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6911. DSI_ALL_CLKS, DSI_CLK_ON);
  6912. if (display->poms_pending) {
  6913. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6914. dsi_panel_pre_mode_switch_to_video(display->panel);
  6915. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6916. /*
  6917. * Add unbalanced vote for clock & cmd engine to enable
  6918. * async trigger of pre video to cmd mode switch.
  6919. */
  6920. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6921. DSI_ALL_CLKS, DSI_CLK_ON);
  6922. if (rc) {
  6923. DSI_ERR("[%s]failed to enable all clocks,rc=%d",
  6924. display->name, rc);
  6925. goto exit;
  6926. }
  6927. rc = dsi_display_cmd_engine_enable(display);
  6928. if (rc) {
  6929. DSI_ERR("[%s]failed to enable cmd engine,rc=%d",
  6930. display->name, rc);
  6931. goto error_disable_clks;
  6932. }
  6933. dsi_panel_pre_mode_switch_to_cmd(display->panel);
  6934. }
  6935. } else {
  6936. rc = dsi_panel_pre_disable(display->panel);
  6937. if (rc)
  6938. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  6939. display->name, rc);
  6940. }
  6941. goto exit;
  6942. error_disable_clks:
  6943. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6944. DSI_ALL_CLKS, DSI_CLK_OFF);
  6945. if (rc)
  6946. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  6947. display->name, rc);
  6948. exit:
  6949. mutex_unlock(&display->display_lock);
  6950. return rc;
  6951. }
  6952. static void dsi_display_handle_poms_te(struct work_struct *work)
  6953. {
  6954. struct dsi_display *display = NULL;
  6955. struct delayed_work *dw = to_delayed_work(work);
  6956. struct mipi_dsi_device *dsi = NULL;
  6957. struct dsi_panel *panel = NULL;
  6958. int rc = 0;
  6959. display = container_of(dw, struct dsi_display, poms_te_work);
  6960. if (!display || !display->panel) {
  6961. DSI_ERR("Invalid params\n");
  6962. return;
  6963. }
  6964. panel = display->panel;
  6965. mutex_lock(&panel->panel_lock);
  6966. if (!dsi_panel_initialized(panel)) {
  6967. rc = -EINVAL;
  6968. goto error;
  6969. }
  6970. dsi = &panel->mipi_device;
  6971. rc = mipi_dsi_dcs_set_tear_off(dsi);
  6972. error:
  6973. mutex_unlock(&panel->panel_lock);
  6974. if (rc < 0)
  6975. DSI_ERR("failed to set tear off\n");
  6976. }
  6977. int dsi_display_disable(struct dsi_display *display)
  6978. {
  6979. int rc = 0;
  6980. if (!display) {
  6981. DSI_ERR("Invalid params\n");
  6982. return -EINVAL;
  6983. }
  6984. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6985. mutex_lock(&display->display_lock);
  6986. /* cancel delayed work */
  6987. if (display->poms_pending &&
  6988. display->panel->poms_align_vsync)
  6989. cancel_delayed_work_sync(&display->poms_te_work);
  6990. rc = dsi_display_wake_up(display);
  6991. if (rc)
  6992. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  6993. display->name, rc);
  6994. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6995. rc = dsi_display_vid_engine_disable(display);
  6996. if (rc)
  6997. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  6998. display->name, rc);
  6999. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  7000. /**
  7001. * On POMS request , disable panel TE through
  7002. * delayed work queue.
  7003. */
  7004. if (display->poms_pending &&
  7005. display->panel->poms_align_vsync) {
  7006. INIT_DELAYED_WORK(&display->poms_te_work,
  7007. dsi_display_handle_poms_te);
  7008. queue_delayed_work(system_wq,
  7009. &display->poms_te_work,
  7010. msecs_to_jiffies(100));
  7011. }
  7012. rc = dsi_display_cmd_engine_disable(display);
  7013. if (rc)
  7014. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  7015. display->name, rc);
  7016. } else {
  7017. DSI_ERR("[%s] Invalid configuration\n", display->name);
  7018. rc = -EINVAL;
  7019. }
  7020. if (!display->poms_pending && !is_skip_op_required(display)) {
  7021. rc = dsi_panel_disable(display->panel);
  7022. if (rc)
  7023. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  7024. display->name, rc);
  7025. }
  7026. if (is_skip_op_required(display)) {
  7027. /* applicable only for trusted vm */
  7028. display->panel->panel_initialized = false;
  7029. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  7030. }
  7031. mutex_unlock(&display->display_lock);
  7032. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7033. return rc;
  7034. }
  7035. int dsi_display_update_pps(char *pps_cmd, void *disp)
  7036. {
  7037. struct dsi_display *display;
  7038. if (pps_cmd == NULL || disp == NULL) {
  7039. DSI_ERR("Invalid parameter\n");
  7040. return -EINVAL;
  7041. }
  7042. display = disp;
  7043. mutex_lock(&display->display_lock);
  7044. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  7045. mutex_unlock(&display->display_lock);
  7046. return 0;
  7047. }
  7048. int dsi_display_dump_clks_state(struct dsi_display *display)
  7049. {
  7050. int rc = 0;
  7051. if (!display) {
  7052. DSI_ERR("invalid display argument\n");
  7053. return -EINVAL;
  7054. }
  7055. if (!display->clk_mngr) {
  7056. DSI_ERR("invalid clk manager\n");
  7057. return -EINVAL;
  7058. }
  7059. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  7060. DSI_ERR("invalid clk handles\n");
  7061. return -EINVAL;
  7062. }
  7063. mutex_lock(&display->display_lock);
  7064. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  7065. if (rc) {
  7066. DSI_ERR("failed to dump dsi clock state\n");
  7067. goto end;
  7068. }
  7069. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  7070. if (rc) {
  7071. DSI_ERR("failed to dump mdp clock state\n");
  7072. goto end;
  7073. }
  7074. end:
  7075. mutex_unlock(&display->display_lock);
  7076. return rc;
  7077. }
  7078. int dsi_display_unprepare(struct dsi_display *display)
  7079. {
  7080. int rc = 0, i;
  7081. struct dsi_display_ctrl *ctrl;
  7082. if (!display) {
  7083. DSI_ERR("Invalid params\n");
  7084. return -EINVAL;
  7085. }
  7086. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7087. mutex_lock(&display->display_lock);
  7088. rc = dsi_display_wake_up(display);
  7089. if (rc)
  7090. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7091. display->name, rc);
  7092. if (!display->poms_pending && !is_skip_op_required(display)) {
  7093. rc = dsi_panel_unprepare(display->panel);
  7094. if (rc)
  7095. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  7096. display->name, rc);
  7097. }
  7098. /* Remove additional vote added for pre_mode_switch_to_cmd */
  7099. if (display->poms_pending &&
  7100. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7101. display_for_each_ctrl(i, display) {
  7102. ctrl = &display->ctrl[i];
  7103. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  7104. continue;
  7105. flush_workqueue(display->dma_cmd_workq);
  7106. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  7107. ctrl->ctrl->dma_wait_queued = false;
  7108. }
  7109. dsi_display_cmd_engine_disable(display);
  7110. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7111. DSI_ALL_CLKS, DSI_CLK_OFF);
  7112. }
  7113. rc = dsi_display_ctrl_host_disable(display);
  7114. if (rc)
  7115. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  7116. display->name, rc);
  7117. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7118. DSI_LINK_CLK, DSI_CLK_OFF);
  7119. if (rc)
  7120. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  7121. display->name, rc);
  7122. rc = dsi_display_ctrl_deinit(display);
  7123. if (rc)
  7124. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  7125. display->name, rc);
  7126. if (!display->panel->ulps_suspend_enabled) {
  7127. rc = dsi_display_phy_disable(display);
  7128. if (rc)
  7129. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  7130. display->name, rc);
  7131. }
  7132. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7133. DSI_CORE_CLK, DSI_CLK_OFF);
  7134. if (rc)
  7135. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  7136. display->name, rc);
  7137. /* destrory dsi isr set up */
  7138. dsi_display_ctrl_isr_configure(display, false);
  7139. if (!display->poms_pending && !is_skip_op_required(display)) {
  7140. rc = dsi_panel_post_unprepare(display->panel);
  7141. if (rc)
  7142. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  7143. display->name, rc);
  7144. }
  7145. mutex_unlock(&display->display_lock);
  7146. /* Free up DSI ERROR event callback */
  7147. dsi_display_unregister_error_handler(display);
  7148. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7149. return rc;
  7150. }
  7151. void __init dsi_display_register(void)
  7152. {
  7153. dsi_phy_drv_register();
  7154. dsi_ctrl_drv_register();
  7155. dsi_display_parse_boot_display_selection();
  7156. platform_driver_register(&dsi_display_driver);
  7157. }
  7158. void __exit dsi_display_unregister(void)
  7159. {
  7160. platform_driver_unregister(&dsi_display_driver);
  7161. dsi_ctrl_drv_unregister();
  7162. dsi_phy_drv_unregister();
  7163. }
  7164. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  7165. 0600);
  7166. MODULE_PARM_DESC(dsi_display0,
  7167. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  7168. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  7169. 0600);
  7170. MODULE_PARM_DESC(dsi_display1,
  7171. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");