dp_tx.c 108 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #define DP_TX_QUEUE_MASK 0x3
  34. /* TODO Add support in TSO */
  35. #define DP_DESC_NUM_FRAG(x) 0
  36. /* disable TQM_BYPASS */
  37. #define TQM_BYPASS_WAR 0
  38. /* invalid peer id for reinject*/
  39. #define DP_INVALID_PEER 0XFFFE
  40. /*mapping between hal encrypt type and cdp_sec_type*/
  41. #define MAX_CDP_SEC_TYPE 12
  42. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  43. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  44. HAL_TX_ENCRYPT_TYPE_WEP_128,
  45. HAL_TX_ENCRYPT_TYPE_WEP_104,
  46. HAL_TX_ENCRYPT_TYPE_WEP_40,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  48. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  49. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  50. HAL_TX_ENCRYPT_TYPE_WAPI,
  51. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  53. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  54. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  55. /**
  56. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  57. * @vdev: DP Virtual device handle
  58. * @nbuf: Buffer pointer
  59. * @queue: queue ids container for nbuf
  60. *
  61. * TX packet queue has 2 instances, software descriptors id and dma ring id
  62. * Based on tx feature and hardware configuration queue id combination could be
  63. * different.
  64. * For example -
  65. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  66. * With no XPS,lock based resource protection, Descriptor pool ids are different
  67. * for each vdev, dma ring id will be same as single pdev id
  68. *
  69. * Return: None
  70. */
  71. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  72. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  73. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  74. {
  75. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  76. queue->desc_pool_id = queue_offset;
  77. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  79. "%s, pool_id:%d ring_id: %d",
  80. __func__, queue->desc_pool_id, queue->ring_id);
  81. return;
  82. }
  83. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  84. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  85. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  86. {
  87. /* get flow id */
  88. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  89. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  91. "%s, pool_id:%d ring_id: %d",
  92. __func__, queue->desc_pool_id, queue->ring_id);
  93. return;
  94. }
  95. #endif
  96. #if defined(FEATURE_TSO)
  97. /**
  98. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  99. *
  100. * @soc - core txrx main context
  101. * @seg_desc - tso segment descriptor
  102. * @num_seg_desc - tso number segment descriptor
  103. */
  104. static void dp_tx_tso_unmap_segment(
  105. struct dp_soc *soc,
  106. struct qdf_tso_seg_elem_t *seg_desc,
  107. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  108. {
  109. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  110. if (qdf_unlikely(!seg_desc)) {
  111. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  112. __func__, __LINE__);
  113. qdf_assert(0);
  114. } else if (qdf_unlikely(!num_seg_desc)) {
  115. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  116. __func__, __LINE__);
  117. qdf_assert(0);
  118. } else {
  119. bool is_last_seg;
  120. /* no tso segment left to do dma unmap */
  121. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  122. return;
  123. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  124. true : false;
  125. qdf_nbuf_unmap_tso_segment(soc->osdev,
  126. seg_desc, is_last_seg);
  127. num_seg_desc->num_seg.tso_cmn_num_seg--;
  128. }
  129. }
  130. /**
  131. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  132. * back to the freelist
  133. *
  134. * @soc - soc device handle
  135. * @tx_desc - Tx software descriptor
  136. */
  137. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  138. struct dp_tx_desc_s *tx_desc)
  139. {
  140. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  141. if (qdf_unlikely(!tx_desc->tso_desc)) {
  142. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  143. "%s %d TSO desc is NULL!",
  144. __func__, __LINE__);
  145. qdf_assert(0);
  146. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  147. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  148. "%s %d TSO num desc is NULL!",
  149. __func__, __LINE__);
  150. qdf_assert(0);
  151. } else {
  152. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  153. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  154. /* Add the tso num segment into the free list */
  155. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  156. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  157. tx_desc->tso_num_desc);
  158. tx_desc->tso_num_desc = NULL;
  159. }
  160. /* Add the tso segment into the free list*/
  161. dp_tx_tso_desc_free(soc,
  162. tx_desc->pool_id, tx_desc->tso_desc);
  163. tx_desc->tso_desc = NULL;
  164. }
  165. }
  166. #else
  167. static void dp_tx_tso_unmap_segment(
  168. struct dp_soc *soc,
  169. struct qdf_tso_seg_elem_t *seg_desc,
  170. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  171. {
  172. }
  173. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  174. struct dp_tx_desc_s *tx_desc)
  175. {
  176. }
  177. #endif
  178. /**
  179. * dp_tx_desc_release() - Release Tx Descriptor
  180. * @tx_desc : Tx Descriptor
  181. * @desc_pool_id: Descriptor Pool ID
  182. *
  183. * Deallocate all resources attached to Tx descriptor and free the Tx
  184. * descriptor.
  185. *
  186. * Return:
  187. */
  188. static void
  189. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  190. {
  191. struct dp_pdev *pdev = tx_desc->pdev;
  192. struct dp_soc *soc;
  193. uint8_t comp_status = 0;
  194. qdf_assert(pdev);
  195. soc = pdev->soc;
  196. if (tx_desc->frm_type == dp_tx_frm_tso)
  197. dp_tx_tso_desc_release(soc, tx_desc);
  198. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  199. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  200. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  201. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  202. qdf_atomic_dec(&pdev->num_tx_outstanding);
  203. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  204. qdf_atomic_dec(&pdev->num_tx_exception);
  205. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  206. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  207. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  208. soc->hal_soc);
  209. else
  210. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  212. "Tx Completion Release desc %d status %d outstanding %d",
  213. tx_desc->id, comp_status,
  214. qdf_atomic_read(&pdev->num_tx_outstanding));
  215. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  216. return;
  217. }
  218. /**
  219. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  220. * @vdev: DP vdev Handle
  221. * @nbuf: skb
  222. *
  223. * Prepares and fills HTT metadata in the frame pre-header for special frames
  224. * that should be transmitted using varying transmit parameters.
  225. * There are 2 VDEV modes that currently needs this special metadata -
  226. * 1) Mesh Mode
  227. * 2) DSRC Mode
  228. *
  229. * Return: HTT metadata size
  230. *
  231. */
  232. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  233. uint32_t *meta_data)
  234. {
  235. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  236. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  237. uint8_t htt_desc_size;
  238. /* Size rounded of multiple of 8 bytes */
  239. uint8_t htt_desc_size_aligned;
  240. uint8_t *hdr = NULL;
  241. /*
  242. * Metadata - HTT MSDU Extension header
  243. */
  244. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  245. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  246. if (vdev->mesh_vdev) {
  247. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  248. htt_desc_size_aligned)) {
  249. DP_STATS_INC(vdev,
  250. tx_i.dropped.headroom_insufficient, 1);
  251. return 0;
  252. }
  253. /* Fill and add HTT metaheader */
  254. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  255. if (hdr == NULL) {
  256. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  257. "Error in filling HTT metadata");
  258. return 0;
  259. }
  260. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  261. } else if (vdev->opmode == wlan_op_mode_ocb) {
  262. /* Todo - Add support for DSRC */
  263. }
  264. return htt_desc_size_aligned;
  265. }
  266. /**
  267. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  268. * @tso_seg: TSO segment to process
  269. * @ext_desc: Pointer to MSDU extension descriptor
  270. *
  271. * Return: void
  272. */
  273. #if defined(FEATURE_TSO)
  274. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  275. void *ext_desc)
  276. {
  277. uint8_t num_frag;
  278. uint32_t tso_flags;
  279. /*
  280. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  281. * tcp_flag_mask
  282. *
  283. * Checksum enable flags are set in TCL descriptor and not in Extension
  284. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  285. */
  286. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  287. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  288. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  289. tso_seg->tso_flags.ip_len);
  290. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  291. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  292. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  293. uint32_t lo = 0;
  294. uint32_t hi = 0;
  295. qdf_dmaaddr_to_32s(
  296. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  297. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  298. tso_seg->tso_frags[num_frag].length);
  299. }
  300. return;
  301. }
  302. #else
  303. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  304. void *ext_desc)
  305. {
  306. return;
  307. }
  308. #endif
  309. #if defined(FEATURE_TSO)
  310. /**
  311. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  312. * allocated and free them
  313. *
  314. * @soc: soc handle
  315. * @free_seg: list of tso segments
  316. * @msdu_info: msdu descriptor
  317. *
  318. * Return - void
  319. */
  320. static void dp_tx_free_tso_seg_list(
  321. struct dp_soc *soc,
  322. struct qdf_tso_seg_elem_t *free_seg,
  323. struct dp_tx_msdu_info_s *msdu_info)
  324. {
  325. struct qdf_tso_seg_elem_t *next_seg;
  326. while (free_seg) {
  327. next_seg = free_seg->next;
  328. dp_tx_tso_desc_free(soc,
  329. msdu_info->tx_queue.desc_pool_id,
  330. free_seg);
  331. free_seg = next_seg;
  332. }
  333. }
  334. /**
  335. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  336. * allocated and free them
  337. *
  338. * @soc: soc handle
  339. * @free_num_seg: list of tso number segments
  340. * @msdu_info: msdu descriptor
  341. * Return - void
  342. */
  343. static void dp_tx_free_tso_num_seg_list(
  344. struct dp_soc *soc,
  345. struct qdf_tso_num_seg_elem_t *free_num_seg,
  346. struct dp_tx_msdu_info_s *msdu_info)
  347. {
  348. struct qdf_tso_num_seg_elem_t *next_num_seg;
  349. while (free_num_seg) {
  350. next_num_seg = free_num_seg->next;
  351. dp_tso_num_seg_free(soc,
  352. msdu_info->tx_queue.desc_pool_id,
  353. free_num_seg);
  354. free_num_seg = next_num_seg;
  355. }
  356. }
  357. /**
  358. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  359. * do dma unmap for each segment
  360. *
  361. * @soc: soc handle
  362. * @free_seg: list of tso segments
  363. * @num_seg_desc: tso number segment descriptor
  364. *
  365. * Return - void
  366. */
  367. static void dp_tx_unmap_tso_seg_list(
  368. struct dp_soc *soc,
  369. struct qdf_tso_seg_elem_t *free_seg,
  370. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  371. {
  372. struct qdf_tso_seg_elem_t *next_seg;
  373. if (qdf_unlikely(!num_seg_desc)) {
  374. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  375. return;
  376. }
  377. while (free_seg) {
  378. next_seg = free_seg->next;
  379. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  380. free_seg = next_seg;
  381. }
  382. }
  383. /**
  384. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  385. * free the tso segments descriptor and
  386. * tso num segments descriptor
  387. *
  388. * @soc: soc handle
  389. * @msdu_info: msdu descriptor
  390. * @tso_seg_unmap: flag to show if dma unmap is necessary
  391. *
  392. * Return - void
  393. */
  394. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  395. struct dp_tx_msdu_info_s *msdu_info,
  396. bool tso_seg_unmap)
  397. {
  398. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  399. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  400. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  401. tso_info->tso_num_seg_list;
  402. /* do dma unmap for each segment */
  403. if (tso_seg_unmap)
  404. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  405. /* free all tso number segment descriptor though looks only have 1 */
  406. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  407. /* free all tso segment descriptor */
  408. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  409. }
  410. /**
  411. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  412. * @vdev: virtual device handle
  413. * @msdu: network buffer
  414. * @msdu_info: meta data associated with the msdu
  415. *
  416. * Return: QDF_STATUS_SUCCESS success
  417. */
  418. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  419. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  420. {
  421. struct qdf_tso_seg_elem_t *tso_seg;
  422. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  423. struct dp_soc *soc = vdev->pdev->soc;
  424. struct qdf_tso_info_t *tso_info;
  425. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  426. tso_info = &msdu_info->u.tso_info;
  427. tso_info->curr_seg = NULL;
  428. tso_info->tso_seg_list = NULL;
  429. tso_info->num_segs = num_seg;
  430. msdu_info->frm_type = dp_tx_frm_tso;
  431. tso_info->tso_num_seg_list = NULL;
  432. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  433. while (num_seg) {
  434. tso_seg = dp_tx_tso_desc_alloc(
  435. soc, msdu_info->tx_queue.desc_pool_id);
  436. if (tso_seg) {
  437. tso_seg->next = tso_info->tso_seg_list;
  438. tso_info->tso_seg_list = tso_seg;
  439. num_seg--;
  440. } else {
  441. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  442. __func__);
  443. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  444. return QDF_STATUS_E_NOMEM;
  445. }
  446. }
  447. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  448. tso_num_seg = dp_tso_num_seg_alloc(soc,
  449. msdu_info->tx_queue.desc_pool_id);
  450. if (tso_num_seg) {
  451. tso_num_seg->next = tso_info->tso_num_seg_list;
  452. tso_info->tso_num_seg_list = tso_num_seg;
  453. } else {
  454. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  455. __func__);
  456. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  457. return QDF_STATUS_E_NOMEM;
  458. }
  459. msdu_info->num_seg =
  460. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  461. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  462. msdu_info->num_seg);
  463. if (!(msdu_info->num_seg)) {
  464. /*
  465. * Free allocated TSO seg desc and number seg desc,
  466. * do unmap for segments if dma map has done.
  467. */
  468. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  469. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  470. return QDF_STATUS_E_INVAL;
  471. }
  472. tso_info->curr_seg = tso_info->tso_seg_list;
  473. return QDF_STATUS_SUCCESS;
  474. }
  475. #else
  476. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  477. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  478. {
  479. return QDF_STATUS_E_NOMEM;
  480. }
  481. #endif
  482. /**
  483. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  484. * @vdev: DP Vdev handle
  485. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  486. * @desc_pool_id: Descriptor Pool ID
  487. *
  488. * Return:
  489. */
  490. static
  491. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  492. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  493. {
  494. uint8_t i;
  495. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  496. struct dp_tx_seg_info_s *seg_info;
  497. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  498. struct dp_soc *soc = vdev->pdev->soc;
  499. /* Allocate an extension descriptor */
  500. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  501. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  502. if (!msdu_ext_desc) {
  503. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  504. return NULL;
  505. }
  506. if (msdu_info->exception_fw &&
  507. qdf_unlikely(vdev->mesh_vdev)) {
  508. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  509. &msdu_info->meta_data[0],
  510. sizeof(struct htt_tx_msdu_desc_ext2_t));
  511. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  512. }
  513. switch (msdu_info->frm_type) {
  514. case dp_tx_frm_sg:
  515. case dp_tx_frm_me:
  516. case dp_tx_frm_raw:
  517. seg_info = msdu_info->u.sg_info.curr_seg;
  518. /* Update the buffer pointers in MSDU Extension Descriptor */
  519. for (i = 0; i < seg_info->frag_cnt; i++) {
  520. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  521. seg_info->frags[i].paddr_lo,
  522. seg_info->frags[i].paddr_hi,
  523. seg_info->frags[i].len);
  524. }
  525. break;
  526. case dp_tx_frm_tso:
  527. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  528. &cached_ext_desc[0]);
  529. break;
  530. default:
  531. break;
  532. }
  533. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  534. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  535. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  536. msdu_ext_desc->vaddr);
  537. return msdu_ext_desc;
  538. }
  539. /**
  540. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  541. *
  542. * @skb: skb to be traced
  543. * @msdu_id: msdu_id of the packet
  544. * @vdev_id: vdev_id of the packet
  545. *
  546. * Return: None
  547. */
  548. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  549. uint8_t vdev_id)
  550. {
  551. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  552. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  553. DPTRACE(qdf_dp_trace_ptr(skb,
  554. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  555. QDF_TRACE_DEFAULT_PDEV_ID,
  556. qdf_nbuf_data_addr(skb),
  557. sizeof(qdf_nbuf_data(skb)),
  558. msdu_id, vdev_id));
  559. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  560. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  561. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  562. msdu_id, QDF_TX));
  563. }
  564. /**
  565. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  566. * @vdev: DP vdev handle
  567. * @nbuf: skb
  568. * @desc_pool_id: Descriptor pool ID
  569. * @meta_data: Metadata to the fw
  570. * @tx_exc_metadata: Handle that holds exception path metadata
  571. * Allocate and prepare Tx descriptor with msdu information.
  572. *
  573. * Return: Pointer to Tx Descriptor on success,
  574. * NULL on failure
  575. */
  576. static
  577. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  578. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  579. struct dp_tx_msdu_info_s *msdu_info,
  580. struct cdp_tx_exception_metadata *tx_exc_metadata)
  581. {
  582. uint8_t align_pad;
  583. uint8_t is_exception = 0;
  584. uint8_t htt_hdr_size;
  585. qdf_ether_header_t *eh;
  586. struct dp_tx_desc_s *tx_desc;
  587. struct dp_pdev *pdev = vdev->pdev;
  588. struct dp_soc *soc = pdev->soc;
  589. /* Allocate software Tx descriptor */
  590. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  591. if (qdf_unlikely(!tx_desc)) {
  592. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  593. return NULL;
  594. }
  595. /* Flow control/Congestion Control counters */
  596. qdf_atomic_inc(&pdev->num_tx_outstanding);
  597. /* Initialize the SW tx descriptor */
  598. tx_desc->nbuf = nbuf;
  599. tx_desc->frm_type = dp_tx_frm_std;
  600. tx_desc->tx_encap_type = (tx_exc_metadata ?
  601. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  602. tx_desc->vdev = vdev;
  603. tx_desc->pdev = pdev;
  604. tx_desc->msdu_ext_desc = NULL;
  605. tx_desc->pkt_offset = 0;
  606. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  607. /*
  608. * For special modes (vdev_type == ocb or mesh), data frames should be
  609. * transmitted using varying transmit parameters (tx spec) which include
  610. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  611. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  612. * These frames are sent as exception packets to firmware.
  613. *
  614. * HW requirement is that metadata should always point to a
  615. * 8-byte aligned address. So we add alignment pad to start of buffer.
  616. * HTT Metadata should be ensured to be multiple of 8-bytes,
  617. * to get 8-byte aligned start address along with align_pad added
  618. *
  619. * |-----------------------------|
  620. * | |
  621. * |-----------------------------| <-----Buffer Pointer Address given
  622. * | | ^ in HW descriptor (aligned)
  623. * | HTT Metadata | |
  624. * | | |
  625. * | | | Packet Offset given in descriptor
  626. * | | |
  627. * |-----------------------------| |
  628. * | Alignment Pad | v
  629. * |-----------------------------| <----- Actual buffer start address
  630. * | SKB Data | (Unaligned)
  631. * | |
  632. * | |
  633. * | |
  634. * | |
  635. * | |
  636. * |-----------------------------|
  637. */
  638. if (qdf_unlikely((msdu_info->exception_fw)) ||
  639. (vdev->opmode == wlan_op_mode_ocb)) {
  640. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  641. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  642. DP_STATS_INC(vdev,
  643. tx_i.dropped.headroom_insufficient, 1);
  644. goto failure;
  645. }
  646. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  647. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  648. "qdf_nbuf_push_head failed");
  649. goto failure;
  650. }
  651. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  652. msdu_info->meta_data);
  653. if (htt_hdr_size == 0)
  654. goto failure;
  655. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  656. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  657. is_exception = 1;
  658. }
  659. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  660. qdf_nbuf_map(soc->osdev, nbuf,
  661. QDF_DMA_TO_DEVICE))) {
  662. /* Handle failure */
  663. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  664. "qdf_nbuf_map failed");
  665. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  666. goto failure;
  667. }
  668. if (qdf_unlikely(vdev->nawds_enabled)) {
  669. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  670. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  671. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  672. is_exception = 1;
  673. }
  674. }
  675. #if !TQM_BYPASS_WAR
  676. if (is_exception || tx_exc_metadata)
  677. #endif
  678. {
  679. /* Temporary WAR due to TQM VP issues */
  680. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  681. qdf_atomic_inc(&pdev->num_tx_exception);
  682. }
  683. return tx_desc;
  684. failure:
  685. dp_tx_desc_release(tx_desc, desc_pool_id);
  686. return NULL;
  687. }
  688. /**
  689. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  690. * @vdev: DP vdev handle
  691. * @nbuf: skb
  692. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  693. * @desc_pool_id : Descriptor Pool ID
  694. *
  695. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  696. * information. For frames wth fragments, allocate and prepare
  697. * an MSDU extension descriptor
  698. *
  699. * Return: Pointer to Tx Descriptor on success,
  700. * NULL on failure
  701. */
  702. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  703. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  704. uint8_t desc_pool_id)
  705. {
  706. struct dp_tx_desc_s *tx_desc;
  707. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  708. struct dp_pdev *pdev = vdev->pdev;
  709. struct dp_soc *soc = pdev->soc;
  710. /* Allocate software Tx descriptor */
  711. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  712. if (!tx_desc) {
  713. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  714. return NULL;
  715. }
  716. /* Flow control/Congestion Control counters */
  717. qdf_atomic_inc(&pdev->num_tx_outstanding);
  718. /* Initialize the SW tx descriptor */
  719. tx_desc->nbuf = nbuf;
  720. tx_desc->frm_type = msdu_info->frm_type;
  721. tx_desc->tx_encap_type = vdev->tx_encap_type;
  722. tx_desc->vdev = vdev;
  723. tx_desc->pdev = pdev;
  724. tx_desc->pkt_offset = 0;
  725. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  726. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  727. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  728. /* Handle scattered frames - TSO/SG/ME */
  729. /* Allocate and prepare an extension descriptor for scattered frames */
  730. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  731. if (!msdu_ext_desc) {
  732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  733. "%s Tx Extension Descriptor Alloc Fail",
  734. __func__);
  735. goto failure;
  736. }
  737. #if TQM_BYPASS_WAR
  738. /* Temporary WAR due to TQM VP issues */
  739. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  740. qdf_atomic_inc(&pdev->num_tx_exception);
  741. #endif
  742. if (qdf_unlikely(msdu_info->exception_fw))
  743. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  744. tx_desc->msdu_ext_desc = msdu_ext_desc;
  745. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  746. return tx_desc;
  747. failure:
  748. dp_tx_desc_release(tx_desc, desc_pool_id);
  749. return NULL;
  750. }
  751. /**
  752. * dp_tx_prepare_raw() - Prepare RAW packet TX
  753. * @vdev: DP vdev handle
  754. * @nbuf: buffer pointer
  755. * @seg_info: Pointer to Segment info Descriptor to be prepared
  756. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  757. * descriptor
  758. *
  759. * Return:
  760. */
  761. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  762. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  763. {
  764. qdf_nbuf_t curr_nbuf = NULL;
  765. uint16_t total_len = 0;
  766. qdf_dma_addr_t paddr;
  767. int32_t i;
  768. int32_t mapped_buf_num = 0;
  769. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  770. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  771. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  772. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  773. if (vdev->raw_mode_war &&
  774. (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS))
  775. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  776. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  777. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  778. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  779. QDF_DMA_TO_DEVICE)) {
  780. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  781. "%s dma map error ", __func__);
  782. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  783. mapped_buf_num = i;
  784. goto error;
  785. }
  786. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  787. seg_info->frags[i].paddr_lo = paddr;
  788. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  789. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  790. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  791. total_len += qdf_nbuf_len(curr_nbuf);
  792. }
  793. seg_info->frag_cnt = i;
  794. seg_info->total_len = total_len;
  795. seg_info->next = NULL;
  796. sg_info->curr_seg = seg_info;
  797. msdu_info->frm_type = dp_tx_frm_raw;
  798. msdu_info->num_seg = 1;
  799. return nbuf;
  800. error:
  801. i = 0;
  802. while (nbuf) {
  803. curr_nbuf = nbuf;
  804. if (i < mapped_buf_num) {
  805. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  806. i++;
  807. }
  808. nbuf = qdf_nbuf_next(nbuf);
  809. qdf_nbuf_free(curr_nbuf);
  810. }
  811. return NULL;
  812. }
  813. /**
  814. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  815. * @soc: DP Soc Handle
  816. * @vdev: DP vdev handle
  817. * @tx_desc: Tx Descriptor Handle
  818. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  819. * @fw_metadata: Metadata to send to Target Firmware along with frame
  820. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  821. * @tx_exc_metadata: Handle that holds exception path meta data
  822. *
  823. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  824. * from software Tx descriptor
  825. *
  826. * Return:
  827. */
  828. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  829. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  830. uint16_t fw_metadata, uint8_t ring_id,
  831. struct cdp_tx_exception_metadata
  832. *tx_exc_metadata)
  833. {
  834. uint8_t type;
  835. uint16_t length;
  836. void *hal_tx_desc, *hal_tx_desc_cached;
  837. qdf_dma_addr_t dma_addr;
  838. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  839. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  840. tx_exc_metadata->sec_type : vdev->sec_type);
  841. /* Return Buffer Manager ID */
  842. uint8_t bm_id = ring_id;
  843. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  844. hal_tx_desc_cached = (void *) cached_desc;
  845. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  846. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  847. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  848. type = HAL_TX_BUF_TYPE_EXT_DESC;
  849. dma_addr = tx_desc->msdu_ext_desc->paddr;
  850. } else {
  851. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  852. type = HAL_TX_BUF_TYPE_BUFFER;
  853. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  854. }
  855. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  856. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  857. dma_addr, bm_id, tx_desc->id,
  858. type, soc->hal_soc);
  859. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  860. return QDF_STATUS_E_RESOURCES;
  861. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  862. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  863. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  864. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  865. vdev->pdev->lmac_id);
  866. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  867. vdev->search_type);
  868. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  869. vdev->bss_ast_hash);
  870. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  871. vdev->dscp_tid_map_id);
  872. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  873. sec_type_map[sec_type]);
  874. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  875. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  876. __func__, length, type, (uint64_t)dma_addr,
  877. tx_desc->pkt_offset, tx_desc->id);
  878. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  879. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  880. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  881. vdev->hal_desc_addr_search_flags);
  882. /* verify checksum offload configuration*/
  883. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  884. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  885. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  886. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  887. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  888. }
  889. if (tid != HTT_TX_EXT_TID_INVALID)
  890. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  891. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  892. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  893. /* Sync cached descriptor with HW */
  894. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  895. if (!hal_tx_desc) {
  896. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  897. "%s TCL ring full ring_id:%d", __func__, ring_id);
  898. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  899. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  900. return QDF_STATUS_E_RESOURCES;
  901. }
  902. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  903. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  904. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  905. return QDF_STATUS_SUCCESS;
  906. }
  907. /**
  908. * dp_cce_classify() - Classify the frame based on CCE rules
  909. * @vdev: DP vdev handle
  910. * @nbuf: skb
  911. *
  912. * Classify frames based on CCE rules
  913. * Return: bool( true if classified,
  914. * else false)
  915. */
  916. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  917. {
  918. qdf_ether_header_t *eh = NULL;
  919. uint16_t ether_type;
  920. qdf_llc_t *llcHdr;
  921. qdf_nbuf_t nbuf_clone = NULL;
  922. qdf_dot3_qosframe_t *qos_wh = NULL;
  923. /* for mesh packets don't do any classification */
  924. if (qdf_unlikely(vdev->mesh_vdev))
  925. return false;
  926. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  927. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  928. ether_type = eh->ether_type;
  929. llcHdr = (qdf_llc_t *)(nbuf->data +
  930. sizeof(qdf_ether_header_t));
  931. } else {
  932. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  933. /* For encrypted packets don't do any classification */
  934. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  935. return false;
  936. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  937. if (qdf_unlikely(
  938. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  939. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  940. ether_type = *(uint16_t *)(nbuf->data
  941. + QDF_IEEE80211_4ADDR_HDR_LEN
  942. + sizeof(qdf_llc_t)
  943. - sizeof(ether_type));
  944. llcHdr = (qdf_llc_t *)(nbuf->data +
  945. QDF_IEEE80211_4ADDR_HDR_LEN);
  946. } else {
  947. ether_type = *(uint16_t *)(nbuf->data
  948. + QDF_IEEE80211_3ADDR_HDR_LEN
  949. + sizeof(qdf_llc_t)
  950. - sizeof(ether_type));
  951. llcHdr = (qdf_llc_t *)(nbuf->data +
  952. QDF_IEEE80211_3ADDR_HDR_LEN);
  953. }
  954. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  955. && (ether_type ==
  956. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  957. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  958. return true;
  959. }
  960. }
  961. return false;
  962. }
  963. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  964. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  965. sizeof(*llcHdr));
  966. nbuf_clone = qdf_nbuf_clone(nbuf);
  967. if (qdf_unlikely(nbuf_clone)) {
  968. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  969. if (ether_type == htons(ETHERTYPE_VLAN)) {
  970. qdf_nbuf_pull_head(nbuf_clone,
  971. sizeof(qdf_net_vlanhdr_t));
  972. }
  973. }
  974. } else {
  975. if (ether_type == htons(ETHERTYPE_VLAN)) {
  976. nbuf_clone = qdf_nbuf_clone(nbuf);
  977. if (qdf_unlikely(nbuf_clone)) {
  978. qdf_nbuf_pull_head(nbuf_clone,
  979. sizeof(qdf_net_vlanhdr_t));
  980. }
  981. }
  982. }
  983. if (qdf_unlikely(nbuf_clone))
  984. nbuf = nbuf_clone;
  985. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  986. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  987. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  988. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  989. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  990. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  991. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  992. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  993. if (qdf_unlikely(nbuf_clone != NULL))
  994. qdf_nbuf_free(nbuf_clone);
  995. return true;
  996. }
  997. if (qdf_unlikely(nbuf_clone != NULL))
  998. qdf_nbuf_free(nbuf_clone);
  999. return false;
  1000. }
  1001. /**
  1002. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1003. * @vdev: DP vdev handle
  1004. * @nbuf: skb
  1005. *
  1006. * Extract the DSCP or PCP information from frame and map into TID value.
  1007. * Software based TID classification is required when more than 2 DSCP-TID
  1008. * mapping tables are needed.
  1009. * Hardware supports 2 DSCP-TID mapping tables
  1010. *
  1011. * Return: void
  1012. */
  1013. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1014. struct dp_tx_msdu_info_s *msdu_info)
  1015. {
  1016. uint8_t tos = 0, dscp_tid_override = 0;
  1017. uint8_t *hdr_ptr, *L3datap;
  1018. uint8_t is_mcast = 0;
  1019. qdf_ether_header_t *eh = NULL;
  1020. qdf_ethervlan_header_t *evh = NULL;
  1021. uint16_t ether_type;
  1022. qdf_llc_t *llcHdr;
  1023. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1024. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1025. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1026. return;
  1027. /* for mesh packets don't do any classification */
  1028. if (qdf_unlikely(vdev->mesh_vdev))
  1029. return;
  1030. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1031. eh = (qdf_ether_header_t *)nbuf->data;
  1032. hdr_ptr = eh->ether_dhost;
  1033. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1034. } else {
  1035. qdf_dot3_qosframe_t *qos_wh =
  1036. (qdf_dot3_qosframe_t *) nbuf->data;
  1037. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1038. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1039. return;
  1040. }
  1041. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1042. ether_type = eh->ether_type;
  1043. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1044. /*
  1045. * Check if packet is dot3 or eth2 type.
  1046. */
  1047. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1048. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  1049. sizeof(*llcHdr));
  1050. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1051. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1052. sizeof(*llcHdr);
  1053. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  1054. + sizeof(*llcHdr) +
  1055. sizeof(qdf_net_vlanhdr_t));
  1056. } else {
  1057. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1058. sizeof(*llcHdr);
  1059. }
  1060. } else {
  1061. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1062. evh = (qdf_ethervlan_header_t *) eh;
  1063. ether_type = evh->ether_type;
  1064. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1065. }
  1066. }
  1067. /*
  1068. * Find priority from IP TOS DSCP field
  1069. */
  1070. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1071. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1072. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1073. /* Only for unicast frames */
  1074. if (!is_mcast) {
  1075. /* send it on VO queue */
  1076. msdu_info->tid = DP_VO_TID;
  1077. }
  1078. } else {
  1079. /*
  1080. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1081. * from TOS byte.
  1082. */
  1083. tos = ip->ip_tos;
  1084. dscp_tid_override = 1;
  1085. }
  1086. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1087. /* TODO
  1088. * use flowlabel
  1089. *igmpmld cases to be handled in phase 2
  1090. */
  1091. unsigned long ver_pri_flowlabel;
  1092. unsigned long pri;
  1093. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1094. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1095. DP_IPV6_PRIORITY_SHIFT;
  1096. tos = pri;
  1097. dscp_tid_override = 1;
  1098. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1099. msdu_info->tid = DP_VO_TID;
  1100. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1101. /* Only for unicast frames */
  1102. if (!is_mcast) {
  1103. /* send ucast arp on VO queue */
  1104. msdu_info->tid = DP_VO_TID;
  1105. }
  1106. }
  1107. /*
  1108. * Assign all MCAST packets to BE
  1109. */
  1110. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1111. if (is_mcast) {
  1112. tos = 0;
  1113. dscp_tid_override = 1;
  1114. }
  1115. }
  1116. if (dscp_tid_override == 1) {
  1117. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1118. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1119. }
  1120. return;
  1121. }
  1122. #ifdef FEATURE_WLAN_TDLS
  1123. /**
  1124. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1125. * @tx_desc: TX descriptor
  1126. *
  1127. * Return: None
  1128. */
  1129. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1130. {
  1131. if (tx_desc->vdev) {
  1132. if (tx_desc->vdev->is_tdls_frame) {
  1133. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1134. tx_desc->vdev->is_tdls_frame = false;
  1135. }
  1136. }
  1137. }
  1138. /**
  1139. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1140. * @tx_desc: TX descriptor
  1141. * @vdev: datapath vdev handle
  1142. *
  1143. * Return: None
  1144. */
  1145. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1146. struct dp_vdev *vdev)
  1147. {
  1148. struct hal_tx_completion_status ts = {0};
  1149. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1150. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1151. if (vdev->tx_non_std_data_callback.func) {
  1152. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1153. vdev->tx_non_std_data_callback.func(
  1154. vdev->tx_non_std_data_callback.ctxt,
  1155. nbuf, ts.status);
  1156. return;
  1157. }
  1158. }
  1159. #else
  1160. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1161. {
  1162. }
  1163. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1164. struct dp_vdev *vdev)
  1165. {
  1166. }
  1167. #endif
  1168. /**
  1169. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1170. * @vdev: DP vdev handle
  1171. * @nbuf: skb
  1172. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1173. * @meta_data: Metadata to the fw
  1174. * @tx_q: Tx queue to be used for this Tx frame
  1175. * @peer_id: peer_id of the peer in case of NAWDS frames
  1176. * @tx_exc_metadata: Handle that holds exception path metadata
  1177. *
  1178. * Return: NULL on success,
  1179. * nbuf when it fails to send
  1180. */
  1181. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1182. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1183. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1184. {
  1185. struct dp_pdev *pdev = vdev->pdev;
  1186. struct dp_soc *soc = pdev->soc;
  1187. struct dp_tx_desc_s *tx_desc;
  1188. QDF_STATUS status;
  1189. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1190. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1191. uint16_t htt_tcl_metadata = 0;
  1192. uint8_t tid = msdu_info->tid;
  1193. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1194. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1195. msdu_info, tx_exc_metadata);
  1196. if (!tx_desc) {
  1197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1198. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1199. __func__, vdev, tx_q->desc_pool_id);
  1200. return nbuf;
  1201. }
  1202. if (qdf_unlikely(soc->cce_disable)) {
  1203. if (dp_cce_classify(vdev, nbuf) == true) {
  1204. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1205. tid = DP_VO_TID;
  1206. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1207. }
  1208. }
  1209. dp_tx_update_tdls_flags(tx_desc);
  1210. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1211. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1212. "%s %d : HAL RING Access Failed -- %pK",
  1213. __func__, __LINE__, hal_srng);
  1214. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1215. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1216. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1217. goto fail_return;
  1218. }
  1219. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1220. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1221. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1222. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1223. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1224. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1225. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1226. peer_id);
  1227. } else
  1228. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1229. if (msdu_info->exception_fw) {
  1230. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1231. }
  1232. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1233. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1234. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1235. if (status != QDF_STATUS_SUCCESS) {
  1236. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1237. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1238. __func__, tx_desc, tx_q->ring_id);
  1239. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1240. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1241. goto fail_return;
  1242. }
  1243. nbuf = NULL;
  1244. fail_return:
  1245. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1246. hal_srng_access_end(soc->hal_soc, hal_srng);
  1247. hif_pm_runtime_put(soc->hif_handle);
  1248. } else {
  1249. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1250. }
  1251. return nbuf;
  1252. }
  1253. /**
  1254. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1255. * @vdev: DP vdev handle
  1256. * @nbuf: skb
  1257. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1258. *
  1259. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1260. *
  1261. * Return: NULL on success,
  1262. * nbuf when it fails to send
  1263. */
  1264. #if QDF_LOCK_STATS
  1265. static noinline
  1266. #else
  1267. static
  1268. #endif
  1269. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1270. struct dp_tx_msdu_info_s *msdu_info)
  1271. {
  1272. uint8_t i;
  1273. struct dp_pdev *pdev = vdev->pdev;
  1274. struct dp_soc *soc = pdev->soc;
  1275. struct dp_tx_desc_s *tx_desc;
  1276. bool is_cce_classified = false;
  1277. QDF_STATUS status;
  1278. uint16_t htt_tcl_metadata = 0;
  1279. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1280. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1281. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1282. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1283. "%s %d : HAL RING Access Failed -- %pK",
  1284. __func__, __LINE__, hal_srng);
  1285. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1286. return nbuf;
  1287. }
  1288. if (qdf_unlikely(soc->cce_disable)) {
  1289. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1290. if (is_cce_classified) {
  1291. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1292. msdu_info->tid = DP_VO_TID;
  1293. }
  1294. }
  1295. if (msdu_info->frm_type == dp_tx_frm_me)
  1296. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1297. i = 0;
  1298. /* Print statement to track i and num_seg */
  1299. /*
  1300. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1301. * descriptors using information in msdu_info
  1302. */
  1303. while (i < msdu_info->num_seg) {
  1304. /*
  1305. * Setup Tx descriptor for an MSDU, and MSDU extension
  1306. * descriptor
  1307. */
  1308. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1309. tx_q->desc_pool_id);
  1310. if (!tx_desc) {
  1311. if (msdu_info->frm_type == dp_tx_frm_me) {
  1312. dp_tx_me_free_buf(pdev,
  1313. (void *)(msdu_info->u.sg_info
  1314. .curr_seg->frags[0].vaddr));
  1315. }
  1316. goto done;
  1317. }
  1318. if (msdu_info->frm_type == dp_tx_frm_me) {
  1319. tx_desc->me_buffer =
  1320. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1321. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1322. }
  1323. if (is_cce_classified)
  1324. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1325. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1326. if (msdu_info->exception_fw) {
  1327. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1328. }
  1329. /*
  1330. * Enqueue the Tx MSDU descriptor to HW for transmit
  1331. */
  1332. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1333. htt_tcl_metadata, tx_q->ring_id, NULL);
  1334. if (status != QDF_STATUS_SUCCESS) {
  1335. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1336. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1337. __func__, tx_desc, tx_q->ring_id);
  1338. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1339. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1340. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1341. goto done;
  1342. }
  1343. /*
  1344. * TODO
  1345. * if tso_info structure can be modified to have curr_seg
  1346. * as first element, following 2 blocks of code (for TSO and SG)
  1347. * can be combined into 1
  1348. */
  1349. /*
  1350. * For frames with multiple segments (TSO, ME), jump to next
  1351. * segment.
  1352. */
  1353. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1354. if (msdu_info->u.tso_info.curr_seg->next) {
  1355. msdu_info->u.tso_info.curr_seg =
  1356. msdu_info->u.tso_info.curr_seg->next;
  1357. /*
  1358. * If this is a jumbo nbuf, then increment the number of
  1359. * nbuf users for each additional segment of the msdu.
  1360. * This will ensure that the skb is freed only after
  1361. * receiving tx completion for all segments of an nbuf
  1362. */
  1363. qdf_nbuf_inc_users(nbuf);
  1364. /* Check with MCL if this is needed */
  1365. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1366. }
  1367. }
  1368. /*
  1369. * For Multicast-Unicast converted packets,
  1370. * each converted frame (for a client) is represented as
  1371. * 1 segment
  1372. */
  1373. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1374. (msdu_info->frm_type == dp_tx_frm_me)) {
  1375. if (msdu_info->u.sg_info.curr_seg->next) {
  1376. msdu_info->u.sg_info.curr_seg =
  1377. msdu_info->u.sg_info.curr_seg->next;
  1378. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1379. }
  1380. }
  1381. i++;
  1382. }
  1383. nbuf = NULL;
  1384. done:
  1385. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1386. hal_srng_access_end(soc->hal_soc, hal_srng);
  1387. hif_pm_runtime_put(soc->hif_handle);
  1388. } else {
  1389. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1390. }
  1391. return nbuf;
  1392. }
  1393. /**
  1394. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1395. * for SG frames
  1396. * @vdev: DP vdev handle
  1397. * @nbuf: skb
  1398. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1399. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1400. *
  1401. * Return: NULL on success,
  1402. * nbuf when it fails to send
  1403. */
  1404. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1405. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1406. {
  1407. uint32_t cur_frag, nr_frags;
  1408. qdf_dma_addr_t paddr;
  1409. struct dp_tx_sg_info_s *sg_info;
  1410. sg_info = &msdu_info->u.sg_info;
  1411. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1412. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1413. QDF_DMA_TO_DEVICE)) {
  1414. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1415. "dma map error");
  1416. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1417. qdf_nbuf_free(nbuf);
  1418. return NULL;
  1419. }
  1420. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1421. seg_info->frags[0].paddr_lo = paddr;
  1422. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1423. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1424. seg_info->frags[0].vaddr = (void *) nbuf;
  1425. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1426. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1427. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1428. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1429. "frag dma map error");
  1430. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1431. qdf_nbuf_free(nbuf);
  1432. return NULL;
  1433. }
  1434. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1435. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1436. seg_info->frags[cur_frag + 1].paddr_hi =
  1437. ((uint64_t) paddr) >> 32;
  1438. seg_info->frags[cur_frag + 1].len =
  1439. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1440. }
  1441. seg_info->frag_cnt = (cur_frag + 1);
  1442. seg_info->total_len = qdf_nbuf_len(nbuf);
  1443. seg_info->next = NULL;
  1444. sg_info->curr_seg = seg_info;
  1445. msdu_info->frm_type = dp_tx_frm_sg;
  1446. msdu_info->num_seg = 1;
  1447. return nbuf;
  1448. }
  1449. #ifdef MESH_MODE_SUPPORT
  1450. /**
  1451. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1452. and prepare msdu_info for mesh frames.
  1453. * @vdev: DP vdev handle
  1454. * @nbuf: skb
  1455. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1456. *
  1457. * Return: NULL on failure,
  1458. * nbuf when extracted successfully
  1459. */
  1460. static
  1461. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1462. struct dp_tx_msdu_info_s *msdu_info)
  1463. {
  1464. struct meta_hdr_s *mhdr;
  1465. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1466. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1467. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1468. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1469. msdu_info->exception_fw = 0;
  1470. goto remove_meta_hdr;
  1471. }
  1472. msdu_info->exception_fw = 1;
  1473. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1474. meta_data->host_tx_desc_pool = 1;
  1475. meta_data->update_peer_cache = 1;
  1476. meta_data->learning_frame = 1;
  1477. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1478. meta_data->power = mhdr->power;
  1479. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1480. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1481. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1482. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1483. meta_data->dyn_bw = 1;
  1484. meta_data->valid_pwr = 1;
  1485. meta_data->valid_mcs_mask = 1;
  1486. meta_data->valid_nss_mask = 1;
  1487. meta_data->valid_preamble_type = 1;
  1488. meta_data->valid_retries = 1;
  1489. meta_data->valid_bw_info = 1;
  1490. }
  1491. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1492. meta_data->encrypt_type = 0;
  1493. meta_data->valid_encrypt_type = 1;
  1494. meta_data->learning_frame = 0;
  1495. }
  1496. meta_data->valid_key_flags = 1;
  1497. meta_data->key_flags = (mhdr->keyix & 0x3);
  1498. remove_meta_hdr:
  1499. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1500. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1501. "qdf_nbuf_pull_head failed");
  1502. qdf_nbuf_free(nbuf);
  1503. return NULL;
  1504. }
  1505. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1506. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1507. else
  1508. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1509. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1510. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1511. " tid %d to_fw %d",
  1512. __func__, msdu_info->meta_data[0],
  1513. msdu_info->meta_data[1],
  1514. msdu_info->meta_data[2],
  1515. msdu_info->meta_data[3],
  1516. msdu_info->meta_data[4],
  1517. msdu_info->meta_data[5],
  1518. msdu_info->tid, msdu_info->exception_fw);
  1519. return nbuf;
  1520. }
  1521. #else
  1522. static
  1523. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1524. struct dp_tx_msdu_info_s *msdu_info)
  1525. {
  1526. return nbuf;
  1527. }
  1528. #endif
  1529. #ifdef DP_FEATURE_NAWDS_TX
  1530. /**
  1531. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1532. * @vdev: dp_vdev handle
  1533. * @nbuf: skb
  1534. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1535. * @tx_q: Tx queue to be used for this Tx frame
  1536. * @meta_data: Meta date for mesh
  1537. * @peer_id: peer_id of the peer in case of NAWDS frames
  1538. *
  1539. * return: NULL on success nbuf on failure
  1540. */
  1541. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1542. struct dp_tx_msdu_info_s *msdu_info)
  1543. {
  1544. struct dp_peer *peer = NULL;
  1545. struct dp_soc *soc = vdev->pdev->soc;
  1546. struct dp_ast_entry *ast_entry = NULL;
  1547. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1548. uint16_t peer_id = HTT_INVALID_PEER;
  1549. struct dp_peer *sa_peer = NULL;
  1550. qdf_nbuf_t nbuf_copy;
  1551. qdf_spin_lock_bh(&(soc->ast_lock));
  1552. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1553. (soc,
  1554. (uint8_t *)(eh->ether_shost),
  1555. vdev->pdev->pdev_id);
  1556. if (ast_entry)
  1557. sa_peer = ast_entry->peer;
  1558. qdf_spin_unlock_bh(&(soc->ast_lock));
  1559. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1560. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1561. (peer->nawds_enabled)) {
  1562. if (sa_peer == peer) {
  1563. QDF_TRACE(QDF_MODULE_ID_DP,
  1564. QDF_TRACE_LEVEL_DEBUG,
  1565. " %s: broadcast multicast packet",
  1566. __func__);
  1567. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1568. continue;
  1569. }
  1570. nbuf_copy = qdf_nbuf_copy(nbuf);
  1571. if (!nbuf_copy) {
  1572. QDF_TRACE(QDF_MODULE_ID_DP,
  1573. QDF_TRACE_LEVEL_ERROR,
  1574. "nbuf copy failed");
  1575. }
  1576. peer_id = peer->peer_ids[0];
  1577. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1578. msdu_info, peer_id, NULL);
  1579. if (nbuf_copy != NULL) {
  1580. qdf_nbuf_free(nbuf_copy);
  1581. continue;
  1582. }
  1583. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1584. 1, qdf_nbuf_len(nbuf));
  1585. }
  1586. }
  1587. if (peer_id == HTT_INVALID_PEER)
  1588. return nbuf;
  1589. return NULL;
  1590. }
  1591. #endif
  1592. /**
  1593. * dp_check_exc_metadata() - Checks if parameters are valid
  1594. * @tx_exc - holds all exception path parameters
  1595. *
  1596. * Returns true when all the parameters are valid else false
  1597. *
  1598. */
  1599. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1600. {
  1601. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1602. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1603. tx_exc->sec_type > cdp_num_sec_types) {
  1604. return false;
  1605. }
  1606. return true;
  1607. }
  1608. /**
  1609. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1610. * @vap_dev: DP vdev handle
  1611. * @nbuf: skb
  1612. * @tx_exc_metadata: Handle that holds exception path meta data
  1613. *
  1614. * Entry point for Core Tx layer (DP_TX) invoked from
  1615. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1616. *
  1617. * Return: NULL on success,
  1618. * nbuf when it fails to send
  1619. */
  1620. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1621. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1622. {
  1623. qdf_ether_header_t *eh = NULL;
  1624. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1625. struct dp_tx_msdu_info_s msdu_info;
  1626. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1627. msdu_info.tid = tx_exc_metadata->tid;
  1628. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1629. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1630. "%s , skb %pM",
  1631. __func__, nbuf->data);
  1632. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1633. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1634. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1635. "Invalid parameters in exception path");
  1636. goto fail;
  1637. }
  1638. /* Basic sanity checks for unsupported packets */
  1639. /* MESH mode */
  1640. if (qdf_unlikely(vdev->mesh_vdev)) {
  1641. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1642. "Mesh mode is not supported in exception path");
  1643. goto fail;
  1644. }
  1645. /* TSO or SG */
  1646. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1647. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1648. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1649. "TSO and SG are not supported in exception path");
  1650. goto fail;
  1651. }
  1652. /* RAW */
  1653. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1654. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1655. "Raw frame is not supported in exception path");
  1656. goto fail;
  1657. }
  1658. /* Mcast enhancement*/
  1659. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1660. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1661. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1663. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1664. }
  1665. }
  1666. /*
  1667. * Get HW Queue to use for this frame.
  1668. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1669. * dedicated for data and 1 for command.
  1670. * "queue_id" maps to one hardware ring.
  1671. * With each ring, we also associate a unique Tx descriptor pool
  1672. * to minimize lock contention for these resources.
  1673. */
  1674. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1675. /* Single linear frame */
  1676. /*
  1677. * If nbuf is a simple linear frame, use send_single function to
  1678. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1679. * SRNG. There is no need to setup a MSDU extension descriptor.
  1680. */
  1681. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1682. tx_exc_metadata->peer_id, tx_exc_metadata);
  1683. return nbuf;
  1684. fail:
  1685. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1686. "pkt send failed");
  1687. return nbuf;
  1688. }
  1689. /**
  1690. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1691. * @vap_dev: DP vdev handle
  1692. * @nbuf: skb
  1693. *
  1694. * Entry point for Core Tx layer (DP_TX) invoked from
  1695. * hard_start_xmit in OSIF/HDD
  1696. *
  1697. * Return: NULL on success,
  1698. * nbuf when it fails to send
  1699. */
  1700. #ifdef MESH_MODE_SUPPORT
  1701. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1702. {
  1703. struct meta_hdr_s *mhdr;
  1704. qdf_nbuf_t nbuf_mesh = NULL;
  1705. qdf_nbuf_t nbuf_clone = NULL;
  1706. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1707. uint8_t no_enc_frame = 0;
  1708. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1709. if (nbuf_mesh == NULL) {
  1710. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1711. "qdf_nbuf_unshare failed");
  1712. return nbuf;
  1713. }
  1714. nbuf = nbuf_mesh;
  1715. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1716. if ((vdev->sec_type != cdp_sec_type_none) &&
  1717. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1718. no_enc_frame = 1;
  1719. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1720. !no_enc_frame) {
  1721. nbuf_clone = qdf_nbuf_clone(nbuf);
  1722. if (nbuf_clone == NULL) {
  1723. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1724. "qdf_nbuf_clone failed");
  1725. return nbuf;
  1726. }
  1727. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1728. }
  1729. if (nbuf_clone) {
  1730. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1731. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1732. } else {
  1733. qdf_nbuf_free(nbuf_clone);
  1734. }
  1735. }
  1736. if (no_enc_frame)
  1737. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1738. else
  1739. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1740. nbuf = dp_tx_send(vap_dev, nbuf);
  1741. if ((nbuf == NULL) && no_enc_frame) {
  1742. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1743. }
  1744. return nbuf;
  1745. }
  1746. #else
  1747. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1748. {
  1749. return dp_tx_send(vap_dev, nbuf);
  1750. }
  1751. #endif
  1752. /**
  1753. * dp_tx_send() - Transmit a frame on a given VAP
  1754. * @vap_dev: DP vdev handle
  1755. * @nbuf: skb
  1756. *
  1757. * Entry point for Core Tx layer (DP_TX) invoked from
  1758. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1759. * cases
  1760. *
  1761. * Return: NULL on success,
  1762. * nbuf when it fails to send
  1763. */
  1764. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1765. {
  1766. qdf_ether_header_t *eh = NULL;
  1767. struct dp_tx_msdu_info_s msdu_info;
  1768. struct dp_tx_seg_info_s seg_info;
  1769. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1770. uint16_t peer_id = HTT_INVALID_PEER;
  1771. qdf_nbuf_t nbuf_mesh = NULL;
  1772. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1773. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1774. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1775. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1776. "%s , skb %pM",
  1777. __func__, nbuf->data);
  1778. /*
  1779. * Set Default Host TID value to invalid TID
  1780. * (TID override disabled)
  1781. */
  1782. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1783. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1784. if (qdf_unlikely(vdev->mesh_vdev)) {
  1785. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1786. &msdu_info);
  1787. if (nbuf_mesh == NULL) {
  1788. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1789. "Extracting mesh metadata failed");
  1790. return nbuf;
  1791. }
  1792. nbuf = nbuf_mesh;
  1793. }
  1794. /*
  1795. * Get HW Queue to use for this frame.
  1796. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1797. * dedicated for data and 1 for command.
  1798. * "queue_id" maps to one hardware ring.
  1799. * With each ring, we also associate a unique Tx descriptor pool
  1800. * to minimize lock contention for these resources.
  1801. */
  1802. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1803. /*
  1804. * TCL H/W supports 2 DSCP-TID mapping tables.
  1805. * Table 1 - Default DSCP-TID mapping table
  1806. * Table 2 - 1 DSCP-TID override table
  1807. *
  1808. * If we need a different DSCP-TID mapping for this vap,
  1809. * call tid_classify to extract DSCP/ToS from frame and
  1810. * map to a TID and store in msdu_info. This is later used
  1811. * to fill in TCL Input descriptor (per-packet TID override).
  1812. */
  1813. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1814. /*
  1815. * Classify the frame and call corresponding
  1816. * "prepare" function which extracts the segment (TSO)
  1817. * and fragmentation information (for TSO , SG, ME, or Raw)
  1818. * into MSDU_INFO structure which is later used to fill
  1819. * SW and HW descriptors.
  1820. */
  1821. if (qdf_nbuf_is_tso(nbuf)) {
  1822. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1823. "%s TSO frame %pK", __func__, vdev);
  1824. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1825. qdf_nbuf_len(nbuf));
  1826. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1827. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1828. qdf_nbuf_len(nbuf));
  1829. return nbuf;
  1830. }
  1831. goto send_multiple;
  1832. }
  1833. /* SG */
  1834. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1835. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1836. if (!nbuf)
  1837. return NULL;
  1838. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1839. "%s non-TSO SG frame %pK", __func__, vdev);
  1840. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1841. qdf_nbuf_len(nbuf));
  1842. goto send_multiple;
  1843. }
  1844. #ifdef ATH_SUPPORT_IQUE
  1845. /* Mcast to Ucast Conversion*/
  1846. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1847. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1848. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1849. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1850. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1851. "%s Mcast frm for ME %pK", __func__, vdev);
  1852. DP_STATS_INC_PKT(vdev,
  1853. tx_i.mcast_en.mcast_pkt, 1,
  1854. qdf_nbuf_len(nbuf));
  1855. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1856. QDF_STATUS_SUCCESS) {
  1857. return NULL;
  1858. }
  1859. }
  1860. }
  1861. #endif
  1862. /* RAW */
  1863. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1864. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1865. if (nbuf == NULL)
  1866. return NULL;
  1867. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1868. "%s Raw frame %pK", __func__, vdev);
  1869. goto send_multiple;
  1870. }
  1871. /* Single linear frame */
  1872. /*
  1873. * If nbuf is a simple linear frame, use send_single function to
  1874. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1875. * SRNG. There is no need to setup a MSDU extension descriptor.
  1876. */
  1877. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1878. return nbuf;
  1879. send_multiple:
  1880. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1881. return nbuf;
  1882. }
  1883. /**
  1884. * dp_tx_reinject_handler() - Tx Reinject Handler
  1885. * @tx_desc: software descriptor head pointer
  1886. * @status : Tx completion status from HTT descriptor
  1887. *
  1888. * This function reinjects frames back to Target.
  1889. * Todo - Host queue needs to be added
  1890. *
  1891. * Return: none
  1892. */
  1893. static
  1894. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1895. {
  1896. struct dp_vdev *vdev;
  1897. struct dp_peer *peer = NULL;
  1898. uint32_t peer_id = HTT_INVALID_PEER;
  1899. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1900. qdf_nbuf_t nbuf_copy = NULL;
  1901. struct dp_tx_msdu_info_s msdu_info;
  1902. struct dp_peer *sa_peer = NULL;
  1903. struct dp_ast_entry *ast_entry = NULL;
  1904. struct dp_soc *soc = NULL;
  1905. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1906. #ifdef WDS_VENDOR_EXTENSION
  1907. int is_mcast = 0, is_ucast = 0;
  1908. int num_peers_3addr = 0;
  1909. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1910. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1911. #endif
  1912. vdev = tx_desc->vdev;
  1913. soc = vdev->pdev->soc;
  1914. qdf_assert(vdev);
  1915. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1916. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1917. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1918. "%s Tx reinject path", __func__);
  1919. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1920. qdf_nbuf_len(tx_desc->nbuf));
  1921. qdf_spin_lock_bh(&(soc->ast_lock));
  1922. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1923. (soc,
  1924. (uint8_t *)(eh->ether_shost),
  1925. vdev->pdev->pdev_id);
  1926. if (ast_entry)
  1927. sa_peer = ast_entry->peer;
  1928. qdf_spin_unlock_bh(&(soc->ast_lock));
  1929. #ifdef WDS_VENDOR_EXTENSION
  1930. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1931. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1932. } else {
  1933. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1934. }
  1935. is_ucast = !is_mcast;
  1936. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1937. if (peer->bss_peer)
  1938. continue;
  1939. /* Detect wds peers that use 3-addr framing for mcast.
  1940. * if there are any, the bss_peer is used to send the
  1941. * the mcast frame using 3-addr format. all wds enabled
  1942. * peers that use 4-addr framing for mcast frames will
  1943. * be duplicated and sent as 4-addr frames below.
  1944. */
  1945. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1946. num_peers_3addr = 1;
  1947. break;
  1948. }
  1949. }
  1950. #endif
  1951. if (qdf_unlikely(vdev->mesh_vdev)) {
  1952. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1953. } else {
  1954. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1955. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1956. #ifdef WDS_VENDOR_EXTENSION
  1957. /*
  1958. * . if 3-addr STA, then send on BSS Peer
  1959. * . if Peer WDS enabled and accept 4-addr mcast,
  1960. * send mcast on that peer only
  1961. * . if Peer WDS enabled and accept 4-addr ucast,
  1962. * send ucast on that peer only
  1963. */
  1964. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1965. (peer->wds_enabled &&
  1966. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1967. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1968. #else
  1969. ((peer->bss_peer &&
  1970. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1971. peer->nawds_enabled)) {
  1972. #endif
  1973. peer_id = DP_INVALID_PEER;
  1974. if (peer->nawds_enabled) {
  1975. peer_id = peer->peer_ids[0];
  1976. if (sa_peer == peer) {
  1977. QDF_TRACE(
  1978. QDF_MODULE_ID_DP,
  1979. QDF_TRACE_LEVEL_DEBUG,
  1980. " %s: multicast packet",
  1981. __func__);
  1982. DP_STATS_INC(peer,
  1983. tx.nawds_mcast_drop, 1);
  1984. continue;
  1985. }
  1986. }
  1987. nbuf_copy = qdf_nbuf_copy(nbuf);
  1988. if (!nbuf_copy) {
  1989. QDF_TRACE(QDF_MODULE_ID_DP,
  1990. QDF_TRACE_LEVEL_DEBUG,
  1991. FL("nbuf copy failed"));
  1992. break;
  1993. }
  1994. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1995. nbuf_copy,
  1996. &msdu_info,
  1997. peer_id,
  1998. NULL);
  1999. if (nbuf_copy) {
  2000. QDF_TRACE(QDF_MODULE_ID_DP,
  2001. QDF_TRACE_LEVEL_DEBUG,
  2002. FL("pkt send failed"));
  2003. qdf_nbuf_free(nbuf_copy);
  2004. } else {
  2005. if (peer_id != DP_INVALID_PEER)
  2006. DP_STATS_INC_PKT(peer,
  2007. tx.nawds_mcast,
  2008. 1, qdf_nbuf_len(nbuf));
  2009. }
  2010. }
  2011. }
  2012. }
  2013. if (vdev->nawds_enabled) {
  2014. peer_id = DP_INVALID_PEER;
  2015. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2016. 1, qdf_nbuf_len(nbuf));
  2017. nbuf = dp_tx_send_msdu_single(vdev,
  2018. nbuf,
  2019. &msdu_info,
  2020. peer_id, NULL);
  2021. if (nbuf) {
  2022. QDF_TRACE(QDF_MODULE_ID_DP,
  2023. QDF_TRACE_LEVEL_DEBUG,
  2024. FL("pkt send failed"));
  2025. qdf_nbuf_free(nbuf);
  2026. }
  2027. } else
  2028. qdf_nbuf_free(nbuf);
  2029. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2030. }
  2031. /**
  2032. * dp_tx_inspect_handler() - Tx Inspect Handler
  2033. * @tx_desc: software descriptor head pointer
  2034. * @status : Tx completion status from HTT descriptor
  2035. *
  2036. * Handles Tx frames sent back to Host for inspection
  2037. * (ProxyARP)
  2038. *
  2039. * Return: none
  2040. */
  2041. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2042. {
  2043. struct dp_soc *soc;
  2044. struct dp_pdev *pdev = tx_desc->pdev;
  2045. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2046. "%s Tx inspect path",
  2047. __func__);
  2048. qdf_assert(pdev);
  2049. soc = pdev->soc;
  2050. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2051. qdf_nbuf_len(tx_desc->nbuf));
  2052. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2053. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2054. }
  2055. #ifdef FEATURE_PERPKT_INFO
  2056. /**
  2057. * dp_get_completion_indication_for_stack() - send completion to stack
  2058. * @soc : dp_soc handle
  2059. * @pdev: dp_pdev handle
  2060. * @peer: dp peer handle
  2061. * @ts: transmit completion status structure
  2062. * @netbuf: Buffer pointer for free
  2063. *
  2064. * This function is used for indication whether buffer needs to be
  2065. * sent to stack for freeing or not
  2066. */
  2067. QDF_STATUS
  2068. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2069. struct dp_pdev *pdev,
  2070. struct dp_peer *peer,
  2071. struct hal_tx_completion_status *ts,
  2072. qdf_nbuf_t netbuf)
  2073. {
  2074. struct tx_capture_hdr *ppdu_hdr;
  2075. uint16_t peer_id = ts->peer_id;
  2076. uint32_t ppdu_id = ts->ppdu_id;
  2077. uint8_t first_msdu = ts->first_msdu;
  2078. uint8_t last_msdu = ts->last_msdu;
  2079. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  2080. return QDF_STATUS_E_NOSUPPORT;
  2081. if (!peer) {
  2082. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2083. FL("Peer Invalid"));
  2084. return QDF_STATUS_E_INVAL;
  2085. }
  2086. if (pdev->mcopy_mode) {
  2087. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2088. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2089. return QDF_STATUS_E_INVAL;
  2090. }
  2091. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2092. pdev->m_copy_id.tx_peer_id = peer_id;
  2093. }
  2094. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2095. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2096. FL("No headroom"));
  2097. return QDF_STATUS_E_NOMEM;
  2098. }
  2099. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2100. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2101. IEEE80211_ADDR_LEN);
  2102. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2103. IEEE80211_ADDR_LEN);
  2104. ppdu_hdr->ppdu_id = ppdu_id;
  2105. ppdu_hdr->peer_id = peer_id;
  2106. ppdu_hdr->first_msdu = first_msdu;
  2107. ppdu_hdr->last_msdu = last_msdu;
  2108. return QDF_STATUS_SUCCESS;
  2109. }
  2110. /**
  2111. * dp_send_completion_to_stack() - send completion to stack
  2112. * @soc : dp_soc handle
  2113. * @pdev: dp_pdev handle
  2114. * @peer_id: peer_id of the peer for which completion came
  2115. * @ppdu_id: ppdu_id
  2116. * @netbuf: Buffer pointer for free
  2117. *
  2118. * This function is used to send completion to stack
  2119. * to free buffer
  2120. */
  2121. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2122. uint16_t peer_id, uint32_t ppdu_id,
  2123. qdf_nbuf_t netbuf)
  2124. {
  2125. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2126. netbuf, peer_id,
  2127. WDI_NO_VAL, pdev->pdev_id);
  2128. }
  2129. #else
  2130. static QDF_STATUS
  2131. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2132. struct dp_pdev *pdev,
  2133. struct dp_peer *peer,
  2134. struct hal_tx_completion_status *ts,
  2135. qdf_nbuf_t netbuf)
  2136. {
  2137. return QDF_STATUS_E_NOSUPPORT;
  2138. }
  2139. static void
  2140. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2141. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2142. {
  2143. }
  2144. #endif
  2145. /**
  2146. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2147. * @soc: Soc handle
  2148. * @desc: software Tx descriptor to be processed
  2149. *
  2150. * Return: none
  2151. */
  2152. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2153. struct dp_tx_desc_s *desc)
  2154. {
  2155. struct dp_vdev *vdev = desc->vdev;
  2156. qdf_nbuf_t nbuf = desc->nbuf;
  2157. /* If it is TDLS mgmt, don't unmap or free the frame */
  2158. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2159. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2160. /* 0 : MSDU buffer, 1 : MLE */
  2161. if (desc->msdu_ext_desc) {
  2162. /* TSO free */
  2163. if (hal_tx_ext_desc_get_tso_enable(
  2164. desc->msdu_ext_desc->vaddr)) {
  2165. /* unmap eash TSO seg before free the nbuf */
  2166. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2167. desc->tso_num_desc);
  2168. qdf_nbuf_free(nbuf);
  2169. return;
  2170. }
  2171. }
  2172. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2173. if (qdf_likely(!vdev->mesh_vdev))
  2174. qdf_nbuf_free(nbuf);
  2175. else {
  2176. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2177. qdf_nbuf_free(nbuf);
  2178. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2179. } else
  2180. vdev->osif_tx_free_ext((nbuf));
  2181. }
  2182. }
  2183. /**
  2184. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2185. * @vdev: pointer to dp dev handler
  2186. * @status : Tx completion status from HTT descriptor
  2187. *
  2188. * Handles MEC notify event sent from fw to Host
  2189. *
  2190. * Return: none
  2191. */
  2192. #ifdef FEATURE_WDS
  2193. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2194. {
  2195. struct dp_soc *soc;
  2196. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2197. struct dp_peer *peer;
  2198. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2199. if (!vdev->mec_enabled)
  2200. return;
  2201. /* MEC required only in STA mode */
  2202. if (vdev->opmode != wlan_op_mode_sta)
  2203. return;
  2204. soc = vdev->pdev->soc;
  2205. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2206. peer = TAILQ_FIRST(&vdev->peer_list);
  2207. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2208. if (!peer) {
  2209. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2210. FL("peer is NULL"));
  2211. return;
  2212. }
  2213. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2214. "%s Tx MEC Handler",
  2215. __func__);
  2216. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2217. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2218. status[(DP_MAC_ADDR_LEN - 2) + i];
  2219. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2220. dp_peer_add_ast(soc,
  2221. peer,
  2222. mac_addr,
  2223. CDP_TXRX_AST_TYPE_MEC,
  2224. flags);
  2225. }
  2226. #endif
  2227. #ifdef MESH_MODE_SUPPORT
  2228. /**
  2229. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2230. * in mesh meta header
  2231. * @tx_desc: software descriptor head pointer
  2232. * @ts: pointer to tx completion stats
  2233. * Return: none
  2234. */
  2235. static
  2236. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2237. struct hal_tx_completion_status *ts)
  2238. {
  2239. struct meta_hdr_s *mhdr;
  2240. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2241. if (!tx_desc->msdu_ext_desc) {
  2242. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2243. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2244. "netbuf %pK offset %d",
  2245. netbuf, tx_desc->pkt_offset);
  2246. return;
  2247. }
  2248. }
  2249. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2251. "netbuf %pK offset %lu", netbuf,
  2252. sizeof(struct meta_hdr_s));
  2253. return;
  2254. }
  2255. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2256. mhdr->rssi = ts->ack_frame_rssi;
  2257. mhdr->channel = tx_desc->pdev->operating_channel;
  2258. }
  2259. #else
  2260. static
  2261. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2262. struct hal_tx_completion_status *ts)
  2263. {
  2264. }
  2265. #endif
  2266. /**
  2267. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2268. * @peer: Handle to DP peer
  2269. * @ts: pointer to HAL Tx completion stats
  2270. *
  2271. * Return: None
  2272. */
  2273. static inline void
  2274. dp_tx_update_peer_stats(struct dp_peer *peer,
  2275. struct hal_tx_completion_status *ts, uint32_t length)
  2276. {
  2277. struct dp_pdev *pdev = peer->vdev->pdev;
  2278. struct dp_soc *soc = NULL;
  2279. uint8_t mcs, pkt_type;
  2280. if (!pdev)
  2281. return;
  2282. soc = pdev->soc;
  2283. mcs = ts->mcs;
  2284. pkt_type = ts->pkt_type;
  2285. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2286. dp_err("Release source is not from TQM");
  2287. return;
  2288. }
  2289. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2290. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2291. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2292. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2293. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2294. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2295. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2296. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2297. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2298. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2299. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2300. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2301. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2302. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2303. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2304. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2305. return;
  2306. }
  2307. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2308. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2309. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2310. /*
  2311. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2312. * Return from here if HTT PPDU events are enabled.
  2313. */
  2314. if (!(soc->process_tx_status))
  2315. return;
  2316. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2317. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2318. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2319. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2320. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2321. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2322. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2323. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2324. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2325. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2326. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2327. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2328. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2329. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2330. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2331. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2332. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2333. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2334. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2335. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2336. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2337. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2338. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2339. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2340. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2341. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2342. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2343. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2344. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2345. &peer->stats, ts->peer_id,
  2346. UPDATE_PEER_STATS, pdev->pdev_id);
  2347. #endif
  2348. }
  2349. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2350. /**
  2351. * dp_tx_flow_pool_lock() - take flow pool lock
  2352. * @soc: core txrx main context
  2353. * @tx_desc: tx desc
  2354. *
  2355. * Return: None
  2356. */
  2357. static inline
  2358. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2359. struct dp_tx_desc_s *tx_desc)
  2360. {
  2361. struct dp_tx_desc_pool_s *pool;
  2362. uint8_t desc_pool_id;
  2363. desc_pool_id = tx_desc->pool_id;
  2364. pool = &soc->tx_desc[desc_pool_id];
  2365. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2366. }
  2367. /**
  2368. * dp_tx_flow_pool_unlock() - release flow pool lock
  2369. * @soc: core txrx main context
  2370. * @tx_desc: tx desc
  2371. *
  2372. * Return: None
  2373. */
  2374. static inline
  2375. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2376. struct dp_tx_desc_s *tx_desc)
  2377. {
  2378. struct dp_tx_desc_pool_s *pool;
  2379. uint8_t desc_pool_id;
  2380. desc_pool_id = tx_desc->pool_id;
  2381. pool = &soc->tx_desc[desc_pool_id];
  2382. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2383. }
  2384. #else
  2385. static inline
  2386. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2387. {
  2388. }
  2389. static inline
  2390. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2391. {
  2392. }
  2393. #endif
  2394. /**
  2395. * dp_tx_notify_completion() - Notify tx completion for this desc
  2396. * @soc: core txrx main context
  2397. * @tx_desc: tx desc
  2398. * @netbuf: buffer
  2399. *
  2400. * Return: none
  2401. */
  2402. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2403. struct dp_tx_desc_s *tx_desc,
  2404. qdf_nbuf_t netbuf)
  2405. {
  2406. void *osif_dev;
  2407. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2408. qdf_assert(tx_desc);
  2409. dp_tx_flow_pool_lock(soc, tx_desc);
  2410. if (!tx_desc->vdev ||
  2411. !tx_desc->vdev->osif_vdev) {
  2412. dp_tx_flow_pool_unlock(soc, tx_desc);
  2413. return;
  2414. }
  2415. osif_dev = tx_desc->vdev->osif_vdev;
  2416. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2417. dp_tx_flow_pool_unlock(soc, tx_desc);
  2418. if (tx_compl_cbk)
  2419. tx_compl_cbk(netbuf, osif_dev);
  2420. }
  2421. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2422. * @pdev: pdev handle
  2423. * @tid: tid value
  2424. * @txdesc_ts: timestamp from txdesc
  2425. * @ppdu_id: ppdu id
  2426. *
  2427. * Return: none
  2428. */
  2429. #ifdef FEATURE_PERPKT_INFO
  2430. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2431. uint8_t tid,
  2432. uint64_t txdesc_ts,
  2433. uint32_t ppdu_id)
  2434. {
  2435. uint64_t delta_ms;
  2436. struct cdp_tx_sojourn_stats *sojourn_stats;
  2437. if (pdev->enhanced_stats_en == 0)
  2438. return;
  2439. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2440. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2441. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2442. if (!pdev->sojourn_buf)
  2443. return;
  2444. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2445. qdf_nbuf_data(pdev->sojourn_buf);
  2446. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2447. sizeof(struct cdp_tx_sojourn_stats));
  2448. qdf_mem_zero(&pdev->sojourn_stats,
  2449. sizeof(struct cdp_tx_sojourn_stats));
  2450. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2451. pdev->sojourn_buf, HTT_INVALID_PEER,
  2452. WDI_NO_VAL, pdev->pdev_id);
  2453. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2454. }
  2455. if (tid == HTT_INVALID_TID)
  2456. return;
  2457. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2458. txdesc_ts;
  2459. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2460. delta_ms);
  2461. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2462. pdev->sojourn_stats.num_msdus[tid]++;
  2463. }
  2464. #else
  2465. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2466. uint8_t tid,
  2467. uint64_t txdesc_ts,
  2468. uint32_t ppdu_id)
  2469. {
  2470. }
  2471. #endif
  2472. /**
  2473. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2474. * @soc: DP Soc handle
  2475. * @tx_desc: software Tx descriptor
  2476. * @ts : Tx completion status from HAL/HTT descriptor
  2477. *
  2478. * Return: none
  2479. */
  2480. static inline void
  2481. dp_tx_comp_process_desc(struct dp_soc *soc,
  2482. struct dp_tx_desc_s *desc,
  2483. struct hal_tx_completion_status *ts,
  2484. struct dp_peer *peer)
  2485. {
  2486. /*
  2487. * m_copy/tx_capture modes are not supported for
  2488. * scatter gather packets
  2489. */
  2490. if (!(desc->msdu_ext_desc) &&
  2491. (dp_get_completion_indication_for_stack(soc, desc->pdev,
  2492. peer, ts, desc->nbuf)
  2493. == QDF_STATUS_SUCCESS)) {
  2494. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2495. QDF_DMA_TO_DEVICE);
  2496. dp_send_completion_to_stack(soc, desc->pdev, ts->peer_id,
  2497. ts->ppdu_id, desc->nbuf);
  2498. } else {
  2499. dp_tx_comp_free_buf(soc, desc);
  2500. }
  2501. }
  2502. /**
  2503. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2504. * @tx_desc: software descriptor head pointer
  2505. * @ts: Tx completion status
  2506. * @peer: peer handle
  2507. *
  2508. * Return: none
  2509. */
  2510. static inline
  2511. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2512. struct hal_tx_completion_status *ts,
  2513. struct dp_peer *peer)
  2514. {
  2515. uint32_t length;
  2516. struct dp_soc *soc = NULL;
  2517. struct dp_vdev *vdev = tx_desc->vdev;
  2518. qdf_ether_header_t *eh =
  2519. (qdf_ether_header_t *)qdf_nbuf_data(tx_desc->nbuf);
  2520. if (!vdev) {
  2521. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2522. "invalid vdev");
  2523. goto out;
  2524. }
  2525. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2526. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2527. QDF_TRACE_DEFAULT_PDEV_ID,
  2528. qdf_nbuf_data_addr(tx_desc->nbuf),
  2529. sizeof(qdf_nbuf_data(tx_desc->nbuf)),
  2530. tx_desc->id,
  2531. ts->status));
  2532. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2533. "-------------------- \n"
  2534. "Tx Completion Stats: \n"
  2535. "-------------------- \n"
  2536. "ack_frame_rssi = %d \n"
  2537. "first_msdu = %d \n"
  2538. "last_msdu = %d \n"
  2539. "msdu_part_of_amsdu = %d \n"
  2540. "rate_stats valid = %d \n"
  2541. "bw = %d \n"
  2542. "pkt_type = %d \n"
  2543. "stbc = %d \n"
  2544. "ldpc = %d \n"
  2545. "sgi = %d \n"
  2546. "mcs = %d \n"
  2547. "ofdma = %d \n"
  2548. "tones_in_ru = %d \n"
  2549. "tsf = %d \n"
  2550. "ppdu_id = %d \n"
  2551. "transmit_cnt = %d \n"
  2552. "tid = %d \n"
  2553. "peer_id = %d\n",
  2554. ts->ack_frame_rssi, ts->first_msdu,
  2555. ts->last_msdu, ts->msdu_part_of_amsdu,
  2556. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2557. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2558. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2559. ts->transmit_cnt, ts->tid, ts->peer_id);
  2560. soc = vdev->pdev->soc;
  2561. /* Update SoC level stats */
  2562. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2563. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2564. /* Update per-packet stats for mesh mode */
  2565. if (qdf_unlikely(vdev->mesh_vdev) &&
  2566. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2567. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2568. length = qdf_nbuf_len(tx_desc->nbuf);
  2569. /* Update peer level stats */
  2570. if (!peer) {
  2571. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2572. "peer is null or deletion in progress");
  2573. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2574. goto out;
  2575. }
  2576. if (qdf_likely(!peer->bss_peer)) {
  2577. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2578. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2579. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2580. } else {
  2581. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2582. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2583. if ((peer->vdev->tx_encap_type ==
  2584. htt_cmn_pkt_type_ethernet) &&
  2585. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2586. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2587. }
  2588. }
  2589. }
  2590. dp_tx_update_peer_stats(peer, ts, length);
  2591. out:
  2592. return;
  2593. }
  2594. /**
  2595. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2596. * @soc: core txrx main context
  2597. * @comp_head: software descriptor head pointer
  2598. *
  2599. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2600. * and release the software descriptors after processing is complete
  2601. *
  2602. * Return: none
  2603. */
  2604. static void
  2605. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2606. struct dp_tx_desc_s *comp_head)
  2607. {
  2608. struct dp_tx_desc_s *desc;
  2609. struct dp_tx_desc_s *next;
  2610. struct hal_tx_completion_status ts = {0};
  2611. struct dp_peer *peer;
  2612. DP_HIST_INIT();
  2613. desc = comp_head;
  2614. while (desc) {
  2615. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2616. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2617. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2618. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2619. if (peer)
  2620. dp_peer_unref_del_find_by_id(peer);
  2621. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2622. next = desc->next;
  2623. dp_tx_desc_release(desc, desc->pool_id);
  2624. desc = next;
  2625. }
  2626. DP_TX_HIST_STATS_PER_PDEV();
  2627. }
  2628. /**
  2629. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2630. * @tx_desc: software descriptor head pointer
  2631. * @status : Tx completion status from HTT descriptor
  2632. *
  2633. * This function will process HTT Tx indication messages from Target
  2634. *
  2635. * Return: none
  2636. */
  2637. static
  2638. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2639. {
  2640. uint8_t tx_status;
  2641. struct dp_pdev *pdev;
  2642. struct dp_vdev *vdev;
  2643. struct dp_soc *soc;
  2644. struct hal_tx_completion_status ts = {0};
  2645. uint32_t *htt_desc = (uint32_t *)status;
  2646. struct dp_peer *peer;
  2647. qdf_assert(tx_desc->pdev);
  2648. pdev = tx_desc->pdev;
  2649. vdev = tx_desc->vdev;
  2650. soc = pdev->soc;
  2651. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2652. switch (tx_status) {
  2653. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2654. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2655. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2656. {
  2657. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2658. ts.peer_id =
  2659. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2660. htt_desc[2]);
  2661. ts.tid =
  2662. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2663. htt_desc[2]);
  2664. } else {
  2665. ts.peer_id = HTT_INVALID_PEER;
  2666. ts.tid = HTT_INVALID_TID;
  2667. }
  2668. ts.ppdu_id =
  2669. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2670. htt_desc[1]);
  2671. ts.ack_frame_rssi =
  2672. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2673. htt_desc[1]);
  2674. ts.first_msdu = 1;
  2675. ts.last_msdu = 1;
  2676. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  2677. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2678. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2679. if (qdf_likely(peer))
  2680. dp_peer_unref_del_find_by_id(peer);
  2681. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2682. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2683. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2684. break;
  2685. }
  2686. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2687. {
  2688. dp_tx_reinject_handler(tx_desc, status);
  2689. break;
  2690. }
  2691. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2692. {
  2693. dp_tx_inspect_handler(tx_desc, status);
  2694. break;
  2695. }
  2696. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2697. {
  2698. dp_tx_mec_handler(vdev, status);
  2699. break;
  2700. }
  2701. default:
  2702. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2703. "%s Invalid HTT tx_status %d\n",
  2704. __func__, tx_status);
  2705. break;
  2706. }
  2707. }
  2708. /**
  2709. * dp_tx_comp_handler() - Tx completion handler
  2710. * @soc: core txrx main context
  2711. * @ring_id: completion ring id
  2712. * @quota: No. of packets/descriptors that can be serviced in one loop
  2713. *
  2714. * This function will collect hardware release ring element contents and
  2715. * handle descriptor contents. Based on contents, free packet or handle error
  2716. * conditions
  2717. *
  2718. * Return: none
  2719. */
  2720. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2721. {
  2722. void *tx_comp_hal_desc;
  2723. uint8_t buffer_src;
  2724. uint8_t pool_id;
  2725. uint32_t tx_desc_id;
  2726. struct dp_tx_desc_s *tx_desc = NULL;
  2727. struct dp_tx_desc_s *head_desc = NULL;
  2728. struct dp_tx_desc_s *tail_desc = NULL;
  2729. uint32_t num_processed;
  2730. uint32_t count;
  2731. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2732. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2733. "%s %d : HAL RING Access Failed -- %pK",
  2734. __func__, __LINE__, hal_srng);
  2735. return 0;
  2736. }
  2737. num_processed = 0;
  2738. count = 0;
  2739. /* Find head descriptor from completion ring */
  2740. while (qdf_likely(tx_comp_hal_desc =
  2741. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2742. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2743. /* If this buffer was not released by TQM or FW, then it is not
  2744. * Tx completion indication, assert */
  2745. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2746. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2747. QDF_TRACE(QDF_MODULE_ID_DP,
  2748. QDF_TRACE_LEVEL_FATAL,
  2749. "Tx comp release_src != TQM | FW");
  2750. qdf_assert_always(0);
  2751. }
  2752. /* Get descriptor id */
  2753. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2754. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2755. DP_TX_DESC_ID_POOL_OS;
  2756. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2757. continue;
  2758. /* Find Tx descriptor */
  2759. tx_desc = dp_tx_desc_find(soc, pool_id,
  2760. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2761. DP_TX_DESC_ID_PAGE_OS,
  2762. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2763. DP_TX_DESC_ID_OFFSET_OS);
  2764. /*
  2765. * If the descriptor is already freed in vdev_detach,
  2766. * continue to next descriptor
  2767. */
  2768. if (!tx_desc->vdev) {
  2769. QDF_TRACE(QDF_MODULE_ID_DP,
  2770. QDF_TRACE_LEVEL_INFO,
  2771. "Descriptor freed in vdev_detach %d",
  2772. tx_desc_id);
  2773. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2774. count++;
  2775. continue;
  2776. }
  2777. /*
  2778. * If the release source is FW, process the HTT status
  2779. */
  2780. if (qdf_unlikely(buffer_src ==
  2781. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2782. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2783. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2784. htt_tx_status);
  2785. dp_tx_process_htt_completion(tx_desc,
  2786. htt_tx_status);
  2787. } else {
  2788. /* Pool id is not matching. Error */
  2789. if (tx_desc->pool_id != pool_id) {
  2790. QDF_TRACE(QDF_MODULE_ID_DP,
  2791. QDF_TRACE_LEVEL_FATAL,
  2792. "Tx Comp pool id %d not matched %d",
  2793. pool_id, tx_desc->pool_id);
  2794. qdf_assert_always(0);
  2795. }
  2796. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2797. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2798. QDF_TRACE(QDF_MODULE_ID_DP,
  2799. QDF_TRACE_LEVEL_FATAL,
  2800. "Txdesc invalid, flgs = %x,id = %d",
  2801. tx_desc->flags, tx_desc_id);
  2802. qdf_assert_always(0);
  2803. }
  2804. /* First ring descriptor on the cycle */
  2805. if (!head_desc) {
  2806. head_desc = tx_desc;
  2807. tail_desc = tx_desc;
  2808. }
  2809. tail_desc->next = tx_desc;
  2810. tx_desc->next = NULL;
  2811. tail_desc = tx_desc;
  2812. /* Collect hw completion contents */
  2813. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2814. &tx_desc->comp, 1);
  2815. }
  2816. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2817. /*
  2818. * Processed packet count is more than given quota
  2819. * stop to processing
  2820. */
  2821. if ((num_processed >= quota))
  2822. break;
  2823. count++;
  2824. }
  2825. hal_srng_access_end(soc->hal_soc, hal_srng);
  2826. /* Process the reaped descriptors */
  2827. if (head_desc)
  2828. dp_tx_comp_process_desc_list(soc, head_desc);
  2829. return num_processed;
  2830. }
  2831. #ifdef FEATURE_WLAN_TDLS
  2832. /**
  2833. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2834. *
  2835. * @data_vdev - which vdev should transmit the tx data frames
  2836. * @tx_spec - what non-standard handling to apply to the tx data frames
  2837. * @msdu_list - NULL-terminated list of tx MSDUs
  2838. *
  2839. * Return: NULL on success,
  2840. * nbuf when it fails to send
  2841. */
  2842. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2843. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2844. {
  2845. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2846. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2847. vdev->is_tdls_frame = true;
  2848. return dp_tx_send(vdev_handle, msdu_list);
  2849. }
  2850. #endif
  2851. /**
  2852. * dp_tx_vdev_attach() - attach vdev to dp tx
  2853. * @vdev: virtual device instance
  2854. *
  2855. * Return: QDF_STATUS_SUCCESS: success
  2856. * QDF_STATUS_E_RESOURCES: Error return
  2857. */
  2858. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2859. {
  2860. /*
  2861. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2862. */
  2863. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2864. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2865. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2866. vdev->vdev_id);
  2867. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2868. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2869. /*
  2870. * Set HTT Extension Valid bit to 0 by default
  2871. */
  2872. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2873. dp_tx_vdev_update_search_flags(vdev);
  2874. return QDF_STATUS_SUCCESS;
  2875. }
  2876. #ifdef FEATURE_WDS
  2877. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2878. {
  2879. struct dp_soc *soc = vdev->pdev->soc;
  2880. /*
  2881. * If AST index override support is available (HKv2 etc),
  2882. * DA search flag be enabled always
  2883. *
  2884. * If AST index override support is not available (HKv1),
  2885. * DA search flag should be used for all modes except QWRAP
  2886. */
  2887. if (soc->ast_override_support || !vdev->proxysta_vdev)
  2888. return true;
  2889. return false;
  2890. }
  2891. #else
  2892. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2893. {
  2894. return false;
  2895. }
  2896. #endif
  2897. /**
  2898. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2899. * @vdev: virtual device instance
  2900. *
  2901. * Return: void
  2902. *
  2903. */
  2904. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2905. {
  2906. struct dp_soc *soc = vdev->pdev->soc;
  2907. /*
  2908. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2909. * for TDLS link
  2910. *
  2911. * Enable AddrY (SA based search) only for non-WDS STA and
  2912. * ProxySTA VAP (in HKv1) modes.
  2913. *
  2914. * In all other VAP modes, only DA based search should be
  2915. * enabled
  2916. */
  2917. if (vdev->opmode == wlan_op_mode_sta &&
  2918. vdev->tdls_link_connected)
  2919. vdev->hal_desc_addr_search_flags =
  2920. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2921. else if ((vdev->opmode == wlan_op_mode_sta) &&
  2922. !dp_tx_da_search_override(vdev))
  2923. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2924. else
  2925. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2926. /* Set search type only when peer map v2 messaging is enabled
  2927. * as we will have the search index (AST hash) only when v2 is
  2928. * enabled
  2929. */
  2930. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  2931. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  2932. else
  2933. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  2934. }
  2935. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2936. /* dp_tx_desc_flush() - release resources associated
  2937. * to tx_desc
  2938. * @vdev: virtual device instance
  2939. *
  2940. * This function will free all outstanding Tx buffers,
  2941. * including ME buffer for which either free during
  2942. * completion didn't happened or completion is not
  2943. * received.
  2944. */
  2945. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2946. {
  2947. uint8_t i;
  2948. uint32_t j;
  2949. uint32_t num_desc, page_id, offset;
  2950. uint16_t num_desc_per_page;
  2951. struct dp_soc *soc = vdev->pdev->soc;
  2952. struct dp_tx_desc_s *tx_desc = NULL;
  2953. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2954. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  2955. tx_desc_pool = &soc->tx_desc[i];
  2956. if (!(tx_desc_pool->pool_size) ||
  2957. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  2958. !(tx_desc_pool->desc_pages.cacheable_pages))
  2959. continue;
  2960. num_desc = tx_desc_pool->pool_size;
  2961. num_desc_per_page =
  2962. tx_desc_pool->desc_pages.num_element_per_page;
  2963. for (j = 0; j < num_desc; j++) {
  2964. page_id = j / num_desc_per_page;
  2965. offset = j % num_desc_per_page;
  2966. if (qdf_unlikely(!(tx_desc_pool->
  2967. desc_pages.cacheable_pages)))
  2968. break;
  2969. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  2970. if (tx_desc && (tx_desc->vdev == vdev) &&
  2971. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2972. dp_tx_comp_free_buf(soc, tx_desc);
  2973. dp_tx_desc_release(tx_desc, i);
  2974. }
  2975. }
  2976. }
  2977. }
  2978. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2979. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2980. {
  2981. uint8_t i, num_pool;
  2982. uint32_t j;
  2983. uint32_t num_desc, page_id, offset;
  2984. uint16_t num_desc_per_page;
  2985. struct dp_soc *soc = vdev->pdev->soc;
  2986. struct dp_tx_desc_s *tx_desc = NULL;
  2987. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2988. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2989. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2990. for (i = 0; i < num_pool; i++) {
  2991. tx_desc_pool = &soc->tx_desc[i];
  2992. if (!tx_desc_pool->desc_pages.cacheable_pages)
  2993. continue;
  2994. num_desc_per_page =
  2995. tx_desc_pool->desc_pages.num_element_per_page;
  2996. for (j = 0; j < num_desc; j++) {
  2997. page_id = j / num_desc_per_page;
  2998. offset = j % num_desc_per_page;
  2999. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3000. if (tx_desc && (tx_desc->vdev == vdev) &&
  3001. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  3002. dp_tx_comp_free_buf(soc, tx_desc);
  3003. dp_tx_desc_release(tx_desc, i);
  3004. }
  3005. }
  3006. }
  3007. }
  3008. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3009. /**
  3010. * dp_tx_vdev_detach() - detach vdev from dp tx
  3011. * @vdev: virtual device instance
  3012. *
  3013. * Return: QDF_STATUS_SUCCESS: success
  3014. * QDF_STATUS_E_RESOURCES: Error return
  3015. */
  3016. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3017. {
  3018. dp_tx_desc_flush(vdev);
  3019. return QDF_STATUS_SUCCESS;
  3020. }
  3021. /**
  3022. * dp_tx_pdev_attach() - attach pdev to dp tx
  3023. * @pdev: physical device instance
  3024. *
  3025. * Return: QDF_STATUS_SUCCESS: success
  3026. * QDF_STATUS_E_RESOURCES: Error return
  3027. */
  3028. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3029. {
  3030. struct dp_soc *soc = pdev->soc;
  3031. /* Initialize Flow control counters */
  3032. qdf_atomic_init(&pdev->num_tx_exception);
  3033. qdf_atomic_init(&pdev->num_tx_outstanding);
  3034. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3035. /* Initialize descriptors in TCL Ring */
  3036. hal_tx_init_data_ring(soc->hal_soc,
  3037. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3038. }
  3039. return QDF_STATUS_SUCCESS;
  3040. }
  3041. /**
  3042. * dp_tx_pdev_detach() - detach pdev from dp tx
  3043. * @pdev: physical device instance
  3044. *
  3045. * Return: QDF_STATUS_SUCCESS: success
  3046. * QDF_STATUS_E_RESOURCES: Error return
  3047. */
  3048. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3049. {
  3050. dp_tx_me_exit(pdev);
  3051. return QDF_STATUS_SUCCESS;
  3052. }
  3053. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3054. /* Pools will be allocated dynamically */
  3055. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3056. int num_desc)
  3057. {
  3058. uint8_t i;
  3059. for (i = 0; i < num_pool; i++) {
  3060. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3061. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3062. }
  3063. return 0;
  3064. }
  3065. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3066. {
  3067. uint8_t i;
  3068. for (i = 0; i < num_pool; i++)
  3069. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3070. }
  3071. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3072. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3073. int num_desc)
  3074. {
  3075. uint8_t i;
  3076. /* Allocate software Tx descriptor pools */
  3077. for (i = 0; i < num_pool; i++) {
  3078. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3079. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3080. "%s Tx Desc Pool alloc %d failed %pK",
  3081. __func__, i, soc);
  3082. return ENOMEM;
  3083. }
  3084. }
  3085. return 0;
  3086. }
  3087. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3088. {
  3089. uint8_t i;
  3090. for (i = 0; i < num_pool; i++) {
  3091. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3092. if (dp_tx_desc_pool_free(soc, i)) {
  3093. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3094. "%s Tx Desc Pool Free failed", __func__);
  3095. }
  3096. }
  3097. }
  3098. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3099. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3100. /**
  3101. * dp_tso_attach_wifi3() - TSO attach handler
  3102. * @txrx_soc: Opaque Dp handle
  3103. *
  3104. * Reserve TSO descriptor buffers
  3105. *
  3106. * Return: QDF_STATUS_E_FAILURE on failure or
  3107. * QDF_STATUS_SUCCESS on success
  3108. */
  3109. static
  3110. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3111. {
  3112. return dp_tso_soc_attach(txrx_soc);
  3113. }
  3114. /**
  3115. * dp_tso_detach_wifi3() - TSO Detach handler
  3116. * @txrx_soc: Opaque Dp handle
  3117. *
  3118. * Deallocate TSO descriptor buffers
  3119. *
  3120. * Return: QDF_STATUS_E_FAILURE on failure or
  3121. * QDF_STATUS_SUCCESS on success
  3122. */
  3123. static
  3124. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3125. {
  3126. return dp_tso_soc_detach(txrx_soc);
  3127. }
  3128. #else
  3129. static
  3130. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3131. {
  3132. return QDF_STATUS_SUCCESS;
  3133. }
  3134. static
  3135. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3136. {
  3137. return QDF_STATUS_SUCCESS;
  3138. }
  3139. #endif
  3140. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3141. {
  3142. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3143. uint8_t i;
  3144. uint8_t num_pool;
  3145. uint32_t num_desc;
  3146. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3147. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3148. for (i = 0; i < num_pool; i++)
  3149. dp_tx_tso_desc_pool_free(soc, i);
  3150. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3151. __func__, num_pool, num_desc);
  3152. for (i = 0; i < num_pool; i++)
  3153. dp_tx_tso_num_seg_pool_free(soc, i);
  3154. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3155. __func__, num_pool, num_desc);
  3156. return QDF_STATUS_SUCCESS;
  3157. }
  3158. /**
  3159. * dp_tso_attach() - TSO attach handler
  3160. * @txrx_soc: Opaque Dp handle
  3161. *
  3162. * Reserve TSO descriptor buffers
  3163. *
  3164. * Return: QDF_STATUS_E_FAILURE on failure or
  3165. * QDF_STATUS_SUCCESS on success
  3166. */
  3167. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3168. {
  3169. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3170. uint8_t i;
  3171. uint8_t num_pool;
  3172. uint32_t num_desc;
  3173. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3174. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3175. for (i = 0; i < num_pool; i++) {
  3176. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3177. dp_err("TSO Desc Pool alloc %d failed %pK",
  3178. i, soc);
  3179. return QDF_STATUS_E_FAILURE;
  3180. }
  3181. }
  3182. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3183. __func__, num_pool, num_desc);
  3184. for (i = 0; i < num_pool; i++) {
  3185. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3186. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3187. i, soc);
  3188. return QDF_STATUS_E_FAILURE;
  3189. }
  3190. }
  3191. return QDF_STATUS_SUCCESS;
  3192. }
  3193. /**
  3194. * dp_tx_soc_detach() - detach soc from dp tx
  3195. * @soc: core txrx main context
  3196. *
  3197. * This function will detach dp tx into main device context
  3198. * will free dp tx resource and initialize resources
  3199. *
  3200. * Return: QDF_STATUS_SUCCESS: success
  3201. * QDF_STATUS_E_RESOURCES: Error return
  3202. */
  3203. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3204. {
  3205. uint8_t num_pool;
  3206. uint16_t num_desc;
  3207. uint16_t num_ext_desc;
  3208. uint8_t i;
  3209. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3210. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3211. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3212. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3213. dp_tx_flow_control_deinit(soc);
  3214. dp_tx_delete_static_pools(soc, num_pool);
  3215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3216. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3217. __func__, num_pool, num_desc);
  3218. for (i = 0; i < num_pool; i++) {
  3219. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3220. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3221. "%s Tx Ext Desc Pool Free failed",
  3222. __func__);
  3223. return QDF_STATUS_E_RESOURCES;
  3224. }
  3225. }
  3226. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3227. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3228. __func__, num_pool, num_ext_desc);
  3229. status = dp_tso_detach_wifi3(soc);
  3230. if (status != QDF_STATUS_SUCCESS)
  3231. return status;
  3232. return QDF_STATUS_SUCCESS;
  3233. }
  3234. /**
  3235. * dp_tx_soc_attach() - attach soc to dp tx
  3236. * @soc: core txrx main context
  3237. *
  3238. * This function will attach dp tx into main device context
  3239. * will allocate dp tx resource and initialize resources
  3240. *
  3241. * Return: QDF_STATUS_SUCCESS: success
  3242. * QDF_STATUS_E_RESOURCES: Error return
  3243. */
  3244. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3245. {
  3246. uint8_t i;
  3247. uint8_t num_pool;
  3248. uint32_t num_desc;
  3249. uint32_t num_ext_desc;
  3250. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3251. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3252. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3253. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3254. if (num_pool > MAX_TXDESC_POOLS)
  3255. goto fail;
  3256. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3257. goto fail;
  3258. dp_tx_flow_control_init(soc);
  3259. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3260. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3261. __func__, num_pool, num_desc);
  3262. /* Allocate extension tx descriptor pools */
  3263. for (i = 0; i < num_pool; i++) {
  3264. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3265. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3266. "MSDU Ext Desc Pool alloc %d failed %pK",
  3267. i, soc);
  3268. goto fail;
  3269. }
  3270. }
  3271. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3272. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3273. __func__, num_pool, num_ext_desc);
  3274. status = dp_tso_attach_wifi3((void *)soc);
  3275. if (status != QDF_STATUS_SUCCESS)
  3276. goto fail;
  3277. /* Initialize descriptors in TCL Rings */
  3278. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3279. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3280. hal_tx_init_data_ring(soc->hal_soc,
  3281. soc->tcl_data_ring[i].hal_srng);
  3282. }
  3283. }
  3284. /*
  3285. * todo - Add a runtime config option to enable this.
  3286. */
  3287. /*
  3288. * Due to multiple issues on NPR EMU, enable it selectively
  3289. * only for NPR EMU, should be removed, once NPR platforms
  3290. * are stable.
  3291. */
  3292. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3293. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3294. "%s HAL Tx init Success", __func__);
  3295. return QDF_STATUS_SUCCESS;
  3296. fail:
  3297. /* Detach will take care of freeing only allocated resources */
  3298. dp_tx_soc_detach(soc);
  3299. return QDF_STATUS_E_RESOURCES;
  3300. }
  3301. /*
  3302. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3303. * pdev: pointer to DP PDEV structure
  3304. * seg_info_head: Pointer to the head of list
  3305. *
  3306. * return: void
  3307. */
  3308. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3309. struct dp_tx_seg_info_s *seg_info_head)
  3310. {
  3311. struct dp_tx_me_buf_t *mc_uc_buf;
  3312. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3313. qdf_nbuf_t nbuf = NULL;
  3314. uint64_t phy_addr;
  3315. while (seg_info_head) {
  3316. nbuf = seg_info_head->nbuf;
  3317. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3318. seg_info_head->frags[0].vaddr;
  3319. phy_addr = seg_info_head->frags[0].paddr_hi;
  3320. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3321. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3322. phy_addr,
  3323. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  3324. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3325. qdf_nbuf_free(nbuf);
  3326. seg_info_new = seg_info_head;
  3327. seg_info_head = seg_info_head->next;
  3328. qdf_mem_free(seg_info_new);
  3329. }
  3330. }
  3331. /**
  3332. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3333. * @vdev: DP VDEV handle
  3334. * @nbuf: Multicast nbuf
  3335. * @newmac: Table of the clients to which packets have to be sent
  3336. * @new_mac_cnt: No of clients
  3337. *
  3338. * return: no of converted packets
  3339. */
  3340. uint16_t
  3341. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3342. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3343. {
  3344. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3345. struct dp_pdev *pdev = vdev->pdev;
  3346. qdf_ether_header_t *eh;
  3347. uint8_t *data;
  3348. uint16_t len;
  3349. /* reference to frame dst addr */
  3350. uint8_t *dstmac;
  3351. /* copy of original frame src addr */
  3352. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3353. /* local index into newmac */
  3354. uint8_t new_mac_idx = 0;
  3355. struct dp_tx_me_buf_t *mc_uc_buf;
  3356. qdf_nbuf_t nbuf_clone;
  3357. struct dp_tx_msdu_info_s msdu_info;
  3358. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3359. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3360. struct dp_tx_seg_info_s *seg_info_new;
  3361. struct dp_tx_frag_info_s data_frag;
  3362. qdf_dma_addr_t paddr_data;
  3363. qdf_dma_addr_t paddr_mcbuf = 0;
  3364. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3365. QDF_STATUS status;
  3366. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3367. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3368. eh = (qdf_ether_header_t *)nbuf;
  3369. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3370. len = qdf_nbuf_len(nbuf);
  3371. data = qdf_nbuf_data(nbuf);
  3372. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3373. QDF_DMA_TO_DEVICE);
  3374. if (status) {
  3375. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3376. "Mapping failure Error:%d", status);
  3377. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3378. qdf_nbuf_free(nbuf);
  3379. return 1;
  3380. }
  3381. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3382. /*preparing data fragment*/
  3383. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3384. data_frag.paddr_lo = (uint32_t)paddr_data;
  3385. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3386. data_frag.len = len - DP_MAC_ADDR_LEN;
  3387. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3388. dstmac = newmac[new_mac_idx];
  3389. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3390. "added mac addr (%pM)", dstmac);
  3391. /* Check for NULL Mac Address */
  3392. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3393. continue;
  3394. /* frame to self mac. skip */
  3395. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3396. continue;
  3397. /*
  3398. * TODO: optimize to avoid malloc in per-packet path
  3399. * For eg. seg_pool can be made part of vdev structure
  3400. */
  3401. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3402. if (!seg_info_new) {
  3403. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3404. "alloc failed");
  3405. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3406. goto fail_seg_alloc;
  3407. }
  3408. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3409. if (mc_uc_buf == NULL)
  3410. goto fail_buf_alloc;
  3411. /*
  3412. * TODO: Check if we need to clone the nbuf
  3413. * Or can we just use the reference for all cases
  3414. */
  3415. if (new_mac_idx < (new_mac_cnt - 1)) {
  3416. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3417. if (nbuf_clone == NULL) {
  3418. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3419. goto fail_clone;
  3420. }
  3421. } else {
  3422. /*
  3423. * Update the ref
  3424. * to account for frame sent without cloning
  3425. */
  3426. qdf_nbuf_ref(nbuf);
  3427. nbuf_clone = nbuf;
  3428. }
  3429. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3430. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3431. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3432. &paddr_mcbuf);
  3433. if (status) {
  3434. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3435. "Mapping failure Error:%d", status);
  3436. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3437. goto fail_map;
  3438. }
  3439. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3440. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3441. seg_info_new->frags[0].paddr_hi =
  3442. ((uint64_t) paddr_mcbuf >> 32);
  3443. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3444. seg_info_new->frags[1] = data_frag;
  3445. seg_info_new->nbuf = nbuf_clone;
  3446. seg_info_new->frag_cnt = 2;
  3447. seg_info_new->total_len = len;
  3448. seg_info_new->next = NULL;
  3449. if (seg_info_head == NULL)
  3450. seg_info_head = seg_info_new;
  3451. else
  3452. seg_info_tail->next = seg_info_new;
  3453. seg_info_tail = seg_info_new;
  3454. }
  3455. if (!seg_info_head) {
  3456. goto free_return;
  3457. }
  3458. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3459. msdu_info.num_seg = new_mac_cnt;
  3460. msdu_info.frm_type = dp_tx_frm_me;
  3461. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3462. qdf_unlikely(pdev->hmmc_tid_override_en))
  3463. msdu_info.tid = pdev->hmmc_tid;
  3464. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3465. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3466. while (seg_info_head->next) {
  3467. seg_info_new = seg_info_head;
  3468. seg_info_head = seg_info_head->next;
  3469. qdf_mem_free(seg_info_new);
  3470. }
  3471. qdf_mem_free(seg_info_head);
  3472. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3473. qdf_nbuf_free(nbuf);
  3474. return new_mac_cnt;
  3475. fail_map:
  3476. qdf_nbuf_free(nbuf_clone);
  3477. fail_clone:
  3478. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3479. fail_buf_alloc:
  3480. qdf_mem_free(seg_info_new);
  3481. fail_seg_alloc:
  3482. dp_tx_me_mem_free(pdev, seg_info_head);
  3483. free_return:
  3484. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3485. qdf_nbuf_free(nbuf);
  3486. return 1;
  3487. }