hal_8074v1_rx.h 14 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "hal_hw_headers.h"
  19. #include "hal_internal.h"
  20. #include "cdp_txrx_mon_struct.h"
  21. #include "qdf_trace.h"
  22. #include "hal_rx.h"
  23. #include "hal_tx.h"
  24. #include "dp_types.h"
  25. #include "hal_api_mon.h"
  26. #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
  27. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  28. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
  29. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
  30. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
  31. #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
  32. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  33. RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
  34. RX_MSDU_END_5_DA_IS_MCBC_MASK, \
  35. RX_MSDU_END_5_DA_IS_MCBC_LSB))
  36. #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
  37. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  38. RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \
  39. RX_MSDU_END_5_SA_IS_VALID_MASK, \
  40. RX_MSDU_END_5_SA_IS_VALID_LSB))
  41. #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
  42. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  43. RX_MSDU_END_13_SA_IDX_OFFSET)), \
  44. RX_MSDU_END_13_SA_IDX_MASK, \
  45. RX_MSDU_END_13_SA_IDX_LSB))
  46. #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
  47. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  48. RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
  49. RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
  50. RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
  51. #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
  52. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  53. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
  54. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \
  55. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB))
  56. #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
  57. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  58. RX_MPDU_INFO_4_PN_31_0_OFFSET)), \
  59. RX_MPDU_INFO_4_PN_31_0_MASK, \
  60. RX_MPDU_INFO_4_PN_31_0_LSB))
  61. #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
  62. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  63. RX_MPDU_INFO_5_PN_63_32_OFFSET)), \
  64. RX_MPDU_INFO_5_PN_63_32_MASK, \
  65. RX_MPDU_INFO_5_PN_63_32_LSB))
  66. #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
  67. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  68. RX_MPDU_INFO_6_PN_95_64_OFFSET)), \
  69. RX_MPDU_INFO_6_PN_95_64_MASK, \
  70. RX_MPDU_INFO_6_PN_95_64_LSB))
  71. #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
  72. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  73. RX_MPDU_INFO_7_PN_127_96_OFFSET)), \
  74. RX_MPDU_INFO_7_PN_127_96_MASK, \
  75. RX_MPDU_INFO_7_PN_127_96_LSB))
  76. #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
  77. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  78. RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \
  79. RX_MSDU_END_5_FIRST_MSDU_MASK, \
  80. RX_MSDU_END_5_FIRST_MSDU_LSB))
  81. #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
  82. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  83. RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \
  84. RX_MSDU_END_5_DA_IS_VALID_MASK, \
  85. RX_MSDU_END_5_DA_IS_VALID_LSB))
  86. #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
  87. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  88. RX_MSDU_END_5_LAST_MSDU_OFFSET)), \
  89. RX_MSDU_END_5_LAST_MSDU_MASK, \
  90. RX_MSDU_END_5_LAST_MSDU_LSB))
  91. #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \
  92. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  93. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
  94. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
  95. RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
  96. #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
  97. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  98. RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \
  99. RX_MPDU_INFO_1_SW_PEER_ID_MASK, \
  100. RX_MPDU_INFO_1_SW_PEER_ID_LSB))
  101. #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
  102. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  103. RX_MPDU_INFO_2_TO_DS_OFFSET)), \
  104. RX_MPDU_INFO_2_TO_DS_MASK, \
  105. RX_MPDU_INFO_2_TO_DS_LSB))
  106. #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
  107. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  108. RX_MPDU_INFO_2_FR_DS_OFFSET)), \
  109. RX_MPDU_INFO_2_FR_DS_MASK, \
  110. RX_MPDU_INFO_2_FR_DS_LSB))
  111. #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
  112. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  113. RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
  114. RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \
  115. RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB))
  116. /*
  117. * hal_rx_msdu_start_nss_get_8074(): API to get the NSS
  118. * Interval from rx_msdu_start
  119. *
  120. * @buf: pointer to the start of RX PKT TLV header
  121. * Return: uint32_t(nss)
  122. */
  123. static uint32_t
  124. hal_rx_msdu_start_nss_get_8074(uint8_t *buf)
  125. {
  126. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  127. struct rx_msdu_start *msdu_start =
  128. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  129. uint32_t nss;
  130. nss = HAL_RX_MSDU_START_NSS_GET(msdu_start);
  131. return nss;
  132. }
  133. /**
  134. * hal_rx_mon_hw_desc_get_mpdu_status_8074(): Retrieve MPDU status
  135. *
  136. * @ hw_desc_addr: Start address of Rx HW TLVs
  137. * @ rs: Status for monitor mode
  138. *
  139. * Return: void
  140. */
  141. static void hal_rx_mon_hw_desc_get_mpdu_status_8074(void *hw_desc_addr,
  142. struct mon_rx_status *rs)
  143. {
  144. struct rx_msdu_start *rx_msdu_start;
  145. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  146. uint32_t reg_value;
  147. const uint32_t sgi_hw_to_cdp[] = {
  148. CDP_SGI_0_8_US,
  149. CDP_SGI_0_4_US,
  150. CDP_SGI_1_6_US,
  151. CDP_SGI_3_2_US,
  152. };
  153. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  154. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  155. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  156. RX_MSDU_START_5, USER_RSSI);
  157. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  158. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  159. rs->sgi = sgi_hw_to_cdp[reg_value];
  160. rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS);
  161. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  162. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  163. /* TODO: rs->beamformed should be set for SU beamforming also */
  164. }
  165. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  166. static uint32_t hal_get_link_desc_size_8074(void)
  167. {
  168. return LINK_DESC_SIZE;
  169. }
  170. /*
  171. * hal_rx_get_tlv_8074(): API to get the tlv
  172. *
  173. * @rx_tlv: TLV data extracted from the rx packet
  174. * Return: uint8_t
  175. */
  176. static uint8_t hal_rx_get_tlv_8074(void *rx_tlv)
  177. {
  178. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH);
  179. }
  180. /**
  181. * hal_rx_proc_phyrx_other_receive_info_tlv_8074()
  182. * -process other receive info TLV
  183. * @rx_tlv_hdr: pointer to TLV header
  184. * @ppdu_info: pointer to ppdu_info
  185. *
  186. * Return: None
  187. */
  188. static
  189. void hal_rx_proc_phyrx_other_receive_info_tlv_8074(void *rx_tlv_hdr,
  190. void *ppdu_info)
  191. {
  192. }
  193. /**
  194. * hal_rx_dump_msdu_start_tlv_8074() : dump RX msdu_start TLV in structured
  195. * human readable format.
  196. * @ msdu_start: pointer the msdu_start TLV in pkt.
  197. * @ dbg_level: log level.
  198. *
  199. * Return: void
  200. */
  201. static void hal_rx_dump_msdu_start_tlv_8074(void *msdustart,
  202. uint8_t dbg_level)
  203. {
  204. struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
  205. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  206. "rx_msdu_start tlv - "
  207. "rxpcu_mpdu_filter_in_category: %d "
  208. "sw_frame_group_id: %d "
  209. "phy_ppdu_id: %d "
  210. "msdu_length: %d "
  211. "ipsec_esp: %d "
  212. "l3_offset: %d "
  213. "ipsec_ah: %d "
  214. "l4_offset: %d "
  215. "msdu_number: %d "
  216. "decap_format: %d "
  217. "ipv4_proto: %d "
  218. "ipv6_proto: %d "
  219. "tcp_proto: %d "
  220. "udp_proto: %d "
  221. "ip_frag: %d "
  222. "tcp_only_ack: %d "
  223. "da_is_bcast_mcast: %d "
  224. "ip4_protocol_ip6_next_header: %d "
  225. "toeplitz_hash_2_or_4: %d "
  226. "flow_id_toeplitz: %d "
  227. "user_rssi: %d "
  228. "pkt_type: %d "
  229. "stbc: %d "
  230. "sgi: %d "
  231. "rate_mcs: %d "
  232. "receive_bandwidth: %d "
  233. "reception_type: %d "
  234. "toeplitz_hash: %d "
  235. "nss: %d "
  236. "ppdu_start_timestamp: %d "
  237. "sw_phy_meta_data: %d ",
  238. msdu_start->rxpcu_mpdu_filter_in_category,
  239. msdu_start->sw_frame_group_id,
  240. msdu_start->phy_ppdu_id,
  241. msdu_start->msdu_length,
  242. msdu_start->ipsec_esp,
  243. msdu_start->l3_offset,
  244. msdu_start->ipsec_ah,
  245. msdu_start->l4_offset,
  246. msdu_start->msdu_number,
  247. msdu_start->decap_format,
  248. msdu_start->ipv4_proto,
  249. msdu_start->ipv6_proto,
  250. msdu_start->tcp_proto,
  251. msdu_start->udp_proto,
  252. msdu_start->ip_frag,
  253. msdu_start->tcp_only_ack,
  254. msdu_start->da_is_bcast_mcast,
  255. msdu_start->ip4_protocol_ip6_next_header,
  256. msdu_start->toeplitz_hash_2_or_4,
  257. msdu_start->flow_id_toeplitz,
  258. msdu_start->user_rssi,
  259. msdu_start->pkt_type,
  260. msdu_start->stbc,
  261. msdu_start->sgi,
  262. msdu_start->rate_mcs,
  263. msdu_start->receive_bandwidth,
  264. msdu_start->reception_type,
  265. msdu_start->toeplitz_hash,
  266. msdu_start->nss,
  267. msdu_start->ppdu_start_timestamp,
  268. msdu_start->sw_phy_meta_data);
  269. }
  270. /**
  271. * hal_rx_dump_msdu_end_tlv_8074: dump RX msdu_end TLV in structured
  272. * human readable format.
  273. * @ msdu_end: pointer the msdu_end TLV in pkt.
  274. * @ dbg_level: log level.
  275. *
  276. * Return: void
  277. */
  278. static void hal_rx_dump_msdu_end_tlv_8074(void *msduend,
  279. uint8_t dbg_level)
  280. {
  281. struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
  282. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  283. "rx_msdu_end tlv - "
  284. "rxpcu_mpdu_filter_in_category: %d "
  285. "sw_frame_group_id: %d "
  286. "phy_ppdu_id: %d "
  287. "ip_hdr_chksum: %d "
  288. "tcp_udp_chksum: %d "
  289. "key_id_octet: %d "
  290. "cce_super_rule: %d "
  291. "cce_classify_not_done_truncat: %d "
  292. "cce_classify_not_done_cce_dis: %d "
  293. "ext_wapi_pn_63_48: %d "
  294. "ext_wapi_pn_95_64: %d "
  295. "ext_wapi_pn_127_96: %d "
  296. "reported_mpdu_length: %d "
  297. "first_msdu: %d "
  298. "last_msdu: %d "
  299. "sa_idx_timeout: %d "
  300. "da_idx_timeout: %d "
  301. "msdu_limit_error: %d "
  302. "flow_idx_timeout: %d "
  303. "flow_idx_invalid: %d "
  304. "wifi_parser_error: %d "
  305. "amsdu_parser_error: %d "
  306. "sa_is_valid: %d "
  307. "da_is_valid: %d "
  308. "da_is_mcbc: %d "
  309. "l3_header_padding: %d "
  310. "ipv6_options_crc: %d "
  311. "tcp_seq_number: %d "
  312. "tcp_ack_number: %d "
  313. "tcp_flag: %d "
  314. "lro_eligible: %d "
  315. "window_size: %d "
  316. "da_offset: %d "
  317. "sa_offset: %d "
  318. "da_offset_valid: %d "
  319. "sa_offset_valid: %d "
  320. "rule_indication_31_0: %d "
  321. "rule_indication_63_32: %d "
  322. "sa_idx: %d "
  323. "da_idx: %d "
  324. "msdu_drop: %d "
  325. "reo_destination_indication: %d "
  326. "flow_idx: %d "
  327. "fse_metadata: %d "
  328. "cce_metadata: %d "
  329. "sa_sw_peer_id: %d ",
  330. msdu_end->rxpcu_mpdu_filter_in_category,
  331. msdu_end->sw_frame_group_id,
  332. msdu_end->phy_ppdu_id,
  333. msdu_end->ip_hdr_chksum,
  334. msdu_end->tcp_udp_chksum,
  335. msdu_end->key_id_octet,
  336. msdu_end->cce_super_rule,
  337. msdu_end->cce_classify_not_done_truncate,
  338. msdu_end->cce_classify_not_done_cce_dis,
  339. msdu_end->ext_wapi_pn_63_48,
  340. msdu_end->ext_wapi_pn_95_64,
  341. msdu_end->ext_wapi_pn_127_96,
  342. msdu_end->reported_mpdu_length,
  343. msdu_end->first_msdu,
  344. msdu_end->last_msdu,
  345. msdu_end->sa_idx_timeout,
  346. msdu_end->da_idx_timeout,
  347. msdu_end->msdu_limit_error,
  348. msdu_end->flow_idx_timeout,
  349. msdu_end->flow_idx_invalid,
  350. msdu_end->wifi_parser_error,
  351. msdu_end->amsdu_parser_error,
  352. msdu_end->sa_is_valid,
  353. msdu_end->da_is_valid,
  354. msdu_end->da_is_mcbc,
  355. msdu_end->l3_header_padding,
  356. msdu_end->ipv6_options_crc,
  357. msdu_end->tcp_seq_number,
  358. msdu_end->tcp_ack_number,
  359. msdu_end->tcp_flag,
  360. msdu_end->lro_eligible,
  361. msdu_end->window_size,
  362. msdu_end->da_offset,
  363. msdu_end->sa_offset,
  364. msdu_end->da_offset_valid,
  365. msdu_end->sa_offset_valid,
  366. msdu_end->rule_indication_31_0,
  367. msdu_end->rule_indication_63_32,
  368. msdu_end->sa_idx,
  369. msdu_end->da_idx,
  370. msdu_end->msdu_drop,
  371. msdu_end->reo_destination_indication,
  372. msdu_end->flow_idx,
  373. msdu_end->fse_metadata,
  374. msdu_end->cce_metadata,
  375. msdu_end->sa_sw_peer_id);
  376. }
  377. /*
  378. * Get tid from RX_MPDU_START
  379. */
  380. #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
  381. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  382. RX_MPDU_INFO_3_TID_OFFSET)), \
  383. RX_MPDU_INFO_3_TID_MASK, \
  384. RX_MPDU_INFO_3_TID_LSB))
  385. static uint32_t hal_rx_mpdu_start_tid_get_8074(uint8_t *buf)
  386. {
  387. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  388. struct rx_mpdu_start *mpdu_start =
  389. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  390. uint32_t tid;
  391. tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
  392. return tid;
  393. }
  394. #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
  395. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  396. RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
  397. RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
  398. RX_MSDU_START_5_RECEPTION_TYPE_LSB))
  399. /*
  400. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  401. * Interval from rx_msdu_start
  402. *
  403. * @buf: pointer to the start of RX PKT TLV header
  404. * Return: uint32_t(reception_type)
  405. */
  406. static uint32_t hal_rx_msdu_start_reception_type_get_8074(uint8_t *buf)
  407. {
  408. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  409. struct rx_msdu_start *msdu_start =
  410. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  411. uint32_t reception_type;
  412. reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
  413. return reception_type;
  414. }
  415. #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
  416. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  417. RX_MSDU_END_13_DA_IDX_OFFSET)), \
  418. RX_MSDU_END_13_DA_IDX_MASK, \
  419. RX_MSDU_END_13_DA_IDX_LSB))
  420. /**
  421. * hal_rx_msdu_end_da_idx_get_8074: API to get da_idx
  422. * from rx_msdu_end TLV
  423. *
  424. * @ buf: pointer to the start of RX PKT TLV headers
  425. * Return: da index
  426. */
  427. static uint16_t hal_rx_msdu_end_da_idx_get_8074(uint8_t *buf)
  428. {
  429. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  430. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  431. uint16_t da_idx;
  432. da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  433. return da_idx;
  434. }