hal_be_generic_api.h 51 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_BE_GENERIC_API_H_
  19. #define _HAL_BE_GENERIC_API_H_
  20. #include <hal_be_hw_headers.h>
  21. #include "hal_be_tx.h"
  22. #include "hal_be_reo.h"
  23. /**
  24. * hal_tx_comp_get_status() - TQM Release reason
  25. * @hal_desc: completion ring Tx status
  26. *
  27. * This function will parse the WBM completion descriptor and populate in
  28. * HAL structure
  29. *
  30. * Return: none
  31. */
  32. static inline
  33. void hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  34. struct hal_soc *hal)
  35. {
  36. uint8_t rate_stats_valid = 0;
  37. uint32_t rate_stats = 0;
  38. struct hal_tx_completion_status *ts =
  39. (struct hal_tx_completion_status *)ts1;
  40. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  41. TQM_STATUS_NUMBER);
  42. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  43. ACK_FRAME_RSSI);
  44. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  45. FIRST_MSDU);
  46. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  47. LAST_MSDU);
  48. #if 0
  49. // TODO - This has to be calculated form first and last msdu
  50. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  51. WBM2SW_COMPLETION_RING_TX,
  52. MSDU_PART_OF_AMSDU);
  53. #endif
  54. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  55. SW_PEER_ID);
  56. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  57. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  58. TRANSMIT_COUNT);
  59. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  60. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  61. TX_RATE_STATS_INFO_VALID, rate_stats);
  62. ts->valid = rate_stats_valid;
  63. if (rate_stats_valid) {
  64. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  65. rate_stats);
  66. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  67. TRANSMIT_PKT_TYPE, rate_stats);
  68. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  69. TRANSMIT_STBC, rate_stats);
  70. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  71. rate_stats);
  72. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  73. rate_stats);
  74. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  75. rate_stats);
  76. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  77. rate_stats);
  78. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  79. rate_stats);
  80. }
  81. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  82. ts->status = hal_tx_comp_get_release_reason(
  83. desc,
  84. hal_soc_to_hal_soc_handle(hal));
  85. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  86. TX_RATE_STATS_INFO_TX_RATE_STATS);
  87. }
  88. /**
  89. * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
  90. * @desc: Handle to Tx Descriptor
  91. * @paddr: Physical Address
  92. * @pool_id: Return Buffer Manager ID
  93. * @desc_id: Descriptor ID
  94. * @type: 0 - Address points to a MSDU buffer
  95. * 1 - Address points to MSDU extension descriptor
  96. *
  97. * Return: void
  98. */
  99. static inline void
  100. hal_tx_desc_set_buf_addr_generic_be(void *desc, dma_addr_t paddr,
  101. uint8_t rbm_id, uint32_t desc_id,
  102. uint8_t type)
  103. {
  104. /* Set buffer_addr_info.buffer_addr_31_0 */
  105. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0,
  106. BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
  107. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
  108. /* Set buffer_addr_info.buffer_addr_39_32 */
  109. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  110. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  111. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
  112. (((uint64_t)paddr) >> 32));
  113. /* Set buffer_addr_info.return_buffer_manager = rbm id */
  114. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  115. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  116. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1,
  117. RETURN_BUFFER_MANAGER, rbm_id);
  118. /* Set buffer_addr_info.sw_buffer_cookie = desc_id */
  119. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  120. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  121. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
  122. desc_id);
  123. /* Set Buffer or Ext Descriptor Type */
  124. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2,
  125. BUF_OR_EXT_DESC_TYPE) |=
  126. HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
  127. }
  128. #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
  129. /**
  130. * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
  131. * tlv_tag: Taf of the TLVs
  132. * rx_tlv: the pointer to the TLVs
  133. * @ppdu_info: pointer to ppdu_info
  134. *
  135. * Return: true if the tlv is handled, false if not
  136. */
  137. static inline bool
  138. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  139. struct hal_rx_ppdu_info *ppdu_info)
  140. {
  141. uint32_t value;
  142. switch (tlv_tag) {
  143. case WIFIPHYRX_HE_SIG_A_MU_UL_E:
  144. {
  145. uint8_t *he_sig_a_mu_ul_info =
  146. (uint8_t *)rx_tlv +
  147. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL,
  148. HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
  149. ppdu_info->rx_status.he_flags = 1;
  150. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  151. FORMAT_INDICATION);
  152. if (value == 0) {
  153. ppdu_info->rx_status.he_data1 =
  154. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  155. } else {
  156. ppdu_info->rx_status.he_data1 =
  157. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  158. }
  159. /* data1 */
  160. ppdu_info->rx_status.he_data1 |=
  161. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  162. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  163. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  164. /* data2 */
  165. ppdu_info->rx_status.he_data2 |=
  166. QDF_MON_STATUS_TXOP_KNOWN;
  167. /*data3*/
  168. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  169. HE_SIG_A_MU_UL_INFO, BSS_COLOR_ID);
  170. ppdu_info->rx_status.he_data3 = value;
  171. /* 1 for UL and 0 for DL */
  172. value = 1;
  173. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  174. ppdu_info->rx_status.he_data3 |= value;
  175. /*data4*/
  176. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  177. SPATIAL_REUSE);
  178. ppdu_info->rx_status.he_data4 = value;
  179. /*data5*/
  180. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  181. HE_SIG_A_MU_UL_INFO, TRANSMIT_BW);
  182. ppdu_info->rx_status.he_data5 = value;
  183. ppdu_info->rx_status.bw = value;
  184. /*data6*/
  185. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  186. TXOP_DURATION);
  187. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  188. ppdu_info->rx_status.he_data6 |= value;
  189. return true;
  190. }
  191. default:
  192. return false;
  193. }
  194. }
  195. #else
  196. static inline bool
  197. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  198. struct hal_rx_ppdu_info *ppdu_info)
  199. {
  200. return false;
  201. }
  202. #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
  203. #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \
  204. defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
  205. static inline void
  206. hal_rx_handle_mu_ul_info(void *rx_tlv,
  207. struct mon_rx_user_status *mon_rx_user_status)
  208. {
  209. mon_rx_user_status->mu_ul_user_v0_word0 =
  210. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  211. SW_RESPONSE_REFERENCE_PTR);
  212. mon_rx_user_status->mu_ul_user_v0_word1 =
  213. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  214. SW_RESPONSE_REFERENCE_PTR_EXT);
  215. }
  216. static inline void
  217. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  218. struct mon_rx_user_status *mon_rx_user_status)
  219. {
  220. uint32_t mpdu_ok_byte_count;
  221. uint32_t mpdu_err_byte_count;
  222. mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
  223. RX_PPDU_END_USER_STATS,
  224. MPDU_OK_BYTE_COUNT);
  225. mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
  226. RX_PPDU_END_USER_STATS,
  227. MPDU_ERR_BYTE_COUNT);
  228. mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
  229. mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
  230. }
  231. #else
  232. static inline void
  233. hal_rx_handle_mu_ul_info(void *rx_tlv,
  234. struct mon_rx_user_status *mon_rx_user_status)
  235. {
  236. }
  237. static inline void
  238. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  239. struct mon_rx_user_status *mon_rx_user_status)
  240. {
  241. struct hal_rx_ppdu_info *ppdu_info =
  242. (struct hal_rx_ppdu_info *)ppduinfo;
  243. /* HKV1: doesn't support mpdu byte count */
  244. mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
  245. mon_rx_user_status->mpdu_err_byte_count = 0;
  246. }
  247. #endif
  248. static inline void
  249. hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
  250. struct mon_rx_user_status *mon_rx_user_status)
  251. {
  252. struct mon_rx_info *mon_rx_info;
  253. struct mon_rx_user_info *mon_rx_user_info;
  254. struct hal_rx_ppdu_info *ppdu_info =
  255. (struct hal_rx_ppdu_info *)ppduinfo;
  256. mon_rx_info = &ppdu_info->rx_info;
  257. mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
  258. mon_rx_user_info->qos_control_info_valid =
  259. mon_rx_info->qos_control_info_valid;
  260. mon_rx_user_info->qos_control = mon_rx_info->qos_control;
  261. mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
  262. mon_rx_user_status->tid = ppdu_info->rx_status.tid;
  263. mon_rx_user_status->tcp_msdu_count =
  264. ppdu_info->rx_status.tcp_msdu_count;
  265. mon_rx_user_status->udp_msdu_count =
  266. ppdu_info->rx_status.udp_msdu_count;
  267. mon_rx_user_status->other_msdu_count =
  268. ppdu_info->rx_status.other_msdu_count;
  269. mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
  270. mon_rx_user_status->frame_control_info_valid =
  271. ppdu_info->rx_status.frame_control_info_valid;
  272. mon_rx_user_status->data_sequence_control_info_valid =
  273. ppdu_info->rx_status.data_sequence_control_info_valid;
  274. mon_rx_user_status->first_data_seq_ctrl =
  275. ppdu_info->rx_status.first_data_seq_ctrl;
  276. mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
  277. mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
  278. mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
  279. mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
  280. mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
  281. mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
  282. mon_rx_user_status->mpdu_cnt_fcs_ok =
  283. ppdu_info->com_info.mpdu_cnt_fcs_ok;
  284. mon_rx_user_status->mpdu_cnt_fcs_err =
  285. ppdu_info->com_info.mpdu_cnt_fcs_err;
  286. qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
  287. &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
  288. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  289. sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
  290. hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
  291. }
  292. #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \
  293. ppdu_info, rssi_info_tlv) \
  294. { \
  295. ppdu_info->rx_status.rssi_chain[chain][0] = \
  296. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  297. RSSI_PRI20_CHAIN##chain); \
  298. ppdu_info->rx_status.rssi_chain[chain][1] = \
  299. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  300. RSSI_EXT20_CHAIN##chain); \
  301. ppdu_info->rx_status.rssi_chain[chain][2] = \
  302. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  303. RSSI_EXT40_LOW20_CHAIN##chain); \
  304. ppdu_info->rx_status.rssi_chain[chain][3] = \
  305. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  306. RSSI_EXT40_HIGH20_CHAIN##chain); \
  307. ppdu_info->rx_status.rssi_chain[chain][4] = \
  308. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  309. RSSI_EXT80_LOW20_CHAIN##chain); \
  310. ppdu_info->rx_status.rssi_chain[chain][5] = \
  311. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  312. RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
  313. ppdu_info->rx_status.rssi_chain[chain][6] = \
  314. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  315. RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
  316. ppdu_info->rx_status.rssi_chain[chain][7] = \
  317. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  318. RSSI_EXT80_HIGH20_CHAIN##chain); \
  319. } \
  320. #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
  321. {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \
  322. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \
  323. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \
  324. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \
  325. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, ppdu_info, rssi_info_tlv) \
  326. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, ppdu_info, rssi_info_tlv) \
  327. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, ppdu_info, rssi_info_tlv) \
  328. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, ppdu_info, rssi_info_tlv)} \
  329. static inline uint32_t
  330. hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  331. uint8_t *rssi_info_tlv)
  332. {
  333. // TODO - Find all these registers for wcn7850
  334. #if 0
  335. HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
  336. #endif
  337. return 0;
  338. }
  339. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  340. static inline void
  341. hal_get_qos_control(void *rx_tlv,
  342. struct hal_rx_ppdu_info *ppdu_info)
  343. {
  344. ppdu_info->rx_info.qos_control_info_valid =
  345. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  346. QOS_CONTROL_INFO_VALID);
  347. if (ppdu_info->rx_info.qos_control_info_valid)
  348. ppdu_info->rx_info.qos_control =
  349. HAL_RX_GET(rx_tlv,
  350. RX_PPDU_END_USER_STATS,
  351. QOS_CONTROL_FIELD);
  352. }
  353. static inline void
  354. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  355. struct hal_rx_ppdu_info *ppdu_info)
  356. {
  357. if ((ppdu_info->sw_frame_group_id
  358. == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
  359. (ppdu_info->sw_frame_group_id ==
  360. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
  361. ppdu_info->rx_info.mac_addr1_valid =
  362. HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
  363. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
  364. HAL_RX_GET(rx_mpdu_start,
  365. RX_MPDU_INFO,
  366. MAC_ADDR_AD1_31_0);
  367. if (ppdu_info->sw_frame_group_id ==
  368. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
  369. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] =
  370. HAL_RX_GET(rx_mpdu_start,
  371. RX_MPDU_INFO,
  372. MAC_ADDR_AD1_47_32);
  373. }
  374. }
  375. }
  376. #else
  377. static inline void
  378. hal_get_qos_control(void *rx_tlv,
  379. struct hal_rx_ppdu_info *ppdu_info)
  380. {
  381. }
  382. static inline void
  383. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  384. struct hal_rx_ppdu_info *ppdu_info)
  385. {
  386. }
  387. #endif
  388. /**
  389. * hal_rx_status_get_tlv_info() - process receive info TLV
  390. * @rx_tlv_hdr: pointer to TLV header
  391. * @ppdu_info: pointer to ppdu_info
  392. *
  393. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  394. */
  395. static inline uint32_t
  396. hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo,
  397. hal_soc_handle_t hal_soc_hdl,
  398. qdf_nbuf_t nbuf)
  399. {
  400. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  401. uint32_t tlv_tag, user_id, tlv_len, value;
  402. uint8_t group_id = 0;
  403. uint8_t he_dcm = 0;
  404. uint8_t he_stbc = 0;
  405. uint16_t he_gi = 0;
  406. uint16_t he_ltf = 0;
  407. void *rx_tlv;
  408. bool unhandled = false;
  409. struct mon_rx_user_status *mon_rx_user_status;
  410. struct hal_rx_ppdu_info *ppdu_info =
  411. (struct hal_rx_ppdu_info *)ppduinfo;
  412. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  413. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
  414. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  415. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  416. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  417. rx_tlv, tlv_len);
  418. switch (tlv_tag) {
  419. case WIFIRX_PPDU_START_E:
  420. {
  421. if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
  422. HAL_RX_GET(rx_tlv, RX_PPDU_START, PHY_PPDU_ID)))
  423. hal_err("Matching ppdu_id(%u) detected",
  424. ppdu_info->com_info.last_ppdu_id);
  425. /* Reset ppdu_info before processing the ppdu */
  426. qdf_mem_zero(ppdu_info,
  427. sizeof(struct hal_rx_ppdu_info));
  428. ppdu_info->com_info.last_ppdu_id =
  429. ppdu_info->com_info.ppdu_id =
  430. HAL_RX_GET(rx_tlv, RX_PPDU_START,
  431. PHY_PPDU_ID);
  432. /* channel number is set in PHY meta data */
  433. ppdu_info->rx_status.chan_num =
  434. (HAL_RX_GET(rx_tlv, RX_PPDU_START,
  435. SW_PHY_META_DATA) & 0x0000FFFF);
  436. ppdu_info->rx_status.chan_freq =
  437. (HAL_RX_GET(rx_tlv, RX_PPDU_START,
  438. SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
  439. if (ppdu_info->rx_status.chan_num &&
  440. ppdu_info->rx_status.chan_freq) {
  441. ppdu_info->rx_status.chan_freq =
  442. hal_rx_radiotap_num_to_freq(
  443. ppdu_info->rx_status.chan_num,
  444. ppdu_info->rx_status.chan_freq);
  445. }
  446. #ifdef DP_BE_NOTYET_WAR
  447. // TODO - timestamp is changed to 64-bit for wcn7850
  448. ppdu_info->com_info.ppdu_timestamp =
  449. HAL_RX_GET(rx_tlv, RX_PPDU_START,
  450. PPDU_START_TIMESTAMP);
  451. #endif
  452. ppdu_info->rx_status.ppdu_timestamp =
  453. ppdu_info->com_info.ppdu_timestamp;
  454. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  455. break;
  456. }
  457. case WIFIRX_PPDU_START_USER_INFO_E:
  458. break;
  459. case WIFIRX_PPDU_END_E:
  460. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  461. "[%s][%d] ppdu_end_e len=%d",
  462. __func__, __LINE__, tlv_len);
  463. /* This is followed by sub-TLVs of PPDU_END */
  464. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  465. break;
  466. case WIFIPHYRX_PKT_END_E:
  467. hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
  468. break;
  469. case WIFIRXPCU_PPDU_END_INFO_E:
  470. ppdu_info->rx_status.rx_antenna =
  471. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA);
  472. ppdu_info->rx_status.tsft =
  473. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO,
  474. WB_TIMESTAMP_UPPER_32);
  475. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  476. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO,
  477. WB_TIMESTAMP_LOWER_32);
  478. ppdu_info->rx_status.duration =
  479. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
  480. RX_PPDU_DURATION);
  481. hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
  482. break;
  483. /*
  484. * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
  485. * for MU, based on num users we see this tlv that many times.
  486. */
  487. case WIFIRX_PPDU_END_USER_STATS_E:
  488. {
  489. unsigned long tid = 0;
  490. uint16_t seq = 0;
  491. ppdu_info->rx_status.ast_index =
  492. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  493. AST_INDEX);
  494. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  495. RECEIVED_QOS_DATA_TID_BITMAP);
  496. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
  497. sizeof(tid) * 8);
  498. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  499. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  500. ppdu_info->rx_status.tcp_msdu_count =
  501. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  502. TCP_MSDU_COUNT) +
  503. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  504. TCP_ACK_MSDU_COUNT);
  505. ppdu_info->rx_status.udp_msdu_count =
  506. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  507. UDP_MSDU_COUNT);
  508. ppdu_info->rx_status.other_msdu_count =
  509. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  510. OTHER_MSDU_COUNT);
  511. if (ppdu_info->sw_frame_group_id
  512. != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  513. ppdu_info->rx_status.frame_control_info_valid =
  514. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  515. FRAME_CONTROL_INFO_VALID);
  516. if (ppdu_info->rx_status.frame_control_info_valid)
  517. ppdu_info->rx_status.frame_control =
  518. HAL_RX_GET(rx_tlv,
  519. RX_PPDU_END_USER_STATS,
  520. FRAME_CONTROL_FIELD);
  521. hal_get_qos_control(rx_tlv, ppdu_info);
  522. }
  523. ppdu_info->rx_status.data_sequence_control_info_valid =
  524. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  525. DATA_SEQUENCE_CONTROL_INFO_VALID);
  526. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  527. FIRST_DATA_SEQ_CTRL);
  528. if (ppdu_info->rx_status.data_sequence_control_info_valid)
  529. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  530. ppdu_info->rx_status.preamble_type =
  531. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  532. HT_CONTROL_FIELD_PKT_TYPE);
  533. switch (ppdu_info->rx_status.preamble_type) {
  534. case HAL_RX_PKT_TYPE_11N:
  535. ppdu_info->rx_status.ht_flags = 1;
  536. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  537. break;
  538. case HAL_RX_PKT_TYPE_11AC:
  539. ppdu_info->rx_status.vht_flags = 1;
  540. break;
  541. case HAL_RX_PKT_TYPE_11AX:
  542. ppdu_info->rx_status.he_flags = 1;
  543. break;
  544. default:
  545. break;
  546. }
  547. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  548. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  549. MPDU_CNT_FCS_OK);
  550. ppdu_info->com_info.mpdu_cnt_fcs_err =
  551. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  552. MPDU_CNT_FCS_ERR);
  553. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  554. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  555. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  556. else
  557. ppdu_info->rx_status.rs_flags &=
  558. (~IEEE80211_AMPDU_FLAG);
  559. ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
  560. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  561. FCS_OK_BITMAP_31_0);
  562. ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
  563. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  564. FCS_OK_BITMAP_63_32);
  565. if (user_id < HAL_MAX_UL_MU_USERS) {
  566. mon_rx_user_status =
  567. &ppdu_info->rx_user_status[user_id];
  568. hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
  569. ppdu_info->com_info.num_users++;
  570. hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
  571. user_id,
  572. mon_rx_user_status);
  573. }
  574. break;
  575. }
  576. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  577. ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
  578. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  579. FCS_OK_BITMAP_95_64);
  580. ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
  581. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  582. FCS_OK_BITMAP_127_96);
  583. ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
  584. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  585. FCS_OK_BITMAP_159_128);
  586. ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
  587. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  588. FCS_OK_BITMAP_191_160);
  589. ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
  590. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  591. FCS_OK_BITMAP_223_192);
  592. ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
  593. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  594. FCS_OK_BITMAP_255_224);
  595. break;
  596. case WIFIRX_PPDU_END_STATUS_DONE_E:
  597. return HAL_TLV_STATUS_PPDU_DONE;
  598. case WIFIDUMMY_E:
  599. return HAL_TLV_STATUS_BUF_DONE;
  600. case WIFIPHYRX_HT_SIG_E:
  601. {
  602. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  603. HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
  604. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  605. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO,
  606. FEC_CODING);
  607. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  608. 1 : 0;
  609. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  610. HT_SIG_INFO, MCS);
  611. ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
  612. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  613. HT_SIG_INFO, CBW);
  614. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  615. HT_SIG_INFO, SHORT_GI);
  616. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  617. ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
  618. HT_SIG_SU_NSS_SHIFT) + 1;
  619. ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
  620. break;
  621. }
  622. case WIFIPHYRX_L_SIG_B_E:
  623. {
  624. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  625. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
  626. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  627. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE);
  628. ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
  629. switch (value) {
  630. case 1:
  631. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  632. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  633. break;
  634. case 2:
  635. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  636. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  637. break;
  638. case 3:
  639. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  640. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  641. break;
  642. case 4:
  643. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  644. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  645. break;
  646. case 5:
  647. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  648. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  649. break;
  650. case 6:
  651. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  652. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  653. break;
  654. case 7:
  655. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  656. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  657. break;
  658. default:
  659. break;
  660. }
  661. ppdu_info->rx_status.cck_flag = 1;
  662. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  663. break;
  664. }
  665. case WIFIPHYRX_L_SIG_A_E:
  666. {
  667. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  668. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
  669. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  670. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE);
  671. ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
  672. switch (value) {
  673. case 8:
  674. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  675. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  676. break;
  677. case 9:
  678. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  679. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  680. break;
  681. case 10:
  682. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  683. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  684. break;
  685. case 11:
  686. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  687. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  688. break;
  689. case 12:
  690. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  691. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  692. break;
  693. case 13:
  694. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  695. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  696. break;
  697. case 14:
  698. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  699. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  700. break;
  701. case 15:
  702. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  703. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
  704. break;
  705. default:
  706. break;
  707. }
  708. ppdu_info->rx_status.ofdm_flag = 1;
  709. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  710. break;
  711. }
  712. case WIFIPHYRX_VHT_SIG_A_E:
  713. {
  714. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  715. HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
  716. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  717. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO,
  718. SU_MU_CODING);
  719. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  720. 1 : 0;
  721. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID);
  722. ppdu_info->rx_status.vht_flag_values5 = group_id;
  723. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  724. VHT_SIG_A_INFO, MCS);
  725. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  726. VHT_SIG_A_INFO, GI_SETTING);
  727. switch (hal->target_type) {
  728. case TARGET_TYPE_QCA8074:
  729. case TARGET_TYPE_QCA8074V2:
  730. case TARGET_TYPE_QCA6018:
  731. case TARGET_TYPE_QCA5018:
  732. case TARGET_TYPE_QCN9000:
  733. case TARGET_TYPE_QCN6122:
  734. #ifdef QCA_WIFI_QCA6390
  735. case TARGET_TYPE_QCA6390:
  736. #endif
  737. ppdu_info->rx_status.is_stbc =
  738. HAL_RX_GET(vht_sig_a_info,
  739. VHT_SIG_A_INFO, STBC);
  740. value = HAL_RX_GET(vht_sig_a_info,
  741. VHT_SIG_A_INFO, N_STS);
  742. value = value & VHT_SIG_SU_NSS_MASK;
  743. if (ppdu_info->rx_status.is_stbc && (value > 0))
  744. value = ((value + 1) >> 1) - 1;
  745. ppdu_info->rx_status.nss =
  746. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  747. break;
  748. case TARGET_TYPE_QCA6290:
  749. #if !defined(QCA_WIFI_QCA6290_11AX)
  750. ppdu_info->rx_status.is_stbc =
  751. HAL_RX_GET(vht_sig_a_info,
  752. VHT_SIG_A_INFO, STBC);
  753. value = HAL_RX_GET(vht_sig_a_info,
  754. VHT_SIG_A_INFO, N_STS);
  755. value = value & VHT_SIG_SU_NSS_MASK;
  756. if (ppdu_info->rx_status.is_stbc && (value > 0))
  757. value = ((value + 1) >> 1) - 1;
  758. ppdu_info->rx_status.nss =
  759. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  760. #else
  761. ppdu_info->rx_status.nss = 0;
  762. #endif
  763. break;
  764. case TARGET_TYPE_QCA6490:
  765. case TARGET_TYPE_QCA6750:
  766. case TARGET_TYPE_WCN7850:
  767. ppdu_info->rx_status.nss = 0;
  768. break;
  769. default:
  770. break;
  771. }
  772. ppdu_info->rx_status.vht_flag_values3[0] =
  773. (((ppdu_info->rx_status.mcs) << 4)
  774. | ppdu_info->rx_status.nss);
  775. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  776. VHT_SIG_A_INFO, BANDWIDTH);
  777. ppdu_info->rx_status.vht_flag_values2 =
  778. ppdu_info->rx_status.bw;
  779. ppdu_info->rx_status.vht_flag_values4 =
  780. HAL_RX_GET(vht_sig_a_info,
  781. VHT_SIG_A_INFO, SU_MU_CODING);
  782. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  783. VHT_SIG_A_INFO, BEAMFORMED);
  784. if (group_id == 0 || group_id == 63)
  785. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  786. else
  787. ppdu_info->rx_status.reception_type =
  788. HAL_RX_TYPE_MU_MIMO;
  789. break;
  790. }
  791. case WIFIPHYRX_HE_SIG_A_SU_E:
  792. {
  793. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  794. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
  795. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  796. ppdu_info->rx_status.he_flags = 1;
  797. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  798. FORMAT_INDICATION);
  799. if (value == 0) {
  800. ppdu_info->rx_status.he_data1 =
  801. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  802. } else {
  803. ppdu_info->rx_status.he_data1 =
  804. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  805. }
  806. /* data1 */
  807. ppdu_info->rx_status.he_data1 |=
  808. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  809. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  810. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  811. QDF_MON_STATUS_HE_MCS_KNOWN |
  812. QDF_MON_STATUS_HE_DCM_KNOWN |
  813. QDF_MON_STATUS_HE_CODING_KNOWN |
  814. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  815. QDF_MON_STATUS_HE_STBC_KNOWN |
  816. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  817. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  818. /* data2 */
  819. ppdu_info->rx_status.he_data2 =
  820. QDF_MON_STATUS_HE_GI_KNOWN;
  821. ppdu_info->rx_status.he_data2 |=
  822. QDF_MON_STATUS_TXBF_KNOWN |
  823. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  824. QDF_MON_STATUS_TXOP_KNOWN |
  825. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  826. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  827. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  828. /* data3 */
  829. value = HAL_RX_GET(he_sig_a_su_info,
  830. HE_SIG_A_SU_INFO, BSS_COLOR_ID);
  831. ppdu_info->rx_status.he_data3 = value;
  832. value = HAL_RX_GET(he_sig_a_su_info,
  833. HE_SIG_A_SU_INFO, BEAM_CHANGE);
  834. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  835. ppdu_info->rx_status.he_data3 |= value;
  836. value = HAL_RX_GET(he_sig_a_su_info,
  837. HE_SIG_A_SU_INFO, DL_UL_FLAG);
  838. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  839. ppdu_info->rx_status.he_data3 |= value;
  840. value = HAL_RX_GET(he_sig_a_su_info,
  841. HE_SIG_A_SU_INFO, TRANSMIT_MCS);
  842. ppdu_info->rx_status.mcs = value;
  843. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  844. ppdu_info->rx_status.he_data3 |= value;
  845. value = HAL_RX_GET(he_sig_a_su_info,
  846. HE_SIG_A_SU_INFO, DCM);
  847. he_dcm = value;
  848. value = value << QDF_MON_STATUS_DCM_SHIFT;
  849. ppdu_info->rx_status.he_data3 |= value;
  850. value = HAL_RX_GET(he_sig_a_su_info,
  851. HE_SIG_A_SU_INFO, CODING);
  852. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  853. 1 : 0;
  854. value = value << QDF_MON_STATUS_CODING_SHIFT;
  855. ppdu_info->rx_status.he_data3 |= value;
  856. value = HAL_RX_GET(he_sig_a_su_info,
  857. HE_SIG_A_SU_INFO,
  858. LDPC_EXTRA_SYMBOL);
  859. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  860. ppdu_info->rx_status.he_data3 |= value;
  861. value = HAL_RX_GET(he_sig_a_su_info,
  862. HE_SIG_A_SU_INFO, STBC);
  863. he_stbc = value;
  864. value = value << QDF_MON_STATUS_STBC_SHIFT;
  865. ppdu_info->rx_status.he_data3 |= value;
  866. /* data4 */
  867. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  868. SPATIAL_REUSE);
  869. ppdu_info->rx_status.he_data4 = value;
  870. /* data5 */
  871. value = HAL_RX_GET(he_sig_a_su_info,
  872. HE_SIG_A_SU_INFO, TRANSMIT_BW);
  873. ppdu_info->rx_status.he_data5 = value;
  874. ppdu_info->rx_status.bw = value;
  875. value = HAL_RX_GET(he_sig_a_su_info,
  876. HE_SIG_A_SU_INFO, CP_LTF_SIZE);
  877. switch (value) {
  878. case 0:
  879. he_gi = HE_GI_0_8;
  880. he_ltf = HE_LTF_1_X;
  881. break;
  882. case 1:
  883. he_gi = HE_GI_0_8;
  884. he_ltf = HE_LTF_2_X;
  885. break;
  886. case 2:
  887. he_gi = HE_GI_1_6;
  888. he_ltf = HE_LTF_2_X;
  889. break;
  890. case 3:
  891. if (he_dcm && he_stbc) {
  892. he_gi = HE_GI_0_8;
  893. he_ltf = HE_LTF_4_X;
  894. } else {
  895. he_gi = HE_GI_3_2;
  896. he_ltf = HE_LTF_4_X;
  897. }
  898. break;
  899. }
  900. ppdu_info->rx_status.sgi = he_gi;
  901. ppdu_info->rx_status.ltf_size = he_ltf;
  902. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  903. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  904. ppdu_info->rx_status.he_data5 |= value;
  905. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  906. ppdu_info->rx_status.he_data5 |= value;
  907. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  908. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  909. ppdu_info->rx_status.he_data5 |= value;
  910. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  911. PACKET_EXTENSION_A_FACTOR);
  912. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  913. ppdu_info->rx_status.he_data5 |= value;
  914. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF);
  915. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  916. ppdu_info->rx_status.he_data5 |= value;
  917. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  918. PACKET_EXTENSION_PE_DISAMBIGUITY);
  919. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  920. ppdu_info->rx_status.he_data5 |= value;
  921. /* data6 */
  922. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  923. value++;
  924. ppdu_info->rx_status.nss = value;
  925. ppdu_info->rx_status.he_data6 = value;
  926. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  927. DOPPLER_INDICATION);
  928. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  929. ppdu_info->rx_status.he_data6 |= value;
  930. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  931. TXOP_DURATION);
  932. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  933. ppdu_info->rx_status.he_data6 |= value;
  934. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  935. HE_SIG_A_SU_INFO, TXBF);
  936. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  937. break;
  938. }
  939. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  940. {
  941. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  942. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
  943. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  944. ppdu_info->rx_status.he_mu_flags = 1;
  945. /* HE Flags */
  946. /*data1*/
  947. ppdu_info->rx_status.he_data1 =
  948. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  949. ppdu_info->rx_status.he_data1 |=
  950. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  951. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  952. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  953. QDF_MON_STATUS_HE_STBC_KNOWN |
  954. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  955. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  956. /* data2 */
  957. ppdu_info->rx_status.he_data2 =
  958. QDF_MON_STATUS_HE_GI_KNOWN;
  959. ppdu_info->rx_status.he_data2 |=
  960. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  961. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  962. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  963. QDF_MON_STATUS_TXOP_KNOWN |
  964. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  965. /*data3*/
  966. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  967. HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID);
  968. ppdu_info->rx_status.he_data3 = value;
  969. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  970. HE_SIG_A_MU_DL_INFO, DL_UL_FLAG);
  971. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  972. ppdu_info->rx_status.he_data3 |= value;
  973. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  974. HE_SIG_A_MU_DL_INFO,
  975. LDPC_EXTRA_SYMBOL);
  976. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  977. ppdu_info->rx_status.he_data3 |= value;
  978. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  979. HE_SIG_A_MU_DL_INFO, STBC);
  980. he_stbc = value;
  981. value = value << QDF_MON_STATUS_STBC_SHIFT;
  982. ppdu_info->rx_status.he_data3 |= value;
  983. /*data4*/
  984. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  985. SPATIAL_REUSE);
  986. ppdu_info->rx_status.he_data4 = value;
  987. /*data5*/
  988. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  989. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  990. ppdu_info->rx_status.he_data5 = value;
  991. ppdu_info->rx_status.bw = value;
  992. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  993. HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE);
  994. switch (value) {
  995. case 0:
  996. he_gi = HE_GI_0_8;
  997. he_ltf = HE_LTF_4_X;
  998. break;
  999. case 1:
  1000. he_gi = HE_GI_0_8;
  1001. he_ltf = HE_LTF_2_X;
  1002. break;
  1003. case 2:
  1004. he_gi = HE_GI_1_6;
  1005. he_ltf = HE_LTF_2_X;
  1006. break;
  1007. case 3:
  1008. he_gi = HE_GI_3_2;
  1009. he_ltf = HE_LTF_4_X;
  1010. break;
  1011. }
  1012. ppdu_info->rx_status.sgi = he_gi;
  1013. ppdu_info->rx_status.ltf_size = he_ltf;
  1014. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  1015. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  1016. ppdu_info->rx_status.he_data5 |= value;
  1017. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  1018. ppdu_info->rx_status.he_data5 |= value;
  1019. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1020. HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS);
  1021. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  1022. ppdu_info->rx_status.he_data5 |= value;
  1023. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  1024. PACKET_EXTENSION_A_FACTOR);
  1025. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  1026. ppdu_info->rx_status.he_data5 |= value;
  1027. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  1028. PACKET_EXTENSION_PE_DISAMBIGUITY);
  1029. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  1030. ppdu_info->rx_status.he_data5 |= value;
  1031. /*data6*/
  1032. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  1033. DOPPLER_INDICATION);
  1034. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  1035. ppdu_info->rx_status.he_data6 |= value;
  1036. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  1037. TXOP_DURATION);
  1038. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  1039. ppdu_info->rx_status.he_data6 |= value;
  1040. /* HE-MU Flags */
  1041. /* HE-MU-flags1 */
  1042. ppdu_info->rx_status.he_flags1 =
  1043. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1044. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1045. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1046. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1047. QDF_MON_STATUS_RU_0_KNOWN;
  1048. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1049. HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B);
  1050. ppdu_info->rx_status.he_flags1 |= value;
  1051. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1052. HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B);
  1053. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  1054. ppdu_info->rx_status.he_flags1 |= value;
  1055. /* HE-MU-flags2 */
  1056. ppdu_info->rx_status.he_flags2 =
  1057. QDF_MON_STATUS_BW_KNOWN;
  1058. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1059. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  1060. ppdu_info->rx_status.he_flags2 |= value;
  1061. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1062. HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B);
  1063. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1064. ppdu_info->rx_status.he_flags2 |= value;
  1065. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1066. HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS);
  1067. value = value - 1;
  1068. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1069. ppdu_info->rx_status.he_flags2 |= value;
  1070. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1071. break;
  1072. }
  1073. case WIFIPHYRX_HE_SIG_B1_MU_E:
  1074. {
  1075. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  1076. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
  1077. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  1078. ppdu_info->rx_status.he_sig_b_common_known |=
  1079. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  1080. /* TODO: Check on the availability of other fields in
  1081. * sig_b_common
  1082. */
  1083. value = HAL_RX_GET(he_sig_b1_mu_info,
  1084. HE_SIG_B1_MU_INFO, RU_ALLOCATION);
  1085. ppdu_info->rx_status.he_RU[0] = value;
  1086. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1087. break;
  1088. }
  1089. case WIFIPHYRX_HE_SIG_B2_MU_E:
  1090. {
  1091. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  1092. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
  1093. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  1094. /*
  1095. * Not all "HE" fields can be updated from
  1096. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1097. * to populate rest of the "HE" fields for MU scenarios.
  1098. */
  1099. /* HE-data1 */
  1100. ppdu_info->rx_status.he_data1 |=
  1101. QDF_MON_STATUS_HE_MCS_KNOWN |
  1102. QDF_MON_STATUS_HE_CODING_KNOWN;
  1103. /* HE-data2 */
  1104. /* HE-data3 */
  1105. value = HAL_RX_GET(he_sig_b2_mu_info,
  1106. HE_SIG_B2_MU_INFO, STA_MCS);
  1107. ppdu_info->rx_status.mcs = value;
  1108. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1109. ppdu_info->rx_status.he_data3 |= value;
  1110. value = HAL_RX_GET(he_sig_b2_mu_info,
  1111. HE_SIG_B2_MU_INFO, STA_CODING);
  1112. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1113. ppdu_info->rx_status.he_data3 |= value;
  1114. /* HE-data4 */
  1115. value = HAL_RX_GET(he_sig_b2_mu_info,
  1116. HE_SIG_B2_MU_INFO, STA_ID);
  1117. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1118. ppdu_info->rx_status.he_data4 |= value;
  1119. /* HE-data5 */
  1120. /* HE-data6 */
  1121. value = HAL_RX_GET(he_sig_b2_mu_info,
  1122. HE_SIG_B2_MU_INFO, NSTS);
  1123. /* value n indicates n+1 spatial streams */
  1124. value++;
  1125. ppdu_info->rx_status.nss = value;
  1126. ppdu_info->rx_status.he_data6 |= value;
  1127. break;
  1128. }
  1129. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  1130. {
  1131. uint8_t *he_sig_b2_ofdma_info =
  1132. (uint8_t *)rx_tlv +
  1133. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
  1134. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  1135. /*
  1136. * Not all "HE" fields can be updated from
  1137. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1138. * to populate rest of "HE" fields for MU OFDMA scenarios.
  1139. */
  1140. /* HE-data1 */
  1141. ppdu_info->rx_status.he_data1 |=
  1142. QDF_MON_STATUS_HE_MCS_KNOWN |
  1143. QDF_MON_STATUS_HE_DCM_KNOWN |
  1144. QDF_MON_STATUS_HE_CODING_KNOWN;
  1145. /* HE-data2 */
  1146. ppdu_info->rx_status.he_data2 |=
  1147. QDF_MON_STATUS_TXBF_KNOWN;
  1148. /* HE-data3 */
  1149. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1150. HE_SIG_B2_OFDMA_INFO, STA_MCS);
  1151. ppdu_info->rx_status.mcs = value;
  1152. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1153. ppdu_info->rx_status.he_data3 |= value;
  1154. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1155. HE_SIG_B2_OFDMA_INFO, STA_DCM);
  1156. he_dcm = value;
  1157. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1158. ppdu_info->rx_status.he_data3 |= value;
  1159. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1160. HE_SIG_B2_OFDMA_INFO, STA_CODING);
  1161. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1162. ppdu_info->rx_status.he_data3 |= value;
  1163. /* HE-data4 */
  1164. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1165. HE_SIG_B2_OFDMA_INFO, STA_ID);
  1166. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1167. ppdu_info->rx_status.he_data4 |= value;
  1168. /* HE-data5 */
  1169. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1170. HE_SIG_B2_OFDMA_INFO, TXBF);
  1171. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1172. ppdu_info->rx_status.he_data5 |= value;
  1173. /* HE-data6 */
  1174. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1175. HE_SIG_B2_OFDMA_INFO, NSTS);
  1176. /* value n indicates n+1 spatial streams */
  1177. value++;
  1178. ppdu_info->rx_status.nss = value;
  1179. ppdu_info->rx_status.he_data6 |= value;
  1180. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1181. break;
  1182. }
  1183. case WIFIPHYRX_RSSI_LEGACY_E:
  1184. {
  1185. uint8_t reception_type;
  1186. int8_t rssi_value;
  1187. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1188. HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
  1189. RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
  1190. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1191. PHYRX_RSSI_LEGACY, RSSI_COMB);
  1192. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  1193. ppdu_info->rx_status.he_re = 0;
  1194. reception_type = HAL_RX_GET(rx_tlv,
  1195. PHYRX_RSSI_LEGACY,
  1196. RECEPTION_TYPE);
  1197. switch (reception_type) {
  1198. case QDF_RECEPTION_TYPE_ULOFMDA:
  1199. ppdu_info->rx_status.reception_type =
  1200. HAL_RX_TYPE_MU_OFDMA;
  1201. ppdu_info->rx_status.ulofdma_flag = 1;
  1202. ppdu_info->rx_status.he_data1 =
  1203. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  1204. break;
  1205. case QDF_RECEPTION_TYPE_ULMIMO:
  1206. ppdu_info->rx_status.reception_type =
  1207. HAL_RX_TYPE_MU_MIMO;
  1208. ppdu_info->rx_status.he_data1 =
  1209. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1210. break;
  1211. default:
  1212. ppdu_info->rx_status.reception_type =
  1213. HAL_RX_TYPE_SU;
  1214. break;
  1215. }
  1216. hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
  1217. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1218. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN0);
  1219. ppdu_info->rx_status.rssi[0] = rssi_value;
  1220. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1221. "RSSI_PRI20_CHAIN0: %d\n", rssi_value);
  1222. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1223. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN1);
  1224. ppdu_info->rx_status.rssi[1] = rssi_value;
  1225. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1226. "RSSI_PRI20_CHAIN1: %d\n", rssi_value);
  1227. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1228. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN2);
  1229. ppdu_info->rx_status.rssi[2] = rssi_value;
  1230. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1231. "RSSI_PRI20_CHAIN2: %d\n", rssi_value);
  1232. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1233. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN3);
  1234. ppdu_info->rx_status.rssi[3] = rssi_value;
  1235. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1236. "RSSI_PRI20_CHAIN3: %d\n", rssi_value);
  1237. #ifdef DP_BE_NOTYET_WAR
  1238. // TODO - this is not preset for wcn7850
  1239. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1240. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN4);
  1241. ppdu_info->rx_status.rssi[4] = rssi_value;
  1242. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1243. "RSSI_PRI20_CHAIN4: %d\n", rssi_value);
  1244. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1245. RECEIVE_RSSI_INFO,
  1246. RSSI_PRI20_CHAIN5);
  1247. ppdu_info->rx_status.rssi[5] = rssi_value;
  1248. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1249. "RSSI_PRI20_CHAIN5: %d\n", rssi_value);
  1250. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1251. RECEIVE_RSSI_INFO,
  1252. RSSI_PRI20_CHAIN6);
  1253. ppdu_info->rx_status.rssi[6] = rssi_value;
  1254. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1255. "RSSI_PRI20_CHAIN6: %d\n", rssi_value);
  1256. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1257. RECEIVE_RSSI_INFO,
  1258. RSSI_PRI20_CHAIN7);
  1259. ppdu_info->rx_status.rssi[7] = rssi_value;
  1260. #endif
  1261. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1262. "RSSI_PRI20_CHAIN7: %d\n", rssi_value);
  1263. break;
  1264. }
  1265. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1266. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  1267. ppdu_info);
  1268. break;
  1269. case WIFIRX_HEADER_E:
  1270. {
  1271. struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
  1272. if (ppdu_info->fcs_ok_cnt >=
  1273. HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
  1274. hal_err("Number of MPDUs(%d) per status buff exceeded",
  1275. ppdu_info->fcs_ok_cnt);
  1276. break;
  1277. }
  1278. /* Update first_msdu_payload for every mpdu and increment
  1279. * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
  1280. */
  1281. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
  1282. rx_tlv;
  1283. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
  1284. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1285. ppdu_info->msdu_info.payload_len = tlv_len;
  1286. ppdu_info->user_id = user_id;
  1287. ppdu_info->hdr_len = tlv_len;
  1288. ppdu_info->data = rx_tlv;
  1289. ppdu_info->data += 4;
  1290. /* for every RX_HEADER TLV increment mpdu_cnt */
  1291. com_info->mpdu_cnt++;
  1292. return HAL_TLV_STATUS_HEADER;
  1293. }
  1294. case WIFIRX_MPDU_START_E:
  1295. {
  1296. uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
  1297. uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_tlv);
  1298. uint8_t filter_category = 0;
  1299. ppdu_info->nac_info.fc_valid =
  1300. HAL_RX_GET_FC_VALID(rx_tlv);
  1301. ppdu_info->nac_info.to_ds_flag =
  1302. HAL_RX_GET_TO_DS_FLAG(rx_tlv);
  1303. ppdu_info->nac_info.frame_control =
  1304. HAL_RX_GET(rx_mpdu_start,
  1305. RX_MPDU_INFO,
  1306. MPDU_FRAME_CONTROL_FIELD);
  1307. ppdu_info->sw_frame_group_id =
  1308. HAL_RX_GET_SW_FRAME_GROUP_ID(rx_tlv);
  1309. if (ppdu_info->sw_frame_group_id ==
  1310. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  1311. ppdu_info->rx_status.frame_control_info_valid =
  1312. ppdu_info->nac_info.fc_valid;
  1313. ppdu_info->rx_status.frame_control =
  1314. ppdu_info->nac_info.frame_control;
  1315. }
  1316. hal_get_mac_addr1(rx_mpdu_start,
  1317. ppdu_info);
  1318. ppdu_info->nac_info.mac_addr2_valid =
  1319. HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_tlv);
  1320. *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
  1321. HAL_RX_GET(rx_mpdu_start,
  1322. RX_MPDU_INFO,
  1323. MAC_ADDR_AD2_15_0);
  1324. *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
  1325. HAL_RX_GET(rx_mpdu_start,
  1326. RX_MPDU_INFO,
  1327. MAC_ADDR_AD2_47_16);
  1328. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1329. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1330. ppdu_info->rx_status.ppdu_len =
  1331. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO,
  1332. MPDU_LENGTH);
  1333. } else {
  1334. ppdu_info->rx_status.ppdu_len +=
  1335. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO,
  1336. MPDU_LENGTH);
  1337. }
  1338. filter_category =
  1339. HAL_RX_GET_FILTER_CATEGORY(rx_tlv);
  1340. if (filter_category == 0)
  1341. ppdu_info->rx_status.rxpcu_filter_pass = 1;
  1342. else if (filter_category == 1)
  1343. ppdu_info->rx_status.monitor_direct_used = 1;
  1344. ppdu_info->nac_info.mcast_bcast =
  1345. HAL_RX_GET(rx_mpdu_start,
  1346. RX_MPDU_INFO,
  1347. MCAST_BCAST);
  1348. break;
  1349. }
  1350. case WIFIRX_MPDU_END_E:
  1351. ppdu_info->user_id = user_id;
  1352. ppdu_info->fcs_err =
  1353. HAL_RX_GET(rx_tlv, RX_MPDU_END,
  1354. FCS_ERR);
  1355. return HAL_TLV_STATUS_MPDU_END;
  1356. case WIFIRX_MSDU_END_E:
  1357. if (user_id < HAL_MAX_UL_MU_USERS) {
  1358. ppdu_info->rx_msdu_info[user_id].cce_metadata =
  1359. HAL_RX_TLV_CCE_METADATA_GET(rx_tlv);
  1360. ppdu_info->rx_msdu_info[user_id].fse_metadata =
  1361. HAL_RX_TLV_FSE_METADATA_GET(rx_tlv);
  1362. ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
  1363. HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(rx_tlv);
  1364. ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
  1365. HAL_RX_TLV_FLOW_IDX_INVALID_GET(rx_tlv);
  1366. ppdu_info->rx_msdu_info[user_id].flow_idx =
  1367. HAL_RX_TLV_FLOW_IDX_GET(rx_tlv);
  1368. }
  1369. return HAL_TLV_STATUS_MSDU_END;
  1370. case 0:
  1371. return HAL_TLV_STATUS_PPDU_DONE;
  1372. default:
  1373. if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
  1374. unhandled = false;
  1375. else
  1376. unhandled = true;
  1377. break;
  1378. }
  1379. if (!unhandled)
  1380. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1381. "%s TLV type: %d, TLV len:%d %s",
  1382. __func__, tlv_tag, tlv_len,
  1383. unhandled == true ? "unhandled" : "");
  1384. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1385. rx_tlv, tlv_len);
  1386. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1387. }
  1388. /**
  1389. * hal_tx_comp_get_release_reason_generic_be() - TQM Release reason
  1390. * @hal_desc: completion ring descriptor pointer
  1391. *
  1392. * This function will return the type of pointer - buffer or descriptor
  1393. *
  1394. * Return: buffer type
  1395. */
  1396. static inline uint8_t hal_tx_comp_get_release_reason_generic_be(void *hal_desc)
  1397. {
  1398. uint32_t comp_desc =
  1399. *(uint32_t *)(((uint8_t *)hal_desc) +
  1400. WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET);
  1401. return (comp_desc & WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK) >>
  1402. WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB;
  1403. }
  1404. /**
  1405. * hal_get_wbm_internal_error_generic_be() - is WBM internal error
  1406. * @hal_desc: completion ring descriptor pointer
  1407. *
  1408. * This function will return 0 or 1 - is it WBM internal error or not
  1409. *
  1410. * Return: uint8_t
  1411. */
  1412. static inline uint8_t hal_get_wbm_internal_error_generic_be(void *hal_desc)
  1413. {
  1414. //TODO - This func is called by tx comp and wbm error handler
  1415. //Check if one needs to use WBM2SW-TX and other WBM2SW-RX
  1416. uint32_t comp_desc =
  1417. *(uint32_t *)(((uint8_t *)hal_desc) +
  1418. HAL_WBM_INTERNAL_ERROR_OFFSET);
  1419. return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >>
  1420. HAL_WBM_INTERNAL_ERROR_LSB;
  1421. }
  1422. /**
  1423. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  1424. * @soc: HAL SoC context
  1425. * @map: PCP-TID mapping table
  1426. *
  1427. * PCP are mapped to 8 TID values using TID values programmed
  1428. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  1429. * The mapping register has TID mapping for 8 PCP values
  1430. *
  1431. * Return: none
  1432. */
  1433. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  1434. {
  1435. uint32_t addr, value;
  1436. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1437. MAC_TCL_REG_REG_BASE);
  1438. value = (map[0] |
  1439. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  1440. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  1441. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  1442. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  1443. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  1444. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  1445. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  1446. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1447. }
  1448. /**
  1449. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  1450. * value received from user-space
  1451. * @soc: HAL SoC context
  1452. * @pcp: pcp value
  1453. * @tid : tid value
  1454. *
  1455. * Return: void
  1456. */
  1457. static void
  1458. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  1459. uint8_t pcp, uint8_t tid)
  1460. {
  1461. uint32_t addr, value, regval;
  1462. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1463. MAC_TCL_REG_REG_BASE);
  1464. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  1465. /* Read back previous PCP TID config and update
  1466. * with new config.
  1467. */
  1468. regval = HAL_REG_READ(soc, addr);
  1469. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  1470. regval |= value;
  1471. HAL_REG_WRITE(soc, addr,
  1472. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1473. }
  1474. /**
  1475. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  1476. * @soc: HAL SoC context
  1477. * @val: priority value
  1478. *
  1479. * Return: void
  1480. */
  1481. static
  1482. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  1483. {
  1484. uint32_t addr;
  1485. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  1486. MAC_TCL_REG_REG_BASE);
  1487. HAL_REG_WRITE(soc, addr,
  1488. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  1489. }
  1490. /**
  1491. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  1492. * @rx_pkt_tlv_size: TLV size for regular RX packets
  1493. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  1494. *
  1495. * Return: size of rx pkt tlv before the actual data
  1496. */
  1497. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  1498. uint16_t *rx_mon_pkt_tlv_size)
  1499. {
  1500. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  1501. /* For now mon pkt tlv is same as rx pkt tlv */
  1502. *rx_mon_pkt_tlv_size = RX_PKT_TLVS_LEN;
  1503. }
  1504. #endif /* _HAL_BE_GENERIC_API_H_ */