dp_tx.c 172 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. #define DP_RETRY_COUNT 7
  63. #ifdef WLAN_PEER_JITTER
  64. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  65. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  66. #endif
  67. #ifdef QCA_DP_TX_FW_METADATA_V2
  68. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  69. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  80. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  82. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  84. #else
  85. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  86. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  97. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  98. HTT_TCL_METADATA_TYPE_PEER_BASED
  99. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  100. HTT_TCL_METADATA_TYPE_VDEV_BASED
  101. #endif
  102. #define DP_GET_HW_LINK_ID_FRM_PPDU_ID(PPDU_ID, LINK_ID_OFFSET, LINK_ID_BITS) \
  103. (((PPDU_ID) >> (LINK_ID_OFFSET)) & ((1 << (LINK_ID_BITS)) - 1))
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc: core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc: core txrx main context
  249. * @seg_desc: tso segment descriptor
  250. * @num_seg_desc: tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc: soc device handle
  283. * @tx_desc: Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. void
  327. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  328. {
  329. struct dp_pdev *pdev = tx_desc->pdev;
  330. struct dp_soc *soc;
  331. uint8_t comp_status = 0;
  332. qdf_assert(pdev);
  333. soc = pdev->soc;
  334. dp_tx_outstanding_dec(pdev);
  335. if (tx_desc->msdu_ext_desc) {
  336. if (tx_desc->frm_type == dp_tx_frm_tso)
  337. dp_tx_tso_desc_release(soc, tx_desc);
  338. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  339. dp_tx_me_free_buf(tx_desc->pdev,
  340. tx_desc->msdu_ext_desc->me_buffer);
  341. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  342. }
  343. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  344. qdf_atomic_dec(&soc->num_tx_exception);
  345. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  346. tx_desc->buffer_src)
  347. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  348. soc->hal_soc);
  349. else
  350. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  351. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  352. tx_desc->id, comp_status,
  353. qdf_atomic_read(&pdev->num_tx_outstanding));
  354. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  355. return;
  356. }
  357. /**
  358. * dp_tx_prepare_htt_metadata() - Prepare HTT metadata for special frames
  359. * @vdev: DP vdev Handle
  360. * @nbuf: skb
  361. * @msdu_info: msdu_info required to create HTT metadata
  362. *
  363. * Prepares and fills HTT metadata in the frame pre-header for special frames
  364. * that should be transmitted using varying transmit parameters.
  365. * There are 2 VDEV modes that currently needs this special metadata -
  366. * 1) Mesh Mode
  367. * 2) DSRC Mode
  368. *
  369. * Return: HTT metadata size
  370. *
  371. */
  372. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  373. struct dp_tx_msdu_info_s *msdu_info)
  374. {
  375. uint32_t *meta_data = msdu_info->meta_data;
  376. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  377. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  378. uint8_t htt_desc_size;
  379. /* Size rounded of multiple of 8 bytes */
  380. uint8_t htt_desc_size_aligned;
  381. uint8_t *hdr = NULL;
  382. /*
  383. * Metadata - HTT MSDU Extension header
  384. */
  385. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  386. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  387. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  388. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  389. meta_data[0]) ||
  390. msdu_info->exception_fw) {
  391. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  392. htt_desc_size_aligned)) {
  393. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  394. htt_desc_size_aligned);
  395. if (!nbuf) {
  396. /*
  397. * qdf_nbuf_realloc_headroom won't do skb_clone
  398. * as skb_realloc_headroom does. so, no free is
  399. * needed here.
  400. */
  401. DP_STATS_INC(vdev,
  402. tx_i.dropped.headroom_insufficient,
  403. 1);
  404. qdf_print(" %s[%d] skb_realloc_headroom failed",
  405. __func__, __LINE__);
  406. return 0;
  407. }
  408. }
  409. /* Fill and add HTT metaheader */
  410. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  411. if (!hdr) {
  412. dp_tx_err("Error in filling HTT metadata");
  413. return 0;
  414. }
  415. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  416. } else if (vdev->opmode == wlan_op_mode_ocb) {
  417. /* Todo - Add support for DSRC */
  418. }
  419. return htt_desc_size_aligned;
  420. }
  421. /**
  422. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  423. * @tso_seg: TSO segment to process
  424. * @ext_desc: Pointer to MSDU extension descriptor
  425. *
  426. * Return: void
  427. */
  428. #if defined(FEATURE_TSO)
  429. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  430. void *ext_desc)
  431. {
  432. uint8_t num_frag;
  433. uint32_t tso_flags;
  434. /*
  435. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  436. * tcp_flag_mask
  437. *
  438. * Checksum enable flags are set in TCL descriptor and not in Extension
  439. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  440. */
  441. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  442. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  443. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  444. tso_seg->tso_flags.ip_len);
  445. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  446. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  447. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  448. uint32_t lo = 0;
  449. uint32_t hi = 0;
  450. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  451. (tso_seg->tso_frags[num_frag].length));
  452. qdf_dmaaddr_to_32s(
  453. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  454. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  455. tso_seg->tso_frags[num_frag].length);
  456. }
  457. return;
  458. }
  459. #else
  460. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  461. void *ext_desc)
  462. {
  463. return;
  464. }
  465. #endif
  466. #if defined(FEATURE_TSO)
  467. /**
  468. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  469. * allocated and free them
  470. * @soc: soc handle
  471. * @free_seg: list of tso segments
  472. * @msdu_info: msdu descriptor
  473. *
  474. * Return: void
  475. */
  476. static void dp_tx_free_tso_seg_list(
  477. struct dp_soc *soc,
  478. struct qdf_tso_seg_elem_t *free_seg,
  479. struct dp_tx_msdu_info_s *msdu_info)
  480. {
  481. struct qdf_tso_seg_elem_t *next_seg;
  482. while (free_seg) {
  483. next_seg = free_seg->next;
  484. dp_tx_tso_desc_free(soc,
  485. msdu_info->tx_queue.desc_pool_id,
  486. free_seg);
  487. free_seg = next_seg;
  488. }
  489. }
  490. /**
  491. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  492. * allocated and free them
  493. * @soc: soc handle
  494. * @free_num_seg: list of tso number segments
  495. * @msdu_info: msdu descriptor
  496. *
  497. * Return: void
  498. */
  499. static void dp_tx_free_tso_num_seg_list(
  500. struct dp_soc *soc,
  501. struct qdf_tso_num_seg_elem_t *free_num_seg,
  502. struct dp_tx_msdu_info_s *msdu_info)
  503. {
  504. struct qdf_tso_num_seg_elem_t *next_num_seg;
  505. while (free_num_seg) {
  506. next_num_seg = free_num_seg->next;
  507. dp_tso_num_seg_free(soc,
  508. msdu_info->tx_queue.desc_pool_id,
  509. free_num_seg);
  510. free_num_seg = next_num_seg;
  511. }
  512. }
  513. /**
  514. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  515. * do dma unmap for each segment
  516. * @soc: soc handle
  517. * @free_seg: list of tso segments
  518. * @num_seg_desc: tso number segment descriptor
  519. *
  520. * Return: void
  521. */
  522. static void dp_tx_unmap_tso_seg_list(
  523. struct dp_soc *soc,
  524. struct qdf_tso_seg_elem_t *free_seg,
  525. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  526. {
  527. struct qdf_tso_seg_elem_t *next_seg;
  528. if (qdf_unlikely(!num_seg_desc)) {
  529. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  530. return;
  531. }
  532. while (free_seg) {
  533. next_seg = free_seg->next;
  534. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  535. free_seg = next_seg;
  536. }
  537. }
  538. #ifdef FEATURE_TSO_STATS
  539. /**
  540. * dp_tso_get_stats_idx() - Retrieve the tso packet id
  541. * @pdev: pdev handle
  542. *
  543. * Return: id
  544. */
  545. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  546. {
  547. uint32_t stats_idx;
  548. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  549. % CDP_MAX_TSO_PACKETS);
  550. return stats_idx;
  551. }
  552. #else
  553. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  554. {
  555. return 0;
  556. }
  557. #endif /* FEATURE_TSO_STATS */
  558. /**
  559. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  560. * free the tso segments descriptor and
  561. * tso num segments descriptor
  562. * @soc: soc handle
  563. * @msdu_info: msdu descriptor
  564. * @tso_seg_unmap: flag to show if dma unmap is necessary
  565. *
  566. * Return: void
  567. */
  568. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  569. struct dp_tx_msdu_info_s *msdu_info,
  570. bool tso_seg_unmap)
  571. {
  572. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  573. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  574. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  575. tso_info->tso_num_seg_list;
  576. /* do dma unmap for each segment */
  577. if (tso_seg_unmap)
  578. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  579. /* free all tso number segment descriptor though looks only have 1 */
  580. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  581. /* free all tso segment descriptor */
  582. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  583. }
  584. /**
  585. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  586. * @vdev: virtual device handle
  587. * @msdu: network buffer
  588. * @msdu_info: meta data associated with the msdu
  589. *
  590. * Return: QDF_STATUS_SUCCESS success
  591. */
  592. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  593. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  594. {
  595. struct qdf_tso_seg_elem_t *tso_seg;
  596. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  597. struct dp_soc *soc = vdev->pdev->soc;
  598. struct dp_pdev *pdev = vdev->pdev;
  599. struct qdf_tso_info_t *tso_info;
  600. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  601. tso_info = &msdu_info->u.tso_info;
  602. tso_info->curr_seg = NULL;
  603. tso_info->tso_seg_list = NULL;
  604. tso_info->num_segs = num_seg;
  605. msdu_info->frm_type = dp_tx_frm_tso;
  606. tso_info->tso_num_seg_list = NULL;
  607. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  608. while (num_seg) {
  609. tso_seg = dp_tx_tso_desc_alloc(
  610. soc, msdu_info->tx_queue.desc_pool_id);
  611. if (tso_seg) {
  612. tso_seg->next = tso_info->tso_seg_list;
  613. tso_info->tso_seg_list = tso_seg;
  614. num_seg--;
  615. } else {
  616. dp_err_rl("Failed to alloc tso seg desc");
  617. DP_STATS_INC_PKT(vdev->pdev,
  618. tso_stats.tso_no_mem_dropped, 1,
  619. qdf_nbuf_len(msdu));
  620. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  621. return QDF_STATUS_E_NOMEM;
  622. }
  623. }
  624. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  625. tso_num_seg = dp_tso_num_seg_alloc(soc,
  626. msdu_info->tx_queue.desc_pool_id);
  627. if (tso_num_seg) {
  628. tso_num_seg->next = tso_info->tso_num_seg_list;
  629. tso_info->tso_num_seg_list = tso_num_seg;
  630. } else {
  631. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  632. __func__);
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. msdu_info->num_seg =
  637. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  638. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  639. msdu_info->num_seg);
  640. if (!(msdu_info->num_seg)) {
  641. /*
  642. * Free allocated TSO seg desc and number seg desc,
  643. * do unmap for segments if dma map has done.
  644. */
  645. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  647. return QDF_STATUS_E_INVAL;
  648. }
  649. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  650. msdu, 0, DP_TX_DESC_MAP);
  651. tso_info->curr_seg = tso_info->tso_seg_list;
  652. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  653. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  654. msdu, msdu_info->num_seg);
  655. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  656. tso_info->msdu_stats_idx);
  657. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  658. return QDF_STATUS_SUCCESS;
  659. }
  660. #else
  661. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  662. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  663. {
  664. return QDF_STATUS_E_NOMEM;
  665. }
  666. #endif
  667. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  668. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  669. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  670. /**
  671. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  672. * @vdev: DP Vdev handle
  673. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  674. * @desc_pool_id: Descriptor Pool ID
  675. *
  676. * Return:
  677. */
  678. static
  679. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  680. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  681. {
  682. uint8_t i;
  683. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  684. struct dp_tx_seg_info_s *seg_info;
  685. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  686. struct dp_soc *soc = vdev->pdev->soc;
  687. /* Allocate an extension descriptor */
  688. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  689. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  690. if (!msdu_ext_desc) {
  691. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  692. return NULL;
  693. }
  694. if (msdu_info->exception_fw &&
  695. qdf_unlikely(vdev->mesh_vdev)) {
  696. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  697. &msdu_info->meta_data[0],
  698. sizeof(struct htt_tx_msdu_desc_ext2_t));
  699. qdf_atomic_inc(&soc->num_tx_exception);
  700. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  701. }
  702. switch (msdu_info->frm_type) {
  703. case dp_tx_frm_sg:
  704. case dp_tx_frm_me:
  705. case dp_tx_frm_raw:
  706. seg_info = msdu_info->u.sg_info.curr_seg;
  707. /* Update the buffer pointers in MSDU Extension Descriptor */
  708. for (i = 0; i < seg_info->frag_cnt; i++) {
  709. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  710. seg_info->frags[i].paddr_lo,
  711. seg_info->frags[i].paddr_hi,
  712. seg_info->frags[i].len);
  713. }
  714. break;
  715. case dp_tx_frm_tso:
  716. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  717. &cached_ext_desc[0]);
  718. break;
  719. default:
  720. break;
  721. }
  722. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  723. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  724. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  725. msdu_ext_desc->vaddr);
  726. return msdu_ext_desc;
  727. }
  728. /**
  729. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  730. * @soc: datapath SOC
  731. * @skb: skb to be traced
  732. * @msdu_id: msdu_id of the packet
  733. * @vdev_id: vdev_id of the packet
  734. *
  735. * Return: None
  736. */
  737. #ifdef DP_DISABLE_TX_PKT_TRACE
  738. static void dp_tx_trace_pkt(struct dp_soc *soc,
  739. qdf_nbuf_t skb, uint16_t msdu_id,
  740. uint8_t vdev_id)
  741. {
  742. }
  743. #else
  744. static void dp_tx_trace_pkt(struct dp_soc *soc,
  745. qdf_nbuf_t skb, uint16_t msdu_id,
  746. uint8_t vdev_id)
  747. {
  748. if (dp_is_tput_high(soc))
  749. return;
  750. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  751. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  752. DPTRACE(qdf_dp_trace_ptr(skb,
  753. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  754. QDF_TRACE_DEFAULT_PDEV_ID,
  755. qdf_nbuf_data_addr(skb),
  756. sizeof(qdf_nbuf_data(skb)),
  757. msdu_id, vdev_id, 0));
  758. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  759. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  760. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  761. msdu_id, QDF_TX));
  762. }
  763. #endif
  764. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  765. /**
  766. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  767. * exception by the upper layer (OS_IF)
  768. * @soc: DP soc handle
  769. * @nbuf: packet to be transmitted
  770. *
  771. * Return: 1 if the packet is marked as exception,
  772. * 0, if the packet is not marked as exception.
  773. */
  774. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  775. qdf_nbuf_t nbuf)
  776. {
  777. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  778. }
  779. #else
  780. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  781. qdf_nbuf_t nbuf)
  782. {
  783. return 0;
  784. }
  785. #endif
  786. #ifdef DP_TRAFFIC_END_INDICATION
  787. /**
  788. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  789. * as indication to fw to inform that
  790. * data stream has ended
  791. * @vdev: DP vdev handle
  792. * @nbuf: original buffer from network stack
  793. *
  794. * Return: NULL on failure,
  795. * nbuf on success
  796. */
  797. static inline qdf_nbuf_t
  798. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  799. qdf_nbuf_t nbuf)
  800. {
  801. /* Packet length should be enough to copy upto L3 header */
  802. uint8_t end_nbuf_len = 64;
  803. uint8_t htt_desc_size_aligned;
  804. uint8_t htt_desc_size;
  805. qdf_nbuf_t end_nbuf;
  806. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  807. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  808. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  809. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  810. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  811. if (!end_nbuf) {
  812. end_nbuf = qdf_nbuf_alloc(NULL,
  813. (htt_desc_size_aligned +
  814. end_nbuf_len),
  815. htt_desc_size_aligned,
  816. 8, false);
  817. if (!end_nbuf) {
  818. dp_err("Packet allocation failed");
  819. goto out;
  820. }
  821. } else {
  822. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  823. }
  824. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  825. end_nbuf_len);
  826. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  827. return end_nbuf;
  828. }
  829. out:
  830. return NULL;
  831. }
  832. /**
  833. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  834. * via exception path.
  835. * @vdev: DP vdev handle
  836. * @end_nbuf: skb to send as indication
  837. * @msdu_info: msdu_info of original nbuf
  838. * @peer_id: peer id
  839. *
  840. * Return: None
  841. */
  842. static inline void
  843. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  844. qdf_nbuf_t end_nbuf,
  845. struct dp_tx_msdu_info_s *msdu_info,
  846. uint16_t peer_id)
  847. {
  848. struct dp_tx_msdu_info_s e_msdu_info = {0};
  849. qdf_nbuf_t nbuf;
  850. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  851. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  852. e_msdu_info.tx_queue = msdu_info->tx_queue;
  853. e_msdu_info.tid = msdu_info->tid;
  854. e_msdu_info.exception_fw = 1;
  855. desc_ext->host_tx_desc_pool = 1;
  856. desc_ext->traffic_end_indication = 1;
  857. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  858. peer_id, NULL);
  859. if (nbuf) {
  860. dp_err("Traffic end indication packet tx failed");
  861. qdf_nbuf_free(nbuf);
  862. }
  863. }
  864. /**
  865. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  866. * mark it traffic end indication
  867. * packet.
  868. * @tx_desc: Tx descriptor pointer
  869. * @msdu_info: msdu_info structure pointer
  870. *
  871. * Return: None
  872. */
  873. static inline void
  874. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  875. struct dp_tx_msdu_info_s *msdu_info)
  876. {
  877. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  878. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  879. if (qdf_unlikely(desc_ext->traffic_end_indication))
  880. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  881. }
  882. /**
  883. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  884. * freeing which are associated
  885. * with traffic end indication
  886. * flagged descriptor.
  887. * @soc: dp soc handle
  888. * @desc: Tx descriptor pointer
  889. * @nbuf: buffer pointer
  890. *
  891. * Return: True if packet gets enqueued else false
  892. */
  893. static bool
  894. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  895. struct dp_tx_desc_s *desc,
  896. qdf_nbuf_t nbuf)
  897. {
  898. struct dp_vdev *vdev = NULL;
  899. if (qdf_unlikely((desc->flags &
  900. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  901. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  902. DP_MOD_ID_TX_COMP);
  903. if (vdev) {
  904. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  905. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  906. return true;
  907. }
  908. }
  909. return false;
  910. }
  911. /**
  912. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  913. * enable/disable status
  914. * @vdev: dp vdev handle
  915. *
  916. * Return: True if feature is enable else false
  917. */
  918. static inline bool
  919. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  920. {
  921. return qdf_unlikely(vdev->traffic_end_ind_en);
  922. }
  923. static inline qdf_nbuf_t
  924. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  925. struct dp_tx_msdu_info_s *msdu_info,
  926. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  927. {
  928. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  929. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  930. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  931. if (qdf_unlikely(end_nbuf))
  932. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  933. msdu_info, peer_id);
  934. return nbuf;
  935. }
  936. #else
  937. static inline qdf_nbuf_t
  938. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  939. qdf_nbuf_t nbuf)
  940. {
  941. return NULL;
  942. }
  943. static inline void
  944. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  945. qdf_nbuf_t end_nbuf,
  946. struct dp_tx_msdu_info_s *msdu_info,
  947. uint16_t peer_id)
  948. {}
  949. static inline void
  950. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  951. struct dp_tx_msdu_info_s *msdu_info)
  952. {}
  953. static inline bool
  954. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  955. struct dp_tx_desc_s *desc,
  956. qdf_nbuf_t nbuf)
  957. {
  958. return false;
  959. }
  960. static inline bool
  961. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  962. {
  963. return false;
  964. }
  965. static inline qdf_nbuf_t
  966. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  967. struct dp_tx_msdu_info_s *msdu_info,
  968. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  969. {
  970. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  971. }
  972. #endif
  973. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  974. static bool
  975. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  976. struct cdp_tx_exception_metadata *tx_exc_metadata)
  977. {
  978. if (soc->features.wds_ext_ast_override_enable &&
  979. tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  980. return true;
  981. return false;
  982. }
  983. #else
  984. static bool
  985. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  986. struct cdp_tx_exception_metadata *tx_exc_metadata)
  987. {
  988. return false;
  989. }
  990. #endif
  991. /**
  992. * dp_tx_prepare_desc_single() - Allocate and prepare Tx descriptor
  993. * @vdev: DP vdev handle
  994. * @nbuf: skb
  995. * @desc_pool_id: Descriptor pool ID
  996. * @msdu_info: Metadata to the fw
  997. * @tx_exc_metadata: Handle that holds exception path metadata
  998. *
  999. * Allocate and prepare Tx descriptor with msdu information.
  1000. *
  1001. * Return: Pointer to Tx Descriptor on success,
  1002. * NULL on failure
  1003. */
  1004. static
  1005. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1006. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1007. struct dp_tx_msdu_info_s *msdu_info,
  1008. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1009. {
  1010. uint8_t align_pad;
  1011. uint8_t is_exception = 0;
  1012. uint8_t htt_hdr_size;
  1013. struct dp_tx_desc_s *tx_desc;
  1014. struct dp_pdev *pdev = vdev->pdev;
  1015. struct dp_soc *soc = pdev->soc;
  1016. if (dp_tx_limit_check(vdev, nbuf))
  1017. return NULL;
  1018. /* Allocate software Tx descriptor */
  1019. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1020. if (qdf_unlikely(!tx_desc)) {
  1021. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1022. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1023. return NULL;
  1024. }
  1025. dp_tx_outstanding_inc(pdev);
  1026. /* Initialize the SW tx descriptor */
  1027. tx_desc->nbuf = nbuf;
  1028. tx_desc->frm_type = dp_tx_frm_std;
  1029. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1030. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1031. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1032. tx_desc->vdev_id = vdev->vdev_id;
  1033. tx_desc->pdev = pdev;
  1034. tx_desc->msdu_ext_desc = NULL;
  1035. tx_desc->pkt_offset = 0;
  1036. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1037. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1038. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1039. if (qdf_unlikely(vdev->multipass_en)) {
  1040. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1041. goto failure;
  1042. }
  1043. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1044. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1045. is_exception = 1;
  1046. /* for BE chipsets if wds extension was enbled will not mark FW
  1047. * in desc will mark ast index based search for ast index.
  1048. */
  1049. if (dp_tx_is_wds_ast_override_en(soc, tx_exc_metadata))
  1050. return tx_desc;
  1051. /*
  1052. * For special modes (vdev_type == ocb or mesh), data frames should be
  1053. * transmitted using varying transmit parameters (tx spec) which include
  1054. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1055. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1056. * These frames are sent as exception packets to firmware.
  1057. *
  1058. * HW requirement is that metadata should always point to a
  1059. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1060. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1061. * to get 8-byte aligned start address along with align_pad added
  1062. *
  1063. * |-----------------------------|
  1064. * | |
  1065. * |-----------------------------| <-----Buffer Pointer Address given
  1066. * | | ^ in HW descriptor (aligned)
  1067. * | HTT Metadata | |
  1068. * | | |
  1069. * | | | Packet Offset given in descriptor
  1070. * | | |
  1071. * |-----------------------------| |
  1072. * | Alignment Pad | v
  1073. * |-----------------------------| <----- Actual buffer start address
  1074. * | SKB Data | (Unaligned)
  1075. * | |
  1076. * | |
  1077. * | |
  1078. * | |
  1079. * | |
  1080. * |-----------------------------|
  1081. */
  1082. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1083. (vdev->opmode == wlan_op_mode_ocb) ||
  1084. (tx_exc_metadata &&
  1085. tx_exc_metadata->is_tx_sniffer)) {
  1086. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1087. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1088. DP_STATS_INC(vdev,
  1089. tx_i.dropped.headroom_insufficient, 1);
  1090. goto failure;
  1091. }
  1092. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1093. dp_tx_err("qdf_nbuf_push_head failed");
  1094. goto failure;
  1095. }
  1096. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1097. msdu_info);
  1098. if (htt_hdr_size == 0)
  1099. goto failure;
  1100. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1101. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1102. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1103. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1104. msdu_info);
  1105. is_exception = 1;
  1106. tx_desc->length -= tx_desc->pkt_offset;
  1107. }
  1108. #if !TQM_BYPASS_WAR
  1109. if (is_exception || tx_exc_metadata)
  1110. #endif
  1111. {
  1112. /* Temporary WAR due to TQM VP issues */
  1113. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1114. qdf_atomic_inc(&soc->num_tx_exception);
  1115. }
  1116. return tx_desc;
  1117. failure:
  1118. dp_tx_desc_release(tx_desc, desc_pool_id);
  1119. return NULL;
  1120. }
  1121. /**
  1122. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment
  1123. * frame
  1124. * @vdev: DP vdev handle
  1125. * @nbuf: skb
  1126. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1127. * @desc_pool_id : Descriptor Pool ID
  1128. *
  1129. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1130. * information. For frames with fragments, allocate and prepare
  1131. * an MSDU extension descriptor
  1132. *
  1133. * Return: Pointer to Tx Descriptor on success,
  1134. * NULL on failure
  1135. */
  1136. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1137. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1138. uint8_t desc_pool_id)
  1139. {
  1140. struct dp_tx_desc_s *tx_desc;
  1141. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1142. struct dp_pdev *pdev = vdev->pdev;
  1143. struct dp_soc *soc = pdev->soc;
  1144. if (dp_tx_limit_check(vdev, nbuf))
  1145. return NULL;
  1146. /* Allocate software Tx descriptor */
  1147. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1148. if (!tx_desc) {
  1149. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1150. return NULL;
  1151. }
  1152. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1153. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1154. dp_tx_outstanding_inc(pdev);
  1155. /* Initialize the SW tx descriptor */
  1156. tx_desc->nbuf = nbuf;
  1157. tx_desc->frm_type = msdu_info->frm_type;
  1158. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1159. tx_desc->vdev_id = vdev->vdev_id;
  1160. tx_desc->pdev = pdev;
  1161. tx_desc->pkt_offset = 0;
  1162. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1163. /* Handle scattered frames - TSO/SG/ME */
  1164. /* Allocate and prepare an extension descriptor for scattered frames */
  1165. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1166. if (!msdu_ext_desc) {
  1167. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1168. goto failure;
  1169. }
  1170. #if TQM_BYPASS_WAR
  1171. /* Temporary WAR due to TQM VP issues */
  1172. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1173. qdf_atomic_inc(&soc->num_tx_exception);
  1174. #endif
  1175. if (qdf_unlikely(msdu_info->exception_fw))
  1176. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1177. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1178. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1179. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1180. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1181. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1182. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1183. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1184. else
  1185. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1186. return tx_desc;
  1187. failure:
  1188. dp_tx_desc_release(tx_desc, desc_pool_id);
  1189. return NULL;
  1190. }
  1191. /**
  1192. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1193. * @vdev: DP vdev handle
  1194. * @nbuf: buffer pointer
  1195. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1196. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1197. * descriptor
  1198. *
  1199. * Return:
  1200. */
  1201. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1202. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1203. {
  1204. qdf_nbuf_t curr_nbuf = NULL;
  1205. uint16_t total_len = 0;
  1206. qdf_dma_addr_t paddr;
  1207. int32_t i;
  1208. int32_t mapped_buf_num = 0;
  1209. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1210. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1211. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1212. /* Continue only if frames are of DATA type */
  1213. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1214. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1215. dp_tx_debug("Pkt. recd is of not data type");
  1216. goto error;
  1217. }
  1218. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1219. if (vdev->raw_mode_war &&
  1220. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1221. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1222. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1223. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1224. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1225. /*
  1226. * Number of nbuf's must not exceed the size of the frags
  1227. * array in seg_info.
  1228. */
  1229. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1230. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1231. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1232. goto error;
  1233. }
  1234. if (QDF_STATUS_SUCCESS !=
  1235. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1236. curr_nbuf,
  1237. QDF_DMA_TO_DEVICE,
  1238. curr_nbuf->len)) {
  1239. dp_tx_err("%s dma map error ", __func__);
  1240. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1241. goto error;
  1242. }
  1243. /* Update the count of mapped nbuf's */
  1244. mapped_buf_num++;
  1245. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1246. seg_info->frags[i].paddr_lo = paddr;
  1247. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1248. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1249. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1250. total_len += qdf_nbuf_len(curr_nbuf);
  1251. }
  1252. seg_info->frag_cnt = i;
  1253. seg_info->total_len = total_len;
  1254. seg_info->next = NULL;
  1255. sg_info->curr_seg = seg_info;
  1256. msdu_info->frm_type = dp_tx_frm_raw;
  1257. msdu_info->num_seg = 1;
  1258. return nbuf;
  1259. error:
  1260. i = 0;
  1261. while (nbuf) {
  1262. curr_nbuf = nbuf;
  1263. if (i < mapped_buf_num) {
  1264. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1265. QDF_DMA_TO_DEVICE,
  1266. curr_nbuf->len);
  1267. i++;
  1268. }
  1269. nbuf = qdf_nbuf_next(nbuf);
  1270. qdf_nbuf_free(curr_nbuf);
  1271. }
  1272. return NULL;
  1273. }
  1274. /**
  1275. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1276. * @soc: DP soc handle
  1277. * @nbuf: Buffer pointer
  1278. *
  1279. * unmap the chain of nbufs that belong to this RAW frame.
  1280. *
  1281. * Return: None
  1282. */
  1283. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1284. qdf_nbuf_t nbuf)
  1285. {
  1286. qdf_nbuf_t cur_nbuf = nbuf;
  1287. do {
  1288. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1289. QDF_DMA_TO_DEVICE,
  1290. cur_nbuf->len);
  1291. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1292. } while (cur_nbuf);
  1293. }
  1294. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1295. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1296. qdf_nbuf_t nbuf)
  1297. {
  1298. qdf_nbuf_t nbuf_local;
  1299. struct dp_vdev *vdev_local = vdev_hdl;
  1300. do {
  1301. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1302. break;
  1303. nbuf_local = nbuf;
  1304. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1305. htt_cmn_pkt_type_raw))
  1306. break;
  1307. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1308. break;
  1309. else if (qdf_nbuf_is_tso((nbuf_local)))
  1310. break;
  1311. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1312. (nbuf_local),
  1313. NULL, 1, 0);
  1314. } while (0);
  1315. }
  1316. #endif
  1317. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1318. void dp_tx_update_stats(struct dp_soc *soc,
  1319. struct dp_tx_desc_s *tx_desc,
  1320. uint8_t ring_id)
  1321. {
  1322. uint32_t stats_len = dp_tx_get_pkt_len(tx_desc);
  1323. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1324. }
  1325. int
  1326. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1327. struct dp_tx_desc_s *tx_desc,
  1328. uint8_t tid,
  1329. struct dp_tx_msdu_info_s *msdu_info,
  1330. uint8_t ring_id)
  1331. {
  1332. struct dp_swlm *swlm = &soc->swlm;
  1333. union swlm_data swlm_query_data;
  1334. struct dp_swlm_tcl_data tcl_data;
  1335. QDF_STATUS status;
  1336. int ret;
  1337. if (!swlm->is_enabled)
  1338. return msdu_info->skip_hp_update;
  1339. tcl_data.nbuf = tx_desc->nbuf;
  1340. tcl_data.tid = tid;
  1341. tcl_data.ring_id = ring_id;
  1342. tcl_data.pkt_len = dp_tx_get_pkt_len(tx_desc);
  1343. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1344. swlm_query_data.tcl_data = &tcl_data;
  1345. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1346. if (QDF_IS_STATUS_ERROR(status)) {
  1347. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1348. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1349. return 0;
  1350. }
  1351. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1352. if (ret) {
  1353. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1354. } else {
  1355. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1356. }
  1357. return ret;
  1358. }
  1359. void
  1360. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1361. int coalesce)
  1362. {
  1363. if (coalesce)
  1364. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1365. else
  1366. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1367. }
  1368. static inline void
  1369. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1370. {
  1371. if (((i + 1) < msdu_info->num_seg))
  1372. msdu_info->skip_hp_update = 1;
  1373. else
  1374. msdu_info->skip_hp_update = 0;
  1375. }
  1376. static inline void
  1377. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1378. {
  1379. hal_ring_handle_t hal_ring_hdl =
  1380. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1381. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1382. dp_err("Fillmore: SRNG access start failed");
  1383. return;
  1384. }
  1385. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1386. }
  1387. static inline void
  1388. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1389. QDF_STATUS status,
  1390. struct dp_tx_msdu_info_s *msdu_info)
  1391. {
  1392. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1393. dp_flush_tcp_hp(soc,
  1394. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1395. }
  1396. }
  1397. #else
  1398. static inline void
  1399. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1400. {
  1401. }
  1402. static inline void
  1403. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1404. QDF_STATUS status,
  1405. struct dp_tx_msdu_info_s *msdu_info)
  1406. {
  1407. }
  1408. #endif
  1409. #ifdef FEATURE_RUNTIME_PM
  1410. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1411. {
  1412. int ret;
  1413. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1414. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1415. return ret;
  1416. }
  1417. void
  1418. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1419. hal_ring_handle_t hal_ring_hdl,
  1420. int coalesce)
  1421. {
  1422. int ret;
  1423. /*
  1424. * Avoid runtime get and put APIs under high throughput scenarios.
  1425. */
  1426. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1427. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1428. return;
  1429. }
  1430. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1431. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1432. if (hif_system_pm_state_check(soc->hif_handle)) {
  1433. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1434. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1435. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1436. } else {
  1437. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1438. }
  1439. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1440. } else {
  1441. dp_runtime_get(soc);
  1442. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1443. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1444. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1445. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1446. dp_runtime_put(soc);
  1447. }
  1448. }
  1449. #else
  1450. #ifdef DP_POWER_SAVE
  1451. void
  1452. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1453. hal_ring_handle_t hal_ring_hdl,
  1454. int coalesce)
  1455. {
  1456. if (hif_system_pm_state_check(soc->hif_handle)) {
  1457. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1458. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1459. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1460. } else {
  1461. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1462. }
  1463. }
  1464. #endif
  1465. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1466. {
  1467. return 0;
  1468. }
  1469. #endif
  1470. /**
  1471. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1472. * @vdev: DP vdev handle
  1473. * @nbuf: skb
  1474. * @msdu_info: msdu descriptor
  1475. *
  1476. * Extract the DSCP or PCP information from frame and map into TID value.
  1477. *
  1478. * Return: void
  1479. */
  1480. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1481. struct dp_tx_msdu_info_s *msdu_info)
  1482. {
  1483. uint8_t tos = 0, dscp_tid_override = 0;
  1484. uint8_t *hdr_ptr, *L3datap;
  1485. uint8_t is_mcast = 0;
  1486. qdf_ether_header_t *eh = NULL;
  1487. qdf_ethervlan_header_t *evh = NULL;
  1488. uint16_t ether_type;
  1489. qdf_llc_t *llcHdr;
  1490. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1491. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1492. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1493. eh = (qdf_ether_header_t *)nbuf->data;
  1494. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1495. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1496. } else {
  1497. qdf_dot3_qosframe_t *qos_wh =
  1498. (qdf_dot3_qosframe_t *) nbuf->data;
  1499. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1500. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1501. return;
  1502. }
  1503. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1504. ether_type = eh->ether_type;
  1505. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1506. /*
  1507. * Check if packet is dot3 or eth2 type.
  1508. */
  1509. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1510. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1511. sizeof(*llcHdr));
  1512. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1513. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1514. sizeof(*llcHdr);
  1515. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1516. + sizeof(*llcHdr) +
  1517. sizeof(qdf_net_vlanhdr_t));
  1518. } else {
  1519. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1520. sizeof(*llcHdr);
  1521. }
  1522. } else {
  1523. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1524. evh = (qdf_ethervlan_header_t *) eh;
  1525. ether_type = evh->ether_type;
  1526. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1527. }
  1528. }
  1529. /*
  1530. * Find priority from IP TOS DSCP field
  1531. */
  1532. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1533. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1534. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1535. /* Only for unicast frames */
  1536. if (!is_mcast) {
  1537. /* send it on VO queue */
  1538. msdu_info->tid = DP_VO_TID;
  1539. }
  1540. } else {
  1541. /*
  1542. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1543. * from TOS byte.
  1544. */
  1545. tos = ip->ip_tos;
  1546. dscp_tid_override = 1;
  1547. }
  1548. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1549. /* TODO
  1550. * use flowlabel
  1551. *igmpmld cases to be handled in phase 2
  1552. */
  1553. unsigned long ver_pri_flowlabel;
  1554. unsigned long pri;
  1555. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1556. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1557. DP_IPV6_PRIORITY_SHIFT;
  1558. tos = pri;
  1559. dscp_tid_override = 1;
  1560. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1561. msdu_info->tid = DP_VO_TID;
  1562. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1563. /* Only for unicast frames */
  1564. if (!is_mcast) {
  1565. /* send ucast arp on VO queue */
  1566. msdu_info->tid = DP_VO_TID;
  1567. }
  1568. }
  1569. /*
  1570. * Assign all MCAST packets to BE
  1571. */
  1572. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1573. if (is_mcast) {
  1574. tos = 0;
  1575. dscp_tid_override = 1;
  1576. }
  1577. }
  1578. if (dscp_tid_override == 1) {
  1579. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1580. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1581. }
  1582. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1583. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1584. return;
  1585. }
  1586. /**
  1587. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1588. * @vdev: DP vdev handle
  1589. * @nbuf: skb
  1590. * @msdu_info: msdu descriptor
  1591. *
  1592. * Software based TID classification is required when more than 2 DSCP-TID
  1593. * mapping tables are needed.
  1594. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1595. *
  1596. * Return: void
  1597. */
  1598. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1599. struct dp_tx_msdu_info_s *msdu_info)
  1600. {
  1601. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1602. /*
  1603. * skip_sw_tid_classification flag will set in below cases-
  1604. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1605. * 2. hlos_tid_override enabled for vdev
  1606. * 3. mesh mode enabled for vdev
  1607. */
  1608. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1609. /* Update tid in msdu_info from skb priority */
  1610. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1611. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1612. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1613. if (tid == DP_TX_INVALID_QOS_TAG)
  1614. return;
  1615. msdu_info->tid = tid;
  1616. return;
  1617. }
  1618. return;
  1619. }
  1620. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1621. }
  1622. #ifdef FEATURE_WLAN_TDLS
  1623. /**
  1624. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1625. * @soc: datapath SOC
  1626. * @vdev: datapath vdev
  1627. * @tx_desc: TX descriptor
  1628. *
  1629. * Return: None
  1630. */
  1631. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1632. struct dp_vdev *vdev,
  1633. struct dp_tx_desc_s *tx_desc)
  1634. {
  1635. if (vdev) {
  1636. if (vdev->is_tdls_frame) {
  1637. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1638. vdev->is_tdls_frame = false;
  1639. }
  1640. }
  1641. }
  1642. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1643. {
  1644. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1645. switch (soc->arch_id) {
  1646. case CDP_ARCH_TYPE_LI:
  1647. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1648. break;
  1649. case CDP_ARCH_TYPE_BE:
  1650. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1651. break;
  1652. default:
  1653. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1654. QDF_BUG(0);
  1655. }
  1656. return tx_status;
  1657. }
  1658. /**
  1659. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1660. * @soc: dp_soc handle
  1661. * @tx_desc: TX descriptor
  1662. *
  1663. * Return: None
  1664. */
  1665. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1666. struct dp_tx_desc_s *tx_desc)
  1667. {
  1668. uint8_t tx_status = 0;
  1669. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1670. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1671. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1672. DP_MOD_ID_TDLS);
  1673. if (qdf_unlikely(!vdev)) {
  1674. dp_err_rl("vdev is null!");
  1675. goto error;
  1676. }
  1677. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1678. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1679. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1680. if (vdev->tx_non_std_data_callback.func) {
  1681. qdf_nbuf_set_next(nbuf, NULL);
  1682. vdev->tx_non_std_data_callback.func(
  1683. vdev->tx_non_std_data_callback.ctxt,
  1684. nbuf, tx_status);
  1685. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1686. return;
  1687. } else {
  1688. dp_err_rl("callback func is null");
  1689. }
  1690. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1691. error:
  1692. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1693. qdf_nbuf_free(nbuf);
  1694. }
  1695. /**
  1696. * dp_tx_msdu_single_map() - do nbuf map
  1697. * @vdev: DP vdev handle
  1698. * @tx_desc: DP TX descriptor pointer
  1699. * @nbuf: skb pointer
  1700. *
  1701. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1702. * operation done in other component.
  1703. *
  1704. * Return: QDF_STATUS
  1705. */
  1706. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1707. struct dp_tx_desc_s *tx_desc,
  1708. qdf_nbuf_t nbuf)
  1709. {
  1710. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1711. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1712. nbuf,
  1713. QDF_DMA_TO_DEVICE,
  1714. nbuf->len);
  1715. else
  1716. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1717. QDF_DMA_TO_DEVICE);
  1718. }
  1719. #else
  1720. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1721. struct dp_vdev *vdev,
  1722. struct dp_tx_desc_s *tx_desc)
  1723. {
  1724. }
  1725. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1726. struct dp_tx_desc_s *tx_desc)
  1727. {
  1728. }
  1729. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1730. struct dp_tx_desc_s *tx_desc,
  1731. qdf_nbuf_t nbuf)
  1732. {
  1733. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1734. nbuf,
  1735. QDF_DMA_TO_DEVICE,
  1736. nbuf->len);
  1737. }
  1738. #endif
  1739. static inline
  1740. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1741. struct dp_tx_desc_s *tx_desc,
  1742. qdf_nbuf_t nbuf)
  1743. {
  1744. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1745. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1746. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1747. return 0;
  1748. return qdf_nbuf_mapped_paddr_get(nbuf);
  1749. }
  1750. static inline
  1751. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1752. {
  1753. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1754. desc->nbuf,
  1755. desc->dma_addr,
  1756. QDF_DMA_TO_DEVICE,
  1757. desc->length);
  1758. }
  1759. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1760. static inline bool
  1761. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1762. {
  1763. struct net_device *ingress_dev;
  1764. skb_frag_t *frag;
  1765. uint16_t buf_len = 0;
  1766. uint16_t linear_data_len = 0;
  1767. uint8_t *payload_addr = NULL;
  1768. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1769. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1770. dev_put(ingress_dev);
  1771. frag = &(skb_shinfo(nbuf)->frags[0]);
  1772. buf_len = skb_frag_size(frag);
  1773. payload_addr = (uint8_t *)skb_frag_address(frag);
  1774. linear_data_len = skb_headlen(nbuf);
  1775. buf_len += linear_data_len;
  1776. payload_addr = payload_addr - linear_data_len;
  1777. memcpy(payload_addr, nbuf->data, linear_data_len);
  1778. msdu_info->frm_type = dp_tx_frm_rmnet;
  1779. msdu_info->buf_len = buf_len;
  1780. msdu_info->payload_addr = payload_addr;
  1781. return true;
  1782. }
  1783. dev_put(ingress_dev);
  1784. return false;
  1785. }
  1786. static inline
  1787. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1788. struct dp_tx_desc_s *tx_desc)
  1789. {
  1790. qdf_dma_addr_t paddr;
  1791. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1792. tx_desc->length = msdu_info->buf_len;
  1793. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1794. (void *)(msdu_info->payload_addr +
  1795. msdu_info->buf_len));
  1796. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1797. return paddr;
  1798. }
  1799. #else
  1800. static inline bool
  1801. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1802. {
  1803. return false;
  1804. }
  1805. static inline
  1806. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1807. struct dp_tx_desc_s *tx_desc)
  1808. {
  1809. return 0;
  1810. }
  1811. #endif
  1812. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1813. static inline
  1814. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1815. struct dp_tx_desc_s *tx_desc,
  1816. qdf_nbuf_t nbuf)
  1817. {
  1818. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1819. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1820. (void *)(nbuf->data + nbuf->len));
  1821. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1822. } else {
  1823. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1824. }
  1825. }
  1826. static inline
  1827. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1828. struct dp_tx_desc_s *desc)
  1829. {
  1830. if (qdf_unlikely(!(desc->flags &
  1831. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1832. return dp_tx_nbuf_unmap_regular(soc, desc);
  1833. }
  1834. #else
  1835. static inline
  1836. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1837. struct dp_tx_desc_s *tx_desc,
  1838. qdf_nbuf_t nbuf)
  1839. {
  1840. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1841. }
  1842. static inline
  1843. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1844. struct dp_tx_desc_s *desc)
  1845. {
  1846. return dp_tx_nbuf_unmap_regular(soc, desc);
  1847. }
  1848. #endif
  1849. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1850. static inline
  1851. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1852. {
  1853. dp_tx_nbuf_unmap(soc, desc);
  1854. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1855. }
  1856. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1857. {
  1858. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1859. dp_tx_nbuf_unmap(soc, desc);
  1860. }
  1861. #else
  1862. static inline
  1863. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1864. {
  1865. }
  1866. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1867. {
  1868. dp_tx_nbuf_unmap(soc, desc);
  1869. }
  1870. #endif
  1871. #ifdef MESH_MODE_SUPPORT
  1872. /**
  1873. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1874. * @soc: datapath SOC
  1875. * @vdev: datapath vdev
  1876. * @tx_desc: TX descriptor
  1877. *
  1878. * Return: None
  1879. */
  1880. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1881. struct dp_vdev *vdev,
  1882. struct dp_tx_desc_s *tx_desc)
  1883. {
  1884. if (qdf_unlikely(vdev->mesh_vdev))
  1885. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1886. }
  1887. /**
  1888. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1889. * @soc: dp_soc handle
  1890. * @tx_desc: TX descriptor
  1891. * @delayed_free: delay the nbuf free
  1892. *
  1893. * Return: nbuf to be freed late
  1894. */
  1895. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1896. struct dp_tx_desc_s *tx_desc,
  1897. bool delayed_free)
  1898. {
  1899. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1900. struct dp_vdev *vdev = NULL;
  1901. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1902. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1903. if (vdev)
  1904. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1905. if (delayed_free)
  1906. return nbuf;
  1907. qdf_nbuf_free(nbuf);
  1908. } else {
  1909. if (vdev && vdev->osif_tx_free_ext) {
  1910. vdev->osif_tx_free_ext((nbuf));
  1911. } else {
  1912. if (delayed_free)
  1913. return nbuf;
  1914. qdf_nbuf_free(nbuf);
  1915. }
  1916. }
  1917. if (vdev)
  1918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1919. return NULL;
  1920. }
  1921. #else
  1922. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1923. struct dp_vdev *vdev,
  1924. struct dp_tx_desc_s *tx_desc)
  1925. {
  1926. }
  1927. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1928. struct dp_tx_desc_s *tx_desc,
  1929. bool delayed_free)
  1930. {
  1931. return NULL;
  1932. }
  1933. #endif
  1934. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1935. {
  1936. struct dp_pdev *pdev = NULL;
  1937. struct dp_ast_entry *src_ast_entry = NULL;
  1938. struct dp_ast_entry *dst_ast_entry = NULL;
  1939. struct dp_soc *soc = NULL;
  1940. qdf_assert(vdev);
  1941. pdev = vdev->pdev;
  1942. qdf_assert(pdev);
  1943. soc = pdev->soc;
  1944. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1945. (soc, dstmac, vdev->pdev->pdev_id);
  1946. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1947. (soc, srcmac, vdev->pdev->pdev_id);
  1948. if (dst_ast_entry && src_ast_entry) {
  1949. if (dst_ast_entry->peer_id ==
  1950. src_ast_entry->peer_id)
  1951. return 1;
  1952. }
  1953. return 0;
  1954. }
  1955. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1956. defined(WLAN_MCAST_MLO)
  1957. /* MLO peer id for reinject*/
  1958. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1959. /* MLO vdev id inc offset */
  1960. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1961. #ifdef QCA_SUPPORT_WDS_EXTENDED
  1962. static inline bool
  1963. dp_tx_wds_ext_check(struct cdp_tx_exception_metadata *tx_exc_metadata)
  1964. {
  1965. if (tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  1966. return true;
  1967. return false;
  1968. }
  1969. #else
  1970. static inline bool
  1971. dp_tx_wds_ext_check(struct cdp_tx_exception_metadata *tx_exc_metadata)
  1972. {
  1973. return false;
  1974. }
  1975. #endif
  1976. static inline void
  1977. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  1978. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1979. {
  1980. /* wds ext enabled will not set the TO_FW bit */
  1981. if (dp_tx_wds_ext_check(tx_exc_metadata))
  1982. return;
  1983. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1984. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1985. qdf_atomic_inc(&soc->num_tx_exception);
  1986. }
  1987. }
  1988. static inline void
  1989. dp_tx_update_mcast_param(uint16_t peer_id,
  1990. uint16_t *htt_tcl_metadata,
  1991. struct dp_vdev *vdev,
  1992. struct dp_tx_msdu_info_s *msdu_info)
  1993. {
  1994. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1995. *htt_tcl_metadata = 0;
  1996. DP_TX_TCL_METADATA_TYPE_SET(
  1997. *htt_tcl_metadata,
  1998. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1999. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2000. msdu_info->gsn);
  2001. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2002. if (qdf_unlikely(vdev->nawds_enabled ||
  2003. dp_vdev_is_wds_ext_enabled(vdev)))
  2004. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2005. *htt_tcl_metadata, 1);
  2006. } else {
  2007. msdu_info->vdev_id = vdev->vdev_id;
  2008. }
  2009. }
  2010. #else
  2011. static inline void
  2012. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  2013. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2014. {
  2015. }
  2016. static inline void
  2017. dp_tx_update_mcast_param(uint16_t peer_id,
  2018. uint16_t *htt_tcl_metadata,
  2019. struct dp_vdev *vdev,
  2020. struct dp_tx_msdu_info_s *msdu_info)
  2021. {
  2022. }
  2023. #endif
  2024. #ifdef DP_TX_SW_DROP_STATS_INC
  2025. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2026. qdf_nbuf_t nbuf,
  2027. enum cdp_tx_sw_drop drop_code)
  2028. {
  2029. /* EAPOL Drop stats */
  2030. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2031. switch (drop_code) {
  2032. case TX_DESC_ERR:
  2033. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2034. break;
  2035. case TX_HAL_RING_ACCESS_ERR:
  2036. DP_STATS_INC(pdev,
  2037. eap_drop_stats.tx_hal_ring_access_err, 1);
  2038. break;
  2039. case TX_DMA_MAP_ERR:
  2040. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2041. break;
  2042. case TX_HW_ENQUEUE:
  2043. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2044. break;
  2045. case TX_SW_ENQUEUE:
  2046. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2047. break;
  2048. default:
  2049. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2050. break;
  2051. }
  2052. }
  2053. }
  2054. #else
  2055. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2056. qdf_nbuf_t nbuf,
  2057. enum cdp_tx_sw_drop drop_code)
  2058. {
  2059. }
  2060. #endif
  2061. qdf_nbuf_t
  2062. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2063. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2064. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2065. {
  2066. struct dp_pdev *pdev = vdev->pdev;
  2067. struct dp_soc *soc = pdev->soc;
  2068. struct dp_tx_desc_s *tx_desc;
  2069. QDF_STATUS status;
  2070. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2071. uint16_t htt_tcl_metadata = 0;
  2072. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2073. uint8_t tid = msdu_info->tid;
  2074. struct cdp_tid_tx_stats *tid_stats = NULL;
  2075. qdf_dma_addr_t paddr;
  2076. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2077. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2078. msdu_info, tx_exc_metadata);
  2079. if (!tx_desc) {
  2080. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2081. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2082. drop_code = TX_DESC_ERR;
  2083. goto fail_return;
  2084. }
  2085. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2086. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2087. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2088. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2089. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2090. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2091. DP_TCL_METADATA_TYPE_PEER_BASED);
  2092. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2093. peer_id);
  2094. dp_tx_bypass_reinjection(soc, tx_desc, tx_exc_metadata);
  2095. } else
  2096. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2097. if (msdu_info->exception_fw)
  2098. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2099. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2100. !pdev->enhanced_stats_en);
  2101. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2102. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2103. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2104. else
  2105. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2106. if (!paddr) {
  2107. /* Handle failure */
  2108. dp_err("qdf_nbuf_map failed");
  2109. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2110. drop_code = TX_DMA_MAP_ERR;
  2111. goto release_desc;
  2112. }
  2113. tx_desc->dma_addr = paddr;
  2114. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2115. tx_desc->id, DP_TX_DESC_MAP);
  2116. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2117. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2118. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2119. htt_tcl_metadata,
  2120. tx_exc_metadata, msdu_info);
  2121. if (status != QDF_STATUS_SUCCESS) {
  2122. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2123. tx_desc, tx_q->ring_id);
  2124. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2125. tx_desc->id, DP_TX_DESC_UNMAP);
  2126. dp_tx_nbuf_unmap(soc, tx_desc);
  2127. drop_code = TX_HW_ENQUEUE;
  2128. goto release_desc;
  2129. }
  2130. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2131. return NULL;
  2132. release_desc:
  2133. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2134. fail_return:
  2135. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2136. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2137. tid_stats = &pdev->stats.tid_stats.
  2138. tid_tx_stats[tx_q->ring_id][tid];
  2139. tid_stats->swdrop_cnt[drop_code]++;
  2140. return nbuf;
  2141. }
  2142. /**
  2143. * dp_tdls_tx_comp_free_buff() - Free non std buffer when TDLS flag is set
  2144. * @soc: Soc handle
  2145. * @desc: software Tx descriptor to be processed
  2146. *
  2147. * Return: 0 if Success
  2148. */
  2149. #ifdef FEATURE_WLAN_TDLS
  2150. static inline int
  2151. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2152. {
  2153. /* If it is TDLS mgmt, don't unmap or free the frame */
  2154. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2155. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2156. return 0;
  2157. }
  2158. return 1;
  2159. }
  2160. #else
  2161. static inline int
  2162. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2163. {
  2164. return 1;
  2165. }
  2166. #endif
  2167. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2168. bool delayed_free)
  2169. {
  2170. qdf_nbuf_t nbuf = desc->nbuf;
  2171. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2172. /* nbuf already freed in vdev detach path */
  2173. if (!nbuf)
  2174. return NULL;
  2175. if (!dp_tdls_tx_comp_free_buff(soc, desc))
  2176. return NULL;
  2177. /* 0 : MSDU buffer, 1 : MLE */
  2178. if (desc->msdu_ext_desc) {
  2179. /* TSO free */
  2180. if (hal_tx_ext_desc_get_tso_enable(
  2181. desc->msdu_ext_desc->vaddr)) {
  2182. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2183. desc->id, DP_TX_COMP_MSDU_EXT);
  2184. dp_tx_tso_seg_history_add(soc,
  2185. desc->msdu_ext_desc->tso_desc,
  2186. desc->nbuf, desc->id, type);
  2187. /* unmap eash TSO seg before free the nbuf */
  2188. dp_tx_tso_unmap_segment(soc,
  2189. desc->msdu_ext_desc->tso_desc,
  2190. desc->msdu_ext_desc->
  2191. tso_num_desc);
  2192. goto nbuf_free;
  2193. }
  2194. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2195. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2196. qdf_dma_addr_t iova;
  2197. uint32_t frag_len;
  2198. uint32_t i;
  2199. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2200. QDF_DMA_TO_DEVICE,
  2201. qdf_nbuf_headlen(nbuf));
  2202. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2203. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2204. &iova,
  2205. &frag_len);
  2206. if (!iova || !frag_len)
  2207. break;
  2208. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2209. QDF_DMA_TO_DEVICE);
  2210. }
  2211. goto nbuf_free;
  2212. }
  2213. }
  2214. /* If it's ME frame, dont unmap the cloned nbuf's */
  2215. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2216. goto nbuf_free;
  2217. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2218. dp_tx_unmap(soc, desc);
  2219. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2220. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2221. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2222. return NULL;
  2223. nbuf_free:
  2224. if (delayed_free)
  2225. return nbuf;
  2226. qdf_nbuf_free(nbuf);
  2227. return NULL;
  2228. }
  2229. /**
  2230. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2231. * @soc: DP soc handle
  2232. * @nbuf: skb
  2233. * @msdu_info: MSDU info
  2234. *
  2235. * Return: None
  2236. */
  2237. static inline void
  2238. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2239. struct dp_tx_msdu_info_s *msdu_info)
  2240. {
  2241. uint32_t cur_idx;
  2242. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2243. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2244. qdf_nbuf_headlen(nbuf));
  2245. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2246. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2247. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2248. seg->frags[cur_idx].paddr_hi) << 32),
  2249. seg->frags[cur_idx].len,
  2250. QDF_DMA_TO_DEVICE);
  2251. }
  2252. #if QDF_LOCK_STATS
  2253. noinline
  2254. #else
  2255. #endif
  2256. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2257. struct dp_tx_msdu_info_s *msdu_info)
  2258. {
  2259. uint32_t i;
  2260. struct dp_pdev *pdev = vdev->pdev;
  2261. struct dp_soc *soc = pdev->soc;
  2262. struct dp_tx_desc_s *tx_desc;
  2263. bool is_cce_classified = false;
  2264. QDF_STATUS status;
  2265. uint16_t htt_tcl_metadata = 0;
  2266. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2267. struct cdp_tid_tx_stats *tid_stats = NULL;
  2268. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2269. if (msdu_info->frm_type == dp_tx_frm_me)
  2270. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2271. i = 0;
  2272. /* Print statement to track i and num_seg */
  2273. /*
  2274. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2275. * descriptors using information in msdu_info
  2276. */
  2277. while (i < msdu_info->num_seg) {
  2278. /*
  2279. * Setup Tx descriptor for an MSDU, and MSDU extension
  2280. * descriptor
  2281. */
  2282. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2283. tx_q->desc_pool_id);
  2284. if (!tx_desc) {
  2285. if (msdu_info->frm_type == dp_tx_frm_me) {
  2286. prep_desc_fail++;
  2287. dp_tx_me_free_buf(pdev,
  2288. (void *)(msdu_info->u.sg_info
  2289. .curr_seg->frags[0].vaddr));
  2290. if (prep_desc_fail == msdu_info->num_seg) {
  2291. /*
  2292. * Unmap is needed only if descriptor
  2293. * preparation failed for all segments.
  2294. */
  2295. qdf_nbuf_unmap(soc->osdev,
  2296. msdu_info->u.sg_info.
  2297. curr_seg->nbuf,
  2298. QDF_DMA_TO_DEVICE);
  2299. }
  2300. /*
  2301. * Free the nbuf for the current segment
  2302. * and make it point to the next in the list.
  2303. * For me, there are as many segments as there
  2304. * are no of clients.
  2305. */
  2306. qdf_nbuf_free(msdu_info->u.sg_info
  2307. .curr_seg->nbuf);
  2308. if (msdu_info->u.sg_info.curr_seg->next) {
  2309. msdu_info->u.sg_info.curr_seg =
  2310. msdu_info->u.sg_info
  2311. .curr_seg->next;
  2312. nbuf = msdu_info->u.sg_info
  2313. .curr_seg->nbuf;
  2314. }
  2315. i++;
  2316. continue;
  2317. }
  2318. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2319. dp_tx_tso_seg_history_add(
  2320. soc,
  2321. msdu_info->u.tso_info.curr_seg,
  2322. nbuf, 0, DP_TX_DESC_UNMAP);
  2323. dp_tx_tso_unmap_segment(soc,
  2324. msdu_info->u.tso_info.
  2325. curr_seg,
  2326. msdu_info->u.tso_info.
  2327. tso_num_seg_list);
  2328. if (msdu_info->u.tso_info.curr_seg->next) {
  2329. msdu_info->u.tso_info.curr_seg =
  2330. msdu_info->u.tso_info.curr_seg->next;
  2331. i++;
  2332. continue;
  2333. }
  2334. }
  2335. if (msdu_info->frm_type == dp_tx_frm_sg)
  2336. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2337. goto done;
  2338. }
  2339. if (msdu_info->frm_type == dp_tx_frm_me) {
  2340. tx_desc->msdu_ext_desc->me_buffer =
  2341. (struct dp_tx_me_buf_t *)msdu_info->
  2342. u.sg_info.curr_seg->frags[0].vaddr;
  2343. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2344. }
  2345. if (is_cce_classified)
  2346. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2347. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2348. if (msdu_info->exception_fw) {
  2349. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2350. }
  2351. dp_tx_is_hp_update_required(i, msdu_info);
  2352. /*
  2353. * For frames with multiple segments (TSO, ME), jump to next
  2354. * segment.
  2355. */
  2356. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2357. if (msdu_info->u.tso_info.curr_seg->next) {
  2358. msdu_info->u.tso_info.curr_seg =
  2359. msdu_info->u.tso_info.curr_seg->next;
  2360. /*
  2361. * If this is a jumbo nbuf, then increment the
  2362. * number of nbuf users for each additional
  2363. * segment of the msdu. This will ensure that
  2364. * the skb is freed only after receiving tx
  2365. * completion for all segments of an nbuf
  2366. */
  2367. qdf_nbuf_inc_users(nbuf);
  2368. /* Check with MCL if this is needed */
  2369. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2370. */
  2371. }
  2372. }
  2373. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2374. &htt_tcl_metadata,
  2375. vdev,
  2376. msdu_info);
  2377. /*
  2378. * Enqueue the Tx MSDU descriptor to HW for transmit
  2379. */
  2380. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2381. htt_tcl_metadata,
  2382. NULL, msdu_info);
  2383. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2384. if (status != QDF_STATUS_SUCCESS) {
  2385. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2386. tx_desc, tx_q->ring_id);
  2387. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2388. tid_stats = &pdev->stats.tid_stats.
  2389. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2390. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2391. if (msdu_info->frm_type == dp_tx_frm_me) {
  2392. hw_enq_fail++;
  2393. if (hw_enq_fail == msdu_info->num_seg) {
  2394. /*
  2395. * Unmap is needed only if enqueue
  2396. * failed for all segments.
  2397. */
  2398. qdf_nbuf_unmap(soc->osdev,
  2399. msdu_info->u.sg_info.
  2400. curr_seg->nbuf,
  2401. QDF_DMA_TO_DEVICE);
  2402. }
  2403. /*
  2404. * Free the nbuf for the current segment
  2405. * and make it point to the next in the list.
  2406. * For me, there are as many segments as there
  2407. * are no of clients.
  2408. */
  2409. qdf_nbuf_free(msdu_info->u.sg_info
  2410. .curr_seg->nbuf);
  2411. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2412. if (msdu_info->u.sg_info.curr_seg->next) {
  2413. msdu_info->u.sg_info.curr_seg =
  2414. msdu_info->u.sg_info
  2415. .curr_seg->next;
  2416. nbuf = msdu_info->u.sg_info
  2417. .curr_seg->nbuf;
  2418. } else
  2419. break;
  2420. i++;
  2421. continue;
  2422. }
  2423. /*
  2424. * For TSO frames, the nbuf users increment done for
  2425. * the current segment has to be reverted, since the
  2426. * hw enqueue for this segment failed
  2427. */
  2428. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2429. msdu_info->u.tso_info.curr_seg) {
  2430. /*
  2431. * unmap and free current,
  2432. * retransmit remaining segments
  2433. */
  2434. dp_tx_comp_free_buf(soc, tx_desc, false);
  2435. i++;
  2436. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2437. continue;
  2438. }
  2439. if (msdu_info->frm_type == dp_tx_frm_sg)
  2440. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2441. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2442. goto done;
  2443. }
  2444. /*
  2445. * TODO
  2446. * if tso_info structure can be modified to have curr_seg
  2447. * as first element, following 2 blocks of code (for TSO and SG)
  2448. * can be combined into 1
  2449. */
  2450. /*
  2451. * For Multicast-Unicast converted packets,
  2452. * each converted frame (for a client) is represented as
  2453. * 1 segment
  2454. */
  2455. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2456. (msdu_info->frm_type == dp_tx_frm_me)) {
  2457. if (msdu_info->u.sg_info.curr_seg->next) {
  2458. msdu_info->u.sg_info.curr_seg =
  2459. msdu_info->u.sg_info.curr_seg->next;
  2460. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2461. } else
  2462. break;
  2463. }
  2464. i++;
  2465. }
  2466. nbuf = NULL;
  2467. done:
  2468. return nbuf;
  2469. }
  2470. /**
  2471. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2472. * for SG frames
  2473. * @vdev: DP vdev handle
  2474. * @nbuf: skb
  2475. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2476. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2477. *
  2478. * Return: NULL on success,
  2479. * nbuf when it fails to send
  2480. */
  2481. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2482. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2483. {
  2484. uint32_t cur_frag, nr_frags, i;
  2485. qdf_dma_addr_t paddr;
  2486. struct dp_tx_sg_info_s *sg_info;
  2487. sg_info = &msdu_info->u.sg_info;
  2488. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2489. if (QDF_STATUS_SUCCESS !=
  2490. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2491. QDF_DMA_TO_DEVICE,
  2492. qdf_nbuf_headlen(nbuf))) {
  2493. dp_tx_err("dma map error");
  2494. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2495. qdf_nbuf_free(nbuf);
  2496. return NULL;
  2497. }
  2498. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2499. seg_info->frags[0].paddr_lo = paddr;
  2500. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2501. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2502. seg_info->frags[0].vaddr = (void *) nbuf;
  2503. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2504. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2505. nbuf, 0,
  2506. QDF_DMA_TO_DEVICE,
  2507. cur_frag)) {
  2508. dp_tx_err("frag dma map error");
  2509. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2510. goto map_err;
  2511. }
  2512. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2513. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2514. seg_info->frags[cur_frag + 1].paddr_hi =
  2515. ((uint64_t) paddr) >> 32;
  2516. seg_info->frags[cur_frag + 1].len =
  2517. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2518. }
  2519. seg_info->frag_cnt = (cur_frag + 1);
  2520. seg_info->total_len = qdf_nbuf_len(nbuf);
  2521. seg_info->next = NULL;
  2522. sg_info->curr_seg = seg_info;
  2523. msdu_info->frm_type = dp_tx_frm_sg;
  2524. msdu_info->num_seg = 1;
  2525. return nbuf;
  2526. map_err:
  2527. /* restore paddr into nbuf before calling unmap */
  2528. qdf_nbuf_mapped_paddr_set(nbuf,
  2529. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2530. ((uint64_t)
  2531. seg_info->frags[0].paddr_hi) << 32));
  2532. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2533. QDF_DMA_TO_DEVICE,
  2534. seg_info->frags[0].len);
  2535. for (i = 1; i <= cur_frag; i++) {
  2536. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2537. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2538. seg_info->frags[i].paddr_hi) << 32),
  2539. seg_info->frags[i].len,
  2540. QDF_DMA_TO_DEVICE);
  2541. }
  2542. qdf_nbuf_free(nbuf);
  2543. return NULL;
  2544. }
  2545. /**
  2546. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2547. * @vdev: DP vdev handle
  2548. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2549. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2550. *
  2551. * Return: NULL on failure,
  2552. * nbuf when extracted successfully
  2553. */
  2554. static
  2555. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2556. struct dp_tx_msdu_info_s *msdu_info,
  2557. uint16_t ppdu_cookie)
  2558. {
  2559. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2560. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2561. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2562. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2563. (msdu_info->meta_data[5], 1);
  2564. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2565. (msdu_info->meta_data[5], 1);
  2566. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2567. (msdu_info->meta_data[6], ppdu_cookie);
  2568. msdu_info->exception_fw = 1;
  2569. msdu_info->is_tx_sniffer = 1;
  2570. }
  2571. #ifdef MESH_MODE_SUPPORT
  2572. /**
  2573. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2574. * and prepare msdu_info for mesh frames.
  2575. * @vdev: DP vdev handle
  2576. * @nbuf: skb
  2577. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2578. *
  2579. * Return: NULL on failure,
  2580. * nbuf when extracted successfully
  2581. */
  2582. static
  2583. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2584. struct dp_tx_msdu_info_s *msdu_info)
  2585. {
  2586. struct meta_hdr_s *mhdr;
  2587. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2588. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2589. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2590. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2591. msdu_info->exception_fw = 0;
  2592. goto remove_meta_hdr;
  2593. }
  2594. msdu_info->exception_fw = 1;
  2595. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2596. meta_data->host_tx_desc_pool = 1;
  2597. meta_data->update_peer_cache = 1;
  2598. meta_data->learning_frame = 1;
  2599. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2600. meta_data->power = mhdr->power;
  2601. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2602. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2603. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2604. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2605. meta_data->dyn_bw = 1;
  2606. meta_data->valid_pwr = 1;
  2607. meta_data->valid_mcs_mask = 1;
  2608. meta_data->valid_nss_mask = 1;
  2609. meta_data->valid_preamble_type = 1;
  2610. meta_data->valid_retries = 1;
  2611. meta_data->valid_bw_info = 1;
  2612. }
  2613. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2614. meta_data->encrypt_type = 0;
  2615. meta_data->valid_encrypt_type = 1;
  2616. meta_data->learning_frame = 0;
  2617. }
  2618. meta_data->valid_key_flags = 1;
  2619. meta_data->key_flags = (mhdr->keyix & 0x3);
  2620. remove_meta_hdr:
  2621. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2622. dp_tx_err("qdf_nbuf_pull_head failed");
  2623. qdf_nbuf_free(nbuf);
  2624. return NULL;
  2625. }
  2626. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2627. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2628. " tid %d to_fw %d",
  2629. msdu_info->meta_data[0],
  2630. msdu_info->meta_data[1],
  2631. msdu_info->meta_data[2],
  2632. msdu_info->meta_data[3],
  2633. msdu_info->meta_data[4],
  2634. msdu_info->meta_data[5],
  2635. msdu_info->tid, msdu_info->exception_fw);
  2636. return nbuf;
  2637. }
  2638. #else
  2639. static
  2640. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2641. struct dp_tx_msdu_info_s *msdu_info)
  2642. {
  2643. return nbuf;
  2644. }
  2645. #endif
  2646. /**
  2647. * dp_check_exc_metadata() - Checks if parameters are valid
  2648. * @tx_exc: holds all exception path parameters
  2649. *
  2650. * Return: true when all the parameters are valid else false
  2651. *
  2652. */
  2653. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2654. {
  2655. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2656. HTT_INVALID_TID);
  2657. bool invalid_encap_type =
  2658. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2659. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2660. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2661. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2662. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2663. tx_exc->ppdu_cookie == 0);
  2664. if (tx_exc->is_intrabss_fwd)
  2665. return true;
  2666. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2667. invalid_cookie) {
  2668. return false;
  2669. }
  2670. return true;
  2671. }
  2672. #ifdef ATH_SUPPORT_IQUE
  2673. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2674. {
  2675. qdf_ether_header_t *eh;
  2676. /* Mcast to Ucast Conversion*/
  2677. if (qdf_likely(!vdev->mcast_enhancement_en))
  2678. return true;
  2679. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2680. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2681. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2682. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2683. qdf_nbuf_set_next(nbuf, NULL);
  2684. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2685. qdf_nbuf_len(nbuf));
  2686. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2687. QDF_STATUS_SUCCESS) {
  2688. return false;
  2689. }
  2690. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2691. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2692. QDF_STATUS_SUCCESS) {
  2693. return false;
  2694. }
  2695. }
  2696. }
  2697. return true;
  2698. }
  2699. #else
  2700. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2701. {
  2702. return true;
  2703. }
  2704. #endif
  2705. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2706. /**
  2707. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2708. * @vdev: vdev handle
  2709. * @nbuf: skb
  2710. *
  2711. * Return: true if frame is dropped, false otherwise
  2712. */
  2713. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2714. {
  2715. /* Drop tx mcast and WDS Extended feature check */
  2716. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2717. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2718. qdf_nbuf_data(nbuf);
  2719. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2720. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2721. return true;
  2722. }
  2723. }
  2724. return false;
  2725. }
  2726. #else
  2727. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2728. {
  2729. return false;
  2730. }
  2731. #endif
  2732. /**
  2733. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2734. * @nbuf: qdf_nbuf_t
  2735. * @vdev: struct dp_vdev *
  2736. *
  2737. * Allow packet for processing only if it is for peer client which is
  2738. * connected with same vap. Drop packet if client is connected to
  2739. * different vap.
  2740. *
  2741. * Return: QDF_STATUS
  2742. */
  2743. static inline QDF_STATUS
  2744. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2745. {
  2746. struct dp_ast_entry *dst_ast_entry = NULL;
  2747. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2748. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2749. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2750. return QDF_STATUS_SUCCESS;
  2751. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2752. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2753. eh->ether_dhost,
  2754. vdev->vdev_id);
  2755. /* If there is no ast entry, return failure */
  2756. if (qdf_unlikely(!dst_ast_entry)) {
  2757. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2758. return QDF_STATUS_E_FAILURE;
  2759. }
  2760. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2761. return QDF_STATUS_SUCCESS;
  2762. }
  2763. /**
  2764. * dp_tx_nawds_handler() - NAWDS handler
  2765. *
  2766. * @soc: DP soc handle
  2767. * @vdev: DP vdev handle
  2768. * @msdu_info: msdu_info required to create HTT metadata
  2769. * @nbuf: skb
  2770. * @sa_peer_id:
  2771. *
  2772. * This API transfers the multicast frames with the peer id
  2773. * on NAWDS enabled peer.
  2774. *
  2775. * Return: none
  2776. */
  2777. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2778. struct dp_tx_msdu_info_s *msdu_info,
  2779. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2780. {
  2781. struct dp_peer *peer = NULL;
  2782. qdf_nbuf_t nbuf_clone = NULL;
  2783. uint16_t peer_id = DP_INVALID_PEER;
  2784. struct dp_txrx_peer *txrx_peer;
  2785. uint8_t link_id = 0;
  2786. /* This check avoids pkt forwarding which is entered
  2787. * in the ast table but still doesn't have valid peerid.
  2788. */
  2789. if (sa_peer_id == HTT_INVALID_PEER)
  2790. return;
  2791. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2792. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2793. txrx_peer = dp_get_txrx_peer(peer);
  2794. if (!txrx_peer)
  2795. continue;
  2796. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2797. peer_id = peer->peer_id;
  2798. if (!dp_peer_is_primary_link_peer(peer))
  2799. continue;
  2800. /* In the case of wds ext peer mcast traffic will be
  2801. * sent as part of VLAN interface
  2802. */
  2803. if (dp_peer_is_wds_ext_peer(txrx_peer))
  2804. continue;
  2805. /* Multicast packets needs to be
  2806. * dropped in case of intra bss forwarding
  2807. */
  2808. if (sa_peer_id == txrx_peer->peer_id) {
  2809. dp_tx_debug("multicast packet");
  2810. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2811. tx.nawds_mcast_drop,
  2812. 1, link_id);
  2813. continue;
  2814. }
  2815. nbuf_clone = qdf_nbuf_clone(nbuf);
  2816. if (!nbuf_clone) {
  2817. QDF_TRACE(QDF_MODULE_ID_DP,
  2818. QDF_TRACE_LEVEL_ERROR,
  2819. FL("nbuf clone failed"));
  2820. break;
  2821. }
  2822. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2823. msdu_info, peer_id,
  2824. NULL);
  2825. if (nbuf_clone) {
  2826. dp_tx_debug("pkt send failed");
  2827. qdf_nbuf_free(nbuf_clone);
  2828. } else {
  2829. if (peer_id != DP_INVALID_PEER)
  2830. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2831. tx.nawds_mcast,
  2832. 1, qdf_nbuf_len(nbuf), link_id);
  2833. }
  2834. }
  2835. }
  2836. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2837. }
  2838. qdf_nbuf_t
  2839. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2840. qdf_nbuf_t nbuf,
  2841. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2842. {
  2843. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2844. struct dp_tx_msdu_info_s msdu_info;
  2845. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2846. DP_MOD_ID_TX_EXCEPTION);
  2847. if (qdf_unlikely(!vdev))
  2848. goto fail;
  2849. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2850. if (!tx_exc_metadata)
  2851. goto fail;
  2852. msdu_info.tid = tx_exc_metadata->tid;
  2853. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2854. QDF_MAC_ADDR_REF(nbuf->data));
  2855. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2856. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2857. dp_tx_err("Invalid parameters in exception path");
  2858. goto fail;
  2859. }
  2860. /* for peer based metadata check if peer is valid */
  2861. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2862. struct dp_peer *peer = NULL;
  2863. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2864. tx_exc_metadata->peer_id,
  2865. DP_MOD_ID_TX_EXCEPTION);
  2866. if (qdf_unlikely(!peer)) {
  2867. DP_STATS_INC(vdev,
  2868. tx_i.dropped.invalid_peer_id_in_exc_path,
  2869. 1);
  2870. goto fail;
  2871. }
  2872. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2873. }
  2874. /* Basic sanity checks for unsupported packets */
  2875. /* MESH mode */
  2876. if (qdf_unlikely(vdev->mesh_vdev)) {
  2877. dp_tx_err("Mesh mode is not supported in exception path");
  2878. goto fail;
  2879. }
  2880. /*
  2881. * Classify the frame and call corresponding
  2882. * "prepare" function which extracts the segment (TSO)
  2883. * and fragmentation information (for TSO , SG, ME, or Raw)
  2884. * into MSDU_INFO structure which is later used to fill
  2885. * SW and HW descriptors.
  2886. */
  2887. if (qdf_nbuf_is_tso(nbuf)) {
  2888. dp_verbose_debug("TSO frame %pK", vdev);
  2889. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2890. qdf_nbuf_len(nbuf));
  2891. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2892. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2893. qdf_nbuf_len(nbuf));
  2894. goto fail;
  2895. }
  2896. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  2897. goto send_multiple;
  2898. }
  2899. /* SG */
  2900. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2901. struct dp_tx_seg_info_s seg_info = {0};
  2902. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2903. if (!nbuf)
  2904. goto fail;
  2905. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2906. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2907. qdf_nbuf_len(nbuf));
  2908. goto send_multiple;
  2909. }
  2910. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2911. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2912. qdf_nbuf_len(nbuf));
  2913. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2914. tx_exc_metadata->ppdu_cookie);
  2915. }
  2916. /*
  2917. * Get HW Queue to use for this frame.
  2918. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2919. * dedicated for data and 1 for command.
  2920. * "queue_id" maps to one hardware ring.
  2921. * With each ring, we also associate a unique Tx descriptor pool
  2922. * to minimize lock contention for these resources.
  2923. */
  2924. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2925. /*
  2926. * if the packet is mcast packet send through mlo_macst handler
  2927. * for all prnt_vdevs
  2928. */
  2929. if (soc->arch_ops.dp_tx_mlo_mcast_send) {
  2930. nbuf = soc->arch_ops.dp_tx_mlo_mcast_send(soc, vdev,
  2931. nbuf,
  2932. tx_exc_metadata);
  2933. if (!nbuf)
  2934. goto fail;
  2935. }
  2936. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2937. if (qdf_unlikely(vdev->nawds_enabled)) {
  2938. /*
  2939. * This is a multicast packet
  2940. */
  2941. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2942. tx_exc_metadata->peer_id);
  2943. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2944. 1, qdf_nbuf_len(nbuf));
  2945. }
  2946. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2947. DP_INVALID_PEER, NULL);
  2948. } else {
  2949. /*
  2950. * Check exception descriptors
  2951. */
  2952. if (dp_tx_exception_limit_check(vdev))
  2953. goto fail;
  2954. /* Single linear frame */
  2955. /*
  2956. * If nbuf is a simple linear frame, use send_single function to
  2957. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2958. * SRNG. There is no need to setup a MSDU extension descriptor.
  2959. */
  2960. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2961. tx_exc_metadata->peer_id,
  2962. tx_exc_metadata);
  2963. }
  2964. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2965. return nbuf;
  2966. send_multiple:
  2967. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2968. fail:
  2969. if (vdev)
  2970. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2971. dp_verbose_debug("pkt send failed");
  2972. return nbuf;
  2973. }
  2974. qdf_nbuf_t
  2975. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2976. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2977. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2978. {
  2979. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2980. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2981. DP_MOD_ID_TX_EXCEPTION);
  2982. if (qdf_unlikely(!vdev))
  2983. goto fail;
  2984. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2985. == QDF_STATUS_E_FAILURE)) {
  2986. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2987. goto fail;
  2988. }
  2989. /* Unref count as it will again be taken inside dp_tx_exception */
  2990. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2991. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2992. fail:
  2993. if (vdev)
  2994. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2995. dp_verbose_debug("pkt send failed");
  2996. return nbuf;
  2997. }
  2998. #ifdef MESH_MODE_SUPPORT
  2999. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3000. qdf_nbuf_t nbuf)
  3001. {
  3002. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3003. struct meta_hdr_s *mhdr;
  3004. qdf_nbuf_t nbuf_mesh = NULL;
  3005. qdf_nbuf_t nbuf_clone = NULL;
  3006. struct dp_vdev *vdev;
  3007. uint8_t no_enc_frame = 0;
  3008. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3009. if (!nbuf_mesh) {
  3010. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3011. "qdf_nbuf_unshare failed");
  3012. return nbuf;
  3013. }
  3014. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3015. if (!vdev) {
  3016. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3017. "vdev is NULL for vdev_id %d", vdev_id);
  3018. return nbuf;
  3019. }
  3020. nbuf = nbuf_mesh;
  3021. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3022. if ((vdev->sec_type != cdp_sec_type_none) &&
  3023. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3024. no_enc_frame = 1;
  3025. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3026. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3027. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3028. !no_enc_frame) {
  3029. nbuf_clone = qdf_nbuf_clone(nbuf);
  3030. if (!nbuf_clone) {
  3031. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3032. "qdf_nbuf_clone failed");
  3033. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3034. return nbuf;
  3035. }
  3036. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3037. }
  3038. if (nbuf_clone) {
  3039. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3040. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3041. } else {
  3042. qdf_nbuf_free(nbuf_clone);
  3043. }
  3044. }
  3045. if (no_enc_frame)
  3046. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3047. else
  3048. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3049. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3050. if ((!nbuf) && no_enc_frame) {
  3051. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3052. }
  3053. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3054. return nbuf;
  3055. }
  3056. #else
  3057. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3058. qdf_nbuf_t nbuf)
  3059. {
  3060. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3061. }
  3062. #endif
  3063. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3064. static inline
  3065. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3066. {
  3067. if (nbuf) {
  3068. qdf_prefetch(&nbuf->len);
  3069. qdf_prefetch(&nbuf->data);
  3070. }
  3071. }
  3072. #else
  3073. static inline
  3074. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3075. {
  3076. }
  3077. #endif
  3078. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3079. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3080. qdf_nbuf_t nbuf)
  3081. {
  3082. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3083. struct dp_vdev *vdev = NULL;
  3084. vdev = soc->vdev_id_map[vdev_id];
  3085. if (qdf_unlikely(!vdev))
  3086. return nbuf;
  3087. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3088. return nbuf;
  3089. }
  3090. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3091. qdf_nbuf_t nbuf,
  3092. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3093. {
  3094. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3095. }
  3096. #endif
  3097. #ifdef FEATURE_DIRECT_LINK
  3098. /**
  3099. * dp_vdev_tx_mark_to_fw() - Mark to_fw bit for the tx packet
  3100. * @nbuf: skb
  3101. * @vdev: DP vdev handle
  3102. *
  3103. * Return: None
  3104. */
  3105. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3106. {
  3107. if (qdf_unlikely(vdev->to_fw))
  3108. QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf) = 1;
  3109. }
  3110. #else
  3111. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3112. {
  3113. }
  3114. #endif
  3115. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3116. qdf_nbuf_t nbuf)
  3117. {
  3118. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3119. uint16_t peer_id = HTT_INVALID_PEER;
  3120. /*
  3121. * doing a memzero is causing additional function call overhead
  3122. * so doing static stack clearing
  3123. */
  3124. struct dp_tx_msdu_info_s msdu_info = {0};
  3125. struct dp_vdev *vdev = NULL;
  3126. qdf_nbuf_t end_nbuf = NULL;
  3127. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3128. return nbuf;
  3129. /*
  3130. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3131. * this in per packet path.
  3132. *
  3133. * As in this path vdev memory is already protected with netdev
  3134. * tx lock
  3135. */
  3136. vdev = soc->vdev_id_map[vdev_id];
  3137. if (qdf_unlikely(!vdev))
  3138. return nbuf;
  3139. dp_vdev_tx_mark_to_fw(nbuf, vdev);
  3140. /*
  3141. * Set Default Host TID value to invalid TID
  3142. * (TID override disabled)
  3143. */
  3144. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3145. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  3146. if (qdf_unlikely(vdev->mesh_vdev)) {
  3147. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3148. &msdu_info);
  3149. if (!nbuf_mesh) {
  3150. dp_verbose_debug("Extracting mesh metadata failed");
  3151. return nbuf;
  3152. }
  3153. nbuf = nbuf_mesh;
  3154. }
  3155. /*
  3156. * Get HW Queue to use for this frame.
  3157. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3158. * dedicated for data and 1 for command.
  3159. * "queue_id" maps to one hardware ring.
  3160. * With each ring, we also associate a unique Tx descriptor pool
  3161. * to minimize lock contention for these resources.
  3162. */
  3163. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3164. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3165. 1);
  3166. /*
  3167. * TCL H/W supports 2 DSCP-TID mapping tables.
  3168. * Table 1 - Default DSCP-TID mapping table
  3169. * Table 2 - 1 DSCP-TID override table
  3170. *
  3171. * If we need a different DSCP-TID mapping for this vap,
  3172. * call tid_classify to extract DSCP/ToS from frame and
  3173. * map to a TID and store in msdu_info. This is later used
  3174. * to fill in TCL Input descriptor (per-packet TID override).
  3175. */
  3176. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3177. /*
  3178. * Classify the frame and call corresponding
  3179. * "prepare" function which extracts the segment (TSO)
  3180. * and fragmentation information (for TSO , SG, ME, or Raw)
  3181. * into MSDU_INFO structure which is later used to fill
  3182. * SW and HW descriptors.
  3183. */
  3184. if (qdf_nbuf_is_tso(nbuf)) {
  3185. dp_verbose_debug("TSO frame %pK", vdev);
  3186. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3187. qdf_nbuf_len(nbuf));
  3188. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3189. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3190. qdf_nbuf_len(nbuf));
  3191. return nbuf;
  3192. }
  3193. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  3194. goto send_multiple;
  3195. }
  3196. /* SG */
  3197. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3198. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3199. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3200. return nbuf;
  3201. } else {
  3202. struct dp_tx_seg_info_s seg_info = {0};
  3203. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3204. goto send_single;
  3205. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3206. &msdu_info);
  3207. if (!nbuf)
  3208. return NULL;
  3209. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3210. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3211. qdf_nbuf_len(nbuf));
  3212. goto send_multiple;
  3213. }
  3214. }
  3215. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3216. return NULL;
  3217. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3218. return nbuf;
  3219. /* RAW */
  3220. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3221. struct dp_tx_seg_info_s seg_info = {0};
  3222. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3223. if (!nbuf)
  3224. return NULL;
  3225. dp_verbose_debug("Raw frame %pK", vdev);
  3226. goto send_multiple;
  3227. }
  3228. if (qdf_unlikely(vdev->nawds_enabled)) {
  3229. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3230. qdf_nbuf_data(nbuf);
  3231. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3232. uint16_t sa_peer_id = DP_INVALID_PEER;
  3233. if (!soc->ast_offload_support) {
  3234. struct dp_ast_entry *ast_entry = NULL;
  3235. qdf_spin_lock_bh(&soc->ast_lock);
  3236. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3237. (soc,
  3238. (uint8_t *)(eh->ether_shost),
  3239. vdev->pdev->pdev_id);
  3240. if (ast_entry)
  3241. sa_peer_id = ast_entry->peer_id;
  3242. qdf_spin_unlock_bh(&soc->ast_lock);
  3243. }
  3244. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3245. sa_peer_id);
  3246. }
  3247. peer_id = DP_INVALID_PEER;
  3248. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3249. 1, qdf_nbuf_len(nbuf));
  3250. }
  3251. send_single:
  3252. /* Single linear frame */
  3253. /*
  3254. * If nbuf is a simple linear frame, use send_single function to
  3255. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3256. * SRNG. There is no need to setup a MSDU extension descriptor.
  3257. */
  3258. dp_tx_prefetch_nbuf_data(nbuf);
  3259. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3260. peer_id, end_nbuf);
  3261. return nbuf;
  3262. send_multiple:
  3263. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3264. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3265. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3266. return nbuf;
  3267. }
  3268. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3269. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3270. {
  3271. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3272. struct dp_vdev *vdev = NULL;
  3273. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3274. return nbuf;
  3275. /*
  3276. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3277. * this in per packet path.
  3278. *
  3279. * As in this path vdev memory is already protected with netdev
  3280. * tx lock
  3281. */
  3282. vdev = soc->vdev_id_map[vdev_id];
  3283. if (qdf_unlikely(!vdev))
  3284. return nbuf;
  3285. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3286. == QDF_STATUS_E_FAILURE)) {
  3287. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3288. return nbuf;
  3289. }
  3290. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3291. }
  3292. #ifdef UMAC_SUPPORT_PROXY_ARP
  3293. /**
  3294. * dp_tx_proxy_arp() - Tx proxy arp handler
  3295. * @vdev: datapath vdev handle
  3296. * @nbuf: sk buffer
  3297. *
  3298. * Return: status
  3299. */
  3300. static inline
  3301. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3302. {
  3303. if (vdev->osif_proxy_arp)
  3304. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3305. /*
  3306. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3307. * osif_proxy_arp has a valid function pointer assigned
  3308. * to it
  3309. */
  3310. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3311. return QDF_STATUS_NOT_INITIALIZED;
  3312. }
  3313. #else
  3314. static inline
  3315. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3316. {
  3317. return QDF_STATUS_SUCCESS;
  3318. }
  3319. #endif
  3320. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  3321. !defined(CONFIG_MLO_SINGLE_DEV)
  3322. #ifdef WLAN_MCAST_MLO
  3323. static bool
  3324. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3325. struct dp_tx_desc_s *tx_desc,
  3326. qdf_nbuf_t nbuf,
  3327. uint8_t reinject_reason)
  3328. {
  3329. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3330. if (soc->arch_ops.dp_tx_mcast_handler)
  3331. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3332. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3333. return true;
  3334. }
  3335. return false;
  3336. }
  3337. #else /* WLAN_MCAST_MLO */
  3338. static inline bool
  3339. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3340. struct dp_tx_desc_s *tx_desc,
  3341. qdf_nbuf_t nbuf,
  3342. uint8_t reinject_reason)
  3343. {
  3344. return false;
  3345. }
  3346. #endif /* WLAN_MCAST_MLO */
  3347. #else
  3348. static inline bool
  3349. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3350. struct dp_tx_desc_s *tx_desc,
  3351. qdf_nbuf_t nbuf,
  3352. uint8_t reinject_reason)
  3353. {
  3354. return false;
  3355. }
  3356. #endif
  3357. void dp_tx_reinject_handler(struct dp_soc *soc,
  3358. struct dp_vdev *vdev,
  3359. struct dp_tx_desc_s *tx_desc,
  3360. uint8_t *status,
  3361. uint8_t reinject_reason)
  3362. {
  3363. struct dp_peer *peer = NULL;
  3364. uint32_t peer_id = HTT_INVALID_PEER;
  3365. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3366. qdf_nbuf_t nbuf_copy = NULL;
  3367. struct dp_tx_msdu_info_s msdu_info;
  3368. #ifdef WDS_VENDOR_EXTENSION
  3369. int is_mcast = 0, is_ucast = 0;
  3370. int num_peers_3addr = 0;
  3371. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3372. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3373. #endif
  3374. struct dp_txrx_peer *txrx_peer;
  3375. qdf_assert(vdev);
  3376. dp_tx_debug("Tx reinject path");
  3377. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3378. qdf_nbuf_len(tx_desc->nbuf));
  3379. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3380. return;
  3381. #ifdef WDS_VENDOR_EXTENSION
  3382. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3383. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3384. } else {
  3385. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3386. }
  3387. is_ucast = !is_mcast;
  3388. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3389. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3390. txrx_peer = dp_get_txrx_peer(peer);
  3391. if (!txrx_peer || txrx_peer->bss_peer)
  3392. continue;
  3393. /* Detect wds peers that use 3-addr framing for mcast.
  3394. * if there are any, the bss_peer is used to send the
  3395. * the mcast frame using 3-addr format. all wds enabled
  3396. * peers that use 4-addr framing for mcast frames will
  3397. * be duplicated and sent as 4-addr frames below.
  3398. */
  3399. if (!txrx_peer->wds_enabled ||
  3400. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3401. num_peers_3addr = 1;
  3402. break;
  3403. }
  3404. }
  3405. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3406. #endif
  3407. if (qdf_unlikely(vdev->mesh_vdev)) {
  3408. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3409. } else {
  3410. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3411. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3412. txrx_peer = dp_get_txrx_peer(peer);
  3413. if (!txrx_peer)
  3414. continue;
  3415. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3416. #ifdef WDS_VENDOR_EXTENSION
  3417. /*
  3418. * . if 3-addr STA, then send on BSS Peer
  3419. * . if Peer WDS enabled and accept 4-addr mcast,
  3420. * send mcast on that peer only
  3421. * . if Peer WDS enabled and accept 4-addr ucast,
  3422. * send ucast on that peer only
  3423. */
  3424. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3425. (txrx_peer->wds_enabled &&
  3426. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3427. (is_ucast &&
  3428. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3429. #else
  3430. (txrx_peer->bss_peer &&
  3431. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3432. #endif
  3433. peer_id = DP_INVALID_PEER;
  3434. nbuf_copy = qdf_nbuf_copy(nbuf);
  3435. if (!nbuf_copy) {
  3436. dp_tx_debug("nbuf copy failed");
  3437. break;
  3438. }
  3439. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3440. dp_tx_get_queue(vdev, nbuf,
  3441. &msdu_info.tx_queue);
  3442. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3443. nbuf_copy,
  3444. &msdu_info,
  3445. peer_id,
  3446. NULL);
  3447. if (nbuf_copy) {
  3448. dp_tx_debug("pkt send failed");
  3449. qdf_nbuf_free(nbuf_copy);
  3450. }
  3451. }
  3452. }
  3453. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3454. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3455. QDF_DMA_TO_DEVICE, nbuf->len);
  3456. qdf_nbuf_free(nbuf);
  3457. }
  3458. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3459. }
  3460. void dp_tx_inspect_handler(struct dp_soc *soc,
  3461. struct dp_vdev *vdev,
  3462. struct dp_tx_desc_s *tx_desc,
  3463. uint8_t *status)
  3464. {
  3465. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3466. "%s Tx inspect path",
  3467. __func__);
  3468. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3469. qdf_nbuf_len(tx_desc->nbuf));
  3470. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3471. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3472. }
  3473. #ifdef MESH_MODE_SUPPORT
  3474. /**
  3475. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3476. * in mesh meta header
  3477. * @tx_desc: software descriptor head pointer
  3478. * @ts: pointer to tx completion stats
  3479. * Return: none
  3480. */
  3481. static
  3482. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3483. struct hal_tx_completion_status *ts)
  3484. {
  3485. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3486. if (!tx_desc->msdu_ext_desc) {
  3487. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3488. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3489. "netbuf %pK offset %d",
  3490. netbuf, tx_desc->pkt_offset);
  3491. return;
  3492. }
  3493. }
  3494. }
  3495. #else
  3496. static
  3497. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3498. struct hal_tx_completion_status *ts)
  3499. {
  3500. }
  3501. #endif
  3502. #ifdef CONFIG_SAWF
  3503. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3504. struct dp_vdev *vdev,
  3505. struct dp_txrx_peer *txrx_peer,
  3506. struct dp_tx_desc_s *tx_desc,
  3507. struct hal_tx_completion_status *ts,
  3508. uint8_t tid)
  3509. {
  3510. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3511. ts, tid);
  3512. }
  3513. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3514. uint32_t nw_delay,
  3515. uint32_t sw_delay,
  3516. uint32_t hw_delay)
  3517. {
  3518. dp_peer_tid_delay_avg(tx_delay,
  3519. nw_delay,
  3520. sw_delay,
  3521. hw_delay);
  3522. }
  3523. #else
  3524. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3525. struct dp_vdev *vdev,
  3526. struct dp_txrx_peer *txrx_peer,
  3527. struct dp_tx_desc_s *tx_desc,
  3528. struct hal_tx_completion_status *ts,
  3529. uint8_t tid)
  3530. {
  3531. }
  3532. static inline void
  3533. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3534. uint32_t nw_delay, uint32_t sw_delay,
  3535. uint32_t hw_delay)
  3536. {
  3537. }
  3538. #endif
  3539. #ifdef QCA_PEER_EXT_STATS
  3540. #ifdef WLAN_CONFIG_TX_DELAY
  3541. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3542. struct dp_tx_desc_s *tx_desc,
  3543. struct hal_tx_completion_status *ts,
  3544. struct dp_vdev *vdev)
  3545. {
  3546. struct dp_soc *soc = vdev->pdev->soc;
  3547. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3548. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3549. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3550. if (!ts->valid)
  3551. return;
  3552. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3553. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3554. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3555. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3556. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3557. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3558. &fwhw_transmit_delay))
  3559. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3560. fwhw_transmit_delay);
  3561. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3562. fwhw_transmit_delay);
  3563. }
  3564. #else
  3565. /**
  3566. * dp_tx_compute_tid_delay() - Compute per TID delay
  3567. * @stats: Per TID delay stats
  3568. * @tx_desc: Software Tx descriptor
  3569. * @ts: Tx completion status
  3570. * @vdev: vdev
  3571. *
  3572. * Compute the software enqueue and hw enqueue delays and
  3573. * update the respective histograms
  3574. *
  3575. * Return: void
  3576. */
  3577. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3578. struct dp_tx_desc_s *tx_desc,
  3579. struct hal_tx_completion_status *ts,
  3580. struct dp_vdev *vdev)
  3581. {
  3582. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3583. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3584. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3585. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3586. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3587. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3588. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3589. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3590. timestamp_hw_enqueue);
  3591. /*
  3592. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3593. */
  3594. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3595. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3596. }
  3597. #endif
  3598. /**
  3599. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3600. * @txrx_peer: DP peer context
  3601. * @tx_desc: Tx software descriptor
  3602. * @ts: Tx completion status
  3603. * @ring_id: Rx CPU context ID/CPU_ID
  3604. *
  3605. * Update the peer extended stats. These are enhanced other
  3606. * delay stats per msdu level.
  3607. *
  3608. * Return: void
  3609. */
  3610. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3611. struct dp_tx_desc_s *tx_desc,
  3612. struct hal_tx_completion_status *ts,
  3613. uint8_t ring_id)
  3614. {
  3615. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3616. struct dp_soc *soc = NULL;
  3617. struct dp_peer_delay_stats *delay_stats = NULL;
  3618. uint8_t tid;
  3619. soc = pdev->soc;
  3620. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3621. return;
  3622. if (!txrx_peer->delay_stats)
  3623. return;
  3624. tid = ts->tid;
  3625. delay_stats = txrx_peer->delay_stats;
  3626. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3627. /*
  3628. * For non-TID packets use the TID 9
  3629. */
  3630. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3631. tid = CDP_MAX_DATA_TIDS - 1;
  3632. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3633. tx_desc, ts, txrx_peer->vdev);
  3634. }
  3635. #else
  3636. static inline
  3637. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3638. struct dp_tx_desc_s *tx_desc,
  3639. struct hal_tx_completion_status *ts,
  3640. uint8_t ring_id)
  3641. {
  3642. }
  3643. #endif
  3644. #ifdef WLAN_PEER_JITTER
  3645. /**
  3646. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3647. * @curr_delay: Current delay
  3648. * @prev_delay: Previous delay
  3649. * @avg_jitter: Average Jitter
  3650. * Return: Newly Computed Average Jitter
  3651. */
  3652. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3653. uint32_t prev_delay,
  3654. uint32_t avg_jitter)
  3655. {
  3656. uint32_t curr_jitter;
  3657. int32_t jitter_diff;
  3658. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3659. if (!avg_jitter)
  3660. return curr_jitter;
  3661. jitter_diff = curr_jitter - avg_jitter;
  3662. if (jitter_diff < 0)
  3663. avg_jitter = avg_jitter -
  3664. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3665. else
  3666. avg_jitter = avg_jitter +
  3667. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3668. return avg_jitter;
  3669. }
  3670. /**
  3671. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3672. * @curr_delay: Current delay
  3673. * @avg_delay: Average delay
  3674. * Return: Newly Computed Average Delay
  3675. */
  3676. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3677. uint32_t avg_delay)
  3678. {
  3679. int32_t delay_diff;
  3680. if (!avg_delay)
  3681. return curr_delay;
  3682. delay_diff = curr_delay - avg_delay;
  3683. if (delay_diff < 0)
  3684. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3685. DP_AVG_DELAY_WEIGHT_DENOM);
  3686. else
  3687. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3688. DP_AVG_DELAY_WEIGHT_DENOM);
  3689. return avg_delay;
  3690. }
  3691. #ifdef WLAN_CONFIG_TX_DELAY
  3692. /**
  3693. * dp_tx_compute_cur_delay() - get the current delay
  3694. * @soc: soc handle
  3695. * @vdev: vdev structure for data path state
  3696. * @ts: Tx completion status
  3697. * @curr_delay: current delay
  3698. * @tx_desc: tx descriptor
  3699. * Return: void
  3700. */
  3701. static
  3702. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3703. struct dp_vdev *vdev,
  3704. struct hal_tx_completion_status *ts,
  3705. uint32_t *curr_delay,
  3706. struct dp_tx_desc_s *tx_desc)
  3707. {
  3708. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3709. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3710. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3711. curr_delay);
  3712. return status;
  3713. }
  3714. #else
  3715. static
  3716. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3717. struct dp_vdev *vdev,
  3718. struct hal_tx_completion_status *ts,
  3719. uint32_t *curr_delay,
  3720. struct dp_tx_desc_s *tx_desc)
  3721. {
  3722. int64_t current_timestamp, timestamp_hw_enqueue;
  3723. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3724. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3725. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3726. return QDF_STATUS_SUCCESS;
  3727. }
  3728. #endif
  3729. /**
  3730. * dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3731. * @jitter: per tid per ring jitter stats
  3732. * @ts: Tx completion status
  3733. * @vdev: vdev structure for data path state
  3734. * @tx_desc: tx descriptor
  3735. * Return: void
  3736. */
  3737. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3738. struct hal_tx_completion_status *ts,
  3739. struct dp_vdev *vdev,
  3740. struct dp_tx_desc_s *tx_desc)
  3741. {
  3742. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3743. struct dp_soc *soc = vdev->pdev->soc;
  3744. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3745. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3746. jitter->tx_drop += 1;
  3747. return;
  3748. }
  3749. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3750. tx_desc);
  3751. if (QDF_IS_STATUS_SUCCESS(status)) {
  3752. avg_delay = jitter->tx_avg_delay;
  3753. avg_jitter = jitter->tx_avg_jitter;
  3754. prev_delay = jitter->tx_prev_delay;
  3755. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3756. prev_delay,
  3757. avg_jitter);
  3758. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3759. jitter->tx_avg_delay = avg_delay;
  3760. jitter->tx_avg_jitter = avg_jitter;
  3761. jitter->tx_prev_delay = curr_delay;
  3762. jitter->tx_total_success += 1;
  3763. } else if (status == QDF_STATUS_E_FAILURE) {
  3764. jitter->tx_avg_err += 1;
  3765. }
  3766. }
  3767. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3768. * @txrx_peer: DP peer context
  3769. * @tx_desc: Tx software descriptor
  3770. * @ts: Tx completion status
  3771. * @ring_id: Rx CPU context ID/CPU_ID
  3772. * Return: void
  3773. */
  3774. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3775. struct dp_tx_desc_s *tx_desc,
  3776. struct hal_tx_completion_status *ts,
  3777. uint8_t ring_id)
  3778. {
  3779. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3780. struct dp_soc *soc = pdev->soc;
  3781. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3782. uint8_t tid;
  3783. struct cdp_peer_tid_stats *rx_tid = NULL;
  3784. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3785. return;
  3786. tid = ts->tid;
  3787. jitter_stats = txrx_peer->jitter_stats;
  3788. qdf_assert_always(jitter_stats);
  3789. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3790. /*
  3791. * For non-TID packets use the TID 9
  3792. */
  3793. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3794. tid = CDP_MAX_DATA_TIDS - 1;
  3795. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3796. dp_tx_compute_tid_jitter(rx_tid,
  3797. ts, txrx_peer->vdev, tx_desc);
  3798. }
  3799. #else
  3800. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3801. struct dp_tx_desc_s *tx_desc,
  3802. struct hal_tx_completion_status *ts,
  3803. uint8_t ring_id)
  3804. {
  3805. }
  3806. #endif
  3807. #ifdef HW_TX_DELAY_STATS_ENABLE
  3808. /**
  3809. * dp_update_tx_delay_stats() - update the delay stats
  3810. * @vdev: vdev handle
  3811. * @delay: delay in ms or us based on the flag delay_in_us
  3812. * @tid: tid value
  3813. * @mode: type of tx delay mode
  3814. * @ring_id: ring number
  3815. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3816. *
  3817. * Return: none
  3818. */
  3819. static inline
  3820. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3821. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3822. {
  3823. struct cdp_tid_tx_stats *tstats =
  3824. &vdev->stats.tid_tx_stats[ring_id][tid];
  3825. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3826. delay_in_us);
  3827. }
  3828. #else
  3829. static inline
  3830. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3831. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3832. {
  3833. struct cdp_tid_tx_stats *tstats =
  3834. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3835. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3836. delay_in_us);
  3837. }
  3838. #endif
  3839. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3840. uint8_t tid, uint8_t ring_id)
  3841. {
  3842. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3843. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3844. uint32_t fwhw_transmit_delay_us;
  3845. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3846. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3847. return;
  3848. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3849. fwhw_transmit_delay_us =
  3850. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3851. qdf_ktime_to_us(tx_desc->timestamp);
  3852. /*
  3853. * Delay between packet enqueued to HW and Tx completion in us
  3854. */
  3855. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3856. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3857. ring_id, true);
  3858. /*
  3859. * For MCL, only enqueue to completion delay is required
  3860. * so return if the vdev flag is enabled.
  3861. */
  3862. return;
  3863. }
  3864. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3865. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3866. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3867. timestamp_hw_enqueue);
  3868. if (!timestamp_hw_enqueue)
  3869. return;
  3870. /*
  3871. * Delay between packet enqueued to HW and Tx completion in ms
  3872. */
  3873. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3874. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3875. false);
  3876. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3877. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3878. interframe_delay = (uint32_t)(timestamp_ingress -
  3879. vdev->prev_tx_enq_tstamp);
  3880. /*
  3881. * Delay in software enqueue
  3882. */
  3883. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3884. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3885. false);
  3886. /*
  3887. * Update interframe delay stats calculated at hardstart receive point.
  3888. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3889. * interframe delay will not be calculate correctly for 1st frame.
  3890. * On the other side, this will help in avoiding extra per packet check
  3891. * of !vdev->prev_tx_enq_tstamp.
  3892. */
  3893. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3894. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3895. false);
  3896. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3897. }
  3898. #ifdef DISABLE_DP_STATS
  3899. static
  3900. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3901. struct dp_txrx_peer *txrx_peer,
  3902. uint8_t link_id)
  3903. {
  3904. }
  3905. #else
  3906. static inline void
  3907. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer,
  3908. uint8_t link_id)
  3909. {
  3910. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3911. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3912. if (subtype != QDF_PROTO_INVALID)
  3913. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3914. 1, link_id);
  3915. }
  3916. #endif
  3917. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3918. #ifdef DP_PEER_EXTENDED_API
  3919. static inline uint8_t
  3920. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3921. {
  3922. return txrx_peer->mpdu_retry_threshold;
  3923. }
  3924. #else
  3925. static inline uint8_t
  3926. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3927. {
  3928. return 0;
  3929. }
  3930. #endif
  3931. /**
  3932. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3933. *
  3934. * @ts: Tx compltion status
  3935. * @txrx_peer: datapath txrx_peer handle
  3936. * @link_id: Link id
  3937. *
  3938. * Return: void
  3939. */
  3940. static inline void
  3941. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3942. struct dp_txrx_peer *txrx_peer, uint8_t link_id)
  3943. {
  3944. uint8_t mcs, pkt_type, dst_mcs_idx;
  3945. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  3946. mcs = ts->mcs;
  3947. pkt_type = ts->pkt_type;
  3948. /* do HW to SW pkt type conversion */
  3949. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3950. hal_2_dp_pkt_type_map[pkt_type]);
  3951. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3952. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3953. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3954. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3955. 1, link_id);
  3956. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1, link_id);
  3957. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1, link_id);
  3958. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi,
  3959. link_id);
  3960. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3961. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1,
  3962. link_id);
  3963. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc, link_id);
  3964. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc, link_id);
  3965. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1,
  3966. link_id);
  3967. if (ts->first_msdu) {
  3968. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3969. ts->transmit_cnt > 1, link_id);
  3970. if (!retry_threshold)
  3971. return;
  3972. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3973. qdf_do_div(ts->transmit_cnt,
  3974. retry_threshold),
  3975. ts->transmit_cnt > retry_threshold,
  3976. link_id);
  3977. }
  3978. }
  3979. #else
  3980. static inline void
  3981. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3982. struct dp_txrx_peer *txrx_peer, uint8_t link_id)
  3983. {
  3984. }
  3985. #endif
  3986. #ifdef WLAN_FEATURE_11BE_MLO
  3987. static inline int
  3988. dp_tx_get_link_id_from_ppdu_id(struct dp_soc *soc,
  3989. struct hal_tx_completion_status *ts,
  3990. struct dp_txrx_peer *txrx_peer,
  3991. struct dp_vdev *vdev)
  3992. {
  3993. uint8_t hw_link_id = 0;
  3994. uint32_t ppdu_id;
  3995. uint8_t link_id_offset, link_id_bits;
  3996. if (!txrx_peer->is_mld_peer || !vdev->pdev->link_peer_stats)
  3997. return 0;
  3998. link_id_offset = soc->link_id_offset;
  3999. link_id_bits = soc->link_id_bits;
  4000. ppdu_id = ts->ppdu_id;
  4001. hw_link_id = DP_GET_HW_LINK_ID_FRM_PPDU_ID(ppdu_id, link_id_offset,
  4002. link_id_bits);
  4003. return (hw_link_id + 1);
  4004. }
  4005. #else
  4006. static inline int
  4007. dp_tx_get_link_id_from_ppdu_id(struct dp_soc *soc,
  4008. struct hal_tx_completion_status *ts,
  4009. struct dp_txrx_peer *txrx_peer,
  4010. struct dp_vdev *vdev)
  4011. {
  4012. return 0;
  4013. }
  4014. #endif
  4015. /**
  4016. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4017. * per wbm ring
  4018. *
  4019. * @tx_desc: software descriptor head pointer
  4020. * @ts: Tx completion status
  4021. * @txrx_peer: peer handle
  4022. * @ring_id: ring number
  4023. * @link_id: Link id
  4024. *
  4025. * Return: None
  4026. */
  4027. static inline void
  4028. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4029. struct hal_tx_completion_status *ts,
  4030. struct dp_txrx_peer *txrx_peer, uint8_t ring_id,
  4031. uint8_t link_id)
  4032. {
  4033. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4034. uint8_t tid = ts->tid;
  4035. uint32_t length;
  4036. struct cdp_tid_tx_stats *tid_stats;
  4037. if (!pdev)
  4038. return;
  4039. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4040. tid = CDP_MAX_DATA_TIDS - 1;
  4041. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4042. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4043. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4044. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1,
  4045. link_id);
  4046. return;
  4047. }
  4048. length = qdf_nbuf_len(tx_desc->nbuf);
  4049. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4050. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4051. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4052. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4053. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4054. tid_stats->tqm_status_cnt[ts->status]++;
  4055. }
  4056. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4057. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4058. ts->transmit_cnt > 1, link_id);
  4059. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4060. 1, ts->transmit_cnt > 2, link_id);
  4061. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma,
  4062. link_id);
  4063. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4064. ts->msdu_part_of_amsdu, link_id);
  4065. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4066. !ts->msdu_part_of_amsdu, link_id);
  4067. txrx_peer->stats[link_id].per_pkt_stats.tx.last_tx_ts =
  4068. qdf_system_ticks();
  4069. dp_tx_update_peer_extd_stats(ts, txrx_peer, link_id);
  4070. return;
  4071. }
  4072. /*
  4073. * tx_failed is ideally supposed to be updated from HTT ppdu
  4074. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4075. * hw limitation there are no completions for failed cases.
  4076. * Hence updating tx_failed from data path. Please note that
  4077. * if tx_failed is fixed to be from ppdu, then this has to be
  4078. * removed
  4079. */
  4080. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4081. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4082. ts->transmit_cnt > DP_RETRY_COUNT,
  4083. link_id);
  4084. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer, link_id);
  4085. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4086. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1,
  4087. link_id);
  4088. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4089. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4090. length, link_id);
  4091. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4092. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1,
  4093. link_id);
  4094. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4095. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1,
  4096. link_id);
  4097. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4098. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1,
  4099. link_id);
  4100. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4101. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1,
  4102. link_id);
  4103. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4104. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1,
  4105. link_id);
  4106. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4107. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4108. tx.dropped.fw_rem_queue_disable, 1,
  4109. link_id);
  4110. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4111. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4112. tx.dropped.fw_rem_no_match, 1,
  4113. link_id);
  4114. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4115. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4116. tx.dropped.drop_threshold, 1,
  4117. link_id);
  4118. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4119. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4120. tx.dropped.drop_link_desc_na, 1,
  4121. link_id);
  4122. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4123. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4124. tx.dropped.invalid_drop, 1,
  4125. link_id);
  4126. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4127. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4128. tx.dropped.mcast_vdev_drop, 1,
  4129. link_id);
  4130. } else {
  4131. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1,
  4132. link_id);
  4133. }
  4134. }
  4135. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4136. /**
  4137. * dp_tx_flow_pool_lock() - take flow pool lock
  4138. * @soc: core txrx main context
  4139. * @tx_desc: tx desc
  4140. *
  4141. * Return: None
  4142. */
  4143. static inline
  4144. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4145. struct dp_tx_desc_s *tx_desc)
  4146. {
  4147. struct dp_tx_desc_pool_s *pool;
  4148. uint8_t desc_pool_id;
  4149. desc_pool_id = tx_desc->pool_id;
  4150. pool = &soc->tx_desc[desc_pool_id];
  4151. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4152. }
  4153. /**
  4154. * dp_tx_flow_pool_unlock() - release flow pool lock
  4155. * @soc: core txrx main context
  4156. * @tx_desc: tx desc
  4157. *
  4158. * Return: None
  4159. */
  4160. static inline
  4161. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4162. struct dp_tx_desc_s *tx_desc)
  4163. {
  4164. struct dp_tx_desc_pool_s *pool;
  4165. uint8_t desc_pool_id;
  4166. desc_pool_id = tx_desc->pool_id;
  4167. pool = &soc->tx_desc[desc_pool_id];
  4168. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4169. }
  4170. #else
  4171. static inline
  4172. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4173. {
  4174. }
  4175. static inline
  4176. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4177. {
  4178. }
  4179. #endif
  4180. /**
  4181. * dp_tx_notify_completion() - Notify tx completion for this desc
  4182. * @soc: core txrx main context
  4183. * @vdev: datapath vdev handle
  4184. * @tx_desc: tx desc
  4185. * @netbuf: buffer
  4186. * @status: tx status
  4187. *
  4188. * Return: none
  4189. */
  4190. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4191. struct dp_vdev *vdev,
  4192. struct dp_tx_desc_s *tx_desc,
  4193. qdf_nbuf_t netbuf,
  4194. uint8_t status)
  4195. {
  4196. void *osif_dev;
  4197. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4198. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4199. qdf_assert(tx_desc);
  4200. if (!vdev ||
  4201. !vdev->osif_vdev) {
  4202. return;
  4203. }
  4204. osif_dev = vdev->osif_vdev;
  4205. tx_compl_cbk = vdev->tx_comp;
  4206. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4207. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4208. if (tx_compl_cbk)
  4209. tx_compl_cbk(netbuf, osif_dev, flag);
  4210. }
  4211. /**
  4212. * dp_tx_sojourn_stats_process() - Collect sojourn stats
  4213. * @pdev: pdev handle
  4214. * @txrx_peer: DP peer context
  4215. * @tid: tid value
  4216. * @txdesc_ts: timestamp from txdesc
  4217. * @ppdu_id: ppdu id
  4218. * @link_id: link id
  4219. *
  4220. * Return: none
  4221. */
  4222. #ifdef FEATURE_PERPKT_INFO
  4223. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4224. struct dp_txrx_peer *txrx_peer,
  4225. uint8_t tid,
  4226. uint64_t txdesc_ts,
  4227. uint32_t ppdu_id,
  4228. uint8_t link_id)
  4229. {
  4230. uint64_t delta_ms;
  4231. struct cdp_tx_sojourn_stats *sojourn_stats;
  4232. struct dp_peer *primary_link_peer = NULL;
  4233. struct dp_soc *link_peer_soc = NULL;
  4234. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4235. return;
  4236. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4237. tid >= CDP_DATA_TID_MAX))
  4238. return;
  4239. if (qdf_unlikely(!pdev->sojourn_buf))
  4240. return;
  4241. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4242. txrx_peer->peer_id,
  4243. DP_MOD_ID_TX_COMP);
  4244. if (qdf_unlikely(!primary_link_peer))
  4245. return;
  4246. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4247. qdf_nbuf_data(pdev->sojourn_buf);
  4248. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4249. sojourn_stats->cookie = (void *)
  4250. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4251. primary_link_peer);
  4252. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4253. txdesc_ts;
  4254. qdf_ewma_tx_lag_add(&txrx_peer->stats[link_id].per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4255. delta_ms);
  4256. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4257. sojourn_stats->num_msdus[tid] = 1;
  4258. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4259. txrx_peer->stats[link_id].
  4260. per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4261. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4262. pdev->sojourn_buf, HTT_INVALID_PEER,
  4263. WDI_NO_VAL, pdev->pdev_id);
  4264. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4265. sojourn_stats->num_msdus[tid] = 0;
  4266. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4267. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4268. }
  4269. #else
  4270. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4271. struct dp_txrx_peer *txrx_peer,
  4272. uint8_t tid,
  4273. uint64_t txdesc_ts,
  4274. uint32_t ppdu_id)
  4275. {
  4276. }
  4277. #endif
  4278. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4279. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4280. struct dp_tx_desc_s *desc,
  4281. struct hal_tx_completion_status *ts)
  4282. {
  4283. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4284. desc, ts->peer_id,
  4285. WDI_NO_VAL, desc->pdev->pdev_id);
  4286. }
  4287. #endif
  4288. void
  4289. dp_tx_comp_process_desc(struct dp_soc *soc,
  4290. struct dp_tx_desc_s *desc,
  4291. struct hal_tx_completion_status *ts,
  4292. struct dp_txrx_peer *txrx_peer)
  4293. {
  4294. uint64_t time_latency = 0;
  4295. uint16_t peer_id = DP_INVALID_PEER_ID;
  4296. /*
  4297. * m_copy/tx_capture modes are not supported for
  4298. * scatter gather packets
  4299. */
  4300. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4301. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4302. qdf_ktime_to_ms(desc->timestamp));
  4303. }
  4304. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4305. if (dp_tx_pkt_tracepoints_enabled())
  4306. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4307. desc->msdu_ext_desc ?
  4308. desc->msdu_ext_desc->tso_desc : NULL,
  4309. qdf_ktime_to_ms(desc->timestamp));
  4310. if (!(desc->msdu_ext_desc)) {
  4311. dp_tx_enh_unmap(soc, desc);
  4312. if (txrx_peer)
  4313. peer_id = txrx_peer->peer_id;
  4314. if (QDF_STATUS_SUCCESS ==
  4315. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4316. return;
  4317. }
  4318. if (QDF_STATUS_SUCCESS ==
  4319. dp_get_completion_indication_for_stack(soc,
  4320. desc->pdev,
  4321. txrx_peer, ts,
  4322. desc->nbuf,
  4323. time_latency)) {
  4324. dp_send_completion_to_stack(soc,
  4325. desc->pdev,
  4326. ts->peer_id,
  4327. ts->ppdu_id,
  4328. desc->nbuf);
  4329. return;
  4330. }
  4331. }
  4332. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4333. dp_tx_comp_free_buf(soc, desc, false);
  4334. }
  4335. #ifdef DISABLE_DP_STATS
  4336. /**
  4337. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4338. * @soc: core txrx main context
  4339. * @vdev: virtual device instance
  4340. * @tx_desc: tx desc
  4341. * @status: tx status
  4342. *
  4343. * Return: none
  4344. */
  4345. static inline
  4346. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4347. struct dp_vdev *vdev,
  4348. struct dp_tx_desc_s *tx_desc,
  4349. uint8_t status)
  4350. {
  4351. }
  4352. #else
  4353. static inline
  4354. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4355. struct dp_vdev *vdev,
  4356. struct dp_tx_desc_s *tx_desc,
  4357. uint8_t status)
  4358. {
  4359. void *osif_dev;
  4360. ol_txrx_stats_rx_fp stats_cbk;
  4361. uint8_t pkt_type;
  4362. qdf_assert(tx_desc);
  4363. if (!vdev ||
  4364. !vdev->osif_vdev ||
  4365. !vdev->stats_cb)
  4366. return;
  4367. osif_dev = vdev->osif_vdev;
  4368. stats_cbk = vdev->stats_cb;
  4369. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4370. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4371. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4372. &pkt_type);
  4373. }
  4374. #endif
  4375. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4376. /* Mask for bit29 ~ bit31 */
  4377. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4378. /* Timestamp value (unit us) if bit29 is set */
  4379. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4380. /**
  4381. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4382. * @ack_ts: OTA ack timestamp, unit us.
  4383. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4384. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4385. *
  4386. * this function will restore the bit29 ~ bit31 3 bits value for
  4387. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4388. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4389. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4390. *
  4391. * Return: the adjusted buffer_timestamp value
  4392. */
  4393. static inline
  4394. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4395. uint32_t enqueue_ts,
  4396. uint32_t base_delta_ts)
  4397. {
  4398. uint32_t ack_buffer_ts;
  4399. uint32_t ack_buffer_ts_bit29_31;
  4400. uint32_t adjusted_enqueue_ts;
  4401. /* corresponding buffer_timestamp value when receive OTA Ack */
  4402. ack_buffer_ts = ack_ts - base_delta_ts;
  4403. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4404. /* restore the bit29 ~ bit31 value */
  4405. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4406. /*
  4407. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4408. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4409. * should not be marked, otherwise extra 0x20000000 us is added to
  4410. * enqueue_ts.
  4411. */
  4412. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4413. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4414. return adjusted_enqueue_ts;
  4415. }
  4416. QDF_STATUS
  4417. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4418. uint32_t delta_tsf,
  4419. uint32_t *delay_us)
  4420. {
  4421. uint32_t buffer_ts;
  4422. uint32_t delay;
  4423. if (!delay_us)
  4424. return QDF_STATUS_E_INVAL;
  4425. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4426. if (!ts->valid)
  4427. return QDF_STATUS_E_INVAL;
  4428. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4429. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4430. * valid up to 29 bits.
  4431. */
  4432. buffer_ts = ts->buffer_timestamp << 10;
  4433. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4434. buffer_ts, delta_tsf);
  4435. delay = ts->tsf - buffer_ts - delta_tsf;
  4436. if (qdf_unlikely(delay & 0x80000000)) {
  4437. dp_err_rl("delay = 0x%x (-ve)\n"
  4438. "release_src = %d\n"
  4439. "ppdu_id = 0x%x\n"
  4440. "peer_id = 0x%x\n"
  4441. "tid = 0x%x\n"
  4442. "release_reason = %d\n"
  4443. "tsf = %u (0x%x)\n"
  4444. "buffer_timestamp = %u (0x%x)\n"
  4445. "delta_tsf = %u (0x%x)\n",
  4446. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4447. ts->tid, ts->status, ts->tsf, ts->tsf,
  4448. ts->buffer_timestamp, ts->buffer_timestamp,
  4449. delta_tsf, delta_tsf);
  4450. delay = 0;
  4451. goto end;
  4452. }
  4453. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4454. if (delay > 0x1000000) {
  4455. dp_info_rl("----------------------\n"
  4456. "Tx completion status:\n"
  4457. "----------------------\n"
  4458. "release_src = %d\n"
  4459. "ppdu_id = 0x%x\n"
  4460. "release_reason = %d\n"
  4461. "tsf = %u (0x%x)\n"
  4462. "buffer_timestamp = %u (0x%x)\n"
  4463. "delta_tsf = %u (0x%x)\n",
  4464. ts->release_src, ts->ppdu_id, ts->status,
  4465. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4466. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4467. return QDF_STATUS_E_FAILURE;
  4468. }
  4469. end:
  4470. *delay_us = delay;
  4471. return QDF_STATUS_SUCCESS;
  4472. }
  4473. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4474. uint32_t delta_tsf)
  4475. {
  4476. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4477. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4478. DP_MOD_ID_CDP);
  4479. if (!vdev) {
  4480. dp_err_rl("vdev %d does not exist", vdev_id);
  4481. return;
  4482. }
  4483. vdev->delta_tsf = delta_tsf;
  4484. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4485. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4486. }
  4487. #endif
  4488. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4489. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4490. uint8_t vdev_id, bool enable)
  4491. {
  4492. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4493. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4494. DP_MOD_ID_CDP);
  4495. if (!vdev) {
  4496. dp_err_rl("vdev %d does not exist", vdev_id);
  4497. return QDF_STATUS_E_FAILURE;
  4498. }
  4499. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4500. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4501. return QDF_STATUS_SUCCESS;
  4502. }
  4503. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4504. uint32_t *val)
  4505. {
  4506. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4507. struct dp_vdev *vdev;
  4508. uint32_t delay_accum;
  4509. uint32_t pkts_accum;
  4510. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4511. if (!vdev) {
  4512. dp_err_rl("vdev %d does not exist", vdev_id);
  4513. return QDF_STATUS_E_FAILURE;
  4514. }
  4515. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4516. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4517. return QDF_STATUS_E_FAILURE;
  4518. }
  4519. /* Average uplink delay based on current accumulated values */
  4520. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4521. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4522. *val = delay_accum / pkts_accum;
  4523. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4524. delay_accum, pkts_accum);
  4525. /* Reset accumulated values to 0 */
  4526. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4527. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4528. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4529. return QDF_STATUS_SUCCESS;
  4530. }
  4531. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4532. struct hal_tx_completion_status *ts)
  4533. {
  4534. uint32_t ul_delay;
  4535. if (qdf_unlikely(!vdev)) {
  4536. dp_info_rl("vdev is null or delete in progress");
  4537. return;
  4538. }
  4539. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4540. return;
  4541. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4542. vdev->delta_tsf,
  4543. &ul_delay)))
  4544. return;
  4545. ul_delay /= 1000; /* in unit of ms */
  4546. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4547. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4548. }
  4549. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4550. static inline
  4551. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4552. struct hal_tx_completion_status *ts)
  4553. {
  4554. }
  4555. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4556. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4557. struct dp_tx_desc_s *tx_desc,
  4558. struct hal_tx_completion_status *ts,
  4559. struct dp_txrx_peer *txrx_peer,
  4560. uint8_t ring_id)
  4561. {
  4562. uint32_t length;
  4563. qdf_ether_header_t *eh;
  4564. struct dp_vdev *vdev = NULL;
  4565. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4566. enum qdf_dp_tx_rx_status dp_status;
  4567. uint8_t link_id = 0;
  4568. if (!nbuf) {
  4569. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4570. goto out;
  4571. }
  4572. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4573. length = dp_tx_get_pkt_len(tx_desc);
  4574. dp_status = dp_tx_hw_to_qdf(ts->status);
  4575. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4576. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4577. QDF_TRACE_DEFAULT_PDEV_ID,
  4578. qdf_nbuf_data_addr(nbuf),
  4579. sizeof(qdf_nbuf_data(nbuf)),
  4580. tx_desc->id, ts->status, dp_status));
  4581. dp_tx_comp_debug("-------------------- \n"
  4582. "Tx Completion Stats: \n"
  4583. "-------------------- \n"
  4584. "ack_frame_rssi = %d \n"
  4585. "first_msdu = %d \n"
  4586. "last_msdu = %d \n"
  4587. "msdu_part_of_amsdu = %d \n"
  4588. "rate_stats valid = %d \n"
  4589. "bw = %d \n"
  4590. "pkt_type = %d \n"
  4591. "stbc = %d \n"
  4592. "ldpc = %d \n"
  4593. "sgi = %d \n"
  4594. "mcs = %d \n"
  4595. "ofdma = %d \n"
  4596. "tones_in_ru = %d \n"
  4597. "tsf = %d \n"
  4598. "ppdu_id = %d \n"
  4599. "transmit_cnt = %d \n"
  4600. "tid = %d \n"
  4601. "peer_id = %d\n"
  4602. "tx_status = %d\n",
  4603. ts->ack_frame_rssi, ts->first_msdu,
  4604. ts->last_msdu, ts->msdu_part_of_amsdu,
  4605. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4606. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4607. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4608. ts->transmit_cnt, ts->tid, ts->peer_id,
  4609. ts->status);
  4610. /* Update SoC level stats */
  4611. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4612. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4613. if (!txrx_peer) {
  4614. dp_info_rl("peer is null or deletion in progress");
  4615. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4616. goto out;
  4617. }
  4618. vdev = txrx_peer->vdev;
  4619. #ifdef DP_MLO_LINK_STATS_SUPPORT
  4620. link_id = dp_tx_get_link_id_from_ppdu_id(soc, ts, txrx_peer, vdev);
  4621. if (link_id < 1 || link_id > DP_MAX_MLO_LINKS)
  4622. link_id = 0;
  4623. #endif
  4624. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4625. dp_tx_update_uplink_delay(soc, vdev, ts);
  4626. /* check tx complete notification */
  4627. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4628. dp_tx_notify_completion(soc, vdev, tx_desc,
  4629. nbuf, ts->status);
  4630. /* Update per-packet stats for mesh mode */
  4631. if (qdf_unlikely(vdev->mesh_vdev) &&
  4632. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4633. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4634. /* Update peer level stats */
  4635. if (qdf_unlikely(txrx_peer->bss_peer &&
  4636. vdev->opmode == wlan_op_mode_ap)) {
  4637. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4638. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4639. length, link_id);
  4640. if (txrx_peer->vdev->tx_encap_type ==
  4641. htt_cmn_pkt_type_ethernet &&
  4642. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4643. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4644. tx.bcast, 1,
  4645. length, link_id);
  4646. }
  4647. }
  4648. } else {
  4649. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length,
  4650. link_id);
  4651. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4652. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4653. 1, length, link_id);
  4654. if (qdf_unlikely(txrx_peer->in_twt)) {
  4655. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4656. tx.tx_success_twt,
  4657. 1, length,
  4658. link_id);
  4659. }
  4660. }
  4661. }
  4662. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id, link_id);
  4663. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4664. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4665. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4666. ts, ts->tid);
  4667. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4668. #ifdef QCA_SUPPORT_RDK_STATS
  4669. if (soc->peerstats_enabled)
  4670. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4671. qdf_ktime_to_ms(tx_desc->timestamp),
  4672. ts->ppdu_id, link_id);
  4673. #endif
  4674. out:
  4675. return;
  4676. }
  4677. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4678. defined(QCA_ENHANCED_STATS_SUPPORT)
  4679. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4680. uint32_t length, uint8_t tx_status,
  4681. bool update)
  4682. {
  4683. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4684. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4685. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4686. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4687. }
  4688. }
  4689. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4690. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4691. uint32_t length, uint8_t tx_status,
  4692. bool update)
  4693. {
  4694. if (!txrx_peer->hw_txrx_stats_en) {
  4695. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4696. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4697. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4698. }
  4699. }
  4700. #else
  4701. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4702. uint32_t length, uint8_t tx_status,
  4703. bool update)
  4704. {
  4705. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4706. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4707. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4708. }
  4709. #endif
  4710. /**
  4711. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4712. * @next: descriptor of the nrxt buffer
  4713. *
  4714. * Return: none
  4715. */
  4716. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4717. static inline
  4718. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4719. {
  4720. qdf_nbuf_t nbuf = NULL;
  4721. if (next)
  4722. nbuf = next->nbuf;
  4723. if (nbuf)
  4724. qdf_prefetch(nbuf);
  4725. }
  4726. #else
  4727. static inline
  4728. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4729. {
  4730. }
  4731. #endif
  4732. /**
  4733. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4734. * @soc: core txrx main context
  4735. * @desc: software descriptor
  4736. *
  4737. * Return: true when packet is reinjected
  4738. */
  4739. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4740. defined(WLAN_MCAST_MLO) && !defined(CONFIG_MLO_SINGLE_DEV)
  4741. static inline bool
  4742. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4743. {
  4744. struct dp_vdev *vdev = NULL;
  4745. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4746. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4747. !soc->arch_ops.dp_tx_is_mcast_primary)
  4748. return false;
  4749. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4750. DP_MOD_ID_REINJECT);
  4751. if (qdf_unlikely(!vdev)) {
  4752. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4753. desc->id);
  4754. return false;
  4755. }
  4756. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4757. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4758. return false;
  4759. }
  4760. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4761. qdf_nbuf_len(desc->nbuf));
  4762. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4763. dp_tx_desc_release(desc, desc->pool_id);
  4764. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4765. return true;
  4766. }
  4767. return false;
  4768. }
  4769. #else
  4770. static inline bool
  4771. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4772. {
  4773. return false;
  4774. }
  4775. #endif
  4776. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4777. static inline void
  4778. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4779. {
  4780. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4781. }
  4782. static inline void
  4783. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4784. struct dp_tx_desc_s *desc)
  4785. {
  4786. qdf_nbuf_t nbuf = NULL;
  4787. nbuf = desc->nbuf;
  4788. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4789. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4790. else
  4791. qdf_nbuf_free(nbuf);
  4792. }
  4793. static inline void
  4794. dp_tx_nbuf_dev_queue_free_no_flag(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4795. qdf_nbuf_t nbuf)
  4796. {
  4797. if (!nbuf)
  4798. return;
  4799. if (nbuf->is_from_recycler)
  4800. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4801. else
  4802. qdf_nbuf_free(nbuf);
  4803. }
  4804. static inline void
  4805. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4806. {
  4807. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4808. }
  4809. #else
  4810. static inline void
  4811. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4812. {
  4813. }
  4814. static inline void
  4815. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4816. struct dp_tx_desc_s *desc)
  4817. {
  4818. qdf_nbuf_free(desc->nbuf);
  4819. }
  4820. static inline void
  4821. dp_tx_nbuf_dev_queue_free_no_flag(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4822. qdf_nbuf_t nbuf)
  4823. {
  4824. qdf_nbuf_free(nbuf);
  4825. }
  4826. static inline void
  4827. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4828. {
  4829. }
  4830. #endif
  4831. void
  4832. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4833. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4834. {
  4835. struct dp_tx_desc_s *desc;
  4836. struct dp_tx_desc_s *next;
  4837. struct hal_tx_completion_status ts;
  4838. struct dp_txrx_peer *txrx_peer = NULL;
  4839. uint16_t peer_id = DP_INVALID_PEER;
  4840. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4841. qdf_nbuf_queue_head_t h;
  4842. desc = comp_head;
  4843. dp_tx_nbuf_queue_head_init(&h);
  4844. while (desc) {
  4845. next = desc->next;
  4846. dp_tx_prefetch_next_nbuf_data(next);
  4847. if (peer_id != desc->peer_id) {
  4848. if (txrx_peer)
  4849. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4850. DP_MOD_ID_TX_COMP);
  4851. peer_id = desc->peer_id;
  4852. txrx_peer =
  4853. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4854. &txrx_ref_handle,
  4855. DP_MOD_ID_TX_COMP);
  4856. }
  4857. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4858. desc = next;
  4859. continue;
  4860. }
  4861. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4862. qdf_nbuf_t nbuf;
  4863. if (qdf_likely(txrx_peer))
  4864. dp_tx_update_peer_basic_stats(txrx_peer,
  4865. desc->length,
  4866. desc->tx_status,
  4867. false);
  4868. nbuf = dp_ppeds_tx_desc_free(soc, desc);
  4869. dp_tx_nbuf_dev_queue_free_no_flag(&h, nbuf);
  4870. desc = next;
  4871. continue;
  4872. }
  4873. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4874. struct dp_pdev *pdev = desc->pdev;
  4875. if (qdf_likely(txrx_peer))
  4876. dp_tx_update_peer_basic_stats(txrx_peer,
  4877. desc->length,
  4878. desc->tx_status,
  4879. false);
  4880. qdf_assert(pdev);
  4881. dp_tx_outstanding_dec(pdev);
  4882. /*
  4883. * Calling a QDF WRAPPER here is creating significant
  4884. * performance impact so avoided the wrapper call here
  4885. */
  4886. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4887. desc->id, DP_TX_COMP_UNMAP);
  4888. dp_tx_nbuf_unmap(soc, desc);
  4889. dp_tx_nbuf_dev_queue_free(&h, desc);
  4890. dp_tx_desc_free(soc, desc, desc->pool_id);
  4891. desc = next;
  4892. continue;
  4893. }
  4894. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4895. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4896. ring_id);
  4897. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4898. dp_tx_desc_release(desc, desc->pool_id);
  4899. desc = next;
  4900. }
  4901. dp_tx_nbuf_dev_kfree_list(&h);
  4902. if (txrx_peer)
  4903. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4904. }
  4905. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4906. static inline
  4907. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4908. int max_reap_limit)
  4909. {
  4910. bool limit_hit = false;
  4911. limit_hit =
  4912. (num_reaped >= max_reap_limit) ? true : false;
  4913. if (limit_hit)
  4914. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4915. return limit_hit;
  4916. }
  4917. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4918. {
  4919. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4920. }
  4921. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4922. {
  4923. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4924. return cfg->tx_comp_loop_pkt_limit;
  4925. }
  4926. #else
  4927. static inline
  4928. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4929. int max_reap_limit)
  4930. {
  4931. return false;
  4932. }
  4933. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4934. {
  4935. return false;
  4936. }
  4937. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4938. {
  4939. return 0;
  4940. }
  4941. #endif
  4942. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4943. static inline int
  4944. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4945. int *max_reap_limit)
  4946. {
  4947. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4948. max_reap_limit);
  4949. }
  4950. #else
  4951. static inline int
  4952. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4953. int *max_reap_limit)
  4954. {
  4955. return 0;
  4956. }
  4957. #endif
  4958. #ifdef DP_TX_TRACKING
  4959. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4960. {
  4961. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4962. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4963. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4964. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4965. }
  4966. }
  4967. #endif
  4968. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4969. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4970. uint32_t quota)
  4971. {
  4972. void *tx_comp_hal_desc;
  4973. void *last_prefetched_hw_desc = NULL;
  4974. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4975. hal_soc_handle_t hal_soc;
  4976. uint8_t buffer_src;
  4977. struct dp_tx_desc_s *tx_desc = NULL;
  4978. struct dp_tx_desc_s *head_desc = NULL;
  4979. struct dp_tx_desc_s *tail_desc = NULL;
  4980. uint32_t num_processed = 0;
  4981. uint32_t count;
  4982. uint32_t num_avail_for_reap = 0;
  4983. bool force_break = false;
  4984. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4985. int max_reap_limit, ring_near_full;
  4986. uint32_t num_entries;
  4987. DP_HIST_INIT();
  4988. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  4989. more_data:
  4990. hal_soc = soc->hal_soc;
  4991. /* Re-initialize local variables to be re-used */
  4992. head_desc = NULL;
  4993. tail_desc = NULL;
  4994. count = 0;
  4995. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4996. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4997. &max_reap_limit);
  4998. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4999. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  5000. return 0;
  5001. }
  5002. if (!num_avail_for_reap)
  5003. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  5004. hal_ring_hdl, 0);
  5005. if (num_avail_for_reap >= quota)
  5006. num_avail_for_reap = quota;
  5007. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  5008. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  5009. hal_ring_hdl,
  5010. num_avail_for_reap);
  5011. /* Find head descriptor from completion ring */
  5012. while (qdf_likely(num_avail_for_reap--)) {
  5013. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  5014. if (qdf_unlikely(!tx_comp_hal_desc))
  5015. break;
  5016. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  5017. tx_comp_hal_desc);
  5018. /* If this buffer was not released by TQM or FW, then it is not
  5019. * Tx completion indication, assert */
  5020. if (qdf_unlikely(buffer_src !=
  5021. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  5022. (qdf_unlikely(buffer_src !=
  5023. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  5024. uint8_t wbm_internal_error;
  5025. dp_err_rl(
  5026. "Tx comp release_src != TQM | FW but from %d",
  5027. buffer_src);
  5028. hal_dump_comp_desc(tx_comp_hal_desc);
  5029. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  5030. /* When WBM sees NULL buffer_addr_info in any of
  5031. * ingress rings it sends an error indication,
  5032. * with wbm_internal_error=1, to a specific ring.
  5033. * The WBM2SW ring used to indicate these errors is
  5034. * fixed in HW, and that ring is being used as Tx
  5035. * completion ring. These errors are not related to
  5036. * Tx completions, and should just be ignored
  5037. */
  5038. wbm_internal_error = hal_get_wbm_internal_error(
  5039. hal_soc,
  5040. tx_comp_hal_desc);
  5041. if (wbm_internal_error) {
  5042. dp_err_rl("Tx comp wbm_internal_error!!");
  5043. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5044. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5045. buffer_src)
  5046. dp_handle_wbm_internal_error(
  5047. soc,
  5048. tx_comp_hal_desc,
  5049. hal_tx_comp_get_buffer_type(
  5050. tx_comp_hal_desc));
  5051. } else {
  5052. dp_err_rl("Tx comp wbm_internal_error false");
  5053. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5054. }
  5055. continue;
  5056. }
  5057. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5058. tx_comp_hal_desc,
  5059. &tx_desc);
  5060. if (qdf_unlikely(!tx_desc)) {
  5061. dp_err("unable to retrieve tx_desc!");
  5062. hal_dump_comp_desc(tx_comp_hal_desc);
  5063. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  5064. QDF_BUG(0);
  5065. continue;
  5066. }
  5067. tx_desc->buffer_src = buffer_src;
  5068. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5069. goto add_to_pool2;
  5070. /*
  5071. * If the release source is FW, process the HTT status
  5072. */
  5073. if (qdf_unlikely(buffer_src ==
  5074. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5075. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5076. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5077. htt_tx_status);
  5078. /* Collect hw completion contents */
  5079. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5080. &tx_desc->comp, 1);
  5081. soc->arch_ops.dp_tx_process_htt_completion(
  5082. soc,
  5083. tx_desc,
  5084. htt_tx_status,
  5085. ring_id);
  5086. } else {
  5087. tx_desc->tx_status =
  5088. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5089. tx_desc->buffer_src = buffer_src;
  5090. /*
  5091. * If the fast completion mode is enabled extended
  5092. * metadata from descriptor is not copied
  5093. */
  5094. if (qdf_likely(tx_desc->flags &
  5095. DP_TX_DESC_FLAG_SIMPLE))
  5096. goto add_to_pool;
  5097. /*
  5098. * If the descriptor is already freed in vdev_detach,
  5099. * continue to next descriptor
  5100. */
  5101. if (qdf_unlikely
  5102. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5103. !tx_desc->flags)) {
  5104. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5105. tx_desc->id);
  5106. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5107. dp_tx_desc_check_corruption(tx_desc);
  5108. continue;
  5109. }
  5110. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5111. dp_tx_comp_info_rl("pdev in down state %d",
  5112. tx_desc->id);
  5113. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5114. dp_tx_comp_free_buf(soc, tx_desc, false);
  5115. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5116. goto next_desc;
  5117. }
  5118. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5119. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5120. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5121. tx_desc->flags, tx_desc->id);
  5122. qdf_assert_always(0);
  5123. }
  5124. /* Collect hw completion contents */
  5125. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5126. &tx_desc->comp, 1);
  5127. add_to_pool:
  5128. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5129. add_to_pool2:
  5130. /* First ring descriptor on the cycle */
  5131. if (!head_desc) {
  5132. head_desc = tx_desc;
  5133. tail_desc = tx_desc;
  5134. }
  5135. tail_desc->next = tx_desc;
  5136. tx_desc->next = NULL;
  5137. tail_desc = tx_desc;
  5138. }
  5139. next_desc:
  5140. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5141. /*
  5142. * Processed packet count is more than given quota
  5143. * stop to processing
  5144. */
  5145. count++;
  5146. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5147. num_avail_for_reap,
  5148. hal_ring_hdl,
  5149. &last_prefetched_hw_desc,
  5150. &last_prefetched_sw_desc);
  5151. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5152. break;
  5153. }
  5154. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5155. /* Process the reaped descriptors */
  5156. if (head_desc)
  5157. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5158. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5159. /*
  5160. * If we are processing in near-full condition, there are 3 scenario
  5161. * 1) Ring entries has reached critical state
  5162. * 2) Ring entries are still near high threshold
  5163. * 3) Ring entries are below the safe level
  5164. *
  5165. * One more loop will move the state to normal processing and yield
  5166. */
  5167. if (ring_near_full)
  5168. goto more_data;
  5169. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5170. if (num_processed >= quota)
  5171. force_break = true;
  5172. if (!force_break &&
  5173. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5174. hal_ring_hdl)) {
  5175. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5176. if (!hif_exec_should_yield(soc->hif_handle,
  5177. int_ctx->dp_intr_id))
  5178. goto more_data;
  5179. num_avail_for_reap =
  5180. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5181. hal_ring_hdl,
  5182. true);
  5183. if (qdf_unlikely(num_entries &&
  5184. (num_avail_for_reap >=
  5185. num_entries >> 1))) {
  5186. DP_STATS_INC(soc, tx.near_full, 1);
  5187. goto more_data;
  5188. }
  5189. }
  5190. }
  5191. DP_TX_HIST_STATS_PER_PDEV();
  5192. return num_processed;
  5193. }
  5194. #ifdef FEATURE_WLAN_TDLS
  5195. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5196. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5197. {
  5198. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5199. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5200. DP_MOD_ID_TDLS);
  5201. if (!vdev) {
  5202. dp_err("vdev handle for id %d is NULL", vdev_id);
  5203. return NULL;
  5204. }
  5205. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5206. vdev->is_tdls_frame = true;
  5207. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5208. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5209. }
  5210. #endif
  5211. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5212. {
  5213. int pdev_id;
  5214. /*
  5215. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5216. */
  5217. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5218. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5219. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5220. vdev->vdev_id);
  5221. pdev_id =
  5222. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5223. vdev->pdev->pdev_id);
  5224. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5225. /*
  5226. * Set HTT Extension Valid bit to 0 by default
  5227. */
  5228. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5229. dp_tx_vdev_update_search_flags(vdev);
  5230. return QDF_STATUS_SUCCESS;
  5231. }
  5232. #ifndef FEATURE_WDS
  5233. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5234. {
  5235. return false;
  5236. }
  5237. #endif
  5238. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5239. {
  5240. struct dp_soc *soc = vdev->pdev->soc;
  5241. /*
  5242. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5243. * for TDLS link
  5244. *
  5245. * Enable AddrY (SA based search) only for non-WDS STA and
  5246. * ProxySTA VAP (in HKv1) modes.
  5247. *
  5248. * In all other VAP modes, only DA based search should be
  5249. * enabled
  5250. */
  5251. if (vdev->opmode == wlan_op_mode_sta &&
  5252. vdev->tdls_link_connected)
  5253. vdev->hal_desc_addr_search_flags =
  5254. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5255. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5256. !dp_tx_da_search_override(vdev))
  5257. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5258. else
  5259. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5260. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5261. vdev->search_type = soc->sta_mode_search_policy;
  5262. else
  5263. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5264. }
  5265. static inline bool
  5266. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5267. struct dp_vdev *vdev,
  5268. struct dp_tx_desc_s *tx_desc)
  5269. {
  5270. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5271. return false;
  5272. /*
  5273. * if vdev is given, then only check whether desc
  5274. * vdev match. if vdev is NULL, then check whether
  5275. * desc pdev match.
  5276. */
  5277. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5278. (tx_desc->pdev == pdev);
  5279. }
  5280. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5281. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5282. bool force_free)
  5283. {
  5284. uint8_t i;
  5285. uint32_t j;
  5286. uint32_t num_desc, page_id, offset;
  5287. uint16_t num_desc_per_page;
  5288. struct dp_soc *soc = pdev->soc;
  5289. struct dp_tx_desc_s *tx_desc = NULL;
  5290. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5291. if (!vdev && !force_free) {
  5292. dp_err("Reset TX desc vdev, Vdev param is required!");
  5293. return;
  5294. }
  5295. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5296. tx_desc_pool = &soc->tx_desc[i];
  5297. if (!(tx_desc_pool->pool_size) ||
  5298. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5299. !(tx_desc_pool->desc_pages.cacheable_pages))
  5300. continue;
  5301. /*
  5302. * Add flow pool lock protection in case pool is freed
  5303. * due to all tx_desc is recycled when handle TX completion.
  5304. * this is not necessary when do force flush as:
  5305. * a. double lock will happen if dp_tx_desc_release is
  5306. * also trying to acquire it.
  5307. * b. dp interrupt has been disabled before do force TX desc
  5308. * flush in dp_pdev_deinit().
  5309. */
  5310. if (!force_free)
  5311. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5312. num_desc = tx_desc_pool->pool_size;
  5313. num_desc_per_page =
  5314. tx_desc_pool->desc_pages.num_element_per_page;
  5315. for (j = 0; j < num_desc; j++) {
  5316. page_id = j / num_desc_per_page;
  5317. offset = j % num_desc_per_page;
  5318. if (qdf_unlikely(!(tx_desc_pool->
  5319. desc_pages.cacheable_pages)))
  5320. break;
  5321. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5322. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5323. /*
  5324. * Free TX desc if force free is
  5325. * required, otherwise only reset vdev
  5326. * in this TX desc.
  5327. */
  5328. if (force_free) {
  5329. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5330. dp_tx_comp_free_buf(soc, tx_desc,
  5331. false);
  5332. dp_tx_desc_release(tx_desc, i);
  5333. } else {
  5334. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5335. }
  5336. }
  5337. }
  5338. if (!force_free)
  5339. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5340. }
  5341. }
  5342. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5343. /**
  5344. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5345. *
  5346. * @soc: Handle to DP soc structure
  5347. * @tx_desc: pointer of one TX desc
  5348. * @desc_pool_id: TX Desc pool id
  5349. */
  5350. static inline void
  5351. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5352. uint8_t desc_pool_id)
  5353. {
  5354. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5355. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5356. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5357. }
  5358. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5359. bool force_free)
  5360. {
  5361. uint8_t i, num_pool;
  5362. uint32_t j;
  5363. uint32_t num_desc, page_id, offset;
  5364. uint16_t num_desc_per_page;
  5365. struct dp_soc *soc = pdev->soc;
  5366. struct dp_tx_desc_s *tx_desc = NULL;
  5367. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5368. if (!vdev && !force_free) {
  5369. dp_err("Reset TX desc vdev, Vdev param is required!");
  5370. return;
  5371. }
  5372. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5373. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5374. for (i = 0; i < num_pool; i++) {
  5375. tx_desc_pool = &soc->tx_desc[i];
  5376. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5377. continue;
  5378. num_desc_per_page =
  5379. tx_desc_pool->desc_pages.num_element_per_page;
  5380. for (j = 0; j < num_desc; j++) {
  5381. page_id = j / num_desc_per_page;
  5382. offset = j % num_desc_per_page;
  5383. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5384. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5385. if (force_free) {
  5386. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5387. dp_tx_comp_free_buf(soc, tx_desc,
  5388. false);
  5389. dp_tx_desc_release(tx_desc, i);
  5390. } else {
  5391. dp_tx_desc_reset_vdev(soc, tx_desc,
  5392. i);
  5393. }
  5394. }
  5395. }
  5396. }
  5397. }
  5398. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5399. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5400. {
  5401. struct dp_pdev *pdev = vdev->pdev;
  5402. /* Reset TX desc associated to this Vdev as NULL */
  5403. dp_tx_desc_flush(pdev, vdev, false);
  5404. return QDF_STATUS_SUCCESS;
  5405. }
  5406. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5407. /* Pools will be allocated dynamically */
  5408. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5409. int num_desc)
  5410. {
  5411. uint8_t i;
  5412. for (i = 0; i < num_pool; i++) {
  5413. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5414. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5415. }
  5416. return QDF_STATUS_SUCCESS;
  5417. }
  5418. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5419. uint32_t num_desc)
  5420. {
  5421. return QDF_STATUS_SUCCESS;
  5422. }
  5423. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5424. {
  5425. }
  5426. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5427. {
  5428. uint8_t i;
  5429. for (i = 0; i < num_pool; i++)
  5430. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5431. }
  5432. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5433. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5434. uint32_t num_desc)
  5435. {
  5436. uint8_t i, count;
  5437. /* Allocate software Tx descriptor pools */
  5438. for (i = 0; i < num_pool; i++) {
  5439. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5440. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5441. FL("Tx Desc Pool alloc %d failed %pK"),
  5442. i, soc);
  5443. goto fail;
  5444. }
  5445. }
  5446. return QDF_STATUS_SUCCESS;
  5447. fail:
  5448. for (count = 0; count < i; count++)
  5449. dp_tx_desc_pool_free(soc, count);
  5450. return QDF_STATUS_E_NOMEM;
  5451. }
  5452. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5453. uint32_t num_desc)
  5454. {
  5455. uint8_t i;
  5456. for (i = 0; i < num_pool; i++) {
  5457. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5458. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5459. FL("Tx Desc Pool init %d failed %pK"),
  5460. i, soc);
  5461. return QDF_STATUS_E_NOMEM;
  5462. }
  5463. }
  5464. return QDF_STATUS_SUCCESS;
  5465. }
  5466. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5467. {
  5468. uint8_t i;
  5469. for (i = 0; i < num_pool; i++)
  5470. dp_tx_desc_pool_deinit(soc, i);
  5471. }
  5472. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5473. {
  5474. uint8_t i;
  5475. for (i = 0; i < num_pool; i++)
  5476. dp_tx_desc_pool_free(soc, i);
  5477. }
  5478. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5479. /**
  5480. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5481. * @soc: core txrx main context
  5482. * @num_pool: number of pools
  5483. *
  5484. */
  5485. static void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5486. {
  5487. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5488. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5489. }
  5490. /**
  5491. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5492. * @soc: core txrx main context
  5493. * @num_pool: number of pools
  5494. *
  5495. */
  5496. static void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5497. {
  5498. dp_tx_tso_desc_pool_free(soc, num_pool);
  5499. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5500. }
  5501. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5502. {
  5503. uint8_t num_pool;
  5504. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5505. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5506. dp_tx_ext_desc_pool_free(soc, num_pool);
  5507. dp_tx_delete_static_pools(soc, num_pool);
  5508. }
  5509. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5510. {
  5511. uint8_t num_pool;
  5512. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5513. dp_tx_flow_control_deinit(soc);
  5514. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5515. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5516. dp_tx_deinit_static_pools(soc, num_pool);
  5517. }
  5518. /**
  5519. * dp_tx_tso_cmn_desc_pool_alloc() - TSO cmn desc pool allocator
  5520. * @soc: DP soc handle
  5521. * @num_pool: Number of pools
  5522. * @num_desc: Number of descriptors
  5523. *
  5524. * Reserve TSO descriptor buffers
  5525. *
  5526. * Return: QDF_STATUS_E_FAILURE on failure or
  5527. * QDF_STATUS_SUCCESS on success
  5528. */
  5529. static QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5530. uint8_t num_pool,
  5531. uint32_t num_desc)
  5532. {
  5533. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5534. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5535. return QDF_STATUS_E_FAILURE;
  5536. }
  5537. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5538. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5539. num_pool, soc);
  5540. return QDF_STATUS_E_FAILURE;
  5541. }
  5542. return QDF_STATUS_SUCCESS;
  5543. }
  5544. /**
  5545. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5546. * @soc: DP soc handle
  5547. * @num_pool: Number of pools
  5548. * @num_desc: Number of descriptors
  5549. *
  5550. * Initialize TSO descriptor pools
  5551. *
  5552. * Return: QDF_STATUS_E_FAILURE on failure or
  5553. * QDF_STATUS_SUCCESS on success
  5554. */
  5555. static QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5556. uint8_t num_pool,
  5557. uint32_t num_desc)
  5558. {
  5559. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5560. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5561. return QDF_STATUS_E_FAILURE;
  5562. }
  5563. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5564. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5565. num_pool, soc);
  5566. return QDF_STATUS_E_FAILURE;
  5567. }
  5568. return QDF_STATUS_SUCCESS;
  5569. }
  5570. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5571. {
  5572. uint8_t num_pool;
  5573. uint32_t num_desc;
  5574. uint32_t num_ext_desc;
  5575. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5576. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5577. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5578. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5579. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5580. __func__, num_pool, num_desc);
  5581. if ((num_pool > MAX_TXDESC_POOLS) ||
  5582. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5583. goto fail1;
  5584. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5585. goto fail1;
  5586. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5587. goto fail2;
  5588. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5589. return QDF_STATUS_SUCCESS;
  5590. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5591. goto fail3;
  5592. return QDF_STATUS_SUCCESS;
  5593. fail3:
  5594. dp_tx_ext_desc_pool_free(soc, num_pool);
  5595. fail2:
  5596. dp_tx_delete_static_pools(soc, num_pool);
  5597. fail1:
  5598. return QDF_STATUS_E_RESOURCES;
  5599. }
  5600. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5601. {
  5602. uint8_t num_pool;
  5603. uint32_t num_desc;
  5604. uint32_t num_ext_desc;
  5605. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5606. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5607. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5608. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5609. goto fail1;
  5610. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5611. goto fail2;
  5612. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5613. return QDF_STATUS_SUCCESS;
  5614. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5615. goto fail3;
  5616. dp_tx_flow_control_init(soc);
  5617. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5618. return QDF_STATUS_SUCCESS;
  5619. fail3:
  5620. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5621. fail2:
  5622. dp_tx_deinit_static_pools(soc, num_pool);
  5623. fail1:
  5624. return QDF_STATUS_E_RESOURCES;
  5625. }
  5626. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5627. {
  5628. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5629. uint8_t num_pool;
  5630. uint32_t num_ext_desc;
  5631. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5632. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5633. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5634. return QDF_STATUS_E_FAILURE;
  5635. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5636. return QDF_STATUS_E_FAILURE;
  5637. return QDF_STATUS_SUCCESS;
  5638. }
  5639. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5640. {
  5641. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5642. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5643. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5644. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5645. return QDF_STATUS_SUCCESS;
  5646. }
  5647. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5648. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5649. enum qdf_pkt_timestamp_index index, uint64_t time,
  5650. qdf_nbuf_t nbuf)
  5651. {
  5652. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5653. uint64_t tsf_time;
  5654. if (vdev->get_tsf_time) {
  5655. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5656. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5657. }
  5658. }
  5659. }
  5660. void dp_pkt_get_timestamp(uint64_t *time)
  5661. {
  5662. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5663. *time = qdf_get_log_timestamp();
  5664. }
  5665. #endif