wsa884x.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/device.h>
  11. #include <linux/printk.h>
  12. #include <linux/bitops.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/regmap.h>
  21. #include <linux/debugfs.h>
  22. #include <soc/soundwire.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/tlv.h>
  28. #include <asoc/msm-cdc-pinctrl.h>
  29. #include <asoc/msm-cdc-supply.h>
  30. #include "wsa884x-registers.h"
  31. #include "wsa884x.h"
  32. #include "internal.h"
  33. #include "asoc/bolero-slave-internal.h"
  34. #include <linux/qti-regmap-debugfs.h>
  35. #define T1_TEMP -10
  36. #define T2_TEMP 150
  37. #define LOW_TEMP_THRESHOLD 5
  38. #define HIGH_TEMP_THRESHOLD 45
  39. #define TEMP_INVALID 0xFFFF
  40. #define WSA884X_TEMP_RETRY 3
  41. #define WSA884X_IRQ_RETRY 2
  42. #define PBR_MAX_VOLTAGE 20
  43. #define PBR_MAX_CODE 255
  44. #define WSA884X_IDLE_DETECT_NG_BLOCK_MASK 0x38
  45. #define MAX_NAME_LEN 40
  46. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  47. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  48. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  49. SNDRV_PCM_RATE_384000)
  50. /* Fractional Rates */
  51. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  52. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  53. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  54. SNDRV_PCM_FMTBIT_S24_LE |\
  55. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  56. #define REG_FIELD_VALUE(register_name, field_name, value) \
  57. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  58. value << FIELD_SHIFT(register_name, field_name)
  59. enum {
  60. IDLE_DETECT,
  61. NG1,
  62. NG2,
  63. NG3,
  64. };
  65. struct wsa_temp_register {
  66. u8 d1_msb;
  67. u8 d1_lsb;
  68. u8 d2_msb;
  69. u8 d2_lsb;
  70. u8 dmeas_msb;
  71. u8 dmeas_lsb;
  72. };
  73. enum {
  74. COMP_OFFSET0,
  75. COMP_OFFSET1,
  76. COMP_OFFSET2,
  77. COMP_OFFSET3,
  78. COMP_OFFSET4,
  79. };
  80. #define WSA884X_VTH_TO_REG(vth) \
  81. ((vth) != 0 ? (((vth) - 150) * PBR_MAX_CODE / (PBR_MAX_VOLTAGE * 100) + 1) : 0)
  82. struct wsa_reg_mask_val {
  83. u16 reg;
  84. u8 mask;
  85. u8 val;
  86. };
  87. static const struct wsa_reg_mask_val reg_init[] = {
  88. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  89. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  90. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  91. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  92. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  93. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  94. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  95. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  96. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  97. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  98. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  99. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  100. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  101. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  102. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  103. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  104. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  105. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  106. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  107. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  108. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  109. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  110. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  111. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  112. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  113. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  114. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  115. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  116. {REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
  117. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  118. {REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
  119. {REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
  120. {REG_FIELD_VALUE(VBAT_CAL_CTL, RESERVE, 0x02)},
  121. {REG_FIELD_VALUE(REF_CTRL, BG_RDY_SEL, 0x01)},
  122. {REG_FIELD_VALUE(ZX_CTRL1, ZX_DET_SW_SEL, 0x03)},
  123. };
  124. static const struct wsa_reg_mask_val reg_init_2S[] = {
  125. {REG_FIELD_VALUE(CLSH_CTL_1, SLR_MAX, 0x02)},
  126. {REG_FIELD_VALUE(CLSH_V_HD_PA, V_HD_PA, 0x13)},
  127. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_VTH, 0x03)},
  128. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_HYST, 0x03)},
  129. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG2, DAC_VCM_SHIFT, 0x06)},
  130. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG3, DAC_VCM_SHIFT, 0x14)},
  131. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG4, DAC_VCM_SHIFT, 0x19)},
  132. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG5, DAC_VCM_SHIFT, 0x1B)},
  133. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG6, DAC_VCM_SHIFT, 0x1C)},
  134. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG7, DAC_VCM_SHIFT_FINAL_OVERRIDE, 0x01)},
  135. };
  136. static int wsa884x_handle_post_irq(void *data);
  137. static int wsa884x_get_temperature(struct snd_soc_component *component,
  138. int *temp);
  139. enum {
  140. WSA8840 = 0,
  141. WSA8845 = 5,
  142. WSA8845H = 0xC,
  143. };
  144. enum {
  145. SPKR_STATUS = 0,
  146. WSA_SUPPLIES_LPM_MODE,
  147. SPKR_ADIE_LB,
  148. };
  149. enum {
  150. WSA884X_IRQ_INT_SAF2WAR = 0,
  151. WSA884X_IRQ_INT_WAR2SAF,
  152. WSA884X_IRQ_INT_DISABLE,
  153. WSA884X_IRQ_INT_OCP,
  154. WSA884X_IRQ_INT_CLIP,
  155. WSA884X_IRQ_INT_PDM_WD,
  156. WSA884X_IRQ_INT_CLK_WD,
  157. WSA884X_IRQ_INT_INTR_PIN,
  158. WSA884X_IRQ_INT_UVLO,
  159. WSA884X_IRQ_INT_PA_ON_ERR,
  160. WSA884X_NUM_IRQS,
  161. };
  162. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  163. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  164. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  165. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  166. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  167. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  168. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  169. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  170. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  171. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  172. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  173. };
  174. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  175. .name = "wsa884x",
  176. .irqs = wsa884x_irqs,
  177. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  178. .num_regs = 2,
  179. .status_base = WSA884X_INTR_STATUS0,
  180. .mask_base = WSA884X_INTR_MASK0,
  181. .type_base = WSA884X_INTR_LEVEL0,
  182. .ack_base = WSA884X_INTR_CLEAR0,
  183. .use_ack = 1,
  184. .runtime_pm = false,
  185. .handle_post_irq = wsa884x_handle_post_irq,
  186. .irq_drv_data = NULL,
  187. };
  188. static int wsa884x_handle_post_irq(void *data)
  189. {
  190. struct wsa884x_priv *wsa884x = data;
  191. u32 sts1 = 0, sts2 = 0;
  192. int retry = WSA884X_IRQ_RETRY;
  193. if (!wsa884x)
  194. return IRQ_NONE;
  195. if (!wsa884x->pa_mute) {
  196. do {
  197. wsa884x->pa_mute = 0;
  198. regmap_update_bits(wsa884x->regmap,
  199. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  200. usleep_range(1000, 1100);
  201. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  202. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  203. wsa884x->swr_slave->slave_irq_pending =
  204. ((sts1 || sts2) ? true : false);
  205. pr_debug("%s: IRQs Sts0: %x, Sts1: %x\n", __func__,
  206. sts1, sts2);
  207. if (wsa884x->swr_slave->slave_irq_pending) {
  208. pr_debug("%s: IRQ retries left: %0d\n",
  209. __func__, retry);
  210. regmap_update_bits(wsa884x->regmap,
  211. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  212. wsa884x->pa_mute = 1;
  213. if (retry--)
  214. usleep_range(1000, 1100);
  215. } else {
  216. break;
  217. }
  218. } while (retry);
  219. }
  220. return IRQ_HANDLED;
  221. }
  222. #ifdef CONFIG_DEBUG_FS
  223. static int codec_debug_open(struct inode *inode, struct file *file)
  224. {
  225. file->private_data = inode->i_private;
  226. return 0;
  227. }
  228. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  229. {
  230. char *token;
  231. int base, cnt;
  232. token = strsep(&buf, " ");
  233. for (cnt = 0; cnt < num_of_par; cnt++) {
  234. if (token) {
  235. if ((token[1] == 'x') || (token[1] == 'X'))
  236. base = 16;
  237. else
  238. base = 10;
  239. if (kstrtou32(token, base, &param1[cnt]) != 0)
  240. return -EINVAL;
  241. token = strsep(&buf, " ");
  242. } else {
  243. return -EINVAL;
  244. }
  245. }
  246. return 0;
  247. }
  248. static bool is_swr_slave_reg_readable(int reg)
  249. {
  250. int ret = true;
  251. if (((reg > 0x46) && (reg < 0x4A)) ||
  252. ((reg > 0x4A) && (reg < 0x50)) ||
  253. ((reg > 0x55) && (reg < 0x60)) ||
  254. ((reg > 0x60) && (reg < 0x70)) ||
  255. ((reg > 0x70) && (reg < 0xC0)) ||
  256. ((reg > 0xC1) && (reg < 0xC8)) ||
  257. ((reg > 0xC8) && (reg < 0xD0)) ||
  258. ((reg > 0xD0) && (reg < 0xE0)) ||
  259. ((reg > 0xE0) && (reg < 0xF0)) ||
  260. ((reg > 0xF0) && (reg < 0x100)) ||
  261. ((reg > 0x105) && (reg < 0x120)) ||
  262. ((reg > 0x205) && (reg < 0x220)) ||
  263. ((reg > 0x305) && (reg < 0x320)) ||
  264. ((reg > 0x405) && (reg < 0x420)) ||
  265. ((reg > 0x505) && (reg < 0x520)) ||
  266. ((reg > 0x605) && (reg < 0x620)) ||
  267. ((reg > 0x127) && (reg < 0x130)) ||
  268. ((reg > 0x227) && (reg < 0x230)) ||
  269. ((reg > 0x327) && (reg < 0x330)) ||
  270. ((reg > 0x427) && (reg < 0x430)) ||
  271. ((reg > 0x527) && (reg < 0x530)) ||
  272. ((reg > 0x627) && (reg < 0x630)) ||
  273. ((reg > 0x137) && (reg < 0x200)) ||
  274. ((reg > 0x237) && (reg < 0x300)) ||
  275. ((reg > 0x337) && (reg < 0x400)) ||
  276. ((reg > 0x437) && (reg < 0x500)) ||
  277. ((reg > 0x537) && (reg < 0x600)) ||
  278. ((reg > 0x637) && (reg < 0xF00)) ||
  279. ((reg > 0xF05) && (reg < 0xF20)) ||
  280. ((reg > 0xF25) && (reg < 0xF30)) ||
  281. ((reg > 0xF35) && (reg < 0x2000)))
  282. ret = false;
  283. return ret;
  284. }
  285. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  286. size_t count, loff_t *ppos)
  287. {
  288. int i, reg_val, len;
  289. ssize_t total = 0;
  290. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  291. if (!ubuf || !ppos)
  292. return 0;
  293. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  294. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  295. if (!is_swr_slave_reg_readable(i))
  296. continue;
  297. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  298. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  299. (reg_val & 0xFF));
  300. if (len < 0) {
  301. pr_err_ratelimited("%s: fail to fill the buffer\n", __func__);
  302. total = -EFAULT;
  303. goto copy_err;
  304. }
  305. if ((total + len) >= count - 1)
  306. break;
  307. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  308. pr_err_ratelimited("%s: fail to copy reg dump\n", __func__);
  309. total = -EFAULT;
  310. goto copy_err;
  311. }
  312. total += len;
  313. *ppos += len;
  314. }
  315. copy_err:
  316. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  317. return total;
  318. }
  319. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  320. size_t count, loff_t *ppos)
  321. {
  322. struct swr_device *pdev;
  323. if (!count || !file || !ppos || !ubuf)
  324. return -EINVAL;
  325. pdev = file->private_data;
  326. if (!pdev)
  327. return -EINVAL;
  328. if (*ppos < 0)
  329. return -EINVAL;
  330. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  331. }
  332. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  333. size_t count, loff_t *ppos)
  334. {
  335. char lbuf[SWR_SLV_RD_BUF_LEN];
  336. struct swr_device *pdev = NULL;
  337. struct wsa884x_priv *wsa884x = NULL;
  338. if (!count || !file || !ppos || !ubuf)
  339. return -EINVAL;
  340. pdev = file->private_data;
  341. if (!pdev)
  342. return -EINVAL;
  343. wsa884x = swr_get_dev_data(pdev);
  344. if (!wsa884x)
  345. return -EINVAL;
  346. if (*ppos < 0)
  347. return -EINVAL;
  348. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  349. (wsa884x->read_data & 0xFF));
  350. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  351. strnlen(lbuf, 7));
  352. }
  353. static ssize_t codec_debug_peek_write(struct file *file,
  354. const char __user *ubuf, size_t cnt, loff_t *ppos)
  355. {
  356. char lbuf[SWR_SLV_WR_BUF_LEN];
  357. int rc = 0;
  358. u32 param[5];
  359. struct swr_device *pdev = NULL;
  360. struct wsa884x_priv *wsa884x = NULL;
  361. if (!cnt || !file || !ppos || !ubuf)
  362. return -EINVAL;
  363. pdev = file->private_data;
  364. if (!pdev)
  365. return -EINVAL;
  366. wsa884x = swr_get_dev_data(pdev);
  367. if (!wsa884x)
  368. return -EINVAL;
  369. if (*ppos < 0)
  370. return -EINVAL;
  371. if (cnt > sizeof(lbuf) - 1)
  372. return -EINVAL;
  373. rc = copy_from_user(lbuf, ubuf, cnt);
  374. if (rc)
  375. return -EFAULT;
  376. lbuf[cnt] = '\0';
  377. rc = get_parameters(lbuf, param, 1);
  378. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  379. return -EINVAL;
  380. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  381. if (rc == 0)
  382. rc = cnt;
  383. else
  384. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  385. return rc;
  386. }
  387. static ssize_t codec_debug_write(struct file *file,
  388. const char __user *ubuf, size_t cnt, loff_t *ppos)
  389. {
  390. char lbuf[SWR_SLV_WR_BUF_LEN];
  391. int rc = 0;
  392. u32 param[5];
  393. struct swr_device *pdev;
  394. if (!file || !ppos || !ubuf)
  395. return -EINVAL;
  396. pdev = file->private_data;
  397. if (!pdev)
  398. return -EINVAL;
  399. if (cnt > sizeof(lbuf) - 1)
  400. return -EINVAL;
  401. rc = copy_from_user(lbuf, ubuf, cnt);
  402. if (rc)
  403. return -EFAULT;
  404. lbuf[cnt] = '\0';
  405. rc = get_parameters(lbuf, param, 2);
  406. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  407. (param[1] <= 0xFF) && (rc == 0)))
  408. return -EINVAL;
  409. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  410. if (rc == 0)
  411. rc = cnt;
  412. else
  413. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  414. return rc;
  415. }
  416. static const struct file_operations codec_debug_write_ops = {
  417. .open = codec_debug_open,
  418. .write = codec_debug_write,
  419. };
  420. static const struct file_operations codec_debug_read_ops = {
  421. .open = codec_debug_open,
  422. .read = codec_debug_read,
  423. .write = codec_debug_peek_write,
  424. };
  425. static const struct file_operations codec_debug_dump_ops = {
  426. .open = codec_debug_open,
  427. .read = codec_debug_dump,
  428. };
  429. #endif
  430. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  431. {
  432. mutex_lock(&wsa884x->res_lock);
  433. regcache_mark_dirty(wsa884x->regmap);
  434. regcache_sync(wsa884x->regmap);
  435. mutex_unlock(&wsa884x->res_lock);
  436. }
  437. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  438. {
  439. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  440. __func__, irq);
  441. return IRQ_HANDLED;
  442. }
  443. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  444. {
  445. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  446. __func__, irq);
  447. return IRQ_HANDLED;
  448. }
  449. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  450. {
  451. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  452. __func__, irq);
  453. return IRQ_HANDLED;
  454. }
  455. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  456. {
  457. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  458. __func__, irq);
  459. return IRQ_HANDLED;
  460. }
  461. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  462. {
  463. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  464. __func__, irq);
  465. return IRQ_HANDLED;
  466. }
  467. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  468. {
  469. struct wsa884x_priv *wsa884x = data;
  470. struct snd_soc_component *component = NULL;
  471. if (!wsa884x)
  472. return IRQ_NONE;
  473. component = wsa884x->component;
  474. snd_soc_component_update_bits(component,
  475. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  476. snd_soc_component_update_bits(component,
  477. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  478. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  479. __func__, irq);
  480. return IRQ_HANDLED;
  481. }
  482. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  483. {
  484. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  485. __func__, irq);
  486. return IRQ_HANDLED;
  487. }
  488. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  489. {
  490. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  491. __func__, irq);
  492. return IRQ_HANDLED;
  493. }
  494. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  495. {
  496. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  497. __func__, irq);
  498. return IRQ_HANDLED;
  499. }
  500. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  501. {
  502. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  503. struct wsa884x_priv *wsa884x = data;
  504. struct snd_soc_component *component = NULL;
  505. if (!wsa884x)
  506. return IRQ_NONE;
  507. component = wsa884x->component;
  508. if (!component)
  509. return IRQ_NONE;
  510. snd_soc_component_update_bits(component,
  511. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  512. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  513. & 0x1F);
  514. if (pa_fsm_sta)
  515. pa_fsm_err = snd_soc_component_read(component,
  516. WSA884X_PA_FSM_ERR_COND0);
  517. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  518. __func__, irq);
  519. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  520. 0x10, 0x00);
  521. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  522. 0x10, 0x10);
  523. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  524. 0x10, 0x00);
  525. return IRQ_HANDLED;
  526. }
  527. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  528. {
  529. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  530. u8 igain;
  531. u8 vgain;
  532. switch (wsa884x->bat_cfg) {
  533. case CONFIG_1S:
  534. case EXT_1S:
  535. switch (wsa884x->system_gain) {
  536. case G_21_DB:
  537. wsa884x->comp_offset = COMP_OFFSET0;
  538. wsa884x->min_gain = G_0_DB;
  539. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  540. break;
  541. case G_19P5_DB:
  542. wsa884x->comp_offset = COMP_OFFSET1;
  543. wsa884x->min_gain = G_M1P5_DB;
  544. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  545. break;
  546. case G_18_DB:
  547. wsa884x->comp_offset = COMP_OFFSET2;
  548. wsa884x->min_gain = G_M3_DB;
  549. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  550. break;
  551. case G_16P5_DB:
  552. wsa884x->comp_offset = COMP_OFFSET3;
  553. wsa884x->min_gain = G_M4P5_DB;
  554. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  555. break;
  556. default:
  557. wsa884x->comp_offset = COMP_OFFSET4;
  558. wsa884x->min_gain = G_M6_DB;
  559. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  560. break;
  561. }
  562. break;
  563. case CONFIG_3S:
  564. case EXT_3S:
  565. wsa884x->comp_offset = COMP_OFFSET0;
  566. wsa884x->min_gain = G_7P5_DB;
  567. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  568. break;
  569. case EXT_ABOVE_3S:
  570. wsa884x->comp_offset = COMP_OFFSET0;
  571. wsa884x->min_gain = G_12_DB;
  572. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  573. break;
  574. default:
  575. wsa884x->comp_offset = COMP_OFFSET0;
  576. wsa884x->min_gain = G_0_DB;
  577. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  578. break;
  579. }
  580. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  581. vgain = vsense_gain_data[wsa884x->system_gain];
  582. snd_soc_component_update_bits(component,
  583. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  584. snd_soc_component_update_bits(component,
  585. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  586. snd_soc_component_update_bits(component,
  587. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  588. if (wsa884x->comp_enable) {
  589. snd_soc_component_update_bits(component,
  590. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  591. wsa884x->comp_offset));
  592. snd_soc_component_update_bits(component,
  593. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  594. } else {
  595. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->pa_gain];
  596. snd_soc_component_update_bits(component,
  597. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  598. snd_soc_component_update_bits(component,
  599. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, wsa884x->pa_gain));
  600. }
  601. return 0;
  602. }
  603. static int wsa884x_set_pbr_parameters(struct snd_soc_component *component)
  604. {
  605. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  606. int vth1_reg_val;
  607. int vth2_reg_val;
  608. int vth3_reg_val;
  609. int vth4_reg_val;
  610. int vth5_reg_val;
  611. int vth6_reg_val;
  612. int vth7_reg_val;
  613. int vth8_reg_val;
  614. int vth9_reg_val;
  615. int vth10_reg_val;
  616. int vth11_reg_val;
  617. int vth12_reg_val;
  618. int vth13_reg_val;
  619. int vth14_reg_val;
  620. int vth15_reg_val;
  621. int vth1_val = pbr_vth1_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  622. int vth2_val = pbr_vth2_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  623. int vth3_val = pbr_vth3_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  624. int vth4_val = pbr_vth4_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  625. int vth5_val = pbr_vth5_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  626. int vth6_val = pbr_vth6_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  627. int vth7_val = pbr_vth7_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  628. int vth8_val = pbr_vth8_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  629. int vth9_val = pbr_vth9_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  630. int vth10_val = pbr_vth10_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  631. int vth11_val = pbr_vth11_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  632. int vth12_val = pbr_vth12_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  633. int vth13_val = pbr_vth13_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  634. int vth14_val = pbr_vth14_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  635. int vth15_val = pbr_vth15_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  636. vth1_reg_val = WSA884X_VTH_TO_REG(vth1_val);
  637. vth2_reg_val = WSA884X_VTH_TO_REG(vth2_val);
  638. vth3_reg_val = WSA884X_VTH_TO_REG(vth3_val);
  639. vth4_reg_val = WSA884X_VTH_TO_REG(vth4_val);
  640. vth5_reg_val = WSA884X_VTH_TO_REG(vth5_val);
  641. vth6_reg_val = WSA884X_VTH_TO_REG(vth6_val);
  642. vth7_reg_val = WSA884X_VTH_TO_REG(vth7_val);
  643. vth8_reg_val = WSA884X_VTH_TO_REG(vth8_val);
  644. vth9_reg_val = WSA884X_VTH_TO_REG(vth9_val);
  645. vth10_reg_val = WSA884X_VTH_TO_REG(vth10_val);
  646. vth11_reg_val = WSA884X_VTH_TO_REG(vth11_val);
  647. vth12_reg_val = WSA884X_VTH_TO_REG(vth12_val);
  648. vth13_reg_val = WSA884X_VTH_TO_REG(vth13_val);
  649. vth14_reg_val = WSA884X_VTH_TO_REG(vth14_val);
  650. vth15_reg_val = WSA884X_VTH_TO_REG(vth15_val);
  651. snd_soc_component_write(component, WSA884X_CLSH_VTH1, vth1_reg_val);
  652. snd_soc_component_write(component, WSA884X_CLSH_VTH2, vth2_reg_val);
  653. snd_soc_component_write(component, WSA884X_CLSH_VTH3, vth3_reg_val);
  654. snd_soc_component_write(component, WSA884X_CLSH_VTH4, vth4_reg_val);
  655. snd_soc_component_write(component, WSA884X_CLSH_VTH5, vth5_reg_val);
  656. snd_soc_component_write(component, WSA884X_CLSH_VTH6, vth6_reg_val);
  657. snd_soc_component_write(component, WSA884X_CLSH_VTH7, vth7_reg_val);
  658. snd_soc_component_write(component, WSA884X_CLSH_VTH8, vth8_reg_val);
  659. snd_soc_component_write(component, WSA884X_CLSH_VTH9, vth9_reg_val);
  660. snd_soc_component_write(component, WSA884X_CLSH_VTH10, vth10_reg_val);
  661. snd_soc_component_write(component, WSA884X_CLSH_VTH11, vth11_reg_val);
  662. snd_soc_component_write(component, WSA884X_CLSH_VTH12, vth12_reg_val);
  663. snd_soc_component_write(component, WSA884X_CLSH_VTH13, vth13_reg_val);
  664. snd_soc_component_write(component, WSA884X_CLSH_VTH14, vth14_reg_val);
  665. snd_soc_component_write(component, WSA884X_CLSH_VTH15, vth15_reg_val);
  666. return 0;
  667. }
  668. static void wsa_noise_gate_write(struct snd_soc_component *component,
  669. int imode)
  670. {
  671. switch (imode) {
  672. case NG1:
  673. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  674. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x30);
  675. break;
  676. case NG2:
  677. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  678. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x20);
  679. break;
  680. case NG3:
  681. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  682. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x10);
  683. break;
  684. default:
  685. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  686. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x8);
  687. break;
  688. }
  689. }
  690. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  691. struct snd_ctl_elem_value *ucontrol)
  692. {
  693. struct snd_soc_component *component =
  694. snd_soc_kcontrol_component(kcontrol);
  695. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  696. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  697. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  698. wsa884x->dev_mode);
  699. return 0;
  700. }
  701. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  702. struct snd_ctl_elem_value *ucontrol)
  703. {
  704. struct snd_soc_component *component =
  705. snd_soc_kcontrol_component(kcontrol);
  706. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  707. int dev_mode;
  708. int wsa_dev_index;
  709. if ((ucontrol->value.integer.value[0] >= SPEAKER) &&
  710. (ucontrol->value.integer.value[0] < MAX_DEV_MODE))
  711. dev_mode = ucontrol->value.integer.value[0];
  712. else
  713. return -EINVAL;
  714. dev_dbg(component->dev, "%s: Dev Mode current: %d, new: %d\n",
  715. __func__, wsa884x->dev_mode, dev_mode);
  716. /* Check if input parameter is in range */
  717. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  718. if ((dev_mode + wsa_dev_index * 2) < (MAX_DEV_MODE * 2)) {
  719. wsa884x->dev_mode = dev_mode;
  720. wsa884x->system_gain = wsa884x->sys_gains[dev_mode + wsa_dev_index * 2];
  721. } else {
  722. return -EINVAL;
  723. }
  724. return 0;
  725. }
  726. static const char * const wsa_pa_gain_text[] = {
  727. "G_21_DB", "G_19P5_DB" "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB",
  728. "G_12_DB", "G_10P5_DB", "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB",
  729. "G_3_DB", "G_1P5_DB", "G_0_DB", "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB"
  730. "G_M6_DB", "G_M7P5_DB", "G_M9_DB"
  731. };
  732. static const struct soc_enum wsa_pa_gain_enum =
  733. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  734. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  735. struct snd_ctl_elem_value *ucontrol)
  736. {
  737. struct snd_soc_component *component =
  738. snd_soc_kcontrol_component(kcontrol);
  739. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  740. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  741. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  742. wsa884x->pa_gain);
  743. return 0;
  744. }
  745. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  746. struct snd_ctl_elem_value *ucontrol)
  747. {
  748. struct snd_soc_component *component =
  749. snd_soc_kcontrol_component(kcontrol);
  750. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  751. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  752. __func__, ucontrol->value.integer.value[0]);
  753. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  754. return 0;
  755. }
  756. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  757. struct snd_ctl_elem_value *ucontrol)
  758. {
  759. struct snd_soc_component *component =
  760. snd_soc_kcontrol_component(kcontrol);
  761. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  762. int temp = 0;
  763. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  764. temp = wsa884x->curr_temp;
  765. else
  766. wsa884x_get_temperature(component, &temp);
  767. ucontrol->value.integer.value[0] = temp;
  768. return 0;
  769. }
  770. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  771. void *file_private_data, struct file *file,
  772. char __user *buf, size_t count, loff_t pos)
  773. {
  774. struct wsa884x_priv *wsa884x;
  775. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  776. int len = 0;
  777. wsa884x = (struct wsa884x_priv *) entry->private_data;
  778. if (!wsa884x) {
  779. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  780. return -EINVAL;
  781. }
  782. switch (wsa884x->version) {
  783. case WSA884X_VERSION_1_0:
  784. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  785. break;
  786. default:
  787. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  788. break;
  789. }
  790. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  791. }
  792. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  793. .read = wsa884x_codec_version_read,
  794. };
  795. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  796. void *file_private_data,
  797. struct file *file,
  798. char __user *buf, size_t count,
  799. loff_t pos)
  800. {
  801. struct wsa884x_priv *wsa884x;
  802. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  803. int len = 0;
  804. wsa884x = (struct wsa884x_priv *) entry->private_data;
  805. if (!wsa884x) {
  806. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  807. return -EINVAL;
  808. }
  809. switch (wsa884x->variant) {
  810. case WSA8840:
  811. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  812. break;
  813. case WSA8845:
  814. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  815. break;
  816. case WSA8845H:
  817. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  818. break;
  819. default:
  820. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  821. break;
  822. }
  823. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  824. }
  825. static struct snd_info_entry_ops wsa884x_variant_ops = {
  826. .read = wsa884x_variant_read,
  827. };
  828. /*
  829. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  830. * @codec_root: The parent directory
  831. * @component: Codec instance
  832. *
  833. * Creates wsa884x module and version entry under the given
  834. * parent directory.
  835. *
  836. * Return: 0 on success or negative error code on failure.
  837. */
  838. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  839. struct snd_soc_component *component)
  840. {
  841. struct snd_info_entry *version_entry;
  842. struct snd_info_entry *variant_entry;
  843. struct wsa884x_priv *wsa884x;
  844. struct snd_soc_card *card;
  845. char name[80];
  846. if (!codec_root || !component)
  847. return -EINVAL;
  848. wsa884x = snd_soc_component_get_drvdata(component);
  849. if (wsa884x->entry) {
  850. dev_dbg(wsa884x->dev,
  851. "%s:wsa884x module already created\n", __func__);
  852. return 0;
  853. }
  854. card = component->card;
  855. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  856. wsa884x->swr_slave->addr);
  857. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  858. (const char *)name,
  859. codec_root);
  860. if (!wsa884x->entry) {
  861. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  862. __func__);
  863. return -ENOMEM;
  864. }
  865. wsa884x->entry->mode = S_IFDIR | 0555;
  866. if (snd_info_register(wsa884x->entry) < 0) {
  867. snd_info_free_entry(wsa884x->entry);
  868. return -ENOMEM;
  869. }
  870. version_entry = snd_info_create_card_entry(card->snd_card,
  871. "version",
  872. wsa884x->entry);
  873. if (!version_entry) {
  874. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  875. __func__);
  876. snd_info_free_entry(wsa884x->entry);
  877. return -ENOMEM;
  878. }
  879. version_entry->private_data = wsa884x;
  880. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  881. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  882. version_entry->c.ops = &wsa884x_codec_info_ops;
  883. if (snd_info_register(version_entry) < 0) {
  884. snd_info_free_entry(version_entry);
  885. snd_info_free_entry(wsa884x->entry);
  886. return -ENOMEM;
  887. }
  888. wsa884x->version_entry = version_entry;
  889. variant_entry = snd_info_create_card_entry(card->snd_card,
  890. "variant",
  891. wsa884x->entry);
  892. if (!variant_entry) {
  893. dev_dbg(component->dev,
  894. "%s: failed to create wsa884x variant entry\n",
  895. __func__);
  896. snd_info_free_entry(version_entry);
  897. snd_info_free_entry(wsa884x->entry);
  898. return -ENOMEM;
  899. }
  900. variant_entry->private_data = wsa884x;
  901. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  902. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  903. variant_entry->c.ops = &wsa884x_variant_ops;
  904. if (snd_info_register(variant_entry) < 0) {
  905. snd_info_free_entry(variant_entry);
  906. snd_info_free_entry(version_entry);
  907. snd_info_free_entry(wsa884x->entry);
  908. return -ENOMEM;
  909. }
  910. wsa884x->variant_entry = variant_entry;
  911. return 0;
  912. }
  913. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  914. /*
  915. * wsa884x_codec_get_dev_num - returns swr device number
  916. * @component: Codec instance
  917. *
  918. * Return: swr device number on success or negative error
  919. * code on failure.
  920. */
  921. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  922. {
  923. struct wsa884x_priv *wsa884x;
  924. if (!component)
  925. return -EINVAL;
  926. wsa884x = snd_soc_component_get_drvdata(component);
  927. if (!wsa884x) {
  928. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  929. return -EINVAL;
  930. }
  931. return wsa884x->swr_slave->dev_num;
  932. }
  933. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  934. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  935. struct snd_ctl_elem_value *ucontrol)
  936. {
  937. struct snd_soc_component *component =
  938. snd_soc_kcontrol_component(kcontrol);
  939. struct wsa884x_priv *wsa884x;
  940. if (!component)
  941. return -EINVAL;
  942. wsa884x = snd_soc_component_get_drvdata(component);
  943. if (!wsa884x) {
  944. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  945. return -EINVAL;
  946. }
  947. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  948. return 0;
  949. }
  950. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  951. struct snd_ctl_elem_value *ucontrol)
  952. {
  953. struct snd_soc_component *component =
  954. snd_soc_kcontrol_component(kcontrol);
  955. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  956. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  957. return 0;
  958. }
  959. /*
  960. * wsa884x_validate_dt_configuration_params - returns 1 or 0
  961. * Return: 0 Valid configuration, 1 Invalid configuration
  962. */
  963. static bool wsa884x_validate_dt_configuration_params(struct snd_soc_component *component,
  964. u8 irload, u8 ibat_cfg_dts, u8 isystem_gain)
  965. {
  966. u8 bat_cfg_reg;
  967. bool is_invalid_flag = true;
  968. bat_cfg_reg = snd_soc_component_read(component, WSA884X_VPHX_SYS_EN_STATUS);
  969. dev_info(component->dev, "VPHX EN Status: %d", bat_cfg_reg);
  970. if ((ibat_cfg_dts == EXT_1S) || (ibat_cfg_dts == EXT_2S) || (ibat_cfg_dts == EXT_3S))
  971. ibat_cfg_dts = EXT_ABOVE_3S;
  972. if ((WSA_4_OHMS <= irload && irload < WSA_MAX_OHMS) &&
  973. (G_21_DB <= isystem_gain && isystem_gain < G_MAX_DB) &&
  974. (EXT_ABOVE_3S <= ibat_cfg_dts && ibat_cfg_dts < CONFIG_MAX) &&
  975. (ibat_cfg_dts == bat_cfg_reg))
  976. is_invalid_flag = false;
  977. return is_invalid_flag;
  978. }
  979. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  980. struct snd_ctl_elem_value *ucontrol)
  981. {
  982. struct snd_soc_component *component =
  983. snd_soc_kcontrol_component(kcontrol);
  984. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  985. int value = ucontrol->value.integer.value[0];
  986. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  987. __func__, wsa884x->comp_enable, value);
  988. wsa884x->comp_enable = value;
  989. return 0;
  990. }
  991. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  992. struct snd_ctl_elem_value *ucontrol)
  993. {
  994. struct snd_soc_component *component =
  995. snd_soc_kcontrol_component(kcontrol);
  996. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  997. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  998. return 0;
  999. }
  1000. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  1001. struct snd_ctl_elem_value *ucontrol)
  1002. {
  1003. struct snd_soc_component *component =
  1004. snd_soc_kcontrol_component(kcontrol);
  1005. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1006. int value = ucontrol->value.integer.value[0];
  1007. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  1008. __func__, wsa884x->visense_enable, value);
  1009. wsa884x->visense_enable = value;
  1010. return 0;
  1011. }
  1012. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  1013. struct snd_ctl_elem_value *ucontrol)
  1014. {
  1015. struct snd_soc_component *component =
  1016. snd_soc_kcontrol_component(kcontrol);
  1017. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1018. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  1019. return 0;
  1020. }
  1021. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  1022. struct snd_ctl_elem_value *ucontrol)
  1023. {
  1024. struct snd_soc_component *component =
  1025. snd_soc_kcontrol_component(kcontrol);
  1026. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1027. int value = ucontrol->value.integer.value[0];
  1028. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  1029. __func__, wsa884x->pbr_enable, value);
  1030. wsa884x->pbr_enable = value;
  1031. return 0;
  1032. }
  1033. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  1034. struct snd_ctl_elem_value *ucontrol)
  1035. {
  1036. struct snd_soc_component *component =
  1037. snd_soc_kcontrol_component(kcontrol);
  1038. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1039. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  1040. return 0;
  1041. }
  1042. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  1043. struct snd_ctl_elem_value *ucontrol)
  1044. {
  1045. struct snd_soc_component *component =
  1046. snd_soc_kcontrol_component(kcontrol);
  1047. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1048. int value = ucontrol->value.integer.value[0];
  1049. dev_dbg(component->dev, "%s: CPS enable current %d, new %d\n",
  1050. __func__, wsa884x->cps_enable, value);
  1051. wsa884x->cps_enable = value;
  1052. return 0;
  1053. }
  1054. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  1055. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  1056. wsa_pa_gain_get, wsa_pa_gain_put),
  1057. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1058. wsa_get_temp, NULL),
  1059. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1060. wsa884x_get_dev_num, NULL),
  1061. SOC_SINGLE_EXT("WSA MODE", SND_SOC_NOPM, 0, 1, 0,
  1062. wsa_dev_mode_get, wsa_dev_mode_put),
  1063. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1064. wsa884x_get_compander, wsa884x_set_compander),
  1065. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  1066. wsa884x_get_visense, wsa884x_set_visense),
  1067. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  1068. wsa884x_get_pbr, wsa884x_set_pbr),
  1069. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  1070. wsa884x_get_cps, wsa884x_set_cps),
  1071. };
  1072. static const struct snd_kcontrol_new swr_dac_port[] = {
  1073. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1074. };
  1075. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  1076. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  1077. u8 *port_type)
  1078. {
  1079. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1080. *port_id = wsa884x->port[port_idx].port_id;
  1081. *num_ch = wsa884x->port[port_idx].num_ch;
  1082. *ch_mask = wsa884x->port[port_idx].ch_mask;
  1083. *ch_rate = wsa884x->port[port_idx].ch_rate;
  1084. *port_type = wsa884x->port[port_idx].port_type;
  1085. return 0;
  1086. }
  1087. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  1088. struct snd_kcontrol *kcontrol, int event)
  1089. {
  1090. struct snd_soc_component *component =
  1091. snd_soc_dapm_to_component(w->dapm);
  1092. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1093. u8 port_id[WSA884X_MAX_SWR_PORTS];
  1094. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  1095. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  1096. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1097. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1098. u8 num_port = 0;
  1099. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1100. event, w->name);
  1101. if (wsa884x == NULL)
  1102. return -EINVAL;
  1103. switch (event) {
  1104. case SND_SOC_DAPM_PRE_PMU:
  1105. wsa884x_set_port(component, SWR_DAC_PORT,
  1106. &port_id[num_port], &num_ch[num_port],
  1107. &ch_mask[num_port], &ch_rate[num_port],
  1108. &port_type[num_port]);
  1109. if (wsa884x->dev_mode == RECEIVER)
  1110. ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
  1111. ++num_port;
  1112. if (wsa884x->comp_enable) {
  1113. wsa884x_set_port(component, SWR_COMP_PORT,
  1114. &port_id[num_port], &num_ch[num_port],
  1115. &ch_mask[num_port], &ch_rate[num_port],
  1116. &port_type[num_port]);
  1117. ++num_port;
  1118. }
  1119. if (wsa884x->pbr_enable) {
  1120. wsa884x_set_port(component, SWR_PBR_PORT,
  1121. &port_id[num_port], &num_ch[num_port],
  1122. &ch_mask[num_port], &ch_rate[num_port],
  1123. &port_type[num_port]);
  1124. ++num_port;
  1125. }
  1126. if (wsa884x->visense_enable) {
  1127. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1128. &port_id[num_port], &num_ch[num_port],
  1129. &ch_mask[num_port], &ch_rate[num_port],
  1130. &port_type[num_port]);
  1131. ++num_port;
  1132. }
  1133. if (wsa884x->cps_enable) {
  1134. wsa884x_set_port(component, SWR_CPS_PORT,
  1135. &port_id[num_port], &num_ch[num_port],
  1136. &ch_mask[num_port], &ch_rate[num_port],
  1137. &port_type[num_port]);
  1138. ++num_port;
  1139. }
  1140. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1141. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1142. &port_type[0]);
  1143. break;
  1144. case SND_SOC_DAPM_POST_PMU:
  1145. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1146. break;
  1147. case SND_SOC_DAPM_PRE_PMD:
  1148. wsa884x_set_port(component, SWR_DAC_PORT,
  1149. &port_id[num_port], &num_ch[num_port],
  1150. &ch_mask[num_port], &ch_rate[num_port],
  1151. &port_type[num_port]);
  1152. ++num_port;
  1153. if (wsa884x->comp_enable) {
  1154. wsa884x_set_port(component, SWR_COMP_PORT,
  1155. &port_id[num_port], &num_ch[num_port],
  1156. &ch_mask[num_port], &ch_rate[num_port],
  1157. &port_type[num_port]);
  1158. ++num_port;
  1159. }
  1160. if (wsa884x->pbr_enable) {
  1161. wsa884x_set_port(component, SWR_PBR_PORT,
  1162. &port_id[num_port], &num_ch[num_port],
  1163. &ch_mask[num_port], &ch_rate[num_port],
  1164. &port_type[num_port]);
  1165. ++num_port;
  1166. }
  1167. if (wsa884x->visense_enable) {
  1168. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1169. &port_id[num_port], &num_ch[num_port],
  1170. &ch_mask[num_port], &ch_rate[num_port],
  1171. &port_type[num_port]);
  1172. ++num_port;
  1173. }
  1174. if (wsa884x->cps_enable) {
  1175. wsa884x_set_port(component, SWR_CPS_PORT,
  1176. &port_id[num_port], &num_ch[num_port],
  1177. &ch_mask[num_port], &ch_rate[num_port],
  1178. &port_type[num_port]);
  1179. ++num_port;
  1180. }
  1181. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1182. &ch_mask[0], &port_type[0]);
  1183. break;
  1184. case SND_SOC_DAPM_POST_PMD:
  1185. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1186. dev_err_ratelimited(component->dev,
  1187. "%s: set num ch failed\n", __func__);
  1188. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1189. wsa884x->swr_slave->dev_num,
  1190. false);
  1191. break;
  1192. default:
  1193. break;
  1194. }
  1195. return 0;
  1196. }
  1197. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1198. struct snd_kcontrol *kcontrol, int event)
  1199. {
  1200. struct snd_soc_component *component =
  1201. snd_soc_dapm_to_component(w->dapm);
  1202. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1203. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1204. switch (event) {
  1205. case SND_SOC_DAPM_POST_PMU:
  1206. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1207. wsa884x->swr_slave->dev_num,
  1208. true);
  1209. wsa884x_set_gain_parameters(component);
  1210. if (wsa884x->dev_mode == SPEAKER) {
  1211. snd_soc_component_update_bits(component,
  1212. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1213. } else {
  1214. snd_soc_component_update_bits(component,
  1215. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1216. snd_soc_component_update_bits(component,
  1217. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1218. snd_soc_component_update_bits(component,
  1219. REG_FIELD_VALUE(PWM_CLK_CTL,
  1220. PWM_CLK_FREQ_SEL, 0x01));
  1221. }
  1222. if (wsa884x->pbr_enable) {
  1223. snd_soc_component_update_bits(component,
  1224. REG_FIELD_VALUE(CURRENT_LIMIT,
  1225. CURRENT_LIMIT_OVRD_EN, 0x00));
  1226. switch (wsa884x->bat_cfg) {
  1227. case CONFIG_1S:
  1228. snd_soc_component_update_bits(component,
  1229. REG_FIELD_VALUE(CURRENT_LIMIT,
  1230. CURRENT_LIMIT, 0x15));
  1231. break;
  1232. case CONFIG_2S:
  1233. snd_soc_component_update_bits(component,
  1234. REG_FIELD_VALUE(CURRENT_LIMIT,
  1235. CURRENT_LIMIT, 0x11));
  1236. break;
  1237. case CONFIG_3S:
  1238. snd_soc_component_update_bits(component,
  1239. REG_FIELD_VALUE(CURRENT_LIMIT,
  1240. CURRENT_LIMIT, 0x0D));
  1241. break;
  1242. }
  1243. } else {
  1244. snd_soc_component_update_bits(component,
  1245. REG_FIELD_VALUE(CURRENT_LIMIT,
  1246. CURRENT_LIMIT_OVRD_EN, 0x01));
  1247. if (wsa884x->system_gain >= G_12_DB)
  1248. snd_soc_component_update_bits(component,
  1249. REG_FIELD_VALUE(CURRENT_LIMIT,
  1250. CURRENT_LIMIT, 0x15));
  1251. else
  1252. snd_soc_component_update_bits(component,
  1253. REG_FIELD_VALUE(CURRENT_LIMIT,
  1254. CURRENT_LIMIT, 0x09));
  1255. }
  1256. /* Force remove group */
  1257. swr_remove_from_group(wsa884x->swr_slave,
  1258. wsa884x->swr_slave->dev_num);
  1259. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask) &&
  1260. !wsa884x->pa_mute)
  1261. snd_soc_component_update_bits(component,
  1262. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1263. break;
  1264. case SND_SOC_DAPM_PRE_PMD:
  1265. snd_soc_component_update_bits(component,
  1266. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1267. snd_soc_component_update_bits(component,
  1268. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1269. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1270. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1271. wsa884x->pa_mute = 0;
  1272. break;
  1273. }
  1274. return 0;
  1275. }
  1276. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1277. SND_SOC_DAPM_INPUT("IN"),
  1278. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1279. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1280. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1281. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1282. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1283. };
  1284. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1285. {"SWR DAC_Port", "Switch", "IN"},
  1286. {"SPKR", NULL, "SWR DAC_Port"},
  1287. };
  1288. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1289. u8 num_port, unsigned int *ch_mask,
  1290. unsigned int *ch_rate, u8 *port_type)
  1291. {
  1292. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1293. int i;
  1294. if (!port || !ch_mask || !ch_rate ||
  1295. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1296. dev_err_ratelimited(component->dev,
  1297. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1298. __func__, port, ch_mask, ch_rate);
  1299. return -EINVAL;
  1300. }
  1301. for (i = 0; i < num_port; i++) {
  1302. wsa884x->port[i].port_id = port[i];
  1303. wsa884x->port[i].ch_mask = ch_mask[i];
  1304. wsa884x->port[i].ch_rate = ch_rate[i];
  1305. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1306. if (port_type)
  1307. wsa884x->port[i].port_type = port_type[i];
  1308. }
  1309. return 0;
  1310. }
  1311. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1312. static void wsa884x_codec_init(struct snd_soc_component *component)
  1313. {
  1314. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1315. int i;
  1316. if (!wsa884x)
  1317. return;
  1318. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1319. snd_soc_component_update_bits(component, reg_init[i].reg,
  1320. reg_init[i].mask, reg_init[i].val);
  1321. /* Register updates for 2S battery configuration */
  1322. if (wsa884x->bat_cfg == CONFIG_2S) {
  1323. for (i = 0; i < ARRAY_SIZE(reg_init_2S); i++)
  1324. snd_soc_component_update_bits(component, reg_init_2S[i].reg,
  1325. reg_init_2S[i].mask, reg_init_2S[i].val);
  1326. }
  1327. wsa_noise_gate_write(component, wsa884x->noise_gate_mode);
  1328. }
  1329. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1330. struct wsa_temp_register *wsa_temp_reg)
  1331. {
  1332. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1333. if (!wsa884x) {
  1334. dev_err_ratelimited(component->dev, "%s: wsa884x is NULL\n", __func__);
  1335. return -EINVAL;
  1336. }
  1337. mutex_lock(&wsa884x->res_lock);
  1338. snd_soc_component_update_bits(component,
  1339. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1340. snd_soc_component_update_bits(component,
  1341. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1342. snd_soc_component_update_bits(component,
  1343. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1344. snd_soc_component_update_bits(component,
  1345. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1346. snd_soc_component_update_bits(component,
  1347. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1348. snd_soc_component_update_bits(component,
  1349. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1350. snd_soc_component_update_bits(component,
  1351. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1352. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1353. WSA884X_TEMP_DIN_MSB);
  1354. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1355. WSA884X_TEMP_DIN_LSB);
  1356. snd_soc_component_update_bits(component,
  1357. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1358. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1359. WSA884X_OTP_REG_1);
  1360. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1361. WSA884X_OTP_REG_2);
  1362. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1363. WSA884X_OTP_REG_3);
  1364. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1365. WSA884X_OTP_REG_4);
  1366. snd_soc_component_update_bits(component,
  1367. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1368. mutex_unlock(&wsa884x->res_lock);
  1369. return 0;
  1370. }
  1371. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1372. int *temp)
  1373. {
  1374. struct wsa_temp_register reg;
  1375. int dmeas, d1, d2;
  1376. int ret = 0;
  1377. int temp_val = 0;
  1378. int t1 = T1_TEMP;
  1379. int t2 = T2_TEMP;
  1380. u8 retry = WSA884X_TEMP_RETRY;
  1381. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1382. if (!wsa884x)
  1383. return -EINVAL;
  1384. do {
  1385. ret = wsa884x_temp_reg_read(component, &reg);
  1386. if (ret) {
  1387. pr_err_ratelimited("%s: temp read failed: %d, current temp: %d\n",
  1388. __func__, ret, wsa884x->curr_temp);
  1389. if (temp)
  1390. *temp = wsa884x->curr_temp;
  1391. return 0;
  1392. }
  1393. /*
  1394. * Temperature register values are expected to be in the
  1395. * following range.
  1396. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1397. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1398. */
  1399. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1400. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1401. reg.d1_lsb == 192)) ||
  1402. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1403. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1404. reg.d2_lsb == 192))) {
  1405. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1406. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1407. reg.d2_lsb);
  1408. }
  1409. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1410. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1411. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1412. if (d1 == d2)
  1413. temp_val = TEMP_INVALID;
  1414. else
  1415. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1416. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1417. temp_val >= HIGH_TEMP_THRESHOLD) {
  1418. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1419. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1420. if (retry--)
  1421. msleep(10);
  1422. } else {
  1423. break;
  1424. }
  1425. } while (retry);
  1426. wsa884x->curr_temp = temp_val;
  1427. if (temp)
  1428. *temp = temp_val;
  1429. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1430. __func__, temp_val, dmeas, d1, d2);
  1431. return ret;
  1432. }
  1433. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1434. {
  1435. char w_name[MAX_NAME_LEN];
  1436. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1437. struct swr_device *dev;
  1438. int variant = 0, version = 0;
  1439. struct snd_soc_dapm_context *dapm =
  1440. snd_soc_component_get_dapm(component);
  1441. if (!wsa884x)
  1442. return -EINVAL;
  1443. if (!component->name_prefix)
  1444. return -EINVAL;
  1445. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1446. dev = wsa884x->swr_slave;
  1447. wsa884x->component = component;
  1448. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1449. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1450. wsa884x->variant = variant;
  1451. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1452. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1453. wsa884x->version = version;
  1454. wsa884x->comp_offset = COMP_OFFSET2;
  1455. wsa884x_codec_init(component);
  1456. wsa884x->global_pa_cnt = 0;
  1457. memset(w_name, 0, sizeof(w_name));
  1458. strlcpy(w_name, wsa884x->dai_driver->playback.stream_name,
  1459. sizeof(w_name));
  1460. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1461. memset(w_name, 0, sizeof(w_name));
  1462. strlcpy(w_name, "IN", sizeof(w_name));
  1463. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1464. memset(w_name, 0, sizeof(w_name));
  1465. strlcpy(w_name, "SWR DAC_Port", sizeof(w_name));
  1466. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1467. memset(w_name, 0, sizeof(w_name));
  1468. strlcpy(w_name, "SPKR", sizeof(w_name));
  1469. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1470. snd_soc_dapm_sync(dapm);
  1471. return 0;
  1472. }
  1473. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1474. {
  1475. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1476. if (!wsa884x)
  1477. return;
  1478. snd_soc_component_exit_regmap(component);
  1479. return;
  1480. }
  1481. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1482. {
  1483. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1484. if (!wsa884x)
  1485. return 0;
  1486. wsa884x->dapm_bias_off = true;
  1487. return 0;
  1488. }
  1489. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1490. {
  1491. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1492. if (!wsa884x)
  1493. return 0;
  1494. wsa884x->dapm_bias_off = false;
  1495. return 0;
  1496. }
  1497. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1498. .name = "",
  1499. .probe = wsa884x_codec_probe,
  1500. .remove = wsa884x_codec_remove,
  1501. .controls = wsa884x_snd_controls,
  1502. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1503. .dapm_widgets = wsa884x_dapm_widgets,
  1504. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1505. .dapm_routes = wsa884x_audio_map,
  1506. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1507. .suspend = wsa884x_soc_codec_suspend,
  1508. .resume = wsa884x_soc_codec_resume,
  1509. };
  1510. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1511. {
  1512. int ret = 0;
  1513. if (enable)
  1514. ret = msm_cdc_pinctrl_select_active_state(
  1515. wsa884x->wsa_rst_np);
  1516. else
  1517. ret = msm_cdc_pinctrl_select_sleep_state(
  1518. wsa884x->wsa_rst_np);
  1519. if (ret != 0)
  1520. dev_err_ratelimited(wsa884x->dev,
  1521. "%s: Failed to turn state %d; ret=%d\n",
  1522. __func__, enable, ret);
  1523. return ret;
  1524. }
  1525. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1526. {
  1527. int ret;
  1528. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1529. if (ret)
  1530. dev_err_ratelimited(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1531. return ret;
  1532. }
  1533. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1534. {
  1535. int ret;
  1536. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1537. if (ret)
  1538. dev_err_ratelimited(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1539. return ret;
  1540. }
  1541. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1542. {
  1543. u8 retry = WSA884X_NUM_RETRY;
  1544. u8 devnum = 0;
  1545. struct swr_device *pdev;
  1546. pdev = wsa884x->swr_slave;
  1547. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1548. /* Retry after 1 msec delay */
  1549. usleep_range(1000, 1100);
  1550. }
  1551. pdev->dev_num = devnum;
  1552. wsa884x_regcache_sync(wsa884x);
  1553. return 0;
  1554. }
  1555. static int wsa884x_event_notify(struct notifier_block *nb,
  1556. unsigned long val, void *ptr)
  1557. {
  1558. u16 event = (val & 0xffff);
  1559. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1560. parent_nblock);
  1561. if (!wsa884x)
  1562. return -EINVAL;
  1563. switch (event) {
  1564. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1565. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1566. snd_soc_component_update_bits(wsa884x->component,
  1567. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1568. wsa884x_swr_down(wsa884x);
  1569. break;
  1570. case BOLERO_SLV_EVT_SSR_UP:
  1571. wsa884x_swr_up(wsa884x);
  1572. /* Add delay to allow enumerate */
  1573. usleep_range(20000, 20010);
  1574. wsa884x_swr_reset(wsa884x);
  1575. dev_err(wsa884x->dev, "%s: BOLERO_SLV_EVT_SSR_UP Called", __func__);
  1576. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1577. wsa884x->swr_wsa_port_params);
  1578. break;
  1579. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1580. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1581. snd_soc_component_update_bits(wsa884x->component,
  1582. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1583. snd_soc_component_update_bits(wsa884x->component,
  1584. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1585. }
  1586. break;
  1587. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1588. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1589. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1590. break;
  1591. default:
  1592. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1593. __func__, event);
  1594. break;
  1595. }
  1596. return 0;
  1597. }
  1598. static int wsa884x_parse_port_params(struct device *dev, char *prop)
  1599. {
  1600. u32 *dt_array, map_size, max_uc;
  1601. int ret = 0;
  1602. u32 cnt = 0;
  1603. u32 i, j;
  1604. struct swr_port_params (*map)[SWR_UC_MAX][WSA884X_MAX_SWR_PORTS];
  1605. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  1606. struct wsa884x_priv *wsa884x = dev_get_drvdata(dev);
  1607. map = &wsa884x->wsa_port_params;
  1608. map_uc = &wsa884x->swr_wsa_port_params;
  1609. if (!of_find_property(dev->of_node, prop,
  1610. &map_size)) {
  1611. dev_err(dev, "missing port mapping prop %s\n", prop);
  1612. ret = -EINVAL;
  1613. goto err_port_map;
  1614. }
  1615. max_uc = map_size / (WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  1616. if (max_uc != SWR_UC_MAX) {
  1617. dev_err(dev, "%s: port params not provided for all usecases\n",
  1618. __func__);
  1619. ret = -EINVAL;
  1620. goto err_port_map;
  1621. }
  1622. dt_array = kzalloc(map_size, GFP_KERNEL);
  1623. if (!dt_array) {
  1624. ret = -ENOMEM;
  1625. goto err_port_map;
  1626. }
  1627. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  1628. WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * max_uc);
  1629. if (ret) {
  1630. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  1631. __func__, prop);
  1632. goto err_pdata_fail;
  1633. }
  1634. for (i = 0; i < max_uc; i++) {
  1635. for (j = 0; j < WSA884X_MAX_SWR_PORTS; j++) {
  1636. cnt = (i * WSA884X_MAX_SWR_PORTS + j) * SWR_PORT_PARAMS;
  1637. (*map)[i][j].offset1 = dt_array[cnt];
  1638. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  1639. }
  1640. (*map_uc)[i].pp = &(*map)[i][0];
  1641. }
  1642. kfree(dt_array);
  1643. return 0;
  1644. err_pdata_fail:
  1645. kfree(dt_array);
  1646. err_port_map:
  1647. return ret;
  1648. }
  1649. static int wsa884x_enable_supplies(struct device *dev,
  1650. struct wsa884x_priv *priv)
  1651. {
  1652. int ret = 0;
  1653. /* Parse power supplies */
  1654. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1655. &priv->num_supplies);
  1656. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1657. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1658. return -EINVAL;
  1659. }
  1660. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1661. priv->regulator, priv->num_supplies);
  1662. if (!priv->supplies) {
  1663. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1664. __func__);
  1665. return ret;
  1666. }
  1667. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1668. priv->regulator,
  1669. priv->num_supplies);
  1670. if (ret)
  1671. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1672. __func__);
  1673. return ret;
  1674. }
  1675. static struct snd_soc_dai_driver wsa_dai[] = {
  1676. {
  1677. .name = "",
  1678. .playback = {
  1679. .stream_name = "",
  1680. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1681. .formats = WSA884X_FORMATS,
  1682. .rate_max = 192000,
  1683. .rate_min = 8000,
  1684. .channels_min = 1,
  1685. .channels_max = 2,
  1686. },
  1687. },
  1688. };
  1689. static int wsa884x_swr_probe(struct swr_device *pdev)
  1690. {
  1691. int ret = 0;
  1692. struct wsa884x_priv *wsa884x;
  1693. u8 devnum = 0;
  1694. bool pin_state_current = false;
  1695. struct wsa_ctrl_platform_data *plat_data = NULL;
  1696. struct snd_soc_component *component;
  1697. u32 noise_gate_mode;
  1698. char buffer[MAX_NAME_LEN];
  1699. int dev_index = 0;
  1700. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1701. u8 wo0_val;
  1702. int sys_gain_size, sys_gain_length;
  1703. int wsa_dev_index;
  1704. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1705. GFP_KERNEL);
  1706. if (!wsa884x)
  1707. return -ENOMEM;
  1708. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1709. GFP_KERNEL);
  1710. if (!wsa884x_sub_regmap_irq_chip)
  1711. return -ENOMEM;
  1712. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1713. sizeof(struct regmap_irq_chip));
  1714. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1715. if (ret) {
  1716. ret = -EPROBE_DEFER;
  1717. goto err;
  1718. }
  1719. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1720. "qcom,spkr-sd-n-node", 0);
  1721. if (!wsa884x->wsa_rst_np) {
  1722. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1723. goto err_supply;
  1724. }
  1725. swr_set_dev_data(pdev, wsa884x);
  1726. wsa884x->swr_slave = pdev;
  1727. wsa884x->dev = &pdev->dev;
  1728. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1729. wsa884x_gpio_ctrl(wsa884x, true);
  1730. /*
  1731. * Add 5msec delay to provide sufficient time for
  1732. * soundwire auto enumeration of slave devices as
  1733. * per HW requirement.
  1734. */
  1735. usleep_range(5000, 5010);
  1736. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1737. if (ret) {
  1738. dev_dbg(&pdev->dev,
  1739. "%s get devnum %d for dev addr %lx failed\n",
  1740. __func__, devnum, pdev->addr);
  1741. ret = -EPROBE_DEFER;
  1742. goto err_supply;
  1743. }
  1744. pdev->dev_num = devnum;
  1745. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1746. &wsa884x_regmap_config);
  1747. if (IS_ERR(wsa884x->regmap)) {
  1748. ret = PTR_ERR(wsa884x->regmap);
  1749. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1750. __func__, ret);
  1751. goto dev_err;
  1752. }
  1753. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1754. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1755. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1756. wsa884x->irq_info.codec_name = "WSA884X";
  1757. wsa884x->irq_info.regmap = wsa884x->regmap;
  1758. wsa884x->irq_info.dev = &pdev->dev;
  1759. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1760. if (ret) {
  1761. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1762. __func__, ret);
  1763. goto dev_err;
  1764. }
  1765. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1766. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1767. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1768. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1769. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1770. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1771. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1772. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1773. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1774. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1775. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1776. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1777. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1778. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1779. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1780. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1781. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1782. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1783. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1784. /* Under Voltage Lock out (UVLO) interrupt handle */
  1785. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1786. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1787. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1788. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1789. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1790. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1791. if (!wsa884x->driver) {
  1792. ret = -ENOMEM;
  1793. goto err_irq;
  1794. }
  1795. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1796. sizeof(struct snd_soc_component_driver));
  1797. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1798. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1799. if (!wsa884x->dai_driver) {
  1800. ret = -ENOMEM;
  1801. goto err_mem;
  1802. }
  1803. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1804. /* Get last digit from HEX format */
  1805. dev_index = (int)((char)(pdev->addr & 0xF));
  1806. dev_index += 1;
  1807. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1808. dev_index += 2;
  1809. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1810. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1811. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1812. wsa884x->dai_driver->name =
  1813. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1814. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1815. wsa884x->dai_driver->playback.stream_name =
  1816. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1817. /* Number of DAI's used is 1 */
  1818. ret = snd_soc_register_component(&pdev->dev,
  1819. wsa884x->driver, wsa884x->dai_driver, 1);
  1820. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1821. if (!component) {
  1822. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1823. ret = -EINVAL;
  1824. goto err_mem;
  1825. }
  1826. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1827. "qcom,bolero-handle", 0);
  1828. if (!wsa884x->parent_np)
  1829. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1830. "qcom,lpass-cdc-handle", 0);
  1831. if (wsa884x->parent_np) {
  1832. wsa884x->parent_dev =
  1833. of_find_device_by_node(wsa884x->parent_np);
  1834. if (wsa884x->parent_dev) {
  1835. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1836. if (plat_data) {
  1837. wsa884x->parent_nblock.notifier_call =
  1838. wsa884x_event_notify;
  1839. if (plat_data->register_notifier)
  1840. plat_data->register_notifier(
  1841. plat_data->handle,
  1842. &wsa884x->parent_nblock,
  1843. true);
  1844. wsa884x->register_notifier =
  1845. plat_data->register_notifier;
  1846. wsa884x->handle = plat_data->handle;
  1847. } else {
  1848. dev_err(&pdev->dev, "%s: plat data not found\n",
  1849. __func__);
  1850. }
  1851. } else {
  1852. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1853. __func__);
  1854. }
  1855. } else {
  1856. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1857. }
  1858. /* Start in speaker mode by default */
  1859. wsa884x->dev_mode = SPEAKER;
  1860. wsa884x->dev_index = dev_index;
  1861. /* wsa_dev_index is macro_agnostic index */
  1862. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  1863. wsa884x->macro_np = of_parse_phandle(pdev->dev.of_node,
  1864. "qcom,wsa-macro-handle", 0);
  1865. if (wsa884x->macro_np) {
  1866. wsa884x->macro_dev =
  1867. of_find_device_by_node(wsa884x->macro_np);
  1868. if (wsa884x->macro_dev) {
  1869. ret = of_property_read_u32_index(
  1870. wsa884x->macro_dev->dev.of_node,
  1871. "qcom,wsa-rloads",
  1872. wsa_dev_index,
  1873. &wsa884x->rload);
  1874. if (ret) {
  1875. dev_err(&pdev->dev,
  1876. "%s: Failed to read wsa rloads\n",
  1877. __func__);
  1878. goto err_mem;
  1879. }
  1880. ret = of_property_read_u32_index(
  1881. wsa884x->macro_dev->dev.of_node,
  1882. "qcom,wsa-bat-cfgs",
  1883. wsa_dev_index,
  1884. &wsa884x->bat_cfg);
  1885. if (ret) {
  1886. dev_err(&pdev->dev,
  1887. "%s: Failed to read wsa bat cfgs\n",
  1888. __func__);
  1889. goto err_mem;
  1890. }
  1891. ret = of_property_read_u32(wsa884x->macro_dev->dev.of_node,
  1892. "qcom,noise-gate-mode", &noise_gate_mode);
  1893. if (ret) {
  1894. dev_info(&pdev->dev,
  1895. "%s: Failed to read wsa noise gate mode\n",
  1896. __func__);
  1897. wsa884x->noise_gate_mode = IDLE_DETECT;
  1898. } else {
  1899. if (IDLE_DETECT <= noise_gate_mode && noise_gate_mode <= NG3)
  1900. wsa884x->noise_gate_mode = noise_gate_mode;
  1901. else
  1902. wsa884x->noise_gate_mode = IDLE_DETECT;
  1903. }
  1904. if (!of_find_property(wsa884x->macro_dev->dev.of_node,
  1905. "qcom,wsa-system-gains", &sys_gain_size)) {
  1906. dev_err(&pdev->dev,
  1907. "%s: missing wsa-system-gains\n",
  1908. __func__);
  1909. goto err_mem;
  1910. }
  1911. sys_gain_length = sys_gain_size / (2 * sizeof(u32));
  1912. ret = of_property_read_u32_array(
  1913. wsa884x->macro_dev->dev.of_node,
  1914. "qcom,wsa-system-gains", wsa884x->sys_gains,
  1915. sys_gain_length);
  1916. if (ret) {
  1917. dev_err(&pdev->dev,
  1918. "%s: Failed to read wsa system gains\n",
  1919. __func__);
  1920. goto err_mem;
  1921. }
  1922. wsa884x->system_gain = wsa884x->sys_gains[
  1923. wsa884x->dev_mode + wsa_dev_index * 2];
  1924. } else {
  1925. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1926. __func__);
  1927. goto err_mem;
  1928. }
  1929. } else {
  1930. dev_err(&pdev->dev, "%s: parent node not found\n", __func__);
  1931. goto err_mem;
  1932. }
  1933. dev_dbg(component->dev,
  1934. "%s: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n", __func__,
  1935. wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1936. ret = wsa884x_validate_dt_configuration_params(component, wsa884x->rload,
  1937. wsa884x->bat_cfg, wsa884x->system_gain);
  1938. if (ret) {
  1939. dev_err(&pdev->dev,
  1940. "%s: invalid dt parameter: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n",
  1941. __func__, wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1942. ret = -EINVAL;
  1943. goto err_mem;
  1944. }
  1945. /* Assume that compander is enabled by default unless it is haptics sku */
  1946. if (wsa884x->variant == WSA8845H)
  1947. wsa884x->comp_enable = false;
  1948. else
  1949. wsa884x->comp_enable = true;
  1950. wsa884x_set_gain_parameters(component);
  1951. wsa884x_set_pbr_parameters(component);
  1952. /* Must write WO registers in a single write */
  1953. wo0_val = (0xC0 | (wsa884x->pa_aux_gain << 0x02) | !wsa884x->dev_mode);
  1954. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_0, wo0_val);
  1955. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_1, 0x0);
  1956. if (wsa884x->rload == WSA_4_OHMS || wsa884x->rload == WSA_6_OHMS)
  1957. snd_soc_component_update_bits(component,
  1958. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1959. if (wsa884x->dev_mode == SPEAKER) {
  1960. snd_soc_component_update_bits(component,
  1961. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1962. } else {
  1963. snd_soc_component_update_bits(component,
  1964. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1965. snd_soc_component_update_bits(component,
  1966. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1967. snd_soc_component_update_bits(component,
  1968. REG_FIELD_VALUE(PWM_CLK_CTL,
  1969. PWM_CLK_FREQ_SEL, 0x01));
  1970. }
  1971. if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
  1972. snd_soc_component_update_bits(component,
  1973. REG_FIELD_VALUE(TOP_CTRL1,
  1974. OCP_LOWVBAT_ITH_SEL_EN, 0x00));
  1975. ret = wsa884x_parse_port_params(&pdev->dev, "qcom,swr-wsa-port-params");
  1976. if (ret) {
  1977. dev_err(&pdev->dev, "Failed to read port params\n");
  1978. goto err;
  1979. }
  1980. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1981. wsa884x->swr_wsa_port_params);
  1982. mutex_init(&wsa884x->res_lock);
  1983. #ifdef CONFIG_DEBUG_FS
  1984. if (!wsa884x->debugfs_dent) {
  1985. wsa884x->debugfs_dent = debugfs_create_dir(
  1986. dev_name(&pdev->dev), 0);
  1987. if (!IS_ERR(wsa884x->debugfs_dent)) {
  1988. wsa884x->debugfs_peek =
  1989. debugfs_create_file("swrslave_peek",
  1990. S_IFREG | 0444,
  1991. wsa884x->debugfs_dent,
  1992. (void *) pdev,
  1993. &codec_debug_read_ops);
  1994. wsa884x->debugfs_poke =
  1995. debugfs_create_file("swrslave_poke",
  1996. S_IFREG | 0444,
  1997. wsa884x->debugfs_dent,
  1998. (void *) pdev,
  1999. &codec_debug_write_ops);
  2000. wsa884x->debugfs_reg_dump =
  2001. debugfs_create_file(
  2002. "swrslave_reg_dump",
  2003. S_IFREG | 0444,
  2004. wsa884x->debugfs_dent,
  2005. (void *) pdev,
  2006. &codec_debug_dump_ops);
  2007. }
  2008. }
  2009. #endif
  2010. return 0;
  2011. err_mem:
  2012. snd_soc_unregister_component(&pdev->dev);
  2013. if (wsa884x->dai_driver) {
  2014. kfree(wsa884x->dai_driver->name);
  2015. kfree(wsa884x->dai_driver->playback.stream_name);
  2016. devm_kfree(&pdev->dev, wsa884x->dai_driver);
  2017. wsa884x->dai_driver = NULL;
  2018. }
  2019. if (wsa884x->driver) {
  2020. kfree(wsa884x->driver->name);
  2021. devm_kfree(&pdev->dev, wsa884x->driver);
  2022. wsa884x->driver = NULL;
  2023. }
  2024. err_irq:
  2025. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  2026. dev_err:
  2027. if (pin_state_current == false)
  2028. wsa884x_gpio_ctrl(wsa884x, false);
  2029. swr_remove_device(pdev);
  2030. err_supply:
  2031. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2032. wsa884x->regulator,
  2033. wsa884x->num_supplies);
  2034. err:
  2035. swr_set_dev_data(pdev, NULL);
  2036. return ret;
  2037. }
  2038. static int wsa884x_swr_remove(struct swr_device *pdev)
  2039. {
  2040. struct wsa884x_priv *wsa884x;
  2041. wsa884x = swr_get_dev_data(pdev);
  2042. if (!wsa884x) {
  2043. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  2044. return -EINVAL;
  2045. }
  2046. if (wsa884x->register_notifier)
  2047. wsa884x->register_notifier(wsa884x->handle,
  2048. &wsa884x->parent_nblock, false);
  2049. #ifdef CONFIG_DEBUG_FS
  2050. debugfs_remove_recursive(wsa884x->debugfs_dent);
  2051. wsa884x->debugfs_dent = NULL;
  2052. #endif
  2053. mutex_destroy(&wsa884x->res_lock);
  2054. snd_soc_unregister_component(&pdev->dev);
  2055. if (wsa884x->dai_driver) {
  2056. kfree(wsa884x->dai_driver->name);
  2057. kfree(wsa884x->dai_driver->playback.stream_name);
  2058. kfree(wsa884x->dai_driver);
  2059. }
  2060. if (wsa884x->driver) {
  2061. kfree(wsa884x->driver->name);
  2062. kfree(wsa884x->driver);
  2063. }
  2064. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2065. wsa884x->regulator,
  2066. wsa884x->num_supplies);
  2067. swr_set_dev_data(pdev, NULL);
  2068. return 0;
  2069. }
  2070. #ifdef CONFIG_PM_SLEEP
  2071. static int wsa884x_swr_suspend(struct device *dev)
  2072. {
  2073. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2074. if (!wsa884x) {
  2075. dev_err_ratelimited(dev, "%s: wsa884x private data is NULL\n", __func__);
  2076. return -EINVAL;
  2077. }
  2078. dev_dbg(dev, "%s: system suspend\n", __func__);
  2079. if (wsa884x->dapm_bias_off ||
  2080. (snd_soc_component_get_bias_level(wsa884x->component) ==
  2081. SND_SOC_BIAS_OFF)) {
  2082. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2083. wsa884x->regulator,
  2084. wsa884x->num_supplies,
  2085. true);
  2086. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2087. }
  2088. return 0;
  2089. }
  2090. static int wsa884x_swr_resume(struct device *dev)
  2091. {
  2092. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2093. if (!wsa884x) {
  2094. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2095. return -EINVAL;
  2096. }
  2097. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  2098. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2099. wsa884x->regulator,
  2100. wsa884x->num_supplies,
  2101. false);
  2102. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2103. }
  2104. dev_dbg(dev, "%s: system resume\n", __func__);
  2105. return 0;
  2106. }
  2107. #endif /* CONFIG_PM_SLEEP */
  2108. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  2109. .suspend_late = wsa884x_swr_suspend,
  2110. .resume_early = wsa884x_swr_resume,
  2111. };
  2112. static const struct swr_device_id wsa884x_swr_id[] = {
  2113. {"wsa884x", 0},
  2114. {"wsa884x_2", 0},
  2115. {}
  2116. };
  2117. static const struct of_device_id wsa884x_swr_dt_match[] = {
  2118. {
  2119. .compatible = "qcom,wsa884x",
  2120. },
  2121. {
  2122. .compatible = "qcom,wsa884x_2",
  2123. },
  2124. {}
  2125. };
  2126. static struct swr_driver wsa884x_swr_driver = {
  2127. .driver = {
  2128. .name = "wsa884x",
  2129. .owner = THIS_MODULE,
  2130. .pm = &wsa884x_swr_pm_ops,
  2131. .of_match_table = wsa884x_swr_dt_match,
  2132. },
  2133. .probe = wsa884x_swr_probe,
  2134. .remove = wsa884x_swr_remove,
  2135. .id_table = wsa884x_swr_id,
  2136. };
  2137. static int __init wsa884x_swr_init(void)
  2138. {
  2139. return swr_driver_register(&wsa884x_swr_driver);
  2140. }
  2141. static void __exit wsa884x_swr_exit(void)
  2142. {
  2143. swr_driver_unregister(&wsa884x_swr_driver);
  2144. }
  2145. module_init(wsa884x_swr_init);
  2146. module_exit(wsa884x_swr_exit);
  2147. MODULE_DESCRIPTION("WSA884x codec driver");
  2148. MODULE_LICENSE("GPL v2");