wsa884x.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/device.h>
  11. #include <linux/printk.h>
  12. #include <linux/bitops.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/regmap.h>
  21. #include <linux/debugfs.h>
  22. #include <soc/soundwire.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/tlv.h>
  28. #include <asoc/msm-cdc-pinctrl.h>
  29. #include <asoc/msm-cdc-supply.h>
  30. #include "wsa884x-registers.h"
  31. #include "wsa884x.h"
  32. #include "internal.h"
  33. #include "asoc/bolero-slave-internal.h"
  34. #include <linux/qti-regmap-debugfs.h>
  35. #define T1_TEMP -10
  36. #define T2_TEMP 150
  37. #define LOW_TEMP_THRESHOLD 5
  38. #define HIGH_TEMP_THRESHOLD 45
  39. #define TEMP_INVALID 0xFFFF
  40. #define WSA884X_TEMP_RETRY 3
  41. #define WSA884X_IRQ_RETRY 2
  42. #define PBR_MAX_VOLTAGE 20
  43. #define PBR_MAX_CODE 255
  44. #define WSA884X_IDLE_DETECT_NG_BLOCK_MASK 0x38
  45. #define MAX_NAME_LEN 40
  46. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  47. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  48. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  49. SNDRV_PCM_RATE_384000)
  50. /* Fractional Rates */
  51. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  52. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  53. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  54. SNDRV_PCM_FMTBIT_S24_LE |\
  55. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  56. #define REG_FIELD_VALUE(register_name, field_name, value) \
  57. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  58. value << FIELD_SHIFT(register_name, field_name)
  59. enum {
  60. IDLE_DETECT,
  61. NG1,
  62. NG2,
  63. NG3,
  64. };
  65. struct wsa_temp_register {
  66. u8 d1_msb;
  67. u8 d1_lsb;
  68. u8 d2_msb;
  69. u8 d2_lsb;
  70. u8 dmeas_msb;
  71. u8 dmeas_lsb;
  72. };
  73. enum {
  74. COMP_OFFSET0,
  75. COMP_OFFSET1,
  76. COMP_OFFSET2,
  77. COMP_OFFSET3,
  78. COMP_OFFSET4,
  79. };
  80. #define WSA884X_VTH_TO_REG(vth) \
  81. ((vth) != 0 ? (((vth) - 150) * PBR_MAX_CODE / (PBR_MAX_VOLTAGE * 100) + 1) : 0)
  82. struct wsa_reg_mask_val {
  83. u16 reg;
  84. u8 mask;
  85. u8 val;
  86. };
  87. static const struct wsa_reg_mask_val reg_init[] = {
  88. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  89. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  90. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  91. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  92. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  93. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  94. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  95. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  96. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  97. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  98. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  99. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  100. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  101. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  102. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  103. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  104. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  105. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  106. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  107. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  108. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  109. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  110. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  111. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  112. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  113. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  114. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  115. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  116. {REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
  117. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  118. {REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
  119. {REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
  120. {REG_FIELD_VALUE(VBAT_CAL_CTL, RESERVE, 0x02)},
  121. {REG_FIELD_VALUE(REF_CTRL, BG_RDY_SEL, 0x01)},
  122. {REG_FIELD_VALUE(ZX_CTRL1, ZX_DET_SW_SEL, 0x03)},
  123. };
  124. static int wsa884x_handle_post_irq(void *data);
  125. static int wsa884x_get_temperature(struct snd_soc_component *component,
  126. int *temp);
  127. enum {
  128. WSA8840 = 0,
  129. WSA8845 = 5,
  130. WSA8845H = 0xC,
  131. };
  132. enum {
  133. SPKR_STATUS = 0,
  134. WSA_SUPPLIES_LPM_MODE,
  135. SPKR_ADIE_LB,
  136. };
  137. enum {
  138. WSA884X_IRQ_INT_SAF2WAR = 0,
  139. WSA884X_IRQ_INT_WAR2SAF,
  140. WSA884X_IRQ_INT_DISABLE,
  141. WSA884X_IRQ_INT_OCP,
  142. WSA884X_IRQ_INT_CLIP,
  143. WSA884X_IRQ_INT_PDM_WD,
  144. WSA884X_IRQ_INT_CLK_WD,
  145. WSA884X_IRQ_INT_INTR_PIN,
  146. WSA884X_IRQ_INT_UVLO,
  147. WSA884X_IRQ_INT_PA_ON_ERR,
  148. WSA884X_NUM_IRQS,
  149. };
  150. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  151. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  152. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  153. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  154. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  155. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  156. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  157. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  158. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  159. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  160. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  161. };
  162. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  163. .name = "wsa884x",
  164. .irqs = wsa884x_irqs,
  165. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  166. .num_regs = 2,
  167. .status_base = WSA884X_INTR_STATUS0,
  168. .mask_base = WSA884X_INTR_MASK0,
  169. .type_base = WSA884X_INTR_LEVEL0,
  170. .ack_base = WSA884X_INTR_CLEAR0,
  171. .use_ack = 1,
  172. .runtime_pm = false,
  173. .handle_post_irq = wsa884x_handle_post_irq,
  174. .irq_drv_data = NULL,
  175. };
  176. static int wsa884x_handle_post_irq(void *data)
  177. {
  178. struct wsa884x_priv *wsa884x = data;
  179. u32 sts1 = 0, sts2 = 0;
  180. int retry = WSA884X_IRQ_RETRY;
  181. struct snd_soc_component *component = NULL;
  182. if (!wsa884x)
  183. return IRQ_NONE;
  184. component = wsa884x->component;
  185. if (!wsa884x->pa_mute) {
  186. do {
  187. wsa884x->pa_mute = 0;
  188. snd_soc_component_update_bits(component,
  189. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  190. usleep_range(1000, 1100);
  191. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  192. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  193. wsa884x->swr_slave->slave_irq_pending =
  194. ((sts1 || sts2) ? true : false);
  195. pr_debug("%s: IRQs Sts0: %x, Sts1: %x\n", __func__,
  196. sts1, sts2);
  197. if (wsa884x->swr_slave->slave_irq_pending) {
  198. pr_debug("%s: IRQ retries left: %0d\n",
  199. __func__, retry);
  200. snd_soc_component_update_bits(component,
  201. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  202. wsa884x->pa_mute = 1;
  203. if (retry--)
  204. usleep_range(1000, 1100);
  205. } else {
  206. break;
  207. }
  208. } while (retry);
  209. }
  210. return IRQ_HANDLED;
  211. }
  212. #ifdef CONFIG_DEBUG_FS
  213. static int codec_debug_open(struct inode *inode, struct file *file)
  214. {
  215. file->private_data = inode->i_private;
  216. return 0;
  217. }
  218. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  219. {
  220. char *token;
  221. int base, cnt;
  222. token = strsep(&buf, " ");
  223. for (cnt = 0; cnt < num_of_par; cnt++) {
  224. if (token) {
  225. if ((token[1] == 'x') || (token[1] == 'X'))
  226. base = 16;
  227. else
  228. base = 10;
  229. if (kstrtou32(token, base, &param1[cnt]) != 0)
  230. return -EINVAL;
  231. token = strsep(&buf, " ");
  232. } else {
  233. return -EINVAL;
  234. }
  235. }
  236. return 0;
  237. }
  238. static bool is_swr_slave_reg_readable(int reg)
  239. {
  240. int ret = true;
  241. if (((reg > 0x46) && (reg < 0x4A)) ||
  242. ((reg > 0x4A) && (reg < 0x50)) ||
  243. ((reg > 0x55) && (reg < 0x60)) ||
  244. ((reg > 0x60) && (reg < 0x70)) ||
  245. ((reg > 0x70) && (reg < 0xC0)) ||
  246. ((reg > 0xC1) && (reg < 0xC8)) ||
  247. ((reg > 0xC8) && (reg < 0xD0)) ||
  248. ((reg > 0xD0) && (reg < 0xE0)) ||
  249. ((reg > 0xE0) && (reg < 0xF0)) ||
  250. ((reg > 0xF0) && (reg < 0x100)) ||
  251. ((reg > 0x105) && (reg < 0x120)) ||
  252. ((reg > 0x205) && (reg < 0x220)) ||
  253. ((reg > 0x305) && (reg < 0x320)) ||
  254. ((reg > 0x405) && (reg < 0x420)) ||
  255. ((reg > 0x505) && (reg < 0x520)) ||
  256. ((reg > 0x605) && (reg < 0x620)) ||
  257. ((reg > 0x127) && (reg < 0x130)) ||
  258. ((reg > 0x227) && (reg < 0x230)) ||
  259. ((reg > 0x327) && (reg < 0x330)) ||
  260. ((reg > 0x427) && (reg < 0x430)) ||
  261. ((reg > 0x527) && (reg < 0x530)) ||
  262. ((reg > 0x627) && (reg < 0x630)) ||
  263. ((reg > 0x137) && (reg < 0x200)) ||
  264. ((reg > 0x237) && (reg < 0x300)) ||
  265. ((reg > 0x337) && (reg < 0x400)) ||
  266. ((reg > 0x437) && (reg < 0x500)) ||
  267. ((reg > 0x537) && (reg < 0x600)) ||
  268. ((reg > 0x637) && (reg < 0xF00)) ||
  269. ((reg > 0xF05) && (reg < 0xF20)) ||
  270. ((reg > 0xF25) && (reg < 0xF30)) ||
  271. ((reg > 0xF35) && (reg < 0x2000)))
  272. ret = false;
  273. return ret;
  274. }
  275. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  276. size_t count, loff_t *ppos)
  277. {
  278. int i, reg_val, len;
  279. ssize_t total = 0;
  280. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  281. if (!ubuf || !ppos)
  282. return 0;
  283. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  284. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  285. if (!is_swr_slave_reg_readable(i))
  286. continue;
  287. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  288. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  289. (reg_val & 0xFF));
  290. if (len < 0) {
  291. pr_err_ratelimited("%s: fail to fill the buffer\n", __func__);
  292. total = -EFAULT;
  293. goto copy_err;
  294. }
  295. if ((total + len) >= count - 1)
  296. break;
  297. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  298. pr_err_ratelimited("%s: fail to copy reg dump\n", __func__);
  299. total = -EFAULT;
  300. goto copy_err;
  301. }
  302. total += len;
  303. *ppos += len;
  304. }
  305. copy_err:
  306. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  307. return total;
  308. }
  309. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  310. size_t count, loff_t *ppos)
  311. {
  312. struct swr_device *pdev;
  313. if (!count || !file || !ppos || !ubuf)
  314. return -EINVAL;
  315. pdev = file->private_data;
  316. if (!pdev)
  317. return -EINVAL;
  318. if (*ppos < 0)
  319. return -EINVAL;
  320. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  321. }
  322. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  323. size_t count, loff_t *ppos)
  324. {
  325. char lbuf[SWR_SLV_RD_BUF_LEN];
  326. struct swr_device *pdev = NULL;
  327. struct wsa884x_priv *wsa884x = NULL;
  328. if (!count || !file || !ppos || !ubuf)
  329. return -EINVAL;
  330. pdev = file->private_data;
  331. if (!pdev)
  332. return -EINVAL;
  333. wsa884x = swr_get_dev_data(pdev);
  334. if (!wsa884x)
  335. return -EINVAL;
  336. if (*ppos < 0)
  337. return -EINVAL;
  338. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  339. (wsa884x->read_data & 0xFF));
  340. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  341. strnlen(lbuf, 7));
  342. }
  343. static ssize_t codec_debug_peek_write(struct file *file,
  344. const char __user *ubuf, size_t cnt, loff_t *ppos)
  345. {
  346. char lbuf[SWR_SLV_WR_BUF_LEN];
  347. int rc = 0;
  348. u32 param[5];
  349. struct swr_device *pdev = NULL;
  350. struct wsa884x_priv *wsa884x = NULL;
  351. if (!cnt || !file || !ppos || !ubuf)
  352. return -EINVAL;
  353. pdev = file->private_data;
  354. if (!pdev)
  355. return -EINVAL;
  356. wsa884x = swr_get_dev_data(pdev);
  357. if (!wsa884x)
  358. return -EINVAL;
  359. if (*ppos < 0)
  360. return -EINVAL;
  361. if (cnt > sizeof(lbuf) - 1)
  362. return -EINVAL;
  363. rc = copy_from_user(lbuf, ubuf, cnt);
  364. if (rc)
  365. return -EFAULT;
  366. lbuf[cnt] = '\0';
  367. rc = get_parameters(lbuf, param, 1);
  368. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  369. return -EINVAL;
  370. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  371. if (rc == 0)
  372. rc = cnt;
  373. else
  374. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  375. return rc;
  376. }
  377. static ssize_t codec_debug_write(struct file *file,
  378. const char __user *ubuf, size_t cnt, loff_t *ppos)
  379. {
  380. char lbuf[SWR_SLV_WR_BUF_LEN];
  381. int rc = 0;
  382. u32 param[5];
  383. struct swr_device *pdev;
  384. if (!file || !ppos || !ubuf)
  385. return -EINVAL;
  386. pdev = file->private_data;
  387. if (!pdev)
  388. return -EINVAL;
  389. if (cnt > sizeof(lbuf) - 1)
  390. return -EINVAL;
  391. rc = copy_from_user(lbuf, ubuf, cnt);
  392. if (rc)
  393. return -EFAULT;
  394. lbuf[cnt] = '\0';
  395. rc = get_parameters(lbuf, param, 2);
  396. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  397. (param[1] <= 0xFF) && (rc == 0)))
  398. return -EINVAL;
  399. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  400. if (rc == 0)
  401. rc = cnt;
  402. else
  403. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  404. return rc;
  405. }
  406. static const struct file_operations codec_debug_write_ops = {
  407. .open = codec_debug_open,
  408. .write = codec_debug_write,
  409. };
  410. static const struct file_operations codec_debug_read_ops = {
  411. .open = codec_debug_open,
  412. .read = codec_debug_read,
  413. .write = codec_debug_peek_write,
  414. };
  415. static const struct file_operations codec_debug_dump_ops = {
  416. .open = codec_debug_open,
  417. .read = codec_debug_dump,
  418. };
  419. #endif
  420. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  421. {
  422. mutex_lock(&wsa884x->res_lock);
  423. regcache_mark_dirty(wsa884x->regmap);
  424. regcache_sync(wsa884x->regmap);
  425. mutex_unlock(&wsa884x->res_lock);
  426. }
  427. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  428. {
  429. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  430. __func__, irq);
  431. return IRQ_HANDLED;
  432. }
  433. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  434. {
  435. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  436. __func__, irq);
  437. return IRQ_HANDLED;
  438. }
  439. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  440. {
  441. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  442. __func__, irq);
  443. return IRQ_HANDLED;
  444. }
  445. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  446. {
  447. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  448. __func__, irq);
  449. return IRQ_HANDLED;
  450. }
  451. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  452. {
  453. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  454. __func__, irq);
  455. return IRQ_HANDLED;
  456. }
  457. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  458. {
  459. struct wsa884x_priv *wsa884x = data;
  460. struct snd_soc_component *component = NULL;
  461. if (!wsa884x)
  462. return IRQ_NONE;
  463. component = wsa884x->component;
  464. snd_soc_component_update_bits(component,
  465. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  466. snd_soc_component_update_bits(component,
  467. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  468. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  469. __func__, irq);
  470. return IRQ_HANDLED;
  471. }
  472. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  473. {
  474. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  475. __func__, irq);
  476. return IRQ_HANDLED;
  477. }
  478. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  479. {
  480. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  481. __func__, irq);
  482. return IRQ_HANDLED;
  483. }
  484. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  485. {
  486. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  487. __func__, irq);
  488. return IRQ_HANDLED;
  489. }
  490. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  491. {
  492. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  493. struct wsa884x_priv *wsa884x = data;
  494. struct snd_soc_component *component = NULL;
  495. if (!wsa884x)
  496. return IRQ_NONE;
  497. component = wsa884x->component;
  498. if (!component)
  499. return IRQ_NONE;
  500. snd_soc_component_update_bits(component,
  501. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  502. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  503. & 0x1F);
  504. if (pa_fsm_sta)
  505. pa_fsm_err = snd_soc_component_read(component,
  506. WSA884X_PA_FSM_ERR_COND0);
  507. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  508. __func__, irq);
  509. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  510. 0x10, 0x00);
  511. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  512. 0x10, 0x10);
  513. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  514. 0x10, 0x00);
  515. return IRQ_HANDLED;
  516. }
  517. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  518. {
  519. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  520. u8 igain;
  521. u8 vgain;
  522. switch (wsa884x->bat_cfg) {
  523. case CONFIG_1S:
  524. case EXT_1S:
  525. switch (wsa884x->system_gain) {
  526. case G_21_DB:
  527. wsa884x->comp_offset = COMP_OFFSET0;
  528. wsa884x->min_gain = G_0_DB;
  529. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  530. break;
  531. case G_19P5_DB:
  532. wsa884x->comp_offset = COMP_OFFSET1;
  533. wsa884x->min_gain = G_M1P5_DB;
  534. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  535. break;
  536. case G_18_DB:
  537. wsa884x->comp_offset = COMP_OFFSET2;
  538. wsa884x->min_gain = G_M3_DB;
  539. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  540. break;
  541. case G_16P5_DB:
  542. wsa884x->comp_offset = COMP_OFFSET3;
  543. wsa884x->min_gain = G_M4P5_DB;
  544. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  545. break;
  546. default:
  547. wsa884x->comp_offset = COMP_OFFSET4;
  548. wsa884x->min_gain = G_M6_DB;
  549. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  550. break;
  551. }
  552. break;
  553. case CONFIG_3S:
  554. case EXT_3S:
  555. wsa884x->comp_offset = COMP_OFFSET0;
  556. wsa884x->min_gain = G_7P5_DB;
  557. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  558. break;
  559. case EXT_ABOVE_3S:
  560. wsa884x->comp_offset = COMP_OFFSET0;
  561. wsa884x->min_gain = G_12_DB;
  562. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  563. break;
  564. default:
  565. wsa884x->comp_offset = COMP_OFFSET0;
  566. wsa884x->min_gain = G_0_DB;
  567. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  568. break;
  569. }
  570. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  571. vgain = vsense_gain_data[wsa884x->system_gain];
  572. snd_soc_component_update_bits(component,
  573. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  574. snd_soc_component_update_bits(component,
  575. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  576. snd_soc_component_update_bits(component,
  577. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  578. if (wsa884x->comp_enable) {
  579. snd_soc_component_update_bits(component,
  580. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  581. wsa884x->comp_offset));
  582. snd_soc_component_update_bits(component,
  583. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  584. } else {
  585. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->pa_gain];
  586. snd_soc_component_update_bits(component,
  587. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  588. snd_soc_component_update_bits(component,
  589. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, wsa884x->pa_gain));
  590. }
  591. return 0;
  592. }
  593. static int wsa884x_set_pbr_parameters(struct snd_soc_component *component)
  594. {
  595. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  596. int vth1_reg_val;
  597. int vth2_reg_val;
  598. int vth3_reg_val;
  599. int vth4_reg_val;
  600. int vth5_reg_val;
  601. int vth6_reg_val;
  602. int vth7_reg_val;
  603. int vth8_reg_val;
  604. int vth9_reg_val;
  605. int vth10_reg_val;
  606. int vth11_reg_val;
  607. int vth12_reg_val;
  608. int vth13_reg_val;
  609. int vth14_reg_val;
  610. int vth15_reg_val;
  611. int vth1_val = pbr_vth1_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  612. int vth2_val = pbr_vth2_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  613. int vth3_val = pbr_vth3_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  614. int vth4_val = pbr_vth4_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  615. int vth5_val = pbr_vth5_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  616. int vth6_val = pbr_vth6_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  617. int vth7_val = pbr_vth7_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  618. int vth8_val = pbr_vth8_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  619. int vth9_val = pbr_vth9_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  620. int vth10_val = pbr_vth10_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  621. int vth11_val = pbr_vth11_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  622. int vth12_val = pbr_vth12_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  623. int vth13_val = pbr_vth13_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  624. int vth14_val = pbr_vth14_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  625. int vth15_val = pbr_vth15_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  626. vth1_reg_val = WSA884X_VTH_TO_REG(vth1_val);
  627. vth2_reg_val = WSA884X_VTH_TO_REG(vth2_val);
  628. vth3_reg_val = WSA884X_VTH_TO_REG(vth3_val);
  629. vth4_reg_val = WSA884X_VTH_TO_REG(vth4_val);
  630. vth5_reg_val = WSA884X_VTH_TO_REG(vth5_val);
  631. vth6_reg_val = WSA884X_VTH_TO_REG(vth6_val);
  632. vth7_reg_val = WSA884X_VTH_TO_REG(vth7_val);
  633. vth8_reg_val = WSA884X_VTH_TO_REG(vth8_val);
  634. vth9_reg_val = WSA884X_VTH_TO_REG(vth9_val);
  635. vth10_reg_val = WSA884X_VTH_TO_REG(vth10_val);
  636. vth11_reg_val = WSA884X_VTH_TO_REG(vth11_val);
  637. vth12_reg_val = WSA884X_VTH_TO_REG(vth12_val);
  638. vth13_reg_val = WSA884X_VTH_TO_REG(vth13_val);
  639. vth14_reg_val = WSA884X_VTH_TO_REG(vth14_val);
  640. vth15_reg_val = WSA884X_VTH_TO_REG(vth15_val);
  641. snd_soc_component_write(component, WSA884X_CLSH_VTH1, vth1_reg_val);
  642. snd_soc_component_write(component, WSA884X_CLSH_VTH2, vth2_reg_val);
  643. snd_soc_component_write(component, WSA884X_CLSH_VTH3, vth3_reg_val);
  644. snd_soc_component_write(component, WSA884X_CLSH_VTH4, vth4_reg_val);
  645. snd_soc_component_write(component, WSA884X_CLSH_VTH5, vth5_reg_val);
  646. snd_soc_component_write(component, WSA884X_CLSH_VTH6, vth6_reg_val);
  647. snd_soc_component_write(component, WSA884X_CLSH_VTH7, vth7_reg_val);
  648. snd_soc_component_write(component, WSA884X_CLSH_VTH8, vth8_reg_val);
  649. snd_soc_component_write(component, WSA884X_CLSH_VTH9, vth9_reg_val);
  650. snd_soc_component_write(component, WSA884X_CLSH_VTH10, vth10_reg_val);
  651. snd_soc_component_write(component, WSA884X_CLSH_VTH11, vth11_reg_val);
  652. snd_soc_component_write(component, WSA884X_CLSH_VTH12, vth12_reg_val);
  653. snd_soc_component_write(component, WSA884X_CLSH_VTH13, vth13_reg_val);
  654. snd_soc_component_write(component, WSA884X_CLSH_VTH14, vth14_reg_val);
  655. snd_soc_component_write(component, WSA884X_CLSH_VTH15, vth15_reg_val);
  656. return 0;
  657. }
  658. static void wsa_noise_gate_write(struct snd_soc_component *component,
  659. int imode)
  660. {
  661. switch (imode) {
  662. case NG1:
  663. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  664. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x30);
  665. break;
  666. case NG2:
  667. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  668. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x20);
  669. break;
  670. case NG3:
  671. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  672. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x10);
  673. break;
  674. default:
  675. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  676. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x8);
  677. break;
  678. }
  679. }
  680. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  681. struct snd_ctl_elem_value *ucontrol)
  682. {
  683. struct snd_soc_component *component =
  684. snd_soc_kcontrol_component(kcontrol);
  685. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  686. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  687. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  688. wsa884x->dev_mode);
  689. return 0;
  690. }
  691. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  692. struct snd_ctl_elem_value *ucontrol)
  693. {
  694. struct snd_soc_component *component =
  695. snd_soc_kcontrol_component(kcontrol);
  696. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  697. int dev_mode;
  698. int wsa_dev_index;
  699. if ((ucontrol->value.integer.value[0] >= SPEAKER) &&
  700. (ucontrol->value.integer.value[0] < MAX_DEV_MODE))
  701. dev_mode = ucontrol->value.integer.value[0];
  702. else
  703. return -EINVAL;
  704. dev_dbg(component->dev, "%s: Dev Mode current: %d, new: %d\n",
  705. __func__, wsa884x->dev_mode, dev_mode);
  706. /* Check if input parameter is in range */
  707. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  708. if ((dev_mode + wsa_dev_index * 2) < (MAX_DEV_MODE * 2)) {
  709. wsa884x->dev_mode = dev_mode;
  710. wsa884x->system_gain = wsa884x->sys_gains[dev_mode + wsa_dev_index * 2];
  711. } else {
  712. return -EINVAL;
  713. }
  714. return 0;
  715. }
  716. static const char * const wsa_pa_gain_text[] = {
  717. "G_21_DB", "G_19P5_DB" "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB",
  718. "G_12_DB", "G_10P5_DB", "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB",
  719. "G_3_DB", "G_1P5_DB", "G_0_DB", "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB"
  720. "G_M6_DB", "G_M7P5_DB", "G_M9_DB"
  721. };
  722. static const struct soc_enum wsa_pa_gain_enum =
  723. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  724. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  725. struct snd_ctl_elem_value *ucontrol)
  726. {
  727. struct snd_soc_component *component =
  728. snd_soc_kcontrol_component(kcontrol);
  729. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  730. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  731. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  732. wsa884x->pa_gain);
  733. return 0;
  734. }
  735. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  736. struct snd_ctl_elem_value *ucontrol)
  737. {
  738. struct snd_soc_component *component =
  739. snd_soc_kcontrol_component(kcontrol);
  740. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  741. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  742. __func__, ucontrol->value.integer.value[0]);
  743. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  744. return 0;
  745. }
  746. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  747. struct snd_ctl_elem_value *ucontrol)
  748. {
  749. struct snd_soc_component *component =
  750. snd_soc_kcontrol_component(kcontrol);
  751. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  752. int temp = 0;
  753. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  754. temp = wsa884x->curr_temp;
  755. else
  756. wsa884x_get_temperature(component, &temp);
  757. ucontrol->value.integer.value[0] = temp;
  758. return 0;
  759. }
  760. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  761. void *file_private_data, struct file *file,
  762. char __user *buf, size_t count, loff_t pos)
  763. {
  764. struct wsa884x_priv *wsa884x;
  765. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  766. int len = 0;
  767. wsa884x = (struct wsa884x_priv *) entry->private_data;
  768. if (!wsa884x) {
  769. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  770. return -EINVAL;
  771. }
  772. switch (wsa884x->version) {
  773. case WSA884X_VERSION_1_0:
  774. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  775. break;
  776. default:
  777. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  778. break;
  779. }
  780. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  781. }
  782. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  783. .read = wsa884x_codec_version_read,
  784. };
  785. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  786. void *file_private_data,
  787. struct file *file,
  788. char __user *buf, size_t count,
  789. loff_t pos)
  790. {
  791. struct wsa884x_priv *wsa884x;
  792. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  793. int len = 0;
  794. wsa884x = (struct wsa884x_priv *) entry->private_data;
  795. if (!wsa884x) {
  796. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  797. return -EINVAL;
  798. }
  799. switch (wsa884x->variant) {
  800. case WSA8840:
  801. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  802. break;
  803. case WSA8845:
  804. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  805. break;
  806. case WSA8845H:
  807. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  808. break;
  809. default:
  810. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  811. break;
  812. }
  813. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  814. }
  815. static struct snd_info_entry_ops wsa884x_variant_ops = {
  816. .read = wsa884x_variant_read,
  817. };
  818. /*
  819. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  820. * @codec_root: The parent directory
  821. * @component: Codec instance
  822. *
  823. * Creates wsa884x module and version entry under the given
  824. * parent directory.
  825. *
  826. * Return: 0 on success or negative error code on failure.
  827. */
  828. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  829. struct snd_soc_component *component)
  830. {
  831. struct snd_info_entry *version_entry;
  832. struct snd_info_entry *variant_entry;
  833. struct wsa884x_priv *wsa884x;
  834. struct snd_soc_card *card;
  835. char name[80];
  836. if (!codec_root || !component)
  837. return -EINVAL;
  838. wsa884x = snd_soc_component_get_drvdata(component);
  839. if (wsa884x->entry) {
  840. dev_dbg(wsa884x->dev,
  841. "%s:wsa884x module already created\n", __func__);
  842. return 0;
  843. }
  844. card = component->card;
  845. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  846. wsa884x->swr_slave->addr);
  847. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  848. (const char *)name,
  849. codec_root);
  850. if (!wsa884x->entry) {
  851. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  852. __func__);
  853. return -ENOMEM;
  854. }
  855. wsa884x->entry->mode = S_IFDIR | 0555;
  856. if (snd_info_register(wsa884x->entry) < 0) {
  857. snd_info_free_entry(wsa884x->entry);
  858. return -ENOMEM;
  859. }
  860. version_entry = snd_info_create_card_entry(card->snd_card,
  861. "version",
  862. wsa884x->entry);
  863. if (!version_entry) {
  864. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  865. __func__);
  866. snd_info_free_entry(wsa884x->entry);
  867. return -ENOMEM;
  868. }
  869. version_entry->private_data = wsa884x;
  870. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  871. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  872. version_entry->c.ops = &wsa884x_codec_info_ops;
  873. if (snd_info_register(version_entry) < 0) {
  874. snd_info_free_entry(version_entry);
  875. snd_info_free_entry(wsa884x->entry);
  876. return -ENOMEM;
  877. }
  878. wsa884x->version_entry = version_entry;
  879. variant_entry = snd_info_create_card_entry(card->snd_card,
  880. "variant",
  881. wsa884x->entry);
  882. if (!variant_entry) {
  883. dev_dbg(component->dev,
  884. "%s: failed to create wsa884x variant entry\n",
  885. __func__);
  886. snd_info_free_entry(version_entry);
  887. snd_info_free_entry(wsa884x->entry);
  888. return -ENOMEM;
  889. }
  890. variant_entry->private_data = wsa884x;
  891. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  892. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  893. variant_entry->c.ops = &wsa884x_variant_ops;
  894. if (snd_info_register(variant_entry) < 0) {
  895. snd_info_free_entry(variant_entry);
  896. snd_info_free_entry(version_entry);
  897. snd_info_free_entry(wsa884x->entry);
  898. return -ENOMEM;
  899. }
  900. wsa884x->variant_entry = variant_entry;
  901. return 0;
  902. }
  903. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  904. /*
  905. * wsa884x_codec_get_dev_num - returns swr device number
  906. * @component: Codec instance
  907. *
  908. * Return: swr device number on success or negative error
  909. * code on failure.
  910. */
  911. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  912. {
  913. struct wsa884x_priv *wsa884x;
  914. if (!component)
  915. return -EINVAL;
  916. wsa884x = snd_soc_component_get_drvdata(component);
  917. if (!wsa884x) {
  918. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  919. return -EINVAL;
  920. }
  921. return wsa884x->swr_slave->dev_num;
  922. }
  923. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  924. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  925. struct snd_ctl_elem_value *ucontrol)
  926. {
  927. struct snd_soc_component *component =
  928. snd_soc_kcontrol_component(kcontrol);
  929. struct wsa884x_priv *wsa884x;
  930. if (!component)
  931. return -EINVAL;
  932. wsa884x = snd_soc_component_get_drvdata(component);
  933. if (!wsa884x) {
  934. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  935. return -EINVAL;
  936. }
  937. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  938. return 0;
  939. }
  940. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  941. struct snd_ctl_elem_value *ucontrol)
  942. {
  943. struct snd_soc_component *component =
  944. snd_soc_kcontrol_component(kcontrol);
  945. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  946. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  947. return 0;
  948. }
  949. /*
  950. * wsa884x_validate_dt_configuration_params - returns 1 or 0
  951. * Return: 0 Valid configuration, 1 Invalid configuration
  952. */
  953. static bool wsa884x_validate_dt_configuration_params(struct snd_soc_component *component,
  954. u8 irload, u8 ibat_cfg_dts, u8 isystem_gain)
  955. {
  956. u8 bat_cfg_reg;
  957. bool is_invalid_flag = true;
  958. bat_cfg_reg = snd_soc_component_read(component, WSA884X_VPHX_SYS_EN_STATUS);
  959. if ((ibat_cfg_dts == EXT_1S) || (ibat_cfg_dts == EXT_2S) || (ibat_cfg_dts == EXT_3S))
  960. ibat_cfg_dts = EXT_ABOVE_3S;
  961. if ((WSA_4_OHMS <= irload && irload < WSA_MAX_OHMS) &&
  962. (G_21_DB <= isystem_gain && isystem_gain < G_MAX_DB) &&
  963. (EXT_ABOVE_3S <= ibat_cfg_dts && ibat_cfg_dts < CONFIG_MAX) &&
  964. (ibat_cfg_dts == bat_cfg_reg))
  965. is_invalid_flag = false;
  966. return is_invalid_flag;
  967. }
  968. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  969. struct snd_ctl_elem_value *ucontrol)
  970. {
  971. struct snd_soc_component *component =
  972. snd_soc_kcontrol_component(kcontrol);
  973. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  974. int value = ucontrol->value.integer.value[0];
  975. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  976. __func__, wsa884x->comp_enable, value);
  977. wsa884x->comp_enable = value;
  978. return 0;
  979. }
  980. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  981. struct snd_ctl_elem_value *ucontrol)
  982. {
  983. struct snd_soc_component *component =
  984. snd_soc_kcontrol_component(kcontrol);
  985. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  986. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  987. return 0;
  988. }
  989. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  990. struct snd_ctl_elem_value *ucontrol)
  991. {
  992. struct snd_soc_component *component =
  993. snd_soc_kcontrol_component(kcontrol);
  994. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  995. int value = ucontrol->value.integer.value[0];
  996. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  997. __func__, wsa884x->visense_enable, value);
  998. wsa884x->visense_enable = value;
  999. return 0;
  1000. }
  1001. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  1002. struct snd_ctl_elem_value *ucontrol)
  1003. {
  1004. struct snd_soc_component *component =
  1005. snd_soc_kcontrol_component(kcontrol);
  1006. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1007. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  1008. return 0;
  1009. }
  1010. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  1011. struct snd_ctl_elem_value *ucontrol)
  1012. {
  1013. struct snd_soc_component *component =
  1014. snd_soc_kcontrol_component(kcontrol);
  1015. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1016. int value = ucontrol->value.integer.value[0];
  1017. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  1018. __func__, wsa884x->pbr_enable, value);
  1019. wsa884x->pbr_enable = value;
  1020. return 0;
  1021. }
  1022. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  1023. struct snd_ctl_elem_value *ucontrol)
  1024. {
  1025. struct snd_soc_component *component =
  1026. snd_soc_kcontrol_component(kcontrol);
  1027. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1028. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  1029. return 0;
  1030. }
  1031. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  1032. struct snd_ctl_elem_value *ucontrol)
  1033. {
  1034. struct snd_soc_component *component =
  1035. snd_soc_kcontrol_component(kcontrol);
  1036. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1037. int value = ucontrol->value.integer.value[0];
  1038. dev_dbg(component->dev, "%s: CPS enable current %d, new %d\n",
  1039. __func__, wsa884x->cps_enable, value);
  1040. wsa884x->cps_enable = value;
  1041. return 0;
  1042. }
  1043. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  1044. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  1045. wsa_pa_gain_get, wsa_pa_gain_put),
  1046. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1047. wsa_get_temp, NULL),
  1048. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1049. wsa884x_get_dev_num, NULL),
  1050. SOC_SINGLE_EXT("WSA MODE", SND_SOC_NOPM, 0, 1, 0,
  1051. wsa_dev_mode_get, wsa_dev_mode_put),
  1052. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1053. wsa884x_get_compander, wsa884x_set_compander),
  1054. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  1055. wsa884x_get_visense, wsa884x_set_visense),
  1056. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  1057. wsa884x_get_pbr, wsa884x_set_pbr),
  1058. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  1059. wsa884x_get_cps, wsa884x_set_cps),
  1060. };
  1061. static const struct snd_kcontrol_new swr_dac_port[] = {
  1062. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1063. };
  1064. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  1065. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  1066. u8 *port_type)
  1067. {
  1068. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1069. *port_id = wsa884x->port[port_idx].port_id;
  1070. *num_ch = wsa884x->port[port_idx].num_ch;
  1071. *ch_mask = wsa884x->port[port_idx].ch_mask;
  1072. *ch_rate = wsa884x->port[port_idx].ch_rate;
  1073. *port_type = wsa884x->port[port_idx].port_type;
  1074. return 0;
  1075. }
  1076. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  1077. struct snd_kcontrol *kcontrol, int event)
  1078. {
  1079. struct snd_soc_component *component =
  1080. snd_soc_dapm_to_component(w->dapm);
  1081. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1082. u8 port_id[WSA884X_MAX_SWR_PORTS];
  1083. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  1084. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  1085. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1086. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1087. u8 num_port = 0;
  1088. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1089. event, w->name);
  1090. if (wsa884x == NULL)
  1091. return -EINVAL;
  1092. switch (event) {
  1093. case SND_SOC_DAPM_PRE_PMU:
  1094. wsa884x_set_port(component, SWR_DAC_PORT,
  1095. &port_id[num_port], &num_ch[num_port],
  1096. &ch_mask[num_port], &ch_rate[num_port],
  1097. &port_type[num_port]);
  1098. if (wsa884x->dev_mode == RECEIVER)
  1099. ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
  1100. ++num_port;
  1101. if (wsa884x->comp_enable) {
  1102. wsa884x_set_port(component, SWR_COMP_PORT,
  1103. &port_id[num_port], &num_ch[num_port],
  1104. &ch_mask[num_port], &ch_rate[num_port],
  1105. &port_type[num_port]);
  1106. ++num_port;
  1107. }
  1108. if (wsa884x->pbr_enable) {
  1109. wsa884x_set_port(component, SWR_PBR_PORT,
  1110. &port_id[num_port], &num_ch[num_port],
  1111. &ch_mask[num_port], &ch_rate[num_port],
  1112. &port_type[num_port]);
  1113. ++num_port;
  1114. }
  1115. if (wsa884x->visense_enable) {
  1116. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1117. &port_id[num_port], &num_ch[num_port],
  1118. &ch_mask[num_port], &ch_rate[num_port],
  1119. &port_type[num_port]);
  1120. ++num_port;
  1121. }
  1122. if (wsa884x->cps_enable) {
  1123. wsa884x_set_port(component, SWR_CPS_PORT,
  1124. &port_id[num_port], &num_ch[num_port],
  1125. &ch_mask[num_port], &ch_rate[num_port],
  1126. &port_type[num_port]);
  1127. ++num_port;
  1128. }
  1129. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1130. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1131. &port_type[0]);
  1132. break;
  1133. case SND_SOC_DAPM_POST_PMU:
  1134. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1135. break;
  1136. case SND_SOC_DAPM_PRE_PMD:
  1137. wsa884x_set_port(component, SWR_DAC_PORT,
  1138. &port_id[num_port], &num_ch[num_port],
  1139. &ch_mask[num_port], &ch_rate[num_port],
  1140. &port_type[num_port]);
  1141. ++num_port;
  1142. if (wsa884x->comp_enable) {
  1143. wsa884x_set_port(component, SWR_COMP_PORT,
  1144. &port_id[num_port], &num_ch[num_port],
  1145. &ch_mask[num_port], &ch_rate[num_port],
  1146. &port_type[num_port]);
  1147. ++num_port;
  1148. }
  1149. if (wsa884x->pbr_enable) {
  1150. wsa884x_set_port(component, SWR_PBR_PORT,
  1151. &port_id[num_port], &num_ch[num_port],
  1152. &ch_mask[num_port], &ch_rate[num_port],
  1153. &port_type[num_port]);
  1154. ++num_port;
  1155. }
  1156. if (wsa884x->visense_enable) {
  1157. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1158. &port_id[num_port], &num_ch[num_port],
  1159. &ch_mask[num_port], &ch_rate[num_port],
  1160. &port_type[num_port]);
  1161. ++num_port;
  1162. }
  1163. if (wsa884x->cps_enable) {
  1164. wsa884x_set_port(component, SWR_CPS_PORT,
  1165. &port_id[num_port], &num_ch[num_port],
  1166. &ch_mask[num_port], &ch_rate[num_port],
  1167. &port_type[num_port]);
  1168. ++num_port;
  1169. }
  1170. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1171. &ch_mask[0], &port_type[0]);
  1172. break;
  1173. case SND_SOC_DAPM_POST_PMD:
  1174. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1175. dev_err_ratelimited(component->dev,
  1176. "%s: set num ch failed\n", __func__);
  1177. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1178. wsa884x->swr_slave->dev_num,
  1179. false);
  1180. break;
  1181. default:
  1182. break;
  1183. }
  1184. return 0;
  1185. }
  1186. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1187. struct snd_kcontrol *kcontrol, int event)
  1188. {
  1189. struct snd_soc_component *component =
  1190. snd_soc_dapm_to_component(w->dapm);
  1191. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1192. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1193. switch (event) {
  1194. case SND_SOC_DAPM_POST_PMU:
  1195. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1196. wsa884x->swr_slave->dev_num,
  1197. true);
  1198. wsa884x_set_gain_parameters(component);
  1199. if (wsa884x->dev_mode == SPEAKER) {
  1200. snd_soc_component_update_bits(component,
  1201. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1202. } else {
  1203. snd_soc_component_update_bits(component,
  1204. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1205. snd_soc_component_update_bits(component,
  1206. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1207. snd_soc_component_update_bits(component,
  1208. REG_FIELD_VALUE(PWM_CLK_CTL,
  1209. PWM_CLK_FREQ_SEL, 0x01));
  1210. }
  1211. if (wsa884x->pbr_enable) {
  1212. snd_soc_component_update_bits(component,
  1213. REG_FIELD_VALUE(CURRENT_LIMIT,
  1214. CURRENT_LIMIT_OVRD_EN, 0x00));
  1215. switch (wsa884x->bat_cfg) {
  1216. case CONFIG_1S:
  1217. snd_soc_component_update_bits(component,
  1218. REG_FIELD_VALUE(CURRENT_LIMIT,
  1219. CURRENT_LIMIT, 0x15));
  1220. break;
  1221. case CONFIG_2S:
  1222. snd_soc_component_update_bits(component,
  1223. REG_FIELD_VALUE(CURRENT_LIMIT,
  1224. CURRENT_LIMIT, 0x11));
  1225. break;
  1226. case CONFIG_3S:
  1227. snd_soc_component_update_bits(component,
  1228. REG_FIELD_VALUE(CURRENT_LIMIT,
  1229. CURRENT_LIMIT, 0x0D));
  1230. break;
  1231. }
  1232. } else {
  1233. snd_soc_component_update_bits(component,
  1234. REG_FIELD_VALUE(CURRENT_LIMIT,
  1235. CURRENT_LIMIT_OVRD_EN, 0x01));
  1236. if (wsa884x->system_gain >= G_12_DB)
  1237. snd_soc_component_update_bits(component,
  1238. REG_FIELD_VALUE(CURRENT_LIMIT,
  1239. CURRENT_LIMIT, 0x15));
  1240. else
  1241. snd_soc_component_update_bits(component,
  1242. REG_FIELD_VALUE(CURRENT_LIMIT,
  1243. CURRENT_LIMIT, 0x09));
  1244. }
  1245. /* Force remove group */
  1246. swr_remove_from_group(wsa884x->swr_slave,
  1247. wsa884x->swr_slave->dev_num);
  1248. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask) &&
  1249. !wsa884x->pa_mute)
  1250. snd_soc_component_update_bits(component,
  1251. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1252. break;
  1253. case SND_SOC_DAPM_PRE_PMD:
  1254. snd_soc_component_update_bits(component,
  1255. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1256. snd_soc_component_update_bits(component,
  1257. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1258. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1259. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1260. wsa884x->pa_mute = 0;
  1261. break;
  1262. }
  1263. return 0;
  1264. }
  1265. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1266. SND_SOC_DAPM_INPUT("IN"),
  1267. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1268. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1269. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1270. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1271. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1272. };
  1273. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1274. {"SWR DAC_Port", "Switch", "IN"},
  1275. {"SPKR", NULL, "SWR DAC_Port"},
  1276. };
  1277. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1278. u8 num_port, unsigned int *ch_mask,
  1279. unsigned int *ch_rate, u8 *port_type)
  1280. {
  1281. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1282. int i;
  1283. if (!port || !ch_mask || !ch_rate ||
  1284. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1285. dev_err_ratelimited(component->dev,
  1286. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1287. __func__, port, ch_mask, ch_rate);
  1288. return -EINVAL;
  1289. }
  1290. for (i = 0; i < num_port; i++) {
  1291. wsa884x->port[i].port_id = port[i];
  1292. wsa884x->port[i].ch_mask = ch_mask[i];
  1293. wsa884x->port[i].ch_rate = ch_rate[i];
  1294. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1295. if (port_type)
  1296. wsa884x->port[i].port_type = port_type[i];
  1297. }
  1298. return 0;
  1299. }
  1300. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1301. static void wsa884x_codec_init(struct snd_soc_component *component)
  1302. {
  1303. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1304. int i;
  1305. if (!wsa884x)
  1306. return;
  1307. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1308. snd_soc_component_update_bits(component, reg_init[i].reg,
  1309. reg_init[i].mask, reg_init[i].val);
  1310. wsa_noise_gate_write(component, wsa884x->noise_gate_mode);
  1311. }
  1312. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1313. struct wsa_temp_register *wsa_temp_reg)
  1314. {
  1315. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1316. if (!wsa884x) {
  1317. dev_err_ratelimited(component->dev, "%s: wsa884x is NULL\n", __func__);
  1318. return -EINVAL;
  1319. }
  1320. mutex_lock(&wsa884x->res_lock);
  1321. snd_soc_component_update_bits(component,
  1322. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1323. snd_soc_component_update_bits(component,
  1324. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1325. snd_soc_component_update_bits(component,
  1326. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1327. snd_soc_component_update_bits(component,
  1328. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1329. snd_soc_component_update_bits(component,
  1330. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1331. snd_soc_component_update_bits(component,
  1332. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1333. snd_soc_component_update_bits(component,
  1334. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1335. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1336. WSA884X_TEMP_DIN_MSB);
  1337. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1338. WSA884X_TEMP_DIN_LSB);
  1339. snd_soc_component_update_bits(component,
  1340. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1341. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1342. WSA884X_OTP_REG_1);
  1343. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1344. WSA884X_OTP_REG_2);
  1345. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1346. WSA884X_OTP_REG_3);
  1347. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1348. WSA884X_OTP_REG_4);
  1349. snd_soc_component_update_bits(component,
  1350. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1351. mutex_unlock(&wsa884x->res_lock);
  1352. return 0;
  1353. }
  1354. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1355. int *temp)
  1356. {
  1357. struct wsa_temp_register reg;
  1358. int dmeas, d1, d2;
  1359. int ret = 0;
  1360. int temp_val = 0;
  1361. int t1 = T1_TEMP;
  1362. int t2 = T2_TEMP;
  1363. u8 retry = WSA884X_TEMP_RETRY;
  1364. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1365. if (!wsa884x)
  1366. return -EINVAL;
  1367. do {
  1368. ret = wsa884x_temp_reg_read(component, &reg);
  1369. if (ret) {
  1370. pr_err_ratelimited("%s: temp read failed: %d, current temp: %d\n",
  1371. __func__, ret, wsa884x->curr_temp);
  1372. if (temp)
  1373. *temp = wsa884x->curr_temp;
  1374. return 0;
  1375. }
  1376. /*
  1377. * Temperature register values are expected to be in the
  1378. * following range.
  1379. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1380. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1381. */
  1382. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1383. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1384. reg.d1_lsb == 192)) ||
  1385. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1386. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1387. reg.d2_lsb == 192))) {
  1388. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1389. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1390. reg.d2_lsb);
  1391. }
  1392. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1393. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1394. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1395. if (d1 == d2)
  1396. temp_val = TEMP_INVALID;
  1397. else
  1398. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1399. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1400. temp_val >= HIGH_TEMP_THRESHOLD) {
  1401. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1402. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1403. if (retry--)
  1404. msleep(10);
  1405. } else {
  1406. break;
  1407. }
  1408. } while (retry);
  1409. wsa884x->curr_temp = temp_val;
  1410. if (temp)
  1411. *temp = temp_val;
  1412. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1413. __func__, temp_val, dmeas, d1, d2);
  1414. return ret;
  1415. }
  1416. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1417. {
  1418. char w_name[MAX_NAME_LEN];
  1419. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1420. struct swr_device *dev;
  1421. int variant = 0, version = 0;
  1422. struct snd_soc_dapm_context *dapm =
  1423. snd_soc_component_get_dapm(component);
  1424. if (!wsa884x)
  1425. return -EINVAL;
  1426. if (!component->name_prefix)
  1427. return -EINVAL;
  1428. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1429. dev = wsa884x->swr_slave;
  1430. wsa884x->component = component;
  1431. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1432. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1433. wsa884x->variant = variant;
  1434. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1435. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1436. wsa884x->version = version;
  1437. wsa884x->comp_offset = COMP_OFFSET2;
  1438. wsa884x_codec_init(component);
  1439. wsa884x->global_pa_cnt = 0;
  1440. memset(w_name, 0, sizeof(w_name));
  1441. strlcpy(w_name, wsa884x->dai_driver->playback.stream_name,
  1442. sizeof(w_name));
  1443. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1444. memset(w_name, 0, sizeof(w_name));
  1445. strlcpy(w_name, "IN", sizeof(w_name));
  1446. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1447. memset(w_name, 0, sizeof(w_name));
  1448. strlcpy(w_name, "SWR DAC_Port", sizeof(w_name));
  1449. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1450. memset(w_name, 0, sizeof(w_name));
  1451. strlcpy(w_name, "SPKR", sizeof(w_name));
  1452. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1453. snd_soc_dapm_sync(dapm);
  1454. return 0;
  1455. }
  1456. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1457. {
  1458. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1459. if (!wsa884x)
  1460. return;
  1461. snd_soc_component_exit_regmap(component);
  1462. return;
  1463. }
  1464. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1465. {
  1466. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1467. if (!wsa884x)
  1468. return 0;
  1469. wsa884x->dapm_bias_off = true;
  1470. return 0;
  1471. }
  1472. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1473. {
  1474. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1475. if (!wsa884x)
  1476. return 0;
  1477. wsa884x->dapm_bias_off = false;
  1478. return 0;
  1479. }
  1480. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1481. .name = "",
  1482. .probe = wsa884x_codec_probe,
  1483. .remove = wsa884x_codec_remove,
  1484. .controls = wsa884x_snd_controls,
  1485. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1486. .dapm_widgets = wsa884x_dapm_widgets,
  1487. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1488. .dapm_routes = wsa884x_audio_map,
  1489. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1490. .suspend = wsa884x_soc_codec_suspend,
  1491. .resume = wsa884x_soc_codec_resume,
  1492. };
  1493. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1494. {
  1495. int ret = 0;
  1496. if (enable)
  1497. ret = msm_cdc_pinctrl_select_active_state(
  1498. wsa884x->wsa_rst_np);
  1499. else
  1500. ret = msm_cdc_pinctrl_select_sleep_state(
  1501. wsa884x->wsa_rst_np);
  1502. if (ret != 0)
  1503. dev_err_ratelimited(wsa884x->dev,
  1504. "%s: Failed to turn state %d; ret=%d\n",
  1505. __func__, enable, ret);
  1506. return ret;
  1507. }
  1508. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1509. {
  1510. int ret;
  1511. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1512. if (ret)
  1513. dev_err_ratelimited(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1514. return ret;
  1515. }
  1516. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1517. {
  1518. int ret;
  1519. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1520. if (ret)
  1521. dev_err_ratelimited(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1522. return ret;
  1523. }
  1524. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1525. {
  1526. u8 retry = WSA884X_NUM_RETRY;
  1527. u8 devnum = 0;
  1528. struct swr_device *pdev;
  1529. pdev = wsa884x->swr_slave;
  1530. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1531. /* Retry after 1 msec delay */
  1532. usleep_range(1000, 1100);
  1533. }
  1534. pdev->dev_num = devnum;
  1535. wsa884x_regcache_sync(wsa884x);
  1536. return 0;
  1537. }
  1538. static int wsa884x_event_notify(struct notifier_block *nb,
  1539. unsigned long val, void *ptr)
  1540. {
  1541. u16 event = (val & 0xffff);
  1542. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1543. parent_nblock);
  1544. if (!wsa884x)
  1545. return -EINVAL;
  1546. switch (event) {
  1547. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1548. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1549. snd_soc_component_update_bits(wsa884x->component,
  1550. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1551. wsa884x_swr_down(wsa884x);
  1552. break;
  1553. case BOLERO_SLV_EVT_SSR_UP:
  1554. wsa884x_swr_up(wsa884x);
  1555. /* Add delay to allow enumerate */
  1556. usleep_range(20000, 20010);
  1557. wsa884x_swr_reset(wsa884x);
  1558. dev_err(wsa884x->dev, "%s: BOLERO_SLV_EVT_SSR_UP Called", __func__);
  1559. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1560. wsa884x->swr_wsa_port_params);
  1561. break;
  1562. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1563. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1564. snd_soc_component_update_bits(wsa884x->component,
  1565. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1566. snd_soc_component_update_bits(wsa884x->component,
  1567. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1568. }
  1569. break;
  1570. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1571. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1572. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1573. break;
  1574. default:
  1575. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1576. __func__, event);
  1577. break;
  1578. }
  1579. return 0;
  1580. }
  1581. static int wsa884x_parse_port_params(struct device *dev, char *prop)
  1582. {
  1583. u32 *dt_array, map_size, max_uc;
  1584. int ret = 0;
  1585. u32 cnt = 0;
  1586. u32 i, j;
  1587. struct swr_port_params (*map)[SWR_UC_MAX][WSA884X_MAX_SWR_PORTS];
  1588. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  1589. struct wsa884x_priv *wsa884x = dev_get_drvdata(dev);
  1590. map = &wsa884x->wsa_port_params;
  1591. map_uc = &wsa884x->swr_wsa_port_params;
  1592. if (!of_find_property(dev->of_node, prop,
  1593. &map_size)) {
  1594. dev_err(dev, "missing port mapping prop %s\n", prop);
  1595. ret = -EINVAL;
  1596. goto err_port_map;
  1597. }
  1598. max_uc = map_size / (WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  1599. if (max_uc != SWR_UC_MAX) {
  1600. dev_err(dev, "%s: port params not provided for all usecases\n",
  1601. __func__);
  1602. ret = -EINVAL;
  1603. goto err_port_map;
  1604. }
  1605. dt_array = kzalloc(map_size, GFP_KERNEL);
  1606. if (!dt_array) {
  1607. ret = -ENOMEM;
  1608. goto err_port_map;
  1609. }
  1610. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  1611. WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * max_uc);
  1612. if (ret) {
  1613. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  1614. __func__, prop);
  1615. goto err_pdata_fail;
  1616. }
  1617. for (i = 0; i < max_uc; i++) {
  1618. for (j = 0; j < WSA884X_MAX_SWR_PORTS; j++) {
  1619. cnt = (i * WSA884X_MAX_SWR_PORTS + j) * SWR_PORT_PARAMS;
  1620. (*map)[i][j].offset1 = dt_array[cnt];
  1621. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  1622. }
  1623. (*map_uc)[i].pp = &(*map)[i][0];
  1624. }
  1625. kfree(dt_array);
  1626. return 0;
  1627. err_pdata_fail:
  1628. kfree(dt_array);
  1629. err_port_map:
  1630. return ret;
  1631. }
  1632. static int wsa884x_enable_supplies(struct device *dev,
  1633. struct wsa884x_priv *priv)
  1634. {
  1635. int ret = 0;
  1636. /* Parse power supplies */
  1637. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1638. &priv->num_supplies);
  1639. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1640. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1641. return -EINVAL;
  1642. }
  1643. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1644. priv->regulator, priv->num_supplies);
  1645. if (!priv->supplies) {
  1646. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1647. __func__);
  1648. return ret;
  1649. }
  1650. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1651. priv->regulator,
  1652. priv->num_supplies);
  1653. if (ret)
  1654. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1655. __func__);
  1656. return ret;
  1657. }
  1658. static struct snd_soc_dai_driver wsa_dai[] = {
  1659. {
  1660. .name = "",
  1661. .playback = {
  1662. .stream_name = "",
  1663. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1664. .formats = WSA884X_FORMATS,
  1665. .rate_max = 192000,
  1666. .rate_min = 8000,
  1667. .channels_min = 1,
  1668. .channels_max = 2,
  1669. },
  1670. },
  1671. };
  1672. static int wsa884x_swr_probe(struct swr_device *pdev)
  1673. {
  1674. int ret = 0;
  1675. struct wsa884x_priv *wsa884x;
  1676. u8 devnum = 0;
  1677. bool pin_state_current = false;
  1678. struct wsa_ctrl_platform_data *plat_data = NULL;
  1679. struct snd_soc_component *component;
  1680. u32 noise_gate_mode;
  1681. char buffer[MAX_NAME_LEN];
  1682. int dev_index = 0;
  1683. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1684. u8 wo0_val;
  1685. int sys_gain_size, sys_gain_length;
  1686. int wsa_dev_index;
  1687. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1688. GFP_KERNEL);
  1689. if (!wsa884x)
  1690. return -ENOMEM;
  1691. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1692. GFP_KERNEL);
  1693. if (!wsa884x_sub_regmap_irq_chip)
  1694. return -ENOMEM;
  1695. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1696. sizeof(struct regmap_irq_chip));
  1697. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1698. if (ret) {
  1699. ret = -EPROBE_DEFER;
  1700. goto err;
  1701. }
  1702. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1703. "qcom,spkr-sd-n-node", 0);
  1704. if (!wsa884x->wsa_rst_np) {
  1705. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1706. goto err_supply;
  1707. }
  1708. swr_set_dev_data(pdev, wsa884x);
  1709. wsa884x->swr_slave = pdev;
  1710. wsa884x->dev = &pdev->dev;
  1711. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1712. wsa884x_gpio_ctrl(wsa884x, true);
  1713. /*
  1714. * Add 5msec delay to provide sufficient time for
  1715. * soundwire auto enumeration of slave devices as
  1716. * per HW requirement.
  1717. */
  1718. usleep_range(5000, 5010);
  1719. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1720. if (ret) {
  1721. dev_dbg(&pdev->dev,
  1722. "%s get devnum %d for dev addr %lx failed\n",
  1723. __func__, devnum, pdev->addr);
  1724. ret = -EPROBE_DEFER;
  1725. goto err_supply;
  1726. }
  1727. pdev->dev_num = devnum;
  1728. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1729. &wsa884x_regmap_config);
  1730. if (IS_ERR(wsa884x->regmap)) {
  1731. ret = PTR_ERR(wsa884x->regmap);
  1732. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1733. __func__, ret);
  1734. goto dev_err;
  1735. }
  1736. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1737. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1738. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1739. wsa884x->irq_info.codec_name = "WSA884X";
  1740. wsa884x->irq_info.regmap = wsa884x->regmap;
  1741. wsa884x->irq_info.dev = &pdev->dev;
  1742. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1743. if (ret) {
  1744. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1745. __func__, ret);
  1746. goto dev_err;
  1747. }
  1748. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1749. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1750. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1751. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1752. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1753. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1754. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1755. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1756. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1757. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1758. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1759. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1760. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1761. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1762. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1763. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1764. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1765. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1766. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1767. /* Under Voltage Lock out (UVLO) interrupt handle */
  1768. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1769. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1770. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1771. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1772. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1773. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1774. if (!wsa884x->driver) {
  1775. ret = -ENOMEM;
  1776. goto err_irq;
  1777. }
  1778. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1779. sizeof(struct snd_soc_component_driver));
  1780. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1781. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1782. if (!wsa884x->dai_driver) {
  1783. ret = -ENOMEM;
  1784. goto err_mem;
  1785. }
  1786. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1787. /* Get last digit from HEX format */
  1788. dev_index = (int)((char)(pdev->addr & 0xF));
  1789. dev_index += 1;
  1790. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1791. dev_index += 2;
  1792. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1793. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1794. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1795. wsa884x->dai_driver->name =
  1796. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1797. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1798. wsa884x->dai_driver->playback.stream_name =
  1799. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1800. /* Number of DAI's used is 1 */
  1801. ret = snd_soc_register_component(&pdev->dev,
  1802. wsa884x->driver, wsa884x->dai_driver, 1);
  1803. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1804. if (!component) {
  1805. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1806. ret = -EINVAL;
  1807. goto err_mem;
  1808. }
  1809. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1810. "qcom,bolero-handle", 0);
  1811. if (!wsa884x->parent_np)
  1812. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1813. "qcom,lpass-cdc-handle", 0);
  1814. if (wsa884x->parent_np) {
  1815. wsa884x->parent_dev =
  1816. of_find_device_by_node(wsa884x->parent_np);
  1817. if (wsa884x->parent_dev) {
  1818. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1819. if (plat_data) {
  1820. wsa884x->parent_nblock.notifier_call =
  1821. wsa884x_event_notify;
  1822. if (plat_data->register_notifier)
  1823. plat_data->register_notifier(
  1824. plat_data->handle,
  1825. &wsa884x->parent_nblock,
  1826. true);
  1827. wsa884x->register_notifier =
  1828. plat_data->register_notifier;
  1829. wsa884x->handle = plat_data->handle;
  1830. } else {
  1831. dev_err(&pdev->dev, "%s: plat data not found\n",
  1832. __func__);
  1833. }
  1834. } else {
  1835. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1836. __func__);
  1837. }
  1838. } else {
  1839. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1840. }
  1841. /* Start in speaker mode by default */
  1842. wsa884x->dev_mode = SPEAKER;
  1843. wsa884x->dev_index = dev_index;
  1844. /* wsa_dev_index is macro_agnostic index */
  1845. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  1846. wsa884x->macro_np = of_parse_phandle(pdev->dev.of_node,
  1847. "qcom,wsa-macro-handle", 0);
  1848. if (wsa884x->macro_np) {
  1849. wsa884x->macro_dev =
  1850. of_find_device_by_node(wsa884x->macro_np);
  1851. if (wsa884x->macro_dev) {
  1852. ret = of_property_read_u32_index(
  1853. wsa884x->macro_dev->dev.of_node,
  1854. "qcom,wsa-rloads",
  1855. wsa_dev_index,
  1856. &wsa884x->rload);
  1857. if (ret) {
  1858. dev_err(&pdev->dev,
  1859. "%s: Failed to read wsa rloads\n",
  1860. __func__);
  1861. goto err_mem;
  1862. }
  1863. ret = of_property_read_u32_index(
  1864. wsa884x->macro_dev->dev.of_node,
  1865. "qcom,wsa-bat-cfgs",
  1866. wsa_dev_index,
  1867. &wsa884x->bat_cfg);
  1868. if (ret) {
  1869. dev_err(&pdev->dev,
  1870. "%s: Failed to read wsa bat cfgs\n",
  1871. __func__);
  1872. goto err_mem;
  1873. }
  1874. ret = of_property_read_u32(wsa884x->macro_dev->dev.of_node,
  1875. "qcom,noise-gate-mode", &noise_gate_mode);
  1876. if (ret) {
  1877. dev_info(&pdev->dev,
  1878. "%s: Failed to read wsa noise gate mode\n",
  1879. __func__);
  1880. wsa884x->noise_gate_mode = IDLE_DETECT;
  1881. } else {
  1882. if (IDLE_DETECT <= noise_gate_mode && noise_gate_mode <= NG3)
  1883. wsa884x->noise_gate_mode = noise_gate_mode;
  1884. else
  1885. wsa884x->noise_gate_mode = IDLE_DETECT;
  1886. }
  1887. if (!of_find_property(wsa884x->macro_dev->dev.of_node,
  1888. "qcom,wsa-system-gains", &sys_gain_size)) {
  1889. dev_err(&pdev->dev,
  1890. "%s: missing wsa-system-gains\n",
  1891. __func__);
  1892. goto err_mem;
  1893. }
  1894. sys_gain_length = sys_gain_size / (2 * sizeof(u32));
  1895. ret = of_property_read_u32_array(
  1896. wsa884x->macro_dev->dev.of_node,
  1897. "qcom,wsa-system-gains", wsa884x->sys_gains,
  1898. sys_gain_length);
  1899. if (ret) {
  1900. dev_err(&pdev->dev,
  1901. "%s: Failed to read wsa system gains\n",
  1902. __func__);
  1903. goto err_mem;
  1904. }
  1905. wsa884x->system_gain = wsa884x->sys_gains[
  1906. wsa884x->dev_mode + wsa_dev_index * 2];
  1907. } else {
  1908. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1909. __func__);
  1910. goto err_mem;
  1911. }
  1912. } else {
  1913. dev_err(&pdev->dev, "%s: parent node not found\n", __func__);
  1914. goto err_mem;
  1915. }
  1916. dev_dbg(component->dev,
  1917. "%s: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n", __func__,
  1918. wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1919. ret = wsa884x_validate_dt_configuration_params(component, wsa884x->rload,
  1920. wsa884x->bat_cfg, wsa884x->system_gain);
  1921. if (ret) {
  1922. dev_err(&pdev->dev,
  1923. "%s: invalid dt parameter: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n",
  1924. __func__, wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1925. ret = -EINVAL;
  1926. goto err_mem;
  1927. }
  1928. /* Assume that compander is enabled by default unless it is haptics sku */
  1929. if (wsa884x->variant == WSA8845H)
  1930. wsa884x->comp_enable = false;
  1931. else
  1932. wsa884x->comp_enable = true;
  1933. wsa884x_set_gain_parameters(component);
  1934. wsa884x_set_pbr_parameters(component);
  1935. /* Must write WO registers in a single write */
  1936. wo0_val = (0xC | (wsa884x->pa_aux_gain << 0x02) | !wsa884x->dev_mode);
  1937. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_0, wo0_val);
  1938. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_1, 0x0);
  1939. if (wsa884x->rload == WSA_4_OHMS || wsa884x->rload == WSA_6_OHMS)
  1940. snd_soc_component_update_bits(component,
  1941. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1942. if (wsa884x->dev_mode == SPEAKER) {
  1943. snd_soc_component_update_bits(component,
  1944. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1945. } else {
  1946. snd_soc_component_update_bits(component,
  1947. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1948. snd_soc_component_update_bits(component,
  1949. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1950. snd_soc_component_update_bits(component,
  1951. REG_FIELD_VALUE(PWM_CLK_CTL,
  1952. PWM_CLK_FREQ_SEL, 0x01));
  1953. }
  1954. if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
  1955. snd_soc_component_update_bits(component,
  1956. REG_FIELD_VALUE(TOP_CTRL1,
  1957. OCP_LOWVBAT_ITH_SEL_EN, 0x00));
  1958. ret = wsa884x_parse_port_params(&pdev->dev, "qcom,swr-wsa-port-params");
  1959. if (ret) {
  1960. dev_err(&pdev->dev, "Failed to read port params\n");
  1961. goto err;
  1962. }
  1963. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1964. wsa884x->swr_wsa_port_params);
  1965. mutex_init(&wsa884x->res_lock);
  1966. #ifdef CONFIG_DEBUG_FS
  1967. if (!wsa884x->debugfs_dent) {
  1968. wsa884x->debugfs_dent = debugfs_create_dir(
  1969. dev_name(&pdev->dev), 0);
  1970. if (!IS_ERR(wsa884x->debugfs_dent)) {
  1971. wsa884x->debugfs_peek =
  1972. debugfs_create_file("swrslave_peek",
  1973. S_IFREG | 0444,
  1974. wsa884x->debugfs_dent,
  1975. (void *) pdev,
  1976. &codec_debug_read_ops);
  1977. wsa884x->debugfs_poke =
  1978. debugfs_create_file("swrslave_poke",
  1979. S_IFREG | 0444,
  1980. wsa884x->debugfs_dent,
  1981. (void *) pdev,
  1982. &codec_debug_write_ops);
  1983. wsa884x->debugfs_reg_dump =
  1984. debugfs_create_file(
  1985. "swrslave_reg_dump",
  1986. S_IFREG | 0444,
  1987. wsa884x->debugfs_dent,
  1988. (void *) pdev,
  1989. &codec_debug_dump_ops);
  1990. }
  1991. }
  1992. #endif
  1993. return 0;
  1994. err_mem:
  1995. if (wsa884x->dai_driver) {
  1996. kfree(wsa884x->dai_driver->name);
  1997. kfree(wsa884x->dai_driver->playback.stream_name);
  1998. kfree(wsa884x->dai_driver);
  1999. }
  2000. if (wsa884x->driver) {
  2001. kfree(wsa884x->driver->name);
  2002. kfree(wsa884x->driver);
  2003. }
  2004. err_irq:
  2005. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  2006. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  2007. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  2008. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  2009. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  2010. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  2011. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  2012. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  2013. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  2014. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  2015. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  2016. dev_err:
  2017. if (pin_state_current == false)
  2018. wsa884x_gpio_ctrl(wsa884x, false);
  2019. swr_remove_device(pdev);
  2020. err_supply:
  2021. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2022. wsa884x->regulator,
  2023. wsa884x->num_supplies);
  2024. err:
  2025. swr_set_dev_data(pdev, NULL);
  2026. return ret;
  2027. }
  2028. static int wsa884x_swr_remove(struct swr_device *pdev)
  2029. {
  2030. struct wsa884x_priv *wsa884x;
  2031. wsa884x = swr_get_dev_data(pdev);
  2032. if (!wsa884x) {
  2033. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  2034. return -EINVAL;
  2035. }
  2036. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  2037. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  2038. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  2039. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  2040. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  2041. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  2042. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  2043. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  2044. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  2045. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  2046. if (wsa884x->register_notifier)
  2047. wsa884x->register_notifier(wsa884x->handle,
  2048. &wsa884x->parent_nblock, false);
  2049. #ifdef CONFIG_DEBUG_FS
  2050. debugfs_remove_recursive(wsa884x->debugfs_dent);
  2051. wsa884x->debugfs_dent = NULL;
  2052. #endif
  2053. mutex_destroy(&wsa884x->res_lock);
  2054. snd_soc_unregister_component(&pdev->dev);
  2055. if (wsa884x->dai_driver) {
  2056. kfree(wsa884x->dai_driver->name);
  2057. kfree(wsa884x->dai_driver->playback.stream_name);
  2058. kfree(wsa884x->dai_driver);
  2059. }
  2060. if (wsa884x->driver) {
  2061. kfree(wsa884x->driver->name);
  2062. kfree(wsa884x->driver);
  2063. }
  2064. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2065. wsa884x->regulator,
  2066. wsa884x->num_supplies);
  2067. swr_set_dev_data(pdev, NULL);
  2068. return 0;
  2069. }
  2070. #ifdef CONFIG_PM_SLEEP
  2071. static int wsa884x_swr_suspend(struct device *dev)
  2072. {
  2073. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2074. if (!wsa884x) {
  2075. dev_err_ratelimited(dev, "%s: wsa884x private data is NULL\n", __func__);
  2076. return -EINVAL;
  2077. }
  2078. dev_dbg(dev, "%s: system suspend\n", __func__);
  2079. if (wsa884x->dapm_bias_off ||
  2080. (snd_soc_component_get_bias_level(wsa884x->component) ==
  2081. SND_SOC_BIAS_OFF)) {
  2082. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2083. wsa884x->regulator,
  2084. wsa884x->num_supplies,
  2085. true);
  2086. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2087. }
  2088. return 0;
  2089. }
  2090. static int wsa884x_swr_resume(struct device *dev)
  2091. {
  2092. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2093. if (!wsa884x) {
  2094. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2095. return -EINVAL;
  2096. }
  2097. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  2098. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2099. wsa884x->regulator,
  2100. wsa884x->num_supplies,
  2101. false);
  2102. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2103. }
  2104. dev_dbg(dev, "%s: system resume\n", __func__);
  2105. return 0;
  2106. }
  2107. #endif /* CONFIG_PM_SLEEP */
  2108. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  2109. .suspend_late = wsa884x_swr_suspend,
  2110. .resume_early = wsa884x_swr_resume,
  2111. };
  2112. static const struct swr_device_id wsa884x_swr_id[] = {
  2113. {"wsa884x", 0},
  2114. {"wsa884x_2", 0},
  2115. {}
  2116. };
  2117. static const struct of_device_id wsa884x_swr_dt_match[] = {
  2118. {
  2119. .compatible = "qcom,wsa884x",
  2120. },
  2121. {
  2122. .compatible = "qcom,wsa884x_2",
  2123. },
  2124. {}
  2125. };
  2126. static struct swr_driver wsa884x_swr_driver = {
  2127. .driver = {
  2128. .name = "wsa884x",
  2129. .owner = THIS_MODULE,
  2130. .pm = &wsa884x_swr_pm_ops,
  2131. .of_match_table = wsa884x_swr_dt_match,
  2132. },
  2133. .probe = wsa884x_swr_probe,
  2134. .remove = wsa884x_swr_remove,
  2135. .id_table = wsa884x_swr_id,
  2136. };
  2137. static int __init wsa884x_swr_init(void)
  2138. {
  2139. return swr_driver_register(&wsa884x_swr_driver);
  2140. }
  2141. static void __exit wsa884x_swr_exit(void)
  2142. {
  2143. swr_driver_unregister(&wsa884x_swr_driver);
  2144. }
  2145. module_init(wsa884x_swr_init);
  2146. module_exit(wsa884x_swr_exit);
  2147. MODULE_DESCRIPTION("WSA884x codec driver");
  2148. MODULE_LICENSE("GPL v2");